More lm3s6918 -- clocking + misc fixes

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1768 42af7a65-404d-4744-a932-0658087f49c3

7 files changed, 447 insertions, 16 deletions

diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs
index 1d2fbdbdc..ded34b380 100644
--- a/nuttx/arch/arm/src/lm3s/Make.defs
+++ b/nuttx/arch/arm/src/lm3s/Make.defs
@@ -46,7 +46,7 @@ CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_undefinedinsn.c up_usestack.c
 
 CHIP_ASRCS	= 
-CHIP_CSRCS	= lm3s_start.c
+CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c
 
 ifdef CONFIG_NET
 CHIP_CSRCS	+= lm3s_ethernet.c
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
new file mode 100644
index 000000000..248588b09
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c
@@ -0,0 +1,313 @@
+/****************************************************************************
+ * arch/arm/src/lm3s/lm3s_syscontrol.c
+ * arch/arm/src/chip/lm3s_syscontrol.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+#define RCC_OSCMASK   (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC_XTALMASK  (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN)
+#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2)
+#define RCC_DIVMASK   (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS)
+#define RCC2_DIVMASK  (SYSCON_RCC2_SYSDIV2_MASK)
+#define FAST_OSCDELAY (512*1024)
+#define SLOW_OSCDELAY (4*1024)
+#define PLLLOCK_DELAY (32*1024)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_delay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_delay(uint32 delay)
+{
+  __asm__ __volatile__("1:\n"
+                       "\tsubs  %0, #1\n"
+                       "\tbne   1b\n"
+                       : "=r"(delay) : "r"(delay));
+}
+
+/****************************************************************************
+ * Name: lm3s_oscdelay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void lm3s_oscdelay(uint32 rcc, uint32 rcc2)
+{
+  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
+   * current clock rate is very slow.
+   */
+
+  uint32 delay   = FAST_OSCDELAY;
+
+  /* Are we currently using RCC2? */
+
+  if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
+    {
+      uint32 rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
+      if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) ||
+          (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ))
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* No.. using srce in RCC */
+
+  else
+    {
+      uint32 rccsrc  = rcc  & SYSCON_RCC_OSCSRC_MASK;
+      if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ)
+        {
+          delay = SLOW_OSCDELAY;
+        }
+    }
+
+  /* Then delay that number of loops */
+
+  lm3s_delay(delay);
+}
+
+/****************************************************************************
+ * Name: lm3s_plllock
+ *
+ * Description:
+ *   The new RCC values have been selected... wait for the PLL to lock on
+ *
+ ****************************************************************************/
+
+static inline void lm3s_plllock(void)
+{
+  uint32 delay;
+
+  /* Loop until the lock is achieved or until a timeout occurs */
+
+  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
+    {
+      /* Check if the PLL is locked on */
+
+      if (getreg32(LM3S_SYSCON_RIS) & SYSCON_IMC_PLLLIM)
+        {
+          /* Yes.. return now */
+
+          return;
+        }
+    }
+
+  /* If we get here, then PLL lock was not achieved */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lm3s_clockconfig
+ *
+ * Description:
+ *   Called to check to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void lm3s_clockconfig(uint32 newrcc, uint32 newrcc2)
+{
+  uint32 rcc;
+  uint32 rcc2;
+
+  /* Get the current values of the RCC and RCC2 registers */
+
+  rcc  = getreg32(LM3S_SYSCON_RCC);
+  rcc2 = getreg32(LM3S_SYSCON_RCC2);
+
+  /* Temporarily bypass the PLL and system clock dividers */
+
+  rcc |= SYSCON_RCC_BYPASS;
+  rcc &= ~(SYSCON_RCC_USESYSDIV);
+  putreg32(rcc, LM3S_SYSCON_RCC);
+
+  rcc2 |= SYSCON_RCC2_BYPASS2;
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* We are probably using the main oscillator.  The main oscillator is disabled on
+   * reset and so probably must be enabled here.  The internal oscillator is enabled
+   * on rest and if that is selected, most likely nothing needs to be done.
+   */
+
+  if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) ||
+      ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS)))
+    {
+      /* Enable any selected osciallators */
+
+      rcc &= (~RCC_OSCMASK|(newrcc & RCC_OSCMASK));
+      putreg32(rcc, LM3S_SYSCON_RCC);
+
+      /* Wait for the newly selected oscillator(s) to settle.  This is tricky because
+       * the time that we wait can be significant and is determined by the previous
+       * clock setting, not the one that we are configuring.
+       */
+
+      lm3s_oscdelay(rcc, rcc2);
+    }
+
+  /* Set the new crystal value, oscillator source and PLL configuration */
+
+  rcc  &= ~RCC_XTALMASK;
+  rcc  |= newrcc & RCC_XTALMASK;
+
+  rcc2 &= ~RCC2_XTALMASK;
+  rcc2 |= newrcc2 & RCC2_XTALMASK;
+
+  /* Clear the PLL lock interrupt */
+
+  putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
+
+  /* Write the new RCC/RCC2 values.  Order depends upon whether RCC2 or RCC
+   * is currently enabled.
+   */
+
+  if (rcc2 & SYSCON_RCC2_USERCC2)
+    {
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+      putreg32(rcc, LM3S_SYSCON_RCC);
+    }
+    else
+    {
+      putreg32(rcc, LM3S_SYSCON_RCC);
+      putreg32(rcc2, LM3S_SYSCON_RCC2);
+    }
+
+  /* Wait for the new crystal value and oscillator source to take effect */
+
+  lm3s_delay(16);
+
+  /* Set the requested system deivider and disable the non-selected osciallators */
+
+  rcc &= ~RCC_DIVMASK;
+  rcc |= newrcc & RCC_DIVMASK;
+
+  rcc2 &= ~RCC2_DIVMASK;
+  rcc2 |= newrcc2 & RCC2_DIVMASK;
+
+  /* Will the PLL output be used to clock the system? */
+
+  if ((newrcc & SYSCON_RCC_BYPASS) == 0)
+    {
+      /* Yes, wail untill the PLL is locked */
+
+      lm3s_plllock();
+
+      /* Then enable the PLL */
+
+      rcc  &= ~SYSCON_RCC_BYPASS;
+      rcc2 &= ~SYSCON_RCC2_BYPASS2;
+    }
+
+  /* Now we can set the final RCC/RCC2 values */
+
+  putreg32(rcc, LM3S_SYSCON_RCC);
+  putreg32(rcc2, LM3S_SYSCON_RCC2);
+
+  /* Wait for the system divider to be effective */
+
+  lm3s_delay(6);
+}
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void)
+{
+#ifdef CONFIG_LM3S_REVA2
+  /* Some early silicon returned an increase LDO voltage or 2.75V to work
+   * around a PLL bug
+   */
+
+  putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
+#endif
+
+  /* Set the clocking to run with the default settings provided in the board.h
+   * header file
+   */
+
+  lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
+}
+
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
index 569b5632b..0b6f811cb 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
@@ -121,7 +121,7 @@
 /* Device Identification 0 (DID0), offset 0x000 */
 
 #define SYSCON_DID0_MINOR_SHIFT       0         /* Bits 7-0: Minor Revision of the device */
-#define SYSCON_DID0_MINRO_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
+#define SYSCON_DID0_MINOR_MASK        (0xff << SYSCON_DID0_MINOR_SHIFT)
 #define SYSCON_DID0_MAJOR_SHIFT       8         /* Bits 15-8: Major Revision of the device */
 #define SYSCON_DID0_MAJOR_MASK        (0xff << SYSCON_DID0_MAJOR_SHIFT)
 #define SYSCON_DID0_CLASS_SHIFT       16        /* Bits 23-16: Device Class */
@@ -229,6 +229,17 @@
 
 #define SYSCON_LDOPCTL_VADJ_SHIFT     0         /* Bits 5-0: LDO Output Voltage */
 #define SYSCON_LDOPCTL_VADJ_MASK      (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT)
+#  define SYSCON_LPDOPCTL_2500MV      (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/
+#  define SYSCON_LPDOPCTL_2450MV      (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */
+#  define SYSCON_LPDOPCTL_2400MV      (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */
+#  define SYSCON_LPDOPCTL_2350MV      (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */
+#  define SYSCON_LPDOPCTL_2300MV      (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */
+#  define SYSCON_LPDOPCTL_2250MV      (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */
+#  define SYSCON_LPDOPCTL_2750MV      (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */
+#  define SYSCON_LPDOPCTL_2700MV      (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */
+#  define SYSCON_LPDOPCTL_2650MV      (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */
+#  define SYSCON_LPDOPCTL_2600MV      (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */
+#  define SYSCON_LPDOPCTL_2550MV      (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */
 
 /* Software Reset Control 0 (SRCR0), offset 0x040 */
 
@@ -293,13 +304,34 @@
 #define SYSCON_RCC_IOSCDIS            (1 << 1)  /* Bit 1: Internal Oscillator Disable */
 #define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
 #define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
+#  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC_OSCSRC_30KHZ     (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */
 #define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 9-6: Crystal Value */
 #define SYSCON_RCC_XTAL_MASK          (0x0f << SYSCON_RCC_XTAL_SHIFT)
+#  define SYSCON_RCC_XTAL1000KHZ      ( 0 << SYSCON_RCC_XTAL_SHIFT)  /* 1.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL1843KHZ      ( 1 << SYSCON_RCC_XTAL_SHIFT)  /* 1.8432MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2000KHZ      ( 2 << SYSCON_RCC_XTAL_SHIFT)  /* 2.0000MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL2580KHZ      ( 3 << SYSCON_RCC_XTAL_SHIFT)  /* 2.4576MHz (NO PLL) */
+#  define SYSCON_RCC_XTAL3580KHZ      ( 4 << SYSCON_RCC_XTAL_SHIFT)  /* 3.5795MHz */
+#  define SYSCON_RCC_XTAL3686KHZ      ( 5 << SYSCON_RCC_XTAL_SHIFT)  /* 3.6864MHz */
+#  define SYSCON_RCC_XTAL4000KHZ      ( 6 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0000MHz */
+#  define SYSCON_RCC_XTAL4096KHZ      ( 7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.0960MHz */
+#  define SYSCON_RCC_XTAL4915KHZ      ( 8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152MHz */
+#  define SYSCON_RCC_XTAL5000KHZ      ( 9 << SYSCON_RCC_XTAL_SHIFT)  /* 5.0000MHz */
+#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.1200MHz */
+#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6.0000MHz (reset value) */
+#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.1440MHz */
+#  define SYSCON_RCC_XTAL7373KHZ      (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728MHz */
+#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8.0000MHz */
+#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.1920MHz */
 #define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
 #define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
 #define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */
 #define SYSCON_RCC_SYSDIV_SHIFT       26        /* Bits 26-23: System Clock Divisor */
 #define SYSCON_RCC_SYSDIV_MASK        (0x0f << SYSCON_RCC_SYSDIV_SHIFT)
+#  define SYSCON_RCC_SYSDIV(n)        ((n-1) << SYSCON_RCC_SYSDIV_SHIFT)
 #define SYSCON_RCC_ACG                (1 << 27) /* Bit 27: Auto Clock Gating */
 
 /* XTAL to PLL Translation (PLLCFG), offset 0x064 */
@@ -313,10 +345,16 @@
 
 #define SYSCON_RCC2_OSCSRC2_SHIFT     4         /* Bits 6-4: Oscillator Source */
 #define SYSCON_RCC2_OSCSRC2_MASK      (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT)
+#  define SYSCON_RCC2_OSCSRC2_MOSC    (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */
+#  define SYSCON_RCC2_OSCSRC2_IOSC    (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */
+#  define SYSCON_RCC2_OSCSRC2_IOSC4   (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */
+#  define SYSCON_RCC2_OSCSRC2_30KHZ   (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */
+#  define SYSCON_RCC2_OSCSRC2_32KHZ   (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */
 #define SYSCON_RCC2_BYPASS2           (1 << 11) /* Bit 11: Bypass PLL */
 #define SYSCON_RCC2_PWRDN2            (1 << 13) /* Bit 13: Power-Down PLL */
 #define SYSCON_RCC2_SYSDIV2_SHIFT     23        /* Bits 28-23: System Clock Divisor */
 #define SYSCON_RCC2_SYSDIV2_MASK      (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT)
+#  define SYSCON_RCC2_SYSDIV(n)       ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT)
 #define SYSCON_RCC2_USERCC2           (1 << 31) /* Bit 31: Use RCC2 When set */
 
 /* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */
@@ -442,8 +480,47 @@
  * Public Data
  ************************************************************************************/
 
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
 
+/****************************************************************************
+ * Name: lm3s_clockconfig
+ *
+ * Description:
+ *   Called to check to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+EXTERN void lm3s_clockconfig(uint32 newrcc, uint32 newrcc2);
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the bootsequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+EXTERN void up_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H */
diff --git a/nuttx/configs/eagle100/include/board.h b/nuttx/configs/eagle100/include/board.h
index e08d7af83..ec5b32981 100644
--- a/nuttx/configs/eagle100/include/board.h
+++ b/nuttx/configs/eagle100/include/board.h
@@ -51,7 +51,43 @@
 
 /* Clocking *************************************************************************/
 
-#define LM3X_ARM_CLK_FREQ    50000000  /* 50MHz */
+/* RCC settings */
+
+#define SYSCON_RCC_XTAL      SYSCON_RCC_XTAL8000KHZ /* Eagle100 on-board crystall is 8.00 MHz */
+#define XTAL_FREQUENCY       8000000
+
+/* Oscillator source is the main oscillator (not internal, internal/4, 30KHz or
+ * 30KHz from hibernate module) */
+
+#define SYSCON_RCC_OSCSRC    SYSCON_RCC_OSCSRC_MOSC
+#define SYSCON_RCC2_OSCSRC   SYSCON_RCC2_OSCSRC2_MOSC
+#define OSCSRC_FREQUENCY     XTAL_FREQUENCY
+
+/* Use system divider = 4; this corresponds to a system clock frequency
+ * of (400 / 2) / 4 = 50MHz
+ */
+
+#define LM3S_SYSDIV          4
+#define SYSCLK_FREQUENCY     50000000  /* 50MHz */
+
+/* Other RCC settings:
+ *
+ * - Main and internal oscillators enabled.
+ * - PLL and sys dividers not bypassed
+ * - PLL not powered down
+ * - No auto-clock gating reset
+ */
+
+#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
+
+/* RCC2 settings -- RCC2 not used.  Other RCC2 settings
+ *
+ * - PLL and sys dividers not bypassed.
+ * - PLL not powered down
+ * - Not using RCC2
+ */
+
+#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
 
 /* LED definitions ******************************************************************/
 
diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig
index d686306bc..6abfc057d 100644
--- a/nuttx/configs/eagle100/ostest/defconfig
+++ b/nuttx/configs/eagle100/ostest/defconfig
@@ -180,7 +180,7 @@ CONFIG_HAVE_LIBM=n
 CONFIG_EXAMPLE=ostest
 CONFIG_DEBUG=n
 CONFIG_DEBUG_VERBOSE=n
-CONFIG_MM_REGIONS=2
+CONFIG_MM_REGIONS=1
 CONFIG_ARCH_LOWPUTC=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_INSTRUMENTATION=n
diff --git a/nuttx/configs/eagle100/ostest/ld.script b/nuttx/configs/eagle100/ostest/ld.script
index 4a2bd8cb1..050022f94 100644
--- a/nuttx/configs/eagle100/ostest/ld.script
+++ b/nuttx/configs/eagle100/ostest/ld.script
@@ -33,16 +33,23 @@
  *
  ****************************************************************************/
 
+/* The LM3S6918 has 256Kb of FLASH beginning at address 0x0000:0000. However,
+ * if the the Eagle100 Ethernet bootloader is used, then the entry point must
+ * be at the following offset in FLASH (and the size of the FLASH must be
+ * reduced to 248Kb):
+ */
+
+MEMORY
+{
+/*  flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K */
+    flash (rx) : ORIGIN = 0x00002000, LENGTH = 248K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	/* The LM3S6918 has 256Kb of FLASH beginning at address 0x0000:0000.
-	 * However, if the the tiny Eagle100 Ethernet bootloader is used, then
-	 * the entry point must be at the following offset:
-	 */
-
-	. = 0x00002000;
 	.text : {
 		_stext = ABSOLUTE(.);
 		*(.text)
@@ -53,27 +60,25 @@ SECTIONS
 		*(.glue_7t)
 		*(.got)			/* Global offset table		*/
 		_etext = ABSOLUTE(.);
-	}
+	} > flash
 
 	_eronly = ABSOLUTE(.);		/* See below                    */
-	. = ALIGN(4096);
 
 	/* The LM3S6918 has 64Kb of SRAM beginning at the following address */
 
-	. = 0x20000000;
 	.data : {
 		_sdata = ABSOLUTE(.);
 		*(.data)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	}
+	} > sram AT > flash
 
 	.bss : {			/* BSS				*/
 		_sbss = ABSOLUTE(.);
 		*(.bss)
 		*(COMMON)
 		_ebss = ABSOLUTE(.);
-	}
+	} > sram
 					/* Stabs debugging sections.	*/
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }
diff --git a/nuttx/configs/eagle100/src/up_leds.c b/nuttx/configs/eagle100/src/up_leds.c
index bf23b1eaa..300d63c0e 100644
--- a/nuttx/configs/eagle100/src/up_leds.c
+++ b/nuttx/configs/eagle100/src/up_leds.c
@@ -76,7 +76,7 @@ void up_ledinit(void)
 
   /* Configure Port E, Bit 1 as an output, initial value=OFF */
 
-  lm3s_configgpio(GPIO_DIR_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTE | 1);
+  lm3s_configgpio(GPIO_FUNC_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTE | 1);
 }
 
 /****************************************************************************