APB0 and APB1 must be in same MMU section

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2921 42af7a65-404d-4744-a932-0658087f49c3

14 files changed, 64 insertions, 63 deletions

diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h
index da7fe77fe..499093781 100644
--- a/nuttx/arch/arm/src/arm/pg_macros.h
+++ b/nuttx/arch/arm/src/arm/pg_macros.h
@@ -259,13 +259,17 @@
 #  define PG_L2_VECT_VADDR      CONFIG_PAGING_VECL2VADDR
 
 /* Case 2: Vectors are in low memory and the locked text region starts at
- * the begin of SRAM (which will be aliased to address 0x00000000)
+ * the beginning of SRAM (which will be aliased to address 0x00000000).
+ * However, the beginning of SRAM may not be aligned to the beginning
+ * of the L2 page table (because the beginning of RAM is offset into 
+ * the table.
  */
  
 #elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE)
 #  define PG_VECT_PBASE         PG_LOCKED_PBASE
-#  define PG_L2_VECT_PADDR      PGTABLE_L2_BASE_PADDR
-#  define PG_L2_VECT_VADDR      PGTABLE_L2_BASE_VADDR
+#  define PG_L2_VECT_OFFSET     (((PG_LOCKED_VBASE & 0x000fffff) >> PAGESHIFT) << 2)
+#  define PG_L2_VECT_PADDR      (PGTABLE_L2_BASE_PADDR + PG_L2_VECT_OFFSET)
+#  define PG_L2_VECT_VADDR      (PGTABLE_L2_BASE_VADDR + PG_L2_VECT_OFFSET)
 
 /* Case 3: High vectors or the locked region is not at the beginning or SRAM */
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_adc.h b/nuttx/arch/arm/src/lpc313x/lpc313x_adc.h
index f86013106..4cbbbee10 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_adc.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_adc.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
- * arch/arm/src/lpc313x/lpc313x_ADC.h
+ * arch/arm/src/lpc313x/lpc313x_adc.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* ADC register base address offset into the APB0 domain ****************************************/
 
-#define LPC313X_ADC_VBASE                (LPC313X_APB0_VSECTION+LPC313X_APB0_ADC_OFFSET)
-#define LPC313X_ADC_PBASE                (LPC313X_APB0_PSECTION+LPC313X_APB0_ADC_OFFSET)
+#define LPC313X_ADC_VBASE                (LPC313X_APB0_VADDR+LPC313X_APB0_ADC_OFFSET)
+#define LPC313X_ADC_PBASE                (LPC313X_APB0_PADDR+LPC313X_APB0_ADC_OFFSET)
 
 /* ADC register offsets (with respect to the ADC base) ******************************************/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c b/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c
index cd3de31ae..8840c6fdb 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c
@@ -100,10 +100,8 @@ static const struct section_mapping_s section_mapping[] =
   { LPC313X_INTSROM0_PSECTION, LPC313X_INTSROM0_VSECTION, 
     LPC313X_INTSROM_MMUFLAGS, LPC313X_INTSROM0_NSECTIONS},
 #endif
-  { LPC313X_APB0_PSECTION, LPC313X_APB0_VSECTION, 
-    LPC313X_APB0_MMUFLAGS, LPC313X_APB0_NSECTIONS},
-  { LPC313X_APB1_PSECTION, LPC313X_APB1_VSECTION, 
-    LPC313X_APB1_MMUFLAGS, LPC313X_APB1_NSECTIONS},
+  { LPC313X_APB01_PSECTION, LPC313X_APB01_VSECTION, 
+    LPC313X_APB01_MMUFLAGS, LPC313X_APB01_NSECTIONS},
   { LPC313X_APB2_PSECTION, LPC313X_APB2_VSECTION, 
     LPC313X_APB2_MMUFLAGS, LPC313X_APB2_NSECTIONS},
   { LPC313X_APB3_PSECTION, LPC313X_APB3_VSECTION, 
@@ -210,17 +208,14 @@ static void up_setupmappings(void)
 #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
 static void  up_vectorpermissions(uint32_t mmuflags)
 {
-  /* The PTE for virtual address zero is at the base of the L2 page table */
+  /* The PTE for the beginning of ISRAM is at the base of the L2 page table */
 
-  uint32_t *ptr = (uint32_t*)PGTABLE_BASE_VADDR;
+  uint32_t *ptr = (uint32_t*)PG_L2_VECT_VADDR;
   uint32_t pte;
 
-  /* This is easily because we have already been told everything! */
+  /* The pte might be zero the first time this function is called. */
 
   pte = *ptr;
-
-  /* The pte might be zero the first time this function is called . */
-
   if (pte == 0)
     {
       pte = PG_VECT_PBASE;   
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
index 18f756572..961258e39 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
@@ -59,14 +59,14 @@
 
 /* Virtual and physical base address of the CGU block and CSB and CFG register groups */
 
-#define LPC313X_CGU_VBASE                (LPC313X_APB0_VSECTION+LPC313X_APB0_CGU_OFFSET)
-#define LPC313X_CGU_PBASE                (LPC313X_APB0_PSECTION+LPC313X_APB0_CGU_OFFSET)
+#define LPC313X_CGU_VBASE                (LPC313X_APB0_VADDR+LPC313X_APB0_CGU_OFFSET)
+#define LPC313X_CGU_PBASE                (LPC313X_APB0_PADDR+LPC313X_APB0_CGU_OFFSET)
 
-#define LPC313X_CGU_CSB_VBASE            (LPC313X_APB0_VSECTION+LPC313X_APB0_GCU_CSB_OFFSET)
-#define LPC313X_CGU_CSB_PBASE            (LPC313X_APB0_PSECTION+LPC313X_APB0_GCU_CSB_OFFSET)
+#define LPC313X_CGU_CSB_VBASE            (LPC313X_APB0_VADDR+LPC313X_APB0_GCU_CSB_OFFSET)
+#define LPC313X_CGU_CSB_PBASE            (LPC313X_APB0_PADDR+LPC313X_APB0_GCU_CSB_OFFSET)
 
-#define LPC313X_CGU_CFG_VBASE            (LPC313X_APB0_VSECTION+LPC313X_APB0_GCU_CFG_OFFSET)
-#define LPC313X_CGU_CFG_PBASE            (LPC313X_APB0_PSECTION+LPC313X_APB0_GCU_CFG_OFFSET)
+#define LPC313X_CGU_CFG_VBASE            (LPC313X_APB0_VADDR+LPC313X_APB0_GCU_CFG_OFFSET)
+#define LPC313X_CGU_CFG_PBASE            (LPC313X_APB0_PADDR+LPC313X_APB0_GCU_CFG_OFFSET)
 
 /* CGU register offsets *************************************************************************/
 /* CGU clock switchbox register offsets (with respect to the CGU CSB register base) *************/
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_evntrtr.h b/nuttx/arch/arm/src/lpc313x/lpc313x_evntrtr.h
index 95e6522df..bf2162dbc 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_evntrtr.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_evntrtr.h
@@ -49,8 +49,8 @@
 
 /* EVNTRTR register base address offset into the APB0 domain ********************************************/
 
-#define LPC313X_EVNTRTR_VBASE                      (LPC313X_APB0_VSECTION+LPC313X_APB0_EVNTRTR_OFFSET)
-#define LPC313X_EVNTRTR_PBASE                      (LPC313X_APB0_PSECTION+LPC313X_APB0_EVNTRTR_OFFSET)
+#define LPC313X_EVNTRTR_VBASE                      (LPC313X_APB0_VADDR+LPC313X_APB0_EVNTRTR_OFFSET)
+#define LPC313X_EVNTRTR_PBASE                      (LPC313X_APB0_PADDR+LPC313X_APB0_EVNTRTR_OFFSET)
 
 /* Sizes of things */
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_i2c.h b/nuttx/arch/arm/src/lpc313x/lpc313x_i2c.h
index 64044f948..81b9608df 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_i2c.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_i2c.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_i2c.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,11 +49,11 @@
 
 /* I2C register base address offset into the APB1 domain ****************************************/
 
-#define LPC313X_I2C0_VBASE               (LPC313X_APB1_VSECTION+LPC313X_APB1_I2C0_OFFSET)
-#define LPC313X_I2C0_PBASE               (LPC313X_APB1_PSECTION+LPC313X_APB1_I2C0_OFFSET)
+#define LPC313X_I2C0_VBASE               (LPC313X_APB1_VADDR+LPC313X_APB1_I2C0_OFFSET)
+#define LPC313X_I2C0_PBASE               (LPC313X_APB1_PADDR+LPC313X_APB1_I2C0_OFFSET)
 
-#define LPC313X_I2C1_VBASE               (LPC313X_APB1_VSECTION+LPC313X_APB1_I2C1_OFFSET)
-#define LPC313X_I2C1_PBASE               (LPC313X_APB1_PSECTION+LPC313X_APB1_I2C1_OFFSET)
+#define LPC313X_I2C1_VBASE               (LPC313X_APB1_VADDR+LPC313X_APB1_I2C1_OFFSET)
+#define LPC313X_I2C1_PBASE               (LPC313X_APB1_PADDR+LPC313X_APB1_I2C1_OFFSET)
 
 /* I2C register offsets (with respect to the I2C base) ******************************************/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_ioconfig.h b/nuttx/arch/arm/src/lpc313x/lpc313x_ioconfig.h
index 58752978d..739ac5ab1 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_ioconfig.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_ioconfig.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_ioconfig.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* IOCONFIG register base address offset into the APB0 domain ***********************************/
 
-#define LPC313X_IOCONFIG_VBASE                (LPC313X_APB0_VSECTION+LPC313X_APB0_IOCONFIG_OFFSET)
-#define LPC313X_IOCONFIG_PBASE                (LPC313X_APB0_PSECTION+LPC313X_APB0_IOCONFIG_OFFSET)
+#define LPC313X_IOCONFIG_VBASE                (LPC313X_APB0_VADDR+LPC313X_APB0_IOCONFIG_OFFSET)
+#define LPC313X_IOCONFIG_PBASE                (LPC313X_APB0_PADDR+LPC313X_APB0_IOCONFIG_OFFSET)
 
 /* IOCONFIG function block offsets (with respect to the IOCONFIG register base address) *********/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
index 5812a20e9..ad2281237 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
@@ -57,8 +57,9 @@
                                                   /* 0x11058000-11ffffffff: Reserved */
 #define LPC313X_INTSROM0_PSECTION      0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
                                                   /* 0x12020000-0x12ffffff: Reserved */
-#define LPC313X_APB0_PSECTION          0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
-#define LPC313X_APB1_PSECTION          0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
+#define LPC313X_APB01_PSECTION         0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB1 16Kb */
+#  define LPC313X_APB0_PADDR           0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
+#  define LPC313X_APB1_PADDR           0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
                                                   /* 0x1300c000-0x14ffffff: Reserved */
 #define LPC313X_APB2_PSECTION          0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
 #define LPC313X_APB3_PSECTION          0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
@@ -160,7 +161,7 @@
 
 #define LPC313X_SHADOWSPACE_NSECTIONS  1 /*         4Kb - <1 section  */
 #define LPC313X_INTSRAM_NSECTIONS      1 /* 96 or 192Kb - <1 section */
-#define LPC313X_APB0_NSECTIONS         1 /*        32Kb - <1 section */
+#define LPC313X_APB01_NSECTIONS        1 /*        32Kb - <1 section */
 #define LPC313X_INTSROM0_NSECTIONS     1 /*       128Kb - <1 section */
 #define LPC313X_APB1_NSECTIONS         1 /*        16Kb - <1 section */
 #define LPC313X_APB2_NSECTIONS         1 /*        16Kb - <1 section */
@@ -185,8 +186,7 @@
 #define LPC313X_SHADOWSPACE_MMUFLAGS   MMU_MEMFLAGS
 #define LPC313X_INTSRAM_MMUFLAGS       MMU_MEMFLAGS
 #define LPC313X_INTSROM_MMUFLAGS       MMU_MEMFLAGS
-#define LPC313X_APB0_MMUFLAGS          MMU_IOFLAGS
-#define LPC313X_APB1_MMUFLAGS          MMU_IOFLAGS
+#define LPC313X_APB01_MMUFLAGS         MMU_IOFLAGS
 #define LPC313X_APB2_MMUFLAGS          MMU_IOFLAGS
 #define LPC313X_APB3_MMUFLAGS          MMU_IOFLAGS
 #define LPC313X_APB4MPMC_MMUFLAGS      MMU_IOFLAGS
@@ -217,8 +217,9 @@
 #    define LPC313X_INTSRAM0_VADDR     0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
 #    define LPC313X_INTSRAM1_VADDR     0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
 #  define LPC313X_INTSROM0_VSECTION    0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
-#  define LPC313X_APB0_VSECTION        0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
-#  define LPC313X_APB1_VSECTION        0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
+#  define LPC313X_APB01_VSECTION       0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB0 32Kb */
+#    define LPC313X_APB0_VADDR         0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
+#    define LPC313X_APB1_VADDR         0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
 #  define LPC313X_APB2_VSECTION        0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
 #  define LPC313X_APB3_VSECTION        0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
 #  define LPC313X_APB4MPMC_VSECTION    0x17000000 /*                        8Kb */
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_pwm.h b/nuttx/arch/arm/src/lpc313x/lpc313x_pwm.h
index 778b468b7..45065546c 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_pwm.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_pwm.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_pwm.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* PWM register base address offset into the APB1 domain ****************************************/
 
-#define LPC313X_PWM_VBASE                (LPC313X_APB1_VSECTION+LPC313X_APB1_PWM_OFFSET)
-#define LPC313X_PWM_PBASE                (LPC313X_APB1_PSECTION+LPC313X_APB1_PWM_OFFSET)
+#define LPC313X_PWM_VBASE                (LPC313X_APB1_VADDR+LPC313X_APB1_PWM_OFFSET)
+#define LPC313X_PWM_PBASE                (LPC313X_APB1_PADDR+LPC313X_APB1_PWM_OFFSET)
 
 /* PWM register offsets (with respect to the PWM base) ******************************************/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_rng.h b/nuttx/arch/arm/src/lpc313x/lpc313x_rng.h
index 985d4f81a..dc65d71c2 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_rng.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_rng.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_rng.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* RNG register base address offset into the APB0 domain ****************************************/
 
-#define LPC313X_RNG_VBASE                (LPC313X_APB0_VSECTION+LPC313X_APB0_RNG_OFFSET)
-#define LPC313X_RNG_PBASE                (LPC313X_APB0_PSECTION+LPC313X_APB0_RNG_OFFSET)
+#define LPC313X_RNG_VBASE                (LPC313X_APB0_VADDR+LPC313X_APB0_RNG_OFFSET)
+#define LPC313X_RNG_PBASE                (LPC313X_APB0_PADDR+LPC313X_APB0_RNG_OFFSET)
 
 /* RNG register offsets (with respect to the RNG base) ******************************************/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
index ffd2899d2..6467484d5 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
@@ -1,7 +1,7 @@
 /********************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_syscreg.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* SYSCREG register base address offset into the APB0 domain ********************************************/
 
-#define LPC313X_SYSCREG_VBASE                    (LPC313X_APB0_VSECTION+LPC313X_APB0_SYSCREG_OFFSET)
-#define LPC313X_SYSCREG_PBASE                    (LPC313X_APB0_PSECTION+LPC313X_APB0_SYSCREG_OFFSET)
+#define LPC313X_SYSCREG_VBASE                    (LPC313X_APB0_VADDR+LPC313X_APB0_SYSCREG_OFFSET)
+#define LPC313X_SYSCREG_PBASE                    (LPC313X_APB0_PADDR+LPC313X_APB0_SYSCREG_OFFSET)
 
 /* SYSCREG register offsets (with respect to the SYSCREG base) ******************************************/
 /* Miscellaneous system configuration registers, part1 */
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_timer.h b/nuttx/arch/arm/src/lpc313x/lpc313x_timer.h
index b18a21dc9..528ea4f06 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_timer.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_timer.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_timer.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,17 +49,17 @@
 
 /* TIMER register base address offset into the APB1 domain **************************************/
 
-#define LPC313X_TIMER0_VBASE             (LPC313X_APB1_VSECTION+LPC313X_APB1_TIMER0_OFFSET)
-#define LPC313X_TIMER0_PBASE             (LPC313X_APB1_PSECTION+LPC313X_APB1_TIMER0_OFFSET)
+#define LPC313X_TIMER0_VBASE             (LPC313X_APB1_VADDR+LPC313X_APB1_TIMER0_OFFSET)
+#define LPC313X_TIMER0_PBASE             (LPC313X_APB1_PADDR+LPC313X_APB1_TIMER0_OFFSET)
 
-#define LPC313X_TIMER1_VBASE             (LPC313X_APB1_VSECTION+LPC313X_APB1_TIMER1_OFFSET)
-#define LPC313X_TIMER1_PBASE             (LPC313X_APB1_PSECTION+LPC313X_APB1_TIMER1_OFFSET)
+#define LPC313X_TIMER1_VBASE             (LPC313X_APB1_VADDR+LPC313X_APB1_TIMER1_OFFSET)
+#define LPC313X_TIMER1_PBASE             (LPC313X_APB1_PADDR+LPC313X_APB1_TIMER1_OFFSET)
 
-#define LPC313X_TIMER2_VBASE             (LPC313X_APB1_VSECTION+LPC313X_APB1_TIMER2_OFFSET)
-#define LPC313X_TIMER2_PBASE             (LPC313X_APB1_PSECTION+LPC313X_APB1_TIMER2_OFFSET)
+#define LPC313X_TIMER2_VBASE             (LPC313X_APB1_VADDR+LPC313X_APB1_TIMER2_OFFSET)
+#define LPC313X_TIMER2_PBASE             (LPC313X_APB1_PADDR+LPC313X_APB1_TIMER2_OFFSET)
 
-#define LPC313X_TIMER3_VBASE             (LPC313X_APB1_VSECTION+LPC313X_APB1_TIMER3_OFFSET)
-#define LPC313X_TIMER3_PBASE             (LPC313X_APB1_PSECTION+LPC313X_APB1_TIMER3_OFFSET)
+#define LPC313X_TIMER3_VBASE             (LPC313X_APB1_VADDR+LPC313X_APB1_TIMER3_OFFSET)
+#define LPC313X_TIMER3_PBASE             (LPC313X_APB1_PADDR+LPC313X_APB1_TIMER3_OFFSET)
 
 /* TIMER register offsets (with respect to the TIMERn base) *************************************/
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_wdt.h b/nuttx/arch/arm/src/lpc313x/lpc313x_wdt.h
index fd6e0f4e0..f3652bd73 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_wdt.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_wdt.h
@@ -1,7 +1,7 @@
 /************************************************************************************************
  * arch/arm/src/lpc313x/lpc313x_wdt.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,8 @@
 
 /* WDT register base address offset into the APB0 domain ****************************************/
 
-#define LPC313X_WDT_VBASE                (LPC313X_APB0_VSECTION+LPC313X_APB0_WDT_OFFSET)
-#define LPC313X_WDT_PBASE                (LPC313X_APB0_PSECTION+LPC313X_APB0_WDT_OFFSET)
+#define LPC313X_WDT_VBASE                (LPC313X_APB0_VADDR+LPC313X_APB0_WDT_OFFSET)
+#define LPC313X_WDT_PBASE                (LPC313X_APB0_PADDR+LPC313X_APB0_WDT_OFFSET)
 
 /* WDT register offsets (with respect to the WDT base) ******************************************/
 
diff --git a/nuttx/configs/ea3131/include/board_memorymap.h b/nuttx/configs/ea3131/include/board_memorymap.h
index eb867e603..576228aad 100755
--- a/nuttx/configs/ea3131/include/board_memorymap.h
+++ b/nuttx/configs/ea3131/include/board_memorymap.h
@@ -67,8 +67,9 @@
 #    define LPC313X_INTSRAM0_VADDR     0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
 #    define LPC313X_INTSRAM1_VADDR     0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
 #  define LPC313X_INTSROM0_VSECTION    0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
-#  define LPC313X_APB0_VSECTION        0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
-#  define LPC313X_APB1_VSECTION        0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
+#  define LPC313X_APB01_VSECTION       0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb  APB1 16Kb*/
+#    define LPC313X_APB0_VADDR         0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
+#    define LPC313X_APB1_VADDR         0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
 #  define LPC313X_APB2_VSECTION        0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
 #  define LPC313X_APB3_VSECTION        0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
 #  define LPC313X_APB4MPMC_VSECTION    0x17000000 /*                        8Kb */