Shenzhou schematic is wrong: LCD WR signal is on PB14, not PD14

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5195 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 27 insertions, 11 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 906b63d33..80d889b3b 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3415,4 +3415,6 @@
 	  configuration.
 	* configs/shenzhou:  Oops.  The Shenzhou LCD is and SSD1289,
 	  not an ILI93xx.
+	* configs/shenzhou/src/up_ssd1289.c: The LCD is basically functional
+	  on the Shenzhou board.
 
diff --git a/nuttx/Kconfig b/nuttx/Kconfig
index 7ac512607..f4f6abe7e 100644
--- a/nuttx/Kconfig
+++ b/nuttx/Kconfig
@@ -238,6 +238,8 @@ config DEBUG_ENABLE
 	---help---
 		Support an interface to dynamically enable or disable debug output.
 
+comment "Subsystem Debug Options"
+
 config DEBUG_SCHED
 	bool "Enable Scheduler Debug Output"
 	default n
@@ -288,6 +290,8 @@ config DEBUG_GRAPHICS
 	---help---
 		Enable NX graphics debug output (disabled by default)
 
+comment "Driver Debug Options"
+
 config DEBUG_LCD
 	bool "Enable Low-level LCD Debug Output"
 	default n
diff --git a/nuttx/configs/shenzhou/README.txt b/nuttx/configs/shenzhou/README.txt
index b083f293e..833da5bd1 100644
--- a/nuttx/configs/shenzhou/README.txt
+++ b/nuttx/configs/shenzhou/README.txt
@@ -94,7 +94,7 @@ PN NAME SIGNAL         NOTES
         MII_TXD0       Ethernet PHY
 52 PB13 I2S_CK         Audio DAC
         MII_TXD1       Ethernet PHY
-53 PB14 SD_CD
+53 PB14 SD_CD          There is confusion here.  Schematic is wrong LCD_WR is PB14.
 54 PB15 I2S_DIN        Audio DAC
 
 -- ---- -------------- -------------------------------------------------------------------
@@ -139,7 +139,7 @@ PN NAME SIGNAL         NOTES
 58 PD11 SD_CS          Active low: Pulled high (See also TFT LCD CN13, pin 32)
 59 PD12 WIRELESS_CS    To the NRF24L01 2.4G wireless module
 60 PD13 LCD_RS         To TFT LCD (CN13)
-61 PD14 LCD_WR         To TFT LCD (CN13)
+61 PD14 LCD_WR         To TFT LCD (CN13). Schematic is wrong LCD_WR is PB14.
 62 PD15 LCD_RD         To TFT LCD (CN13)
 
 -- ---- -------------- -------------------------------------------------------------------
diff --git a/nuttx/configs/shenzhou/src/shenzhou-internal.h b/nuttx/configs/shenzhou/src/shenzhou-internal.h
index 51ab10553..f9cebc5e3 100644
--- a/nuttx/configs/shenzhou/src/shenzhou-internal.h
+++ b/nuttx/configs/shenzhou/src/shenzhou-internal.h
@@ -164,7 +164,7 @@
  * 80 PC12 SPI3_MOSI      To TFT LCD (CN13, pin 27)
  * 58 PD11 SD_CS          Active low: Pulled high (See also TFT LCD CN13, pin 32)
  * 60 PD13 LCD_RS         To TFT LCD (CN13, pin 20)
- * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21)
+ * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
  * 62 PD15 LCD_RD         To TFT LCD (CN13, pin 22)
  * 97 PE0  DB00           To TFT LCD (CN13, pin 3)
  * 98 PE1  DB01           To TFT LCD (CN13, pin 4)
@@ -281,7 +281,7 @@
 #define GPIO_LCD_RD     (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
                          GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN15)
 #define GPIO_LCD_WR     (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
-                         GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN14)
+                         GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN14)
 #define GPIO_LCD_LE     (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
                          GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN2)
 
@@ -307,9 +307,9 @@
 #define LCD_RD_CLEAR    LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 15) /* GPIO_PORTD|GPIO_PIN15 */
 #define LCD_RD_SET      LCD_BIT_SET(STM32_GPIOD_OFFSET, 15)
 #define LCD_RD_READ     LCD_BIT_READ(STM32_GPIOD_OFFSET, 15)
-#define LCD_WR_CLEAR    LCD_BIT_CLEAR(STM32_GPIOD_OFFSET, 14) /* GPIO_PORTD|GPIO_PIN14 */
-#define LCD_WR_SET      LCD_BIT_SET(STM32_GPIOD_OFFSET, 14)
-#define LCD_WR_READ     LCD_BIT_READ(STM32_GPIOD_OFFSET, 14)
+#define LCD_WR_CLEAR    LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 14) /* GPIO_PORTB|GPIO_PIN14 */
+#define LCD_WR_SET      LCD_BIT_SET(STM32_GPIOB_OFFSET, 14)
+#define LCD_WR_READ     LCD_BIT_READ(STM32_GPIOB_OFFSET, 14)
 #define LCD_LE_CLEAR    LCD_BIT_CLEAR(STM32_GPIOB_OFFSET, 2)  /* GPIO_PORTB|GPIO_PIN2 */
 #define LCD_LE_SET      LCD_BIT_SET(STM32_GPIOB_OFFSET, 2)
 #define LCD_LE_READ     LCD_BIT_READ(STM32_GPIOB_OFFSET, 2)
@@ -383,7 +383,7 @@
  * -- ---- -------------- -------------------------------------------------------------------
  * PN NAME SIGNAL         NOTES
  * -- ---- -------------- -------------------------------------------------------------------
- * 53 PB14 SD_CD          Active low: Pulled high
+ * 53 PB14 SD_CD          Active low: Pulled high. Schematic is wrong LCD_WR is PB14.
  * 58 PD11 SD_CS          Active low: Pulled high (See also TFT LCD CN13, pin 32)
  */
 
diff --git a/nuttx/configs/shenzhou/src/up_ili93xx.c b/nuttx/configs/shenzhou/src/up_ili93xx.c
index ef2cee417..d3e2291da 100644
--- a/nuttx/configs/shenzhou/src/up_ili93xx.c
+++ b/nuttx/configs/shenzhou/src/up_ili93xx.c
@@ -49,7 +49,7 @@
  * 80 PC12 SPI3_MOSI      To TFT LCD (CN13, pin 27)
  * 58 PD11 SD_CS          Active low: Pulled high (See also TFT LCD CN13, pin 32)
  * 60 PD13 LCD_RS         To TFT LCD (CN13, pin 20)
- * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21)
+ * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
  * 62 PD15 LCD_RD         To TFT LCD (CN13, pin 22)
  * 97 PE0  DB00           To TFT LCD (CN13, pin 3)
  * 98 PE1  DB01           To TFT LCD (CN13, pin 4)
diff --git a/nuttx/configs/shenzhou/src/up_ssd1289.c b/nuttx/configs/shenzhou/src/up_ssd1289.c
index cf02b36d1..00e0ac0dd 100644
--- a/nuttx/configs/shenzhou/src/up_ssd1289.c
+++ b/nuttx/configs/shenzhou/src/up_ssd1289.c
@@ -160,7 +160,7 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv);
  * 80 PC12 SPI3_MOSI      To TFT LCD (CN13, pin 27)
  * 58 PD11 SD_CS          Active low: Pulled high (See also TFT LCD CN13, pin 32)
  * 60 PD13 LCD_RS         To TFT LCD (CN13, pin 20)
- * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21)
+ * 61 PD14 LCD_WR         To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14.
  * 62 PD15 LCD_RD         To TFT LCD (CN13, pin 22)
  * 97 PE0  DB00           To TFT LCD (CN13, pin 3)
  * 98 PE1  DB01           To TFT LCD (CN13, pin 4)
@@ -312,6 +312,9 @@ static void stm32_wrdata(FAR struct stm32_lower_s *priv, uint16_t data)
 
   putreg32(1, LCD_WR_CLEAR);
   putreg32((uint32_t)data, LCD_ODR);
+
+  /* Total WR pulse with should be 50ns wide. */
+
   putreg32(1, LCD_WR_SET);
 }
 
@@ -326,6 +329,8 @@ static void stm32_wrdata(FAR struct stm32_lower_s *priv, uint16_t data)
 #ifndef CONFIG_SSD1289_WRONLY
 static inline uint16_t stm32_rddata(FAR struct stm32_lower_s *priv)
 {
+  uint16_t regval;
+
   /* Make sure D0-D15 are configured as inputs */
 
   stm32_lcdinput(priv);
@@ -333,8 +338,13 @@ static inline uint16_t stm32_rddata(FAR struct stm32_lower_s *priv)
   /* Toggle the RD line to latch the 16-bit LCD data */
 
   putreg32(1, LCD_RD_CLEAR);
+
+  /* Data should appear 250ns after RD.  Total RD pulse width should be 500nS */
+
+  __asm__ __volatile__(" nop\n nop\n nop\n nop\n");
+  regval = (uint16_t)getreg32(LCD_IDR);
   putreg32(1, LCD_RD_SET);
-  return (uint16_t)getreg32(LCD_IDR);
+  return regval;
 }
 #endif