SAM4L GPIO port addressing fixes; SAM4L Xplained LED support; minor documentation updates

5 files changed, 430 insertions, 125 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index fcde5f0c2..88f3b26d1 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -4896,4 +4896,10 @@
 	  file to sam3u_gpio.h (2013-6-4).
 	* nuttx/arch/arm/src/sam34/sam4l_gpio.c: Created GPIO driver for
 	  the SAM4L (2013-6-4).
-
+	* nuttx/configs/sam4l-xplained/src/sam_userleds.c:  Added.
+	  (2013-6-4).
+	* configs/sam4l-xplained/src/sam_userleds.c:  Add application
+	  LED interfaces (2013-6-5).
+	* arch/arm/src/sam34/sam4l_gpio.c and arch/arm/src/sam34/chip/sam4l_gpio.h:
+	  Fix GPIO port address; fix compilation errors (2013-6-5).
+ 
diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html
index 5d8f48767..36428215d 100644
--- a/nuttx/Documentation/NuttxUserGuide.html
+++ b/nuttx/Documentation/NuttxUserGuide.html
@@ -13,7 +13,7 @@
       <h1><big><font color="#3c34ec"><i>NuttX Operating System<p>User's Manual</i></font></big></h1>
       <p><small>by</small></p>
       <p>Gregory Nutt<p>
-      <p>Last Updated: Aprill 22, 2013</p>
+      <p>Last Updated: June 4, 2013</p>
     </td>
   </tr>
 </table>
@@ -8124,15 +8124,16 @@ int     getopt(int argc, FAR char *const argv[], FAR const char *optstring);
 <ul><pre>
 #include &lt;stdio.h&gt;
 
+void   clearerr(register FILE *stream);
 int    fclose(FILE *stream);
 int    fflush(FILE *stream);
-FILE  *fdopen(int fd, const char *type);
-int    feof(FILE *stream);                               /* Prototyped but not implemented */
-int    ferror(FILE *stream);                             /* Prototyped but not implemented */
+int    feof(FILE *stream);
+int    ferror(FILE *stream);
 int    fileno(FAR FILE *stream);
 int    fgetc(FILE *stream);
 int    fgetpos(FILE *stream, fpos_t *pos);
 char  *fgets(char *s, int n, FILE *stream);
+FILE  *fdopen(int fd, const char *type);
 FILE  *fopen(const char *path, const char *type);
 int    fprintf(FILE *stream, const char *format, ...);
 int    fputc(int c, FILE *stream);
@@ -8143,19 +8144,30 @@ int    fsetpos(FILE *stream, fpos_t *pos);
 long   ftell(FILE *stream);
 size_t fwrite(const void *ptr, size_t size, size_t n_items, FILE *stream);
 char  *gets(char *s);
+int    ungetc(int c, FAR FILE *stream);
 
 int    printf(const char *format, ...);
 int    puts(const char *s);
 int    rename(const char *source, const char *target);
-int    snprintf(FAR char *buf, size_t size, const char *format, ...);
 int    sprintf(char *dest, const char *format, ...);
+int    asprintf (FAR char **ptr, FAR const char *fmt, ...);
+int    snprintf(FAR char *buf, size_t size, const char *format, ...);
 int    sscanf(const char *buf, const char *fmt, ...);
-int    ungetc(int c, FILE *stream);
+void   perror(FAR const char *s);
+int    avsprintf(FAR char **ptr, const char *fmt, va_list ap);
+
 int    vprintf(const char *s, va_list ap);
 int    vfprintf(FILE *stream, const char *s, va_list ap);
+int    vsprintf(char *buf, const char *s, va_list ap);
+int    avsprintf(FAR char **ptr, const char *fmt, va_list ap);
 int    vsnprintf(FAR char *buf, size_t size, const char *format, va_list ap);
 int    vsscanf(char *buf, const char *s, va_list ap);
-int    vsprintf(char *buf, const char *s, va_list ap);
+
+FAR FILE *fdopen(int fd, FAR const char *type);
+int    dprintf(int fd, FAR const char *fmt, ...);
+int    vdprintf(int fd, FAR const char *fmt, va_list ap);
+
+int    statfs(FAR const char *path, FAR struct statfs *buf);
 
 #include &lt;sys/stat.h&gt;
 
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
index 4927ab706..cf5631da3 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
@@ -94,8 +94,6 @@
 #define SAM_GPIO_OVRC_OFFSET       0x0058 /* Output Value Register Clear */
 #define SAM_GPIO_OVRT_OFFSET       0x005c /* Output Value Register Toggle */
 
-/* Pin Value Register Read (4 registers)*/
-
 #define SAM_GPIO_PVR_OFFSET        0x0060 /* Pin Value Register Read */
 
 /* {PUER, PDER} Selected Function
@@ -108,7 +106,7 @@
 
 #define SAM_GPIO_PUER_OFFSET       0x0070 /* Pull-up Enable Register Read/Write */
 #define SAM_GPIO_PUERS_OFFSET      0x0074 /* Pull-up Enable Register Set */
-#define SAM_GPIO_PUERC_OFFSET      0x0078 /* Pull-up Enable Register Clear*/ 
+#define SAM_GPIO_PUERC_OFFSET      0x0078 /* Pull-up Enable Register Clear */
 #define SAM_GPIO_PUERT_OFFSET      0x007c /* Pull-up Enable Register Toggle */
 
 #define SAM_GPIO_PDER_OFFSET       0x0080 /* Pull-down Enable Register Read/Write */
@@ -144,13 +142,8 @@
 #define SAM_GPIO_GFERC_OFFSET      0x00c8 /* Glitch Filter Enable Register Clear */
 #define SAM_GPIO_GFERT_OFFSET      0x00cc /* Glitch Filter Enable Register Toggle */
 
-/* Interrupt Flag Register Read (2 registers)*/
-
 #define SAM_GPIO_IFR_OFFSET        0x00d0 /* Interrupt Flag Register 0 Read */
-
-/* Interrupt Flag Register Clear (2 registers)*/
-
-#define SAM_GPIO_IFRC _OFFSET      0x00d8 /* Interrupt Flag Register 0 Clear */
+#define SAM_GPIO_IFRC_OFFSET       0x00d8 /* Interrupt Flag Register 0 Clear */
 
 /* {ODCR1, ODCR0} Output drive strength
  *
@@ -188,107 +181,398 @@
 #define SAM_GPIO_PARAMETER_OFFSET  0x01f8 /* Parameter Register Read */
 #define SAM_GPIO_VERSION_OFFSET    0x01fc /* Version Register Read */
 
+/* GPIO port offsets and addresses ******************************************************/
+
+#define SAM_GPIOA                  0
+#define SAM_GPIOB                  1
+#define SAM_GPIOC                  2
+
+#define SAM_GPIO_PORTSIZE          0x200
+#define SAM_GPION_OFFSET(n)        ((n) << 9)
+#define SAM_GPION_BASE(n)          (SAM_GPIO_BASE+SAM_GPION_OFFSET(n))
+#define SAM_GPIOA_BASE             SAM_GPION_BASE(SAM_GPIOA)
+#define SAM_GPIOB_BASE             SAM_GPION_BASE(SAM_GPIOB)
+#define SAM_GPIOC_BASE             SAM_GPION_BASE(SAM_GPIOC)
+
 /* GPIO register adresses ***************************************************************/
 
-#define SAM_GPIO_GPER              (SAM_GPIO_BASE+SAM_GPIO_GPER_OFFSET)
-#define SAM_GPIO_GPERS             (SAM_GPIO_BASE+SAM_GPIO_GPERS_OFFSET)
-#define SAM_GPIO_GPERC             (SAM_GPIO_BASE+SAM_GPIO_GPERC_OFFSET)
-#define SAM_GPIO_GPERT             (SAM_GPIO_BASE+SAM_GPIO_GPERT_OFFSET)
-
-#define SAM_GPIO_PMR0              (SAM_GPIO_BASE+SAM_GPIO_PMR0_OFFSET)
-#define SAM_GPIO_PMR0S             (SAM_GPIO_BASE+SAM_GPIO_PMR0S_OFFSET)
-#define SAM_GPIO_PMR0C             (SAM_GPIO_BASE+SAM_GPIO_PMR0C_OFFSET)
-#define SAM_GPIO_PMR0T             (SAM_GPIO_BASE+SAM_GPIO_PMR0T_OFFSET_
-
-#define SAM_GPIO_PMR1              (SAM_GPIO_BASE+SAM_GPIO_PMR1_OFFSET)
-#define SAM_GPIO_PMR1S             (SAM_GPIO_BASE+SAM_GPIO_PMR1S_OFFSET)
-#define SAM_GPIO_PMR1C             (SAM_GPIO_BASE+SAM_GPIO_PMR1C_OFFSET)
-#define SAM_GPIO_PMR1T             (SAM_GPIO_BASE+SAM_GPIO_PMR1T_OFFSET)
-
-#define SAM_GPIO_PMR2              (SAM_GPIO_BASE+SAM_GPIO_PMR2_OFFSET)
-#define SAM_GPIO_PMR2S             (SAM_GPIO_BASE+SAM_GPIO_PMR2S_OFFSET)
-#define SAM_GPIO_PMR2C             (SAM_GPIO_BASE+SAM_GPIO_PMR2C_OFFSET)
-#define SAM_GPIO_PMR2T             (SAM_GPIO_BASE+SAM_GPIO_PMR2T_OFFSET)
-
-#define SAM_GPIO_ODER              (SAM_GPIO_BASE+SAM_GPIO_ODER_OFFSET)
-#define SAM_GPIO_ODERS             (SAM_GPIO_BASE+SAM_GPIO_ODERS_OFFSET)
-#define SAM_GPIO_ODERC             (SAM_GPIO_BASE+SAM_GPIO_ODERC_OFFSET)
-#define SAM_GPIO_ODERT             (SAM_GPIO_BASE+SAM_GPIO_ODERT_OFFSET)
-
-#define SAM_GPIO_OVR               (SAM_GPIO_BASE+SAM_GPIO_OVR_OFFSET)
-#define SAM_GPIO_OVRS              (SAM_GPIO_BASE+SAM_GPIO_OVRS_OFFSET)
-#define SAM_GPIO_OVRC              (SAM_GPIO_BASE+SAM_GPIO_OVRC_OFFSET)
-#define SAM_GPIO_OVRT              (SAM_GPIO_BASE+SAM_GPIO_OVRT_OFFSET)
-
-/* Pin Value Register Read (4 registers)*/
-
-#define SAM_GPIO_PVR               (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET)
-
-#define SAM_GPIO_PUER              (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET)
-#define SAM_GPIO_PUERS             (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET)
-#define SAM_GPIO_PUERC             (SAM_GPIO_BASE+SAM_GPIO_PUERC_OFFSET)
-#define SAM_GPIO_PUERT             (SAM_GPIO_BASE+SAM_GPIO_PUERT_OFFSET)
-
-#define SAM_GPIO_PDER              (SAM_GPIO_BASE+SAM_GPIO_PDER_OFFSET)
-#define SAM_GPIO_PDERS             (SAM_GPIO_BASE+SAM_GPIO_PDERS_OFFSET)
-#define SAM_GPIO_PDERC             (SAM_GPIO_BASE+SAM_GPIO_PDERC_OFFSET)
-#define SAM_GPIO_PDERT             (SAM_GPIO_BASE+SAM_GPIO_PDERT_OFFSET)
-
-#define SAM_GPIO_IER               (SAM_GPIO_BASE+SAM_GPIO_IER_OFFSET)
-#define SAM_GPIO_IERS              (SAM_GPIO_BASE+SAM_GPIO_IERS_OFFSET)
-#define SAM_GPIO_IERC              (SAM_GPIO_BASE+SAM_GPIO_IERC_OFFSET)
-#define SAM_GPIO_IERT              (SAM_GPIO_BASE+SAM_GPIO_IERT_OFFSET)
-
-#define SAM_GPIO_IMR0              (SAM_GPIO_BASE+SAM_GPIO_IMR0_OFFSET)
-#define SAM_GPIO_IMR0S             (SAM_GPIO_BASE+SAM_GPIO_IMR0S_OFFSET)
-#define SAM_GPIO_IMR0C             (SAM_GPIO_BASE+SAM_GPIO_IMR0C_OFFSET)
-#define SAM_GPIO_IMR0T             (SAM_GPIO_BASE+SAM_GPIO_IMR0T_OFFSET)
-
-#define SAM_GPIO_IMR1              (SAM_GPIO_BASE+SAM_GPIO_IMR1_OFFSET)
-#define SAM_GPIO_IMR1S             (SAM_GPIO_BASE+SAM_GPIO_IMR1S_OFFSET)
-#define SAM_GPIO_IMR1C             (SAM_GPIO_BASE+SAM_GPIO_IMR1C_OFFSET)
-#define SAM_GPIO_IMR1T             (SAM_GPIO_BASE+SAM_GPIO_IMR1T_OFFSET)
-
-#define SAM_GPIO_GFER              (SAM_GPIO_BASE+SAM_GPIO_GFER_OFFSET)
-#define SAM_GPIO_GFERS             (SAM_GPIO_BASE+SAM_GPIO_GFERS_OFFSET)
-#define SAM_GPIO_GFERC             (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET)
-#define SAM_GPIO_GFERT             (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET)
-
-/* Interrupt Flag Register Read */
-
-#define SAM_GPIO_IFR               (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET)
-
-/* Interrupt Flag Register Clear */
-
-#define SAM_GPIO_IFRC              (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET)
-
-#define SAM_GPIO_ODCR0             (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET)
-#define SAM_GPIO_ODCR0S            (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET)
-#define SAM_GPIO_ODCR0C            (SAM_GPIO_BASE+SAM_GPIO_ODCR0C_OFFSET)
-#define SAM_GPIO_ODCR0T            (SAM_GPIO_BASE+SAM_GPIO_ODCR0T_OFFSET)
-
-#define SAM_GPIO_ODCR1             (SAM_GPIO_BASE+SAM_GPIO_ODCR1_OFFSET)
-#define SAM_GPIO_ODCR1S            (SAM_GPIO_BASE+SAM_GPIO_ODCR1S_OFFSET)
-#define SAM_GPIO_ODCR1C            (SAM_GPIO_BASE+SAM_GPIO_ODCR1C_OFFSET)
-#define SAM_GPIO_ODCR1T            (SAM_GPIO_BASE+SAM_GPIO_ODCR1T_OFFSET)
-
-#define SAM_GPIO_OSRR0             (SAM_GPIO_BASE+SAM_GPIO_OSRR0_OFFSET)
-#define SAM_GPIO_OSRR0S            (SAM_GPIO_BASE+SAM_GPIO_OSRR0S_OFFSET)
-#define SAM_GPIO_OSRR0C            (SAM_GPIO_BASE+SAM_GPIO_OSRR0C_OFFSET)
-#define SAM_GPIO_OSRR0T            (SAM_GPIO_BASE+SAM_GPIO_OSRR0T_OFFSET)
-
-#define SAM_GPIO_STER              (SAM_GPIO_BASE+SAM_GPIO_STER_OFFSET)
-#define SAM_GPIO_STERS             (SAM_GPIO_BASE+SAM_GPIO_STERS_OFFSET)
-#define SAM_GPIO_STERC             (SAM_GPIO_BASE+SAM_GPIO_STERC_OFFSET)
-#define SAM_GPIO_STERT             (SAM_GPIO_BASE+SAM_GPIO_STERT_OFFSET)
-
-#define SAM_GPIO_EVER              (SAM_GPIO_BASE+SAM_GPIO_EVER_OFFSET)
-#define SAM_GPIO_EVERS             (SAM_GPIO_BASE+SAM_GPIO_EVERS_OFFSET)
-#define SAM_GPIO_EVERC             (SAM_GPIO_BASE+SAM_GPIO_EVERC_OFFSET)
-#define SAM_GPIO_EVERT             (SAM_GPIO_BASE+SAM_GPIO_EVERT_OFFSET)
-
-#define SAM_GPIO_PARAMETER         (SAM_GPIO_BASE+SAM_GPIO_PARAMETER_OFFSET)
-#define SAM_GPIO_VERSION           (SAM_GPIO_BASE+SAM_GPIO_VERSION_OFFSET)
+#define SAM_GPIO_GPER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIO_GPERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIO_GPERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIO_GPERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIO_PMR0(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIO_PMR0S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIO_PMR0C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIO_PMR0T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIO_PMR1(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIO_PMR1S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIO_PMR1C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIO_PMR1T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIO_PMR2(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIO_PMR2S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIO_PMR2C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIO_PMR2T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIO_ODER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIO_ODERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIO_ODERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIO_ODERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIO_OVR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIO_OVRS(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIO_OVRC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIO_OVRT(n)           (SAM_GPION_BASE(n)+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIO_PVR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIO_PUER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIO_PUERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIO_PUERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIO_PUERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIO_PDER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIO_PDERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIO_PDERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIO_PDERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIO_IER(n)            (SAM_GPION_BASE(n)+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIO_IERS(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIO_IERC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIO_IERT(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIO_IMR0(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIO_IMR0S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIO_IMR0C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIO_IMR0T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIO_IMR1(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIO_IMR1S(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIO_IMR1C(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIO_IMR1T(n)          (SAM_GPION_BASE(n)+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIO_GFER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIO_GFERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIO_GFERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIO_GFERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIO_IFR(n)            (SAM_GPION_BASE(n)+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIO_IFRC(n)           (SAM_GPION_BASE(n)+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIO_ODCR0(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIO_ODCR0S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIO_ODCR0C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIO_ODCR0T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIO_ODCR1(n)          (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIO_ODCR1S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIO_ODCR1C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIO_ODCR1T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIO_OSRR0(n)          (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIO_OSRR0S(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIO_OSRR0C(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIO_OSRR0T(n)         (SAM_GPION_BASE(n)+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIO_STER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIO_STERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIO_STERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIO_STERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIO_EVER(n)           (SAM_GPION_BASE(n)+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIO_EVERS(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIO_EVERC(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIO_EVERT(n)          (SAM_GPION_BASE(n)+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIO_PARAMETER(n)      (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIO_VERSION (n)       (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTA register adresses *********************************************************/
+
+#define SAM_GPIOA_GPER             (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOA_GPERS            (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOA_GPERC            (SAM_GPIOA_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOA_GPERT            (SAM_GPIOA_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOA_PMR0             (SAM_GPIOA_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOA_PMR0S            (SAM_GPIOA_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOA_PMR0C            (SAM_GPIOA_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOA_PMR0T            (SAM_GPIOA_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOA_PMR1             (SAM_GPIOA_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOA_PMR1S            (SAM_GPIOA_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOA_PMR1C            (SAM_GPIOA_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOA_PMR1T            (SAM_GPIOA_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOA_PMR2             (SAM_GPIOA_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOA_PMR2S            (SAM_GPIOA_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOA_PMR2C            (SAM_GPIOA_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOA_PMR2T            (SAM_GPIOA_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOA_ODER             (SAM_GPIOA_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOA_ODERS            (SAM_GPIOA_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOA_ODERC            (SAM_GPIOA_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOA_ODERT            (SAM_GPIOA_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOA_OVR              (SAM_GPIOA_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOA_OVRS             (SAM_GPIOA_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOA_OVRC             (SAM_GPIOA_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOA_OVRT             (SAM_GPIOA_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOA_PVR              (SAM_GPIOA_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOA_PUER             (SAM_GPIOA_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOA_PUERS            (SAM_GPIOA_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOA_PUERC            (SAM_GPIOA_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOA_PUERT            (SAM_GPIOA_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOA_PDER             (SAM_GPIOA_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOA_PDERS            (SAM_GPIOA_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOA_PDERC            (SAM_GPIOA_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOA_PDERT            (SAM_GPIOA_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOA_IER              (SAM_GPIOA_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOA_IERS             (SAM_GPIOA_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOA_IERC             (SAM_GPIOA_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOA_IERT             (SAM_GPIOA_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOA_IMR0             (SAM_GPIOA_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOA_IMR0S            (SAM_GPIOA_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOA_IMR0C            (SAM_GPIOA_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOA_IMR0T            (SAM_GPIOA_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOA_IMR1             (SAM_GPIOA_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOA_IMR1S            (SAM_GPIOA_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOA_IMR1C            (SAM_GPIOA_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOA_IMR1T            (SAM_GPIOA_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOA_GFER             (SAM_GPIOA_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOA_GFERS            (SAM_GPIOA_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOA_GFERC            (SAM_GPIOA_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOA_GFERT            (SAM_GPIOA_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOA_IFR              (SAM_GPIOA_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOA_IFRC             (SAM_GPIOA_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOA_ODCR0            (SAM_GPIOA_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOA_ODCR0S           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOA_ODCR0C           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOA_ODCR0T           (SAM_GPIOA_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOA_ODCR1            (SAM_GPIOA_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOA_ODCR1S           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOA_ODCR1C           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOA_ODCR1T           (SAM_GPIOA_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOA_OSRR0            (SAM_GPIOA_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOA_OSRR0S           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOA_OSRR0C           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOA_OSRR0T           (SAM_GPIOA_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOA_STER             (SAM_GPIOA_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOA_STERS            (SAM_GPIOA_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOA_STERC            (SAM_GPIOA_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOA_STERT            (SAM_GPIOA_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOA_EVER             (SAM_GPIOA_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOA_EVERS            (SAM_GPIOA_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOA_EVERC            (SAM_GPIOA_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOA_EVERT            (SAM_GPIOA_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOA_PARAMETER        (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOA_VERSION          (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTB register adresses *********************************************************/
+
+#define SAM_GPIOB_GPER             (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOB_GPERS            (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOB_GPERC            (SAM_GPIOB_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOB_GPERT            (SAM_GPIOB_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOB_PMR0             (SAM_GPIOB_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOB_PMR0S            (SAM_GPIOB_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOB_PMR0C            (SAM_GPIOB_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOB_PMR0T            (SAM_GPIOB_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOB_PMR1             (SAM_GPIOB_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOB_PMR1S            (SAM_GPIOB_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOB_PMR1C            (SAM_GPIOB_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOB_PMR1T            (SAM_GPIOB_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOB_PMR2             (SAM_GPIOB_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOB_PMR2S            (SAM_GPIOB_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOB_PMR2C            (SAM_GPIOB_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOB_PMR2T            (SAM_GPIOB_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOB_ODER             (SAM_GPIOB_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOB_ODERS            (SAM_GPIOB_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOB_ODERC            (SAM_GPIOB_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOB_ODERT            (SAM_GPIOB_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOB_OVR              (SAM_GPIOB_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOB_OVRS             (SAM_GPIOB_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOB_OVRC             (SAM_GPIOB_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOB_OVRT             (SAM_GPIOB_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOB_PVR              (SAM_GPIOB_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOB_PUER             (SAM_GPIOB_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOB_PUERS            (SAM_GPIOB_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOB_PUERC            (SAM_GPIOB_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOB_PUERT            (SAM_GPIOB_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOB_PDER             (SAM_GPIOB_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOB_PDERS            (SAM_GPIOB_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOB_PDERC            (SAM_GPIOB_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOB_PDERT            (SAM_GPIOB_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOB_IER              (SAM_GPIOB_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOB_IERS             (SAM_GPIOB_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOB_IERC             (SAM_GPIOB_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOB_IERT             (SAM_GPIOB_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOB_IMR0             (SAM_GPIOB_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOB_IMR0S            (SAM_GPIOB_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOB_IMR0C            (SAM_GPIOB_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOB_IMR0T            (SAM_GPIOB_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOB_IMR1             (SAM_GPIOB_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOB_IMR1S            (SAM_GPIOB_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOB_IMR1C            (SAM_GPIOB_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOB_IMR1T            (SAM_GPIOB_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOB_GFER             (SAM_GPIOB_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOB_GFERS            (SAM_GPIOB_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOB_GFERC            (SAM_GPIOB_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOB_GFERT            (SAM_GPIOB_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOB_IFR              (SAM_GPIOB_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOB_IFRC             (SAM_GPIOB_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOB_ODCR0            (SAM_GPIOB_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOB_ODCR0S           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOB_ODCR0C           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOB_ODCR0T           (SAM_GPIOB_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOB_ODCR1            (SAM_GPIOB_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOB_ODCR1S           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOB_ODCR1C           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOB_ODCR1T           (SAM_GPIOB_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOB_OSRR0            (SAM_GPIOB_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOB_OSRR0S           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOB_OSRR0C           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOB_OSRR0T           (SAM_GPIOB_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOB_STER             (SAM_GPIOB_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOB_STERS            (SAM_GPIOB_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOB_STERC            (SAM_GPIOB_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOB_STERT            (SAM_GPIOB_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOB_EVER             (SAM_GPIOB_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOB_EVERS            (SAM_GPIOB_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOB_EVERC            (SAM_GPIOB_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOB_EVERT            (SAM_GPIOB_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOB_PARAMETER        (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOB_VERSION          (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO PORTC register adresses *********************************************************/
+
+#define SAM_GPIOC_GPER             (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIOC_GPERS            (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIOC_GPERC            (SAM_GPIOC_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIOC_GPERT            (SAM_GPIOC_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIOC_PMR0             (SAM_GPIOC_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIOC_PMR0S            (SAM_GPIOC_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIOC_PMR0C            (SAM_GPIOC_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIOC_PMR0T            (SAM_GPIOC_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIOC_PMR1             (SAM_GPIOC_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIOC_PMR1S            (SAM_GPIOC_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIOC_PMR1C            (SAM_GPIOC_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIOC_PMR1T            (SAM_GPIOC_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIOC_PMR2             (SAM_GPIOC_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIOC_PMR2S            (SAM_GPIOC_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIOC_PMR2C            (SAM_GPIOC_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIOC_PMR2T            (SAM_GPIOC_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIOC_ODER             (SAM_GPIOC_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIOC_ODERS            (SAM_GPIOC_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIOC_ODERC            (SAM_GPIOC_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIOC_ODERT            (SAM_GPIOC_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIOC_OVR              (SAM_GPIOC_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIOC_OVRS             (SAM_GPIOC_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIOC_OVRC             (SAM_GPIOC_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIOC_OVRT             (SAM_GPIOC_BASE+SAM_GPIO_OVRT_OFFSET)
+
+#define SAM_GPIOC_PVR              (SAM_GPIOC_BASE+SAM_GPIO_PVR_OFFSET)
+
+#define SAM_GPIOC_PUER             (SAM_GPIOC_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIOC_PUERS            (SAM_GPIOC_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIOC_PUERC            (SAM_GPIOC_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIOC_PUERT            (SAM_GPIOC_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIOC_PDER             (SAM_GPIOC_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIOC_PDERS            (SAM_GPIOC_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIOC_PDERC            (SAM_GPIOC_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIOC_PDERT            (SAM_GPIOC_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIOC_IER              (SAM_GPIOC_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIOC_IERS             (SAM_GPIOC_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIOC_IERC             (SAM_GPIOC_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIOC_IERT             (SAM_GPIOC_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIOC_IMR0             (SAM_GPIOC_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIOC_IMR0S            (SAM_GPIOC_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIOC_IMR0C            (SAM_GPIOC_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIOC_IMR0T            (SAM_GPIOC_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIOC_IMR1             (SAM_GPIOC_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIOC_IMR1S            (SAM_GPIOC_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIOC_IMR1C            (SAM_GPIOC_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIOC_IMR1T            (SAM_GPIOC_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIOC_GFER             (SAM_GPIOC_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIOC_GFERS            (SAM_GPIOC_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIOC_GFERC            (SAM_GPIOC_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIOC_GFERT            (SAM_GPIOC_BASE+SAM_GPIO_GFERT_OFFSET)
+
+#define SAM_GPIOC_IFR              (SAM_GPIOC_BASE+SAM_GPIO_IFR_OFFSET)
+#define SAM_GPIOC_IFRC             (SAM_GPIOC_BASE+SAM_GPIO_IFRC_OFFSET)
+
+#define SAM_GPIOC_ODCR0            (SAM_GPIOC_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIOC_ODCR0S           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIOC_ODCR0C           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIOC_ODCR0T           (SAM_GPIOC_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIOC_ODCR1            (SAM_GPIOC_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIOC_ODCR1S           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIOC_ODCR1C           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIOC_ODCR1T           (SAM_GPIOC_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIOC_OSRR0            (SAM_GPIOC_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIOC_OSRR0S           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIOC_OSRR0C           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIOC_OSRR0T           (SAM_GPIOC_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIOC_STER             (SAM_GPIOC_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIOC_STERS            (SAM_GPIOC_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIOC_STERC            (SAM_GPIOC_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIOC_STERT            (SAM_GPIOC_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIOC_EVER             (SAM_GPIOC_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIOC_EVERS            (SAM_GPIOC_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIOC_EVERC            (SAM_GPIOC_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIOC_EVERT            (SAM_GPIOC_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIOC_PARAMETER        (SAM_GPIOC_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIOC_VERSION          (SAM_GPIOC_BASE+SAM_GPIO_VERSION_OFFSET)
 
 /* GPIO register bit definitions ********************************************************/
 
diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.c b/nuttx/arch/arm/src/sam34/sam4l_gpio.c
index 88f3d02cb..977e91e60 100644
--- a/nuttx/arch/arm/src/sam34/sam4l_gpio.c
+++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.c
@@ -105,6 +105,8 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
  *
  * Description:
  *   Configure a GPIO input pin based on bit-encoded description of the pin.
+ *   This function serves the dual role of putting all pins into a known,
+ *   initial state.  Hence, it is overkill for what really needs to be done.
  *
  ****************************************************************************/
 
@@ -200,10 +202,10 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
    * falling edges.
    */
 
-  ret = sam_configinput(base, pin, cfgset)
-  if (ret = OK)
+  ret = sam_configinput(base, pin, cfgset);
+  if (ret == OK)
     {
-      /* Disable rising and falling edge interrupts as requested 
+      /* Disable rising and falling edge interrupts as requested
        * {IMR1, IMR0} Interrupt Mode
        *
        *   00 Pin Change   <-- We already have this
@@ -214,13 +216,13 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
 
       gpio_pinset_t edges = cfgset & GPIO_INT_MASK;
 
-      if (eges = GPIO_INT_RISING)
+      if (edges == GPIO_INT_RISING)
         {
           /* Rising only.. disable interrrupts on the falling edge */
 
           putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET);
         }
-      else if (edges = GPIO_INT_FALLING)
+      else if (edges == GPIO_INT_FALLING)
         {
           /* Falling only.. disable interrrupts on the rising edge */
 
@@ -363,7 +365,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
       case _GPIO_FUNCC: /* Function C 010 */
         putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET);
         break;
- 
+
       case _GPIO_FUNCE: /* Function E 100 */
         putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET);
         break;
@@ -397,13 +399,13 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
    */
 
   edges = cfgset & GPIO_INT_MASK;
-  if (eges = GPIO_INT_RISING)
+  if (edges == GPIO_INT_RISING)
     {
       /* Rising only.. disable interrrupts on the falling edge */
 
       putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET);
     }
-  else if (edges = GPIO_INT_FALLING)
+  else if (edges == GPIO_INT_FALLING)
     {
       /* Falling only.. disable interrrupts on the rising edge */
 
diff --git a/nuttx/configs/sam4l-xplained/src/sam_userleds.c b/nuttx/configs/sam4l-xplained/src/sam_userleds.c
index bf77e2c7f..7a2c45efc 100644
--- a/nuttx/configs/sam4l-xplained/src/sam_userleds.c
+++ b/nuttx/configs/sam4l-xplained/src/sam_userleds.c
@@ -41,7 +41,8 @@
  * PC07 to GND.
  *
  * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
- * control LED0.  Otherwise, LED0 can be controlled from logic in this file.
+ * control LED0.  Otherwise, LED0 can be controlled from user applications
+ * using the logic in this file.
  */
 
 /****************************************************************************