Add SAM4L (and 4S) GPIO register definitions

6 files changed, 1067 insertions, 266 deletions

diff --git a/nuttx/arch/arm/src/sam34/chip.h b/nuttx/arch/arm/src/sam34/chip.h
index 3c92f53ef..eefb969bc 100644
--- a/nuttx/arch/arm/src/sam34/chip.h
+++ b/nuttx/arch/arm/src/sam34/chip.h
@@ -58,7 +58,8 @@
 #    include "chip/sam3u_vectors.h"
 #  elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #    include "chip/sam4l_vectors.h"
-#    include "chip/sam4l_memorymap.h"
+#  elif defined(CONFIG_ARCH_CHIP_SAM4S)
+#    include "chip/sam4s_vectors.h"
 #  else
 #    error Unrecognized SAM architecture
 #  endif
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h
new file mode 100644
index 000000000..14ceb0724
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h
@@ -0,0 +1,324 @@
+/****************************************************************************************
+ * arch/arm/src/sam34/chip/sam3u_pio.h
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* PIO register offsets *****************************************************************/
+
+#define SAM_PIO_PER_OFFSET         0x0000 /* PIO Enable Register */
+#define SAM_PIO_PDR_OFFSET         0x0004 /* PIO Disable Register */
+#define SAM_PIO_PSR_OFFSET         0x0008 /* PIO Status Register */
+                                          /* 0x000c: Reserved */
+#define SAM_PIO_OER_OFFSET         0x0010 /* Output Enable Register */
+#define SAM_PIO_ODR_OFFSET         0x0014 /* Output Disable Register */
+#define SAM_PIO_OSR_OFFSET         0x0018 /* utput Status Register */
+                                          /* 0x001c: Reserved */
+#define SAM_PIO_IFER_OFFSET        0x0020 /* Glitch Input Filter Enable Register */
+#define SAM_PIO_IFDR_OFFSET        0x0024 /* Glitch Input Filter Disable Register */
+#define SAM_PIO_IFSR_OFFSET        0x0028 /* Glitch Input Filter Status Register */
+                                          /* 0x002c: Reserved */
+#define SAM_PIO_SODR_OFFSET        0x0030 /* Set Output Data Register */
+#define SAM_PIO_CODR_OFFSET        0x0034 /* Clear Output Data Register */
+#define SAM_PIO_ODSR_OFFSET        0x0038 /* Output Data Status Register */
+#define SAM_PIO_PDSR_OFFSET        0x003c /* Pin Data Status Register */
+#define SAM_PIO_IER_OFFSET         0x0040 /* Interrupt Enable Register */
+#define SAM_PIO_IDR_OFFSET         0x0044 /* Interrupt Disable Register */
+#define SAM_PIO_IMR_OFFSET         0x0048 /* Interrupt Mask Register */
+#define SAM_PIO_ISR_OFFSET         0x004c /* Interrupt Status Register */
+#define SAM_PIO_MDER_OFFSET        0x0050 /* Multi-driver Enable Register */
+#define SAM_PIO_MDDR_OFFSET        0x0054 /* Multi-driver Disable Register */
+#define SAM_PIO_MDSR_OFFSET        0x0058 /* Multi-driver Status Register */
+                                          /* 0x005c: Reserved */
+#define SAM_PIO_PUDR_OFFSET        0x0060 /* Pull-up Disable Register */
+#define SAM_PIO_PUER_OFFSET        0x0064 /* Pull-up Enable Register */
+#define SAM_PIO_PUSR_OFFSET        0x0068 /* Pad Pull-up Status Register */
+                                          /* 0x006c: Reserved */
+#define SAM_PIO_ABSR_OFFSET        0x0070 /* Peripheral AB Select Register */
+                                          /* 0x0074-0x007c: Reserved */
+#define SAM_PIO_SCIFSR_OFFSET      0x0080 /* System Clock Glitch Input Filter Select Register */
+#define SAM_PIO_DIFSR_OFFSET       0x0084 /* Debouncing Input Filter Select Register */
+#define SAM_PIO_IFDGSR_OFFSET      0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define SAM_PIO_SCDR_OFFSET        0x008c /* Slow Clock Divider Debouncing Register */
+                                          /* 0x0090-0x009c: Reserved */
+#define SAM_PIO_OWER_OFFSET        0x00a0 /* Output Write Enable */
+#define SAM_PIO_OWDR_OFFSET        0x00a4 /* Output Write Disable */
+#define SAM_PIO_OWSR_OFFSET        0x00a8 /* Output Write Status Register */
+                                          /* 0x00ac: Reserved */
+#define SAM_PIO_AIMER_OFFSET       0x00b0 /* Additional Interrupt Modes Enable Register */
+#define SAM_PIO_AIMDR_OFFSET       0x00b4 /* Additional Interrupt Modes Disables Register */
+#define SAM_PIO_AIMMR_OFFSET       0x00b8 /* Additional Interrupt Modes Mask Register */
+                                          /* 0x00bc: Reserved */
+#define SAM_PIO_ESR_OFFSET         0x00c0 /* Edge Select Register */
+#define SAM_PIO_LSR_OFFSET         0x00c4 /* Level Select Register */
+#define SAM_PIO_ELSR_OFFSET        0x00c8 /* Edge/Level Status Register */
+                                          /* 0x00cc: Reserved */
+#define SAM_PIO_FELLSR_OFFSET      0x00d0 /* Falling Edge/Low Level Select Register */
+#define SAM_PIO_REHLSR_OFFSET      0x00d4 /* Rising Edge/ High Level Select Register */
+#define SAM_PIO_FRLHSR_OFFSET      0x00d8 /* Fall/Rise - Low/High Status Register */
+                                          /* 0x00dc: Reserved */
+#define SAM_PIO_LOCKSR_OFFSET      0x00e0 /* Lock Status */
+#define SAM_PIO_WPMR_OFFSET        0x00e4 /* Write Protect Mode Register */
+#define SAM_PIO_WPSR_OFFSET        0x00e8 /* Write Protect Status Register */
+                                          /* 0x00ec-0x00f8: Reserved */
+                                          /* 0x0100-0x0144: Reserved */
+
+/* PIO register adresses ****************************************************************/
+
+#define PIOA                       (0)
+#define PIOB                       (1)
+#define PIOC                       (2)
+#define NPIO                       (3)
+
+#define SAM_PIO_PER(n)             (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET)
+#define SAM_PIO_PDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET)
+#define SAM_PIO_PSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET)
+#define SAM_PIO_OER(n)             (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET)
+#define SAM_PIO_ODR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET)
+#define SAM_PIO_OSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET)
+#define SAM_PIO_IFER(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET)
+#define SAM_PIO_IFDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIO_IFSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIO_SODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET)
+#define SAM_PIO_CODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET)
+#define SAM_PIO_ODSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIO_PDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIO_IER(n)             (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET)
+#define SAM_PIO_IDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET)
+#define SAM_PIO_IMR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET)
+#define SAM_PIO_ISR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET)
+#define SAM_PIO_MDER(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET)
+#define SAM_PIO_MDDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIO_MDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIO_PUDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIO_PUER(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET)
+#define SAM_PIO_PUSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIO_ABSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET)
+#define SAM_PIO_SCIFSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET)
+#define SAM_PIO_DIFSR(n)           (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET)
+#define SAM_PIO_IFDGSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET)
+#define SAM_PIO_SCDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIO_OWER(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET)
+#define SAM_PIO_OWDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIO_OWSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIO_AIMER(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIO_AIMDR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIO_AIMMR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIO_ESR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET)
+#define SAM_PIO_LSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET)
+#define SAM_PIO_ELSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIO_FELLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIO_REHLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIO_FRLHSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIO_LOCKSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIO_WPMR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIO_WPSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET)
+
+#define SAM_PIOA_PER               (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOA_PDR               (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOA_PSR               (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOA_OER               (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOA_ODR               (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOA_OSR               (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOA_IFER              (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOA_IFDR              (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOA_IFSR              (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOA_SODR              (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOA_CODR              (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOA_ODSR              (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOA_PDSR              (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOA_IER               (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOA_IDR               (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOA_IMR               (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOA_ISR               (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOA_MDER              (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOA_MDDR              (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOA_MDSR              (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOA_PUDR              (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOA_PUER              (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOA_PUSR              (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOA_ABSR              (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET)
+#define SAM_PIOA_SCIFSR            (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET)
+#define SAM_PIOA_DIFSR             (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET)
+#define SAM_PIOA_IFDGSR            (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET)
+#define SAM_PIOA_SCDR              (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOA_OWER              (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOA_OWDR              (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOA_OWSR              (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOA_AIMER             (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOA_AIMDR             (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOA_AIMMR             (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOA_ESR               (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOA_LSR               (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOA_ELSR              (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOA_FELLSR            (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOA_REHLSR            (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOA_FRLHSR            (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOA_LOCKSR            (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOA_WPMR              (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOA_WPSR              (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET)
+
+#define SAM_PIOB_PER               (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOB_PDR_              (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOB_PSR               (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOB_OER               (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOB_ODR               (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOB_OSR               (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOB_IFER              (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOB_IFDR              (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOB_IFSR              (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOB_SODR              (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOB_CODR              (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOB_ODSR              (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOB_PDSR              (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOB_IER               (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOB_IDR               (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOB_IMR               (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOB_ISR               (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOB_MDER              (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOB_MDDR              (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOB_MDSR              (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOB_PUDR              (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOB_PUER              (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOB_PUSR              (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOB_ABSR              (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET)
+#define SAM_PIOB_SCIFSR            (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET)
+#define SAM_PIOB_DIFSR             (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET)
+#define SAM_PIOB_IFDGSR            (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET)
+#define SAM_PIOB_SCDR              (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOB_OWER              (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOB_OWDR              (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOB_OWSR              (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOB_AIMER             (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOB_AIMDR             (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOB_AIMMR             (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOB_ESR               (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOB_LSR               (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOB_ELSR              (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOB_FELLSR            (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOB_REHLSR            (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOB_FRLHSR            (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOB_LOCKSR            (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOB_WPMR              (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOB_WPSR              (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET)
+
+#define SAM_PIOC_PER               (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOC_PDR_              (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOC_PSR               (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOC_OER               (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOC_ODR               (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOC_OSR               (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOC_IFER              (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOC_IFDR              (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOC_IFSR              (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOC_SODR              (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOC_CODR              (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOC_ODSR              (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOC_PDSR              (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOC_IER               (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOC_IDR               (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOC_IMR               (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOC_ISR               (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOC_MDER              (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOC_MDDR              (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOC_MDSR              (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOC_PUDR              (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOC_PUER              (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOC_PUSR              (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOC_ABSR              (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET)
+#define SAM_PIOC_SCIFSR            (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET)
+#define SAM_PIOC_DIFSR             (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET)
+#define SAM_PIOC_IFDGSR            (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET)
+#define SAM_PIOC_SCDR              (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOC_OWER              (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOC_OWDR              (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOC_OWSR              (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOC_AIMER             (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOC_AIMDR             (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOC_AIMMR             (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOC_ESR               (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOC_LSR               (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOC_ELSR              (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOC_FELLSR            (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOC_REHLSR            (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOC_FRLHSR            (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOC_LOCKSR            (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOC_WPMR              (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOC_WPSR              (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET)
+
+/* PIO register bit definitions *********************************************************/
+
+/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
+
+#define PIO(n)                     (1<<(n)) /* Bit n: PIO n */
+
+/* PIO Write Protect Mode Register */
+
+#define PIO_WPMR_WPEN              1 << 0)  /* Bit 0:  Write Protect Enable */
+#define PIO_WPMR_WPKEY_SHIFT       8)       /* Bits 8-31: Write Protect KEY */
+#define PIO_WPMR_WPKEY_MASK        0xffffff << PIO_WPMR_WPKEY_SHIFT)
+
+/* PIO Write Protect Status Register */
+
+#define PIO_WPSR_WPVS              1 << 0)  /* Bit 0:  Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_SHIFT      8)       /* Bits 8-23: Write Protect Violation Source */
+#define PIO_WPSR_WPVSRC_MASK       0xffff << PIO_WPSR_WPVSRC_SHIFT)
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H */
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
new file mode 100644
index 000000000..d180b2b92
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h
@@ -0,0 +1,327 @@
+/****************************************************************************************
+ * arch/arm/src/sam34/chip/sam4l_gpio.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* PIO register offsets *****************************************************************/
+
+#define SAM_GPIO_GPER_OFFSET       0x0000 /* GPIO Enable Register Read/Write */
+#define SAM_GPIO_GPERS_OFFSET      0x0004 /* GPIO Enable Register Set */
+#define SAM_GPIO_GPERC_OFFSET      0x0008 /* GPIO Enable Register Clear */
+#define SAM_GPIO_GPERT_OFFSET      0x000c /* GPIO Enable Register Toggle */
+
+/* {PMR2, PMR1, PMR0} Selected Peripheral Function
+ *
+ *   000 GPIO 100 D
+ *   001 A    101 E
+ *   010 B    110 F
+ *   011 C    111 G
+ *
+ * NOTE:  Labeling in the data sheet is inconsistent.  In the pin multiplexing table,
+ * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO.  In the
+ * register description, it should A-H with presumably A corresponding to 000.  Here
+ * we adopt the above convention.
+ */
+
+#define SAM_GPIO_PMR0_OFFSET       0x0010 /* Peripheral Mux Register 0 Read/Write */
+#define SAM_GPIO_PMR0S_OFFSET      0x0014 /* Peripheral Mux Register 0 Set */
+#define SAM_GPIO_PMR0C_OFFSET      0x0018 /* Peripheral Mux Register 0 Clear */
+#define SAM_GPIO_PMR0T_OFFSET      0x001c /* Peripheral Mux Register 0 Toggle */
+
+#define SAM_GPIO_PMR1_OFFSET       0x0020 /* Peripheral Mux Register 1 Read/Write */
+#define SAM_GPIO_PMR1S_OFFSET      0x0024 /* Peripheral Mux Register 1 Set */
+#define SAM_GPIO_PMR1C_OFFSET      0x0028 /* Peripheral Mux Register 1 Clear */
+#define SAM_GPIO_PMR1T_OFFSET      0x002c /* Peripheral Mux Register 1 Toggle */
+
+#define SAM_GPIO_PMR2_OFFSET       0x0030 /* Peripheral Mux Register 2 Read/Write */
+#define SAM_GPIO_PMR2S_OFFSET      0x0034 /* Peripheral Mux Register 2 Set */
+#define SAM_GPIO_PMR2C_OFFSET      0x0038 /* Peripheral Mux Register 2 Clear */
+#define SAM_GPIO_PMR2T_OFFSET      0x003c /* Peripheral Mux Register 2 Toggle */
+
+#define SAM_GPIO_ODER_OFFSET       0x0040 /* Output Driver Enable Register Read/Write */
+#define SAM_GPIO_ODERS_OFFSET      0x0044 /* Output Driver Enable Register Set */
+#define SAM_GPIO_ODERC_OFFSET      0x0048 /* Output Driver Enable Register Clear */
+#define SAM_GPIO_ODERT_OFFSET      0x004c /* Output Driver Enable Register Toggle */
+
+#define SAM_GPIO_OVR_OFFSET        0x0050 /* Output Value Register Read/Write */
+#define SAM_GPIO_OVRS_OFFSET       0x0054 /* Output Value Register Set */
+#define SAM_GPIO_OVRC_OFFSET       0x0058 /* Output Value Register Clear */
+#define SAM_GPIO_OVRT_OFFSET       0x005c /* Output Value Register Toggle */
+
+/* Pin Value Register Read (4 registers)*/
+
+#define SAM_GPIO_PVR_OFFSET(n)     (0x0060 + (((n) & ~31) >> 3))
+#define SAM_GPIO_PVR0_OFFSET       0x0060 /* Pin Value Register 0 Read*/
+#define SAM_GPIO_PVR1_OFFSET       0x0064 /* Pin Value Register 1 Read*/
+#define SAM_GPIO_PVR2_OFFSET       0x0068 /* Pin Value Register 2 Read*/
+#define SAM_GPIO_PVR3_OFFSET       0x006c /* Pin Value Register 3 Read*/
+
+/* {PUER, PDER} Selected Function
+ *
+ *   00 Disabled
+ *   01 Pull-down enabled
+ *   10 Pull-up enabled
+ *   11 Buskeeper enabled
+ */
+
+#define SAM_GPIO_PUER_OFFSET       0x0070 /* Pull-up Enable Register Read/Write */
+#define SAM_GPIO_PUERS_OFFSET      0x0074 /* Pull-up Enable Register Set */
+#define SAM_GPIO_PUERC_OFFSET      0x0078 /* Pull-up Enable Register Clear*/ 
+#define SAM_GPIO_PUERT_OFFSET      0x007c /* Pull-up Enable Register Toggle */
+
+#define SAM_GPIO_PDER_OFFSET       0x0080 /* Pull-down Enable Register Read/Write */
+#define SAM_GPIO_PDERS_OFFSET      0x0084 /* Pull-down Enable Register Set */
+#define SAM_GPIO_PDERC_OFFSET      0x0088 /* Pull-down Enable Register Clear */
+#define SAM_GPIO_PDERT_OFFSET      0x008c /* Pull-down Enable Register Toggle */
+
+#define SAM_GPIO_IER_OFFSET        0x0090 /* Interrupt Enable Register Read/Write */
+#define SAM_GPIO_IERS_OFFSET       0x0094 /* Interrupt Enable Register Set */
+#define SAM_GPIO_IERC_OFFSET       0x0098 /* Interrupt Enable Register Clear */
+#define SAM_GPIO_IERT_OFFSET       0x009c /* Interrupt Enable Register Toggle */
+
+/* {IMR1, IMR0} Interrupt Mode
+ *
+ *   00 Pin Change
+ *   01 Rising Edge
+ *   10 Falling Edge
+ *   11 Reserved
+ */
+
+#define SAM_GPIO_IMR0_OFFSET       0x00a0 /* Interrupt Mode Register 0 Read/Write */
+#define SAM_GPIO_IMR0S_OFFSET      0x00a4 /* Interrupt Mode Register 0 Set */
+#define SAM_GPIO_IMR0C_OFFSET      0x00a8 /* Interrupt Mode Register 0 Clear */
+#define SAM_GPIO_IMR0T_OFFSET      0x00ac /* Interrupt Mode Register 0 Toggle */
+
+#define SAM_GPIO_IMR1_OFFSET       0x00b0 /* Interrupt Mode Register 1 Read/Write */
+#define SAM_GPIO_IMR1S_OFFSET      0x00b4 /* Interrupt Mode Register 1 Set */
+#define SAM_GPIO_IMR1C_OFFSET      0x00b8 /* Interrupt Mode Register 1 Clear */
+#define SAM_GPIO_IMR1T_OFFSET      0x00bc /* Interrupt Mode Register 1 Toggle */
+
+#define SAM_GPIO_GFER_OFFSET       0x00c0 /* Glitch Filter Enable Register Read/Write */
+#define SAM_GPIO_GFERS_OFFSET      0x00c4 /* Glitch Filter Enable Register Set */
+#define SAM_GPIO_GFERC_OFFSET      0x00c8 /* Glitch Filter Enable Register Clear */
+#define SAM_GPIO_GFERT_OFFSET      0x00cc /* Glitch Filter Enable Register Toggle */
+
+/* Interrupt Flag Register Read (2 registers)*/
+
+#define SAM_GPIO_IFR_OFFSET(n)     (0x00d0 + (((n) & ~31) >> 3))
+#define SAM_GPIO_IFR0_OFFSET       0x00d0 /* Interrupt Flag Register 0 Read */
+#define SAM_GPIO_IFR1_OFFSET       0x00d4 /* Interrupt Flag Register 0 Read */
+
+/* Interrupt Flag Register Clear (2 registers)*/
+
+#define SAM_GPIO_IFRC_OFFSET(n)    (0x00d8 + (((n) & ~31) >> 3))
+#define SAM_GPIO_IFRC0_OFFSET      0x00d8 /* Interrupt Flag Register 0 Clear */
+#define SAM_GPIO_IFRC1_OFFSET      0x00dc /* Interrupt Flag Register 1 Clear */
+
+/* {ODCR1, ODCR0} Interrupt Mode
+ *
+ *   00 Lowest drive strength
+ *   01 ...
+ *   10 ...
+ *   11 Highest drive strength
+ */
+
+#define SAM_GPIO_ODCR0_OFFSET      0x0100 /* Output Driving Capability Register 0 Read/Write */
+#define SAM_GPIO_ODCR0S_OFFSET     0x0104 /* Output Driving Capability Register 0 Set */
+#define SAM_GPIO_ODCR0C_OFFSET     0x0108 /* Output Driving Capability Register 0 Clear */
+#define SAM_GPIO_ODCR0T_OFFSET     0x010c /* Output Driving Capability Register 0 Toggle */
+
+#define SAM_GPIO_ODCR1_OFFSET      0x0110 /* Output Driving Capability Register 1 Read */
+#define SAM_GPIO_ODCR1S_OFFSET     0x0114 /* Output Driving Capability Register 1 Set */
+#define SAM_GPIO_ODCR1C_OFFSET     0x0118 /* Output Driving Capability Register 1 Clear */
+#define SAM_GPIO_ODCR1T_OFFSET     0x011c /* Output Driving Capability Register 1 Toggle */
+
+#define SAM_GPIO_OSRR0_OFFSET      0x0130 /* Output Slew Rate Register 0 Read */
+#define SAM_GPIO_OSRR0S_OFFSET     0x0134 /* Output Slew Rate Register 0 Set */
+#define SAM_GPIO_OSRR0C_OFFSET     0x0138 /* Output Slew Rate Register 0 Clear */
+#define SAM_GPIO_OSRR0T_OFFSET     0x013c /* Output Slew Rate Register 0 Toggle */
+
+#define SAM_GPIO_STER_OFFSET       0x0160 /* Schmitt Trigger Enable Register Read */
+#define SAM_GPIO_STERS_OFFSET      0x0164 /* Schmitt Trigger Enable Register Set */
+#define SAM_GPIO_STERC_OFFSET      0x0168 /* Schmitt Trigger Enable Register Clear */
+#define SAM_GPIO_STERT_OFFSET      0x016c /* Schmitt Trigger Enable Register Toggle */
+
+#define SAM_GPIO_EVER_OFFSET       0x0180 /* Event Enable Register Read */
+#define SAM_GPIO_EVERS_OFFSET      0x0184 /* Event Enable Register Set */
+#define SAM_GPIO_EVERC_OFFSET      0x0188 /* Event Enable Register Clear */
+#define SAM_GPIO_EVERT_OFFSET      0x018c /* Event Enable Register Toggle */
+
+#define SAM_GPIO_PARAMETER_OFFSET  0x01f8 /* Parameter Register Read */
+#define SAM_GPIO_VERSION_OFFSET    0x01fc /* Version Register Read */
+
+/* GPIO register adresses ***************************************************************/
+
+#define SAM_GPIO_GPER              (SAM_GPIO_BASE+SAM_GPIO_GPER_OFFSET)
+#define SAM_GPIO_GPERS             (SAM_GPIO_BASE+SAM_GPIO_GPERS_OFFSET)
+#define SAM_GPIO_GPERC             (SAM_GPIO_BASE+SAM_GPIO_GPERC_OFFSET)
+#define SAM_GPIO_GPERT             (SAM_GPIO_BASE+SAM_GPIO_GPERT_OFFSET)
+
+#define SAM_GPIO_PMR0              (SAM_GPIO_BASE+SAM_GPIO_PMR0_OFFSET)
+#define SAM_GPIO_PMR0S             (SAM_GPIO_BASE+SAM_GPIO_PMR0S_OFFSET)
+#define SAM_GPIO_PMR0C             (SAM_GPIO_BASE+SAM_GPIO_PMR0C_OFFSET)
+#define SAM_GPIO_PMR0T             (SAM_GPIO_BASE+SAM_GPIO_PMR0T_OFFSET_
+
+#define SAM_GPIO_PMR1              (SAM_GPIO_BASE+SAM_GPIO_PMR1_OFFSET)
+#define SAM_GPIO_PMR1S             (SAM_GPIO_BASE+SAM_GPIO_PMR1S_OFFSET)
+#define SAM_GPIO_PMR1C             (SAM_GPIO_BASE+SAM_GPIO_PMR1C_OFFSET)
+#define SAM_GPIO_PMR1T             (SAM_GPIO_BASE+SAM_GPIO_PMR1T_OFFSET)
+
+#define SAM_GPIO_PMR2              (SAM_GPIO_BASE+SAM_GPIO_PMR2_OFFSET)
+#define SAM_GPIO_PMR2S             (SAM_GPIO_BASE+SAM_GPIO_PMR2S_OFFSET)
+#define SAM_GPIO_PMR2C             (SAM_GPIO_BASE+SAM_GPIO_PMR2C_OFFSET)
+#define SAM_GPIO_PMR2T             (SAM_GPIO_BASE+SAM_GPIO_PMR2T_OFFSET)
+
+#define SAM_GPIO_ODER              (SAM_GPIO_BASE+SAM_GPIO_ODER_OFFSET)
+#define SAM_GPIO_ODERS             (SAM_GPIO_BASE+SAM_GPIO_ODERS_OFFSET)
+#define SAM_GPIO_ODERC             (SAM_GPIO_BASE+SAM_GPIO_ODERC_OFFSET)
+#define SAM_GPIO_ODERT             (SAM_GPIO_BASE+SAM_GPIO_ODERT_OFFSET)
+
+#define SAM_GPIO_OVR               (SAM_GPIO_BASE+SAM_GPIO_OVR_OFFSET)
+#define SAM_GPIO_OVRS              (SAM_GPIO_BASE+SAM_GPIO_OVRS_OFFSET)
+#define SAM_GPIO_OVRC              (SAM_GPIO_BASE+SAM_GPIO_OVRC_OFFSET)
+#define SAM_GPIO_OVRT              (SAM_GPIO_BASE+SAM_GPIO_OVRT_OFFSET)
+
+/* Pin Value Register Read (4 registers)*/
+
+#define SAM_GPIO_PVR(n)            (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET(n))
+#define SAM_GPIO_PVR0              (SAM_GPIO_BASE+SAM_GPIO_PVR0_OFFSET)
+#define SAM_GPIO_PVR1              (SAM_GPIO_BASE+SAM_GPIO_PVR1_OFFSET)
+#define SAM_GPIO_PVR2              (SAM_GPIO_BASE+SAM_GPIO_PVR2_OFFSET)
+#define SAM_GPIO_PVR3              (SAM_GPIO_BASE+SAM_GPIO_PVR3_OFFSET)
+
+#define SAM_GPIO_PUER              (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET)
+#define SAM_GPIO_PUERS             (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET)
+#define SAM_GPIO_PUERC             (SAM_GPIO_BASE+SAM_GPIO_PUERC_OFFSET)
+#define SAM_GPIO_PUERT             (SAM_GPIO_BASE+SAM_GPIO_PUERT_OFFSET)
+
+#define SAM_GPIO_PDER              (SAM_GPIO_BASE+SAM_GPIO_PDER_OFFSET)
+#define SAM_GPIO_PDERS             (SAM_GPIO_BASE+SAM_GPIO_PDERS_OFFSET)
+#define SAM_GPIO_PDERC             (SAM_GPIO_BASE+SAM_GPIO_PDERC_OFFSET)
+#define SAM_GPIO_PDERT             (SAM_GPIO_BASE+SAM_GPIO_PDERT_OFFSET)
+
+#define SAM_GPIO_IER               (SAM_GPIO_BASE+SAM_GPIO_IER_OFFSET)
+#define SAM_GPIO_IERS              (SAM_GPIO_BASE+SAM_GPIO_IERS_OFFSET)
+#define SAM_GPIO_IERC              (SAM_GPIO_BASE+SAM_GPIO_IERC_OFFSET)
+#define SAM_GPIO_IERT              (SAM_GPIO_BASE+SAM_GPIO_IERT_OFFSET)
+
+#define SAM_GPIO_IMR0              (SAM_GPIO_BASE+SAM_GPIO_IMR0_OFFSET)
+#define SAM_GPIO_IMR0S             (SAM_GPIO_BASE+SAM_GPIO_IMR0S_OFFSET)
+#define SAM_GPIO_IMR0C             (SAM_GPIO_BASE+SAM_GPIO_IMR0C_OFFSET)
+#define SAM_GPIO_IMR0T             (SAM_GPIO_BASE+SAM_GPIO_IMR0T_OFFSET)
+
+#define SAM_GPIO_IMR1              (SAM_GPIO_BASE+SAM_GPIO_IMR1_OFFSET)
+#define SAM_GPIO_IMR1S             (SAM_GPIO_BASE+SAM_GPIO_IMR1S_OFFSET)
+#define SAM_GPIO_IMR1C             (SAM_GPIO_BASE+SAM_GPIO_IMR1C_OFFSET)
+#define SAM_GPIO_IMR1T             (SAM_GPIO_BASE+SAM_GPIO_IMR1T_OFFSET)
+
+#define SAM_GPIO_GFER              (SAM_GPIO_BASE+SAM_GPIO_GFER_OFFSET)
+#define SAM_GPIO_GFERS             (SAM_GPIO_BASE+SAM_GPIO_GFERS_OFFSET)
+#define SAM_GPIO_GFERC             (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET)
+#define SAM_GPIO_GFERT             (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET)
+
+/* Interrupt Flag Register Read (2 registers)*/
+
+#define SAM_GPIO_IFR(n)            (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET(n))
+#define SAM_GPIO_IFR0              (SAM_GPIO_BASE+SAM_GPIO_IFR0_OFFSET)
+#define SAM_GPIO_IFR1              (SAM_GPIO_BASE+SAM_GPIO_IFR1_OFFSET)
+
+/* Interrupt Flag Register Clear (2 registers)*/
+
+#define SAM_GPIO_IFRC(n)           (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET(n))
+#define SAM_GPIO_IFRC0             (SAM_GPIO_BASE+SAM_GPIO_IFRC0_OFFSET)
+#define SAM_GPIO_IFRC1             (SAM_GPIO_BASE+SAM_GPIO_IFRC1_OFFSET)
+
+#define SAM_GPIO_ODCR0             (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET)
+#define SAM_GPIO_ODCR0S            (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET)
+#define SAM_GPIO_ODCR0C            (SAM_GPIO_BASE+SAM_GPIO_ODCR0C_OFFSET)
+#define SAM_GPIO_ODCR0T            (SAM_GPIO_BASE+SAM_GPIO_ODCR0T_OFFSET)
+
+#define SAM_GPIO_ODCR1             (SAM_GPIO_BASE+SAM_GPIO_ODCR1_OFFSET)
+#define SAM_GPIO_ODCR1S            (SAM_GPIO_BASE+SAM_GPIO_ODCR1S_OFFSET)
+#define SAM_GPIO_ODCR1C            (SAM_GPIO_BASE+SAM_GPIO_ODCR1C_OFFSET)
+#define SAM_GPIO_ODCR1T            (SAM_GPIO_BASE+SAM_GPIO_ODCR1T_OFFSET)
+
+#define SAM_GPIO_OSRR0             (SAM_GPIO_BASE+SAM_GPIO_OSRR0_OFFSET)
+#define SAM_GPIO_OSRR0S            (SAM_GPIO_BASE+SAM_GPIO_OSRR0S_OFFSET)
+#define SAM_GPIO_OSRR0C            (SAM_GPIO_BASE+SAM_GPIO_OSRR0C_OFFSET)
+#define SAM_GPIO_OSRR0T            (SAM_GPIO_BASE+SAM_GPIO_OSRR0T_OFFSET)
+
+#define SAM_GPIO_STER              (SAM_GPIO_BASE+SAM_GPIO_STER_OFFSET)
+#define SAM_GPIO_STERS             (SAM_GPIO_BASE+SAM_GPIO_STERS_OFFSET)
+#define SAM_GPIO_STERC             (SAM_GPIO_BASE+SAM_GPIO_STERC_OFFSET)
+#define SAM_GPIO_STERT             (SAM_GPIO_BASE+SAM_GPIO_STERT_OFFSET)
+
+#define SAM_GPIO_EVER              (SAM_GPIO_BASE+SAM_GPIO_EVER_OFFSET)
+#define SAM_GPIO_EVERS             (SAM_GPIO_BASE+SAM_GPIO_EVERS_OFFSET)
+#define SAM_GPIO_EVERC             (SAM_GPIO_BASE+SAM_GPIO_EVERC_OFFSET)
+#define SAM_GPIO_EVERT             (SAM_GPIO_BASE+SAM_GPIO_EVERT_OFFSET)
+
+#define SAM_GPIO_PARAMETER         (SAM_GPIO_BASE+SAM_GPIO_PARAMETER_OFFSET)
+#define SAM_GPIO_VERSION           (SAM_GPIO_BASE+SAM_GPIO_VERSION_OFFSET)
+
+/* GPIO register bit definitions ********************************************************/
+
+/* Common bit definitions for all GPIO registers */
+
+#define PIN(n)                     (1 << (n)) /* Bit n: PIO n */
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H */
diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h
new file mode 100644
index 000000000..c65d5dcbe
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h
@@ -0,0 +1,399 @@
+/****************************************************************************************
+ * arch/arm/src/sam34/chip/sam4s_pio.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* PIO register offsets *****************************************************************/
+
+#define SAM_PIO_PER_OFFSET         0x0000 /* PIO Enable Register */
+#define SAM_PIO_PDR_OFFSET         0x0004 /* PIO Disable Register */
+#define SAM_PIO_PSR_OFFSET         0x0008 /* PIO Status Register */
+                                          /* 0x000c: Reserved */
+#define SAM_PIO_OER_OFFSET         0x0010 /* Output Enable Register */
+#define SAM_PIO_ODR_OFFSET         0x0014 /* Output Disable Register */
+#define SAM_PIO_OSR_OFFSET         0x0018 /* utput Status Register */
+                                          /* 0x001c: Reserved */
+#define SAM_PIO_IFER_OFFSET        0x0020 /* Glitch Input Filter Enable Register */
+#define SAM_PIO_IFDR_OFFSET        0x0024 /* Glitch Input Filter Disable Register */
+#define SAM_PIO_IFSR_OFFSET        0x0028 /* Glitch Input Filter Status Register */
+                                          /* 0x002c: Reserved */
+#define SAM_PIO_SODR_OFFSET        0x0030 /* Set Output Data Register */
+#define SAM_PIO_CODR_OFFSET        0x0034 /* Clear Output Data Register */
+#define SAM_PIO_ODSR_OFFSET        0x0038 /* Output Data Status Register */
+#define SAM_PIO_PDSR_OFFSET        0x003c /* Pin Data Status Register */
+#define SAM_PIO_IER_OFFSET         0x0040 /* Interrupt Enable Register */
+#define SAM_PIO_IDR_OFFSET         0x0044 /* Interrupt Disable Register */
+#define SAM_PIO_IMR_OFFSET         0x0048 /* Interrupt Mask Register */
+#define SAM_PIO_ISR_OFFSET         0x004c /* Interrupt Status Register */
+#define SAM_PIO_MDER_OFFSET        0x0050 /* Multi-driver Enable Register */
+#define SAM_PIO_MDDR_OFFSET        0x0054 /* Multi-driver Disable Register */
+#define SAM_PIO_MDSR_OFFSET        0x0058 /* Multi-driver Status Register */
+                                          /* 0x005c: Reserved */
+#define SAM_PIO_PUDR_OFFSET        0x0060 /* Pull-up Disable Register */
+#define SAM_PIO_PUER_OFFSET        0x0064 /* Pull-up Enable Register */
+#define SAM_PIO_PUSR_OFFSET        0x0068 /* Pad Pull-up Status Register */
+                                          /* 0x006c: Reserved */
+#define SAM_PIO_ABCDSR1_OFFSET     0x0070 /* Peripheral Select Register 1 */
+#define SAM_PIO_ABCDSR2_OFFSET     0x0074 /* Peripheral Select Register 2 */
+                                          /* 0x0078-0x007c: Reserved */
+#define SAM_PIO_IFSCDR_OFFSET      0x0080 /* SInput Filter Slow Clock Disable Register */
+#define SAM_PIO_IFSCER_OFFSET      0x0084 /* Input Filter Slow Clock Enable Register */
+#define SAM_PIO_IFSCSR_OFFSET      0x0088 /* Input Filter Slow Clock Status Register */
+#define SAM_PIO_SCDR_OFFSET        0x008c /* Slow Clock Divider Debouncing Register */
+#define SAM_PIO_PPDDR_OFFSET       0x0090 /* Pad Pull-down Enable Register */
+#define SAM_PIO_PPDER_OFFSET       0x0094 /* Pad Pull-down Status Register */
+#define SAM_PIO_PPDSR_OFFSET       0x0098 /* Input Filter Slow Clock Disable Register */
+                                          /* 0x009c: Reserved */
+#define SAM_PIO_OWER_OFFSET        0x00a0 /* Output Write Enable */
+#define SAM_PIO_OWDR_OFFSET        0x00a4 /* Output Write Disable */
+#define SAM_PIO_OWSR_OFFSET        0x00a8 /* Output Write Status Register */
+                                          /* 0x00ac: Reserved */
+#define SAM_PIO_AIMER_OFFSET       0x00b0 /* Additional Interrupt Modes Enable Register */
+#define SAM_PIO_AIMDR_OFFSET       0x00b4 /* Additional Interrupt Modes Disables Register */
+#define SAM_PIO_AIMMR_OFFSET       0x00b8 /* Additional Interrupt Modes Mask Register */
+                                          /* 0x00bc: Reserved */
+#define SAM_PIO_ESR_OFFSET         0x00c0 /* Edge Select Register */
+#define SAM_PIO_LSR_OFFSET         0x00c4 /* Level Select Register */
+#define SAM_PIO_ELSR_OFFSET        0x00c8 /* Edge/Level Status Register */
+                                          /* 0x00cc: Reserved */
+#define SAM_PIO_FELLSR_OFFSET      0x00d0 /* Falling Edge/Low Level Select Register */
+#define SAM_PIO_REHLSR_OFFSET      0x00d4 /* Rising Edge/ High Level Select Register */
+#define SAM_PIO_FRLHSR_OFFSET      0x00d8 /* Fall/Rise - Low/High Status Register */
+                                          /* 0x00dc: Reserved */
+#define SAM_PIO_LOCKSR_OFFSET      0x00e0 /* Lock Status */
+#define SAM_PIO_WPMR_OFFSET        0x00e4 /* Write Protect Mode Register */
+#define SAM_PIO_WPSR_OFFSET        0x00e8 /* Write Protect Status Register */
+                                          /* 0x00ec-0x00f8: Reserved */
+#define SAM_PIO_SCHMITT_OFFSET     0x0100 /* Schmitt Trigger Register */
+                                          /* 0x0104-0x14c: Reserved */
+#define SAM_PIO_PCMR_OFFSET        0x0150 /* Parallel Capture Mode Register */
+#define SAM_PIO_PCIER_OFFSET       0x0154 /* Parallel Capture Interrupt Enable Register */
+#define SAM_PIO_PCIDR_OFFSET       0x0158 /* Parallel Capture Interrupt Disable Register */
+#define SAM_PIO_PCIMR_OFFSET       0x015c /* Parallel Capture Interrupt Mask Register */
+#define SAM_PIO_PCISR_OFFSET       0x0160 /* Parallel Capture Interrupt Status Register */
+#define SAM_PIO_PCRHR_OFFSET       0x0164 /* Parallel Capture Reception Holding Register */
+                                          /* 0x0168-0x018c: Reserved for PDC registers */
+
+/* PIO register adresses ****************************************************************/
+
+#define PIOA                       (0)
+#define PIOB                       (1)
+#define PIOC                       (2)
+#define NPIO                       (3)
+
+#define SAM_PIO_PER(n)             (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET)
+#define SAM_PIO_PDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET)
+#define SAM_PIO_PSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET)
+#define SAM_PIO_OER(n)             (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET)
+#define SAM_PIO_ODR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET)
+#define SAM_PIO_OSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET)
+#define SAM_PIO_IFER(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET)
+#define SAM_PIO_IFDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIO_IFSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIO_SODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET)
+#define SAM_PIO_CODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET)
+#define SAM_PIO_ODSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIO_PDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIO_IER(n)             (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET)
+#define SAM_PIO_IDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET)
+#define SAM_PIO_IMR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET)
+#define SAM_PIO_ISR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET)
+#define SAM_PIO_MDER(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET)
+#define SAM_PIO_MDDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIO_MDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIO_PUDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIO_PUER(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET)
+#define SAM_PIO_PUSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIO_ABCDSR1(n)         (SAM_PIO_BASE(n)+SAM_PIO_ABCDSR1_OFFSET)
+#define SAM_PIO_ABCDSR2(n)         (SAM_PIO_BASE(n)+SAM_PIO_ABCDSR2_OFFSET)
+#define SAM_PIO_IFSCDR(n)          (SAM_PIO_BASE(n)+SAM_PIO_IFSCDR_OFFSET)
+#define SAM_PIO_IFSCER(n)          (SAM_PIO_BASE(n)+SAM_PIO_IFSCER_OFFSET)
+#define SAM_PIO_IFSCSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_IFSCSR_OFFSET)
+#define SAM_PIO_SCDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIO_PPDDR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PPDDR_OFFSET)
+#define SAM_PIO_PPDER(n)           (SAM_PIO_BASE(n)+SAM_PIO_PPDER_OFFSET)
+#define SAM_PIO_PPDSR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PPDSR_OFFSET)
+#define SAM_PIO_OWER(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET)
+#define SAM_PIO_OWDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIO_OWSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIO_AIMER(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIO_AIMDR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIO_AIMMR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIO_ESR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET)
+#define SAM_PIO_LSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET)
+#define SAM_PIO_ELSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIO_FELLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIO_REHLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIO_FRLHSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIO_LOCKSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIO_WPMR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIO_WPSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET)
+#define SAM_PIO_SCHMITT(n)         (SAM_PIO_BASE(n)+SAM_PIO_SCHMITT_OFFSET)
+#define SAM_PIO_PCMR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PCMR_OFFSET)
+#define SAM_PIO_PCIER(n)           (SAM_PIO_BASE(n)+SAM_PIO_PCIER_OFFSET)
+#define SAM_PIO_PCIDR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PCIDR_OFFSET)
+#define SAM_PIO_PCIMR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PCIMR_OFFSET)
+#define SAM_PIO_PCISR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PCISR_OFFSET)
+#define SAM_PIO_PCRHR(n)           (SAM_PIO_BASE(n)+SAM_PIO_PCRHR_OFFSET
+
+#define SAM_PIOA_PER               (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOA_PDR               (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOA_PSR               (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOA_OER               (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOA_ODR               (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOA_OSR               (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOA_IFER              (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOA_IFDR              (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOA_IFSR              (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOA_SODR              (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOA_CODR              (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOA_ODSR              (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOA_PDSR              (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOA_IER               (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOA_IDR               (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOA_IMR               (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOA_ISR               (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOA_MDER              (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOA_MDDR              (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOA_MDSR              (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOA_PUDR              (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOA_PUER              (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOA_PUSR              (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOA_ABCDSR1           (SAM_PIOA_BASE+SAM_PIO_ABCDSR1_OFFSET)
+#define SAM_PIOA_ABCDSR2           (SAM_PIOA_BASE+SAM_PIO_ABCDSR2_OFFSET)
+#define SAM_PIOA_IFSCDR            (SAM_PIOA_BASE+SAM_PIO_IFSCDR_OFFSET)
+#define SAM_PIOA_IFSCER            (SAM_PIOA_BASE+SAM_PIO_IFSCER_OFFSET)
+#define SAM_PIOA_IFSCSR            (SAM_PIOA_BASE+SAM_PIO_IFSCSR_OFFSET)
+#define SAM_PIOA_SCDR              (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOA_PPDDR             (SAM_PIOA_BASE+SAM_PIO_PPDDR_OFFSET)
+#define SAM_PIOA_PPDER             (SAM_PIOA_BASE+SAM_PIO_PPDER_OFFSET)
+#define SAM_PIOA_PPDSR             (SAM_PIOA_BASE+SAM_PIO_PPDSR_OFFSET)
+#define SAM_PIOA_OWER              (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOA_OWDR              (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOA_OWSR              (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOA_AIMER             (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOA_AIMDR             (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOA_AIMMR             (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOA_ESR               (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOA_LSR               (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOA_ELSR              (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOA_FELLSR            (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOA_REHLSR            (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOA_FRLHSR            (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOA_LOCKSR            (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOA_WPMR              (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOA_WPSR              (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET)
+#define SAM_PIOA_SCHMITT           (SAM_PIOA_BASE+SAM_PIO_SCHMITT_OFFSET)
+#define SAM_PIOA_PCMR              (SAM_PIOA_BASE+SAM_PIO_PCMR_OFFSET)
+#define SAM_PIOA_PCIER             (SAM_PIOA_BASE+SAM_PIO_PCIER_OFFSET)
+#define SAM_PIOA_PCIDR             (SAM_PIOA_BASE+SAM_PIO_PCIDR_OFFSET)
+#define SAM_PIOA_PCIMR             (SAM_PIOA_BASE+SAM_PIO_PCIMR_OFFSET)
+#define SAM_PIOA_PCISR             (SAM_PIOA_BASE+SAM_PIO_PCISR_OFFSET)
+#define SAM_PIOA_PCRHR             (SAM_PIOA_BASE+SAM_PIO_PCRHR_OFFSET
+
+#define SAM_PIOB_PER               (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOB_PDR               (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOB_PSR               (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOB_OER               (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOB_ODR               (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOB_OSR               (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOB_IFER              (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOB_IFDR              (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOB_IFSR              (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOB_SODR              (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOB_CODR              (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOB_ODSR              (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOB_PDSR              (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOB_IER               (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOB_IDR               (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOB_IMR               (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOB_ISR               (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOB_MDER              (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOB_MDDR              (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOB_MDSR              (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOB_PUDR              (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOB_PUER              (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOB_PUSR              (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOB_ABCDSR1           (SAM_PIOB_BASE+SAM_PIO_ABCDSR1_OFFSET)
+#define SAM_PIOB_ABCDSR2           (SAM_PIOB_BASE+SAM_PIO_ABCDSR2_OFFSET)
+#define SAM_PIOB_IFSCDR            (SAM_PIOB_BASE+SAM_PIO_IFSCDR_OFFSET)
+#define SAM_PIOB_IFSCER            (SAM_PIOB_BASE+SAM_PIO_IFSCER_OFFSET)
+#define SAM_PIOB_IFSCSR            (SAM_PIOB_BASE+SAM_PIO_IFSCSR_OFFSET)
+#define SAM_PIOB_SCDR              (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOB_PPDDR             (SAM_PIOB_BASE+SAM_PIO_PPDDR_OFFSET)
+#define SAM_PIOB_PPDER             (SAM_PIOB_BASE+SAM_PIO_PPDER_OFFSET)
+#define SAM_PIOB_PPDSR             (SAM_PIOB_BASE+SAM_PIO_PPDSR_OFFSET)
+#define SAM_PIOB_OWER              (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOB_OWDR              (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOB_OWSR              (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOB_AIMER             (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOB_AIMDR             (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOB_AIMMR             (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOB_ESR               (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOB_LSR               (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOB_ELSR              (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOB_FELLSR            (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOB_REHLSR            (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOB_FRLHSR            (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOB_LOCKSR            (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOB_WPMR              (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOB_WPSR              (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET)
+#define SAM_PIOB_SCHMITT           (SAM_PIOB_BASE+SAM_PIO_SCHMITT_OFFSET)
+#define SAM_PIOB_PCMR              (SAM_PIOB_BASE+SAM_PIO_PCMR_OFFSET)
+#define SAM_PIOB_PCIER             (SAM_PIOB_BASE+SAM_PIO_PCIER_OFFSET)
+#define SAM_PIOB_PCIDR             (SAM_PIOB_BASE+SAM_PIO_PCIDR_OFFSET)
+#define SAM_PIOB_PCIMR             (SAM_PIOB_BASE+SAM_PIO_PCIMR_OFFSET)
+#define SAM_PIOB_PCISR             (SAM_PIOB_BASE+SAM_PIO_PCISR_OFFSET)
+#define SAM_PIOB_PCRHR             (SAM_PIOB_BASE+SAM_PIO_PCRHR_OFFSET
+
+#define SAM_PIOC_PER               (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET)
+#define SAM_PIOC_PDR               (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET)
+#define SAM_PIOC_PSR               (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET)
+#define SAM_PIOC_OER               (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET)
+#define SAM_PIOC_ODR               (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET)
+#define SAM_PIOC_OSR               (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET)
+#define SAM_PIOC_IFER              (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET)
+#define SAM_PIOC_IFDR              (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET)
+#define SAM_PIOC_IFSR              (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET)
+#define SAM_PIOC_SODR              (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET)
+#define SAM_PIOC_CODR              (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET)
+#define SAM_PIOC_ODSR              (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET)
+#define SAM_PIOC_PDSR              (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET)
+#define SAM_PIOC_IER               (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET)
+#define SAM_PIOC_IDR               (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET)
+#define SAM_PIOC_IMR               (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET)
+#define SAM_PIOC_ISR               (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET)
+#define SAM_PIOC_MDER              (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET)
+#define SAM_PIOC_MDDR              (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET)
+#define SAM_PIOC_MDSR              (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET)
+#define SAM_PIOC_PUDR              (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET)
+#define SAM_PIOC_PUER              (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET)
+#define SAM_PIOC_PUSR              (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET)
+#define SAM_PIOC_ABCDSR1           (SAM_PIOC_BASE+SAM_PIO_ABCDSR1_OFFSET)
+#define SAM_PIOC_ABCDSR2           (SAM_PIOC_BASE+SAM_PIO_ABCDSR2_OFFSET)
+#define SAM_PIOC_IFSCDR            (SAM_PIOC_BASE+SAM_PIO_IFSCDR_OFFSET)
+#define SAM_PIOC_IFSCER            (SAM_PIOC_BASE+SAM_PIO_IFSCER_OFFSET)
+#define SAM_PIOC_IFSCSR            (SAM_PIOC_BASE+SAM_PIO_IFSCSR_OFFSET)
+#define SAM_PIOC_SCDR              (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET)
+#define SAM_PIOC_PPDDR             (SAM_PIOC_BASE+SAM_PIO_PPDDR_OFFSET)
+#define SAM_PIOC_PPDER             (SAM_PIOC_BASE+SAM_PIO_PPDER_OFFSET)
+#define SAM_PIOC_PPDSR             (SAM_PIOC_BASE+SAM_PIO_PPDSR_OFFSET)
+#define SAM_PIOC_OWER              (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET)
+#define SAM_PIOC_OWDR              (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET)
+#define SAM_PIOC_OWSR              (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET)
+#define SAM_PIOC_AIMER             (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET)
+#define SAM_PIOC_AIMDR             (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET)
+#define SAM_PIOC_AIMMR             (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET)
+#define SAM_PIOC_ESR               (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET)
+#define SAM_PIOC_LSR               (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET)
+#define SAM_PIOC_ELSR              (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET)
+#define SAM_PIOC_FELLSR            (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET)
+#define SAM_PIOC_REHLSR            (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET)
+#define SAM_PIOC_FRLHSR            (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET)
+#define SAM_PIOC_LOCKSR            (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET)
+#define SAM_PIOC_WPMR              (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET)
+#define SAM_PIOC_WPSR              (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET)
+#define SAM_PIOC_SCHMITT           (SAM_PIOC_BASE+SAM_PIO_SCHMITT_OFFSET)
+#define SAM_PIOC_PCMR              (SAM_PIOC_BASE+SAM_PIO_PCMR_OFFSET)
+#define SAM_PIOC_PCIER             (SAM_PIOC_BASE+SAM_PIO_PCIER_OFFSET)
+#define SAM_PIOC_PCIDR             (SAM_PIOC_BASE+SAM_PIO_PCIDR_OFFSET)
+#define SAM_PIOC_PCIMR             (SAM_PIOC_BASE+SAM_PIO_PCIMR_OFFSET)
+#define SAM_PIOC_PCISR             (SAM_PIOC_BASE+SAM_PIO_PCISR_OFFSET)
+#define SAM_PIOC_PCRHR             (SAM_PIOC_BASE+SAM_PIO_PCRHR_OFFSET
+
+/* PIO register bit definitions *********************************************************/
+
+/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
+
+#define PIO(n)                     (1 << (n)) /* Bit n: PIO n */
+
+/* PIO Write Protect Mode Register */
+
+#define PIO_WPMR_WPEN              (1 << 0)  /* Bit 0:  Write Protect Enable */
+#define PIO_WPMR_WPKEY_SHIFT       (8)       /* Bits 8-31: Write Protect KEY */
+#define PIO_WPMR_WPKEY_MASK        (0xffffff << PIO_WPMR_WPKEY_SHIFT)
+
+/* PIO Write Protect Status Register */
+
+#define PIO_WPSR_WPVS              (1 << 0)  /* Bit 0:  Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_SHIFT      (8)       /* Bits 8-23: Write Protect Violation Source */
+#define PIO_WPSR_WPVSRC_MASK       (0xffff << PIO_WPSR_WPVSRC_SHIFT)
+
+/* PIO Parallel Capture Mode Register */
+
+#define PIO_PCMR_PCEN              (1 << 0)  /* Bit 0:  Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_SHIFT       (4)       /* Bits 4-5: Parallel Capture Mode Data Size */
+#define PIO_PCMR_DSIZE_MASK        (3 << PIO_PCMR_DSIZE_SHIFT)
+#  define PIO_PCMR_DSIZE_BYTE      (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */
+#  define PIO_PCMR_DSIZE_HWORD     (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */
+#  define PIO_PCMR_DSIZE_WORD      (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */
+#define PIO_PCMR_ALWYS             (1 << 9)  /* Bit 9:  Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS             (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS             (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */
+
+/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */
+
+#define PIOC_PCINT_DRDY            (1 << 0)  /* Bit 0:  Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIOC_PCINT_OVRE            (1 << 1)  /* Bit 1:  Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIOC_PCINT_ENDRX           (1 << 2)  /* Bit 2:  End of Reception Transfer Interrupt Enable */
+#define PIOC_PCINT_RXBUFF          (1 << 3)  /* Bit 3:  Reception Buffer Full Interrupt Enable */
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H */
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pio.h b/nuttx/arch/arm/src/sam34/chip/sam_pio.h
index f6cef564b..e2596475d 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_pio.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_pio.h
@@ -1,7 +1,7 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_pio.h
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -43,272 +43,19 @@
 #include <nuttx/config.h>
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+
+#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  include "chip/sam3u_vectors.h"
+#elif defined(CONFIG_ARCH_CHIP_SAM4S)
+#  include "chip/sam4s_vectors.h"
+#else
+#  error Unrecognized SAM architecture
+#endif
 
 /****************************************************************************************
  * Pre-processor Definitions
  ****************************************************************************************/
 
-/* PIO register offsets *****************************************************************/
-
-#define SAM_PIO_PER_OFFSET         0x0000 /* PIO Enable Register */
-#define SAM_PIO_PDR_OFFSET         0x0004 /* PIO Disable Register */
-#define SAM_PIO_PSR_OFFSET         0x0008 /* PIO Status Register */
-                                          /* 0x000c: Reserved */
-#define SAM_PIO_OER_OFFSET         0x0010 /* Output Enable Register */
-#define SAM_PIO_ODR_OFFSET         0x0014 /* Output Disable Register */
-#define SAM_PIO_OSR_OFFSET         0x0018 /* utput Status Register */
-                                          /* 0x001c: Reserved */
-#define SAM_PIO_IFER_OFFSET        0x0020 /* Glitch Input Filter Enable Register */
-#define SAM_PIO_IFDR_OFFSET        0x0024 /* Glitch Input Filter Disable Register */
-#define SAM_PIO_IFSR_OFFSET        0x0028 /* Glitch Input Filter Status Register */
-                                          /* 0x002c: Reserved */
-#define SAM_PIO_SODR_OFFSET        0x0030 /* Set Output Data Register */
-#define SAM_PIO_CODR_OFFSET        0x0034 /* Clear Output Data Register */
-#define SAM_PIO_ODSR_OFFSET        0x0038 /* Output Data Status Register */
-#define SAM_PIO_PDSR_OFFSET        0x003c /* Pin Data Status Register */
-#define SAM_PIO_IER_OFFSET         0x0040 /* Interrupt Enable Register */
-#define SAM_PIO_IDR_OFFSET         0x0044 /* Interrupt Disable Register */
-#define SAM_PIO_IMR_OFFSET         0x0048 /* Interrupt Mask Register */
-#define SAM_PIO_ISR_OFFSET         0x004c /* Interrupt Status Register */
-#define SAM_PIO_MDER_OFFSET        0x0050 /* Multi-driver Enable Register */
-#define SAM_PIO_MDDR_OFFSET        0x0054 /* Multi-driver Disable Register */
-#define SAM_PIO_MDSR_OFFSET        0x0058 /* Multi-driver Status Register */
-                                          /* 0x005c: Reserved */
-#define SAM_PIO_PUDR_OFFSET        0x0060 /* Pull-up Disable Register */
-#define SAM_PIO_PUER_OFFSET        0x0064 /* Pull-up Enable Register */
-#define SAM_PIO_PUSR_OFFSET        0x0068 /* Pad Pull-up Status Register */
-                                          /* 0x006c: Reserved */
-#define SAM_PIO_ABSR_OFFSET        0x0070 /* Peripheral AB Select Register */
-                                          /* 0x0074-0x007c: Reserved */
-#define SAM_PIO_SCIFSR_OFFSET      0x0080 /* System Clock Glitch Input Filter Select Register */
-#define SAM_PIO_DIFSR_OFFSET       0x0084 /* Debouncing Input Filter Select Register */
-#define SAM_PIO_IFDGSR_OFFSET      0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define SAM_PIO_SCDR_OFFSET        0x008c /* Slow Clock Divider Debouncing Register */
-                                          /* 0x0090-0x009c: Reserved */
-#define SAM_PIO_OWER_OFFSET        0x00a0 /* Output Write Enable */
-#define SAM_PIO_OWDR_OFFSET        0x00a4 /* Output Write Disable */
-#define SAM_PIO_OWSR_OFFSET        0x00a8 /* Output Write Status Register */
-                                          /* 0x00ac: Reserved */
-#define SAM_PIO_AIMER_OFFSET       0x00b0 /* Additional Interrupt Modes Enable Register */
-#define SAM_PIO_AIMDR_OFFSET       0x00b4 /* Additional Interrupt Modes Disables Register */
-#define SAM_PIO_AIMMR_OFFSET       0x00b8 /* Additional Interrupt Modes Mask Register */
-                                          /* 0x00bc: Reserved */
-#define SAM_PIO_ESR_OFFSET         0x00c0 /* Edge Select Register */
-#define SAM_PIO_LSR_OFFSET         0x00c4 /* Level Select Register */
-#define SAM_PIO_ELSR_OFFSET        0x00c8 /* Edge/Level Status Register */
-                                          /* 0x00cc: Reserved */
-#define SAM_PIO_FELLSR_OFFSET      0x00d0 /* Falling Edge/Low Level Select Register */
-#define SAM_PIO_REHLSR_OFFSET      0x00d4 /* Rising Edge/ High Level Select Register */
-#define SAM_PIO_FRLHSR_OFFSET      0x00d8 /* Fall/Rise - Low/High Status Register */
-                                          /* 0x00dc: Reserved */
-#define SAM_PIO_LOCKSR_OFFSET      0x00e0 /* Lock Status */
-#define SAM_PIO_WPMR_OFFSET        0x00e4 /* Write Protect Mode Register */
-#define SAM_PIO_WPSR_OFFSET        0x00e8 /* Write Protect Status Register */
-                                          /* 0x00ec-0x00f8: Reserved */
-                                          /* 0x0100-0x0144: Reserved */
-
-/* PIO register adresses ****************************************************************/
-
-#define PIOA                       (0)
-#define PIOB                       (1)
-#define PIOC                       (2)
-#define NPIO                       (3)
-
-#define SAM_PIO_PER(n)             (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET)
-#define SAM_PIO_PDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET)
-#define SAM_PIO_PSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET)
-#define SAM_PIO_OER(n)             (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET)
-#define SAM_PIO_ODR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET)
-#define SAM_PIO_OSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET)
-#define SAM_PIO_IFER(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET)
-#define SAM_PIO_IFDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET)
-#define SAM_PIO_IFSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET)
-#define SAM_PIO_SODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET)
-#define SAM_PIO_CODR(n)            (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET)
-#define SAM_PIO_ODSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET)
-#define SAM_PIO_PDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET)
-#define SAM_PIO_IER(n)             (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET)
-#define SAM_PIO_IDR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET)
-#define SAM_PIO_IMR(n)             (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET)
-#define SAM_PIO_ISR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET)
-#define SAM_PIO_MDER(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET)
-#define SAM_PIO_MDDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET)
-#define SAM_PIO_MDSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET)
-#define SAM_PIO_PUDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET)
-#define SAM_PIO_PUER(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET)
-#define SAM_PIO_PUSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET)
-#define SAM_PIO_ABSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET)
-#define SAM_PIO_SCIFSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET)
-#define SAM_PIO_DIFSR(n)           (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET)
-#define SAM_PIO_IFDGSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET)
-#define SAM_PIO_SCDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET)
-#define SAM_PIO_OWER(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET)
-#define SAM_PIO_OWDR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET)
-#define SAM_PIO_OWSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET)
-#define SAM_PIO_AIMER(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET)
-#define SAM_PIO_AIMDR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET)
-#define SAM_PIO_AIMMR(n)           (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET)
-#define SAM_PIO_ESR(n)             (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET)
-#define SAM_PIO_LSR(n)             (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET)
-#define SAM_PIO_ELSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET)
-#define SAM_PIO_FELLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET)
-#define SAM_PIO_REHLSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET)
-#define SAM_PIO_FRLHSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET)
-#define SAM_PIO_LOCKSR(n)          (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET)
-#define SAM_PIO_WPMR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET)
-#define SAM_PIO_WPSR(n)            (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET)
-
-#define SAM_PIOA_PER               (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET)
-#define SAM_PIOA_PDR               (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET)
-#define SAM_PIOA_PSR               (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET)
-#define SAM_PIOA_OER               (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET)
-#define SAM_PIOA_ODR               (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET)
-#define SAM_PIOA_OSR               (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET)
-#define SAM_PIOA_IFER              (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET)
-#define SAM_PIOA_IFDR              (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET)
-#define SAM_PIOA_IFSR              (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET)
-#define SAM_PIOA_SODR              (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET)
-#define SAM_PIOA_CODR              (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET)
-#define SAM_PIOA_ODSR              (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET)
-#define SAM_PIOA_PDSR              (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET)
-#define SAM_PIOA_IER               (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET)
-#define SAM_PIOA_IDR               (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET)
-#define SAM_PIOA_IMR               (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET)
-#define SAM_PIOA_ISR               (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET)
-#define SAM_PIOA_MDER              (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET)
-#define SAM_PIOA_MDDR              (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET)
-#define SAM_PIOA_MDSR              (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET)
-#define SAM_PIOA_PUDR              (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET)
-#define SAM_PIOA_PUER              (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET)
-#define SAM_PIOA_PUSR              (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET)
-#define SAM_PIOA_ABSR              (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET)
-#define SAM_PIOA_SCIFSR            (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET)
-#define SAM_PIOA_DIFSR             (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET)
-#define SAM_PIOA_IFDGSR            (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET)
-#define SAM_PIOA_SCDR              (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET)
-#define SAM_PIOA_OWER              (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET)
-#define SAM_PIOA_OWDR              (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET)
-#define SAM_PIOA_OWSR              (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET)
-#define SAM_PIOA_AIMER             (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET)
-#define SAM_PIOA_AIMDR             (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET)
-#define SAM_PIOA_AIMMR             (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET)
-#define SAM_PIOA_ESR               (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET)
-#define SAM_PIOA_LSR               (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET)
-#define SAM_PIOA_ELSR              (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET)
-#define SAM_PIOA_FELLSR            (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET)
-#define SAM_PIOA_REHLSR            (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET)
-#define SAM_PIOA_FRLHSR            (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET)
-#define SAM_PIOA_LOCKSR            (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET)
-#define SAM_PIOA_WPMR              (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET)
-#define SAM_PIOA_WPSR              (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET)
-
-#define SAM_PIOB_PER               (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET)
-#define SAM_PIOB_PDR_              (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET)
-#define SAM_PIOB_PSR               (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET)
-#define SAM_PIOB_OER               (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET)
-#define SAM_PIOB_ODR               (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET)
-#define SAM_PIOB_OSR               (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET)
-#define SAM_PIOB_IFER              (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET)
-#define SAM_PIOB_IFDR              (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET)
-#define SAM_PIOB_IFSR              (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET)
-#define SAM_PIOB_SODR              (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET)
-#define SAM_PIOB_CODR              (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET)
-#define SAM_PIOB_ODSR              (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET)
-#define SAM_PIOB_PDSR              (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET)
-#define SAM_PIOB_IER               (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET)
-#define SAM_PIOB_IDR               (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET)
-#define SAM_PIOB_IMR               (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET)
-#define SAM_PIOB_ISR               (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET)
-#define SAM_PIOB_MDER              (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET)
-#define SAM_PIOB_MDDR              (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET)
-#define SAM_PIOB_MDSR              (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET)
-#define SAM_PIOB_PUDR              (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET)
-#define SAM_PIOB_PUER              (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET)
-#define SAM_PIOB_PUSR              (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET)
-#define SAM_PIOB_ABSR              (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET)
-#define SAM_PIOB_SCIFSR            (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET)
-#define SAM_PIOB_DIFSR             (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET)
-#define SAM_PIOB_IFDGSR            (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET)
-#define SAM_PIOB_SCDR              (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET)
-#define SAM_PIOB_OWER              (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET)
-#define SAM_PIOB_OWDR              (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET)
-#define SAM_PIOB_OWSR              (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET)
-#define SAM_PIOB_AIMER             (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET)
-#define SAM_PIOB_AIMDR             (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET)
-#define SAM_PIOB_AIMMR             (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET)
-#define SAM_PIOB_ESR               (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET)
-#define SAM_PIOB_LSR               (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET)
-#define SAM_PIOB_ELSR              (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET)
-#define SAM_PIOB_FELLSR            (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET)
-#define SAM_PIOB_REHLSR            (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET)
-#define SAM_PIOB_FRLHSR            (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET)
-#define SAM_PIOB_LOCKSR            (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET)
-#define SAM_PIOB_WPMR              (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET)
-#define SAM_PIOB_WPSR              (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET)
-
-#define SAM_PIOC_PER               (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET)
-#define SAM_PIOC_PDR_              (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET)
-#define SAM_PIOC_PSR               (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET)
-#define SAM_PIOC_OER               (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET)
-#define SAM_PIOC_ODR               (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET)
-#define SAM_PIOC_OSR               (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET)
-#define SAM_PIOC_IFER              (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET)
-#define SAM_PIOC_IFDR              (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET)
-#define SAM_PIOC_IFSR              (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET)
-#define SAM_PIOC_SODR              (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET)
-#define SAM_PIOC_CODR              (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET)
-#define SAM_PIOC_ODSR              (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET)
-#define SAM_PIOC_PDSR              (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET)
-#define SAM_PIOC_IER               (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET)
-#define SAM_PIOC_IDR               (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET)
-#define SAM_PIOC_IMR               (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET)
-#define SAM_PIOC_ISR               (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET)
-#define SAM_PIOC_MDER              (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET)
-#define SAM_PIOC_MDDR              (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET)
-#define SAM_PIOC_MDSR              (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET)
-#define SAM_PIOC_PUDR              (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET)
-#define SAM_PIOC_PUER              (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET)
-#define SAM_PIOC_PUSR              (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET)
-#define SAM_PIOC_ABSR              (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET)
-#define SAM_PIOC_SCIFSR            (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET)
-#define SAM_PIOC_DIFSR             (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET)
-#define SAM_PIOC_IFDGSR            (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET)
-#define SAM_PIOC_SCDR              (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET)
-#define SAM_PIOC_OWER              (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET)
-#define SAM_PIOC_OWDR              (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET)
-#define SAM_PIOC_OWSR              (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET)
-#define SAM_PIOC_AIMER             (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET)
-#define SAM_PIOC_AIMDR             (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET)
-#define SAM_PIOC_AIMMR             (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET)
-#define SAM_PIOC_ESR               (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET)
-#define SAM_PIOC_LSR               (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET)
-#define SAM_PIOC_ELSR              (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET)
-#define SAM_PIOC_FELLSR            (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET)
-#define SAM_PIOC_REHLSR            (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET)
-#define SAM_PIOC_FRLHSR            (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET)
-#define SAM_PIOC_LOCKSR            (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET)
-#define SAM_PIOC_WPMR              (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET)
-#define SAM_PIOC_WPSR              (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET)
-
-/* PIO register bit definitions *********************************************************/
-
-/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
-
-#define PIO(n)                     (1<<(n)) /* Bit n: PIO n */
-
-/* PIO Write Protect Mode Register */
-
-#define PIO_WPMR_WPEN              1 << 0)  /* Bit 0:  Write Protect Enable */
-#define PIO_WPMR_WPKEY_SHIFT       8)       /* Bits 8-31: Write Protect KEY */
-#define PIO_WPMR_WPKEY_MASK        0xffffff << PIO_WPMR_WPKEY_SHIFT)
-
-/* PIO Write Protect Status Register */
-
-#define PIO_WPSR_WPVS              1 << 0)  /* Bit 0:  Write Protect Violation Status */
-#define PIO_WPSR_WPVSRC_SHIFT      8)       /* Bits 8-23: Write Protect Violation Source */
-#define PIO_WPSR_WPVSRC_MASK       0xffff << PIO_WPSR_WPVSRC_SHIFT)
-
 /****************************************************************************************
  * Public Types
  ****************************************************************************************/
diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c
index bf765462e..390234b71 100644
--- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c
+++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c
@@ -224,6 +224,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
 #if CONFIG_MM_REGIONS > 1
 void up_addregion(void)
 {
+#if CONFIG_SAM34_SRAM1_SIZE > 0
   /* Allow user access to the heap memory */
 
   sam_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
@@ -232,7 +233,7 @@ void up_addregion(void)
 
   kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
 
-#if CONFIG_MM_REGIONS > 2
+#if CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0
   /* Allow user access to the heap memory */
 
   sam_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
@@ -240,6 +241,8 @@ void up_addregion(void)
   /* Add the region */
 
   kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
-#endif
+
+#endif /* CONFIG_MM_REGIONS > 2 && CONFIG_SAM34_NFCSRAM_SIZE > 0 */
+#endif /* CONFIG_SAM34_SRAM1_SIZE > 0 */
 }
-#endif
+#endif /* CONFIG_MM_REGIONS > 1 */