Add support SAMA5 UART and serial driver

5 files changed, 2044 insertions, 2 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 3636d11ff..a4da756c3 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -5156,4 +5156,7 @@
 	  SAM3U which is very similar but needs to be verified (2013-7-22).
 	* arch/arm/src/sama5/sam_periphclks.h:  Add macros to enable and
 	  disable SAMA5 peripheral clocks (2013-7-22).
+	* arch/arm/src/sama5/sam_lowputc.c and sam_serial.c:  Add support
+	  for SAMA5 UARTs.  Does not even compile as of initial checkin.
+	  (2013-7-22).
 
diff --git a/nuttx/arch/arm/src/sama5/Make.defs b/nuttx/arch/arm/src/sama5/Make.defs
index ddfb66348..78f0dc0a6 100644
--- a/nuttx/arch/arm/src/sama5/Make.defs
+++ b/nuttx/arch/arm/src/sama5/Make.defs
@@ -60,6 +60,7 @@ ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += arm_elf.c
 endif
 
-CHIP_ASRCS =
+CHIP_ASRCS  =
 
-CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_irq.c sam_timerisr.c
+CHIP_CSRCS  = sam_boot.c sam_clockconfig.c sam_irq.c sam_lowputc.c
+CHIP_CSRCS += sam_serial.c sam_timerisr.c
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_uart.h b/nuttx/arch/arm/src/sama5/chip/sam_uart.h
new file mode 100644
index 000000000..b2e781c08
--- /dev/null
+++ b/nuttx/arch/arm/src/sama5/chip/sam_uart.h
@@ -0,0 +1,410 @@
+/************************************************************************************************
+ * arch/arm/src/sam34/chip/sam3u_uart.h
+ * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
+ * Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A and SAM4S
+ *
+ *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H
+
+/************************************************************************************************
+ * Included Files
+ ************************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "chip/sam_memorymap.h"
+
+/************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************/
+
+/* UART register offsets ************************************************************************/
+
+#define SAM_UART_CR_OFFSET           0x0000 /* Control Register (Common) */
+#define SAM_UART_MR_OFFSET           0x0004 /* Mode Register (Common) */
+#define SAM_UART_IER_OFFSET          0x0008 /* Interrupt Enable Register (Common) */
+#define SAM_UART_IDR_OFFSET          0x000c /* Interrupt Disable Register (Common) */
+#define SAM_UART_IMR_OFFSET          0x0010 /* Interrupt Mask Register (Common) */
+#define SAM_UART_SR_OFFSET           0x0014 /* [Channel] Status Register (Common) */
+#define SAM_UART_RHR_OFFSET          0x0018 /* Receive Holding Register (Common) */
+#define SAM_UART_THR_OFFSET          0x001c /* Transmit Holding Register (Common) */
+#define SAM_UART_BRGR_OFFSET         0x0020 /* Baud Rate Generator Register (Common) */
+                                            /* 0x0024-0x003c: Reserved (UART) */
+#define SAM_UART_RTOR_OFFSET         0x0024 /* Receiver Time-out Register (USART only) */
+#define SAM_UART_TTGR_OFFSET         0x0028 /* Transmitter Timeguard Register (USART only) */
+                                            /* 0x002c-0x003c: Reserved (USART) */
+#define SAM_UART_FIDI_OFFSET         0x0040 /* FI DI Ratio Register (USART only) */
+#define SAM_UART_NER_OFFSET          0x0044 /* Number of Errors Register ((USART only) */
+                                            /* 0x0048: Reserved (USART) */
+#define SAM_UART_IFR_OFFSET          0x004c /* IrDA Filter Register (USART only) */
+#define SAM_UART_MAN_OFFSET          0x0050 /* Manchester Encoder Decoder Register (USART only) */
+#define SAM_UART_WPMR_OFFSET         0x00e4 /* Write Protect Mode Register (USART only) */
+#define SAM_UART_WPSR_OFFSET         0x00e8 /* Write Protect Status Register (USART only) */
+                                            /* 0x005c-0xfc: Reserved (USART) */
+
+/* UART register adresses ***********************************************************************/
+
+#define SAM_UART0_CR                 (SAM_UART0_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_UART0_MR                 (SAM_UART0_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_UART0_IER                (SAM_UART0_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_UART0_IDR                (SAM_UART0_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_UART0_IMR                (SAM_UART0_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_UART0_SR                 (SAM_UART0_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_UART0_RHR                (SAM_UART0_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_UART0_THR                (SAM_UART0_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_UART0_BRGR               (SAM_UART0_VBASE+SAM_UART_BRGR_OFFSET)
+
+#define SAM_UART1_CR                 (SAM_UART1_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_UART1_MR                 (SAM_UART1_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_UART1_IER                (SAM_UART1_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_UART1_IDR                (SAM_UART1_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_UART1_IMR                (SAM_UART1_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_UART1_SR                 (SAM_UART1_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_UART1_RHR                (SAM_UART1_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_UART1_THR                (SAM_UART1_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_UART1_BRGR               (SAM_UART1_VBASE+SAM_UART_BRGR_OFFSET)
+
+#define SAM_USART_CR(n)              (SAM_USARTN_VBASE(n)+SAM_UART_CR_OFFSET)
+#define SAM_USART_MR(n)              (SAM_USARTN_VBASE(n)+SAM_UART_MR_OFFSET)
+#define SAM_USART_IER(n)             (SAM_USARTN_VBASE(n)+SAM_UART_IER_OFFSET)
+#define SAM_USART_IDR(n)             (SAM_USARTN_VBASE(n)+SAM_UART_IDR_OFFSET)
+#define SAM_USART_IMR(n)             (SAM_USARTN_VBASE(n)+SAM_UART_IMR_OFFSET)
+#define SAM_USART_SR(n)              (SAM_USARTN_VBASE(n)+SAM_UART_SR_OFFSET)
+#define SAM_USART_RHR(n)             (SAM_USARTN_VBASE(n)+SAM_UART_RHR_OFFSET)
+#define SAM_USART_THR(n)             (SAM_USARTN_VBASE(n)+SAM_UART_THR_OFFSET)
+#define SAM_USART_BRGR(n)            (SAM_USARTN_VBASE(n)+SAM_UART_BRGR_OFFSET)
+#define SAM_USART_RTOR(n)            (SAM_USARTN_VBASE(n)+SAM_UART_RTOR_OFFSET)
+#define SAM_USART_TTGR(n)            (SAM_USARTN_VBASE(n)+SAM_UART_TTGR_OFFSET)
+#define SAM_USART_FIDI(n)            (SAM_USARTN_VBASE(n)+SAM_UART_FIDI_OFFSET)
+#define SAM_USART_NER(n)             (SAM_USARTN_VBASE(n)+SAM_UART_NER_OFFSET)
+#define SAM_USART_IFR(n)             (SAM_USARTN_VBASE(n)+SAM_UART_IFR_OFFSET)
+#define SAM_USART_MAN(n)             (SAM_USARTN_VBASE(n)+SAM_UART_MAN_OFFSET)
+#define SAM_USART_WPMR(n)            (SAM_USARTN_VBASE(n)+SAM_UART_WPMR_OFFSET)
+#define SAM_USART_WPSR(n)            (SAM_USARTN_VBASE(n)+SAM_UART_WPSR_OFFSET)
+
+#define SAM_USART0_CR                (SAM_USART0_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_USART0_MR                (SAM_USART0_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_USART0_IER               (SAM_USART0_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_USART0_IDR               (SAM_USART0_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_USART0_IMR               (SAM_USART0_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_USART0_SR                (SAM_USART0_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_USART0_RHR               (SAM_USART0_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_USART0_THR               (SAM_USART0_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_USART0_BRGR              (SAM_USART0_VBASE+SAM_UART_BRGR_OFFSET)
+#define SAM_USART0_RTOR              (SAM_USART0_VBASE+SAM_UART_RTOR_OFFSET)
+#define SAM_USART0_TTGR              (SAM_USART0_VBASE+SAM_UART_TTGR_OFFSET)
+#define SAM_USART0_FIDI              (SAM_USART0_VBASE+SAM_UART_FIDI_OFFSET)
+#define SAM_USART0_NER               (SAM_USART0_VBASE+SAM_UART_NER_OFFSET)
+#define SAM_USART0_IFR               (SAM_USART0_VBASE+SAM_UART_IFR_OFFSET)
+#define SAM_USART0_MAN               (SAM_USART0_VBASE+SAM_UART_MAN_OFFSET)
+#define SAM_USART0_WPMR              (SAM_USART0_VBASE+SAM_UART_WPMR_OFFSET)
+#define SAM_USART0_WPSR              (SAM_USART0_VBASE+SAM_UART_WPSR_OFFSET)
+
+#define SAM_USART1_CR                (SAM_USART1_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_USART1_MR                (SAM_USART1_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_USART1_IER               (SAM_USART1_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_USART1_IDR               (SAM_USART1_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_USART1_IMR               (SAM_USART1_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_USART1_SR                (SAM_USART1_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_USART1_RHR               (SAM_USART1_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_USART1_THR               (SAM_USART1_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_USART1_BRGR              (SAM_USART1_VBASE+SAM_UART_BRGR_OFFSET)
+#define SAM_USART1_RTOR              (SAM_USART1_VBASE+SAM_UART_RTOR_OFFSET)
+#define SAM_USART1_TTGR              (SAM_USART1_VBASE+SAM_UART_TTGR_OFFSET)
+#define SAM_USART1_FIDI              (SAM_USART1_VBASE+SAM_UART_FIDI_OFFSET)
+#define SAM_USART1_NER               (SAM_USART1_VBASE+SAM_UART_NER_OFFSET)
+#define SAM_USART1_IFR               (SAM_USART1_VBASE+SAM_UART_IFR_OFFSET)
+#define SAM_USART1_MAN               (SAM_USART1_VBASE+SAM_UART_MAN_OFFSET)
+#define SAM_USART1_WPMR              (SAM_USART1_VBASE+SAM_UART_WPMR_OFFSET)
+#define SAM_USART1_WPSR              (SAM_USART1_VBASE+SAM_UART_WPSR_OFFSET)
+
+#define SAM_USART2_CR                (SAM_USART2_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_USART2_MR                (SAM_USART2_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_USART2_IER               (SAM_USART2_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_USART2_IDR               (SAM_USART2_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_USART2_IMR               (SAM_USART2_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_USART2_SR                (SAM_USART2_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_USART2_RHR               (SAM_USART2_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_USART2_THR               (SAM_USART2_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_USART2_BRGR              (SAM_USART2_VBASE+SAM_UART_BRGR_OFFSET)
+#define SAM_USART2_RTOR              (SAM_USART2_VBASE+SAM_UART_RTOR_OFFSET)
+#define SAM_USART2_TTGR              (SAM_USART2_VBASE+SAM_UART_TTGR_OFFSET)
+#define SAM_USART2_FIDI              (SAM_USART2_VBASE+SAM_UART_FIDI_OFFSET)
+#define SAM_USART2_NER               (SAM_USART2_VBASE+SAM_UART_NER_OFFSET)
+#define SAM_USART2_IFR               (SAM_USART2_VBASE+SAM_UART_IFR_OFFSET)
+#define SAM_USART2_MAN               (SAM_USART2_VBASE+SAM_UART_MAN_OFFSET)
+#define SAM_USART2_WPMR              (SAM_USART2_VBASE+SAM_UART_WPMR_OFFSET)
+#define SAM_USART2_WPSR              (SAM_USART2_VBASE+SAM_UART_WPSR_OFFSET)
+
+#define SAM_USART3_CR                (SAM_USART3_VBASE+SAM_UART_CR_OFFSET)
+#define SAM_USART3_MR                (SAM_USART3_VBASE+SAM_UART_MR_OFFSET)
+#define SAM_USART3_IER               (SAM_USART3_VBASE+SAM_UART_IER_OFFSET)
+#define SAM_USART3_IDR               (SAM_USART3_VBASE+SAM_UART_IDR_OFFSET)
+#define SAM_USART3_IMR               (SAM_USART3_VBASE+SAM_UART_IMR_OFFSET)
+#define SAM_USART3_SR                (SAM_USART3_VBASE+SAM_UART_SR_OFFSET)
+#define SAM_USART3_RHR               (SAM_USART3_VBASE+SAM_UART_RHR_OFFSET)
+#define SAM_USART3_THR               (SAM_USART3_VBASE+SAM_UART_THR_OFFSET)
+#define SAM_USART3_BRGR              (SAM_USART3_VBASE+SAM_UART_BRGR_OFFSET)
+#define SAM_USART3_RTOR              (SAM_USART3_VBASE+SAM_UART_RTOR_OFFSET)
+#define SAM_USART3_TTGR              (SAM_USART3_VBASE+SAM_UART_TTGR_OFFSET)
+#define SAM_USART3_FIDI              (SAM_USART3_VBASE+SAM_UART_FIDI_OFFSET)
+#define SAM_USART3_NER               (SAM_USART3_VBASE+SAM_UART_NER_OFFSET)
+#define SAM_USART3_IFR               (SAM_USART3_VBASE+SAM_UART_IFR_OFFSET)
+#define SAM_USART3_MAN               (SAM_USART3_VBASE+SAM_UART_MAN_OFFSET)
+#define SAM_USART3_WPMR              (SAM_USART3_VBASE+SAM_UART_WPMR_OFFSET)
+#define SAM_USART3_WPSR              (SAM_USART3_VBASE+SAM_UART_WPSR_OFFSET)
+
+/* UART register bit definitions ****************************************************************/
+
+/* UART Control Register */
+
+#define UART_CR_RSTRX                (1 << 2)  /* Bit 2:  Reset Receiver (Common) */
+#define UART_CR_RSTTX                (1 << 3)  /* Bit 3:  Reset Transmitter (Common) */
+#define UART_CR_RXEN                 (1 << 4)  /* Bit 4:  Receiver Enable (Common) */
+#define UART_CR_RXDIS                (1 << 5)  /* Bit 5:  Receiver Disable (Common) */
+#define UART_CR_TXEN                 (1 << 6)  /* Bit 6:  Transmitter Enable (Common) */
+#define UART_CR_TXDIS                (1 << 7)  /* Bit 7:  Transmitter Disable (Common) */
+#define UART_CR_RSTSTA               (1 << 8)  /* Bit 8:  Reset Status Bits (Common) */
+#define UART_CR_STTBRK               (1 << 9)  /* Bit 9:  Start Break (USART UART mode only) */
+#define UART_CR_STPBRK               (1 << 10) /* Bit 10: Stop Break (USART UART mode only) */
+#define UART_CR_STTTO                (1 << 11) /* Bit 11: Start Time-out (USART oUART mode nly) */
+#define UART_CR_SENDA                (1 << 12) /* Bit 12: Send Address (USART UART mode only) */
+#define UART_CR_RSTIT                (1 << 13) /* Bit 13: Reset Iterations (USART UART mode only) */
+#define UART_CR_RSTNACK              (1 << 14) /* Bit 14: Reset Non Acknowledge (USART UART mode only) */
+#define UART_CR_RETTO                (1 << 15) /* Bit 15: Rearm Time-out (USART UART mode only) */
+#define UART_CR_RTSEN                (1 << 18) /* Bit 18: Request to Send Enable (USART UART mode only) */
+#define UART_CR_FCS                  (1 << 18) /* Bit 18: Force SPI Chip Select (USART SPI mode only) */
+#define UART_CR_RTSDIS               (1 << 19) /* Bit 19: Request to Send Disable (USART UART mode only) */
+#define UART_CR_RCS                  (1 << 19) /* Bit 19: Release SPI Chip Select (USART SPI mode only) */
+
+/* UART Mode Register and USART Mode Register (UART MODE)
+ *
+ * NOTES:
+ * (1) Common to UART and USART (all modes)
+ * (2) Common to UART and USART (UART mode only)
+ * (3) USART only (all modes)
+ * (4) USART only (UART mode only)
+ * (5) USART only (SPI mode only)
+ */
+
+#define UART_MR_MODE_SHIFT           (0)       /* Bits 0-3: (3) */
+#define UART_MR_MODE_MASK            (15 << UART_MR_MODE_SHIFT)
+#  define UART_MR_MODE_NORMAL        (0  << UART_MR_MODE_SHIFT) /* Normal */
+#  define UART_MR_MODE_RS485         (1  << UART_MR_MODE_SHIFT) /* RS485 */
+#  define UART_MR_MODE_HWHS          (2  << UART_MR_MODE_SHIFT) /* Hardware Handshaking */
+#  define UART_MR_MODE_ISO7816_0     (4  << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */
+#  define UART_MR_MODE_ISO7816_1     (6  << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */
+#  define UART_MR_MODE_IRDA          (8  << UART_MR_MODE_SHIFT) /* IrDA */
+#  define UART_MR_MODE_SPIMSTR       (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */
+#  define UART_MR_MODE_SPISLV        (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */
+#define UART_MR_USCLKS_SHIFT         (4)       /* Bits 4-5: Clock Selection (3) */
+#define UART_MR_USCLKS_MASK          (3 << UART_MR_USCLKS_SHIFT)
+#  define UART_MR_USCLKS_MCK         (0 << UART_MR_USCLKS_SHIFT) /* MCK */
+#  define UART_MR_USCLKS_MCKDIV      (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */
+#  define UART_MR_USCLKS_SCK         (3 << UART_MR_USCLKS_SHIFT) /* SCK */
+#define UART_MR_CHRL_SHIFT           (6)       /* Bits 6-7: Character Length (3) */
+#define UART_MR_CHRL_MASK            (3 << UART_MR_CHRL_SHIFT)
+#  define UART_MR_CHRL_5BITS         (0 << UART_MR_CHRL_SHIFT) /* 5 bits */
+#  define UART_MR_CHRL_6BITS         (1 << UART_MR_CHRL_SHIFT) /* 6 bits */
+#  define UART_MR_CHRL_7BITS         (2 << UART_MR_CHRL_SHIFT) /* 7 bits */
+#  define UART_MR_CHRL_8BITS         (3 << UART_MR_CHRL_SHIFT) /* 8 bits */
+#define UART_MR_SYNC                 (1 << 8)  /* Bit 8: Synchronous Mode Select (4) */
+#define UART_MR_CPHA                 (1 << 8)  /* Bit 8: SPI Clock Phase (5) */
+#define UART_MR_PAR_SHIFT            (9)       /* Bits 9-11: Parity Type (2) */
+#define UART_MR_PAR_MASK             (7 << UART_MR_PAR_SHIFT)
+#  define UART_MR_PAR_EVEN           (0 << UART_MR_PAR_SHIFT) /* Even parity (1) */
+#  define UART_MR_PAR_ODD            (1 << UART_MR_PAR_SHIFT) /* Odd parity (1) */
+#  define UART_MR_PAR_SPACE          (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (1) */
+#  define UART_MR_PAR_MARK           (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (1) */
+#  define UART_MR_PAR_NONE           (4 << UART_MR_PAR_SHIFT) /* No parity (1) */
+#  define UART_MR_PAR_MULTIDROP      (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (2) */
+#define UART_MR_NBSTOP_SHIFT         (12)      /* Bits 12-13: Number of Stop Bits (2) */
+#define UART_MR_NBSTOP_MASK          (3 << UART_MR_NBSTOP_SHIFT)
+#  define UART_MR_NBSTOP_1           (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
+#  define UART_MR_NBSTOP_1p5         (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
+#  define UART_MR_NBSTOP_2           (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
+#define UART_MR_CHMODE_SHIFT         (14)      /* Bits 14-15: Channel Mode (2) */
+#define UART_MR_CHMODE_MASK          (3 << UART_MR_CHMODE_SHIFT)
+#  define UART_MR_CHMODE_NORMAL      (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
+#  define UART_MR_CHMODE_ECHO        (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */
+#  define UART_MR_CHMODE_LLPBK       (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */
+#  define UART_MR_CHMODE_RLPBK       (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */
+#define UART_MR_MSBF                 (1 << 16) /* Bit 16: Most Significant Bit first (2) */
+#define UART_MR_CPOL                 (1 << 16) /* Bit 16: SPI Clock Polarity (5) */
+#define UART_MR_MODE9                (1 << 17) /* Bit 17: 9-bit Character Length (4) */
+#define UART_MR_CLKO                 (1 << 18) /* Bit 18: Clock Output Select (4) */
+#define UART_MR_OVER                 (1 << 19) /* Bit 19: Oversampling Mode (4) */
+#define UART_MR_INACK                (1 << 20) /* Bit 20: Inhibit Non Acknowledge (4) */
+#define UART_MR_WRDBT                (1 << 20) /* Bit 20: Wait Read Data Before Transfer (5) */
+#define UART_MR_DSNACK               (1 << 21) /* Bit 21: Disable Successive NACK (4) */
+#define UART_MR_VARSYNC              (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (4) */
+#define UART_MR_INVDATA              (1 << 23) /* Bit 23: Inverted Data (4) */
+#define UART_MR_MAXITER_SHIFT        (24)      /* Bits 24-26: Max iterations (ISO7816 T=0 (4) */
+#define UART_MR_MAXITER_MASK         (7 << UART_MR_MAXITER_SHIFT)
+#define UART_MR_FILTER               (1 << 28) /* Bit 28: Infrared Receive Line Filter (4) */
+#define UART_MR_MAN                  (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable () */
+#define UART_MR_MODSYNC              (1 << 30) /* Bit 30: Manchester Synchronization Mode (4) */
+#define UART_MR_ONEBIT               (1 << 31) /* Bit 31: Start Frame Delimiter Selector (4) */
+
+/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask
+ * Register, and UART Status Register common bit field definitions
+ *
+ * NOTES:
+ * (1) Common to UART and USART (all modes)
+ * (2) Common to UART and USART (UART mode only)
+ * (3) USART only (all modes)
+ * (4) USART only (UART mode only)
+ * (5) USART only (SPI mode only)
+ */
+
+#define UART_INT_RXRDY               (1 << 0)  /* Bit 0:  RXRDY Interrupt (1) */
+#define UART_INT_TXRDY               (1 << 1)  /* Bit 1:  TXRDY Interrupt (1) */
+#define UART_INT_RXBRK               (1 << 2)  /* Bit 2:  Break Received/End of Break (2) */
+#define UART_INT_OVRE                (1 << 5)  /* Bit 5:  Overrun Error Interrupt (2) */
+#define UART_INT_FRAME               (1 << 6)  /* Bit 6:  Framing Error Interrupt (2) */
+#define UART_INT_PARE                (1 << 7)  /* Bit 7:  Parity Error Interrupt (2) */
+#define UART_INT_TIMEOUT             (1 << 8)  /* Bit 8:  Time-out Interrupt (4) */
+#define UART_INT_TXEMPTY             (1 << 9)  /* Bit 9:  TXEMPTY Interrupt (1) */
+#define UART_INT_ITER                (1 << 10) /* Bit 10: Iteration Interrupt (4) */
+#define UART_INT_UNRE                (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (5) */
+#define UART_INT_NACK                (1 << 13) /* Bit 13: Non Acknowledge Interrupt (4) */
+#define UART_INT_CTSIC               (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (4) */
+#define UART_SR_CTS                  (1 << 23) /* Bit 23: Image of CTS Input (SR only) */
+#define UART_INT_MANE                (1 << 24) /* Bit 24: Manchester Error Interrupt (4) */
+
+#define UART_INT_ALLINTS              0x018827e7
+
+/* UART Receiver Holding Register */
+
+#if 0
+#  define UART_RHR_RXCHR_SHIFT       (0)       /* Bits 0-7: Received Character (UART only) */
+#  define UART_RHR_RXCHR_MASK        (0xff << UART_RHR_RXCHR_SHIFT)
+#endif
+#define UART_RHR_RXCHR_SHIFT         (0)       /* Bits 0-8: Received Character (USART only) */
+#define UART_RHR_RXCHR_MASK          (0x1ff << UART_RHR_RXCHR_SHIFT)
+#define UART_RHR_RXSYNH              (1 << 15) /* Bit 15: Received Sync (USART only) */
+
+/* UART Transmit Holding Register */
+
+#if 0
+#  define UART_THR_TXCHR_SHIFT       (0)       /* Bits 0-7: Character to be Transmitted (UART only) */
+#  define UART_THR_TXCHR_MASK        (0xff << UART_THR_TXCHR_SHIFT)
+#endif
+#define UART_THR_TXCHR_SHIFT         (0)       /* Bits 0-8: Character to be Transmitted (USART only) */
+#define UART_THR_TXCHR_MASK          (0x1ff << UART_THR_TXCHR_SHIFT)
+#define UART_THR_TXSYNH              (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */
+
+/* UART Baud Rate Generator Register */
+
+#define UART_BRGR_CD_SHIFT           (0)      /* Bits 0-15: Clock Divisor (Common) */
+#define UART_BRGR_CD_MASK            (0xffff << UART_BRGR_CD_SHIFT)
+#define UART_BRGR_FP_SHIFT           (16)      /* Bits 16-18: Fractional Part (USART only) */
+#define UART_BRGR_FP_MASK            (7 << UART_BRGR_FP_SHIFT)
+
+/* USART Receiver Time-out Register (USART only) */
+
+#define UART_RTOR_TO_SHIFT           (0)       /* Bits 0-15: Time-out Value (USART only) */
+#define UART_RTOR_TO_MASK            (0xffff << UART_RTOR_TO_SHIFT)
+
+/* USART Transmitter Timeguard Register (USART only) */
+
+#define UART_TTGR_TG_SHIFT           (0)       /* Bits 0-7: Timeguard Value (USART only) */
+#define UART_TTGR_TG_MASK            (0xff << UART_TTGR_TG_SHIFT)
+
+/* USART FI DI RATIO Register (USART only) */
+
+#define UART_FIDI_RATIO_SHIFT        (0)       /* Bits 0-15: FI Over DI Ratio Value (USART only) */
+#define UART_FIDI_RATIO_MASK         (0xffff << UART_FIDI_RATIO_SHIFT)
+
+/* USART Number of Errors Register (USART only) */
+
+#define UART_NER_NBERRORS_SHIFT      (0)       /* Bits 0-7: Number of Errrors (USART only) */
+#define UART_NER_NBERRORS_MASK       (0xff << UART_NER_NBERRORS_SHIFT)
+
+/* USART IrDA FILTER Register (USART only) */
+
+#define UART_IFR_IRDAFILTER_SHIFT    (0)       /* Bits 0-7: IrDA Filter (USART only) */
+#define UART_IFR_IRDAFILTER_MASK     (0xff << UART_IFR_IRDAFILTER_SHIFT)
+
+/* USART Manchester Configuration Register (USART only) */
+
+#define UART_MAN_TXPL_SHIFT          (0)       /* Bits 0-3: Transmitter Preamble Length (USART only) */
+#define UART_MAN_TXPL_MASK           (15 << UART_MAN_TXPL_SHIFT)
+#define UART_MAN_TXPP_SHIFT          (8)       /* Bits 8-9: Transmitter Preamble Pattern (USART only) */
+#define UART_MAN_TXPP_MASK           (3 << UART_MAN_TXPP_SHIFT)
+#  define UART_MAN_TXPP_ALLONE       (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */
+#  define UART_MAN_TXPP_ALLZERO      (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */
+#  define UART_MAN_TXPP_ZEROONE      (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */
+#  define UART_MAN_TXPP_ONEZERO      (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */
+#define UART_MAN_TXMPOL              (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */
+#define UART_MAN_RXPL_SHIFT          (16)      /* Bits 16-19: Receiver Preamble Length (USART only) */
+#define UART_MAN_RXPL_MASK           (15 << UART_MAN_RXPL_SHIFT)
+#define UART_MAN_RXPP_SHIFT          (24)      /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */
+#define UART_MAN_RXPP_MASK           (3 << UART_MAN_RXPP_SHIFT)
+#  define UART_MAN_RXPP_ALLONE       (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */
+#  define UART_MAN_RXPP_ALLZERO      (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */
+#  define UART_MAN_RXPP_ZEROONE      (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */
+#  define UART_MAN_RXPP_ONEZERO      (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */
+#define UART_MAN_RXMPOL              (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */
+#define UART_MAN_ONE                 (1 << 29) /* Bit 29: Must Be Set to 1 */
+#define UART_MAN_DRIFT               (1 << 30) /* Bit 30: Drift compensation (USART only) */
+
+/* USART Write Protect Mode Register (USART only) */
+
+#define UART_WPMR_WPEN               (1 << 0)  /* Bit 0: Write Protect Enable (USART only) */
+#define UART_WPMR_WPKEY_SHIFT        (8)       /* Bits 8-31: Write Protect KEY (USART only) */
+#define UART_WPMR_WPKEY_MASK         (0x00ffffff << UART_WPMR_WPKEY_SHIFT)
+#  define UART_WPMR_WPKEY            (0x00555341 << UART_WPMR_WPKEY_SHIFT)
+
+/* USART Write Protect Status Register (USART only) */
+
+#define UART_WPSR_WPVS               (1 << 0)  /* Bit 0: Write Protect Violation Status (USART only) */
+#define UART_WPSR_WPVSRC_SHIFT       (8)       /* Bits 8-23: Write Protect Violation Source (USART only) */
+#define UART_WPSR_WPVSRC_MASK        (0xffff << UART_WPSR_WPVSRC_SHIFT)
+
+/************************************************************************************************
+ * Public Types
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Data
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Functions
+ ************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H */
diff --git a/nuttx/arch/arm/src/sama5/sam_lowputc.c b/nuttx/arch/arm/src/sama5/sam_lowputc.c
new file mode 100644
index 000000000..25673b5e4
--- /dev/null
+++ b/nuttx/arch/arm/src/sama5/sam_lowputc.c
@@ -0,0 +1,377 @@
+/**************************************************************************
+ * arch/arm/src/sama5/sam_lowputc.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "sam_gpio.h"
+#include "sam_periphclks.h"
+#include "sam_lowputc.h"
+
+#include "chip/sam_uart.h"
+#include "chip/sam_pinmap.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+/* If the USART is not being used as a UART, then it really isn't enabled
+ * for our purposes.
+ */
+
+#ifndef CONFIG_USART0_ISUART
+#  undef CONFIG_SAMA5_USART0
+#endif
+#ifndef CONFIG_USART1_ISUART
+#  undef CONFIG_SAMA5_USART1
+#endif
+#ifndef CONFIG_USART2_ISUART
+#  undef CONFIG_SAMA5_USART2
+#endif
+#ifndef CONFIG_USART3_ISUART
+#  undef CONFIG_SAMA5_USART3
+#endif
+
+/* Is there a serial console?  It could be on UART0-1 or USART0-3 */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_USART0)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_USART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_USART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_USART3)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* The UART/USART modules are driven by the main clock (MCK). */
+
+#define SAM_USART_CLOCK  BOARD_MCK_FREQUENCY  /* Frequency of the main clock */
+#define SAM_MR_USCLKS    UART_MR_USCLKS_MCK   /* Source = Main clock */
+
+/* Select USART parameters for the selected console */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_UART0_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_UART0_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_UART1_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_UART1_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_USART0_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_USART0_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_USART0_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_USART0_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_USART0_2STOP
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_USART1_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_USART1_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_USART1_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_USART1_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_USART1_2STOP
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_USART2_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_USART2_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_USART2_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_USART2_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_USART2_2STOP
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#  define SAM_CONSOLE_BASE     SAM_USART3_BASE
+#  define SAM_CONSOLE_BAUD     CONFIG_USART3_BAUD
+#  define SAM_CONSOLE_BITS     CONFIG_USART3_BITS
+#  define SAM_CONSOLE_PARITY   CONFIG_USART3_PARITY
+#  define SAM_CONSOLE_2STOP    CONFIG_USART3_2STOP
+#else
+#  error "No CONFIG_U[S]ARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Select the settings for the mode register */
+
+#if SAM_CONSOLE_BITS == 5
+#  define MR_CHRL_VALUE UART_MR_CHRL_5BITS /* 5 bits */
+#elif SAM_CONSOLE_BITS == 6
+#  define MR_CHRL_VALUE UART_MR_CHRL_6BITS  /* 6 bits */
+#elif SAM_CONSOLE_BITS == 7
+#  define MR_CHRL_VALUE UART_MR_CHRL_7BITS /* 7 bits */
+#elif SAM_CONSOLE_BITS == 8
+#  define MR_CHRL_VALUE UART_MR_CHRL_8BITS /* 8 bits */
+#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART0_SERIAL_CONSOLE) && \
+     !defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define MR_CHRL_VALUE UART_MR_MODE9
+#else
+#  error "Invlaid number of bits"
+#endif
+
+#if SAM_CONSOLE_PARITY == 1
+#  define MR_PAR_VALUE UART_MR_PAR_ODD
+#elif SAM_CONSOLE_PARITY == 2
+#  define MR_PAR_VALUE UART_MR_PAR_EVEN
+#else
+#  define MR_PAR_VALUE UART_MR_PAR_NONE
+#endif
+
+#if SAM_CONSOLE_2STOP != 0
+#  define MR_NBSTOP_VALUE UART_MR_NBSTOP_2
+#else
+#  define MR_NBSTOP_VALUE UART_MR_NBSTOP_1
+#endif
+
+#define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \
+                  MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+  /* Wait for the transmitter to be available */
+
+  while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
+
+  /* Send the character */
+
+  putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
+}
+
+/**************************************************************************
+ * Name: sam_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the USART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void sam_lowsetup(void)
+{
+  /* Enable clocking for all selected UART/USARTs */
+
+#ifdef CONFIG_SAMA5_UART0
+  sam_uart0_enableclk();
+#endif
+#ifdef CONFIG_SAMA5_UART1
+  sam_uart1_enableclk();
+#endif
+#ifdef CONFIG_SAMA5_USART0
+  sam_usart0_enableclk();
+#endif
+#ifdef CONFIG_SAMA5_USART1
+  sam_usart1_enableclk();
+#endif
+#ifdef CONFIG_SAMA5_USART2
+  sam_usart2_enableclk();
+#endif
+#ifdef CONFIG_SAMA5_USART3
+  sam_usart3_enableclk();
+#endif
+
+  /* Configure UART pins for all selected UART/USARTs */
+
+#ifdef CONFIG_SAMA5_UART0
+  (void)sam_configgpio(GPIO_UART0_RXD);
+  (void)sam_configgpio(GPIO_UART0_TXD);
+#endif
+
+#ifdef CONFIG_SAMA5_UART1
+  (void)sam_configgpio(GPIO_UART1_RXD);
+  (void)sam_configgpio(GPIO_UART1_TXD);
+#endif
+
+#ifdef CONFIG_SAMA5_USART0
+  (void)sam_configgpio(GPIO_USART0_RXD);
+  (void)sam_configgpio(GPIO_USART0_TXD);
+#ifdef CONFIG_USART0_OFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART0_CTS);
+#endif
+#ifdef CONFIG_USART0_IFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART0_RTS);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_USART1
+  (void)sam_configgpio(GPIO_USART1_RXD);
+  (void)sam_configgpio(GPIO_USART1_TXD);
+#ifdef CONFIG_USART1_OFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART1_CTS);
+#endif
+#ifdef CONFIG_USART1_IFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART1_RTS);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_USART2
+  (void)sam_configgpio(GPIO_USART2_RXD);
+  (void)sam_configgpio(GPIO_USART2_TXD);
+#ifdef CONFIG_USART2_OFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART2_CTS);
+#endif
+#ifdef CONFIG_USART2_IFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART2_RTS);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_USART3
+  (void)sam_configgpio(GPIO_USART3_RXD);
+  (void)sam_configgpio(GPIO_USART3_TXD);
+#ifdef CONFIG_USART3_OFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART3_CTS);
+#endif
+#ifdef CONFIG_USART3_IFLOWCONTROL
+  (void)sam_configgpio(GPIO_USART3_RTS);
+#endif
+#endif
+
+  /* Configure the console (only) */
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  /* Reset and disable receiver and transmitter */
+
+  putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
+           SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
+
+  /* Disable all interrupts */
+
+  putreg32(0xffffffff, SAM_CONSOLE_BASE + SAM_UART_IDR_OFFSET);
+
+  /* Set up the mode register */
+
+  putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET);
+
+  /* Configure the console baud.  NOTE: Oversampling by 8 is not supported.
+   * This may limit BAUD rates for lower USART clocks.
+   */
+
+  putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
+           SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
+
+  /* Enable receiver & transmitter */
+
+  putreg32((UART_CR_RXEN | UART_CR_TXEN),
+           SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
+#endif
+}
+
+
diff --git a/nuttx/arch/arm/src/sama5/sam_serial.c b/nuttx/arch/arm/src/sama5/sam_serial.c
new file mode 100644
index 000000000..047cda656
--- /dev/null
+++ b/nuttx/arch/arm/src/sama5/sam_serial.c
@@ -0,0 +1,1251 @@
+/****************************************************************************
+ * arch/arm/src/sama5/sam_serial.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/serial.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+#include "chip.h"
+#include "chip/sam_uart.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Some sanity checks *******************************************************/
+
+/* If the USART is not being used as a UART, then it really isn't enabled
+ * for our purposes.
+ */
+
+#ifndef CONFIG_USART0_ISUART
+#  undef CONFIG_SAM34_USART0
+#endif
+#ifndef CONFIG_USART1_ISUART
+#  undef CONFIG_SAM34_USART1
+#endif
+#ifndef CONFIG_USART2_ISUART
+#  undef CONFIG_SAM34_USART2
+#endif
+#ifndef CONFIG_USART3_ISUART
+#  undef CONFIG_SAM34_USART3
+#endif
+
+/* Is there a USART/USART enabled? */
+
+#if !defined(CONFIG_SAM34_UART0)  && !defined(CONFIG_SAM34_UART1) && \
+    !defined(CONFIG_SAM34_USART0) && !defined(CONFIG_SAM34_USART1) && \
+    !defined(CONFIG_SAM34_USART2) && !defined(CONFIG_SAM34_USART3)
+#  error "No USARTs enabled"
+#endif
+
+#if defined(CONFIG_SAM34_USART0) || defined(CONFIG_SAM34_USART1) ||\
+    defined(CONFIG_SAM34_USART2) || defined(CONFIG_SAM34_USART3)
+#  define HAVE_USART
+#endif
+
+/* Is there a serial console?  It could be on UART0-1 or USART0-3 */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* If we are not using the serial driver for the console, then we still must
+ * provide some minimal implementation of up_putc.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? */
+
+/* First pick the console and ttys0.  This could be any of UART0-1, USART0-3 */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart0port  /* UART0 is console */
+#    define TTYS0_DEV           g_uart0port  /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart1port  /* UART1 is console */
+#    define TTYS0_DEV           g_uart1port  /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_usart0port /* USART0 is console */
+#    define TTYS0_DEV           g_usart0port /* USART0 is ttyS0 */
+#    define USART0_ASSIGNED     1
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_usart1port /* USART1 is console */
+#    define TTYS0_DEV           g_usart1port /* USART1 is ttyS0 */
+#    define USART1_ASSIGNED     1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_usart2port /* USART2 is console */
+#    define TTYS0_DEV           g_usart2port /* USART2 is ttyS0 */
+#    define USART2_ASSIGNED     1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_usart3port /* USART3 is console */
+#    define TTYS5_DEV           g_usart3port /* USART3 is ttyS0 */
+#else
+#  undef CONSOLE_DEV                         /* No console */
+#  if defined(CONFIG_SAM34_UART0)
+#    define TTYS0_DEV           g_uart0port  /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+#  elif defined(CONFIG_SAM34_UART1)
+#    define TTYS0_DEV           g_uart1port  /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#  elif defined(CONFIG_SAM34_USART0)
+#    define TTYS0_DEV           g_usart0port /* USART0 is ttyS0 */
+#    define USART0_ASSIGNED     1
+#  elif defined(CONFIG_SAM34_USART1)
+#    define TTYS0_DEV           g_usart1port /* USART1 is ttyS0 */
+#    define USART1_ASSIGNED     1
+#  elif defined(CONFIG_SAM34_USART2)
+#    define TTYS0_DEV           g_usart2port /* USART2 is ttyS0 */
+#    define USART2_ASSIGNED     1
+#  elif defined(CONFIG_SAM34_USART3)
+#    define TTYS0_DEV           g_usart3port /* USART3 is ttyS0 */
+#    define USART3_ASSIGNED     1
+#  endif
+#endif
+
+/* Pick ttys1.  This could be any of UART0-1, USART0-3 excluding the console UART. */
+
+#if defined(CONFIG_SAM34_UART0) && !defined(UART0_ASSIGNED)
+#  define TTYS1_DEV           g_uart0port  /* UART0 is ttyS1 */
+#  define UART0_ASSIGNED      1
+#elif defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS1_DEV           g_uart1port  /* UART1 is ttyS1 */
+#  define UART1_ASSIGNED      1
+#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED)
+#  define TTYS1_DEV           g_usart0port /* USART0 is ttyS1 */
+#  define USART0_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED)
+#  define TTYS1_DEV           g_usart1port /* USART1 is ttyS1 */
+#  define USART1_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED)
+#  define TTYS1_DEV           g_usart2port /* USART2 is ttyS1 */
+#  define USART2_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED)
+#  define TTYS1_DEV           g_usart3port /* USART3 is ttyS1 */
+#  define USART3_ASSIGNED     1
+#endif
+
+/* Pick ttys2.  This could be one of UART1 or USART0-3. It can't be UART0
+ * because that was either assigned as ttyS0 or ttys1.  One of these
+ * could also be the console.
+ */
+
+#if defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS2_DEV           g_uart1port  /* UART1 is ttyS2 */
+#  define UART1_ASSIGNED      1
+#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED)
+#  define TTYS2_DEV           g_usart0port /* USART0 is ttyS2 */
+#  define USART0_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED)
+#  define TTYS2_DEV           g_usart1port /* USART1 is ttyS2 */
+#  define USART1_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED)
+#  define TTYS2_DEV           g_usart2port /* USART2 is ttyS2 */
+#  define USART2_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED)
+#  define TTYS2_DEV           g_usart3port /* USART3 is ttyS2 */
+#  define USART3_ASSIGNED     1
+#endif
+
+/* Pick ttys3. This could be one of USART0-3. It can't be UART0-1 because
+ * those have already been assigned to ttsyS0, 1, or 2.  One of
+ * USART0-3 could also be the console.
+ */
+
+#if defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED)
+#  define TTYS3_DEV           g_usart0port /* USART0 is ttyS3 */
+#  define USART0_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED)
+#  define TTYS3_DEV           g_usart1port /* USART1 is ttyS3 */
+#  define USART1_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED)
+#  define TTYS3_DEV           g_usart2port /* USART2 is ttyS3 */
+#  define USART2_ASSIGNED     1
+#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED)
+#  define TTYS3_DEV           g_usart3port /* USART3 is ttyS3 */
+#  define USART3_ASSIGNED     1
+#endif
+
+/* Pick ttys4. This could be one of USART1-3. It can't be UART0-1 or USART0
+ * because those have already been assigned to ttsyS0, 1, 2 or 3.  One of
+ * USART1-3 could also be the console.
+ */
+
+#if defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED)
+#  define TTYS4_DEV           g_usart1port /* USART1 is ttyS4 */
+#  define USART1_ASSIGNED      1
+#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED)
+#  define TTYS4_DEV           g_usart2port /* USART2 is ttyS4 */
+#  define USART2_ASSIGNED      1
+#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED)
+#  define TTYS4_DEV           g_usart3port /* USART3 is ttyS4 */
+#  define USART3_ASSIGNED      1
+#endif
+
+/* Pick ttys5. This could be one of USART2-3. It can't be UART0-1 or
+ * USART0-1 because those have already been assigned to ttsyS0, 1, 2,
+ * 3 or 4.  One of USART2-3 could also be the console.
+ */
+
+#if defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED)
+#  define TTYS5_DEV           g_usart2port /* USART2 is ttyS5 */
+#  define USART2_ASSIGNED      1
+#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED)
+#  define TTYS5_DEV           g_usart3port /* USART3 is ttyS5 */
+#  define USART3_ASSIGNED      1
+#endif
+
+/* The UART/USART modules are driven by the main clock (MCK). */
+
+#define SAM_USART_CLOCK  BOARD_MCK_FREQUENCY  /* Frequency of the main clock */
+#define SAM_MR_USCLKS    UART_MR_USCLKS_MCK   /* Source = Main clock */
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32_t usartbase; /* Base address of USART registers */
+  uint32_t baud;      /* Configured baud */
+  uint32_t sr;        /* Saved status bits */
+  uint8_t  irq;       /* IRQ associated with this USART */
+  uint8_t  parity;    /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;      /* Number of bits (7 or 8) */
+  bool     stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+static const struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_SAM34_UART0
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SAM34_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SAM34_USART0
+static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
+static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SAM34_USART1
+static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
+static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SAM34_USART2
+static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
+static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SAM34_USART3
+static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
+static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
+#endif
+
+/* This describes the state of the UART0 port. */
+
+#ifdef CONFIG_SAM34_UART0
+static struct up_dev_s g_uart0priv =
+{
+  .usartbase      = SAM_UART0_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .irq            = SAM_IRQ_UART0,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the UART1 port. */
+
+#ifdef CONFIG_SAM34_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .usartbase      = SAM_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .irq            = SAM_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/* This describes the state of the USART0 port. */
+
+#ifdef CONFIG_SAM34_USART0
+static struct up_dev_s g_usart0priv =
+{
+  .usartbase      = SAM_USART0_BASE,
+  .baud           = CONFIG_USART0_BAUD,
+  .irq            = SAM_IRQ_USART0,
+  .parity         = CONFIG_USART0_PARITY,
+  .bits           = CONFIG_USART0_BITS,
+  .stopbits2      = CONFIG_USART0_2STOP,
+};
+
+static uart_dev_t g_usart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART0_RXBUFSIZE,
+    .buffer = g_usart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART0_TXBUFSIZE,
+    .buffer = g_usart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_usart0priv,
+};
+#endif
+
+/* This describes the state of the USART1 port. */
+
+#ifdef CONFIG_SAM34_USART1
+static struct up_dev_s g_usart1priv =
+{
+  .usartbase      = SAM_USART1_BASE,
+  .baud           = CONFIG_USART1_BAUD,
+  .irq            = SAM_IRQ_USART1,
+  .parity         = CONFIG_USART1_PARITY,
+  .bits           = CONFIG_USART1_BITS,
+  .stopbits2      = CONFIG_USART1_2STOP,
+};
+
+static uart_dev_t g_usart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART1_RXBUFSIZE,
+    .buffer = g_usart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART1_TXBUFSIZE,
+    .buffer = g_usart1txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_usart1priv,
+};
+#endif
+
+/* This describes the state of the USART2 port. */
+
+#ifdef CONFIG_SAM34_USART2
+static struct up_dev_s g_usart2priv =
+{
+  .usartbase      = SAM_USART2_BASE,
+  .baud           = CONFIG_USART2_BAUD,
+  .irq            = SAM_IRQ_USART2,
+  .parity         = CONFIG_USART2_PARITY,
+  .bits           = CONFIG_USART2_BITS,
+  .stopbits2      = CONFIG_USART2_2STOP,
+};
+
+static uart_dev_t g_usart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART2_RXBUFSIZE,
+    .buffer = g_usart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART2_TXBUFSIZE,
+    .buffer = g_usart2txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_usart2priv,
+};
+#endif
+
+/* This describes the state of the USART3 port. */
+
+#ifdef CONFIG_SAM34_USART3
+static struct up_dev_s g_usart3priv =
+{
+  .usartbase      = SAM_USART3_BASE,
+  .baud           = CONFIG_USART3_BAUD,
+  .irq            = SAM_IRQ_USART3,
+  .parity         = CONFIG_USART3_PARITY,
+  .bits           = CONFIG_USART3_BITS,
+  .stopbits2      = CONFIG_USART3_2STOP,
+};
+
+static uart_dev_t g_usart3port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART3_RXBUFSIZE,
+    .buffer = g_usart3rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART3_TXBUFSIZE,
+    .buffer = g_usart3txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_usart3priv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->usartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->usartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_restoreusartint
+ ****************************************************************************/
+
+static inline void up_restoreusartint(struct up_dev_s *priv, uint32_t imr)
+{
+  /* Restore the previous interrupt state */
+
+  up_serialout(priv, SAM_UART_IMR_OFFSET, imr);
+}
+
+/****************************************************************************
+ * Name: up_disableallints
+ ****************************************************************************/
+
+static void up_disableallints(struct up_dev_s *priv, uint32_t *imr)
+{
+  irqstate_t flags;
+
+  /* The following must be atomic */
+
+  flags = irqsave();
+  if (imr)
+    {
+      /* Return the current interrupt mask */
+
+      *imr = up_serialin(priv, SAM_UART_IMR_OFFSET);
+    }
+
+  /* Disable all interrupts */
+
+  up_serialout(priv, SAM_UART_IDR_OFFSET, UART_INT_ALLINTS);
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the USART baud, bits, parity, etc. This method is called the
+ *   first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  uint32_t regval;
+
+  /* Note: The logic here depends on the fact that that the USART module
+   * was enabled and the pins were configured in sam_lowsetup().
+   */
+
+  /* The shutdown method will put the UART in a known, disabled state */
+
+  up_shutdown(dev);
+
+  /* Set up the mode register.  Start with normal UART mode and the MCK
+   * as the timing source
+   */
+
+  regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS);
+
+  /* OR in settings for the selected number of bits */
+
+  if (priv->bits == 5)
+    {
+      regval |= UART_MR_CHRL_5BITS; /* 5 bits */
+    }
+  else if (priv->bits == 6)
+    {
+      regval |= UART_MR_CHRL_6BITS;  /* 6 bits */
+    }
+  else if (priv->bits == 7)
+    {
+      regval |= UART_MR_CHRL_7BITS; /* 7 bits */
+    }
+#ifdef HAVE_USART
+  else if (priv->bits == 9
+#if defined(CONFIG_SAM34_UART0)
+           && priv->usartbase != SAM_UART0_BASE
+#endif
+#if defined(CONFIG_SAM34_UART1)
+           && priv->usartbase != SAM_UART1_BASE
+#endif
+          )
+    {
+      regval |= UART_MR_MODE9; /* 9 bits */
+    }
+#endif
+  else /* if (priv->bits == 8) */
+    {
+      regval |= UART_MR_CHRL_8BITS; /* 8 bits (default) */
+    }
+
+  /* OR in settings for the selected parity */
+
+  if (priv->parity == 1)
+    {
+      regval |= UART_MR_PAR_ODD;
+    }
+  else if (priv->parity == 2)
+    {
+      regval |= UART_MR_PAR_EVEN;
+    }
+  else
+    {
+      regval |= UART_MR_PAR_NONE;
+    }
+
+  /* OR in settings for the number of stop bits */
+
+  if (priv->stopbits2)
+    {
+      regval |= UART_MR_NBSTOP_2;
+    }
+  else
+    {
+      regval |= UART_MR_NBSTOP_1;
+    }
+
+  /* And save the new mode register value */
+
+  up_serialout(priv, SAM_UART_MR_OFFSET, regval);
+
+  /* Configure the console baud.  NOTE: Oversampling by 8 is not supported.
+   * This may limit BAUD rates for lower USART clocks.
+   */
+
+  regval  = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4);
+  up_serialout(priv, SAM_UART_BRGR_OFFSET, regval);
+
+  /* Enable receiver & transmitter */
+
+  up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN));
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the USART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+
+  /* Reset and disable receiver and transmitter */
+
+  up_serialout(priv, SAM_UART_CR_OFFSET,
+               (UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS));
+
+  /* Disable all interrupts */
+
+  up_disableallints(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the USART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the USART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach USART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception
+ *   is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the USART interrupt handler.  It will be invoked when an
+ *   interrupt received on the 'irq'  It should call uart_transmitchars or
+ *   uart_receivechar to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   approprite uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32_t           pending;
+  uint32_t           imr;
+  int                passes;
+  bool               handled;
+
+#ifdef CONFIG_SAM34_UART0
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_SAM34_UART1
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+#ifdef CONFIG_SAM34_USART0
+  if (g_usart0priv.irq == irq)
+    {
+      dev = &g_usart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_SAM34_USART1
+  if (g_usart1priv.irq == irq)
+    {
+      dev = &g_usart1port;
+    }
+  else
+#endif
+#ifdef CONFIG_SAM34_USART2
+  if (g_usart2priv.irq == irq)
+    {
+      dev = &g_usart2port;
+    }
+  else
+#endif
+#ifdef CONFIG_SAM34_USART3
+  if (g_usart3priv.irq == irq)
+    {
+      dev = &g_usart3port;
+    }
+  else
+#endif
+    {
+      PANIC();
+    }
+
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or, until we have
+   * been looping for a long time.
+   */
+
+  handled = true;
+  for (passes = 0; passes < 256 && handled; passes++)
+    {
+      handled = false;
+
+      /* Get the UART/USART status (we are only interested in the unmasked interrupts). */
+
+      priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET);  /* Save for error reporting */
+      imr      = up_serialin(priv, SAM_UART_IMR_OFFSET); /* Interrupt mask */
+      pending  = priv->sr & imr;                        /* Mask out disabled interrupt sources */
+
+      /* Handle an incoming, receive byte.  RXRDY: At least one complete character
+       * has been received and US_RHR has not yet been read.
+       */
+
+      if ((pending & UART_INT_RXRDY) != 0)
+        {
+           /* Received data ready... process incoming bytes */
+
+           uart_recvchars(dev);
+           handled = true;
+        }
+
+      /* Handle outgoing, transmit bytes. XRDY: There is no character in the
+       * US_THR.
+       */
+
+      if ((pending & UART_INT_TXRDY) != 0)
+        {
+           /* Transmit data register empty ... process outgoing bytes */
+
+           uart_xmitchars(dev);
+           handled = true;
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+#endif
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             ret = -EINVAL;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+#endif
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the USART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+
+  /* Return the error information in the saved status */
+
+  *status  = priv->sr;
+  priv->sr = 0;
+
+  /* Then return the actual received byte */
+
+  return (int)(up_serialin(priv, SAM_UART_RHR_OFFSET) & 0xff);
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RXRDY interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
+       * timeout occurs).
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      up_serialout(priv, SAM_UART_IER_OFFSET, UART_INT_RXRDY);
+#endif
+    }
+  else
+    {
+      up_serialout(priv, SAM_UART_IDR_OFFSET, UART_INT_RXRDY);
+    }
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive holding register is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_RXRDY) != 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART/USART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, SAM_UART_THR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  flags = irqsave();
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX holding register register
+       * is empty
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      up_serialout(priv, SAM_UART_IER_OFFSET, UART_INT_TXRDY);
+
+#  if 0 /* Seems to be unnecessary */
+      /* Fake a TX interrupt here by just calling uart_xmitchars() with
+       * interrupts disabled (note this may recurse).
+       */
+
+      uart_xmitchars(dev);
+#  endif
+#endif
+    }
+  else
+    {
+      /* Disable the TX interrupt */
+
+      up_serialout(priv, SAM_UART_IDR_OFFSET, UART_INT_TXRDY);
+    }
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit holding register is empty (TXRDY)
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0);
+ }
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit holding and shift registers are empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level USART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* NOTE:  All GPIO configuration for the USARTs was performed in
+   * sam_lowsetup
+   */
+
+  /* Disable all USARTS */
+
+  up_disableallints(TTYS0_DEV.priv, NULL);
+#ifdef TTYS1_DEV
+  up_disableallints(TTYS1_DEV.priv, NULL);
+#endif
+#ifdef TTYS2_DEV
+  up_disableallints(TTYS2_DEV.priv, NULL);
+#endif
+#ifdef TTYS3_DEV
+  up_disableallints(TTYS3_DEV.priv, NULL);
+#endif
+#ifdef TTYS4_DEV
+  up_disableallints(TTYS4_DEV.priv, NULL);
+#endif
+#ifdef TTYS5_DEV
+  up_disableallints(TTYS5_DEV.priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef HAVE_CONSOLE
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+  /* Register the console */
+
+#ifdef HAVE_CONSOLE
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+  /* Register all USARTs */
+
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+#ifdef TTYS3_DEV
+  (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+#endif
+#ifdef TTYS4_DEV
+  (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+#endif
+#ifdef TTYS5_DEV
+  (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint32_t imr;
+
+  up_disableallints(priv, &imr);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+  up_restoreusartint(priv, imr);
+#endif
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */