Complete Kinetis USB and add skeletons for all remaining header files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3869 42af7a65-404d-4744-a932-0658087f49c3

8 files changed, 1152 insertions, 66 deletions

diff --git a/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h b/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h
new file mode 100644
index 000000000..150f04f1a
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h
@@ -0,0 +1,183 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_flexcan.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_CAN_MCR_OFFSET      0x0000 /* Module Configuration Register */
+#define KINETIS_CAN_CTRL1_OFFSET    0x0004 /* Control 1 Register */
+#define KINETIS_CAN_TIMER_OFFSET    0x0008 /* Free Running Timer */
+#define KINETIS_CAN_RXMGMASK_OFFSET 0x0010 /* Rx Mailboxes Global Mask Register */
+#define KINETIS_CAN_RX14MASK_OFFSET 0x0014 /* Rx 14 Mask Register */
+#define KINETIS_CAN_RX15MASK_OFFSET 0x0018 /* Rx 15 Mask Register */
+#define KINETIS_CAN_ECR_OFFSET      0x001c /* Error Counter */
+#define KINETIS_CAN_ESR1_OFFSET     0x0020 /* Error and Status 1 Register */
+#define KINETIS_CAN_IMASK2_OFFSET   0x0024 /* Interrupt Masks 2 Register */
+#define KINETIS_CAN_IMASK1_OFFSET   0x0028 /* Interrupt Masks 1 Register */
+#define KINETIS_CAN_IFLAG2_OFFSET   0x002c /* Interrupt Flags 2 Register */
+#define KINETIS_CAN_IFLAG1_OFFSET   0x0030 /* Interrupt Flags 1 Register */
+#define KINETIS_CAN_CTRL2_OFFSET    0x0034 /* Control 2 Register */
+#define KINETIS_CAN_ESR2_OFFSET     0x0038 /* Error and Status 2 Register */
+#define KINETIS_CAN_CRCR_OFFSET     0x0044 /* CRC Register */
+#define KINETIS_CAN_RXFGMASK_OFFSET 0x0048 /* Rx FIFO Global Mask Register */
+#define KINETIS_CAN_RXFIR_OFFSET    0x004c /* Rx FIFO Information Register */
+
+#define KINETIS_CAN_RXIMR_OFFSET(n) (0x0880+((n)<<2)) /* Rn Individual Mask Registers */
+#define KINETIS_CAN_RXIMR0_OFFSET   0x0880 /* R0 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR1_OFFSET   0x0884 /* R1 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR2_OFFSET   0x0888 /* R2 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR3_OFFSET   0x088c /* R3 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR4_OFFSET   0x0890 /* R4 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR5_OFFSET   0x0894 /* R5 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR6_OFFSET   0x0898 /* R6 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR7_OFFSET   0x089c /* R7 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR8_OFFSET   0x08a0 /* R8 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR9_OFFSET   0x08a4 /* R9 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR10_OFFSET  0x08a8 /* R10 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR11_OFFSET  0x08ac /* R11 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR12_OFFSET  0x08b0 /* R12 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR13_OFFSET  0x08b4 /* R13 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR14_OFFSET  0x08b8 /* R14 Individual Mask Registers */
+#define KINETIS_CAN_RXIMR15_OFFSET  0x08bc /* R15 Individual Mask Registers */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_CAN0_MCR           (KINETIS_CAN0_BASE+KINETIS_CAN_MCR_OFFSET)
+#define KINETIS_CAN0_CTRL1         (KINETIS_CAN0_BASE+KINETIS_CAN_CTRL1_OFFSET)
+#define KINETIS_CAN0_TIMER         (KINETIS_CAN0_BASE+KINETIS_CAN_TIMER_OFFSET)
+#define KINETIS_CAN0_RXMGMASK      (KINETIS_CAN0_BASE+KINETIS_CAN_RXMGMASK_OFFSET)
+#define KINETIS_CAN0_RX14MASK      (KINETIS_CAN0_BASE+KINETIS_CAN_RX14MASK_OFFSET)
+#define KINETIS_CAN0_RX15MASK      (KINETIS_CAN0_BASE+KINETIS_CAN_RX15MASK_OFFSET)
+#define KINETIS_CAN0_ECR           (KINETIS_CAN0_BASE+KINETIS_CAN_ECR_OFFSET)
+#define KINETIS_CAN0_ESR1          (KINETIS_CAN0_BASE+KINETIS_CAN_ESR1_OFFSET)
+#define KINETIS_CAN0_IMASK2        (KINETIS_CAN0_BASE+KINETIS_CAN_IMASK2_OFFSET)
+#define KINETIS_CAN0_IMASK1        (KINETIS_CAN0_BASE+KINETIS_CAN_IMASK1_OFFSET)
+#define KINETIS_CAN0_IFLAG2        (KINETIS_CAN0_BASE+KINETIS_CAN_IFLAG2_OFFSET)
+#define KINETIS_CAN0_IFLAG1        (KINETIS_CAN0_BASE+KINETIS_CAN_IFLAG1_OFFSET)
+#define KINETIS_CAN0_CTRL2         (KINETIS_CAN0_BASE+KINETIS_CAN_CTRL2_OFFSET)
+#define KINETIS_CAN0_ESR2          (KINETIS_CAN0_BASE+KINETIS_CAN_ESR2_OFFSET)
+#define KINETIS_CAN0_CRCR          (KINETIS_CAN0_BASE+KINETIS_CAN_CRCR_OFFSET)
+#define KINETIS_CAN0_RXFGMASK      (KINETIS_CAN0_BASE+KINETIS_CAN_RXFGMASK_OFFSET)
+#define KINETIS_CAN0_RXFIR         (KINETIS_CAN0_BASE+KINETIS_CAN_RXFIR_OFFSET)
+
+#define KINETIS_CAN0_RXIMR(n)      (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR_OFFSET(n))
+#define KINETIS_CAN0_RXIMR0        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR0_OFFSET)
+#define KINETIS_CAN0_RXIMR1        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR1_OFFSET)
+#define KINETIS_CAN0_RXIMR2        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR2_OFFSET)
+#define KINETIS_CAN0_RXIMR3        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR3_OFFSET)
+#define KINETIS_CAN0_RXIMR4        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR4_OFFSET)
+#define KINETIS_CAN0_RXIMR5        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR5_OFFSET)
+#define KINETIS_CAN0_RXIMR6        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR6_OFFSET)
+#define KINETIS_CAN0_RXIMR7        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR7_OFFSET)
+#define KINETIS_CAN0_RXIMR8        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR8_OFFSET)
+#define KINETIS_CAN0_RXIMR9        (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR9_OFFSET)
+#define KINETIS_CAN0_RXIMR10       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR10_OFFSET)
+#define KINETIS_CAN0_RXIMR11       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR11_OFFSET)
+#define KINETIS_CAN0_RXIMR12       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR12_OFFSET)
+#define KINETIS_CAN0_RXIMR13       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR13_OFFSET)
+#define KINETIS_CAN0_RXIMR14       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR14_OFFSET)
+#define KINETIS_CAN0_RXIMR15       (KINETIS_CAN0_BASE+KINETIS_CAN_RXIMR15_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Module Configuration Register */
+#define CAN_MCR_
+/* Control 1 Register */
+#define CAN_CTRL1_
+/* Free Running Timer */
+#define CAN_TIMER_
+/* Rx Mailboxes Global Mask Register */
+#define CAN_RXMGMASK_
+/* Rx 14 Mask Register */
+#define CAN_RX14MASK_
+/* Rx 15 Mask Register */
+#define CAN_RX15MASK_
+/* Error Counter */
+#define CAN_ECR_
+/* Error and Status 1 Register */
+#define CAN_ESR1_
+/* Interrupt Masks 2 Register */
+#define CAN_IMASK2_
+/* Interrupt Masks 1 Register */
+#define CAN_IMASK1_
+/* Interrupt Flags 2 Register */
+#define CAN_IFLAG2_
+/* Interrupt Flags 1 Register */
+#define CAN_IFLAG1_
+/* Control 2 Register */
+#define CAN_CTRL2_
+/* Error and Status 2 Register */
+#define CAN_ESR2_
+/* CRC Register */
+#define CAN_CRCR_
+/* Rx FIFO Global Mask Register */
+#define CAN_RXFGMASK_
+/* Rx FIFO Information Register */
+#define CAN_RXFIR_
+
+/* Rn Individual Mask Registers */
+#define CAN_RXIMR_
+
+                (1 << nn)  /* Bit nn:  
+_SHIFT          (nn)       /* Bits nn-nn: 
+_MASK           (nn << nn)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_i2s.h b/nuttx/arch/arm/src/kinetis/kinetis_i2s.h
new file mode 100644
index 000000000..a92699d6f
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_i2s.h
@@ -0,0 +1,160 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_i2s.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_I2S_TX0_OFFSET     0x000 /* I2S Transmit Data Registers 0 */
+#define KINETIS_I2S_TX1_OFFSET     0x004 /* I2S Transmit Data Registers 1 */
+#define KINETIS_I2S_RX0_OFFSET     0x008 /* I2S Receive Data Registers 0 */
+#define KINETIS_I2S_RX1_OFFSET     0x00c /* I2S Receive Data Registers 1 */
+#define KINETIS_I2S_CR_OFFSET      0x010 /* I2S Control Register */
+#define KINETIS_I2S_ISR_OFFSET     0x014 /* I2S Interrupt Status Register */
+#define KINETIS_I2S_IER_OFFSET     0x018 /* I2S Interrupt Enable Register */
+#define KINETIS_I2S_TCR_OFFSET     0x01c /* I2S Transmit Configuration Register */
+#define KINETIS_I2S_RCR_OFFSET     0x020 /* I2S Receive Configuration Register */
+#define KINETIS_I2S_TCCR_OFFSET    0x024 /* I2S Transmit Clock Control Registers */
+#define KINETIS_I2S_RCCR_OFFSET    0x028 /* I2S Receive Clock Control Registers */
+#define KINETIS_I2S_FCSR_OFFSET    0x02c /* I2S FIFO Control/Status Register */
+#define KINETIS_I2S_ACNT_OFFSET    0x038 /* I2S AC97 Control Register */
+#define KINETIS_I2S_ACADD_OFFSET   0x03c /* I2S AC97 Command Address Register */
+#define KINETIS_I2S_ACDAT_OFFSET   0x040 /* I2S AC97 Command Data Register */
+#define KINETIS_I2S_ATAG_OFFSET    0x044 /* I2S AC97 Tag Register */
+#define KINETIS_I2S_TMSK_OFFSET    0x048 /* I2S Transmit Time Slot Mask Register */
+#define KINETIS_I2S_RMSK_OFFSET    0x04c /* I2S Receive Time Slot Mask Register */
+#define KINETIS_I2S_ACCST_OFFSET   0x050 /* I2S AC97 Channel Status Register */
+#define KINETIS_I2S_ACCEN_OFFSET   0x054 /* I2S AC97 Channel Enable Register */
+#define KINETIS_I2S_ACCDIS_OFFSET  0x058 /* I2S AC97 Channel Disable Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_I2S0_TX0           (KINETIS_I2S0_BASE+KINETIS_I2S_TX0_OFFSET)
+#define KINETIS_I2S0_TX1           (KINETIS_I2S0_BASE+KINETIS_I2S_TX1_OFFSET)
+#define KINETIS_I2S0_RX0           (KINETIS_I2S0_BASE+KINETIS_I2S_RX0_OFFSET)
+#define KINETIS_I2S0_RX1           (KINETIS_I2S0_BASE+KINETIS_I2S_RX1_OFFSET)
+#define KINETIS_I2S0_CR            (KINETIS_I2S0_BASE+KINETIS_I2S_CR_OFFSET)
+#define KINETIS_I2S0_ISR           (KINETIS_I2S0_BASE+KINETIS_I2S_ISR_OFFSET)
+#define KINETIS_I2S0_IER           (KINETIS_I2S0_BASE+KINETIS_I2S_IER_OFFSET)
+#define KINETIS_I2S0_TCR           (KINETIS_I2S0_BASE+KINETIS_I2S_TCR_OFFSET)
+#define KINETIS_I2S0_RCR           (KINETIS_I2S0_BASE+KINETIS_I2S_RCR_OFFSET)
+#define KINETIS_I2S0_TCCR          (KINETIS_I2S0_BASE+KINETIS_I2S_TCCR_OFFSET)
+#define KINETIS_I2S0_RCCR          (KINETIS_I2S0_BASE+KINETIS_I2S_RCCR_OFFSET)
+#define KINETIS_I2S0_FCSR          (KINETIS_I2S0_BASE+KINETIS_I2S_FCSR_OFFSET)
+#define KINETIS_I2S0_ACNT          (KINETIS_I2S0_BASE+KINETIS_I2S_ACNT_OFFSET)
+#define KINETIS_I2S0_ACADD         (KINETIS_I2S0_BASE+KINETIS_I2S_ACADD_OFFSET)
+#define KINETIS_I2S0_ACDAT         (KINETIS_I2S0_BASE+KINETIS_I2S_ACDAT_OFFSET)
+#define KINETIS_I2S0_ATAG          (KINETIS_I2S0_BASE+KINETIS_I2S_ATAG_OFFSET)
+#define KINETIS_I2S0_TMSK          (KINETIS_I2S0_BASE+KINETIS_I2S_TMSK_OFFSET)
+#define KINETIS_I2S0_RMSK          (KINETIS_I2S0_BASE+KINETIS_I2S_RMSK_OFFSET)
+#define KINETIS_I2S0_ACCST         (KINETIS_I2S0_BASE+KINETIS_I2S_ACCST_OFFSET)
+#define KINETIS_I2S0_ACCEN         (KINETIS_I2S0_BASE+KINETIS_I2S_ACCEN_OFFSET)
+#define KINETIS_I2S0_ACCDIS        (KINETIS_I2S0_BASE+KINETIS_I2S_ACCDIS_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* I2S Transmit Data Registers 0 */
+#define I2S_TX0_
+/* I2S Transmit Data Registers 1 */
+#define I2S_TX1_
+/* I2S Receive Data Registers 0 */
+#define I2S_RX0_
+/* I2S Receive Data Registers 1 */
+#define I2S_RX1_
+/* I2S Control Register */
+#define I2S_CR_
+/* I2S Interrupt Status Register */
+#define I2S_ISR_
+/* I2S Interrupt Enable Register */
+#define I2S_IER_
+/* I2S Transmit Configuration Register */
+#define I2S_TCR_
+/* I2S Receive Configuration Register */
+#define I2S_RCR_
+/* I2S Transmit Clock Control Registers */
+#define I2S_TCCR_
+/* I2S Receive Clock Control Registers */
+#define I2S_RCCR_
+/* I2S FIFO Control/Status Register */
+#define I2S_FCSR_
+/* I2S AC97 Control Register */
+#define I2S_ACNT_
+/* I2S AC97 Command Address Register */
+#define I2S_ACADD_
+/* I2S AC97 Command Data Register */
+#define I2S_ACDAT_
+/* I2S AC97 Tag Register */
+#define I2S_ATAG_
+/* I2S Transmit Time Slot Mask Register */
+#define I2S_TMSK_
+/* I2S Receive Time Slot Mask Register */
+#define I2S_RMSK_
+/* I2S AC97 Channel Status Register */
+#define I2S_ACCST_
+/* I2S AC97 Channel Enable Register */
+#define I2S_ACCEN_
+/* I2S AC97 Channel Disable Register */
+#define I2S_ACCDIS_
+
+                (1 << nn)  /* Bit nn:  
+_SHIFT          (nn)       /* Bits nn-nn: 
+_MASK           (nn << nn)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
index e7eeb8d11..30ed328f1 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
@@ -104,7 +104,7 @@
 # define KINETIS_FMC_BASE       0x4001f000 /* Flash memory controller */
 # define KINETIS_FTFL_BASE      0x40020000 /* Flash memory */
 # define KINETIS_DMAMUX0_BASE   0x40021000 /* DMA channel mutiplexer 0 */
-# define KINETIS_FLEXCAN0_BASE  0x40024000 /* FlexCAN 0 */
+# define KINETIS_CAN0_BASE      0x40024000 /* FlexCAN 0 */
 # define KINETIS_SPI0_BASE      0x4002c000 /* SPI 0 */
 # define KINETIS_SPI1_BASE      0x4002d000 /* SPI 1 */
 # define KINETIS_I2S0_BASE      0x4002f000 /* I2S 0 */
@@ -121,7 +121,7 @@
 # define KINETIS_SYSR_BASE      0x40041000 /* System register file */
 # define KINETIS_DRYICE_BASE    0x40042000 /* DryIce */
 # define KINETIS_DRYICESS_BASE  0x40043000 /* DryIce secure storage */
-# define KINETIS_TSI_BASE       0x40045000 /* Touch sense interface */
+# define KINETIS_TSI0_BASE      0x40045000 /* Touch sense interface */
 # define KINETIS_SIMLP_BASE     0x40047000 /* SIM low-power logic */
 # define KINETIS_SIM_BASE       0x40048000 /* System integration module (SIM) */
 # define KINETIS_PORT_BASE(n)   (0x40049000 + ((n) << 12))
@@ -151,7 +151,7 @@
 /* Peripheral Bridge 1 Memory Map ***************************************************/
 
 # define KINETIS_AIPS1_BASE     0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
-# define KINETIS_FLEXCAN1_BASE  0x400a4000 /* FlexCAN 1 */
+# define KINETIS_CAN1_BASE      0x400a4000 /* FlexCAN 1 */
 # define KINETIS_SPI2_BASE      0x400ac000 /* SPI 2 */
 # define KINETIS_SDHC_BASE      0x400b1000 /* SDHC */
 # define KINETIS_FTM2_BASE      0x400b8000 /* FlexTimer 2 */
@@ -235,7 +235,7 @@
 # define KINETIS_FMC_BASE       0x4001f000 /* Flash memory controller */
 # define KINETIS_FTFL_BASE      0x40020000 /* Flash memory */
 # define KINETIS_DMAMUX0_BASE   0x40021000 /* DMA channel mutiplexer 0 */
-# define KINETIS_FLEXCAN0_BASE  0x40024000 /* FlexCAN 0 */
+# define KINETIS_CAN0_BASE      0x40024000 /* FlexCAN 0 */
 # define KINETIS_SPI0_BASE      0x4002c000 /* DSPI 0 */
 # define KINETIS_SPI1_BASE      0x4002d000 /* DSPI 1 */
 # define KINETIS_I2S0_BASE      0x4002f000 /* I2S 0 */
@@ -252,7 +252,7 @@
 # define KINETIS_SYSR_BASE      0x40041000 /* System register file */
 # define KINETIS_DRYICE_BASE    0x40042000 /* DryIce */
 # define KINETIS_DRYICESS_BASE  0x40043000 /* DryIce secure storage */
-# define KINETIS_TSI_BASE       0x40045000 /* Touch sense interface */
+# define KINETIS_TSI0_BASE      0x40045000 /* Touch sense interface */
 # define KINETIS_SIMLP_BASE     0x40047000 /* SIM low-power logic */
 # define KINETIS_SIM_BASE       0x40048000 /* System integration module (SIM) */
 # define KINETIS_PORT_BASE(n)   (0x40049000 + ((n) << 12))
@@ -283,7 +283,7 @@
 
 # define KINETIS_AIPS1_BASE     0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
 # define KINETIS_RNGB_BASE      0x400a0000 /* Random number generator (RNGB) */
-# define KINETIS_FLEXCAN1_BASE  0x400a4000 /* FlexCAN 1 */
+# define KINETIS_CAN1_BASE      0x400a4000 /* FlexCAN 1 */
 # define KINETIS_SPI2_BASE      0x400ac000 /* DSPI 2 */
 # define KINETIS_SDHC_BASE      0x400b1000 /* SDHC */
 # define KINETIS_FTM2_BASE      0x400b8000 /* FlexTimer 2 */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h
new file mode 100644
index 000000000..187d3aea2
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h
@@ -0,0 +1,172 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_sdhc.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_SDHC_DSADDR_OFFSET     0x0000 /* DMA System Address Register */
+#define KINETIS_SDHC_BLKATTR_OFFSET    0x0004 /* Block Attributes Register */
+#define KINETIS_SDHC_CMDARG_OFFSET     0x0008 /* Command Argument Register */
+#define KINETIS_SDHC_XFERTYP_OFFSET    0x000c /* Transfer Type Register */
+#define KINETIS_SDHC_CMDRSP0_OFFSET    0x0010 /* Command Response 0 */
+#define KINETIS_SDHC_CMDRSP1_OFFSET    0x0014 /* Command Response 1 */
+#define KINETIS_SDHC_CMDRSP2_OFFSET    0x0018 /* Command Response 2 */
+#define KINETIS_SDHC_CMDRSP3_OFFSET    0x001c /* Command Response 3 */
+#define KINETIS_SDHC_DATPORT_OFFSET    0x0020 /* Buffer Data Port Register */
+#define KINETIS_SDHC_PRSSTAT_OFFSET    0x0024 /* Present State Register */
+#define KINETIS_SDHC_PROCTL_OFFSET     0x0028 /* Protocol Control Register */
+#define KINETIS_SDHC_SYSCTL_OFFSET     0x002c /* System Control Register */
+#define KINETIS_SDHC_IRQSTAT_OFFSET    0x0030 /* Interrupt Status Register */
+#define KINETIS_SDHC_IRQSTATEN_OFFSET  0x0034 /* Interrupt Status Enable Register */
+#define KINETIS_SDHC_IRQSIGEN_OFFSET   0x0038 /* Interrupt Signal Enable Register */
+#define KINETIS_SDHC_AC12ERR_OFFSET    0x003c /* Auto CMD12 Error Status Register */
+#define KINETIS_SDHC_HTCAPBLT_OFFSET   0x0040 /* Host Controller Capabilities */
+#define KINETIS_SDHC_WML_OFFSET        0x0044 /* Watermark Level Register */
+#define KINETIS_SDHC_FEVT_OFFSET       0x0050 /* Force Event Register */
+#define KINETIS_SDHC_ADMAES_OFFSET     0x0054 /* ADMA Error Status Register */
+#define KINETIS_SDHC_ADSADDR_OFFSET    0x0058 /* ADMA System Address Register */
+#define KINETIS_SDHC_VENDOR_OFFSET     0x00c0 /* Vendor Specific Register */
+#define KINETIS_SDHC_MMCBOOT_OFFSET    0x00c4 /* MMC Boot Register */
+#define KINETIS_SDHC_HOSTVER_OFFSET    0x00fc /* Host Controller Version */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_SDHC_DSADDR            (KINETIS_SDHC_BASE+KINETIS_SDHC_DSADDR_OFFSET)
+#define KINETIS_SDHC_BLKATTR           (KINETIS_SDHC_BASE+KINETIS_SDHC_BLKATTR_OFFSET)
+#define KINETIS_SDHC_CMDARG            (KINETIS_SDHC_BASE+KINETIS_SDHC_CMDARG_OFFSET)
+#define KINETIS_SDHC_XFERTYP           (KINETIS_SDHC_BASE+KINETIS_SDHC_XFERTYP_OFFSET)
+#define KINETIS_SDHC_CMDRSP0           (KINETIS_SDHC_BASE+KINETIS_SDHC_CMDRSP0_OFFSET)
+#define KINETIS_SDHC_CMDRSP1           (KINETIS_SDHC_BASE+KINETIS_SDHC_CMDRSP1_OFFSET)
+#define KINETIS_SDHC_CMDRSP2           (KINETIS_SDHC_BASE+KINETIS_SDHC_CMDRSP2_OFFSET)
+#define KINETIS_SDHC_CMDRSP3           (KINETIS_SDHC_BASE+KINETIS_SDHC_CMDRSP3_OFFSET)
+#define KINETIS_SDHC_DATPORT           (KINETIS_SDHC_BASE+KINETIS_SDHC_DATPORT_OFFSET)
+#define KINETIS_SDHC_PRSSTAT           (KINETIS_SDHC_BASE+KINETIS_SDHC_PRSSTAT_OFFSET)
+#define KINETIS_SDHC_PROCTL            (KINETIS_SDHC_BASE+KINETIS_SDHC_PROCTL_OFFSET)
+#define KINETIS_SDHC_SYSCTL            (KINETIS_SDHC_BASE+KINETIS_SDHC_SYSCTL_OFFSET)
+#define KINETIS_SDHC_IRQSTAT           (KINETIS_SDHC_BASE+KINETIS_SDHC_IRQSTAT_OFFSET)
+#define KINETIS_SDHC_IRQSTATEN         (KINETIS_SDHC_BASE+KINETIS_SDHC_IRQSTATEN_OFFSET)
+#define KINETIS_SDHC_IRQSIGEN          (KINETIS_SDHC_BASE+KINETIS_SDHC_IRQSIGEN_OFFSET)
+#define KINETIS_SDHC_AC12ERR           (KINETIS_SDHC_BASE+KINETIS_SDHC_AC12ERR_OFFSET)
+#define KINETIS_SDHC_HTCAPBLT          (KINETIS_SDHC_BASE+KINETIS_SDHC_HTCAPBLT_OFFSET)
+#define KINETIS_SDHC_WML               (KINETIS_SDHC_BASE+KINETIS_SDHC_WML_OFFSET)
+#define KINETIS_SDHC_FEVT              (KINETIS_SDHC_BASE+KINETIS_SDHC_FEVT_OFFSET)
+#define KINETIS_SDHC_ADMAES            (KINETIS_SDHC_BASE+KINETIS_SDHC_ADMAES_OFFSET)
+#define KINETIS_SDHC_ADSADDR           (KINETIS_SDHC_BASE+KINETIS_SDHC_ADSADDR_OFFSET)
+#define KINETIS_SDHC_VENDOR            (KINETIS_SDHC_BASE+KINETIS_SDHC_VENDOR_OFFSET)
+#define KINETIS_SDHC_MMCBOOT           (KINETIS_SDHC_BASE+KINETIS_SDHC_MMCBOOT_OFFSET)
+#define KINETIS_SDHC_HOSTVER           (KINETIS_SDHC_BASE+KINETIS_SDHC_HOSTVER_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* DMA System Address Register */
+#define SDHC_DSADDR_
+/* Block Attributes Register */
+#define SDHC_BLKATTR_
+/* Command Argument Register */
+#define SDHC_CMDARG_
+/* Transfer Type Register */
+#define SDHC_XFERTYP_
+/* Command Response 0 */
+#define SDHC_CMDRSP0_
+/* Command Response 1 */
+#define SDHC_CMDRSP1_
+/* Command Response 2 */
+#define SDHC_CMDRSP2_
+/* Command Response 3 */
+#define SDHC_CMDRSP3_
+/* Buffer Data Port Register */
+#define SDHC_DATPORT_
+/* Present State Register */
+#define SDHC_PRSSTAT_
+/* Protocol Control Register */
+#define SDHC_PROCTL_
+/* System Control Register */
+#define SDHC_SYSCTL_
+/* Interrupt Status Register */
+#define SDHC_IRQSTAT_
+/* Interrupt Status Enable Register */
+#define SDHC_IRQSTATEN_
+/* Interrupt Signal Enable Register */
+#define SDHC_IRQSIGEN_
+/* Auto CMD12 Error Status Register */
+#define SDHC_AC12ERR_
+/* Host Controller Capabilities */
+#define SDHC_HTCAPBLT_
+/* Watermark Level Register */
+#define SDHC_WML_
+/* Force Event Register */
+#define SDHC_FEVT_
+/* ADMA Error Status Register */
+#define SDHC_ADMAES_
+/* ADMA System Address Register */
+#define SDHC_ADSADDR_
+/* Vendor Specific Register */
+#define SDHC_VENDOR_
+/* MMC Boot Register */
+#define SDHC_MMCBOOT_
+/* Host Controller Version */
+#define SDHC_HOSTVER_
+
+                (1 << nn)  /* Bit nn:  
+_SHIFT          (nn)       /* Bits nn-nn: 
+_MASK           (nn << nn)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_slcd.h b/nuttx/arch/arm/src/kinetis/kinetis_slcd.h
new file mode 100644
index 000000000..5b427174d
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_slcd.h
@@ -0,0 +1,172 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_slcd.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_LCD_GCR_OFFSET       0x0000 /* LCD general control register */
+#define KINETIS_LCD_AR_OFFSET        0x0004 /* LCD auxiliary register */
+#define KINETIS_LCD_FDCR_OFFSET      0x0008 /* LCD fault detect control register */
+#define KINETIS_LCD_FDSR_OFFSET      0x000c /* LCD fault detect status register */
+#define KINETIS_LCD_PENL_OFFSET      0x0010 /* LCD pin enable register */
+#define KINETIS_LCD_PENH_OFFSET      0x0014 /* LCD pin enable register */
+#define KINETIS_LCD_BPENL_OFFSET     0x0018 /* LCD backplane enable register */
+#define KINETIS_LCD_BPENH_OFFSET     0x001c /* LCD backplane enable register */
+#define KINETIS_LCD_WF3TO0_OFFSET    0x0020 /* LCD waveform register */
+#define KINETIS_LCD_WF7TO4_OFFSET    0x0024 /* LCD waveform register */
+#define KINETIS_LCD_WF11TO8_OFFSET   0x0028 /* LCD waveform register */
+#define KINETIS_LCD_WF15TO12_OFFSET  0x002c /* LCD waveform register */
+#define KINETIS_LCD_WF19TO16_OFFSET  0x0030 /* LCD waveform register */
+#define KINETIS_LCD_WF23TO20_OFFSET  0x0034 /* LCD waveform register */
+#define KINETIS_LCD_WF27TO24_OFFSET  0x0038 /* LCD waveform register */
+#define KINETIS_LCD_WF31TO28_OFFSET  0x003c /* LCD waveform register */
+#define KINETIS_LCD_WF35TO32_OFFSET  0x0040 /* LCD waveform register */
+#define KINETIS_LCD_WF39TO36_OFFSET  0x0044 /* LCD waveform register */
+#define KINETIS_LCD_WF43TO40_OFFSET  0x0048 /* LCD waveform register */
+#define KINETIS_LCD_WF47TO44_OFFSET  0x004c /* LCD waveform register */
+#define KINETIS_LCD_WF51TO48_OFFSET  0x0050 /* LCD waveform register */
+#define KINETIS_LCD_WF55TO52_OFFSET  0x0054 /* LCD waveform register */
+#define KINETIS_LCD_WF59TO56_OFFSET  0x0058 /* LCD waveform register */
+#define KINETIS_LCD_WF63TO60_OFFSET  0x005C /* LCD waveform register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_LCD_GCR              (KINETIS_SLCD_BASE+KINETIS_LCD_GCR_OFFSET)
+#define KINETIS_LCD_AR               (KINETIS_SLCD_BASE+KINETIS_LCD_AR_OFFSET)
+#define KINETIS_LCD_FDCR             (KINETIS_SLCD_BASE+KINETIS_LCD_FDCR_OFFSET)
+#define KINETIS_LCD_FDSR             (KINETIS_SLCD_BASE+KINETIS_LCD_FDSR_OFFSET)
+#define KINETIS_LCD_PENL             (KINETIS_SLCD_BASE+KINETIS_LCD_PENL_OFFSET)
+#define KINETIS_LCD_PENH             (KINETIS_SLCD_BASE+KINETIS_LCD_PENH_OFFSET)
+#define KINETIS_LCD_BPENL            (KINETIS_SLCD_BASE+KINETIS_LCD_BPENL_OFFSET)
+#define KINETIS_LCD_BPENH            (KINETIS_SLCD_BASE+KINETIS_LCD_BPENH_OFFSET)
+#define KINETIS_LCD_WF3TO0           (KINETIS_SLCD_BASE+KINETIS_LCD_WF3TO0_OFFSET)
+#define KINETIS_LCD_WF7TO4           (KINETIS_SLCD_BASE+KINETIS_LCD_WF7TO4_OFFSET)
+#define KINETIS_LCD_WF11TO8          (KINETIS_SLCD_BASE+KINETIS_LCD_WF11TO8_OFFSET)
+#define KINETIS_LCD_WF15TO12         (KINETIS_SLCD_BASE+KINETIS_LCD_WF15TO12_OFFSET)
+#define KINETIS_LCD_WF19TO16         (KINETIS_SLCD_BASE+KINETIS_LCD_WF19TO16_OFFSET)
+#define KINETIS_LCD_WF23TO20         (KINETIS_SLCD_BASE+KINETIS_LCD_WF23TO20_OFFSET)
+#define KINETIS_LCD_WF27TO24         (KINETIS_SLCD_BASE+KINETIS_LCD_WF27TO24_OFFSET)
+#define KINETIS_LCD_WF31TO28         (KINETIS_SLCD_BASE+KINETIS_LCD_WF31TO28_OFFSET)
+#define KINETIS_LCD_WF35TO32         (KINETIS_SLCD_BASE+KINETIS_LCD_WF35TO32_OFFSET)
+#define KINETIS_LCD_WF39TO36         (KINETIS_SLCD_BASE+KINETIS_LCD_WF39TO36_OFFSET)
+#define KINETIS_LCD_WF43TO40         (KINETIS_SLCD_BASE+KINETIS_LCD_WF43TO40_OFFSET)
+#define KINETIS_LCD_WF47TO44         (KINETIS_SLCD_BASE+KINETIS_LCD_WF47TO44_OFFSET)
+#define KINETIS_LCD_WF51TO48         (KINETIS_SLCD_BASE+KINETIS_LCD_WF51TO48_OFFSET)
+#define KINETIS_LCD_WF55TO52         (KINETIS_SLCD_BASE+KINETIS_LCD_WF55TO52_OFFSET)
+#define KINETIS_LCD_WF59TO56         (KINETIS_SLCD_BASE+KINETIS_LCD_WF59TO56_OFFSET)
+#define KINETIS_LCD_WF63TO60         (KINETIS_SLCD_BASE+KINETIS_LCD_WF63TO60_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* LCD general control register */
+#define LCD_GCR_
+/* LCD auxiliary register */
+#define LCD_AR_
+/* LCD fault detect control register */
+#define LCD_FDCR_
+/* LCD fault detect status register */
+#define LCD_FDSR_
+/* LCD pin enable register */
+#define LCD_PENL_
+/* LCD pin enable register */
+#define LCD_PENH_
+/* LCD backplane enable register */
+#define LCD_BPENL_
+/* LCD backplane enable register */
+#define LCD_BPENH_
+/* LCD waveform register */
+#define LCD_WF3TO0_
+/* LCD waveform register */
+#define LCD_WF7TO4_
+/* LCD waveform register */
+#define LCD_WF11TO8_
+/* LCD waveform register */
+#define LCD_WF15TO12_
+/* LCD waveform register */
+#define LCD_WF19TO16_
+/* LCD waveform register */
+#define LCD_WF23TO20_
+/* LCD waveform register */
+#define LCD_WF27TO24_
+/* LCD waveform register */
+#define LCD_WF31TO28_
+/* LCD waveform register */
+#define LCD_WF35TO32_
+/* LCD waveform register */
+#define LCD_WF39TO36_
+/* LCD waveform register */
+#define LCD_WF43TO40_
+/* LCD waveform register */
+#define LCD_WF47TO44_
+/* LCD waveform register */
+#define LCD_WF51TO48_
+/* LCD waveform register */
+#define LCD_WF55TO52_
+/* LCD waveform register */
+#define LCD_WF59TO56_
+/* LCD waveform register */
+#define LCD_WF63TO60_
+
+                (1 << nn)  /* Bit nn:  
+_SHIFT          (nn)       /* Bits nn-nn: 
+_MASK           (nn << nn)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_tsi.h b/nuttx/arch/arm/src/kinetis/kinetis_tsi.h
new file mode 100644
index 000000000..ac0687b98
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_tsi.h
@@ -0,0 +1,152 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_tsi.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_TSI_GENCS_OFFSET       0x0000 /* General Control and Status Register */
+#define KINETIS_TSI_SCANC_OFFSET       0x0004 /* SCAN control register */
+#define KINETIS_TSI_PEN_OFFSET         0x0008 /* Pin enable register */
+#define KINETIS_TSI_STATUS_OFFSET      0x000c /* Status Register */
+
+#define KINETIS_TSI_CNTR_OFFSET(n)     (0x0100+(((n)-1)<<1) /* Counter Register n */
+#define KINETIS_TSI_CNTR1_OFFSET       0x0100 /* Counter Register 1 */
+#define KINETIS_TSI_CNTR3_OFFSET       0x0104 /* Counter Register 3 */
+#define KINETIS_TSI_CNTR5_OFFSET       0x0108 /* Counter Register 5 */
+#define KINETIS_TSI_CNTR7_OFFSET       0x010c /* Counter Register 7 */
+#define KINETIS_TSI_CNTR9_OFFSET       0x0110 /* Counter Register 9 */
+#define KINETIS_TSI_CNTR11_OFFSET      0x0114 /* Counter Register 11 */
+#define KINETIS_TSI_CNTR13_OFFSET      0x0118 /* Counter Register 13 */
+#define KINETIS_TSI_CNTR15_OFFSET      0x011c /* Counter Register 15 */
+
+#define KINETIS_TSI_THRESHLD_OFFSET(n) (0x0120+((n)<<2)) /* Channel n threshold register */
+#define KINETIS_TSI_THRESHLD0_OFFSET   0x0120 /* Channel 0 threshold register */
+#define KINETIS_TSI_THRESHLD1_OFFSET   0x0124 /* Channel 1 threshold register */
+#define KINETIS_TSI_THRESHLD2_OFFSET   0x0128 /* Channel 2 threshold register */
+#define KINETIS_TSI_THRESHLD3_OFFSET   0x012c /* Channel 3 threshold register */
+#define KINETIS_TSI_THRESHLD4_OFFSET   0x0130 /* Channel 4 threshold register */
+#define KINETIS_TSI_THRESHLD5_OFFSET   0x0134 /* Channel 5 threshold register */
+#define KINETIS_TSI_THRESHLD6_OFFSET   0x0138 /* Channel 6 threshold register */
+#define KINETIS_TSI_THRESHLD7_OFFSET   0x013c /* Channel 7 threshold register */
+#define KINETIS_TSI_THRESHLD8_OFFSET   0x0140 /* Channel 8 threshold register */
+#define KINETIS_TSI_THRESHLD9_OFFSET   0x0144 /* Channel 9 threshold register */
+#define KINETIS_TSI_THRESHLD10_OFFSET  0x0148 /* Channel 10 threshold register */
+#define KINETIS_TSI_THRESHLD11_OFFSET  0x014c /* Channel 11 threshold register */
+#define KINETIS_TSI_THRESHLD12_OFFSET  0x0150 /* Channel 12 threshold register */
+#define KINETIS_TSI_THRESHLD13_OFFSET  0x0154 /* Channel 13 threshold register */
+#define KINETIS_TSI_THRESHLD14_OFFSET  0x0158 /* Channel 14 threshold register */
+#define KINETIS_TSI_THRESHLD15_OFFSET  0x015c /* Channel 15 threshold register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_TSI0_GENCS             (KINETIS_TSI0_BASE+KINETIS_TSI_GENCS_OFFSET)
+#define KINETIS_TSI0_SCANC             (KINETIS_TSI0_BASE+KINETIS_TSI_SCANC_OFFSET)
+#define KINETIS_TSI0_PEN               (KINETIS_TSI0_BASE+KINETIS_TSI_PEN_OFFSET)
+#define KINETIS_TSI0_STATUS            (KINETIS_TSI0_BASE+KINETIS_TSI_STATUS_OFFSET)
+
+#define KINETIS_TSI0_CNTR              (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR_OFFSET(n))
+#define KINETIS_TSI0_CNTR1             (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR1_OFFSET)
+#define KINETIS_TSI0_CNTR3             (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR3_OFFSET)
+#define KINETIS_TSI0_CNTR5             (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR5_OFFSET)
+#define KINETIS_TSI0_CNTR7             (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR7_OFFSET)
+#define KINETIS_TSI0_CNTR9             (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR9_OFFSET)
+#define KINETIS_TSI0_CNTR11            (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR11_OFFSET)
+#define KINETIS_TSI0_CNTR13            (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR13_OFFSET)
+#define KINETIS_TSI0_CNTR15            (KINETIS_TSI0_BASE+KINETIS_TSI_CNTR15_OFFSET)
+
+#define KINETIS_TSI0_THRESHLD(n)       (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD_OFFSET(n))
+#define KINETIS_TSI0_THRESHLD0         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD0_OFFSET)
+#define KINETIS_TSI0_THRESHLD1         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD1_OFFSET)
+#define KINETIS_TSI0_THRESHLD2         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD2_OFFSET)
+#define KINETIS_TSI0_THRESHLD3         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD3_OFFSET)
+#define KINETIS_TSI0_THRESHLD4         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD4_OFFSET)
+#define KINETIS_TSI0_THRESHLD5         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD5_OFFSET)
+#define KINETIS_TSI0_THRESHLD6         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD6_OFFSET)
+#define KINETIS_TSI0_THRESHLD7         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD7_OFFSET)
+#define KINETIS_TSI0_THRESHLD8         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD8_OFFSET)
+#define KINETIS_TSI0_THRESHLD9         (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD9_OFFSET)
+#define KINETIS_TSI0_THRESHLD10        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD10_OFFSET)
+#define KINETIS_TSI0_THRESHLD11        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD11_OFFSET)
+#define KINETIS_TSI0_THRESHLD12        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD12_OFFSET)
+#define KINETIS_TSI0_THRESHLD13        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD13_OFFSET)
+#define KINETIS_TSI0_THRESHLD14        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD14_OFFSET)
+#define KINETIS_TSI0_THRESHLD15        (KINETIS_TSI0_BASE+KINETIS_TSI_THRESHLD15_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* General Control and Status Register */
+#define TSI_GENCS_
+/* SCAN control register */
+#define TSI_SCANC_
+/* Pin enable register */
+#define TSI_PEN_
+/* Status Register */
+#define TSI_STATUS_
+/* Counter Register n */
+#define TSI_CNTR_
+/* Channel n threshold register */
+#define TSI_THRESHLD_
+
+                (1 << nn)  /* Bit nn:  
+_SHIFT          (nn)       /* Bits nn-nn: 
+_MASK           (nn << nn)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h b/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h
new file mode 100644
index 000000000..cfbb28a97
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h
@@ -0,0 +1,141 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_usbdcd.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_USBDCD_CONTROL_OFFSET    0x0000 /* Control Register */
+#define KINETIS_USBDCD_CLOCK_OFFSET      0x0004 /* Clock Register */
+#define KINETIS_USBDCD_STATUS_OFFSET     0x0008 /* Status Register */
+#define KINETIS_USBDCD_TIMER0_OFFSET     0x0010 /* TIMER0 Register */
+#define KINETIS_USBDCD_TIMER1_OFFSET     0x0014 /* TIMER1 Register */
+#define KINETIS_USBDCD_TIMER2_OFFSET     0x0018 /* TIMER2 Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_USBDCD_CONTROL           (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CONTROL_OFFSET)
+#define KINETIS_USBDCD_CLOCK             (KINETIS_USBDCD_BASE+KINETIS_USBDCD_CLOCK_OFFSET)
+#define KINETIS_USBDCD_STATUS            (KINETIS_USBDCD_BASE+KINETIS_USBDCD_STATUS_OFFSET)
+#define KINETIS_USBDCD_TIMER0            (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER0_OFFSET)
+#define KINETIS_USBDCD_TIMER1            (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER1_OFFSET)
+#define KINETIS_USBDCD_TIMER2            (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Control Register */
+#define USBDCD_CONTROL_IACK              (1 << 0)  /* Bit 0:  Interrupt Acknowledge */
+                                                   /* Bits 1-7:  Reserved */
+#define USBDCD_CONTROL_IF                (1 << 8)  /* Bit 8:  Interrupt Flag */
+                                                   /* Bits 9-15:  Reserved */
+#define USBDCD_CONTROL_IE                (1 << 16) /* Bit 16: Interrupt Enable */
+                                                   /* Bits 17-23:  Reserved */
+#define USBDCD_CONTROL_START             (1 << 24) /* Bit 24: Start Change Detection Sequence */
+#define USBDCD_CONTROL_SR                (1 << 25) /* Bit 25: Software Reset */
+                                                   /* Bits 26-31:  Reserved */
+/* Clock Register */
+#define USBDCD_CLOCK_UNIT                (1 << 0)  /* Bit 0:  Unit of measurement encoding for Clock Speed */
+                                                   /* Bit 1:  Reserved */
+#define USBDCD_CLOCK_SPEED_SHIFT         (2)       /* Bits 2-11: Value of Clock Speed */
+#define USBDCD_CLOCK_SPEED_MASK          (0x3ff << USBDCD_CLOCK_SPEED_SHIFT)
+                                                   /* Bits 12-31:  Reserved */
+/* Status Register */
+                                                   /* Bits 0-15:  Reserved */
+#define USBDCD_STATUS_SEQ_RES_SHIFT      (16)      /* Bits 16-17: Charger Detection Sequence Results */
+#define USBDCD_STATUS_SEQ_RES_MASK       (3 << USBDCD_STATUS_SEQ_RES_SHIFT)
+#  define USBDCD_STATUS_SEQ_RES_NONE     (0 << USBDCD_STATUS_SEQ_RES_SHIFT) /* No results */
+#  define USBDCD_STATUS_SEQ_RES_STD      (1 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Standard host */
+#  define USBDCD_STATUS_SEQ_RES_CHGPORT  (2 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Charging port */
+#  define USBDCD_STATUS_SEQ_RES_DEDCTD   (3 << USBDCD_STATUS_SEQ_RES_SHIFT) /* Dedicated charge */
+#define USBDCD_STATUS_SEQ_STAT_SHIFT     (18)      /* Bits 18-19: Charger Detection Sequence Stat */
+#define USBDCD_STATUS_SEQ_STAT_MASK      (3 << USBDCD_STATUS_SEQ_STAT_SHIFT)
+#  define USBDCD_STATUS_SEQ_STAT_DISAB   (0 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Not enabled or data pins not detected */
+#  define USBDCD_STATUS_SEQ_STAT_DATPIN  (1 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Data pin contact detection complete */
+#  define USBDCD_STATUS_SEQ_STAT_CHGDET  (2 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger detection is complete */
+#  define USBDCD_STATUS_SEQ_STAT_CHGTYPE (3 << USBDCD_STATUS_SEQ_STAT_SHIFT) /* Charger type detection complete */
+#define USBDCD_STATUS_ERR                (1 << 20) /* Bit 20: Error Flag */
+#define USBDCD_STATUS_TO                 (1 << 21) /* Bit 21: Timeout Flag */
+#define USBDCD_STATUS_ACTIVE             (1 << 22) /* Bit 22: Active Status Indicator */
+                                                   /* Bits 23-31:  Reserved */
+/* TIMER0 Register */
+
+#define USBDCD_TIMER0_TUNITCON_SHIFT     (0)       /* Bits 0-11: Unit Connection Timer Elapse (in ms) */
+#define USBDCD_TIMER0_TUNITCON_MASK      (0xfff << USBDCD_TIMER0_TUNITCON_SHIFT)
+                                                   /* Bits 12-15:  Reserved */
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT    (16)      /* Bits 16-25: Sequence Initiation Time */
+#define USBDCD_TIMER0_TSEQ_INIT_MASK     (0x3ff << USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+                                                   /* Bits 26-31:  Reserved */
+/* TIMER1 Register */
+
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT   (0)       /* Bits 0-9: Time Period Comparator Enabled */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK    (0x3ff << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+                                                   /* Bits 10-15:  Reserved */
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT    (16)      /* Bits 16-25: Time Period to Debounce D+ Signal */
+#define USBDCD_TIMER1_TDCD_DBNC__MASK    (0x3ff << USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+                                                   /* Bits 26-31:  Reserved */
+/* TIMER2 Register */
+                                                   /* Bits 26-31:  Reserved */
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT  (16)      /* Bits 16-25: Time Period Before Enabling D+ Pullup */
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK   (0x3ff << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)
+                                                   /* Bits 4-15:  Reserved */
+#define USBDCD_TIMER2_CHECK_DM_SHIFT     (0)       /* Bits 0-3: Time Before Check of D- Line */
+#define USBDCD_TIMER2_CHECK_DM_MASK      (15 << USBDCD_TIMER2_CHECK_DM_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h b/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h
index 743a7d138..9219398e7 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -146,66 +146,172 @@
 
 /* Register Bit Definitions *****************************************************************/
 
-/* Peripheral ID Register */
-#define KINETIS_USB_PERID_
-/* Peripheral ID Complement Register */
-#define KINETIS_USB_IDCOMP_
-/* Peripheral Revision Register */
-#define KINETIS_USB_REV_
-/* Peripheral Additional Info Register */
-#define KINETIS_USB_ADDINFO_
-/* OTG Interrupt Status Register */
-#define KINETIS_USB_OTGISTAT_
-/* OTG Interrupt Control Register */
-#define KINETIS_USB_OTGICR_
-/* OTG Status Register */
-#define KINETIS_USB_OTGSTAT_
-/* OTG Control Register */
-#define KINETIS_USB_OTGCTL_
-/* Interrupt Status Register */
-#define KINETIS_USB_ISTAT_
-/* Interrupt Enable Register */
-#define KINETIS_USB_INTEN_
-/* Error Interrupt Status Register */
-#define KINETIS_USB_ERRSTAT_
-/* Error Interrupt Enable Register */
-#define KINETIS_USB_ERREN_
-/* Status Register */
-#define KINETIS_USB_STAT_
-/* Control Register */
-#define KINETIS_USB_CTL_
-/* Address Register */
-#define KINETIS_USB_ADDR_
-/* BDT Page Register 1 */
-#define KINETIS_USB_BDTPAGE1_
-/* Frame Number Register Low */
-#define KINETIS_USB_FRMNUML_
-/* Frame Number Register High */
-#define KINETIS_USB_FRMNUMH_
-/* Token Register */
-#define KINETIS_USB_TOKEN_
-/* SOF Threshold Register */
-#define KINETIS_USB_SOFTHLD_
-/* BDT Page Register 2 */
-#define KINETIS_USB_BDTPAGE2_
-/* BDT Page Register 3 */
-#define KINETIS_USB_BDTPAGE3_
-
-/* Endpoint n Control Register */
-#define KINETIS_USB_ENDPT_
-
-/* USB Control Register */
-#define KINETIS_USB_USBCTRL_
-/* USB OTG Observe Register */
-#define KINETIS_USB_OBSERVE_
-/* USB OTG Control Register */
-#define KINETIS_USB_CONTROL_
-/* USB Transceiver Control Register 0 */
-#define KINETIS_USB_USBTRC0_
-
-                (1 << nn)  /* Bit nn:  
-_SHIFT          (nn)       /* Bits nn-nn: 
-_MASK           (nn << nn)
+/* Peripheral ID Register (8-bit) */
+                                              /* Bits 6-7: Reserved */
+#define USB_PERID_MASK              (0x3f)    /* Bits 0-5: Peripheral identification bits */
+
+/* Peripheral ID Complement Register (8-bit) */
+#define USB_IDCOMP_
+                                              /* Bits 6-7: Reserved */
+#define USB_IDCOMP_MASK             (0x3f)    /* Bits 0-5: Ones complement of peripheral identification bits */
+
+/* Peripheral Revision Register (8-bit revision number) */
+
+/* Peripheral Additional Info Register (8-bit) */
+
+#define USB_ADDINFO_IEHOST          (1 << 0)  /* Bit 0:  This bit is set if host mode is enabled */
+                                              /* Bits 1-2: Reserved */
+#define USB_ADDINFO_IRQNUM_SHIFT    (3)       /* Bits 3-7: Assigned Interrupt Request Number */
+#define USB_ADDINFO_IRQNUM_MASK     (31 << USB_ADDINFO_IRQNUM_SHIFT)
+
+/* OTG Interrupt Status Register(8-bit)  */
+
+#define USB_OTGISTAT_AVBUSCHG       (1 << 0)  /* Bit 0:  Change in VBUS is detected on an A device */
+                                              /* Bit 1:  Reserved */
+#define USB_OTGISTAT_B_SESS_CHG     (1 << 2)  /* Bit 2:  Change in VBUS is detected on a B device */
+#define USB_OTGISTAT_SESSVLDCHG     (1 << 3)  /* Bit 3:  Change in VBUS is detected */
+                                              /* Bit 4:  Reserved */
+#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5)  /* Bit 5:  Change USB line state */
+#define USB_OTGISTAT_ONEMSEC        (1 << 6)  /* Bit 6:  Set when the 1 millisecond timer expires */
+#define USB_OTGISTAT_IDCHG          (1 << 7)  /* Bit 7:  Change in ID Signal from the USB connector */
+
+/* OTG Interrupt Control Register (8-bit) */
+
+#define USB_OTGICR_AVBUSEN          (1 << 0)  /* Bit 0:  A VBUS Valid interrupt enable */
+                                              /* Bit 1:  Reserved */
+#define USB_OTGICR_BSESSEN          (1 << 2)  /* Bit 2:  B Session END interrupt enable */
+#define USB_OTGICR_SESSVLDEN        (1 << 3)  /* Bit 3:  Session valid interrupt enable */
+                                              /* Bit 4:  Reserved */
+#define USB_OTGICR_LINESTATEEN      (1 << 5)  /* Bit 5:  Line State change interrupt enable */
+#define USB_OTGICR_ONEMSECEN        (1 << 6)  /* Bit 6:  1 millisecond interrupt enable */
+#define USB_OTGICR_IDEN             (1 << 7)  /* Bit 7:  ID interrupt enable */
+
+/* OTG Status Register (8-bit) */
+
+#define USB_OTGSTAT_AVBUSVLD        (1 << 0)  /* Bit 0:  A VBUS Valid */
+                                              /* Bit 1:  Reserved */
+#define USB_OTGSTAT_BSESSEND        (1 << 2)  /* Bit 2:  B Session END */
+#define USB_OTGSTAT_SESS_VLD        (1 << 3)  /* Bit 3:  Session valid */
+                                              /* Bit 4:  Reserved */
+#define USB_OTGSTAT_LINESTATESTABLE (1 << 5)  /* Bit 5:  OTGISTAT LINE_STATE_CHG bit stable */
+#define USB_OTGSTAT_ONEMSECEN       (1 << 6)  /* Bit 6:  Reserved for the 1msec count */
+#define USB_OTGSTAT_ID              (1 << 7)  /* Bit 7:  Current state of the ID pin on the USB connector */
+
+/* OTG Control Register (8-bit) */
+                                              /* Bits 0-1:  Reserved */
+#define USB_OTGCTL_OTGEN            (1 << 2)  /* Bit 2:  On-The-Go pullup/pulldown resistor enable */
+                                              /* Bit 3:  Reserved */
+#define USB_OTGCTL_DMLOW            (1 << 4)  /* Bit 4:  D- Data Line pull-down resistor enable */
+#define USB_OTGCTL_DPLOW            (1 << 5)  /* Bit 5:  D+ Data Line pull-down resistor enable */
+                                              /* Bit 6:  Reserved */
+#define USB_OTGCTL_DPHIGH           (1 << 7)  /* Bit 7: D+ Data Line pullup resistor enable */
+
+/* Interrupt Status Register Interrupt Enable Register (8-bit) */
+
+#define USB_INT_USBRST              (1 << 0)  /* Bit 0:  USB Module has decoded a valid USB reset */
+#define USB_INT_ERROR               (1 << 1)  /* Bit 1:  Any of the error conditions within the ERRSTAT register */
+#define USB_INT_SOFTOK              (1 << 2)  /* Bit 2:  USB Module received a Start Of Frame (SOF) token */
+#define USB_INT_TOKDNE              (1 << 3)  /* Bit 3:  Current token being processed has completed */
+#define USB_INT_SLEEP               (1 << 4)  /* Bit 4:  Constant idle on the USB bus for 3 milliseconds */
+#define USB_INT_RESUME              (1 << 5)  /* Bit 5:  Signal remote wake-up signaling */
+#define USB_INT_ATTACH              (1 << 6)  /* Bit 6:  Attach Interrupt */
+#define USB_INT_STALL               (1 << 7)  /* Bit 7:  Stall Interrupt */
+
+/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
+
+#define USB_ERRSTAT_PIDERR          (1 << 0)  /* Bit 0:  This bit is set when the PID check field fails */
+#define USB_ERRSTAT_CRC5EOF         (1 << 1)  /* Bit 1:  Host data CRC error or End of frame errors */
+#define USB_ERRSTAT_CRC16           (1 << 2)  /* Bit 2:  Data packet is rejected due to a CRC16 error */
+#define USB_ERRSTAT_DFN8            (1 << 3)  /* Bit 3:  Data field received was not 8 bits in length */
+#define USB_ERRSTAT_BTOERR          (1 << 4)  /* Bit 4:  Bus turnaround timeout error occurred */
+#define USB_ERRSTAT_DMAERR          (1 << 5)  /* Bit 5:  DMA error */
+                                              /* Bit 6:  Reserved */
+#define USB_ERRSTAT_BTSERR          (1 << 7)  /* Bit 7:  Bit stuff error is detected */
+
+/* Status Register (8-bit) */
+
+                                              /* Bits 0-1:  Reserved */
+#define USB_STAT_ODD                (1 << 2)  /* Bit 2:  Last Buffer Descriptor was in the odd bank of the BDT */
+#define USB_STAT_TX                 (1 << 3)  /* Bit 3:  Transmit Indicator */
+#define USB_STAT_ENDP_SHIFT         (4)       /* Bits 4-7: Endpoint address that received or transmitted the token */
+#define USB_STAT_ENDP_MASK          (15 << USB_STAT_ENDP_SHIFT)
+
+/* Control Register (8-bit) */
+
+#define USB_CTL_USBENSOFEN          (1 << 0)  /* Bit 0:  USB Enable */
+#define USB_CTL_ODDRST              (1 << 1)  /* Bit 1:  Resets all the BDT ODD ping/pong bits to 0 */
+#define USB_CTL_RESUME              (1 << 2)  /* Bit 2:  Enables the USB Module to execute resume signaling */
+#define USB_CTL_HOSTMODEEN          (1 << 3)  /* Bit 3:  Enables the USB Module to operate in Host mode */
+#define USB_CTL_RESET               (1 << 4)  /* Bit 4:  Enables the USB Module to generate USB reset signaling */
+#define USB_CTL_TXSUSPENDTOKENBUSY  (1 << 5)  /* Bit 5:  USB Module is busy executing a USB token */
+#define USB_CTL_SE0                 (1 << 6)  /* Bit 6:  Live USB Single Ended Zero signal */
+#define USB_CTL_JSTATE              (1 << 7)  /* Bit 7:  Live USB differential receiver JSTATE signal */
+
+/* Address Register (8-bit) */
+
+#define USB_ADDR_LSEN               (1 << 7)  /* Bit 7:  Low Speed Enable bit */
+#define USB_ADDR_SHIFT              (0)       /* Bits 0-6: USB address */
+#define USB_ADDR_MASK               (0x7f << USB_ADDR_SHIFT)
+
+/* BDT Page Register 1 (8-bit) */
+                                              /* Bit 0:  Reserved */
+#define USB_BDTPAGE1_SHIFT          (1)       /* Bits 1-7: Address bits 9-15 of the BDT base address */
+#define USB_BDTPAGE1_MASK           (0x7f << USB_BDTPAGE1_SHIFT)
+
+/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
+/* Frame Number Register High (8-bit) */
+                                              /* Bits 3-7:  Reserved */
+#define USB_FRMNUMH_SHIFT           (0)       /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
+#define USB_FRMNUMH_MASK            (7 << USB_FRMNUMH_SHIFT)
+
+/* Token Register (8-bit) */
+
+#define USB_TOKEN_ENDPT_SHIFT       (0)       /* Bits 0-3: Endpoint address for the token command */
+#define USB_TOKEN_ENDPT_MASK        (15 << USB_TOKEN_ENDPT_SHIFT)
+#define USB_TOKEN_PID_SHIFT         (4)       /* Bits 4-7: Token type executed by the USB Module */
+#define USB_TOKEN_PID_MASK          (15 << USB_TOKEN_PID_SHIFT)
+#  define USB_TOKEN_PID_OUT         (1 << USB_TOKEN_PID_SHIFT)  /* OUT Token */
+#  define USB_TOKEN_PID_IN          (9 << USB_TOKEN_PID_SHIFT)  /* IN Token */
+#  define USB_TOKEN_PID_SETUP       (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */
+
+/* SOF Threshold Register (8-bit count value) */
+/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */
+
+/* Endpoint n Control Register (8-bit) */
+
+#define USB_ENDPT_EPHSHK            (1 << 0)  /* Bit 0:  Enable handshaking during a transaction to the endpoint */
+#define USB_ENDPT_EPSTALL           (1 << 1)  /* Bit 1:  Endpoint is stalled */
+#define USB_ENDPT_EPTXEN            (1 << 2)  /* Bit 2:  Enable the endpoint for TX transfers */
+#define USB_ENDPT_EPRXEN            (1 << 3)  /* Bit 3:  Enable the endpoint for RX transfers */
+#define USB_ENDPT_EPCTLDIS          (1 << 4)  /* Bit 4:  Disable control (SETUP) transfers */
+                                              /* Bit 5:  Reserved */
+#define USB_ENDPT_RETRYDIS          (1 << 6)  /* Bit 6:  Disable host retry NAK'ed transactions (host EP0) */
+#define USB_ENDPT_HOSTWOHUB         (1 << 7)  /* Bit 7:  Allows the host to communicate to a low speed device (host EP0) */
+
+/* USB Control Register (8-bit) */
+                                              /* Bits 0-5:  Reserved */
+#define USB_USBCTRL_PDE             (1 << 6)  /* Bit 6:  Enables the weak pulldowns on the USB transceiver */
+#define USB_USBCTRL_SUSP            (1 << 7)  /* Bit 7:  Places the USB transceiver into the suspend state */
+
+/* USB OTG Observe Register (8-bit) */
+                                              /* Bits 0-3:  Reserved */
+#define USB_OBSERVE_DMPD            (1 << 4)  /* Bit 4:  D- Pull Down signal output from the USB OTG module */
+                                              /* Bit 5:  Reserved */
+#define USB_OBSERVE_DPPD            (1 << 6)  /* Bit 6:  D+ Pull Down signal output from the USB OTG module */
+#define USB_OBSERVE_DPPU            (1 << 7)  /* Bit 7:  D+ Pull Up signal output from the USB OTG module */
+
+/* USB OTG Control Register (8-bit) */
+                                              /* Bits 0-3:  Reserved */
+#define USB_CONTROL_DPPULLUPNONOTG  (1 << 4)  /* Bit 4:  Controls of the DP PULLUP in the USB OTG module */
+                                              /* Bits 5-7:  Reserved */
+/* USB Transceiver Control Register 0 (8-bit) */
+
+#define USB_USBTRC0_USBRESET        (1 << 7)  /* Bit 7:  USB reset */
+                                              /* Bit 6:  Reserved */
+#define USB_USBTRC0_USBRESMEN       (1 << 5)  /* Bit 5:  Asynchronous Resume Interrupt Enable */
+                                              /* Bits 2-4:  Reserved */
+#define USB_USBTRC0_SYNC_DET        (1 << 1)  /* Bit 1:  Synchronous USB Interrupt Detect */
+#define USB_USBTRC0_RESUME_INT      (1 << 0)  /* Bit 0:  USB Asynchronous Interrupt */
 
 /********************************************************************************************
  * Public Types