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| author | Mark Whitehorn <kd0aij@gmail.com> | 2014-11-02 16:48:17 -0700 |
|---|---|---|
| committer | Mark Whitehorn <kd0aij@gmail.com> | 2014-11-02 16:48:17 -0700 |
| commit | 0a56b91ada317f40e9f51b386a24bcde71894cfb (patch) | |
| tree | bc3c4a3f1ba30cf544e174b825415cce9888c775 | |
| parent | 26f809f669b1a9cee9c74014cf3a00d17fe7cd62 (diff) | |
| parent | be11f4038578d1f1f37ee3aa40913511af6c1b18 (diff) | |
| download | px4-nuttx-0a56b91ada317f40e9f51b386a24bcde71894cfb.tar.gz px4-nuttx-0a56b91ada317f40e9f51b386a24bcde71894cfb.tar.bz2 px4-nuttx-0a56b91ada317f40e9f51b386a24bcde71894cfb.zip | |
Merge branch 'master' of git://git.code.sf.net/p/nuttx/git
76 files changed, 16270 insertions, 260 deletions
diff --git a/apps/examples/serialblaster/serialblaster_main.c b/apps/examples/serialblaster/serialblaster_main.c index e3e71a4df..7ca5ebe8a 100644 --- a/apps/examples/serialblaster/serialblaster_main.c +++ b/apps/examples/serialblaster/serialblaster_main.c @@ -64,7 +64,7 @@ static const char s[] = "abcdefghijklmnopqrstuvwxyz"; ****************************************************************************/ /**************************************************************************** - * serloop_main + * serialblaster_main ****************************************************************************/ #ifdef CONFIG_BUILD_KERNEL diff --git a/apps/examples/serialrx/serialrx_main.c b/apps/examples/serialrx/serialrx_main.c index 1a8279694..4fe60929f 100644 --- a/apps/examples/serialrx/serialrx_main.c +++ b/apps/examples/serialrx/serialrx_main.c @@ -66,7 +66,7 @@ static int count = 0; ****************************************************************************/ /**************************************************************************** - * serloop_main + * serialrx_main ****************************************************************************/ #ifdef CONFIG_BUILD_KERNEL diff --git a/apps/examples/serloop/serloop_main.c b/apps/examples/serloop/serloop_main.c index 7fad24501..f573a4c7c 100644 --- a/apps/examples/serloop/serloop_main.c +++ b/apps/examples/serloop/serloop_main.c @@ -79,6 +79,7 @@ int serloop_main(int argc, char *argv[]) { ch = '.'; } + putchar(ch); } #else @@ -96,6 +97,7 @@ int serloop_main(int argc, char *argv[]) { ch = '.'; } + ret = write(1, &ch, 1); } #endif diff --git a/apps/nshlib/nsh_telnetd.c b/apps/nshlib/nsh_telnetd.c index bbb0393f7..0602081cb 100644 --- a/apps/nshlib/nsh_telnetd.c +++ b/apps/nshlib/nsh_telnetd.c @@ -41,6 +41,7 @@ #include <stdio.h> #include <unistd.h> +#include <ctype.h> #include <assert.h> #include <debug.h> #include <string.h> @@ -95,7 +96,7 @@ ****************************************************************************/ #ifdef CONFIG_NSH_TELNET_LOGIN -void nsh_telnetecho(struct console_stdio_s *pstate, uint8_t is_use) +static void nsh_telnetecho(FAR struct console_stdio_s *pstate, uint8_t is_use) { uint8_t optbuf[4]; optbuf[0] = TELNET_IAC; @@ -108,11 +109,96 @@ void nsh_telnetecho(struct console_stdio_s *pstate, uint8_t is_use) #endif /**************************************************************************** + * Name: nsh_telnettoken + ****************************************************************************/ + +#ifdef CONFIG_NSH_TELNET_LOGIN +static void nsh_telnettoken(FAR struct console_stdio_s *pstate, + FAR char *buffer, size_t buflen) +{ + FAR char *start; + FAR char *endp1; + bool quoted = false; + + /* Find the start of token. Either (1) the first non-white space + * character on the command line or (2) the character immediately after + * a quotation mark. + */ + + for (start = pstate->cn_line; *start; start++) + { + /* Does the token open with a quotation mark */ + + if (*start == '"') + { + /* Yes.. break out with start set to the character after the + * quotation mark. + */ + + quoted = true; + start++; + break; + } + + /* No, then any non-whitespace is the first character of the token */ + + else if (!isspace(*start)) + { + /* Break out with start set to the first character of the token */ + + break; + } + } + + /* Find the terminating character after the token on the command line. The + * terminating character is either (1) the matching quotation mark, or (2) + * any whitespace. + */ + + for (endp1 = start; *endp1; endp1++) + { + /* Did the token begin with a quotation mark? */ + + if (quoted) + { + /* Yes.. then only the matching quotation mark (or end of string) + * terminates + */ + + if (*endp1 == '"') + { + /* Break out... endp1 points to closing quotation mark */ + + break; + } + } + + /* No.. any whitespace (or end of string) terminates */ + + else if (isspace(*endp1)) + { + /* Break out... endp1 points to first while space encountered */ + + break; + } + } + + /* Replace terminating character with a NUL terminator */ + + *endp1 = '\0'; + + /* Copied the token into the buffer */ + + strncpy(buffer, start, buflen); +} +#endif + +/**************************************************************************** * Name: nsh_telnetlogin ****************************************************************************/ #ifdef CONFIG_NSH_TELNET_LOGIN -int nsh_telnetlogin(struct console_stdio_s *pstate) +static int nsh_telnetlogin(FAR struct console_stdio_s *pstate) { char username[16]; char password[16]; @@ -133,8 +219,9 @@ int nsh_telnetlogin(struct console_stdio_s *pstate) fflush(pstate->cn_outstream); if (fgets(pstate->cn_line, CONFIG_NSH_LINELEN, INSTREAM(pstate)) != NULL) { - strncpy(username, pstate->cn_line, sizeof(username)); - username[sizeof(username) - 1] = 0; + /* Parse out the username */ + + nsh_telnettoken(pstate, username, sizeof(username)); } /* Ask for the login password */ @@ -144,10 +231,11 @@ int nsh_telnetlogin(struct console_stdio_s *pstate) nsh_telnetecho(pstate, TELNET_NOTUSE_ECHO); if (fgets(pstate->cn_line, CONFIG_NSH_LINELEN, INSTREAM(pstate)) != NULL) { - /* Verify the username and password */ + /* Parse out the password */ - strncpy(password, pstate->cn_line, sizeof(password)); - password[sizeof(password) - 1] = 0; + nsh_telnettoken(pstate, password, sizeof(password)); + + /* Verify the username and password */ if (strcmp(password, CONFIG_NSH_TELNET_PASSWORD) == 0 && strcmp(username, CONFIG_NSH_TELNET_USERNAME) == 0) diff --git a/misc/buildroot/configs/README.txt b/misc/buildroot/configs/README.txt index f7d6a0fab..bfffff293 100644 --- a/misc/buildroot/configs/README.txt +++ b/misc/buildroot/configs/README.txt @@ -262,7 +262,7 @@ Q: Some of my libraries like GMP and MPFR are in non-standard locations the checking for correct version of mpfr.h... no configure: error: Building GCC requires GMP 4.1+ and MPFR 2.3.0+. -A: http://tech.groups.yahoo.com/group/nuttx/message/1160 +A: https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1160 "I think that you can specify the path to GMP and MPFR. I think that GCC has some special configuration command line options to support this. I @@ -361,7 +361,7 @@ Building GDB Under Cygwin ^^^^^^^^^^^^^^^^^^^^^^^^^ This can be tricking, but it has been done. See this message sequence for - http://tech.groups.yahoo.com/group/nuttx/message/726 . Apparently there + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/726 . Apparently there are some incompatibilities with Cygwin 1.7 that require an additional patch. See http://old.nabble.com/-RFA--windows-nat.c%3A-Cygwin%3A-Port-to-Cygwin-1.7-td27735619.html diff --git a/misc/tools/README.txt b/misc/tools/README.txt index 7eaa77fff..6bdedee13 100644 --- a/misc/tools/README.txt +++ b/misc/tools/README.txt @@ -198,7 +198,7 @@ http://uvc.de/posts/linux-kernel-configuration-tool-mconf-under-windows.html [The remainder of the text in this section is for historical interest only] -From http://tech.groups.yahoo.com/group/nuttx/message/2900: +From https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/2900: "The build was quite simple: diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 9eb98f67c..e88e4ba09 100755 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -1278,7 +1278,7 @@ board (Contributed by Dave Marples). * sched/sem_wait.c and sem_waitirq.c: Eliminate a race condition that can occur when a semaphore wait is interrupt by a signal. - (see email thread: http://tech.groups.yahoo.com/group/nuttx/message/530) + (see email thread: https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/530) * drivers/mtd/at45db.c: Add a driver for the Atmel AT45DB161D 4Mbit SPI FLASH part (untested on initial check-in). * arch/arm/src/lm3s and arch/arm/include/lm3s: Corrections for the @@ -8894,3 +8894,12 @@ currently supported in the Nuttx C library (2014-10-27). * include/termios.h, libc/termios/lib_isatty.c, and Make.defs: Add isatty() function. From Alan Carvalho de Assis (2014-10-27). + * arch/arm/include/efm32, src/efm32, and configs/efm32-gxxx-stk: + The EFM32 Gecko Starter Kit port is now functional. At least + NSH is running over LEUART0 on the board (2014-10-29). + * arch/arm/src/sm34/sam_serial.c and Kconfig: Add support for SAM3/4 + basic TERMIOS and flow control. There are issues with IFLOW control: + PDC or DMAC support is required (2014-10-29). + * configs/sam4e-ek/src/sam4e-ek.h: Fix an error in a USART1 pin number + (2014-10-29). + diff --git a/nuttx/Documentation/NXGraphicsSubsystem.html b/nuttx/Documentation/NXGraphicsSubsystem.html index 5c1c1ed81..c8c3e0b83 100644 --- a/nuttx/Documentation/NXGraphicsSubsystem.html +++ b/nuttx/Documentation/NXGraphicsSubsystem.html @@ -3706,7 +3706,7 @@ sudo ln -s libXext.so.6.4.0 libXext.so <b>NOTE</b>: There is a workaround in this case: You can build for 32-bit execution on a 64-bit machine by adding <code>-m3</code> to the <code>CFLAGS</code> and <code>-m32 -m elf_i386</code> to the <code>LDFLAGS</code>. See the patch file <code>0001-Quick-hacks-to-build-sim-nsh-ostest-on-x86_64-as-32-.patch</code> - that can be found in NuttX <a href="http://tech.groups.yahoo.com/group/nuttx/files">files</a>. + that can be found in NuttX <a href="https://groups.yahoo.com/neo/groups/nuttx/files">files</a>. </small></p> </li> <li><p> diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 3ced5565a..39777f9ab 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@ <tr align="center" bgcolor="#e4e4e4"> <td> <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1> - <p>Last Updated: September 28, 2014</p> + <p>Last Updated: October 30, 2014</p> </td> </tr> </table> @@ -1165,7 +1165,7 @@ </table> <p> - Most NuttX-related discussion occurs on the <a href="http://tech.groups.yahoo.com/group/nuttx/" target="_top"><i>Yahoo!</i> NuttX group</a>. + Most NuttX-related discussion occurs on the <a href="https://groups.yahoo.com/neo/groups/nuttx/info" target="_top"><i>Yahoo!</i> NuttX group</a>. You are cordially invited to <a href="http://groups.yahoo.com/group/nuttx/join" target="_top">join</a>. I make a special effort to answer any questions and provide any help that I can. </p> @@ -1262,7 +1262,7 @@ <li><a href="#armcortexa5">ARM Cortex-A5</a> (2)</li> <li><a href="#armcortexa8">ARM Cortex-A8</a> (1)</li> <li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (3)</li> - <li><a href="#armcortexm3">ARM Cortex-M3</a> (27)</li> + <li><a href="#armcortexm3">ARM Cortex-M3</a> (29)</li> <li><a href="#armcortexm4">ARM Cortex-M4</a> (16)</li> </ul> <li>Atmel AVR @@ -1391,6 +1391,12 @@ <li><a href="#m16c">Renesas M16C/26</a></li> </ul> </li> + <li>Silicon Laboratories + <ul> + <li><a href="#efm32g">EFM32 Gecko</a> <small>(ARM Cortex-M3)</small></li> + <li><a href="#emf32gg">EFM32 Giant Gecko</a> <small>(ARM Cortex-M3)</small></li> + </ul> + </li> <li>STMicroelectronics <ul> <li><a href="#str71x">STMicro STR71x</a> <small>(ARM7TDMI)</small></li> @@ -1401,15 +1407,17 @@ <li><a href="#stm32f103x">STMicro STM32F103x</a> <small>(STM32 F1 Family, ARM Cortex-M3)</small></li> <li><a href="#stm32f107x">STMicro STM32F107x</a> <small>(STM32 F1 "Connectivity Line" family, ARM Cortex-M3)</small></li> <li><a href="#stm32f207x">STMicro STM32F207x</a> <small>(STM32 F2 family, ARM Cortex-M3)</small></li> + </ul> + </li> + </td> + <td bgcolor="#e4e4e4" valign="top" width="33%"> + <ul> <li><a href="#stm32303x">STMicro STM32F303x <small>(STM32 F3 family, ARM Cortex-M4)</small></b>.</a></li> <li><a href="#stm32f401x">STMicro STM32F401x</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li> <li><a href="#stm32f407x">STMicro STM32F407x</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li> <li><a href="#stm32f427x">STMicro STM32 F427/437</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li> <li><a href="#stm32f429x">STMicro STM32 F429</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li> </ul> - </li> - </td> - <td bgcolor="#e4e4e4" valign="top" width="33%"> <li>Texas Instruments (some formerly Luminary) <ul> <li><a href="#tms320c5471">TI TMS320-C5471</a> <small>(ARM7TDMI)</small></li> @@ -2274,6 +2282,94 @@ nsh> <td><br></td> <td> <p> + <a name="efm32g"><b>SiLabs EFM32 Gecko</b>.</a> + This is a port for the Silicon Laboraties EFM32 <i>Gecko</i> family. + Board support is available for the following: + </p> + <ol> + <li> + <p> + <b>SiLabs EFM32 Gecko Starter Kit t (EFM32-G8XX-STK)</b>. + The Gecko Starter Kit features: + <p> + <ul> + <li>EFM32G890F128 MCU with 128 kB flash and 16 kB RAM + <li>32.768 kHz crystal (LXFO) and 32 MHz crystal (HXFO) + <li>Advanced Energy Monitoring + <li>Touch slider + <li>4x40 LCD + <li>4 User LEDs + <li>2 pushbutton switches + <li>Reset button and a switch to disconnect the battery. + <li>On-board SEGGER J-Link USB emulator + <li>ARM 20 pin JTAG/SWD standard Debug in/out connector + </ul> + <p> + <b>STATUS</b>. + The basic port is verified and available now. This includes + on-board LED and button support and a serial console available + on LEUART0. A single configuration is available using the + NuttShell NSH and the LEUART0 serial console. + DMA and USART-based SPI supported are included, but not fully tested. + </p> + <p> + Refer to the EFM32 Gecko Starter Kit <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/efm32-g8xx-stk/README.txt"><i>README.txt</i></a> file for further information. + </p> + </li> + <li> + <p> + <b>Olimex EFM32G880F120-STK</b>. + This board features: + </p> + <ul> + <li>EFM32G880F128 with 128 kB flash and 16 kB RAM + <li>32.768 kHz crystal (LXFO) and 32 MHz crystal (HXFO) + <li>LCD custom display + <li>DEBUG connector with ARM 2x10 pin layout for programming/debugging with ARM-JTAG-EW + <li>UEXT connector + <li>EXT extension connector + <li>RS232 connector and driver + <li>Four user buttons + <li>Buzzer + </ul> + <p> + <b>STATUS</b>. + The board suppport is complete but untested because of tool-related issues. An OpenOCD compatible, SWD debugger would be required to make further progress in testing. + </p> + <p> + Refer to the Olimex EFM32G880F120-STK <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/olimex-efm32g880f129-stk/README.txt"><i>README.txt</i></a> for further information. + </p> + </li> + </ol> + </td> +</tr> +<tr> + <td><br></td> + <td><hr></td> +</tr> +<tr> + <td><br></td> + <td> + <p> + <a name="efm32gg"><b>SiLabs EFM32 Giant Gecko</b>.</a> + This is a port for the Silicon Laboraties EFM32 <i>Giant Gecko</i> family. + </p> + <ul> + <p> + <b>STATUS</b>. + At this time there are no board support packages for the <i>Giant Gecko</i> in the NuttX source tree (there are ports to proprietary <i>Giant Gecko</i> hardware, howevever). + </p> + </ul> + </td> +</tr> +<tr> + <td><br></td> + <td><hr></td> +</tr> +<tr> + <td><br></td> + <td> + <p> <a name="stm32l152"><b>STMicro STM32L152 (STM32L "EnergyLite" Line)</b>.</a> This is a port of NuttX to the STMicro STM32L-Discovery development board. The STM32L-Discovery board is based on the STM32L152RBT6 MCU (128KB FLASH and 16KB of SRAM). diff --git a/nuttx/Documentation/NuttXDemandPaging.html b/nuttx/Documentation/NuttXDemandPaging.html index b5fa2f9f2..afaaacf86 100644 --- a/nuttx/Documentation/NuttXDemandPaging.html +++ b/nuttx/Documentation/NuttXDemandPaging.html @@ -129,7 +129,7 @@ This document summarizes the design of NuttX on-demand paging. This feature permits embedded MCUs with some limited RAM space to execute large programs from some non-random access media. This feature was first discussed in this email thread: - <a href="http://tech.groups.yahoo.com/group/nuttx/message/213">http://tech.groups.yahoo.com/group/nuttx/message/213</a>. + <a href="https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/213">https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/213</a>. </p> <p> What kind of platforms can support NuttX on-demang paging? diff --git a/nuttx/Documentation/NuttXLinks.html b/nuttx/Documentation/NuttXLinks.html index f278d8376..1ed75096a 100644 --- a/nuttx/Documentation/NuttXLinks.html +++ b/nuttx/Documentation/NuttXLinks.html @@ -21,7 +21,7 @@ <li><a href="http://www.nuttx.org/Documentation/NuttX.html" target="main">Home</a></li> <li><a href="http://sourceforge.net/projects/nuttx/develop" target="_top">SourceForge</a></li> <li><a href="http://freshmeat.net/projects/nuttx/" target="_top">FreshMeat</a></li> - <li><a href="http://tech.groups.yahoo.com/group/nuttx/" target="_top">Forum</a></li> + <li><a href="https://groups.yahoo.com/neo/groups/nuttx/info" target="_top">Forum</a></li> <li><a href="https://www.ohloh.net/p/nuttx" target="_top">Ohloh</a></li> <li><a href="http://www.oschina.net/p/nuttx" target="_top">OSChina</a></li> <li><a href="http://sourceforge.net/projects/nuttx/files/" target="_top">Downloads</a></li> diff --git a/nuttx/README.txt b/nuttx/README.txt index 61c05d48f..40b5a0d85 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -143,20 +143,38 @@ Installation Directories with Spaces in the Path Downloading from Repositories ----------------------------- -Cloning the Repository + Cloning the Repository - The current NuttX du jour is available in from a GIT repository. Cloning - instructions are available here: + The current NuttX du jour is available in from a GIT repository. Cloning + instructions are available here: - https://sourceforge.net/p/nuttx/git + https://sourceforge.net/p/nuttx/git -Cloning NuttX Inside Cygwin + Configuring the Cone - If you are cloning the NuttX repository, it is recommended to avoid - automatic end of lines conversions by git. These conversions may break - some scripts like configure.sh. Before cloning, do the following: + Set your identity: - git config --global core.autocrlf false + git config --global user.name "My Name" + git config --global user.email my.name@example.com + + Colorized diffs are much easier to read: + + git config --global color.branch auto + git config --global color.diff auto + git config --global color.interactive auto + git config --global color.status auto + + Checkout other settings + + git config --list + + Cloning NuttX Inside Cygwin + + If you are cloning the NuttX repository, it is recommended to avoid + automatic end of lines conversions by git. These conversions may break + some scripts like configure.sh. Before cloning, do the following: + + git config --global core.autocrlf false Notes about Header Files ------------------------ diff --git a/nuttx/TODO b/nuttx/TODO index 37e5be03c..c6145174f 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1406,7 +1406,7 @@ o ARM (arch/arm/) interrupt, the stack pointer may increment and possibly overflow. This can happen only under conditions of continuous interrupts. - See this email thread: http://tech.groups.yahoo.com/group/nuttx/message/1261 + See this email thread: https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1261 On suggested change is: ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */ diff --git a/nuttx/arch/arm/src/armv7-m/etm.h b/nuttx/arch/arm/src/armv7-m/etm.h new file mode 100644 index 000000000..eef1ba85d --- /dev/null +++ b/nuttx/arch/arm/src/armv7-m/etm.h @@ -0,0 +1,916 @@ +/******************************************************************************************************************************* + * arch/arm/src/armv7-m/etm.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_M_ETM_H +#define __ARCH_ARM_SRC_ARMV7_M_ETM_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* ETM Register Base Address ***************************************************************************************************/ + +#define ETM_BASE (0xe0041000ul) + +/* ETM Register Offsets ********************************************************************************************************/ + +#define ETM_ETMCR_OFFSET 0x0000 /* Main Control Register */ +#define ETM_ETMCCR_OFFSET 0x0004 /* Configuration Code Register */ +#define ETM_ETMTRIGGER_OFFSET 0x0008 /* ETM Trigger Event Register */ +#define ETM_ETMSR_OFFSET 0x0010 /* ETM Status Register */ +#define ETM_ETMSCR_OFFSET 0x0014 /* ETM System Configuration Register */ +#define ETM_ETMTEEVR_OFFSET 0x0020 /* ETM TraceEnable Event Register */ +#define ETM_ETMTECR1_OFFSET 0x0024 /* ETM Trace control Register */ +#define ETM_ETMFFLR_OFFSET 0x002c /* ETM Fifo Full Level Register */ +#define ETM_ETMCNTRLDVR1_OFFSET 0x0140 /* Counter Reload Value */ +#define ETM_ETMSYNCFR_OFFSET 0x01e0 /* Synchronisation Frequency Register */ +#define ETM_ETMIDR_OFFSET 0x01e4 /* ID Register */ +#define ETM_ETMCCER_OFFSET 0x01e8 /* Configuration Code Extension Register */ +#define ETM_ETMTESSEICR_OFFSET 0x01f0 /* TraceEnable Start/Stop EmbeddedICE Control Register */ +#define ETM_ETMTSEVR_OFFSET 0x01f8 /* Timestamp Event Register */ +#define ETM_ETMTRACEIDR_OFFSET 0x0200 /* CoreSight Trace ID Register */ +#define ETM_ETMIDR2_OFFSET 0x0208 /* ETM ID Register 2 */ +#define ETM_ETMPDSR_OFFSET 0x0314 /* Device Power-down Status Register */ +#define ETM_ETMISCIN_OFFSET 0x0ee0 /* Integration Test Miscellaneous Inputs Register */ +#define ETM_ITTRIGOUT_OFFSET 0x0ee8 /* Integration Test Trigger Out Register */ +#define ETM_ETMITATBCTR2_OFFSET 0x0ef0 /* ETM Integration Test ATB Control 2 Register */ +#define ETM_ETMITATBCTR0_OFFSET 0x0ef8 /* ETM Integration Test ATB Control 0 Register */ +#define ETM_ETMITCTRL_OFFSET 0x0f00 /* ETM Integration Control Register */ +#define ETM_ETMCLAIMSET_OFFSET 0x0fa0 /* ETM Claim Tag Set Register */ +#define ETM_ETMCLAIMCLR_OFFSET 0x0fa4 /* ETM Claim Tag Clear Register */ +#define ETM_ETMLAR_OFFSET 0x0fb0 /* ETM Lock Access Register */ +#define ETM_ETMLSR_OFFSET 0x0fb4 /* Lock Status Register */ +#define ETM_ETMAUTHSTATUS_OFFSET 0x0fb8 /* ETM Authentication Status Register */ +#define ETM_ETMDEVTYPE_OFFSET 0x0fcc /* CoreSight Device Type Register */ +#define ETM_ETMPIDR4_OFFSET 0x0fd0 /* Peripheral ID4 Register */ +#define ETM_ETMPIDR5_OFFSET 0x0fd4 /* Peripheral ID5 Register */ +#define ETM_ETMPIDR6_OFFSET 0x0fd8 /* Peripheral ID6 Register */ +#define ETM_ETMPIDR7_OFFSET 0x0fdc /* Peripheral ID7 Register */ +#define ETM_ETMPIDR0_OFFSET 0x0fe0 /* Peripheral ID0 Register */ +#define ETM_ETMPIDR1_OFFSET 0x0fe4 /* Peripheral ID1 Register */ +#define ETM_ETMPIDR2_OFFSET 0x0fe8 /* Peripheral ID2 Register */ +#define ETM_ETMPIDR3_OFFSET 0x0fec /* Peripheral ID3 Register */ +#define ETM_ETMCIDR0_OFFSET 0x0ff0 /* Component ID0 Register */ +#define ETM_ETMCIDR1_OFFSET 0x0ff4 /* Component ID1 Register */ +#define ETM_ETMCIDR2_OFFSET 0x0ff8 /* Component ID2 Register */ +#define ETM_ETMCIDR3_OFFSET 0x0ffc /* Component ID3 Register */ + +/* ETM Register Addresses ******************************************************************************************************/ + +#define ETM_ETMCR (ETM_BASE+ETM_ETMCR_OFFSET) +#define ETM_ETMCCR (ETM_BASE+ETM_ETMCCR_OFFSET) +#define ETM_ETMTRIGGER (ETM_BASE+ETM_ETMTRIGGER_OFFSET) +#define ETM_ETMSR (ETM_BASE+ETM_ETMSR_OFFSET) +#define ETM_ETMSCR (ETM_BASE+ETM_ETMSCR_OFFSET) +#define ETM_ETMTEEVR (ETM_BASE+ETM_ETMTEEVR_OFFSET) +#define ETM_ETMTECR1 (ETM_BASE+ETM_ETMTECR1_OFFSET) +#define ETM_ETMFFLR (ETM_BASE+ETM_ETMFFLR_OFFSET) +#define ETM_ETMCNTRLDVR1 (ETM_BASE+ETM_ETMCNTRLDVR1_OFFSET) +#define ETM_ETMSYNCFR (ETM_BASE+ETM_ETMSYNCFR_OFFSET) +#define ETM_ETMIDR (ETM_BASE+ETM_ETMIDR_OFFSET) +#define ETM_ETMCCER (ETM_BASE+ETM_ETMCCER_OFFSET) +#define ETM_ETMTESSEICR (ETM_BASE+ETM_ETMTESSEICR_OFFSET) +#define ETM_ETMTSEVR (ETM_BASE+ETM_ETMTSEVR_OFFSET) +#define ETM_ETMTRACEIDR (ETM_BASE+ETM_ETMTRACEIDR_OFFSET) +#define ETM_ETMIDR2 (ETM_BASE+ETM_ETMIDR2_OFFSET) +#define ETM_ETMPDSR (ETM_BASE+ETM_ETMPDSR_OFFSET) +#define ETM_ETMISCIN (ETM_BASE+ETM_ETMISCIN_OFFSET) +#define ETM_ITTRIGOUT (ETM_BASE+ETM_ITTRIGOUT_OFFSET) +#define ETM_ETMITATBCTR2 (ETM_BASE+ETM_ETMITATBCTR2_OFFSET) +#define ETM_ETMITATBCTR0 (ETM_BASE+ETM_ETMITATBCTR0_OFFSET) +#define ETM_ETMITCTRL (ETM_BASE+ETM_ETMITCTRL_OFFSET) +#define ETM_ETMCLAIMSET (ETM_BASE+ETM_ETMCLAIMSET_OFFSET) +#define ETM_ETMCLAIMCLR (ETM_BASE+ETM_ETMCLAIMCLR_OFFSET) +#define ETM_ETMLAR (ETM_BASE+ETM_ETMLAR_OFFSET) +#define ETM_ETMLSR (ETM_BASE+ETM_ETMLSR_OFFSET) +#define ETM_ETMAUTHSTATUS (ETM_BASE+ETM_ETMAUTHSTATUS_OFFSET) +#define ETM_ETMDEVTYPE (ETM_BASE+ETM_ETMDEVTYPE_OFFSET) +#define ETM_ETMPIDR4 (ETM_BASE+ETM_ETMPIDR4_OFFSET) +#define ETM_ETMPIDR5 (ETM_BASE+ETM_ETMPIDR5_OFFSET) +#define ETM_ETMPIDR6 (ETM_BASE+ETM_ETMPIDR6_OFFSET) +#define ETM_ETMPIDR7 (ETM_BASE+ETM_ETMPIDR7_OFFSET) +#define ETM_ETMPIDR0 (ETM_BASE+ETM_ETMPIDR0_OFFSET) +#define ETM_ETMPIDR1 (ETM_BASE+ETM_ETMPIDR1_OFFSET) +#define ETM_ETMPIDR2 (ETM_BASE+ETM_ETMPIDR2_OFFSET) +#define ETM_ETMPIDR3 (ETM_BASE+ETM_ETMPIDR3_OFFSET) +#define ETM_ETMCIDR0 (ETM_BASE+ETM_ETMCIDR0_OFFSET) +#define ETM_ETMCIDR1 (ETM_BASE+ETM_ETMCIDR1_OFFSET) +#define ETM_ETMCIDR2 (ETM_BASE+ETM_ETMCIDR2_OFFSET) +#define ETM_ETMCIDR3 (ETM_BASE+ETM_ETMCIDR3_OFFSET) + +/* ETM Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for ETM ETMCR */ + +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /* Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /* Mask for ETM_ETMCR */ + +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /* ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /* Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /* Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /* Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /* Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /* Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /* Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /* Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /* Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /* Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /* Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /* Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /* Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /* Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /* ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /* Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /* Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /* ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /* Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /* Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /* Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /* Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /* Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /* Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /* Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /* Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /* Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /* Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /* Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /* Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /* Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /* Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /* Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /* Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /* Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /* Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ + +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /* Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /* Mask for ETM_ETMCCR */ + +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /* Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /* Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /* Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /* Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /* Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /* Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /* Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /* Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /* Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /* Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /* Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /* Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /* Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /* Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /* Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /* Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /* Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /* Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /* Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /* Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /* Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /* FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /* Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /* Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /* Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /* Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /* Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /* Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /* Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /* Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /* Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /* Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /* Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /* ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /* Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /* Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /* Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ + +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /* Mask for ETM_ETMTRIGGER */ + +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /* Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /* Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /* Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /* Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /* Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /* Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /* Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /* Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ + +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /* Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /* Mask for ETM_ETMSR */ + +#define ETM_ETMSR_ETHOF (0x1UL << 0) /* ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /* Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /* Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /* ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /* Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /* Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /* Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /* Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /* Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /* Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /* Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /* Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /* Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /* Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /* Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ + +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /* Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /* Mask for ETM_ETMSCR */ + +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /* Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /* Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_Reserved (0x1UL << 3) /* Reserved */ +#define _ETM_ETMSCR_Reserved_SHIFT 3 /* Shift value for ETM_Reserved */ +#define _ETM_ETMSCR_Reserved_MASK 0x8UL /* Bit mask for ETM_Reserved */ +#define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /* FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /* Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /* Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /* Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /* Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /* Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /* Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /* Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /* Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /* Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /* Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /* Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /* Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /* Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /* Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /* No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /* Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /* Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /* Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ + +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /* Mask for ETM_ETMTEEVR */ + +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /* Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /* Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /* Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /* Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /* Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /* Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /* Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /* Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ + +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /* Mask for ETM_ETMTECR1 */ + +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /* Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /* Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /* Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /* Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /* Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /* Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /* Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /* Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /* Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /* Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /* Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /* Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /* Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /* Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /* Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /* Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /* Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /* Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /* Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /* Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /* Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ + +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /* Mask for ETM_ETMFFLR */ + +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /* Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /* Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ + +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /* Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /* Mask for ETM_ETMCNTRLDVR1 */ + +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /* Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /* Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ + +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /* Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /* Mask for ETM_ETMSYNCFR */ + +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /* Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /* Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /* Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ + +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /* Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /* Mask for ETM_ETMIDR */ + +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /* Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /* Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /* Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /* Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /* Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /* Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /* Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /* Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /* Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /* Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /* Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /* 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /* Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /* Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /* Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /* Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /* Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /* Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /* Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /* Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /* Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /* Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /* Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /* Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /* Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ + +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /* Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /* Mask for ETM_ETMCCER */ + +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /* Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /* Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /* Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /* Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /* Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /* Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /* Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /* Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /* Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /* Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /* Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /* Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /* Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /* Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /* Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /* Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /* EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /* Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /* Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /* Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /* Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /* Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /* Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /* Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /* Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /* Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /* Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /* Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /* Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /* Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /* Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /* Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /* Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ + +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /* Mask for ETM_ETMTESSEICR */ + +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /* Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /* Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /* Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /* Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ + +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /* Mask for ETM_ETMTSEVR */ + +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /* Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /* Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /* Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /* Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /* Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /* Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /* Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /* Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ + +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /* Mask for ETM_ETMTRACEIDR */ + +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /* Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /* Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ + +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /* Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /* Mask for ETM_ETMIDR2 */ + +#define ETM_ETMIDR2_RFE (0x1UL << 0) /* RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /* Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /* Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /* Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /* Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /* Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /* Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /* SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /* Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /* Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /* Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /* Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /* Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /* Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /* Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ + +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /* Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /* Mask for ETM_ETMPDSR */ + +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /* ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /* Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /* Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ + +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /* Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /* Mask for ETM_ETMISCIN */ + +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /* Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /* Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /* Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /* Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /* Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ + +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /* Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /* Mask for ETM_ITTRIGOUT */ + +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /* Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /* Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /* Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ + +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /* Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /* Mask for ETM_ETMITATBCTR2 */ + +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /* ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /* Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /* Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ + +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /* Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /* Mask for ETM_ETMITATBCTR0 */ + +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /* ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /* Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /* Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ + +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /* Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /* Mask for ETM_ETMITCTRL */ + +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /* Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /* Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /* Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ + +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /* Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /* Mask for ETM_ETMCLAIMSET */ + +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /* Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /* Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /* Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ + +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /* Mask for ETM_ETMCLAIMCLR */ + +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /* Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /* Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /* Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ + +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /* Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /* Mask for ETM_ETMLAR */ + +#define ETM_ETMLAR_KEY (0x1UL << 0) /* Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /* Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /* Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ + +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /* Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /* Mask for ETM_ETMLSR */ + +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /* ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /* Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /* Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /* ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /* Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /* Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /* Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ + +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /* Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /* Mask for ETM_ETMAUTHSTATUS */ + +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /* Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /* Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /* Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /* Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /* Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /* Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /* Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /* Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /* Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /* Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /* Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /* Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /* Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /* Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /* Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ + +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /* Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /* Mask for ETM_ETMDEVTYPE */ + +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /* Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /* Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /* Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /* Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /* Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ + +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /* Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /* Mask for ETM_ETMPIDR4 */ + +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /* Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /* Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /* Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /* Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ + +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /* Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /* Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ + +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /* Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /* Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ + +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /* Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /* Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ + +#define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL /* Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /* Mask for ETM_ETMPIDR0 */ + +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /* Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /* Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL /* Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ + +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /* Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /* Mask for ETM_ETMPIDR1 */ + +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /* Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /* Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /* Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /* Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /* Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /* Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ + +#define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL /* Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /* Mask for ETM_ETMPIDR2 */ + +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /* Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /* Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /* Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /* Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /* Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /* Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /* Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /* Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /* Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL /* Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ + +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /* Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /* Mask for ETM_ETMPIDR3 */ + +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /* Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /* Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /* Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /* Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /* Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /* Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ + +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /* Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /* Mask for ETM_ETMCIDR0 */ + +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /* Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /* Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /* Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ + +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /* Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /* Mask for ETM_ETMCIDR1 */ + +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /* Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /* Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /* Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ + +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /* Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /* Mask for ETM_ETMCIDR2 */ + +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /* Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /* Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /* Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ + +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /* Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /* Mask for ETM_ETMCIDR3 */ + +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /* Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /* Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /* Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /* Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +#endif /* __ARCH_ARM_SRC_ARMV7_M_ETM_H */ diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h index bd60b0fad..929353e8c 100644 --- a/nuttx/arch/arm/src/common/up_internal.h +++ b/nuttx/arch/arm/src/common/up_internal.h @@ -422,13 +422,13 @@ void up_lowputc(char ch); void up_puts(const char *str); void up_lowputs(const char *str); -#if USE_SERIALDRIVER +#ifdef USE_SERIALDRIVER void up_serialinit(void); #else # define up_serialinit() #endif -#if USE_EARLYSERIALINIT +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void); #else # define up_earlyserialinit() diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_acmp.h b/nuttx/arch/arm/src/efm32/chip/efm32_acmp.h new file mode 100644 index 000000000..e9956ba8e --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_acmp.h @@ -0,0 +1,402 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_acmp.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* ACMP Register Offsets *******************************************************************************************************/ + +#define EFM32_ACMP_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_ACMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */ +#define EFM32_ACMP_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_ACMP_IEN_OFFSET 0x000c /* Interrupt Enable Register */ +#define EFM32_ACMP_IF_OFFSET 0x0010 /* Interrupt Flag Register */ +#define EFM32_ACMP_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ +#define EFM32_ACMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ +#define EFM32_ACMP_ROUTE_OFFSET 0x001c /* I/O Routing Register */ + +/* ACMP Register Addresses *****************************************************************************************************/ + +#define EFM32_ACMP0_CTRL (EFM32_ACMP0_BASE+EFM32_ACMP_CTRL_OFFSET) +#define EFM32_ACMP0_INPUTSEL (EFM32_ACMP0_BASE+EFM32_ACMP_INPUTSEL_OFFSET) +#define EFM32_ACMP0_STATUS (EFM32_ACMP0_BASE+EFM32_ACMP_STATUS_OFFSET) +#define EFM32_ACMP0_IEN (EFM32_ACMP0_BASE+EFM32_ACMP_IEN_OFFSET) +#define EFM32_ACMP0_IF (EFM32_ACMP0_BASE+EFM32_ACMP_IF_OFFSET) +#define EFM32_ACMP0_IFS (EFM32_ACMP0_BASE+EFM32_ACMP_IFS_OFFSET) +#define EFM32_ACMP0_IFC (EFM32_ACMP0_BASE+EFM32_ACMP_IFC_OFFSET) +#define EFM32_ACMP0_ROUTE (EFM32_ACMP0_BASE+EFM32_ACMP_ROUTE_OFFSET) + +#define EFM32_ACMP1_CTRL (EFM32_ACMP1_BASE+EFM32_ACMP_CTRL_OFFSET) +#define EFM32_ACMP1_INPUTSEL (EFM32_ACMP1_BASE+EFM32_ACMP_INPUTSEL_OFFSET) +#define EFM32_ACMP1_STATUS (EFM32_ACMP1_BASE+EFM32_ACMP_STATUS_OFFSET) +#define EFM32_ACMP1_IEN (EFM32_ACMP1_BASE+EFM32_ACMP_IEN_OFFSET) +#define EFM32_ACMP1_IF (EFM32_ACMP1_BASE+EFM32_ACMP_IF_OFFSET) +#define EFM32_ACMP1_IFS (EFM32_ACMP1_BASE+EFM32_ACMP_IFS_OFFSET) +#define EFM32_ACMP1_IFC (EFM32_ACMP1_BASE+EFM32_ACMP_IFC_OFFSET) +#define EFM32_ACMP1_ROUTE (EFM32_ACMP1_BASE+EFM32_ACMP_ROUTE_OFFSET) + +/* ACMP Register Bit Field Definitions *****************************************************************************************/ + +/* Bit fields for ACMP CTRL */ + +#define _ACMP_CTRL_RESETVALUE 0x47000000UL /* Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xCF03077FUL /* Mask for ACMP_CTRL */ + +#define ACMP_CTRL_EN (0x1UL << 0) /* Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /* Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /* Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_MUXEN (0x1UL << 1) /* Input Mux Enable */ +#define _ACMP_CTRL_MUXEN_SHIFT 1 /* Shift value for ACMP_MUXEN */ +#define _ACMP_CTRL_MUXEN_MASK 0x2UL /* Bit mask for ACMP_MUXEN */ +#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /* Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /* Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /* Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /* Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /* Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /* Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /* Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /* Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /* Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /* Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /* Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /* Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /* Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /* Shifted mode INV for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /* Shift value for ACMP_HYSTSEL */ +#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /* Bit mask for ACMP_HYSTSEL */ +#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /* Mode HYST0 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /* Mode HYST1 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /* Mode HYST2 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /* Mode HYST3 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /* Mode HYST4 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /* Mode HYST5 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /* Mode HYST6 for ACMP_CTRL */ +#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /* Mode HYST7 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /* Shifted mode HYST0 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /* Shifted mode HYST1 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /* Shifted mode HYST2 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /* Shifted mode HYST3 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /* Shifted mode HYST4 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /* Shifted mode HYST5 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /* Shifted mode HYST6 for ACMP_CTRL */ +#define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /* Shifted mode HYST7 for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_SHIFT 8 /* Shift value for ACMP_WARMTIME */ +#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /* Bit mask for ACMP_WARMTIME */ +#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /* Mode 4CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /* Mode 8CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /* Mode 16CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /* Mode 32CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /* Mode 64CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /* Mode 128CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /* Mode 256CYCLES for ACMP_CTRL */ +#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /* Mode 512CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /* Shifted mode 4CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /* Shifted mode 8CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /* Shifted mode 16CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /* Shifted mode 32CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /* Shifted mode 64CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /* Shifted mode 128CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /* Shifted mode 256CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /* Shifted mode 512CYCLES for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 16) /* Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 16 /* Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x10000UL /* Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /* Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /* Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /* Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /* Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 17) /* Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 17 /* Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x20000UL /* Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /* Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /* Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /* Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /* Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /* Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /* Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_HALFBIAS (0x1UL << 30) /* Half Bias Current */ +#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /* Shift value for ACMP_HALFBIAS */ +#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /* Bit mask for ACMP_HALFBIAS */ +#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /* Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /* Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /* Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /* Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /* Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ + +#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /* Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /* Mask for ACMP_INPUTSEL */ + +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /* Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /* Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /* Mode CH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /* Mode CH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /* Mode CH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /* Mode CH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /* Mode CH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /* Mode CH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /* Mode CH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /* Mode CH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /* Shifted mode CH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /* Shifted mode CH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /* Shifted mode CH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /* Shifted mode CH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /* Shifted mode CH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /* Shifted mode CH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /* Shifted mode CH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /* Shifted mode CH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /* Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /* Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /* Mode CH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /* Mode CH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /* Mode CH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /* Mode CH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /* Mode CH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /* Mode CH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /* Mode CH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /* Mode CH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /* Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /* Mode 2V5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /* Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /* Mode CAPSENSE for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DAC0CH0 0x0000000CUL /* Mode DAC0CH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DAC0CH1 0x0000000DUL /* Mode DAC0CH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /* Shifted mode CH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /* Shifted mode CH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /* Shifted mode CH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /* Shifted mode CH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /* Shifted mode CH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /* Shifted mode CH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /* Shifted mode CH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /* Shifted mode CH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /* Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /* Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /* Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /* Shifted mode CAPSENSE for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 (_ACMP_INPUTSEL_NEGSEL_DAC0CH0 << 4) /* Shifted mode DAC0CH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 (_ACMP_INPUTSEL_NEGSEL_DAC0CH1 << 4) /* Shifted mode DAC0CH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /* Shift value for ACMP_VDDLEVEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /* Bit mask for ACMP_VDDLEVEL */ +#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_LPREF (0x1UL << 16) /* Low Power Reference Mode */ +#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /* Shift value for ACMP_LPREF */ +#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /* Bit mask for ACMP_LPREF */ +#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /* Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /* Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /* Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /* Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /* Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /* Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /* Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /* Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /* Mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /* Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /* Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /* Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /* Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /* Shifted mode RES3 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ + +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /* Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x00000003UL /* Mask for ACMP_STATUS */ + +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /* Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /* Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /* Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /* Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /* Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /* Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IEN */ + +#define _ACMP_IEN_RESETVALUE 0x00000000UL /* Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000003UL /* Mask for ACMP_IEN */ + +#define ACMP_IEN_EDGE (0x1UL << 0) /* Edge Trigger Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /* Warm-up Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP IF */ + +#define _ACMP_IF_RESETVALUE 0x00000000UL /* Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000003UL /* Mask for ACMP_IF */ + +#define ACMP_IF_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ + +#define _ACMP_IFS_RESETVALUE 0x00000000UL /* Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000003UL /* Mask for ACMP_IFS */ + +#define ACMP_IFS_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Set */ +#define _ACMP_IFS_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Set */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ + +#define _ACMP_IFC_RESETVALUE 0x00000000UL /* Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000003UL /* Mask for ACMP_IFC */ + +#define ACMP_IFC_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Clear */ +#define _ACMP_IFC_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Clear */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP ROUTE */ + +#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /* Default value for ACMP_ROUTE */ +#define _ACMP_ROUTE_MASK 0x00000701UL /* Mask for ACMP_ROUTE */ + +#define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /* ACMP Output Pin Enable */ +#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /* Shift value for ACMP_ACMPPEN */ +#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /* Bit mask for ACMP_ACMPPEN */ +#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_ROUTE */ +#define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_SHIFT 8 /* Shift value for ACMP_LOCATION */ +#define _ACMP_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for ACMP_LOCATION */ +#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for ACMP_ROUTE */ +#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for ACMP_ROUTE */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_adc.h b/nuttx/arch/arm/src/efm32/chip/efm32_adc.h new file mode 100644 index 000000000..8245acffa --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_adc.h @@ -0,0 +1,751 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_adc.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* ADC Register Offsets ********************************************************************************************************/ + +#define EFM32_ADC_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_ADC_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_ADC_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_ADC_SINGLECTRL_OFFSET 0x000c /* Single Sample Control Register */ +#define EFM32_ADC_SCANCTRL_OFFSET 0x0010 /* Scan Control Register */ +#define EFM32_ADC_IEN_OFFSET 0x0014 /* Interrupt Enable Register */ +#define EFM32_ADC_IF_OFFSET 0x0018 /* Interrupt Flag Register */ +#define EFM32_ADC_IFS_OFFSET 0x001c /* Interrupt Flag Set Register */ +#define EFM32_ADC_IFC_OFFSET 0x0020 /* Interrupt Flag Clear Register */ +#define EFM32_ADC_SINGLEDATA_OFFSET 0x0024 /* Single Conversion Result Data */ +#define EFM32_ADC_SCANDATA_OFFSET 0x0028 /* Scan Conversion Result Data */ +#define EFM32_ADC_SINGLEDATAP_OFFSET 0x002c /* Single Conversion Result Data Peek Register */ +#define EFM32_ADC_SCANDATAP_OFFSET 0x0030 /* Scan Sequence Result Data Peek Register */ +#define EFM32_ADC_CAL_OFFSET 0x0034 /* Calibration Register */ +#define EFM32_ADC_BIASPROG_OFFSET 0x003c /* Bias Programming Register */ + +/* ADC Register Addresses ******************************************************************************************************/ + +#define EFM32_ADC0_CTRL (EFM32_ADC0_BASE+EFM32_ADC_CTRL_OFFSET) +#define EFM32_ADC0_CMD (EFM32_ADC0_BASE+EFM32_ADC_CMD_OFFSET) +#define EFM32_ADC0_STATUS (EFM32_ADC0_BASE+EFM32_ADC_STATUS_OFFSET) +#define EFM32_ADC0_SINGLECTRL (EFM32_ADC0_BASE+EFM32_ADC_SINGLECTRL_OFFSET) +#define EFM32_ADC0_SCANCTRL (EFM32_ADC0_BASE+EFM32_ADC_SCANCTRL_OFFSET) +#define EFM32_ADC0_IEN (EFM32_ADC0_BASE+EFM32_ADC_IEN_OFFSET) +#define EFM32_ADC0_IF (EFM32_ADC0_BASE+EFM32_ADC_IF_OFFSET) +#define EFM32_ADC0_IFS (EFM32_ADC0_BASE+EFM32_ADC_IFS_OFFSET) +#define EFM32_ADC0_IFC (EFM32_ADC0_BASE+EFM32_ADC_IFC_OFFSET) +#define EFM32_ADC0_SINGLEDATA (EFM32_ADC0_BASE+EFM32_ADC_SINGLEDATA_OFFSET) +#define EFM32_ADC0_SCANDATA (EFM32_ADC0_BASE+EFM32_ADC_SCANDATA_OFFSET) +#define EFM32_ADC0_SINGLEDATAP (EFM32_ADC0_BASE+EFM32_ADC_SINGLEDATAP_OFFSET) +#define EFM32_ADC0_SCANDATAP (EFM32_ADC0_BASE+EFM32_ADC_SCANDATAP_OFFSET) +#define EFM32_ADC0_CAL (EFM32_ADC0_BASE+EFM32_ADC_CAL_OFFSET) +#define EFM32_ADC0_BIASPROG (EFM32_ADC0_BASE+EFM32_ADC_BIASPROG_OFFSET) + +/* ADC Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for ADC CTRL */ + +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /* Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0x0F1F7F3BUL /* Mask for ADC_CTRL */ + +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /* Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /* Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /* Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /* Mode FASTBG for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /* Mode KEEPSCANREFWARM for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /* Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /* Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /* Shifted mode FASTBG for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /* Shifted mode KEEPSCANREFWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /* Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 3) /* Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 3 /* Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x8UL /* Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /* Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_SHIFT 4 /* Shift value for ADC_LPFMODE */ +#define _ADC_CTRL_LPFMODE_MASK 0x30UL /* Bit mask for ADC_LPFMODE */ +#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /* Mode BYPASS for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /* Mode DECAP for ADC_CTRL */ +#define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /* Mode RCFILT for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /* Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /* Shifted mode BYPASS for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /* Shifted mode DECAP for ADC_CTRL */ +#define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /* Shifted mode RCFILT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /* Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /* Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /* Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /* Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /* Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /* Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /* Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /* Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /* Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /* Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /* Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /* Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /* Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /* Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /* Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /* Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /* Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /* Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /* Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /* Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /* Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /* Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /* Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /* Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /* Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /* Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /* Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /* Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /* Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /* Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /* Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /* Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /* Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /* Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /* Shifted mode X4096 for ADC_CTRL */ + +/* Bit fields for ADC CMD */ + +#define _ADC_CMD_RESETVALUE 0x00000000UL /* Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /* Mask for ADC_CMD */ + +#define ADC_CMD_SINGLESTART (0x1UL << 0) /* Single Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /* Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /* Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /* Single Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /* Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /* Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /* Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /* Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /* Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /* Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /* Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /* Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /* Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /* Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ + +#define _ADC_STATUS_RESETVALUE 0x00000000UL /* Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x07031303UL /* Mask for ADC_STATUS */ + +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /* Single Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /* Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /* Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /* Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /* Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /* Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /* Single Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /* Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /* Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /* Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /* Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /* Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /* ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /* Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /* Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /* Single Sample Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /* Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /* Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /* Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /* Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /* Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /* Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_SHIFT 24 /* Shift value for ADC_SCANDATASRC */ +#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /* Bit mask for ADC_SCANDATASRC */ +#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /* Mode CH0 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /* Mode CH1 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /* Mode CH2 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /* Mode CH3 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /* Mode CH4 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /* Mode CH5 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /* Mode CH6 for ADC_STATUS */ +#define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /* Mode CH7 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /* Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /* Shifted mode CH0 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /* Shifted mode CH1 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /* Shifted mode CH2 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /* Shifted mode CH3 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /* Shifted mode CH4 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /* Shifted mode CH5 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /* Shifted mode CH6 for ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /* Shifted mode CH7 for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ + +#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /* Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /* Mask for ADC_SINGLECTRL */ + +#define ADC_SINGLECTRL_REP (0x1UL << 0) /* Single Sample Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /* Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /* Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /* Single Sample Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /* Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /* Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /* Single Sample Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /* Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /* Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /* Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /* Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /* Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /* Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 4 /* Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x30UL /* Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /* Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /* Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /* Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /* Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /* Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /* Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /* Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /* Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /* Shift value for ADC_INPUTSEL */ +#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /* Bit mask for ADC_INPUTSEL */ +#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /* Mode CH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /* Mode CH0CH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /* Mode CH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /* Mode CH2CH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /* Mode CH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /* Mode CH4CH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /* Mode CH6CH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /* Mode CH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /* Mode CH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /* Mode DIFF0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /* Mode CH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /* Mode CH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /* Mode CH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /* Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /* Mode VDDDIV3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /* Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /* Mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /* Mode VREFDIV2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /* Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /* Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /* Shifted mode CH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /* Shifted mode CH0CH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /* Shifted mode CH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /* Shifted mode CH2CH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /* Shifted mode CH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /* Shifted mode CH4CH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /* Shifted mode CH6CH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /* Shifted mode CH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /* Shifted mode CH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /* Shifted mode DIFF0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /* Shifted mode CH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /* Shifted mode CH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /* Shifted mode CH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /* Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /* Shifted mode VDDDIV3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /* Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /* Shifted mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /* Shifted mode VREFDIV2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /* Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /* Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 16 /* Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0x70000UL /* Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /* Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /* Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /* Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /* Mode 5VDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /* Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /* Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /* Mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /* Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /* Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /* Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /* Shifted mode 5VDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /* Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /* Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /* Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 20 /* Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /* Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /* Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /* Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /* Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /* Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /* Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /* Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /* Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /* Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /* Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /* Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /* Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /* Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /* Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /* Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /* Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /* Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /* Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /* Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /* Single Sample PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /* Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /* Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /* Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /* Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /* Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /* Shifted mode PRSCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /* Shifted mode PRSCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /* Shifted mode PRSCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /* Shifted mode PRSCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /* Shifted mode PRSCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /* Shifted mode PRSCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /* Shifted mode PRSCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /* Shifted mode PRSCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /* Shifted mode PRSCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /* Shifted mode PRSCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /* Shifted mode PRSCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /* Shifted mode PRSCH11 for ADC_SINGLECTRL */ + +/* Bit fields for ADC SCANCTRL */ + +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /* Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /* Mask for ADC_SCANCTRL */ + +#define ADC_SCANCTRL_REP (0x1UL << 0) /* Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /* Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /* Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /* Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /* Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /* Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /* Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /* Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /* Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /* Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /* Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /* Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /* Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 4 /* Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x30UL /* Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /* Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /* Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /* Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /* Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /* Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /* Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /* Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /* Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /* Shift value for ADC_INPUTMASK */ +#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /* Bit mask for ADC_INPUTMASK */ +#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /* Mode CH0 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /* Mode CH0CH1 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /* Mode CH1 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /* Mode CH2CH3 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /* Mode CH2 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /* Mode CH4CH5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /* Mode CH6CH7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /* Mode CH3 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /* Mode CH4 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /* Mode CH5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /* Mode CH6 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /* Mode CH7 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /* Shifted mode CH0 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /* Shifted mode CH0CH1 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /* Shifted mode CH1 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /* Shifted mode CH2CH3 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /* Shifted mode CH2 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /* Shifted mode CH4CH5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /* Shifted mode CH6CH7 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /* Shifted mode CH3 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /* Shifted mode CH4 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /* Shifted mode CH5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /* Shifted mode CH6 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /* Shifted mode CH7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 16 /* Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0x70000UL /* Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /* Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /* Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /* Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /* Mode 5VDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /* Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /* Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /* Mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /* Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /* Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /* Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /* Shifted mode 5VDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /* Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /* Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /* Shifted mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 20 /* Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF00000UL /* Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /* Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /* Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /* Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /* Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /* Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /* Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /* Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /* Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /* Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /* Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /* Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /* Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /* Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /* Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /* Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /* Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /* Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /* Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 24) /* Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 24 /* Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /* Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /* Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /* Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /* Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /* Shifted mode PRSCH0 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /* Shifted mode PRSCH1 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /* Shifted mode PRSCH2 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /* Shifted mode PRSCH3 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /* Shifted mode PRSCH4 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /* Shifted mode PRSCH5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /* Shifted mode PRSCH6 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /* Shifted mode PRSCH7 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /* Shifted mode PRSCH8 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /* Shifted mode PRSCH9 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /* Shifted mode PRSCH10 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /* Shifted mode PRSCH11 for ADC_SCANCTRL */ + +/* Bit fields for ADC IEN */ + +#define _ADC_IEN_RESETVALUE 0x00000000UL /* Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x00000303UL /* Mask for ADC_IEN */ + +#define ADC_IEN_SINGLE (0x1UL << 0) /* Single Conversion Complete Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /* Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /* Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /* Scan Conversion Complete Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /* Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /* Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /* Single Result Overflow Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /* Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /* Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /* Scan Result Overflow Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /* Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /* Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /* Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC IF */ + +#define _ADC_IF_RESETVALUE 0x00000000UL /* Default value for ADC_IF */ +#define _ADC_IF_MASK 0x00000303UL /* Mask for ADC_IF */ + +#define ADC_IF_SINGLE (0x1UL << 0) /* Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /* Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /* Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /* Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /* Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /* Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /* Single Result Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /* Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /* Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /* Scan Result Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /* Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /* Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /* Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ + +#define _ADC_IFS_RESETVALUE 0x00000000UL /* Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x00000303UL /* Mask for ADC_IFS */ + +#define ADC_IFS_SINGLE (0x1UL << 0) /* Single Conversion Complete Interrupt Flag Set */ +#define _ADC_IFS_SINGLE_SHIFT 0 /* Shift value for ADC_SINGLE */ +#define _ADC_IFS_SINGLE_MASK 0x1UL /* Bit mask for ADC_SINGLE */ +#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCAN (0x1UL << 1) /* Scan Conversion Complete Interrupt Flag Set */ +#define _ADC_IFS_SCAN_SHIFT 1 /* Shift value for ADC_SCAN */ +#define _ADC_IFS_SCAN_MASK 0x2UL /* Bit mask for ADC_SCAN */ +#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /* Single Result Overflow Interrupt Flag Set */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /* Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /* Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /* Scan Result Overflow Interrupt Flag Set */ +#define _ADC_IFS_SCANOF_SHIFT 9 /* Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /* Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /* Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ + +#define _ADC_IFC_RESETVALUE 0x00000000UL /* Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x00000303UL /* Mask for ADC_IFC */ + +#define ADC_IFC_SINGLE (0x1UL << 0) /* Single Conversion Complete Interrupt Flag Clear */ +#define _ADC_IFC_SINGLE_SHIFT 0 /* Shift value for ADC_SINGLE */ +#define _ADC_IFC_SINGLE_MASK 0x1UL /* Bit mask for ADC_SINGLE */ +#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCAN (0x1UL << 1) /* Scan Conversion Complete Interrupt Flag Clear */ +#define _ADC_IFC_SCAN_SHIFT 1 /* Shift value for ADC_SCAN */ +#define _ADC_IFC_SCAN_MASK 0x2UL /* Bit mask for ADC_SCAN */ +#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /* Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /* Single Result Overflow Interrupt Flag Clear */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /* Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /* Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /* Scan Result Overflow Interrupt Flag Clear */ +#define _ADC_IFC_SCANOF_SHIFT 9 /* Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /* Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /* Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC SINGLEDATA */ + +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /* Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /* Mask for ADC_SINGLEDATA */ + +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /* Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /* Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ + +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /* Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /* Mask for ADC_SCANDATA */ + +#define _ADC_SCANDATA_DATA_SHIFT 0 /* Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /* Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ + +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /* Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /* Mask for ADC_SINGLEDATAP */ + +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /* Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /* Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ + +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /* Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /* Mask for ADC_SCANDATAP */ + +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /* Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /* Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC CAL */ + +#define _ADC_CAL_RESETVALUE 0x3F003F00UL /* Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0x7F7F7F7FUL /* Mask for ADC_CAL */ + +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /* Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /* Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /* Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /* Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /* Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /* Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /* Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /* Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /* Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /* Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /* Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /* Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /* Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC BIASPROG */ + +#define _ADC_BIASPROG_RESETVALUE 0x00000747UL /* Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x00000F4FUL /* Mask for ADC_BIASPROG */ + +#define _ADC_BIASPROG_BIASPROG_SHIFT 0 /* Shift value for ADC_BIASPROG */ +#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /* Bit mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /* Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /* Half Bias Current */ +#define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /* Shift value for ADC_HALFBIAS */ +#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /* Bit mask for ADC_HALFBIAS */ +#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /* Shifted mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /* Shift value for ADC_COMPBIAS */ +#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /* Bit mask for ADC_COMPBIAS */ +#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /* Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /* Shifted mode DEFAULT for ADC_BIASPROG */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ADC_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_aes.h b/nuttx/arch/arm/src/efm32/chip/efm32_aes.h new file mode 100644 index 000000000..3376edaec --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_aes.h @@ -0,0 +1,327 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_aes.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* AES Register Offsets ********************************************************************************************************/ + +#define EFM32_AES_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_AES_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_AES_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_AES_IEN_OFFSET 0x000c /* Interrupt Enable Register */ +#define EFM32_AES_IF_OFFSET 0x0010 /* Interrupt Flag Register */ +#define EFM32_AES_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ +#define EFM32_AES_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ +#define EFM32_AES_DATA_OFFSET 0x001c /* DATA Register */ +#define EFM32_AES_XORDATA_OFFSET 0x0020 /* XORDATA Register */ +#define EFM32_AES_KEYLA_OFFSET 0x0030 /* KEY Low Register */ +#define EFM32_AES_KEYLB_OFFSET 0x0034 /* KEY Low Register */ +#define EFM32_AES_KEYLC_OFFSET 0x0038 /* KEY Low Register */ +#define EFM32_AES_KEYLD_OFFSET 0x003c /* KEY Low Register */ +#define EFM32_AES_KEYHA_OFFSET 0x0040 /* KEY High Register */ +#define EFM32_AES_KEYHB_OFFSET 0x0044 /* KEY High Register */ +#define EFM32_AES_KEYHC_OFFSET 0x0048 /* KEY High Register */ +#define EFM32_AES_KEYHD_OFFSET 0x004c /* KEY High Register */ + +/* AES Register Addresses ******************************************************************************************************/ + +#define EFM32_AES_CTRL (EFM32_AES_BASE+EFM32_AES_CTRL_OFFSET) +#define EFM32_AES_CMD (EFM32_AES_BASE+EFM32_AES_CMD_OFFSET) +#define EFM32_AES_STATUS (EFM32_AES_BASE+EFM32_AES_STATUS_OFFSET) +#define EFM32_AES_IEN (EFM32_AES_BASE+EFM32_AES_IEN_OFFSET) +#define EFM32_AES_IF (EFM32_AES_BASE+EFM32_AES_IF_OFFSET) +#define EFM32_AES_IFS (EFM32_AES_BASE+EFM32_AES_IFS_OFFSET) +#define EFM32_AES_IFC (EFM32_AES_BASE+EFM32_AES_IFC_OFFSET) +#define EFM32_AES_DATA (EFM32_AES_BASE+EFM32_AES_DATA_OFFSET) +#define EFM32_AES_XORDATA (EFM32_AES_BASE+EFM32_AES_XORDATA_OFFSET) +#define EFM32_AES_KEYLA (EFM32_AES_BASE+EFM32_AES_KEYLA_OFFSET) +#define EFM32_AES_KEYLB (EFM32_AES_BASE+EFM32_AES_KEYLB_OFFSET) +#define EFM32_AES_KEYLC (EFM32_AES_BASE+EFM32_AES_KEYLC_OFFSET) +#define EFM32_AES_KEYLD (EFM32_AES_BASE+EFM32_AES_KEYLD_OFFSET) +#define EFM32_AES_KEYHA (EFM32_AES_BASE+EFM32_AES_KEYHA_OFFSET) +#define EFM32_AES_KEYHB (EFM32_AES_BASE+EFM32_AES_KEYHB_OFFSET) +#define EFM32_AES_KEYHC (EFM32_AES_BASE+EFM32_AES_KEYHC_OFFSET) +#define EFM32_AES_KEYHD (EFM32_AES_BASE+EFM32_AES_KEYHD_OFFSET) + +/* AES Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for AES CTRL */ + +#define _AES_CTRL_RESETVALUE 0x00000000UL /* Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x00000077UL /* Mask for AES_CTRL */ + +#define AES_CTRL_DECRYPT (0x1UL << 0) /* Decryption/Encryption Mode */ +#define _AES_CTRL_DECRYPT_SHIFT 0 /* Shift value for AES_DECRYPT */ +#define _AES_CTRL_DECRYPT_MASK 0x1UL /* Bit mask for AES_DECRYPT */ +#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /* Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_AES256 (0x1UL << 1) /* AES-256 Mode */ +#define _AES_CTRL_AES256_SHIFT 1 /* Shift value for AES_AES256 */ +#define _AES_CTRL_AES256_MASK 0x2UL /* Bit mask for AES_AES256 */ +#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /* Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_KEYBUFEN (0x1UL << 2) /* Key Buffer Enable */ +#define _AES_CTRL_KEYBUFEN_SHIFT 2 /* Shift value for AES_KEYBUFEN */ +#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /* Bit mask for AES_KEYBUFEN */ +#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /* Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_DATASTART (0x1UL << 4) /* AES_DATA Write Start */ +#define _AES_CTRL_DATASTART_SHIFT 4 /* Shift value for AES_DATASTART */ +#define _AES_CTRL_DATASTART_MASK 0x10UL /* Bit mask for AES_DATASTART */ +#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /* Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_XORSTART (0x1UL << 5) /* AES_XORDATA Write Start */ +#define _AES_CTRL_XORSTART_SHIFT 5 /* Shift value for AES_XORSTART */ +#define _AES_CTRL_XORSTART_MASK 0x20UL /* Bit mask for AES_XORSTART */ +#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /* Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_BYTEORDER (0x1UL << 6) /* Configure byte order in data and key registers */ +#define _AES_CTRL_BYTEORDER_SHIFT 6 /* Shift value for AES_BYTEORDER */ +#define _AES_CTRL_BYTEORDER_MASK 0x40UL /* Bit mask for AES_BYTEORDER */ +#define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /* Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ + +#define _AES_CMD_RESETVALUE 0x00000000UL /* Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /* Mask for AES_CMD */ + +#define AES_CMD_START (0x1UL << 0) /* Encryption/Decryption Start */ +#define _AES_CMD_START_SHIFT 0 /* Shift value for AES_START */ +#define _AES_CMD_START_MASK 0x1UL /* Bit mask for AES_START */ +#define _AES_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CMD */ +#define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STOP (0x1UL << 1) /* Encryption/Decryption Stop */ +#define _AES_CMD_STOP_SHIFT 1 /* Shift value for AES_STOP */ +#define _AES_CMD_STOP_MASK 0x2UL /* Bit mask for AES_STOP */ +#define _AES_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CMD */ +#define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ + +#define _AES_STATUS_RESETVALUE 0x00000000UL /* Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0x00000001UL /* Mask for AES_STATUS */ + +#define AES_STATUS_RUNNING (0x1UL << 0) /* AES Running */ +#define _AES_STATUS_RUNNING_SHIFT 0 /* Shift value for AES_RUNNING */ +#define _AES_STATUS_RUNNING_MASK 0x1UL /* Bit mask for AES_RUNNING */ +#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /* Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES IEN */ + +#define _AES_IEN_RESETVALUE 0x00000000UL /* Default value for AES_IEN */ +#define _AES_IEN_MASK 0x00000001UL /* Mask for AES_IEN */ + +#define AES_IEN_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Enable */ +#define _AES_IEN_DONE_SHIFT 0 /* Shift value for AES_DONE */ +#define _AES_IEN_DONE_MASK 0x1UL /* Bit mask for AES_DONE */ +#define _AES_IEN_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IEN */ +#define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ + +#define _AES_IF_RESETVALUE 0x00000000UL /* Default value for AES_IF */ +#define _AES_IF_MASK 0x00000001UL /* Mask for AES_IF */ + +#define AES_IF_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag */ +#define _AES_IF_DONE_SHIFT 0 /* Shift value for AES_DONE */ +#define _AES_IF_DONE_MASK 0x1UL /* Bit mask for AES_DONE */ +#define _AES_IF_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IF */ +#define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IFS */ + +#define _AES_IFS_RESETVALUE 0x00000000UL /* Default value for AES_IFS */ +#define _AES_IFS_MASK 0x00000001UL /* Mask for AES_IFS */ + +#define AES_IFS_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag Set */ +#define _AES_IFS_DONE_SHIFT 0 /* Shift value for AES_DONE */ +#define _AES_IFS_DONE_MASK 0x1UL /* Bit mask for AES_DONE */ +#define _AES_IFS_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IFS */ +#define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IFS */ + +/* Bit fields for AES IFC */ + +#define _AES_IFC_RESETVALUE 0x00000000UL /* Default value for AES_IFC */ +#define _AES_IFC_MASK 0x00000001UL /* Mask for AES_IFC */ + +#define AES_IFC_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag Clear */ +#define _AES_IFC_DONE_SHIFT 0 /* Shift value for AES_DONE */ +#define _AES_IFC_DONE_MASK 0x1UL /* Bit mask for AES_DONE */ +#define _AES_IFC_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IFC */ +#define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IFC */ + +/* Bit fields for AES DATA */ + +#define _AES_DATA_RESETVALUE 0x00000000UL /* Default value for AES_DATA */ +#define _AES_DATA_MASK 0xFFFFFFFFUL /* Mask for AES_DATA */ + +#define _AES_DATA_DATA_SHIFT 0 /* Shift value for AES_DATA */ +#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /* Bit mask for AES_DATA */ +#define _AES_DATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_DATA */ +#define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_DATA */ + +/* Bit fields for AES XORDATA */ + +#define _AES_XORDATA_RESETVALUE 0x00000000UL /* Default value for AES_XORDATA */ +#define _AES_XORDATA_MASK 0xFFFFFFFFUL /* Mask for AES_XORDATA */ + +#define _AES_XORDATA_XORDATA_SHIFT 0 /* Shift value for AES_XORDATA */ +#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /* Bit mask for AES_XORDATA */ +#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_XORDATA */ +#define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_XORDATA */ + +/* Bit fields for AES KEYLA */ + +#define _AES_KEYLA_RESETVALUE 0x00000000UL /* Default value for AES_KEYLA */ +#define _AES_KEYLA_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLA */ + +#define _AES_KEYLA_KEYLA_SHIFT 0 /* Shift value for AES_KEYLA */ +#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLA */ +#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLA */ +#define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLA */ + +/* Bit fields for AES KEYLB */ + +#define _AES_KEYLB_RESETVALUE 0x00000000UL /* Default value for AES_KEYLB */ +#define _AES_KEYLB_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLB */ + +#define _AES_KEYLB_KEYLB_SHIFT 0 /* Shift value for AES_KEYLB */ +#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLB */ +#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLB */ +#define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLB */ + +/* Bit fields for AES KEYLC */ + +#define _AES_KEYLC_RESETVALUE 0x00000000UL /* Default value for AES_KEYLC */ +#define _AES_KEYLC_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLC */ + +#define _AES_KEYLC_KEYLC_SHIFT 0 /* Shift value for AES_KEYLC */ +#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLC */ +#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLC */ +#define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLC */ + +/* Bit fields for AES KEYLD */ + +#define _AES_KEYLD_RESETVALUE 0x00000000UL /* Default value for AES_KEYLD */ +#define _AES_KEYLD_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLD */ + +#define _AES_KEYLD_KEYLD_SHIFT 0 /* Shift value for AES_KEYLD */ +#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLD */ +#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLD */ +#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLD */ + +/* Bit fields for AES KEYHA */ + +#define _AES_KEYHA_RESETVALUE 0x00000000UL /* Default value for AES_KEYHA */ +#define _AES_KEYHA_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHA */ + +#define _AES_KEYHA_KEYHA_SHIFT 0 /* Shift value for AES_KEYHA */ +#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHA */ +#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHA */ +#define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHA */ + +/* Bit fields for AES KEYHB */ + +#define _AES_KEYHB_RESETVALUE 0x00000000UL /* Default value for AES_KEYHB */ +#define _AES_KEYHB_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHB */ + +#define _AES_KEYHB_KEYHB_SHIFT 0 /* Shift value for AES_KEYHB */ +#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHB */ +#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHB */ +#define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHB */ + +/* Bit fields for AES KEYHC */ + +#define _AES_KEYHC_RESETVALUE 0x00000000UL /* Default value for AES_KEYHC */ +#define _AES_KEYHC_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHC */ + +#define _AES_KEYHC_KEYHC_SHIFT 0 /* Shift value for AES_KEYHC */ +#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHC */ +#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHC */ +#define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHC */ + +/* Bit fields for AES KEYHD */ + +#define _AES_KEYHD_RESETVALUE 0x00000000UL /* Default value for AES_KEYHD */ +#define _AES_KEYHD_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHD */ + +#define _AES_KEYHD_KEYHD_SHIFT 0 /* Shift value for AES_KEYHD */ +#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHD */ +#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHD */ +#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHD */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_burtc.h b/nuttx/arch/arm/src/efm32/chip/efm32_burtc.h new file mode 100644 index 000000000..7cdc5cd34 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_burtc.h @@ -0,0 +1,471 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_burtc.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ + +#define EFM32_BURTC_NREGS 128 /* Number of backup retention registers */ + +/* BURTC Register Offsets ******************************************************************************************************/ + +#define EFM32_BURTC_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_BURTC_LPMODE_OFFSET 0x0004 /* Low power mode configuration */ +#define EFM32_BURTC_CNT_OFFSET 0x0008 /* Counter Value Register */ +#define EFM32_BURTC_COMP0_OFFSET 0x000c /* Counter Compare Value */ +#define EFM32_BURTC_TIMESTAMP_OFFSET 0x0010 /* Backup mode timestamp */ +#define EFM32_BURTC_LFXOFDET_OFFSET 0x0014 /* LFXO */ +#define EFM32_BURTC_STATUS_OFFSET 0x0018 /* Backup domain status */ +#define EFM32_BURTC_CMD_OFFSET 0x001c /* Command Register */ +#define EFM32_BURTC_POWERDOWN_OFFSET 0x0020 /* Retention RAM power-down resgister */ +#define EFM32_BURTC_LOCK_OFFSET 0x0024 /* Configuration Lock Register */ +#define EFM32_BURTC_IF_OFFSET 0x0028 /* Interrupt Flag Register */ +#define EFM32_BURTC_IFS_OFFSET 0x002c /* Interrupt Flag Set Register */ +#define EFM32_BURTC_IFC_OFFSET 0x0030 /* Interrupt Flag Clear Register */ +#define EFM32_BURTC_IEN_OFFSET 0x0034 /* Interrupt Enable Register */ +#define EFM32_BURTC_FREEZE_OFFSET 0x0038 /* Freeze Register */ +#define EFM32_BURTC_SYNCBUSY_OFFSET 0x003c /* Synchronization Busy Register */ + +/* Backup retention register */ + +#define EFM32_BURTC_RET_REG_OFFSET(n) (0x0100 + ((n) << 2)) + +/* BURTC Register Addresses ****************************************************************************************************/ + +#define EFM32_BURTC_CTRL (EFM32_BCKRTC_BASE+EFM32_BURTC_CTRL_OFFSET) +#define EFM32_BURTC_LPMODE (EFM32_BCKRTC_BASE+EFM32_BURTC_LPMODE_OFFSET) +#define EFM32_BURTC_CNT (EFM32_BCKRTC_BASE+EFM32_BURTC_CNT_OFFSET) +#define EFM32_BURTC_COMP0 (EFM32_BCKRTC_BASE+EFM32_BURTC_COMP0_OFFSET) +#define EFM32_BURTC_TIMESTAMP (EFM32_BCKRTC_BASE+EFM32_BURTC_TIMESTAMP_OFFSET) +#define EFM32_BURTC_LFXOFDET (EFM32_BCKRTC_BASE+EFM32_BURTC_LFXOFDET_OFFSET) +#define EFM32_BURTC_STATUS (EFM32_BCKRTC_BASE+EFM32_BURTC_STATUS_OFFSET) +#define EFM32_BURTC_CMD (EFM32_BCKRTC_BASE+EFM32_BURTC_CMD_OFFSET) +#define EFM32_BURTC_POWERDOWN (EFM32_BCKRTC_BASE+EFM32_BURTC_POWERDOWN_OFFSET) +#define EFM32_BURTC_LOCK (EFM32_BCKRTC_BASE+EFM32_BURTC_LOCK_OFFSET) +#define EFM32_BURTC_IF (EFM32_BCKRTC_BASE+EFM32_BURTC_IF_OFFSET) +#define EFM32_BURTC_IFS (EFM32_BCKRTC_BASE+EFM32_BURTC_IFS_OFFSET) +#define EFM32_BURTC_IFC (EFM32_BCKRTC_BASE+EFM32_BURTC_IFC_OFFSET) +#define EFM32_BURTC_IEN (EFM32_BCKRTC_BASE+EFM32_BURTC_IEN_OFFSET) +#define EFM32_BURTC_FREEZE (EFM32_BCKRTC_BASE+EFM32_BURTC_FREEZE_OFFSET) +#define EFM32_BURTC_SYNCBUSY (EFM32_BCKRTC_BASE+EFM32_BURTC_SYNCBUSY_OFFSET) + +/* Backup retention register */ + +#define EFM32_BURTC_RET_REG(n) (EFM32_BCKRTC_BASE+EFM32_BURTC_RET_REG_OFFSET(n)) + +/* BURTC Register Bit Field Definitions ****************************************************************************************/ + +/* Bit fields for BURTC CTRL */ + +#define _BURTC_CTRL_RESETVALUE 0x00000008UL /* Default value for BURTC_CTRL */ +#define _BURTC_CTRL_MASK 0x000077FFUL /* Mask for BURTC_CTRL */ + +#define _BURTC_CTRL_MODE_SHIFT 0 /* Shift value for BURTC_MODE */ +#define _BURTC_CTRL_MODE_MASK 0x3UL /* Bit mask for BURTC_MODE */ +#define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_CTRL */ +#define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /* Mode EM2EN for BURTC_CTRL */ +#define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /* Mode EM3EN for BURTC_CTRL */ +#define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /* Mode EM4EN for BURTC_CTRL */ +#define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /* Shifted mode DISABLE for BURTC_CTRL */ +#define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /* Shifted mode EM2EN for BURTC_CTRL */ +#define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /* Shifted mode EM3EN for BURTC_CTRL */ +#define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /* Shifted mode EM4EN for BURTC_CTRL */ +#define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /* Debug Mode Run Enable */ +#define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /* Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /* Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_RSTEN (0x1UL << 3) /* Enable BURTC reset */ +#define _BURTC_CTRL_RSTEN_SHIFT 3 /* Shift value for BURTC_RSTEN */ +#define _BURTC_CTRL_RSTEN_MASK 0x8UL /* Bit mask for BURTC_RSTEN */ +#define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /* Mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_COMP0TOP (0x1UL << 4) /* Compare clear enable */ +#define _BURTC_CTRL_COMP0TOP_SHIFT 4 /* Shift value for BURTC_COMP0TOP */ +#define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /* Bit mask for BURTC_COMP0TOP */ +#define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_SHIFT 5 /* Shift value for BURTC_LPCOMP */ +#define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /* Bit mask for BURTC_LPCOMP */ +#define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /* Mode IGN0LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /* Mode IGN1LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /* Mode IGN2LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /* Mode IGN3LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /* Mode IGN4LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /* Mode IGN5LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /* Mode IGN6LSB for BURTC_CTRL */ +#define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /* Mode IGN7LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /* Shifted mode IGN0LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /* Shifted mode IGN1LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /* Shifted mode IGN2LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /* Shifted mode IGN3LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /* Shifted mode IGN4LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /* Shifted mode IGN5LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /* Shifted mode IGN6LSB for BURTC_CTRL */ +#define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /* Shifted mode IGN7LSB for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_SHIFT 8 /* Shift value for BURTC_PRESC */ +#define _BURTC_CTRL_PRESC_MASK 0x700UL /* Bit mask for BURTC_PRESC */ +#define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /* Mode DIV1 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /* Mode DIV2 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /* Mode DIV4 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /* Mode DIV8 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /* Mode DIV16 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /* Mode DIV32 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /* Mode DIV64 for BURTC_CTRL */ +#define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /* Mode DIV128 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /* Shifted mode DIV1 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /* Shifted mode DIV2 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /* Shifted mode DIV4 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /* Shifted mode DIV8 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /* Shifted mode DIV16 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /* Shifted mode DIV32 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /* Shifted mode DIV64 for BURTC_CTRL */ +#define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /* Shifted mode DIV128 for BURTC_CTRL */ +#define _BURTC_CTRL_CLKSEL_SHIFT 12 /* Shift value for BURTC_CLKSEL */ +#define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /* Bit mask for BURTC_CLKSEL */ +#define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /* Mode NONE for BURTC_CTRL */ +#define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /* Mode LFRCO for BURTC_CTRL */ +#define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /* Mode LFXO for BURTC_CTRL */ +#define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /* Mode ULFRCO for BURTC_CTRL */ +#define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /* Shifted mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /* Shifted mode NONE for BURTC_CTRL */ +#define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /* Shifted mode LFRCO for BURTC_CTRL */ +#define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /* Shifted mode LFXO for BURTC_CTRL */ +#define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /* Shifted mode ULFRCO for BURTC_CTRL */ +#define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /* Backup mode timestamp enable */ +#define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /* Shift value for BURTC_BUMODETSEN */ +#define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /* Bit mask for BURTC_BUMODETSEN */ +#define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */ +#define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /* Shifted mode DEFAULT for BURTC_CTRL */ + +/* Bit fields for BURTC LPMODE */ + +#define _BURTC_LPMODE_RESETVALUE 0x00000000UL /* Default value for BURTC_LPMODE */ +#define _BURTC_LPMODE_MASK 0x00000003UL /* Mask for BURTC_LPMODE */ + +#define _BURTC_LPMODE_LPMODE_SHIFT 0 /* Shift value for BURTC_LPMODE */ +#define _BURTC_LPMODE_LPMODE_MASK 0x3UL /* Bit mask for BURTC_LPMODE */ +#define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LPMODE */ +#define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_LPMODE */ +#define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /* Mode ENABLE for BURTC_LPMODE */ +#define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /* Mode BUEN for BURTC_LPMODE */ +#define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LPMODE */ +#define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /* Shifted mode DISABLE for BURTC_LPMODE */ +#define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /* Shifted mode ENABLE for BURTC_LPMODE */ +#define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /* Shifted mode BUEN for BURTC_LPMODE */ + +/* Bit fields for BURTC CNT */ + +#define _BURTC_CNT_RESETVALUE 0x00000000UL /* Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /* Mask for BURTC_CNT */ + +#define _BURTC_CNT_CNT_SHIFT 0 /* Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC COMP0 */ + +#define _BURTC_COMP0_RESETVALUE 0x00000000UL /* Default value for BURTC_COMP0 */ +#define _BURTC_COMP0_MASK 0xFFFFFFFFUL /* Mask for BURTC_COMP0 */ + +#define _BURTC_COMP0_COMP0_SHIFT 0 /* Shift value for BURTC_COMP0 */ +#define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_COMP0 */ +#define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_COMP0 */ + +/* Bit fields for BURTC TIMESTAMP */ + +#define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /* Default value for BURTC_TIMESTAMP */ +#define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /* Mask for BURTC_TIMESTAMP */ + +#define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /* Shift value for BURTC_TIMESTAMP */ +#define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_TIMESTAMP */ +#define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_TIMESTAMP */ +#define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_TIMESTAMP */ + +/* Bit fields for BURTC LFXOFDET */ + +#define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /* Default value for BURTC_LFXOFDET */ +#define _BURTC_LFXOFDET_MASK 0x000001F3UL /* Mask for BURTC_LFXOFDET */ + +#define _BURTC_LFXOFDET_OSC_SHIFT 0 /* Shift value for BURTC_OSC */ +#define _BURTC_LFXOFDET_OSC_MASK 0x3UL /* Bit mask for BURTC_OSC */ +#define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LFXOFDET */ +#define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_LFXOFDET */ +#define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /* Mode LFRCO for BURTC_LFXOFDET */ +#define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /* Mode ULFRCO for BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /* Shifted mode DISABLE for BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /* Shifted mode LFRCO for BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /* Shifted mode ULFRCO for BURTC_LFXOFDET */ +#define _BURTC_LFXOFDET_TOP_SHIFT 4 /* Shift value for BURTC_TOP */ +#define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /* Bit mask for BURTC_TOP */ +#define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /* Shifted mode DEFAULT for BURTC_LFXOFDET */ + +/* Bit fields for BURTC STATUS */ + +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /* Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000007UL /* Mask for BURTC_STATUS */ + +#define BURTC_STATUS_LPMODEACT (0x1UL << 0) /* Low power mode active */ +#define _BURTC_STATUS_LPMODEACT_SHIFT 0 /* Shift value for BURTC_LPMODEACT */ +#define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /* Bit mask for BURTC_LPMODEACT */ +#define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_BUMODETS (0x1UL << 1) /* Timestamp for backup mode entry stored. */ +#define _BURTC_STATUS_BUMODETS_SHIFT 1 /* Shift value for BURTC_BUMODETS */ +#define _BURTC_STATUS_BUMODETS_MASK 0x2UL /* Bit mask for BURTC_BUMODETS */ +#define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RAMWERR (0x1UL << 2) /* RAM write error. */ +#define _BURTC_STATUS_RAMWERR_SHIFT 2 /* Shift value for BURTC_RAMWERR */ +#define _BURTC_STATUS_RAMWERR_MASK 0x4UL /* Bit mask for BURTC_RAMWERR */ +#define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_STATUS */ + +/* Bit fields for BURTC CMD */ + +#define _BURTC_CMD_RESETVALUE 0x00000000UL /* Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000001UL /* Mask for BURTC_CMD */ + +#define BURTC_CMD_CLRSTATUS (0x1UL << 0) /* Clear BURTC_STATUS register. */ +#define _BURTC_CMD_CLRSTATUS_SHIFT 0 /* Shift value for BURTC_CLRSTATUS */ +#define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /* Bit mask for BURTC_CLRSTATUS */ +#define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC POWERDOWN */ + +#define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /* Default value for BURTC_POWERDOWN */ +#define _BURTC_POWERDOWN_MASK 0x00000001UL /* Mask for BURTC_POWERDOWN */ + +#define BURTC_POWERDOWN_RAM (0x1UL << 0) /* Retention RAM power-down */ +#define _BURTC_POWERDOWN_RAM_SHIFT 0 /* Shift value for BURTC_RAM */ +#define _BURTC_POWERDOWN_RAM_MASK 0x1UL /* Bit mask for BURTC_RAM */ +#define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_POWERDOWN */ +#define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_POWERDOWN */ + +/* Bit fields for BURTC LOCK */ + +#define _BURTC_LOCK_RESETVALUE 0x00000000UL /* Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /* Mask for BURTC_LOCK */ + +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /* Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /* Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /* Mode LOCK for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /* Mode UNLOCKED for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /* Mode LOCKED for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /* Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /* Shifted mode LOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /* Shifted mode UNLOCKED for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC IF */ + +#define _BURTC_IF_RESETVALUE 0x00000000UL /* Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000007UL /* Mask for BURTC_IF */ + +#define BURTC_IF_OF (0x1UL << 0) /* Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /* Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /* Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP0 (0x1UL << 1) /* Compare match Interrupt Flag */ +#define _BURTC_IF_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */ +#define _BURTC_IF_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_LFXOFAIL (0x1UL << 2) /* LFXO failure Interrupt Flag */ +#define _BURTC_IF_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */ +#define _BURTC_IF_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */ +#define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IFS */ + +#define _BURTC_IFS_RESETVALUE 0x00000000UL /* Default value for BURTC_IFS */ +#define _BURTC_IFS_MASK 0x00000007UL /* Mask for BURTC_IFS */ + +#define BURTC_IFS_OF (0x1UL << 0) /* Set Overflow Interrupt Flag */ +#define _BURTC_IFS_OF_SHIFT 0 /* Shift value for BURTC_OF */ +#define _BURTC_IFS_OF_MASK 0x1UL /* Bit mask for BURTC_OF */ +#define _BURTC_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */ +#define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IFS */ +#define BURTC_IFS_COMP0 (0x1UL << 1) /* Set compare match Interrupt Flag */ +#define _BURTC_IFS_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */ +#define _BURTC_IFS_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */ +#define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IFS */ +#define BURTC_IFS_LFXOFAIL (0x1UL << 2) /* Set LFXO fail Interrupt Flag */ +#define _BURTC_IFS_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */ +#define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */ +#define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */ +#define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IFS */ + +/* Bit fields for BURTC IFC */ + +#define _BURTC_IFC_RESETVALUE 0x00000000UL /* Default value for BURTC_IFC */ +#define _BURTC_IFC_MASK 0x00000007UL /* Mask for BURTC_IFC */ + +#define BURTC_IFC_OF (0x1UL << 0) /* Clear Overflow Interrupt Flag */ +#define _BURTC_IFC_OF_SHIFT 0 /* Shift value for BURTC_OF */ +#define _BURTC_IFC_OF_MASK 0x1UL /* Bit mask for BURTC_OF */ +#define _BURTC_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */ +#define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IFC */ +#define BURTC_IFC_COMP0 (0x1UL << 1) /* Clear compare match Interrupt Flag */ +#define _BURTC_IFC_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */ +#define _BURTC_IFC_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */ +#define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IFC */ +#define BURTC_IFC_LFXOFAIL (0x1UL << 2) /* Clear LFXO failure Interrupt Flag */ +#define _BURTC_IFC_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */ +#define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */ +#define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */ +#define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IFC */ + +/* Bit fields for BURTC IEN */ + +#define _BURTC_IEN_RESETVALUE 0x00000000UL /* Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000007UL /* Mask for BURTC_IEN */ + +#define BURTC_IEN_OF (0x1UL << 0) /* Overflow Interrupt Enable */ +#define _BURTC_IEN_OF_SHIFT 0 /* Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /* Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP0 (0x1UL << 1) /* Compare match Interrupt Enable */ +#define _BURTC_IEN_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */ +#define _BURTC_IEN_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_LFXOFAIL (0x1UL << 2) /* LFXO failure Interrupt Enable */ +#define _BURTC_IEN_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */ +#define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */ +#define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC FREEZE */ + +#define _BURTC_FREEZE_RESETVALUE 0x00000000UL /* Default value for BURTC_FREEZE */ +#define _BURTC_FREEZE_MASK 0x00000001UL /* Mask for BURTC_FREEZE */ + +#define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */ +#define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for BURTC_REGFREEZE */ +#define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for BURTC_REGFREEZE */ +#define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_FREEZE */ +#define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for BURTC_FREEZE */ +#define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for BURTC_FREEZE */ +#define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_FREEZE */ +#define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for BURTC_FREEZE */ +#define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for BURTC_FREEZE */ + +/* Bit fields for BURTC SYNCBUSY */ + +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x00000003UL /* Mask for BURTC_SYNCBUSY */ + +#define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /* LPMODE Register Busy */ +#define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /* Shift value for BURTC_LPMODE */ +#define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /* Bit mask for BURTC_LPMODE */ +#define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /* COMP0 Register Busy */ +#define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */ +#define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */ +#define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC RET_REG */ + +#define _BURTC_RET_REG_RESETVALUE 0x00000000UL /* Default value for BURTC_RET_REG */ +#define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /* Mask for BURTC_RET_REG */ + +#define _BURTC_RET_REG_REG_SHIFT 0 /* Shift value for REG */ +#define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /* Bit mask for REG */ +#define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_RET_REG */ +#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_RET_REG */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_calibrate.h b/nuttx/arch/arm/src/efm32/chip/efm32_calibrate.h new file mode 100644 index 000000000..7fb84d1e3 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_calibrate.h @@ -0,0 +1,93 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_calibrate.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ + +#define CALIBRATE_MAX_REGISTERS 50 /* Max number of address/value pairs for calibration */ + +#define CALIBRATE ((const struct efm32_calibrate_s *)EFM32_CALIBRATE_BASE) + +/******************************************************************************************************************************* + * Public Type Definitions + *******************************************************************************************************************************/ + +struct efm32_calibrate_s +{ + const uint32_t address; /* Address of calibration register */ + const uint32_t value; /* Default value for calibration register */ +}; + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_cmu.h b/nuttx/arch/arm/src/efm32/chip/efm32_cmu.h index add85443d..ffefddd69 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_cmu.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_cmu.h @@ -65,8 +65,13 @@ * Included Files *******************************************************************************************************************************/ +#include <nuttx/config.h> #include "chip/efm32_memorymap.h" +#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G) +# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture +#endif + /******************************************************************************************************************************* * Pre-processor Definitions *******************************************************************************************************************************/ @@ -611,8 +616,13 @@ /* Bit fields for CMU LFCLKSEL */ -#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#if defined(CONFIG_EFM32_EFM32GG) +# define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#elif defined(CONFIG_EFM32_EFM32G) +# define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#endif #define _CMU_LFCLKSEL_LFA_SHIFT 0 /* Shift value for CMU_LFA */ #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /* Bit mask for CMU_LFA */ @@ -638,24 +648,27 @@ #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /* Shifted mode LFRCO for CMU_LFCLKSEL */ #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /* Shifted mode LFXO for CMU_LFCLKSEL */ #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /* Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /* Clock Select for LFA Extended */ -#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /* Shift value for CMU_LFAE */ -#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /* Bit mask for CMU_LFAE */ -#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /* Shifted mode DISABLED for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /* Clock Select for LFB Extended */ -#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /* Shift value for CMU_LFBE */ -#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /* Bit mask for CMU_LFBE */ -#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /* Shifted mode DISABLED for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ + +#if defined(CONFIG_EFM32_EFM32GG) +# define CMU_LFCLKSEL_LFAE (0x1UL << 16) /* Clock Select for LFA Extended */ +# define _CMU_LFCLKSEL_LFAE_SHIFT 16 /* Shift value for CMU_LFAE */ +# define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /* Bit mask for CMU_LFAE */ +# define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /* Shifted mode DISABLED for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE (0x1UL << 20) /* Clock Select for LFB Extended */ +# define _CMU_LFCLKSEL_LFBE_SHIFT 20 /* Shift value for CMU_LFBE */ +# define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /* Bit mask for CMU_LFBE */ +# define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /* Shifted mode DISABLED for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ +#endif /* Bit fields for CMU STATUS */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_dac.h b/nuttx/arch/arm/src/efm32/chip/efm32_dac.h new file mode 100644 index 000000000..58aec484d --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_dac.h @@ -0,0 +1,883 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_dac.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* DAC Register Offsets ********************************************************************************************************/ + +#define EFM32_DAC_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_DAC_STATUS_OFFSET 0x0004 /* Status Register */ +#define EFM32_DAC_CH0CTRL_OFFSET 0x0008 /* Channel 0 Control Register */ +#define EFM32_DAC_CH1CTRL_OFFSET 0x000c /* Channel 1 Control Register */ +#define EFM32_DAC_IEN_OFFSET 0x0010 /* Interrupt Enable Register */ +#define EFM32_DAC_IF_OFFSET 0x0014 /* Interrupt Flag Register */ +#define EFM32_DAC_IFS_OFFSET 0x0018 /* Interrupt Flag Set Register */ +#define EFM32_DAC_IFC_OFFSET 0x001c /* Interrupt Flag Clear Register */ +#define EFM32_DAC_CH0DATA_OFFSET 0x0020 /* Channel 0 Data Register */ +#define EFM32_DAC_CH1DATA_OFFSET 0x0024 /* Channel 1 Data Register */ +#define EFM32_DAC_COMBDATA_OFFSET 0x0028 /* Combined Data Register */ +#define EFM32_DAC_CAL_OFFSET 0x002c /* Calibration Register */ +#define EFM32_DAC_BIASPROG_OFFSET 0x0030 /* Bias Programming Register */ +#define EFM32_DAC_OPACTRL_OFFSET 0x0054 /* Operational Amplifier Control Register */ +#define EFM32_DAC_OPAOFFSET_OFFSET 0x0058 /* Operational Amplifier Offset Register */ +#define EFM32_DAC_OPA0MUX_OFFSET 0x005c /* Operational Amplifier Mux Configuration Register */ +#define EFM32_DAC_OPA1MUX_OFFSET 0x0060 /* Operational Amplifier Mux Configuration Register */ +#define EFM32_DAC_OPA2MUX_OFFSET 0x0064 /* Operational Amplifier Mux Configuration Register */ + +/* DAC Register Addresses ******************************************************************************************************/ + +#define EFM32_DAC0_CTRL (EFM32_DAC0_BASE+EFM32_DAC_CTRL_OFFSET) +#define EFM32_DAC0_STATUS (EFM32_DAC0_BASE+EFM32_DAC_STATUS_OFFSET) +#define EFM32_DAC0_CH0CTRL (EFM32_DAC0_BASE+EFM32_DAC_CH0CTRL_OFFSET) +#define EFM32_DAC0_CH1CTRL (EFM32_DAC0_BASE+EFM32_DAC_CH1CTRL_OFFSET) +#define EFM32_DAC0_IEN (EFM32_DAC0_BASE+EFM32_DAC_IEN_OFFSET) +#define EFM32_DAC0_IF (EFM32_DAC0_BASE+EFM32_DAC_IF_OFFSET) +#define EFM32_DAC0_IFS (EFM32_DAC0_BASE+EFM32_DAC_IFS_OFFSET) +#define EFM32_DAC0_IFC (EFM32_DAC0_BASE+EFM32_DAC_IFC_OFFSET) +#define EFM32_DAC0_CH0DATA (EFM32_DAC0_BASE+EFM32_DAC_CH0DATA_OFFSET) +#define EFM32_DAC0_CH1DATA (EFM32_DAC0_BASE+EFM32_DAC_CH1DATA_OFFSET) +#define EFM32_DAC0_COMBDATA (EFM32_DAC0_BASE+EFM32_DAC_COMBDATA_OFFSET) +#define EFM32_DAC0_CAL (EFM32_DAC0_BASE+EFM32_DAC_CAL_OFFSET) +#define EFM32_DAC0_BIASPROG (EFM32_DAC0_BASE+EFM32_DAC_BIASPROG_OFFSET) +#define EFM32_DAC0_OPACTRL (EFM32_DAC0_BASE+EFM32_DAC_OPACTRL_OFFSET) +#define EFM32_DAC0_OPAOFFSET (EFM32_DAC0_BASE+EFM32_DAC_OPAOFFSET_OFFSET) +#define EFM32_DAC0_OPA0MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA0MUX_OFFSET) +#define EFM32_DAC0_OPA1MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA1MUX_OFFSET) +#define EFM32_DAC0_OPA2MUX (EFM32_DAC0_BASE+EFM32_DAC_OPA2MUX_OFFSET) + +/* DAC Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for DAC CTRL */ + +#define _DAC_CTRL_RESETVALUE 0x00000010UL /* Default value for DAC_CTRL */ +#define _DAC_CTRL_MASK 0x003703FFUL /* Mask for DAC_CTRL */ + +#define DAC_CTRL_DIFF (0x1UL << 0) /* Differential Mode */ +#define _DAC_CTRL_DIFF_SHIFT 0 /* Shift value for DAC_DIFF */ +#define _DAC_CTRL_DIFF_MASK 0x1UL /* Bit mask for DAC_DIFF */ +#define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_SINEMODE (0x1UL << 1) /* Sine Mode */ +#define _DAC_CTRL_SINEMODE_SHIFT 1 /* Shift value for DAC_SINEMODE */ +#define _DAC_CTRL_SINEMODE_MASK 0x2UL /* Bit mask for DAC_SINEMODE */ +#define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SHIFT 2 /* Shift value for DAC_CONVMODE */ +#define _DAC_CTRL_CONVMODE_MASK 0xCUL /* Bit mask for DAC_CONVMODE */ +#define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /* Mode CONTINUOUS for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /* Mode SAMPLEHOLD for DAC_CTRL */ +#define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /* Mode SAMPLEOFF for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /* Shifted mode CONTINUOUS for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /* Shifted mode SAMPLEHOLD for DAC_CTRL */ +#define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /* Shifted mode SAMPLEOFF for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_SHIFT 4 /* Shift value for DAC_OUTMODE */ +#define _DAC_CTRL_OUTMODE_MASK 0x30UL /* Bit mask for DAC_OUTMODE */ +#define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /* Mode DISABLE for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /* Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /* Mode PIN for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /* Mode ADC for DAC_CTRL */ +#define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /* Mode PINADC for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /* Shifted mode DISABLE for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /* Shifted mode PIN for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /* Shifted mode ADC for DAC_CTRL */ +#define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /* Shifted mode PINADC for DAC_CTRL */ +#define DAC_CTRL_OUTENPRS (0x1UL << 6) /* PRS Controlled Output Enable */ +#define _DAC_CTRL_OUTENPRS_SHIFT 6 /* Shift value for DAC_OUTENPRS */ +#define _DAC_CTRL_OUTENPRS_MASK 0x40UL /* Bit mask for DAC_OUTENPRS */ +#define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /* Channel 0 Start Reset Prescaler */ +#define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /* Shift value for DAC_CH0PRESCRST */ +#define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /* Bit mask for DAC_CH0PRESCRST */ +#define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /* Shifted mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_SHIFT 8 /* Shift value for DAC_REFSEL */ +#define _DAC_CTRL_REFSEL_MASK 0x300UL /* Bit mask for DAC_REFSEL */ +#define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_1V25 0x00000000UL /* Mode 1V25 for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_2V5 0x00000001UL /* Mode 2V5 for DAC_CTRL */ +#define _DAC_CTRL_REFSEL_VDD 0x00000002UL /* Mode VDD for DAC_CTRL */ +#define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /* Shifted mode 1V25 for DAC_CTRL */ +#define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /* Shifted mode 2V5 for DAC_CTRL */ +#define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /* Shifted mode VDD for DAC_CTRL */ +#define _DAC_CTRL_PRESC_SHIFT 16 /* Shift value for DAC_PRESC */ +#define _DAC_CTRL_PRESC_MASK 0x70000UL /* Bit mask for DAC_PRESC */ +#define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /* Mode NODIVISION for DAC_CTRL */ +#define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /* Shifted mode NODIVISION for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_SHIFT 20 /* Shift value for DAC_REFRSEL */ +#define _DAC_CTRL_REFRSEL_MASK 0x300000UL /* Bit mask for DAC_REFRSEL */ +#define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /* Mode 8CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /* Mode 16CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /* Mode 32CYCLES for DAC_CTRL */ +#define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /* Mode 64CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /* Shifted mode DEFAULT for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /* Shifted mode 8CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /* Shifted mode 16CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /* Shifted mode 32CYCLES for DAC_CTRL */ +#define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /* Shifted mode 64CYCLES for DAC_CTRL */ + +/* Bit fields for DAC STATUS */ + +#define _DAC_STATUS_RESETVALUE 0x00000000UL /* Default value for DAC_STATUS */ +#define _DAC_STATUS_MASK 0x00000003UL /* Mask for DAC_STATUS */ + +#define DAC_STATUS_CH0DV (0x1UL << 0) /* Channel 0 Data Valid */ +#define _DAC_STATUS_CH0DV_SHIFT 0 /* Shift value for DAC_CH0DV */ +#define _DAC_STATUS_CH0DV_MASK 0x1UL /* Bit mask for DAC_CH0DV */ +#define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_STATUS */ +#define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_STATUS */ +#define DAC_STATUS_CH1DV (0x1UL << 1) /* Channel 1 Data Valid */ +#define _DAC_STATUS_CH1DV_SHIFT 1 /* Shift value for DAC_CH1DV */ +#define _DAC_STATUS_CH1DV_MASK 0x2UL /* Bit mask for DAC_CH1DV */ +#define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_STATUS */ +#define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_STATUS */ + +/* Bit fields for DAC CH0CTRL */ + +#define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /* Default value for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_MASK 0x000000F7UL /* Mask for DAC_CH0CTRL */ + +#define DAC_CH0CTRL_EN (0x1UL << 0) /* Channel 0 Enable */ +#define _DAC_CH0CTRL_EN_SHIFT 0 /* Shift value for DAC_EN */ +#define _DAC_CH0CTRL_EN_MASK 0x1UL /* Bit mask for DAC_EN */ +#define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_REFREN (0x1UL << 1) /* Channel 0 Automatic Refresh Enable */ +#define _DAC_CH0CTRL_REFREN_SHIFT 1 /* Shift value for DAC_REFREN */ +#define _DAC_CH0CTRL_REFREN_MASK 0x2UL /* Bit mask for DAC_REFREN */ +#define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSEN (0x1UL << 2) /* Channel 0 PRS Trigger Enable */ +#define _DAC_CH0CTRL_PRSEN_SHIFT 2 /* Shift value for DAC_PRSEN */ +#define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /* Bit mask for DAC_PRSEN */ +#define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /* Shifted mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /* Shift value for DAC_PRSSEL */ +#define _DAC_CH0CTRL_PRSSEL_MASK 0xF0UL /* Bit mask for DAC_PRSSEL */ +#define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for DAC_CH0CTRL */ +#define _DAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /* Shifted mode PRSCH0 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /* Shifted mode PRSCH1 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /* Shifted mode PRSCH2 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /* Shifted mode PRSCH3 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /* Shifted mode PRSCH4 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /* Shifted mode PRSCH5 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /* Shifted mode PRSCH6 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /* Shifted mode PRSCH7 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH8 (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4) /* Shifted mode PRSCH8 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH9 (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4) /* Shifted mode PRSCH9 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH10 (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /* Shifted mode PRSCH10 for DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_PRSCH11 (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /* Shifted mode PRSCH11 for DAC_CH0CTRL */ + +/* Bit fields for DAC CH1CTRL */ + +#define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /* Default value for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_MASK 0x000000F7UL /* Mask for DAC_CH1CTRL */ + +#define DAC_CH1CTRL_EN (0x1UL << 0) /* Channel 1 Enable */ +#define _DAC_CH1CTRL_EN_SHIFT 0 /* Shift value for DAC_EN */ +#define _DAC_CH1CTRL_EN_MASK 0x1UL /* Bit mask for DAC_EN */ +#define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_REFREN (0x1UL << 1) /* Channel 1 Automatic Refresh Enable */ +#define _DAC_CH1CTRL_REFREN_SHIFT 1 /* Shift value for DAC_REFREN */ +#define _DAC_CH1CTRL_REFREN_MASK 0x2UL /* Bit mask for DAC_REFREN */ +#define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSEN (0x1UL << 2) /* Channel 1 PRS Trigger Enable */ +#define _DAC_CH1CTRL_PRSEN_SHIFT 2 /* Shift value for DAC_PRSEN */ +#define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /* Bit mask for DAC_PRSEN */ +#define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /* Shifted mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /* Shift value for DAC_PRSSEL */ +#define _DAC_CH1CTRL_PRSSEL_MASK 0xF0UL /* Bit mask for DAC_PRSSEL */ +#define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for DAC_CH1CTRL */ +#define _DAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /* Shifted mode PRSCH0 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /* Shifted mode PRSCH1 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /* Shifted mode PRSCH2 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /* Shifted mode PRSCH3 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /* Shifted mode PRSCH4 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /* Shifted mode PRSCH5 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /* Shifted mode PRSCH6 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /* Shifted mode PRSCH7 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH8 (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4) /* Shifted mode PRSCH8 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH9 (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4) /* Shifted mode PRSCH9 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH10 (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /* Shifted mode PRSCH10 for DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_PRSCH11 (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /* Shifted mode PRSCH11 for DAC_CH1CTRL */ + +/* Bit fields for DAC IEN */ + +#define _DAC_IEN_RESETVALUE 0x00000000UL /* Default value for DAC_IEN */ +#define _DAC_IEN_MASK 0x00000033UL /* Mask for DAC_IEN */ + +#define DAC_IEN_CH0 (0x1UL << 0) /* Channel 0 Conversion Complete Interrupt Enable */ +#define _DAC_IEN_CH0_SHIFT 0 /* Shift value for DAC_CH0 */ +#define _DAC_IEN_CH0_MASK 0x1UL /* Bit mask for DAC_CH0 */ +#define _DAC_IEN_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1 (0x1UL << 1) /* Channel 1 Conversion Complete Interrupt Enable */ +#define _DAC_IEN_CH1_SHIFT 1 /* Shift value for DAC_CH1 */ +#define _DAC_IEN_CH1_MASK 0x2UL /* Bit mask for DAC_CH1 */ +#define _DAC_IEN_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH0UF (0x1UL << 4) /* Channel 0 Conversion Data Underflow Interrupt Enable */ +#define _DAC_IEN_CH0UF_SHIFT 4 /* Shift value for DAC_CH0UF */ +#define _DAC_IEN_CH0UF_MASK 0x10UL /* Bit mask for DAC_CH0UF */ +#define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1UF (0x1UL << 5) /* Channel 1 Conversion Data Underflow Interrupt Enable */ +#define _DAC_IEN_CH1UF_SHIFT 5 /* Shift value for DAC_CH1UF */ +#define _DAC_IEN_CH1UF_MASK 0x20UL /* Bit mask for DAC_CH1UF */ +#define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IEN */ +#define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /* Shifted mode DEFAULT for DAC_IEN */ + +/* Bit fields for DAC IF */ + +#define _DAC_IF_RESETVALUE 0x00000000UL /* Default value for DAC_IF */ +#define _DAC_IF_MASK 0x00000033UL /* Mask for DAC_IF */ + +#define DAC_IF_CH0 (0x1UL << 0) /* Channel 0 Conversion Complete Interrupt Flag */ +#define _DAC_IF_CH0_SHIFT 0 /* Shift value for DAC_CH0 */ +#define _DAC_IF_CH0_MASK 0x1UL /* Bit mask for DAC_CH0 */ +#define _DAC_IF_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1 (0x1UL << 1) /* Channel 1 Conversion Complete Interrupt Flag */ +#define _DAC_IF_CH1_SHIFT 1 /* Shift value for DAC_CH1 */ +#define _DAC_IF_CH1_MASK 0x2UL /* Bit mask for DAC_CH1 */ +#define _DAC_IF_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_IF */ +#define DAC_IF_CH0UF (0x1UL << 4) /* Channel 0 Data Underflow Interrupt Flag */ +#define _DAC_IF_CH0UF_SHIFT 4 /* Shift value for DAC_CH0UF */ +#define _DAC_IF_CH0UF_MASK 0x10UL /* Bit mask for DAC_CH0UF */ +#define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1UF (0x1UL << 5) /* Channel 1 Data Underflow Interrupt Flag */ +#define _DAC_IF_CH1UF_SHIFT 5 /* Shift value for DAC_CH1UF */ +#define _DAC_IF_CH1UF_MASK 0x20UL /* Bit mask for DAC_CH1UF */ +#define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IF */ +#define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /* Shifted mode DEFAULT for DAC_IF */ + +/* Bit fields for DAC IFS */ + +#define _DAC_IFS_RESETVALUE 0x00000000UL /* Default value for DAC_IFS */ +#define _DAC_IFS_MASK 0x00000033UL /* Mask for DAC_IFS */ + +#define DAC_IFS_CH0 (0x1UL << 0) /* Channel 0 Conversion Complete Interrupt Flag Set */ +#define _DAC_IFS_CH0_SHIFT 0 /* Shift value for DAC_CH0 */ +#define _DAC_IFS_CH0_MASK 0x1UL /* Bit mask for DAC_CH0 */ +#define _DAC_IFS_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1 (0x1UL << 1) /* Channel 1 Conversion Complete Interrupt Flag Set */ +#define _DAC_IFS_CH1_SHIFT 1 /* Shift value for DAC_CH1 */ +#define _DAC_IFS_CH1_MASK 0x2UL /* Bit mask for DAC_CH1 */ +#define _DAC_IFS_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH0UF (0x1UL << 4) /* Channel 0 Data Underflow Interrupt Flag Set */ +#define _DAC_IFS_CH0UF_SHIFT 4 /* Shift value for DAC_CH0UF */ +#define _DAC_IFS_CH0UF_MASK 0x10UL /* Bit mask for DAC_CH0UF */ +#define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1UF (0x1UL << 5) /* Channel 1 Data Underflow Interrupt Flag Set */ +#define _DAC_IFS_CH1UF_SHIFT 5 /* Shift value for DAC_CH1UF */ +#define _DAC_IFS_CH1UF_MASK 0x20UL /* Bit mask for DAC_CH1UF */ +#define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFS */ +#define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /* Shifted mode DEFAULT for DAC_IFS */ + +/* Bit fields for DAC IFC */ + +#define _DAC_IFC_RESETVALUE 0x00000000UL /* Default value for DAC_IFC */ +#define _DAC_IFC_MASK 0x00000033UL /* Mask for DAC_IFC */ + +#define DAC_IFC_CH0 (0x1UL << 0) /* Channel 0 Conversion Complete Interrupt Flag Clear */ +#define _DAC_IFC_CH0_SHIFT 0 /* Shift value for DAC_CH0 */ +#define _DAC_IFC_CH0_MASK 0x1UL /* Bit mask for DAC_CH0 */ +#define _DAC_IFC_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1 (0x1UL << 1) /* Channel 1 Conversion Complete Interrupt Flag Clear */ +#define _DAC_IFC_CH1_SHIFT 1 /* Shift value for DAC_CH1 */ +#define _DAC_IFC_CH1_MASK 0x2UL /* Bit mask for DAC_CH1 */ +#define _DAC_IFC_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH0UF (0x1UL << 4) /* Channel 0 Data Underflow Interrupt Flag Clear */ +#define _DAC_IFC_CH0UF_SHIFT 4 /* Shift value for DAC_CH0UF */ +#define _DAC_IFC_CH0UF_MASK 0x10UL /* Bit mask for DAC_CH0UF */ +#define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1UF (0x1UL << 5) /* Channel 1 Data Underflow Interrupt Flag Clear */ +#define _DAC_IFC_CH1UF_SHIFT 5 /* Shift value for DAC_CH1UF */ +#define _DAC_IFC_CH1UF_MASK 0x20UL /* Bit mask for DAC_CH1UF */ +#define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_IFC */ +#define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /* Shifted mode DEFAULT for DAC_IFC */ + +/* Bit fields for DAC CH0DATA */ + +#define _DAC_CH0DATA_RESETVALUE 0x00000000UL /* Default value for DAC_CH0DATA */ +#define _DAC_CH0DATA_MASK 0x00000FFFUL /* Mask for DAC_CH0DATA */ + +#define _DAC_CH0DATA_DATA_SHIFT 0 /* Shift value for DAC_DATA */ +#define _DAC_CH0DATA_DATA_MASK 0xFFFUL /* Bit mask for DAC_DATA */ +#define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH0DATA */ +#define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CH0DATA */ + +/* Bit fields for DAC CH1DATA */ + +#define _DAC_CH1DATA_RESETVALUE 0x00000000UL /* Default value for DAC_CH1DATA */ +#define _DAC_CH1DATA_MASK 0x00000FFFUL /* Mask for DAC_CH1DATA */ + +#define _DAC_CH1DATA_DATA_SHIFT 0 /* Shift value for DAC_DATA */ +#define _DAC_CH1DATA_DATA_MASK 0xFFFUL /* Bit mask for DAC_DATA */ +#define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CH1DATA */ +#define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CH1DATA */ + +/* Bit fields for DAC COMBDATA */ + +#define _DAC_COMBDATA_RESETVALUE 0x00000000UL /* Default value for DAC_COMBDATA */ +#define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /* Mask for DAC_COMBDATA */ + +#define _DAC_COMBDATA_CH0DATA_SHIFT 0 /* Shift value for DAC_CH0DATA */ +#define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /* Bit mask for DAC_CH0DATA */ +#define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_COMBDATA */ +#define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_COMBDATA */ +#define _DAC_COMBDATA_CH1DATA_SHIFT 16 /* Shift value for DAC_CH1DATA */ +#define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /* Bit mask for DAC_CH1DATA */ +#define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_COMBDATA */ +#define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /* Shifted mode DEFAULT for DAC_COMBDATA */ + +/* Bit fields for DAC CAL */ + +#define _DAC_CAL_RESETVALUE 0x00400000UL /* Default value for DAC_CAL */ +#define _DAC_CAL_MASK 0x007F3F3FUL /* Mask for DAC_CAL */ + +#define _DAC_CAL_CH0OFFSET_SHIFT 0 /* Shift value for DAC_CH0OFFSET */ +#define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /* Bit mask for DAC_CH0OFFSET */ +#define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CAL */ +#define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_CH1OFFSET_SHIFT 8 /* Shift value for DAC_CH1OFFSET */ +#define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /* Bit mask for DAC_CH1OFFSET */ +#define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_CAL */ +#define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_CAL */ +#define _DAC_CAL_GAIN_SHIFT 16 /* Shift value for DAC_GAIN */ +#define _DAC_CAL_GAIN_MASK 0x7F0000UL /* Bit mask for DAC_GAIN */ +#define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /* Mode DEFAULT for DAC_CAL */ +#define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /* Shifted mode DEFAULT for DAC_CAL */ + +/* Bit fields for DAC BIASPROG */ + +#define _DAC_BIASPROG_RESETVALUE 0x00004747UL /* Default value for DAC_BIASPROG */ +#define _DAC_BIASPROG_MASK 0x00004F4FUL /* Mask for DAC_BIASPROG */ + +#define _DAC_BIASPROG_BIASPROG_SHIFT 0 /* Shift value for DAC_BIASPROG */ +#define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /* Bit mask for DAC_BIASPROG */ +#define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /* Half Bias Current */ +#define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /* Shift value for DAC_HALFBIAS */ +#define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /* Bit mask for DAC_HALFBIAS */ +#define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /* Shifted mode DEFAULT for DAC_BIASPROG */ +#define _DAC_BIASPROG_OPA2BIASPROG_SHIFT 8 /* Shift value for DAC_OPA2BIASPROG */ +#define _DAC_BIASPROG_OPA2BIASPROG_MASK 0xF00UL /* Bit mask for DAC_OPA2BIASPROG */ +#define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_OPA2BIASPROG_DEFAULT (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_OPA2HALFBIAS (0x1UL << 14) /* Half Bias Current */ +#define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT 14 /* Shift value for DAC_OPA2HALFBIAS */ +#define _DAC_BIASPROG_OPA2HALFBIAS_MASK 0x4000UL /* Bit mask for DAC_OPA2HALFBIAS */ +#define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for DAC_BIASPROG */ +#define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /* Shifted mode DEFAULT for DAC_BIASPROG */ + +/* Bit fields for DAC OPACTRL */ + +#define _DAC_OPACTRL_RESETVALUE 0x00000000UL /* Default value for DAC_OPACTRL */ +#define _DAC_OPACTRL_MASK 0x01C3F1C7UL /* Mask for DAC_OPACTRL */ + +#define DAC_OPACTRL_OPA0EN (0x1UL << 0) /* OPA0 Enable */ +#define _DAC_OPACTRL_OPA0EN_SHIFT 0 /* Shift value for DAC_OPA0EN */ +#define _DAC_OPACTRL_OPA0EN_MASK 0x1UL /* Bit mask for DAC_OPA0EN */ +#define _DAC_OPACTRL_OPA0EN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0EN_DEFAULT (_DAC_OPACTRL_OPA0EN_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1EN (0x1UL << 1) /* OPA1 Enable */ +#define _DAC_OPACTRL_OPA1EN_SHIFT 1 /* Shift value for DAC_OPA1EN */ +#define _DAC_OPACTRL_OPA1EN_MASK 0x2UL /* Bit mask for DAC_OPA1EN */ +#define _DAC_OPACTRL_OPA1EN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1EN_DEFAULT (_DAC_OPACTRL_OPA1EN_DEFAULT << 1) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2EN (0x1UL << 2) /* OPA2 Enable */ +#define _DAC_OPACTRL_OPA2EN_SHIFT 2 /* Shift value for DAC_OPA2EN */ +#define _DAC_OPACTRL_OPA2EN_MASK 0x4UL /* Bit mask for DAC_OPA2EN */ +#define _DAC_OPACTRL_OPA2EN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2EN_DEFAULT (_DAC_OPACTRL_OPA2EN_DEFAULT << 2) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0HCMDIS (0x1UL << 6) /* High Common Mode Disable. */ +#define _DAC_OPACTRL_OPA0HCMDIS_SHIFT 6 /* Shift value for DAC_OPA0HCMDIS */ +#define _DAC_OPACTRL_OPA0HCMDIS_MASK 0x40UL /* Bit mask for DAC_OPA0HCMDIS */ +#define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0HCMDIS_DEFAULT (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1HCMDIS (0x1UL << 7) /* High Common Mode Disable. */ +#define _DAC_OPACTRL_OPA1HCMDIS_SHIFT 7 /* Shift value for DAC_OPA1HCMDIS */ +#define _DAC_OPACTRL_OPA1HCMDIS_MASK 0x80UL /* Bit mask for DAC_OPA1HCMDIS */ +#define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1HCMDIS_DEFAULT (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2HCMDIS (0x1UL << 8) /* High Common Mode Disable. */ +#define _DAC_OPACTRL_OPA2HCMDIS_SHIFT 8 /* Shift value for DAC_OPA2HCMDIS */ +#define _DAC_OPACTRL_OPA2HCMDIS_MASK 0x100UL /* Bit mask for DAC_OPA2HCMDIS */ +#define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2HCMDIS_DEFAULT (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA0LPFDIS_SHIFT 12 /* Shift value for DAC_OPA0LPFDIS */ +#define _DAC_OPACTRL_OPA0LPFDIS_MASK 0x3000UL /* Bit mask for DAC_OPA0LPFDIS */ +#define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0x00000001UL /* Mode PLPFDIS for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0x00000002UL /* Mode NLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0LPFDIS_DEFAULT (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /* Shifted mode PLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /* Shifted mode NLPFDIS for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA1LPFDIS_SHIFT 14 /* Shift value for DAC_OPA1LPFDIS */ +#define _DAC_OPACTRL_OPA1LPFDIS_MASK 0xC000UL /* Bit mask for DAC_OPA1LPFDIS */ +#define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0x00000001UL /* Mode PLPFDIS for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0x00000002UL /* Mode NLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1LPFDIS_DEFAULT (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /* Shifted mode PLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /* Shifted mode NLPFDIS for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA2LPFDIS_SHIFT 16 /* Shift value for DAC_OPA2LPFDIS */ +#define _DAC_OPACTRL_OPA2LPFDIS_MASK 0x30000UL /* Bit mask for DAC_OPA2LPFDIS */ +#define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0x00000001UL /* Mode PLPFDIS for DAC_OPACTRL */ +#define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0x00000002UL /* Mode NLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2LPFDIS_DEFAULT (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /* Shifted mode PLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /* Shifted mode NLPFDIS for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0SHORT (0x1UL << 22) /* Short the non-inverting and inverting input. */ +#define _DAC_OPACTRL_OPA0SHORT_SHIFT 22 /* Shift value for DAC_OPA0SHORT */ +#define _DAC_OPACTRL_OPA0SHORT_MASK 0x400000UL /* Bit mask for DAC_OPA0SHORT */ +#define _DAC_OPACTRL_OPA0SHORT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA0SHORT_DEFAULT (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1SHORT (0x1UL << 23) /* Short the non-inverting and inverting input. */ +#define _DAC_OPACTRL_OPA1SHORT_SHIFT 23 /* Shift value for DAC_OPA1SHORT */ +#define _DAC_OPACTRL_OPA1SHORT_MASK 0x800000UL /* Bit mask for DAC_OPA1SHORT */ +#define _DAC_OPACTRL_OPA1SHORT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA1SHORT_DEFAULT (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23) /* Shifted mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2SHORT (0x1UL << 24) /* Short the non-inverting and inverting input. */ +#define _DAC_OPACTRL_OPA2SHORT_SHIFT 24 /* Shift value for DAC_OPA2SHORT */ +#define _DAC_OPACTRL_OPA2SHORT_MASK 0x1000000UL /* Bit mask for DAC_OPA2SHORT */ +#define _DAC_OPACTRL_OPA2SHORT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2SHORT_DEFAULT (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24) /* Shifted mode DEFAULT for DAC_OPACTRL */ + +/* Bit fields for DAC OPAOFFSET */ + +#define _DAC_OPAOFFSET_RESETVALUE 0x00000020UL /* Default value for DAC_OPAOFFSET */ +#define _DAC_OPAOFFSET_MASK 0x0000003FUL /* Mask for DAC_OPAOFFSET */ + +#define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT 0 /* Shift value for DAC_OPA2OFFSET */ +#define _DAC_OPAOFFSET_OPA2OFFSET_MASK 0x3FUL /* Bit mask for DAC_OPA2OFFSET */ +#define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT 0x00000020UL /* Mode DEFAULT for DAC_OPAOFFSET */ +#define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_OPAOFFSET */ + +/* Bit fields for DAC OPA0MUX */ + +#define _DAC_OPA0MUX_RESETVALUE 0x00400000UL /* Default value for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_MASK 0x74C7F737UL /* Mask for DAC_OPA0MUX */ + +#define _DAC_OPA0MUX_POSSEL_SHIFT 0 /* Shift value for DAC_POSSEL */ +#define _DAC_OPA0MUX_POSSEL_MASK 0x7UL /* Bit mask for DAC_POSSEL */ +#define _DAC_OPA0MUX_POSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_POSSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_POSSEL_DAC 0x00000001UL /* Mode DAC for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_POSSEL_POSPAD 0x00000002UL /* Mode POSPAD for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_POSSEL_OPA0INP 0x00000003UL /* Mode OPA0INP for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_POSSEL_OPATAP 0x00000004UL /* Mode OPATAP for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_DEFAULT (_DAC_OPA0MUX_POSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_DISABLE (_DAC_OPA0MUX_POSSEL_DISABLE << 0) /* Shifted mode DISABLE for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_DAC (_DAC_OPA0MUX_POSSEL_DAC << 0) /* Shifted mode DAC for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_POSPAD (_DAC_OPA0MUX_POSSEL_POSPAD << 0) /* Shifted mode POSPAD for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_OPA0INP (_DAC_OPA0MUX_POSSEL_OPA0INP << 0) /* Shifted mode OPA0INP for DAC_OPA0MUX */ +#define DAC_OPA0MUX_POSSEL_OPATAP (_DAC_OPA0MUX_POSSEL_OPATAP << 0) /* Shifted mode OPATAP for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_NEGSEL_SHIFT 4 /* Shift value for DAC_NEGSEL */ +#define _DAC_OPA0MUX_NEGSEL_MASK 0x30UL /* Bit mask for DAC_NEGSEL */ +#define _DAC_OPA0MUX_NEGSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_NEGSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_NEGSEL_UG 0x00000001UL /* Mode UG for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_NEGSEL_OPATAP 0x00000002UL /* Mode OPATAP for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_NEGSEL_NEGPAD 0x00000003UL /* Mode NEGPAD for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEGSEL_DEFAULT (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEGSEL_DISABLE (_DAC_OPA0MUX_NEGSEL_DISABLE << 4) /* Shifted mode DISABLE for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEGSEL_UG (_DAC_OPA0MUX_NEGSEL_UG << 4) /* Shifted mode UG for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEGSEL_OPATAP (_DAC_OPA0MUX_NEGSEL_OPATAP << 4) /* Shifted mode OPATAP for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEGSEL_NEGPAD (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4) /* Shifted mode NEGPAD for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_SHIFT 8 /* Shift value for DAC_RESINMUX */ +#define _DAC_OPA0MUX_RESINMUX_MASK 0x700UL /* Bit mask for DAC_RESINMUX */ +#define _DAC_OPA0MUX_RESINMUX_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_OPA0INP 0x00000001UL /* Mode OPA0INP for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_NEGPAD 0x00000002UL /* Mode NEGPAD for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_POSPAD 0x00000003UL /* Mode POSPAD for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESINMUX_VSS 0x00000004UL /* Mode VSS for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_DEFAULT (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_DISABLE (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /* Shifted mode DISABLE for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_OPA0INP (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /* Shifted mode OPA0INP for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_NEGPAD (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8) /* Shifted mode NEGPAD for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_POSPAD (_DAC_OPA0MUX_RESINMUX_POSPAD << 8) /* Shifted mode POSPAD for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESINMUX_VSS (_DAC_OPA0MUX_RESINMUX_VSS << 8) /* Shifted mode VSS for DAC_OPA0MUX */ +#define DAC_OPA0MUX_PPEN (0x1UL << 12) /* OPA0 Positive Pad Input Enable */ +#define _DAC_OPA0MUX_PPEN_SHIFT 12 /* Shift value for DAC_PPEN */ +#define _DAC_OPA0MUX_PPEN_MASK 0x1000UL /* Bit mask for DAC_PPEN */ +#define _DAC_OPA0MUX_PPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_PPEN_DEFAULT (_DAC_OPA0MUX_PPEN_DEFAULT << 12) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NPEN (0x1UL << 13) /* OPA0 Negative Pad Input Enable */ +#define _DAC_OPA0MUX_NPEN_SHIFT 13 /* Shift value for DAC_NPEN */ +#define _DAC_OPA0MUX_NPEN_MASK 0x2000UL /* Bit mask for DAC_NPEN */ +#define _DAC_OPA0MUX_NPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NPEN_DEFAULT (_DAC_OPA0MUX_NPEN_DEFAULT << 13) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_SHIFT 14 /* Shift value for DAC_OUTPEN */ +#define _DAC_OPA0MUX_OUTPEN_MASK 0x7C000UL /* Bit mask for DAC_OUTPEN */ +#define _DAC_OPA0MUX_OUTPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_OUT0 0x00000001UL /* Mode OUT0 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_OUT1 0x00000002UL /* Mode OUT1 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_OUT2 0x00000004UL /* Mode OUT2 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_OUT3 0x00000008UL /* Mode OUT3 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTPEN_OUT4 0x00000010UL /* Mode OUT4 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_DEFAULT (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_OUT0 (_DAC_OPA0MUX_OUTPEN_OUT0 << 14) /* Shifted mode OUT0 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_OUT1 (_DAC_OPA0MUX_OUTPEN_OUT1 << 14) /* Shifted mode OUT1 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_OUT2 (_DAC_OPA0MUX_OUTPEN_OUT2 << 14) /* Shifted mode OUT2 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_OUT3 (_DAC_OPA0MUX_OUTPEN_OUT3 << 14) /* Shifted mode OUT3 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTPEN_OUT4 (_DAC_OPA0MUX_OUTPEN_OUT4 << 14) /* Shifted mode OUT4 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTMODE_SHIFT 22 /* Shift value for DAC_OUTMODE */ +#define _DAC_OPA0MUX_OUTMODE_MASK 0xC00000UL /* Bit mask for DAC_OUTMODE */ +#define _DAC_OPA0MUX_OUTMODE_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTMODE_DEFAULT 0x00000001UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTMODE_MAIN 0x00000001UL /* Mode MAIN for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTMODE_ALT 0x00000002UL /* Mode ALT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_OUTMODE_ALL 0x00000003UL /* Mode ALL for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTMODE_DISABLE (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /* Shifted mode DISABLE for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTMODE_DEFAULT (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTMODE_MAIN (_DAC_OPA0MUX_OUTMODE_MAIN << 22) /* Shifted mode MAIN for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTMODE_ALT (_DAC_OPA0MUX_OUTMODE_ALT << 22) /* Shifted mode ALT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_OUTMODE_ALL (_DAC_OPA0MUX_OUTMODE_ALL << 22) /* Shifted mode ALL for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEXTOUT (0x1UL << 26) /* OPA0 Next Enable */ +#define _DAC_OPA0MUX_NEXTOUT_SHIFT 26 /* Shift value for DAC_NEXTOUT */ +#define _DAC_OPA0MUX_NEXTOUT_MASK 0x4000000UL /* Bit mask for DAC_NEXTOUT */ +#define _DAC_OPA0MUX_NEXTOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_NEXTOUT_DEFAULT (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_SHIFT 28 /* Shift value for DAC_RESSEL */ +#define _DAC_OPA0MUX_RESSEL_MASK 0x70000000UL /* Bit mask for DAC_RESSEL */ +#define _DAC_OPA0MUX_RESSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES0 0x00000000UL /* Mode RES0 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES1 0x00000001UL /* Mode RES1 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES2 0x00000002UL /* Mode RES2 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES3 0x00000003UL /* Mode RES3 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES4 0x00000004UL /* Mode RES4 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES5 0x00000005UL /* Mode RES5 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES6 0x00000006UL /* Mode RES6 for DAC_OPA0MUX */ +#define _DAC_OPA0MUX_RESSEL_RES7 0x00000007UL /* Mode RES7 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_DEFAULT (_DAC_OPA0MUX_RESSEL_DEFAULT << 28) /* Shifted mode DEFAULT for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES0 (_DAC_OPA0MUX_RESSEL_RES0 << 28) /* Shifted mode RES0 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES1 (_DAC_OPA0MUX_RESSEL_RES1 << 28) /* Shifted mode RES1 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES2 (_DAC_OPA0MUX_RESSEL_RES2 << 28) /* Shifted mode RES2 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES3 (_DAC_OPA0MUX_RESSEL_RES3 << 28) /* Shifted mode RES3 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES4 (_DAC_OPA0MUX_RESSEL_RES4 << 28) /* Shifted mode RES4 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES5 (_DAC_OPA0MUX_RESSEL_RES5 << 28) /* Shifted mode RES5 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES6 (_DAC_OPA0MUX_RESSEL_RES6 << 28) /* Shifted mode RES6 for DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_RES7 (_DAC_OPA0MUX_RESSEL_RES7 << 28) /* Shifted mode RES7 for DAC_OPA0MUX */ + +/* Bit fields for DAC OPA1MUX */ + +#define _DAC_OPA1MUX_RESETVALUE 0x00000000UL /* Default value for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_MASK 0x74C7F737UL /* Mask for DAC_OPA1MUX */ + +#define _DAC_OPA1MUX_POSSEL_SHIFT 0 /* Shift value for DAC_POSSEL */ +#define _DAC_OPA1MUX_POSSEL_MASK 0x7UL /* Bit mask for DAC_POSSEL */ +#define _DAC_OPA1MUX_POSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_POSSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_POSSEL_DAC 0x00000001UL /* Mode DAC for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_POSSEL_POSPAD 0x00000002UL /* Mode POSPAD for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_POSSEL_OPA0INP 0x00000003UL /* Mode OPA0INP for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_POSSEL_OPATAP 0x00000004UL /* Mode OPATAP for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_DEFAULT (_DAC_OPA1MUX_POSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_DISABLE (_DAC_OPA1MUX_POSSEL_DISABLE << 0) /* Shifted mode DISABLE for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_DAC (_DAC_OPA1MUX_POSSEL_DAC << 0) /* Shifted mode DAC for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_POSPAD (_DAC_OPA1MUX_POSSEL_POSPAD << 0) /* Shifted mode POSPAD for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_OPA0INP (_DAC_OPA1MUX_POSSEL_OPA0INP << 0) /* Shifted mode OPA0INP for DAC_OPA1MUX */ +#define DAC_OPA1MUX_POSSEL_OPATAP (_DAC_OPA1MUX_POSSEL_OPATAP << 0) /* Shifted mode OPATAP for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_NEGSEL_SHIFT 4 /* Shift value for DAC_NEGSEL */ +#define _DAC_OPA1MUX_NEGSEL_MASK 0x30UL /* Bit mask for DAC_NEGSEL */ +#define _DAC_OPA1MUX_NEGSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_NEGSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_NEGSEL_UG 0x00000001UL /* Mode UG for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_NEGSEL_OPATAP 0x00000002UL /* Mode OPATAP for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_NEGSEL_NEGPAD 0x00000003UL /* Mode NEGPAD for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEGSEL_DEFAULT (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEGSEL_DISABLE (_DAC_OPA1MUX_NEGSEL_DISABLE << 4) /* Shifted mode DISABLE for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEGSEL_UG (_DAC_OPA1MUX_NEGSEL_UG << 4) /* Shifted mode UG for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEGSEL_OPATAP (_DAC_OPA1MUX_NEGSEL_OPATAP << 4) /* Shifted mode OPATAP for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEGSEL_NEGPAD (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4) /* Shifted mode NEGPAD for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_SHIFT 8 /* Shift value for DAC_RESINMUX */ +#define _DAC_OPA1MUX_RESINMUX_MASK 0x700UL /* Bit mask for DAC_RESINMUX */ +#define _DAC_OPA1MUX_RESINMUX_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_OPA0INP 0x00000001UL /* Mode OPA0INP for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_NEGPAD 0x00000002UL /* Mode NEGPAD for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_POSPAD 0x00000003UL /* Mode POSPAD for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESINMUX_VSS 0x00000004UL /* Mode VSS for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_DEFAULT (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_DISABLE (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /* Shifted mode DISABLE for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_OPA0INP (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /* Shifted mode OPA0INP for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_NEGPAD (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8) /* Shifted mode NEGPAD for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_POSPAD (_DAC_OPA1MUX_RESINMUX_POSPAD << 8) /* Shifted mode POSPAD for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESINMUX_VSS (_DAC_OPA1MUX_RESINMUX_VSS << 8) /* Shifted mode VSS for DAC_OPA1MUX */ +#define DAC_OPA1MUX_PPEN (0x1UL << 12) /* OPA1 Positive Pad Input Enable */ +#define _DAC_OPA1MUX_PPEN_SHIFT 12 /* Shift value for DAC_PPEN */ +#define _DAC_OPA1MUX_PPEN_MASK 0x1000UL /* Bit mask for DAC_PPEN */ +#define _DAC_OPA1MUX_PPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_PPEN_DEFAULT (_DAC_OPA1MUX_PPEN_DEFAULT << 12) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NPEN (0x1UL << 13) /* OPA1 Negative Pad Input Enable */ +#define _DAC_OPA1MUX_NPEN_SHIFT 13 /* Shift value for DAC_NPEN */ +#define _DAC_OPA1MUX_NPEN_MASK 0x2000UL /* Bit mask for DAC_NPEN */ +#define _DAC_OPA1MUX_NPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NPEN_DEFAULT (_DAC_OPA1MUX_NPEN_DEFAULT << 13) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_SHIFT 14 /* Shift value for DAC_OUTPEN */ +#define _DAC_OPA1MUX_OUTPEN_MASK 0x7C000UL /* Bit mask for DAC_OUTPEN */ +#define _DAC_OPA1MUX_OUTPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_OUT0 0x00000001UL /* Mode OUT0 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_OUT1 0x00000002UL /* Mode OUT1 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_OUT2 0x00000004UL /* Mode OUT2 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_OUT3 0x00000008UL /* Mode OUT3 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTPEN_OUT4 0x00000010UL /* Mode OUT4 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_DEFAULT (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_OUT0 (_DAC_OPA1MUX_OUTPEN_OUT0 << 14) /* Shifted mode OUT0 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_OUT1 (_DAC_OPA1MUX_OUTPEN_OUT1 << 14) /* Shifted mode OUT1 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_OUT2 (_DAC_OPA1MUX_OUTPEN_OUT2 << 14) /* Shifted mode OUT2 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_OUT3 (_DAC_OPA1MUX_OUTPEN_OUT3 << 14) /* Shifted mode OUT3 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTPEN_OUT4 (_DAC_OPA1MUX_OUTPEN_OUT4 << 14) /* Shifted mode OUT4 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTMODE_SHIFT 22 /* Shift value for DAC_OUTMODE */ +#define _DAC_OPA1MUX_OUTMODE_MASK 0xC00000UL /* Bit mask for DAC_OUTMODE */ +#define _DAC_OPA1MUX_OUTMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTMODE_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTMODE_MAIN 0x00000001UL /* Mode MAIN for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTMODE_ALT 0x00000002UL /* Mode ALT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_OUTMODE_ALL 0x00000003UL /* Mode ALL for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTMODE_DEFAULT (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTMODE_DISABLE (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /* Shifted mode DISABLE for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTMODE_MAIN (_DAC_OPA1MUX_OUTMODE_MAIN << 22) /* Shifted mode MAIN for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTMODE_ALT (_DAC_OPA1MUX_OUTMODE_ALT << 22) /* Shifted mode ALT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_OUTMODE_ALL (_DAC_OPA1MUX_OUTMODE_ALL << 22) /* Shifted mode ALL for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEXTOUT (0x1UL << 26) /* OPA1 Next Enable */ +#define _DAC_OPA1MUX_NEXTOUT_SHIFT 26 /* Shift value for DAC_NEXTOUT */ +#define _DAC_OPA1MUX_NEXTOUT_MASK 0x4000000UL /* Bit mask for DAC_NEXTOUT */ +#define _DAC_OPA1MUX_NEXTOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_NEXTOUT_DEFAULT (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_SHIFT 28 /* Shift value for DAC_RESSEL */ +#define _DAC_OPA1MUX_RESSEL_MASK 0x70000000UL /* Bit mask for DAC_RESSEL */ +#define _DAC_OPA1MUX_RESSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES0 0x00000000UL /* Mode RES0 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES1 0x00000001UL /* Mode RES1 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES2 0x00000002UL /* Mode RES2 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES3 0x00000003UL /* Mode RES3 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES4 0x00000004UL /* Mode RES4 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES5 0x00000005UL /* Mode RES5 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES6 0x00000006UL /* Mode RES6 for DAC_OPA1MUX */ +#define _DAC_OPA1MUX_RESSEL_RES7 0x00000007UL /* Mode RES7 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_DEFAULT (_DAC_OPA1MUX_RESSEL_DEFAULT << 28) /* Shifted mode DEFAULT for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES0 (_DAC_OPA1MUX_RESSEL_RES0 << 28) /* Shifted mode RES0 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES1 (_DAC_OPA1MUX_RESSEL_RES1 << 28) /* Shifted mode RES1 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES2 (_DAC_OPA1MUX_RESSEL_RES2 << 28) /* Shifted mode RES2 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES3 (_DAC_OPA1MUX_RESSEL_RES3 << 28) /* Shifted mode RES3 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES4 (_DAC_OPA1MUX_RESSEL_RES4 << 28) /* Shifted mode RES4 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES5 (_DAC_OPA1MUX_RESSEL_RES5 << 28) /* Shifted mode RES5 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES6 (_DAC_OPA1MUX_RESSEL_RES6 << 28) /* Shifted mode RES6 for DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_RES7 (_DAC_OPA1MUX_RESSEL_RES7 << 28) /* Shifted mode RES7 for DAC_OPA1MUX */ + +/* Bit fields for DAC OPA2MUX */ + +#define _DAC_OPA2MUX_RESETVALUE 0x00000000UL /* Default value for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_MASK 0x7440F737UL /* Mask for DAC_OPA2MUX */ + +#define _DAC_OPA2MUX_POSSEL_SHIFT 0 /* Shift value for DAC_POSSEL */ +#define _DAC_OPA2MUX_POSSEL_MASK 0x7UL /* Bit mask for DAC_POSSEL */ +#define _DAC_OPA2MUX_POSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_POSSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_POSSEL_POSPAD 0x00000002UL /* Mode POSPAD for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_POSSEL_OPA1INP 0x00000003UL /* Mode OPA1INP for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_POSSEL_OPATAP 0x00000004UL /* Mode OPATAP for DAC_OPA2MUX */ +#define DAC_OPA2MUX_POSSEL_DEFAULT (_DAC_OPA2MUX_POSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_POSSEL_DISABLE (_DAC_OPA2MUX_POSSEL_DISABLE << 0) /* Shifted mode DISABLE for DAC_OPA2MUX */ +#define DAC_OPA2MUX_POSSEL_POSPAD (_DAC_OPA2MUX_POSSEL_POSPAD << 0) /* Shifted mode POSPAD for DAC_OPA2MUX */ +#define DAC_OPA2MUX_POSSEL_OPA1INP (_DAC_OPA2MUX_POSSEL_OPA1INP << 0) /* Shifted mode OPA1INP for DAC_OPA2MUX */ +#define DAC_OPA2MUX_POSSEL_OPATAP (_DAC_OPA2MUX_POSSEL_OPATAP << 0) /* Shifted mode OPATAP for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_NEGSEL_SHIFT 4 /* Shift value for DAC_NEGSEL */ +#define _DAC_OPA2MUX_NEGSEL_MASK 0x30UL /* Bit mask for DAC_NEGSEL */ +#define _DAC_OPA2MUX_NEGSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_NEGSEL_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_NEGSEL_UG 0x00000001UL /* Mode UG for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_NEGSEL_OPATAP 0x00000002UL /* Mode OPATAP for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_NEGSEL_NEGPAD 0x00000003UL /* Mode NEGPAD for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEGSEL_DEFAULT (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEGSEL_DISABLE (_DAC_OPA2MUX_NEGSEL_DISABLE << 4) /* Shifted mode DISABLE for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEGSEL_UG (_DAC_OPA2MUX_NEGSEL_UG << 4) /* Shifted mode UG for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEGSEL_OPATAP (_DAC_OPA2MUX_NEGSEL_OPATAP << 4) /* Shifted mode OPATAP for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEGSEL_NEGPAD (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4) /* Shifted mode NEGPAD for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_SHIFT 8 /* Shift value for DAC_RESINMUX */ +#define _DAC_OPA2MUX_RESINMUX_MASK 0x700UL /* Bit mask for DAC_RESINMUX */ +#define _DAC_OPA2MUX_RESINMUX_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_DISABLE 0x00000000UL /* Mode DISABLE for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_OPA1INP 0x00000001UL /* Mode OPA1INP for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_NEGPAD 0x00000002UL /* Mode NEGPAD for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_POSPAD 0x00000003UL /* Mode POSPAD for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESINMUX_VSS 0x00000004UL /* Mode VSS for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_DEFAULT (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_DISABLE (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /* Shifted mode DISABLE for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_OPA1INP (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /* Shifted mode OPA1INP for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_NEGPAD (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8) /* Shifted mode NEGPAD for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_POSPAD (_DAC_OPA2MUX_RESINMUX_POSPAD << 8) /* Shifted mode POSPAD for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESINMUX_VSS (_DAC_OPA2MUX_RESINMUX_VSS << 8) /* Shifted mode VSS for DAC_OPA2MUX */ +#define DAC_OPA2MUX_PPEN (0x1UL << 12) /* OPA2 Positive Pad Input Enable */ +#define _DAC_OPA2MUX_PPEN_SHIFT 12 /* Shift value for DAC_PPEN */ +#define _DAC_OPA2MUX_PPEN_MASK 0x1000UL /* Bit mask for DAC_PPEN */ +#define _DAC_OPA2MUX_PPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_PPEN_DEFAULT (_DAC_OPA2MUX_PPEN_DEFAULT << 12) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NPEN (0x1UL << 13) /* OPA2 Negative Pad Input Enable */ +#define _DAC_OPA2MUX_NPEN_SHIFT 13 /* Shift value for DAC_NPEN */ +#define _DAC_OPA2MUX_NPEN_MASK 0x2000UL /* Bit mask for DAC_NPEN */ +#define _DAC_OPA2MUX_NPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NPEN_DEFAULT (_DAC_OPA2MUX_NPEN_DEFAULT << 13) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_OUTPEN_SHIFT 14 /* Shift value for DAC_OUTPEN */ +#define _DAC_OPA2MUX_OUTPEN_MASK 0xC000UL /* Bit mask for DAC_OUTPEN */ +#define _DAC_OPA2MUX_OUTPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_OUTPEN_OUT0 0x00000001UL /* Mode OUT0 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_OUTPEN_OUT1 0x00000002UL /* Mode OUT1 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_OUTPEN_DEFAULT (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_OUTPEN_OUT0 (_DAC_OPA2MUX_OUTPEN_OUT0 << 14) /* Shifted mode OUT0 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_OUTPEN_OUT1 (_DAC_OPA2MUX_OUTPEN_OUT1 << 14) /* Shifted mode OUT1 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_OUTMODE (0x1UL << 22) /* Output Select */ +#define _DAC_OPA2MUX_OUTMODE_SHIFT 22 /* Shift value for DAC_OUTMODE */ +#define _DAC_OPA2MUX_OUTMODE_MASK 0x400000UL /* Bit mask for DAC_OUTMODE */ +#define _DAC_OPA2MUX_OUTMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_OUTMODE_DEFAULT (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEXTOUT (0x1UL << 26) /* OPA2 Next Enable */ +#define _DAC_OPA2MUX_NEXTOUT_SHIFT 26 /* Shift value for DAC_NEXTOUT */ +#define _DAC_OPA2MUX_NEXTOUT_MASK 0x4000000UL /* Bit mask for DAC_NEXTOUT */ +#define _DAC_OPA2MUX_NEXTOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_NEXTOUT_DEFAULT (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_SHIFT 28 /* Shift value for DAC_RESSEL */ +#define _DAC_OPA2MUX_RESSEL_MASK 0x70000000UL /* Bit mask for DAC_RESSEL */ +#define _DAC_OPA2MUX_RESSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES0 0x00000000UL /* Mode RES0 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES1 0x00000001UL /* Mode RES1 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES2 0x00000002UL /* Mode RES2 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES3 0x00000003UL /* Mode RES3 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES4 0x00000004UL /* Mode RES4 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES5 0x00000005UL /* Mode RES5 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES6 0x00000006UL /* Mode RES6 for DAC_OPA2MUX */ +#define _DAC_OPA2MUX_RESSEL_RES7 0x00000007UL /* Mode RES7 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_DEFAULT (_DAC_OPA2MUX_RESSEL_DEFAULT << 28) /* Shifted mode DEFAULT for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES0 (_DAC_OPA2MUX_RESSEL_RES0 << 28) /* Shifted mode RES0 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES1 (_DAC_OPA2MUX_RESSEL_RES1 << 28) /* Shifted mode RES1 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES2 (_DAC_OPA2MUX_RESSEL_RES2 << 28) /* Shifted mode RES2 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES3 (_DAC_OPA2MUX_RESSEL_RES3 << 28) /* Shifted mode RES3 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES4 (_DAC_OPA2MUX_RESSEL_RES4 << 28) /* Shifted mode RES4 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES5 (_DAC_OPA2MUX_RESSEL_RES5 << 28) /* Shifted mode RES5 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES6 (_DAC_OPA2MUX_RESSEL_RES6 << 28) /* Shifted mode RES6 for DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /* Shifted mode RES7 for DAC_OPA2MUX */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DAC_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_devinfo.h b/nuttx/arch/arm/src/efm32/chip/efm32_devinfo.h new file mode 100644 index 000000000..f55349c15 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_devinfo.h @@ -0,0 +1,213 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_devinfo.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ + +#define DEVINFO ((const struct efm32_devinfo_s *)EFM32_DEVINFO_BASE) + +/* Bit fields for struct efm32_devinfo_s */ + +#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /* Integrity CRC checksum mask */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /* Integrity CRC checksum shift */ +#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /* Calibration temperature, DegC, mask */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /* Calibration temperature shift */ + +#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /* Gain for 1V25 reference, mask */ +#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /* Gain for 1V25 reference, shift */ +#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /* Offset for 1V25 reference, mask */ +#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /* Offset for 1V25 reference, shift */ +#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /* Gain for 2V5 reference, mask */ +#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /* Gain for 2V5 reference, shift */ +#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /* Offset for 2V5 reference, mask */ +#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /* Offset for 2V5 reference, shift */ + +#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /* Gain for VDD reference, mask */ +#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /* Gain for VDD reference, shift */ +#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /* Offset for VDD reference, mask */ +#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /* Offset for VDD reference, shift */ +#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /* Gain 5VDIFF for 5VDIFF reference, mask */ +#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /* Gain for 5VDIFF reference, mask */ +#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /* Offset for 5VDIFF reference, mask */ +#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /* Offset for 5VDIFF reference, shift */ + +#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /* Offset for 2XVDDVSS reference, mask */ +#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /* Offset for 2XVDDVSS reference, shift */ +#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /* Temperature reading at 1V25 reference, mask */ +#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /* Temperature reading at 1V25 reference, DegC */ + +#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /* Gain for 1V25 reference, mask */ +#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /* Gain for 1V25 reference, shift */ +#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 1V25 reference, mask */ +#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 1V25 reference, shift */ +#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 1V25 reference, mask */ +#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 1V25 reference, shift */ + +#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /* Gain for 2V5 reference, mask */ +#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /* Gain for 2V5 reference, shift */ +#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 2V5 reference, mask */ +#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 2V5 reference, shift */ +#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 2V5 reference, mask */ +#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 2V5 reference, shift */ + +#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /* Gain for VDD reference, mask */ +#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /* Gain for VDD reference, shift */ +#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for VDD reference, mask */ +#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for VDD reference, shift */ +#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for VDD reference, mask */ +#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for VDD reference, shift*/ + +#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for AUXHFRCO, mask */ +#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for AUXHFRCO, shift */ +#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for AUXHFRCO, mask */ +#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /* 7MHz tuning value for AUXHFRCO, shift */ +#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /* 11MHz tuning value for AUXHFRCO, mask */ +#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for AUXHFRCO, shift */ +#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for AUXHFRCO, mask */ +#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for AUXHFRCO, shift */ + +#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for AUXHFRCO, mask */ +#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for AUXHFRCO, shift */ +#define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for AUXHFRCO, shift */ +#define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for AUXHFRCO, mask */ + +#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for HFRCO, mask */ +#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for HFRCO, shift */ +#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for HFRCO, mask */ +#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /* 7MHz tuning value for HFRCO, shift */ +#define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /* 11MHz tuning value for HFRCO, mask */ +#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for HFRCO, shift */ +#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for HFRCO, mask */ +#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for HFRCO, shift */ + +#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for HFRCO, mask */ +#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for HFRCO, shift */ +#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for HFRCO, shift */ +#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for HFRCO, mask */ + +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /* Flash page size (refer to ref.man for encoding) mask */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /* Flash page size shift */ + +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /* Lower part of 64-bit device unique number */ +#define _DEVINFO_UNIQUEL_SHIFT 0 /* Unique Low 32-bit shift */ + +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /* High part of 64-bit device unique number */ +#define _DEVINFO_UNIQUEH_SHIFT 0 /* Unique High 32-bit shift */ + +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /* Bit position for flash size */ +#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */ + +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /* Production revision */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /* Bit position for production revision */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /* Device Family, 0x47 for Gecko */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /* Bit position for device family */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /* Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /* Giant Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /* Tiny Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /* Leopard Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /* Wonder Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /* Zero Gecko Device Family */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /* Device number */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /* Bit position for device number */ + +/******************************************************************************************************************************* + * Public Type Definitions + *******************************************************************************************************************************/ + +struct efm32_devinfo_s +{ + const uint32_t cal; /* Calibration temperature and checksum */ + const uint32_t adc0cal0; /* ADC0 Calibration register 0 */ + const uint32_t adc0cal1; /* ADC0 Calibration register 1 */ + const uint32_t adc0cal2; /* ADC0 Calibration register 2 */ + uint32_t reserved0[2]; /* Reserved */ + const uint32_t dac0cal0; /* DAC calibration register 0 */ + const uint32_t dac0cal1; /* DAC calibration register 1 */ + const uint32_t dac0cal2; /* DAC calibration register 2 */ + const uint32_t auxhfrcocal0; /* AUXHFRCO calibration register 0 */ + const uint32_t auxhfrcocal1; /* AUXHFRCO calibration register 1 */ + const uint32_t hfrcocal0; /* HFRCO calibration register 0 */ + const uint32_t hfrcocal1; /* HFRCO calibration register 1 */ + const uint32_t meminfo; /* Memory information */ + uint32_t reserved2[2]; /* Reserved */ + const uint32_t uniquel; /* Low 32 bits of device unique number */ + const uint32_t uniqueh; /* High 32 bits of device unique number */ + const uint32_t msize; /* Flash and SRAM Memory size in KiloBytes */ + const uint32_t part; /* Part description */ +}; + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_dma.h b/nuttx/arch/arm/src/efm32/chip/efm32_dma.h index f8292686f..63cf91095 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_dma.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_dma.h @@ -65,8 +65,13 @@ * Included Files *******************************************************************************************************************************/ +#include <nuttx/config.h> #include "chip/efm32_memorymap.h" +#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G) +# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture +#endif + /******************************************************************************************************************************* * Pre-processor Definitions *******************************************************************************************************************************/ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_emu.h b/nuttx/arch/arm/src/efm32/chip/efm32_emu.h new file mode 100644 index 000000000..9cd1c67bd --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_emu.h @@ -0,0 +1,442 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_emu.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* EMU Register Offsets ********************************************************************************************************/ + +#define EFM32_EMU_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_EMU_MEMCTRL_OFFSET 0x0004 /* Memory Control Register */ +#define EFM32_EMU_LOCK_OFFSET 0x0008 /* Configuration Lock Register */ +#define EFM32_EMU_AUXCTRL_OFFSET 0x0024 /* Auxiliary Control Register */ +#define EFM32_EMU_EM4CONF_OFFSET 0x002c /* Energy mode 4 configuration register */ +#define EFM32_EMU_BUCTRL_OFFSET 0x0030 /* Backup Power configuration register */ +#define EFM32_EMU_PWRCONF_OFFSET 0x0034 /* Power connection configuration register */ +#define EFM32_EMU_BUINACT_OFFSET 0x0038 /* Backup mode inactive configuration register */ +#define EFM32_EMU_BUACT_OFFSET 0x003c /* Backup mode active configuration register */ +#define EFM32_EMU_STATUS_OFFSET 0x0040 /* status register */ +#define EFM32_EMU_ROUTE_OFFSET 0x0044 /* I/O Routing Register */ +#define EFM32_EMU_IF_OFFSET 0x0048 /* Interrupt Flag Register */ +#define EFM32_EMU_IFS_OFFSET 0x004c /* Interrupt Flag Set Register */ +#define EFM32_EMU_IFC_OFFSET 0x0050 /* Interrupt Flag Clear Register */ +#define EFM32_EMU_IEN_OFFSET 0x0054 /* Interrupt Enable Register */ +#define EFM32_EMU_BUBODBUVINCAL_OFFSET 0x0058 /* BU_VIN Backup BOD calibration */ +#define EFM32_EMU_BUBODUNREGCAL_OFFSET 0x005c /* Unregulated power Backup BOD calibration */ + +/* EMU Register Addresses ******************************************************************************************************/ + +#define EFM32_EMU_CTRL (EFM32_EMU_BASE+EFM32_EMU_CTRL_OFFSET) +#define EFM32_EMU_MEMCTRL (EFM32_EMU_BASE+EFM32_EMU_MEMCTRL_OFFSET) +#define EFM32_EMU_LOCK (EFM32_EMU_BASE+EFM32_EMU_LOCK_OFFSET) +#define EFM32_EMU_AUXCTRL (EFM32_EMU_BASE+EFM32_EMU_AUXCTRL_OFFSET) +#define EFM32_EMU_EM4CONF (EFM32_EMU_BASE+EFM32_EMU_EM4CONF_OFFSET) +#define EFM32_EMU_BUCTRL (EFM32_EMU_BASE+EFM32_EMU_BUCTRL_OFFSET) +#define EFM32_EMU_PWRCONF (EFM32_EMU_BASE+EFM32_EMU_PWRCONF_OFFSET) +#define EFM32_EMU_BUINACT (EFM32_EMU_BASE+EFM32_EMU_BUINACT_OFFSET) +#define EFM32_EMU_BUACT (EFM32_EMU_BASE+EFM32_EMU_BUACT_OFFSET) +#define EFM32_EMU_STATUS (EFM32_EMU_BASE+EFM32_EMU_STATUS_OFFSET) +#define EFM32_EMU_ROUTE (EFM32_EMU_BASE+EFM32_EMU_ROUTE_OFFSET) +#define EFM32_EMU_IF (EFM32_EMU_BASE+EFM32_EMU_IF_OFFSET) +#define EFM32_EMU_IFS (EFM32_EMU_BASE+EFM32_EMU_IFS_OFFSET) +#define EFM32_EMU_IFC (EFM32_EMU_BASE+EFM32_EMU_IFC_OFFSET) +#define EFM32_EMU_IEN (EFM32_EMU_BASE+EFM32_EMU_IEN_OFFSET) +#define EFM32_EMU_BUBODBUVINCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODBUVINCAL_OFFSET) +#define EFM32_EMU_BUBODUNREGCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODUNREGCAL_OFFSET) + +/* EMU Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for EMU CTRL */ + +#define _EMU_CTRL_RESETVALUE 0x00000000UL /* Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0000000FUL /* Mask for EMU_CTRL */ + +#define EMU_CTRL_EMVREG (0x1UL << 0) /* Energy Mode Voltage Regulator Control */ +#define _EMU_CTRL_EMVREG_SHIFT 0 /* Shift value for EMU_EMVREG */ +#define _EMU_CTRL_EMVREG_MASK 0x1UL /* Bit mask for EMU_EMVREG */ +#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /* Mode REDUCED for EMU_CTRL */ +#define _EMU_CTRL_EMVREG_FULL 0x00000001UL /* Mode FULL for EMU_CTRL */ +#define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /* Shifted mode REDUCED for EMU_CTRL */ +#define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /* Shifted mode FULL for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /* Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /* Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /* Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4CTRL_SHIFT 2 /* Shift value for EMU_EM4CTRL */ +#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /* Bit mask for EMU_EM4CTRL */ +#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU MEMCTRL */ + +#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_MASK 0x00000007UL /* Mask for EMU_MEMCTRL */ + +#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /* Shift value for EMU_POWERDOWN */ +#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /* Bit mask for EMU_POWERDOWN */ +#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /* Mode BLK3 for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /* Mode BLK23 for EMU_MEMCTRL */ +#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /* Mode BLK123 for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) /* Shifted mode BLK3 for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) /* Shifted mode BLK23 for EMU_MEMCTRL */ +#define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) /* Shifted mode BLK123 for EMU_MEMCTRL */ + +/* Bit fields for EMU LOCK */ + +#define _EMU_LOCK_RESETVALUE 0x00000000UL /* Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /* Mask for EMU_LOCK */ + +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /* Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /* Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /* Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /* Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /* Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /* Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /* Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /* Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU AUXCTRL */ + +#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_AUXCTRL */ +#define _EMU_AUXCTRL_MASK 0x00000101UL /* Mask for EMU_AUXCTRL */ + +#define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /* Hard Reset Cause Clear */ +#define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /* Shift value for EMU_HRCCLR */ +#define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /* Bit mask for EMU_HRCCLR */ +#define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_AUXCTRL */ +#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_AUXCTRL */ +#define EMU_AUXCTRL_REDLFXOBOOST (0x1UL << 8) /* Reduce LFXO Start-up Boost Current */ +#define _EMU_AUXCTRL_REDLFXOBOOST_SHIFT 8 /* Shift value for EMU_REDLFXOBOOST */ +#define _EMU_AUXCTRL_REDLFXOBOOST_MASK 0x100UL /* Bit mask for EMU_REDLFXOBOOST */ +#define _EMU_AUXCTRL_REDLFXOBOOST_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_AUXCTRL */ +#define EMU_AUXCTRL_REDLFXOBOOST_DEFAULT (_EMU_AUXCTRL_REDLFXOBOOST_DEFAULT << 8) /* Shifted mode DEFAULT for EMU_AUXCTRL */ + +/* Bit fields for EMU EM4CONF */ + +#define _EMU_EM4CONF_RESETVALUE 0x00000000UL /* Default value for EMU_EM4CONF */ +#define _EMU_EM4CONF_MASK 0x0001001FUL /* Mask for EMU_EM4CONF */ + +#define EMU_EM4CONF_VREGEN (0x1UL << 0) /* EM4 voltage regulator enable */ +#define _EMU_EM4CONF_VREGEN_SHIFT 0 /* Shift value for EMU_VREGEN */ +#define _EMU_EM4CONF_VREGEN_MASK 0x1UL /* Bit mask for EMU_VREGEN */ +#define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_BURTCWU (0x1UL << 1) /* Backup RTC EM4 wakeup enable */ +#define _EMU_EM4CONF_BURTCWU_SHIFT 1 /* Shift value for EMU_BURTCWU */ +#define _EMU_EM4CONF_BURTCWU_MASK 0x2UL /* Bit mask for EMU_BURTCWU */ +#define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_EM4CONF */ +#define _EMU_EM4CONF_OSC_SHIFT 2 /* Shift value for EMU_OSC */ +#define _EMU_EM4CONF_OSC_MASK 0xCUL /* Bit mask for EMU_OSC */ +#define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */ +#define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL /* Mode ULFRCO for EMU_EM4CONF */ +#define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL /* Mode LFRCO for EMU_EM4CONF */ +#define _EMU_EM4CONF_OSC_LFXO 0x00000002UL /* Mode LFXO for EMU_EM4CONF */ +#define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2) /* Shifted mode ULFRCO for EMU_EM4CONF */ +#define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2) /* Shifted mode LFRCO for EMU_EM4CONF */ +#define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2) /* Shifted mode LFXO for EMU_EM4CONF */ +#define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4) /* Disable reset from Backup BOD in EM4 */ +#define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4 /* Shift value for EMU_BUBODRSTDIS */ +#define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL /* Bit mask for EMU_BUBODRSTDIS */ +#define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /* Shifted mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_LOCKCONF (0x1UL << 16) /* EM4 configuration lock enable */ +#define _EMU_EM4CONF_LOCKCONF_SHIFT 16 /* Shift value for EMU_LOCKCONF */ +#define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL /* Bit mask for EMU_LOCKCONF */ +#define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */ +#define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /* Shifted mode DEFAULT for EMU_EM4CONF */ + +/* Bit fields for EMU BUCTRL */ + +#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_BUCTRL */ +#define _EMU_BUCTRL_MASK 0x00000067UL /* Mask for EMU_BUCTRL */ + +#define EMU_BUCTRL_EN (0x1UL << 0) /* Enable backup mode */ +#define _EMU_BUCTRL_EN_SHIFT 0 /* Shift value for EMU_EN */ +#define _EMU_BUCTRL_EN_MASK 0x1UL /* Bit mask for EMU_EN */ +#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN (0x1UL << 1) /* Enable backup mode status export */ +#define _EMU_BUCTRL_STATEN_SHIFT 1 /* Shift value for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_MASK 0x2UL /* Bit mask for EMU_STATEN */ +#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BODCAL (0x1UL << 2) /* Enable BOD calibration mode */ +#define _EMU_BUCTRL_BODCAL_SHIFT 2 /* Shift value for EMU_BODCAL */ +#define _EMU_BUCTRL_BODCAL_MASK 0x4UL /* Bit mask for EMU_BODCAL */ +#define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PROBE_SHIFT 5 /* Shift value for EMU_PROBE */ +#define _EMU_BUCTRL_PROBE_MASK 0x60UL /* Bit mask for EMU_PROBE */ +#define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */ +#define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /* Mode DISABLE for EMU_BUCTRL */ +#define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /* Mode VDDDREG for EMU_BUCTRL */ +#define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /* Mode BUIN for EMU_BUCTRL */ +#define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /* Mode BUOUT for EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /* Shifted mode DISABLE for EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /* Shifted mode VDDDREG for EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /* Shifted mode BUIN for EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /* Shifted mode BUOUT for EMU_BUCTRL */ + +/* Bit fields for EMU PWRCONF */ + +#define _EMU_PWRCONF_RESETVALUE 0x00000000UL /* Default value for EMU_PWRCONF */ +#define _EMU_PWRCONF_MASK 0x0000001FUL /* Mask for EMU_PWRCONF */ + +#define EMU_PWRCONF_VOUTWEAK (0x1UL << 0) /* BU_VOUT weak enable */ +#define _EMU_PWRCONF_VOUTWEAK_SHIFT 0 /* Shift value for EMU_VOUTWEAK */ +#define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL /* Bit mask for EMU_VOUTWEAK */ +#define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_VOUTMED (0x1UL << 1) /* BU_VOUT medium enable */ +#define _EMU_PWRCONF_VOUTMED_SHIFT 1 /* Shift value for EMU_VOUTMED */ +#define _EMU_PWRCONF_VOUTMED_MASK 0x2UL /* Bit mask for EMU_VOUTMED */ +#define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2) /* BU_VOUT strong enable */ +#define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2 /* Shift value for EMU_VOUTSTRONG */ +#define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL /* Bit mask for EMU_VOUTSTRONG */ +#define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_PWRCONF */ +#define _EMU_PWRCONF_PWRRES_SHIFT 3 /* Shift value for EMU_PWRRES */ +#define _EMU_PWRCONF_PWRRES_MASK 0x18UL /* Bit mask for EMU_PWRRES */ +#define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */ +#define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL /* Mode RES0 for EMU_PWRCONF */ +#define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL /* Mode RES1 for EMU_PWRCONF */ +#define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL /* Mode RES2 for EMU_PWRCONF */ +#define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL /* Mode RES3 for EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3) /* Shifted mode RES0 for EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3) /* Shifted mode RES1 for EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3) /* Shifted mode RES2 for EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3) /* Shifted mode RES3 for EMU_PWRCONF */ + +/* Bit fields for EMU BUINACT */ + +#define _EMU_BUINACT_RESETVALUE 0x0000000BUL /* Default value for EMU_BUINACT */ +#define _EMU_BUINACT_MASK 0x0000007FUL /* Mask for EMU_BUINACT */ + +#define _EMU_BUINACT_BUENTHRES_SHIFT 0 /* Shift value for EMU_BUENTHRES */ +#define _EMU_BUINACT_BUENTHRES_MASK 0x7UL /* Bit mask for EMU_BUENTHRES */ +#define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUINACT */ +#define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUINACT */ +#define _EMU_BUINACT_BUENRANGE_SHIFT 3 /* Shift value for EMU_BUENRANGE */ +#define _EMU_BUINACT_BUENRANGE_MASK 0x18UL /* Bit mask for EMU_BUENRANGE */ +#define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUINACT */ +#define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUINACT */ +#define _EMU_BUINACT_PWRCON_SHIFT 5 /* Shift value for EMU_PWRCON */ +#define _EMU_BUINACT_PWRCON_MASK 0x60UL /* Bit mask for EMU_PWRCON */ +#define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUINACT */ +#define _EMU_BUINACT_PWRCON_NONE 0x00000000UL /* Mode NONE for EMU_BUINACT */ +#define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL /* Mode BUMAIN for EMU_BUINACT */ +#define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL /* Mode MAINBU for EMU_BUINACT */ +#define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL /* Mode NODIODE for EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5) /* Shifted mode NONE for EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5) /* Shifted mode BUMAIN for EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5) /* Shifted mode MAINBU for EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5) /* Shifted mode NODIODE for EMU_BUINACT */ + +/* Bit fields for EMU BUACT */ + +#define _EMU_BUACT_RESETVALUE 0x0000000BUL /* Default value for EMU_BUACT */ +#define _EMU_BUACT_MASK 0x0000007FUL /* Mask for EMU_BUACT */ + +#define _EMU_BUACT_BUEXTHRES_SHIFT 0 /* Shift value for EMU_BUEXTHRES */ +#define _EMU_BUACT_BUEXTHRES_MASK 0x7UL /* Bit mask for EMU_BUEXTHRES */ +#define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUACT */ +#define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUACT */ +#define _EMU_BUACT_BUEXRANGE_SHIFT 3 /* Shift value for EMU_BUEXRANGE */ +#define _EMU_BUACT_BUEXRANGE_MASK 0x18UL /* Bit mask for EMU_BUEXRANGE */ +#define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUACT */ +#define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUACT */ +#define _EMU_BUACT_PWRCON_SHIFT 5 /* Shift value for EMU_PWRCON */ +#define _EMU_BUACT_PWRCON_MASK 0x60UL /* Bit mask for EMU_PWRCON */ +#define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUACT */ +#define _EMU_BUACT_PWRCON_NONE 0x00000000UL /* Mode NONE for EMU_BUACT */ +#define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL /* Mode BUMAIN for EMU_BUACT */ +#define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL /* Mode MAINBU for EMU_BUACT */ +#define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL /* Mode NODIODE for EMU_BUACT */ +#define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUACT */ +#define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5) /* Shifted mode NONE for EMU_BUACT */ +#define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5) /* Shifted mode BUMAIN for EMU_BUACT */ +#define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5) /* Shifted mode MAINBU for EMU_BUACT */ +#define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5) /* Shifted mode NODIODE for EMU_BUACT */ + +/* Bit fields for EMU STATUS */ + +#define _EMU_STATUS_RESETVALUE 0x00000000UL /* Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x00000001UL /* Mask for EMU_STATUS */ + +#define EMU_STATUS_BURDY (0x1UL << 0) /* Backup mode ready */ +#define _EMU_STATUS_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */ +#define _EMU_STATUS_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */ +#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU ROUTE */ + +#define _EMU_ROUTE_RESETVALUE 0x00000001UL /* Default value for EMU_ROUTE */ +#define _EMU_ROUTE_MASK 0x00000001UL /* Mask for EMU_ROUTE */ + +#define EMU_ROUTE_BUVINPEN (0x1UL << 0) /* BU_VIN Pin Enable */ +#define _EMU_ROUTE_BUVINPEN_SHIFT 0 /* Shift value for EMU_BUVINPEN */ +#define _EMU_ROUTE_BUVINPEN_MASK 0x1UL /* Bit mask for EMU_BUVINPEN */ +#define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_ROUTE */ +#define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_ROUTE */ + +/* Bit fields for EMU IF */ + +#define _EMU_IF_RESETVALUE 0x00000000UL /* Default value for EMU_IF */ +#define _EMU_IF_MASK 0x00000001UL /* Mask for EMU_IF */ + +#define EMU_IF_BURDY (0x1UL << 0) /* Backup functionality ready Interrupt Flag */ +#define _EMU_IF_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */ +#define _EMU_IF_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */ +#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IF */ +#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ + +#define _EMU_IFS_RESETVALUE 0x00000000UL /* Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0x00000001UL /* Mask for EMU_IFS */ + +#define EMU_IFS_BURDY (0x1UL << 0) /* Set Backup functionality ready Interrupt Flag */ +#define _EMU_IFS_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */ +#define _EMU_IFS_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */ +#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ + +#define _EMU_IFC_RESETVALUE 0x00000000UL /* Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0x00000001UL /* Mask for EMU_IFC */ + +#define EMU_IFC_BURDY (0x1UL << 0) /* Clear Backup functionality ready Interrupt Flag */ +#define _EMU_IFC_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */ +#define _EMU_IFC_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */ +#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ + +#define _EMU_IEN_RESETVALUE 0x00000000UL /* Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0x00000001UL /* Mask for EMU_IEN */ + +#define EMU_IEN_BURDY (0x1UL << 0) /* Backup functionality ready Interrupt Enable */ +#define _EMU_IEN_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */ +#define _EMU_IEN_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */ +#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU BUBODBUVINCAL */ + +#define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL /* Default value for EMU_BUBODBUVINCAL */ +#define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL /* Mask for EMU_BUBODBUVINCAL */ + +#define _EMU_BUBODBUVINCAL_THRES_SHIFT 0 /* Shift value for EMU_THRES */ +#define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL /* Bit mask for EMU_THRES */ +#define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUBODBUVINCAL */ +#define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUBODBUVINCAL */ +#define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3 /* Shift value for EMU_RANGE */ +#define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL /* Bit mask for EMU_RANGE */ +#define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUBODBUVINCAL */ +#define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUBODBUVINCAL */ + +/* Bit fields for EMU BUBODUNREGCAL */ + +#define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL /* Default value for EMU_BUBODUNREGCAL */ +#define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL /* Mask for EMU_BUBODUNREGCAL */ + +#define _EMU_BUBODUNREGCAL_THRES_SHIFT 0 /* Shift value for EMU_THRES */ +#define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL /* Bit mask for EMU_THRES */ +#define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUBODUNREGCAL */ +#define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUBODUNREGCAL */ +#define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3 /* Shift value for EMU_RANGE */ +#define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL /* Bit mask for EMU_RANGE */ +#define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUBODUNREGCAL */ +#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUBODUNREGCAL */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_gpio.h b/nuttx/arch/arm/src/efm32/chip/efm32_gpio.h index d96172de8..ba3b7ebc0 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_gpio.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_gpio.h @@ -65,8 +65,13 @@ * Included Files *******************************************************************************************************************************/ +#include <nuttx/config.h> #include "chip/efm32_memorymap.h" +#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G) +# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture +#endif + /******************************************************************************************************************************* * Pre-processor Definitions *******************************************************************************************************************************/ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_i2c.h b/nuttx/arch/arm/src/efm32/chip/efm32_i2c.h new file mode 100644 index 000000000..df8382a2a --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_i2c.h @@ -0,0 +1,800 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_i2c.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* I2C Register Offsets ********************************************************************************************************/ + +#define EFM32_I2C_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_I2C_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_I2C_STATE_OFFSET 0x0008 /* State Register */ +#define EFM32_I2C_STATUS_OFFSET 0x000c /* Status Register */ +#define EFM32_I2C_CLKDIV_OFFSET 0x0010 /* Clock Division Register */ +#define EFM32_I2C_SADDR_OFFSET 0x0014 /* Slave Address Register */ +#define EFM32_I2C_SADDRMASK_OFFSET 0x0018 /* Slave Address Mask Register */ +#define EFM32_I2C_RXDATA_OFFSET 0x001c /* Receive Buffer Data Register */ +#define EFM32_I2C_RXDATAP_OFFSET 0x0020 /* Receive Buffer Data Peek Register */ +#define EFM32_I2C_TXDATA_OFFSET 0x0024 /* Transmit Buffer Data Register */ +#define EFM32_I2C_IF_OFFSET 0x0028 /* Interrupt Flag Register */ +#define EFM32_I2C_IFS_OFFSET 0x002c /* Interrupt Flag Set Register */ +#define EFM32_I2C_IFC_OFFSET 0x0030 /* Interrupt Flag Clear Register */ +#define EFM32_I2C_IEN_OFFSET 0x0034 /* Interrupt Enable Register */ +#define EFM32_I2C_ROUTE_OFFSET 0x0038 /* I/O Routing Register */ + +/* I2C Register Addresses ******************************************************************************************************/ + +#define EFM32_I2C0_CTRL (EFM32_I2C0_BASE+EFM32_I2C_CTRL_OFFSET) +#define EFM32_I2C0_CMD (EFM32_I2C0_BASE+EFM32_I2C_CMD_OFFSET) +#define EFM32_I2C0_STATE (EFM32_I2C0_BASE+EFM32_I2C_STATE_OFFSET) +#define EFM32_I2C0_STATUS (EFM32_I2C0_BASE+EFM32_I2C_STATUS_OFFSET) +#define EFM32_I2C0_CLKDIV (EFM32_I2C0_BASE+EFM32_I2C_CLKDIV_OFFSET) +#define EFM32_I2C0_SADDR (EFM32_I2C0_BASE+EFM32_I2C_SADDR_OFFSET) +#define EFM32_I2C0_SADDRMASK (EFM32_I2C0_BASE+EFM32_I2C_SADDRMASK_OFFSET) +#define EFM32_I2C0_RXDATA (EFM32_I2C0_BASE+EFM32_I2C_RXDATA_OFFSET) +#define EFM32_I2C0_RXDATAP (EFM32_I2C0_BASE+EFM32_I2C_RXDATAP_OFFSET) +#define EFM32_I2C0_TXDATA (EFM32_I2C0_BASE+EFM32_I2C_TXDATA_OFFSET) +#define EFM32_I2C0_IF (EFM32_I2C0_BASE+EFM32_I2C_IF_OFFSET) +#define EFM32_I2C0_IFS (EFM32_I2C0_BASE+EFM32_I2C_IFS_OFFSET) +#define EFM32_I2C0_IFC (EFM32_I2C0_BASE+EFM32_I2C_IFC_OFFSET) +#define EFM32_I2C0_IEN (EFM32_I2C0_BASE+EFM32_I2C_IEN_OFFSET) +#define EFM32_I2C0_ROUTE (EFM32_I2C0_BASE+EFM32_I2C_ROUTE_OFFSET) + +#define EFM32_I2C1_CTRL (EFM32_I2C1_BASE+EFM32_I2C_CTRL_OFFSET) +#define EFM32_I2C1_CMD (EFM32_I2C1_BASE+EFM32_I2C_CMD_OFFSET) +#define EFM32_I2C1_STATE (EFM32_I2C1_BASE+EFM32_I2C_STATE_OFFSET) +#define EFM32_I2C1_STATUS (EFM32_I2C1_BASE+EFM32_I2C_STATUS_OFFSET) +#define EFM32_I2C1_CLKDIV (EFM32_I2C1_BASE+EFM32_I2C_CLKDIV_OFFSET) +#define EFM32_I2C1_SADDR (EFM32_I2C1_BASE+EFM32_I2C_SADDR_OFFSET) +#define EFM32_I2C1_SADDRMASK (EFM32_I2C1_BASE+EFM32_I2C_SADDRMASK_OFFSET) +#define EFM32_I2C1_RXDATA (EFM32_I2C1_BASE+EFM32_I2C_RXDATA_OFFSET) +#define EFM32_I2C1_RXDATAP (EFM32_I2C1_BASE+EFM32_I2C_RXDATAP_OFFSET) +#define EFM32_I2C1_TXDATA (EFM32_I2C1_BASE+EFM32_I2C_TXDATA_OFFSET) +#define EFM32_I2C1_IF (EFM32_I2C1_BASE+EFM32_I2C_IF_OFFSET) +#define EFM32_I2C1_IFS (EFM32_I2C1_BASE+EFM32_I2C_IFS_OFFSET) +#define EFM32_I2C1_IFC (EFM32_I2C1_BASE+EFM32_I2C_IFC_OFFSET) +#define EFM32_I2C1_IEN (EFM32_I2C1_BASE+EFM32_I2C_IEN_OFFSET) +#define EFM32_I2C1_ROUTE (EFM32_I2C1_BASE+EFM32_I2C_ROUTE_OFFSET) + +/* I2C Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for I2C CTRL */ + +#define _I2C_CTRL_RESETVALUE 0x00000000UL /* Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B37FUL /* Mask for I2C_CTRL */ + +#define I2C_CTRL_EN (0x1UL << 0) /* I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /* Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /* Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /* Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /* Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /* Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /* Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /* Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /* Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /* Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /* Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /* Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /* Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /* Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /* Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /* Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /* Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /* Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /* General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /* Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /* Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /* Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /* Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /* Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /* Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /* Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /* Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /* Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /* Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /* Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /* Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /* Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /* Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /* Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /* Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /* Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /* Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /* Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /* Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /* Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /* Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /* Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /* Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /* Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /* Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /* Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /* Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /* Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /* Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PPC 0x00000004UL /* Mode 320PPC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /* Mode 1024PPC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /* Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /* Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /* Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /* Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /* Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /* Shifted mode 320PPC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /* Shifted mode 1024PPC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ + +#define _I2C_CMD_RESETVALUE 0x00000000UL /* Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /* Mask for I2C_CMD */ + +#define I2C_CMD_START (0x1UL << 0) /* Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /* Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /* Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /* Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /* Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /* Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /* Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /* Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /* Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /* Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /* Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /* Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /* Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /* Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /* Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /* Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /* Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /* Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /* Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /* Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /* Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /* Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /* Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /* Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ + +#define _I2C_STATE_RESETVALUE 0x00000001UL /* Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /* Mask for I2C_STATE */ + +#define I2C_STATE_BUSY (0x1UL << 0) /* Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /* Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /* Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /* Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /* Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /* Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /* Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /* Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /* Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /* Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /* Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /* Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /* Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /* Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /* Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /* Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /* Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /* Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /* Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /* Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /* Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /* Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /* Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /* Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /* Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /* Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /* Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /* Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /* Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /* Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /* Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /* Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ + +#define _I2C_STATUS_RESETVALUE 0x00000080UL /* Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000001FFUL /* Mask for I2C_STATUS */ + +#define I2C_STATUS_PSTART (0x1UL << 0) /* Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /* Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /* Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /* Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /* Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /* Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /* Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /* Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /* Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /* Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /* Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /* Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /* Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /* Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /* Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /* Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /* Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /* Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /* TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /* Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /* Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /* TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /* Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /* Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /* RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /* Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /* Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ + +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /* Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /* Mask for I2C_CLKDIV */ + +#define _I2C_CLKDIV_DIV_SHIFT 0 /* Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /* Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ + +#define _I2C_SADDR_RESETVALUE 0x00000000UL /* Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /* Mask for I2C_SADDR */ + +#define _I2C_SADDR_ADDR_SHIFT 1 /* Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /* Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ + +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /* Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /* Mask for I2C_SADDRMASK */ + +#define _I2C_SADDRMASK_MASK_SHIFT 1 /* Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /* Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ + +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /* Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /* Mask for I2C_RXDATA */ + +#define _I2C_RXDATA_RXDATA_SHIFT 0 /* Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /* Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDATAP */ + +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /* Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /* Mask for I2C_RXDATAP */ + +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /* Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /* Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C TXDATA */ + +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /* Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /* Mask for I2C_TXDATA */ + +#define _I2C_TXDATA_TXDATA_SHIFT 0 /* Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /* Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C IF */ + +#define _I2C_IF_RESETVALUE 0x00000010UL /* Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0001FFFFUL /* Mask for I2C_IF */ + +#define I2C_IF_START (0x1UL << 0) /* START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /* Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /* Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /* Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /* Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /* Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /* Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /* Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /* Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /* Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /* Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /* Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /* Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /* Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /* Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /* Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /* Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /* Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /* Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /* Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /* Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /* Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /* Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /* Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /* Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /* Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /* Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /* Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /* Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /* Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /* Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /* Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /* Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /* Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /* Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /* Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /* Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /* Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /* Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /* Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /* Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /* Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /* Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /* Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /* Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /* Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /* Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /* Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /* Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /* Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /* Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /* Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /* Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ + +#define _I2C_IFS_RESETVALUE 0x00000000UL /* Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0001FFCFUL /* Mask for I2C_IFS */ + +#define I2C_IFS_START (0x1UL << 0) /* Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /* Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /* Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /* Set Repeated START Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /* Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /* Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /* Set Address Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /* Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /* Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /* Set Transfer Completed Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /* Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /* Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /* Set Acknowledge Received Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /* Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /* Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /* Set Not Acknowledge Received Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /* Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /* Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /* Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /* Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /* Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /* Set Arbitration Lost Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /* Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /* Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /* Set Bus Error Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /* Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /* Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /* Set Bus Held Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /* Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /* Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /* Set Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /* Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /* Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /* Set Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /* Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /* Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /* Set Bus Idle Timeout Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /* Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /* Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /* Set Clock Low Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /* Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /* Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /* Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /* Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /* Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /* Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /* Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ + +#define _I2C_IFC_RESETVALUE 0x00000000UL /* Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0001FFCFUL /* Mask for I2C_IFC */ + +#define I2C_IFC_START (0x1UL << 0) /* Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /* Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /* Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /* Clear Repeated START Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /* Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /* Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /* Clear Address Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /* Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /* Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /* Clear Transfer Completed Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /* Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /* Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /* Clear Acknowledge Received Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /* Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /* Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /* Clear Not Acknowledge Received Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /* Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /* Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /* Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /* Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /* Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /* Clear Arbitration Lost Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /* Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /* Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /* Clear Bus Error Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /* Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /* Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /* Clear Bus Held Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /* Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /* Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /* Clear Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /* Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /* Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /* Clear Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /* Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /* Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /* Clear Bus Idle Timeout Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /* Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /* Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /* Clear Clock Low Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /* Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /* Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /* Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /* Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /* Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /* Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /* Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ + +#define _I2C_IEN_RESETVALUE 0x00000000UL /* Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0001FFFFUL /* Mask for I2C_IEN */ + +#define I2C_IEN_START (0x1UL << 0) /* START Condition Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /* Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /* Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /* Repeated START condition Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /* Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /* Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /* Address Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /* Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /* Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /* Transfer Completed Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /* Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /* Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /* Transmit Buffer level Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /* Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /* Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /* Receive Data Valid Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /* Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /* Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /* Acknowledge Received Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /* Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /* Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /* Not Acknowledge Received Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /* Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /* Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /* MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /* Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /* Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /* Arbitration Lost Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /* Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /* Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /* Bus Error Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /* Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /* Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /* Bus Held Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /* Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /* Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /* Transmit Buffer Overflow Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /* Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /* Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /* Receive Buffer Underflow Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /* Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /* Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /* Bus Idle Timeout Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /* Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /* Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /* Clock Low Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /* Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /* Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /* Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /* SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /* Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /* Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /* Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTE */ + +#define _I2C_ROUTE_RESETVALUE 0x00000000UL /* Default value for I2C_ROUTE */ +#define _I2C_ROUTE_MASK 0x00000703UL /* Mask for I2C_ROUTE */ + +#define I2C_ROUTE_SDAPEN (0x1UL << 0) /* SDA Pin Enable */ +#define _I2C_ROUTE_SDAPEN_SHIFT 0 /* Shift value for I2C_SDAPEN */ +#define _I2C_ROUTE_SDAPEN_MASK 0x1UL /* Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /* Shifted mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_SCLPEN (0x1UL << 1) /* SCL Pin Enable */ +#define _I2C_ROUTE_SCLPEN_SHIFT 1 /* Shift value for I2C_SCLPEN */ +#define _I2C_ROUTE_SCLPEN_MASK 0x2UL /* Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /* Shifted mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_SHIFT 8 /* Shift value for I2C_LOCATION */ +#define _I2C_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for I2C_LOCATION */ +#define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /* Mode LOC3 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /* Mode LOC4 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /* Mode LOC5 for I2C_ROUTE */ +#define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /* Mode LOC6 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /* Shifted mode LOC3 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /* Shifted mode LOC4 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /* Shifted mode LOC5 for I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /* Shifted mode LOC6 for I2C_ROUTE */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_I2C_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_lcd.h b/nuttx/arch/arm/src/efm32/chip/efm32_lcd.h new file mode 100644 index 000000000..f00a4706f --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_lcd.h @@ -0,0 +1,714 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_lcd.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* LCD Register Offsets ********************************************************************************************************/ + +#define EFM32_LCD_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_LCD_DISPCTRL_OFFSET 0x0004 /* Display Control Register */ +#define EFM32_LCD_SEGEN_OFFSET 0x0008 /* Segment Enable Register */ +#define EFM32_LCD_BACTRL_OFFSET 0x000c /* Blink and Animation Control Register */ +#define EFM32_LCD_STATUS_OFFSET 0x0010 /* Status Register */ +#define EFM32_LCD_AREGA_OFFSET 0x0014 /* Animation Register A */ +#define EFM32_LCD_AREGB_OFFSET 0x0018 /* Animation Register B */ +#define EFM32_LCD_IF_OFFSET 0x001c /* Interrupt Flag Register */ +#define EFM32_LCD_IFS_OFFSET 0x0020 /* Interrupt Flag Set Register */ +#define EFM32_LCD_IFC_OFFSET 0x0024 /* Interrupt Flag Clear Register */ +#define EFM32_LCD_IEN_OFFSET 0x0028 /* Interrupt Enable Register */ +#define EFM32_LCD_SEGD0L_OFFSET 0x0040 /* Segment Data Low Register 0 */ +#define EFM32_LCD_SEGD1L_OFFSET 0x0044 /* Segment Data Low Register 1 */ +#define EFM32_LCD_SEGD2L_OFFSET 0x0048 /* Segment Data Low Register 2 */ +#define EFM32_LCD_SEGD3L_OFFSET 0x004c /* Segment Data Low Register 3 */ +#define EFM32_LCD_SEGD0H_OFFSET 0x0050 /* Segment Data High Register 0 */ +#define EFM32_LCD_SEGD1H_OFFSET 0x0054 /* Segment Data High Register 1 */ +#define EFM32_LCD_SEGD2H_OFFSET 0x0058 /* Segment Data High Register 2 */ +#define EFM32_LCD_SEGD3H_OFFSET 0x005c /* Segment Data High Register 3 */ +#define EFM32_LCD_FREEZE_OFFSET 0x0060 /* Freeze Register */ +#define EFM32_LCD_SYNCBUSY_OFFSET 0x0064 /* Synchronization Busy Register */ +#define EFM32_LCD_SEGD4H_OFFSET 0x00b4 /* Segment Data High Register 4 */ +#define EFM32_LCD_SEGD5H_OFFSET 0x00b8 /* Segment Data High Register 5 */ +#define EFM32_LCD_SEGD6H_OFFSET 0x00bc /* Segment Data High Register 6 */ +#define EFM32_LCD_SEGD7H_OFFSET 0x00c0 /* Segment Data High Register 7 */ +#define EFM32_LCD_SEGD4L_OFFSET 0x00cc /* Segment Data Low Register 4 */ +#define EFM32_LCD_SEGD5L_OFFSET 0x00d0 /* Segment Data Low Register 5 */ +#define EFM32_LCD_SEGD6L_OFFSET 0x00d4 /* Segment Data Low Register 6 */ +#define EFM32_LCD_SEGD7L_OFFSET 0x00d8 /* Segment Data Low Register 7 */ + +/* LCD Register Addresses ******************************************************************************************************/ + +#define EFM32_LCD_CTRL (EFM32_LCD_BASE+EFM32_LCD_CTRL_OFFSET) +#define EFM32_LCD_DISPCTRL (EFM32_LCD_BASE+EFM32_LCD_DISPCTRL_OFFSET) +#define EFM32_LCD_SEGEN (EFM32_LCD_BASE+EFM32_LCD_SEGEN_OFFSET) +#define EFM32_LCD_BACTRL (EFM32_LCD_BASE+EFM32_LCD_BACTRL_OFFSET) +#define EFM32_LCD_STATUS (EFM32_LCD_BASE+EFM32_LCD_STATUS_OFFSET) +#define EFM32_LCD_AREGA (EFM32_LCD_BASE+EFM32_LCD_AREGA_OFFSET) +#define EFM32_LCD_AREGB (EFM32_LCD_BASE+EFM32_LCD_AREGB_OFFSET) +#define EFM32_LCD_IF (EFM32_LCD_BASE+EFM32_LCD_IF_OFFSET) +#define EFM32_LCD_IFS (EFM32_LCD_BASE+EFM32_LCD_IFS_OFFSET) +#define EFM32_LCD_IFC (EFM32_LCD_BASE+EFM32_LCD_IFC_OFFSET) +#define EFM32_LCD_IEN (EFM32_LCD_BASE+EFM32_LCD_IEN_OFFSET) +#define EFM32_LCD_SEGD0L (EFM32_LCD_BASE+EFM32_LCD_SEGD0L_OFFSET) +#define EFM32_LCD_SEGD1L (EFM32_LCD_BASE+EFM32_LCD_SEGD1L_OFFSET) +#define EFM32_LCD_SEGD2L (EFM32_LCD_BASE+EFM32_LCD_SEGD2L_OFFSET) +#define EFM32_LCD_SEGD3L (EFM32_LCD_BASE+EFM32_LCD_SEGD3L_OFFSET) +#define EFM32_LCD_SEGD0H (EFM32_LCD_BASE+EFM32_LCD_SEGD0H_OFFSET) +#define EFM32_LCD_SEGD1H (EFM32_LCD_BASE+EFM32_LCD_SEGD1H_OFFSET) +#define EFM32_LCD_SEGD2H (EFM32_LCD_BASE+EFM32_LCD_SEGD2H_OFFSET) +#define EFM32_LCD_SEGD3H (EFM32_LCD_BASE+EFM32_LCD_SEGD3H_OFFSET) +#define EFM32_LCD_FREEZE (EFM32_LCD_BASE+EFM32_LCD_FREEZE_OFFSET) +#define EFM32_LCD_SYNCBUSY (EFM32_LCD_BASE+EFM32_LCD_SYNCBUSY_OFFSET) +#define EFM32_LCD_SEGD4H (EFM32_LCD_BASE+EFM32_LCD_SEGD4H_OFFSET) +#define EFM32_LCD_SEGD5H (EFM32_LCD_BASE+EFM32_LCD_SEGD5H_OFFSET) +#define EFM32_LCD_SEGD6H (EFM32_LCD_BASE+EFM32_LCD_SEGD6H_OFFSET) +#define EFM32_LCD_SEGD7H (EFM32_LCD_BASE+EFM32_LCD_SEGD7H_OFFSET) +#define EFM32_LCD_SEGD4L (EFM32_LCD_BASE+EFM32_LCD_SEGD4L_OFFSET) +#define EFM32_LCD_SEGD5L (EFM32_LCD_BASE+EFM32_LCD_SEGD5L_OFFSET) +#define EFM32_LCD_SEGD6L (EFM32_LCD_BASE+EFM32_LCD_SEGD6L_OFFSET) +#define EFM32_LCD_SEGD7L (EFM32_LCD_BASE+EFM32_LCD_SEGD7L_OFFSET) + +/* LCD Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for LCD CTRL */ + +#define _LCD_CTRL_RESETVALUE 0x00000000UL /* Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x00800007UL /* Mask for LCD_CTRL */ + +#define LCD_CTRL_EN (0x1UL << 0) /* LCD Enable */ +#define _LCD_CTRL_EN_SHIFT 0 /* Shift value for LCD_EN */ +#define _LCD_CTRL_EN_MASK 0x1UL /* Bit mask for LCD_EN */ +#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /* Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /* Bit mask for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /* Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /* Mode FCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /* Mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /* Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /* Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /* Shifted mode FCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /* Shifted mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_DSC (0x1UL << 23) /* Direct Segment Control */ +#define _LCD_CTRL_DSC_SHIFT 23 /* Shift value for LCD_DSC */ +#define _LCD_CTRL_DSC_MASK 0x800000UL /* Bit mask for LCD_DSC */ +#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /* Shifted mode DEFAULT for LCD_CTRL */ + +/* Bit fields for LCD DISPCTRL */ + +#define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /* Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x005D9F1FUL /* Mask for LCD_DISPCTRL */ + +#define _LCD_DISPCTRL_MUX_SHIFT 0 /* Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x3UL /* Bit mask for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /* Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /* Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /* Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /* Mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /* Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /* Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /* Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /* Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 2 /* Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0xCUL /* Bit mask for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /* Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /* Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /* Mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /* Mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /* Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /* Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /* Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /* Shifted mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (0x1UL << 4) /* Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /* Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /* Bit mask for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /* Mode LOWPOWER for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /* Mode NORMAL for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /* Shifted mode LOWPOWER for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /* Shifted mode NORMAL for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_SHIFT 8 /* Shift value for LCD_CONLEV */ +#define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /* Bit mask for LCD_CONLEV */ +#define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /* Mode MIN for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /* Mode MAX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /* Shifted mode MIN for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /* Shifted mode MAX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF (0x1UL << 15) /* Contrast Configuration */ +#define _LCD_DISPCTRL_CONCONF_SHIFT 15 /* Shift value for LCD_CONCONF */ +#define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /* Bit mask for LCD_CONCONF */ +#define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /* Mode VLCD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /* Mode GND for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /* Shifted mode VLCD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /* Shifted mode GND for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /* VLCD Selection */ +#define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /* Shift value for LCD_VLCDSEL */ +#define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /* Bit mask for LCD_VLCDSEL */ +#define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /* Mode VDD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /* Mode VEXTBOOST for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /* Shifted mode VDD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /* Shifted mode VEXTBOOST for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_SHIFT 18 /* Shift value for LCD_VBLEV */ +#define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /* Bit mask for LCD_VBLEV */ +#define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /* Mode LEVEL0 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /* Mode LEVEL1 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /* Mode LEVEL2 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /* Mode LEVEL3 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /* Mode LEVEL4 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /* Mode LEVEL5 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /* Mode LEVEL6 for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /* Mode LEVEL7 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /* Shifted mode LEVEL0 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /* Shifted mode LEVEL1 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /* Shifted mode LEVEL2 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /* Shifted mode LEVEL3 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /* Shifted mode LEVEL4 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /* Shifted mode LEVEL5 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /* Shifted mode LEVEL6 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /* Shifted mode LEVEL7 for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUXE (0x1UL << 22) /* Extended Mux Configuration */ +#define _LCD_DISPCTRL_MUXE_SHIFT 22 /* Shift value for LCD_MUXE */ +#define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /* Bit mask for LCD_MUXE */ +#define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /* Mode MUX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /* Mode MUXE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /* Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /* Shifted mode MUX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /* Shifted mode MUXE for LCD_DISPCTRL */ + +/* Bit fields for LCD SEGEN */ + +#define _LCD_SEGEN_RESETVALUE 0x00000000UL /* Default value for LCD_SEGEN */ +#define _LCD_SEGEN_MASK 0x000003FFUL /* Mask for LCD_SEGEN */ + +#define _LCD_SEGEN_SEGEN_SHIFT 0 /* Shift value for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /* Bit mask for LCD_SEGEN */ +#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGEN */ +#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGEN */ + +/* Bit fields for LCD BACTRL */ + +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /* Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x10FF01FFUL /* Mask for LCD_BACTRL */ + +#define LCD_BACTRL_BLINKEN (0x1UL << 0) /* Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /* Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /* Bit mask for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (0x1UL << 1) /* Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /* Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /* Bit mask for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN (0x1UL << 2) /* Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /* Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /* Bit mask for LCD_AEN */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /* Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /* Bit mask for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /* Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /* Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /* Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /* Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /* Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /* Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /* Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /* Bit mask for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /* Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /* Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /* Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /* Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /* Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /* Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /* Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /* Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /* Bit mask for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /* Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /* Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /* Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /* Shifted mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (0x1UL << 8) /* Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /* Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /* Bit mask for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_SHIFT 16 /* Shift value for LCD_FCPRESC */ +#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /* Bit mask for LCD_FCPRESC */ +#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /* Mode DIV1 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /* Mode DIV2 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /* Mode DIV4 for LCD_BACTRL */ +#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /* Mode DIV8 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /* Shifted mode DIV1 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /* Shifted mode DIV2 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /* Shifted mode DIV4 for LCD_BACTRL */ +#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /* Shifted mode DIV8 for LCD_BACTRL */ +#define _LCD_BACTRL_FCTOP_SHIFT 18 /* Shift value for LCD_FCTOP */ +#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /* Bit mask for LCD_FCTOP */ +#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC (0x1UL << 28) /* Animation Location */ +#define _LCD_BACTRL_ALOC_SHIFT 28 /* Shift value for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /* Bit mask for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /* Mode SEG0TO7 for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /* Mode SEG8TO15 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /* Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /* Shifted mode SEG0TO7 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /* Shifted mode SEG8TO15 for LCD_BACTRL */ + +/* Bit fields for LCD STATUS */ + +#define _LCD_STATUS_RESETVALUE 0x00000000UL /* Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000010FUL /* Mask for LCD_STATUS */ + +#define _LCD_STATUS_ASTATE_SHIFT 0 /* Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /* Bit mask for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (0x1UL << 8) /* Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /* Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /* Bit mask for LCD_BLINK */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /* Shifted mode DEFAULT for LCD_STATUS */ + +/* Bit fields for LCD AREGA */ + +#define _LCD_AREGA_RESETVALUE 0x00000000UL /* Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /* Mask for LCD_AREGA */ + +#define _LCD_AREGA_AREGA_SHIFT 0 /* Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /* Bit mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_AREGA */ + +/* Bit fields for LCD AREGB */ + +#define _LCD_AREGB_RESETVALUE 0x00000000UL /* Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /* Mask for LCD_AREGB */ + +#define _LCD_AREGB_AREGB_SHIFT 0 /* Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /* Bit mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_AREGB */ + +/* Bit fields for LCD IF */ + +#define _LCD_IF_RESETVALUE 0x00000000UL /* Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000001UL /* Mask for LCD_IF */ + +#define LCD_IF_FC (0x1UL << 0) /* Frame Counter Interrupt Flag */ +#define _LCD_IF_FC_SHIFT 0 /* Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /* Bit mask for LCD_FC */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_IF */ +#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_IF */ + +/* Bit fields for LCD IFS */ + +#define _LCD_IFS_RESETVALUE 0x00000000UL /* Default value for LCD_IFS */ +#define _LCD_IFS_MASK 0x00000001UL /* Mask for LCD_IFS */ + +#define LCD_IFS_FC (0x1UL << 0) /* Frame Counter Interrupt Flag Set */ +#define _LCD_IFS_FC_SHIFT 0 /* Shift value for LCD_FC */ +#define _LCD_IFS_FC_MASK 0x1UL /* Bit mask for LCD_FC */ +#define _LCD_IFS_FC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_IFS */ +#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_IFS */ + +/* Bit fields for LCD IFC */ + +#define _LCD_IFC_RESETVALUE 0x00000000UL /* Default value for LCD_IFC */ +#define _LCD_IFC_MASK 0x00000001UL /* Mask for LCD_IFC */ + +#define LCD_IFC_FC (0x1UL << 0) /* Frame Counter Interrupt Flag Clear */ +#define _LCD_IFC_FC_SHIFT 0 /* Shift value for LCD_FC */ +#define _LCD_IFC_FC_MASK 0x1UL /* Bit mask for LCD_FC */ +#define _LCD_IFC_FC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_IFC */ +#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_IFC */ + +/* Bit fields for LCD IEN */ + +#define _LCD_IEN_RESETVALUE 0x00000000UL /* Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000001UL /* Mask for LCD_IEN */ + +#define LCD_IEN_FC (0x1UL << 0) /* Frame Counter Interrupt Enable */ +#define _LCD_IEN_FC_SHIFT 0 /* Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /* Bit mask for LCD_FC */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_IEN */ + +/* Bit fields for LCD SEGD0L */ + +#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD0L */ +#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD0L */ + +#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /* Shift value for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD0L */ +#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD0L */ +#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD0L */ + +/* Bit fields for LCD SEGD1L */ + +#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD1L */ +#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD1L */ + +#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /* Shift value for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD1L */ +#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD1L */ +#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD1L */ + +/* Bit fields for LCD SEGD2L */ + +#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD2L */ +#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD2L */ + +#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /* Shift value for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD2L */ +#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD2L */ +#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD2L */ + +/* Bit fields for LCD SEGD3L */ + +#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD3L */ +#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD3L */ + +#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /* Shift value for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD3L */ +#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD3L */ +#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD3L */ + +/* Bit fields for LCD SEGD0H */ + +#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD0H */ +#define _LCD_SEGD0H_MASK 0x000000FFUL /* Mask for LCD_SEGD0H */ + +#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /* Shift value for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /* Bit mask for LCD_SEGD0H */ +#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD0H */ +#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD0H */ + +/* Bit fields for LCD SEGD1H */ + +#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD1H */ +#define _LCD_SEGD1H_MASK 0x000000FFUL /* Mask for LCD_SEGD1H */ + +#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /* Shift value for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /* Bit mask for LCD_SEGD1H */ +#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD1H */ +#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD1H */ + +/* Bit fields for LCD SEGD2H */ + +#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD2H */ +#define _LCD_SEGD2H_MASK 0x000000FFUL /* Mask for LCD_SEGD2H */ + +#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /* Shift value for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /* Bit mask for LCD_SEGD2H */ +#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD2H */ +#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD2H */ + +/* Bit fields for LCD SEGD3H */ + +#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD3H */ +#define _LCD_SEGD3H_MASK 0x000000FFUL /* Mask for LCD_SEGD3H */ + +#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /* Shift value for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /* Bit mask for LCD_SEGD3H */ +#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD3H */ +#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD3H */ + +/* Bit fields for LCD FREEZE */ + +#define _LCD_FREEZE_RESETVALUE 0x00000000UL /* Default value for LCD_FREEZE */ +#define _LCD_FREEZE_MASK 0x00000001UL /* Mask for LCD_FREEZE */ + +#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */ +#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for LCD_REGFREEZE */ +#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for LCD_REGFREEZE */ +#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for LCD_FREEZE */ +#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for LCD_FREEZE */ +#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for LCD_FREEZE */ + +/* Bit fields for LCD SYNCBUSY */ + +#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for LCD_SYNCBUSY */ +#define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /* Mask for LCD_SYNCBUSY */ + +#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */ +#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for LCD_CTRL */ +#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for LCD_CTRL */ +#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /* BACTRL Register Busy */ +#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /* Shift value for LCD_BACTRL */ +#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /* Bit mask for LCD_BACTRL */ +#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /* AREGA Register Busy */ +#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /* Shift value for LCD_AREGA */ +#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /* Bit mask for LCD_AREGA */ +#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /* AREGB Register Busy */ +#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /* Shift value for LCD_AREGB */ +#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /* Bit mask for LCD_AREGB */ +#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /* SEGD0L Register Busy */ +#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /* Shift value for LCD_SEGD0L */ +#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /* Bit mask for LCD_SEGD0L */ +#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /* SEGD1L Register Busy */ +#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /* Shift value for LCD_SEGD1L */ +#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /* Bit mask for LCD_SEGD1L */ +#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /* SEGD2L Register Busy */ +#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /* Shift value for LCD_SEGD2L */ +#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /* Bit mask for LCD_SEGD2L */ +#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /* SEGD3L Register Busy */ +#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /* Shift value for LCD_SEGD3L */ +#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /* Bit mask for LCD_SEGD3L */ +#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /* SEGD0H Register Busy */ +#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /* Shift value for LCD_SEGD0H */ +#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /* Bit mask for LCD_SEGD0H */ +#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /* SEGD1H Register Busy */ +#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /* Shift value for LCD_SEGD1H */ +#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /* Bit mask for LCD_SEGD1H */ +#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /* SEGD2H Register Busy */ +#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /* Shift value for LCD_SEGD2H */ +#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /* Bit mask for LCD_SEGD2H */ +#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /* SEGD3H Register Busy */ +#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /* Shift value for LCD_SEGD3H */ +#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /* Bit mask for LCD_SEGD3H */ +#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /* SEGD4H Register Busy */ +#define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /* Shift value for LCD_SEGD4H */ +#define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /* Bit mask for LCD_SEGD4H */ +#define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /* SEGD5H Register Busy */ +#define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /* Shift value for LCD_SEGD5H */ +#define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /* Bit mask for LCD_SEGD5H */ +#define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /* SEGD6H Register Busy */ +#define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /* Shift value for LCD_SEGD6H */ +#define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /* Bit mask for LCD_SEGD6H */ +#define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /* SEGD7H Register Busy */ +#define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /* Shift value for LCD_SEGD7H */ +#define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /* Bit mask for LCD_SEGD7H */ +#define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /* SEGD4L Register Busy */ +#define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /* Shift value for LCD_SEGD4L */ +#define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /* Bit mask for LCD_SEGD4L */ +#define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /* SEGD5L Register Busy */ +#define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /* Shift value for LCD_SEGD5L */ +#define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /* Bit mask for LCD_SEGD5L */ +#define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /* SEGD6L Register Busy */ +#define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /* Shift value for LCD_SEGD6L */ +#define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /* Bit mask for LCD_SEGD6L */ +#define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /* SEGD7L Register Busy */ +#define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /* Shift value for LCD_SEGD7L */ +#define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /* Bit mask for LCD_SEGD7L */ +#define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SYNCBUSY */ +#define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /* Shifted mode DEFAULT for LCD_SYNCBUSY */ + +/* Bit fields for LCD SEGD4H */ + +#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD4H */ +#define _LCD_SEGD4H_MASK 0x000000FFUL /* Mask for LCD_SEGD4H */ + +#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /* Shift value for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /* Bit mask for LCD_SEGD4H */ +#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD4H */ +#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD4H */ + +/* Bit fields for LCD SEGD5H */ + +#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD5H */ +#define _LCD_SEGD5H_MASK 0x000000FFUL /* Mask for LCD_SEGD5H */ + +#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /* Shift value for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /* Bit mask for LCD_SEGD5H */ +#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD5H */ +#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD5H */ + +/* Bit fields for LCD SEGD6H */ + +#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD6H */ +#define _LCD_SEGD6H_MASK 0x000000FFUL /* Mask for LCD_SEGD6H */ + +#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /* Shift value for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /* Bit mask for LCD_SEGD6H */ +#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD6H */ +#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD6H */ + +/* Bit fields for LCD SEGD7H */ + +#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD7H */ +#define _LCD_SEGD7H_MASK 0x000000FFUL /* Mask for LCD_SEGD7H */ + +#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /* Shift value for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /* Bit mask for LCD_SEGD7H */ +#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD7H */ +#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD7H */ + +/* Bit fields for LCD SEGD4L */ + +#define _LCD_SEGD4L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD4L */ +#define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD4L */ + +#define _LCD_SEGD4L_SEGD4L_SHIFT 0 /* Shift value for LCD_SEGD4L */ +#define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD4L */ +#define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD4L */ +#define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD4L */ + +/* Bit fields for LCD SEGD5L */ + +#define _LCD_SEGD5L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD5L */ +#define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD5L */ + +#define _LCD_SEGD5L_SEGD5L_SHIFT 0 /* Shift value for LCD_SEGD5L */ +#define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD5L */ +#define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD5L */ +#define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD5L */ + +/* Bit fields for LCD SEGD6L */ + +#define _LCD_SEGD6L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD6L */ +#define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD6L */ + +#define _LCD_SEGD6L_SEGD6L_SHIFT 0 /* Shift value for LCD_SEGD6L */ +#define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD6L */ +#define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD6L */ +#define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD6L */ + +/* Bit fields for LCD SEGD7L */ + +#define _LCD_SEGD7L_RESETVALUE 0x00000000UL /* Default value for LCD_SEGD7L */ +#define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /* Mask for LCD_SEGD7L */ + +#define _LCD_SEGD7L_SEGD7L_SHIFT 0 /* Shift value for LCD_SEGD7L */ +#define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /* Bit mask for LCD_SEGD7L */ +#define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /* Mode DEFAULT for LCD_SEGD7L */ +#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /* Shifted mode DEFAULT for LCD_SEGD7L */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LCD_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_lesense.h b/nuttx/arch/arm/src/efm32/chip/efm32_lesense.h new file mode 100644 index 000000000..512a7095b --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_lesense.h @@ -0,0 +1,2160 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_lesense.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* LESENSE Register Offsets ****************************************************************************************************/ + +#define EFM32_LESENSE_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_LESENSE_TIMCTRL_OFFSET 0x0004 /* Timing Control Register */ +#define EFM32_LESENSE_PERCTRL_OFFSET 0x0008 /* Peripheral Control Register */ +#define EFM32_LESENSE_DECCTRL_OFFSET 0x000c /* Decoder control Register */ +#define EFM32_LESENSE_BIASCTRL_OFFSET 0x0010 /* Bias Control Register */ +#define EFM32_LESENSE_CMD_OFFSET 0x0014 /* Command Register */ +#define EFM32_LESENSE_CHEN_OFFSET 0x0018 /* Channel enable Register */ +#define EFM32_LESENSE_SCANRES_OFFSET 0x001c /* Scan result register */ +#define EFM32_LESENSE_STATUS_OFFSET 0x0020 /* Status Register */ +#define EFM32_LESENSE_PTR_OFFSET 0x0024 /* Result buffer pointers */ +#define EFM32_LESENSE_BUFDATA_OFFSET 0x0028 /* Result buffer data register */ +#define EFM32_LESENSE_CURCH_OFFSET 0x002c /* Current channel index */ +#define EFM32_LESENSE_DECSTATE_OFFSET 0x0030 /* Current decoder state */ +#define EFM32_LESENSE_SENSORSTATE_OFFSET 0x0034 /* Decoder input register */ +#define EFM32_LESENSE_IDLECONF_OFFSET 0x0038 /* GPIO Idlephase configuration */ +#define EFM32_LESENSE_ALTEXCONF_OFFSET 0x003c /* Alternative excite pin configuration */ +#define EFM32_LESENSE_IF_OFFSET 0x0040 /* Interrupt Flag Register */ +#define EFM32_LESENSE_IFC_OFFSET 0x0044 /* Interrupt Flag Clear Register */ +#define EFM32_LESENSE_IFS_OFFSET 0x0048 /* Interrupt Flag Set Register */ +#define EFM32_LESENSE_IEN_OFFSET 0x004c /* Interrupt Enable Register */ +#define EFM32_LESENSE_SYNCBUSY_OFFSET 0x0050 /* Synchronization Busy Register */ +#define EFM32_LESENSE_ROUTE_OFFSET 0x0054 /* I/O Routing Register */ +#define EFM32_LESENSE_POWERDOWN_OFFSET 0x0058 /* LESENSE RAM power-down resgister */ + +#define EFM32_LESENSE_ST_OFFSET(n) (0x0200 + ((n) << 3)) +#define EFM32_LESENSE_ST0_OFFSET 0x0200 /* State 0 transition configuration offset */ +#define EFM32_LESENSE_ST1_OFFSET 0x0208 /* State 1 transition configuration offset */ +#define EFM32_LESENSE_ST2_OFFSET 0x0210 /* State 2 transition configuration offset */ +#define EFM32_LESENSE_ST3_OFFSET 0x0218 /* State 3 transition configuration offset */ +#define EFM32_LESENSE_ST4_OFFSET 0x0220 /* State 4 transition configuration offset */ +#define EFM32_LESENSE_ST5_OFFSET 0x0228 /* State 5 transition configuration offset */ +#define EFM32_LESENSE_ST6_OFFSET 0x0230 /* State 6 transition configuration offset */ +#define EFM32_LESENSE_ST7_OFFSET 0x0238 /* State 7 transition configuration offset */ +#define EFM32_LESENSE_ST8_OFFSET 0x0240 /* State 8 transition configuration offset */ +#define EFM32_LESENSE_ST9_OFFSET 0x0248 /* State 9 transition configuration offset */ +#define EFM32_LESENSE_ST10_OFFSET 0x0250 /* State 10 transition configuration offset */ +#define EFM32_LESENSE_ST11_OFFSET 0x0258 /* State 11 transition configuration offset */ +#define EFM32_LESENSE_ST12_OFFSET 0x0260 /* State 12 transition configuration offset */ +#define EFM32_LESENSE_ST13_OFFSET 0x0268 /* State 13 transition configuration offset */ +#define EFM32_LESENSE_ST14_OFFSET 0x0270 /* State 14 transition configuration offset */ +#define EFM32_LESENSE_ST15_OFFSET 0x0278 /* State 15 transition configuration offset */ + +#define EFM32_LESENSE_STn_TCONFA_OFFSET 0x0000 /* State transition configuration A */ +#define EFM32_LESENSE_STn_TCONFB_OFFSET 0x0004 /* State transition configuration B */ + +#define EFM32_LESENSE_BUF_DATA_OFFSET(n) (0x0280 + ((n) << 2)) +#define EFM32_LESENSE_BUF0_DATA_OFFSET 0x0280 /* Scan results 0 */ +#define EFM32_LESENSE_BUF1_DATA_OFFSET 0x0284 /* Scan results 1 */ +#define EFM32_LESENSE_BUF2_DATA_OFFSET 0x0288 /* Scan results 2 */ +#define EFM32_LESENSE_BUF3_DATA_OFFSET 0x028c /* Scan results 3 */ +#define EFM32_LESENSE_BUF4_DATA_OFFSET 0x0290 /* Scan results 4 */ +#define EFM32_LESENSE_BUF5_DATA_OFFSET 0x0294 /* Scan results 5 */ +#define EFM32_LESENSE_BUF6_DATA_OFFSET 0x0298 /* Scan results 6 */ +#define EFM32_LESENSE_BUF7_DATA_OFFSET 0x029c /* Scan results 7 */ +#define EFM32_LESENSE_BUF8_DATA_OFFSET 0x02a0 /* Scan results 8 */ +#define EFM32_LESENSE_BUF9_DATA_OFFSET 0x02a4 /* Scan results 9 */ +#define EFM32_LESENSE_BUF10_DATA_OFFSET 0x02a8 /* Scan results 10 */ +#define EFM32_LESENSE_BUF11_DATA_OFFSET 0x02ac /* Scan results 11 */ +#define EFM32_LESENSE_BUF12_DATA_OFFSET 0x02b0 /* Scan results 12 */ +#define EFM32_LESENSE_BUF13_DATA_OFFSET 0x02b4 /* Scan results 13 */ +#define EFM32_LESENSE_BUF14_DATA_OFFSET 0x02b8 /* Scan results 14 */ +#define EFM32_LESENSE_BUF15_DATA_OFFSET 0x02bc /* Scan results 15 */ + +#define EFM32_LESENSE_CH_OFFSET(n) (0x02c0 + ((n) << 4)) +#define EFM32_LESENSE_CH0_OFFSET 0x02c0 /* Channel 0 Offset */ +#define EFM32_LESENSE_CH1_OFFSET 0x02d0 /* Channel 1 Offset */ +#define EFM32_LESENSE_CH2_OFFSET 0x02e0 /* Channel 2 Offset */ +#define EFM32_LESENSE_CH3_OFFSET 0x02f0 /* Channel 3 Offset */ +#define EFM32_LESENSE_CH4_OFFSET 0x0300 /* Channel 4 Offset */ +#define EFM32_LESENSE_CH5_OFFSET 0x0310 /* Channel 5 Offset */ +#define EFM32_LESENSE_CH6_OFFSET 0x0320 /* Channel 6 Offset */ +#define EFM32_LESENSE_CH7_OFFSET 0x0330 /* Channel 7 Offset */ +#define EFM32_LESENSE_CH8_OFFSET 0x0340 /* Channel 8 Offset */ +#define EFM32_LESENSE_CH9_OFFSET 0x0350 /* Channel 9 Offset */ +#define EFM32_LESENSE_CH10_OFFSET 0x0360 /* Channel 10 Offset */ +#define EFM32_LESENSE_CH11_OFFSET 0x0370 /* Channel 11 Offset */ +#define EFM32_LESENSE_CH12_OFFSET 0x0380 /* Channel 12 Offset */ +#define EFM32_LESENSE_CH13_OFFSET 0x0390 /* Channel 13 Offset */ +#define EFM32_LESENSE_CH14_OFFSET 0x03a0 /* Channel 14 Offset */ +#define EFM32_LESENSE_CH15_OFFSET 0x03b0 /* Channel 15 Offset */ + +#define EFM32_LESENSE_CHn_TIMING_OFFSET 0x0000 /* Channel n Scan Configuration */ +#define EFM32_LESENSE_CHn_INTERACT_OFFSET 0x0004 /* Channel n Scan Configuration */ +#define EFM32_LESENSE_CHn_EVAL_OFFSET 0x0008 /* Channel n Scan Configuration */ + +/* LESENSE Register Addresses **************************************************************************************************/ + +#define EFM32_LESENSE_CTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_CTRL_OFFSET) +#define EFM32_LESENSE_TIMCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_TIMCTRL_OFFSET) +#define EFM32_LESENSE_PERCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_PERCTRL_OFFSET) +#define EFM32_LESENSE_DECCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_DECCTRL_OFFSET) +#define EFM32_LESENSE_BIASCTRL (EFM32_LESENSE_BASE+EFM32_LESENSE_BIASCTRL_OFFSET) +#define EFM32_LESENSE_CMD (EFM32_LESENSE_BASE+EFM32_LESENSE_CMD_OFFSET) +#define EFM32_LESENSE_CHEN (EFM32_LESENSE_BASE+EFM32_LESENSE_CHEN_OFFSET) +#define EFM32_LESENSE_SCANRES (EFM32_LESENSE_BASE+EFM32_LESENSE_SCANRES_OFFSET) +#define EFM32_LESENSE_STATUS (EFM32_LESENSE_BASE+EFM32_LESENSE_STATUS_OFFSET) +#define EFM32_LESENSE_PTR (EFM32_LESENSE_BASE+EFM32_LESENSE_PTR_OFFSET) +#define EFM32_LESENSE_BUFDATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUFDATA_OFFSET) +#define EFM32_LESENSE_CURCH (EFM32_LESENSE_BASE+EFM32_LESENSE_CURCH_OFFSET) +#define EFM32_LESENSE_DECSTATE (EFM32_LESENSE_BASE+EFM32_LESENSE_DECSTATE_OFFSET) +#define EFM32_LESENSE_SENSORSTATE (EFM32_LESENSE_BASE+EFM32_LESENSE_SENSORSTATE_OFFSET) +#define EFM32_LESENSE_IDLECONF (EFM32_LESENSE_BASE+EFM32_LESENSE_IDLECONF_OFFSET) +#define EFM32_LESENSE_ALTEXCONF (EFM32_LESENSE_BASE+EFM32_LESENSE_ALTEXCONF_OFFSET) +#define EFM32_LESENSE_IF (EFM32_LESENSE_BASE+EFM32_LESENSE_IF_OFFSET) +#define EFM32_LESENSE_IFC (EFM32_LESENSE_BASE+EFM32_LESENSE_IFC_OFFSET) +#define EFM32_LESENSE_IFS (EFM32_LESENSE_BASE+EFM32_LESENSE_IFS_OFFSET) +#define EFM32_LESENSE_IEN (EFM32_LESENSE_BASE+EFM32_LESENSE_IEN_OFFSET) +#define EFM32_LESENSE_SYNCBUSY (EFM32_LESENSE_BASE+EFM32_LESENSE_SYNCBUSY_OFFSET) +#define EFM32_LESENSE_ROUTE (EFM32_LESENSE_BASE+EFM32_LESENSE_ROUTE_OFFSET) +#define EFM32_LESENSE_POWERDOWN (EFM32_LESENSE_BASE+EFM32_LESENSE_POWERDOWN_OFFSET) + +#define EFM32_LESENSE_ST_BASE(n) (EFM32_LESENSE_BASE+EFM32_LESENSE_ST_OFFSET(n)) +#define EFM32_LESENSE_ST0_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST0_OFFSET) +#define EFM32_LESENSE_ST1_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST1_OFFSET) +#define EFM32_LESENSE_ST2_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST2_OFFSET) +#define EFM32_LESENSE_ST3_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST3_OFFSET) +#define EFM32_LESENSE_ST4_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST4_OFFSET) +#define EFM32_LESENSE_ST5_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST5_OFFSET) +#define EFM32_LESENSE_ST6_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST6_OFFSET) +#define EFM32_LESENSE_ST7_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST7_OFFSET) +#define EFM32_LESENSE_ST8_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST8_OFFSET) +#define EFM32_LESENSE_ST9_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST9_OFFSET) +#define EFM32_LESENSE_ST10_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST10_OFFSET) +#define EFM32_LESENSE_ST11_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST11_OFFSET) +#define EFM32_LESENSE_ST12_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST12_OFFSET) +#define EFM32_LESENSE_ST13_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST13_OFFSET) +#define EFM32_LESENSE_ST14_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST14_OFFSET) +#define EFM32_LESENSE_ST15_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_ST15_OFFSET) + +#define EFM32_LESENSE_ST_TCONFA(n) (EFM32_LESENSE_ST_BASE(n)+EFM32_LESENSE_STn_TCONFA_OFFSET) +#define EFM32_LESENSE_ST_TCONFB(n) (EFM32_LESENSE_ST_BASE(n)+EFM32_LESENSE_STn_TCONFB_OFFSET) + +#define EFM32_LESENSE_BUF_DATA_OFFSET(n) (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF_DATA_OFFSET(n)) +#define EFM32_LESENSE_BUF0_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF0_DATA_OFFSET) +#define EFM32_LESENSE_BUF1_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF1_DATA_OFFSET) +#define EFM32_LESENSE_BUF2_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF2_DATA_OFFSET) +#define EFM32_LESENSE_BUF3_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF3_DATA_OFFSET) +#define EFM32_LESENSE_BUF4_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF4_DATA_OFFSET) +#define EFM32_LESENSE_BUF5_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF5_DATA_OFFSET) +#define EFM32_LESENSE_BUF6_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF6_DATA_OFFSET) +#define EFM32_LESENSE_BUF7_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF7_DATA_OFFSET) +#define EFM32_LESENSE_BUF8_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF8_DATA_OFFSET) +#define EFM32_LESENSE_BUF9_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF9_DATA_OFFSET) +#define EFM32_LESENSE_BUF10_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF10_DATA_OFFSET) +#define EFM32_LESENSE_BUF11_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF11_DATA_OFFSET) +#define EFM32_LESENSE_BUF12_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF12_DATA_OFFSET) +#define EFM32_LESENSE_BUF13_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF13_DATA_OFFSET) +#define EFM32_LESENSE_BUF14_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF14_DATA_OFFSET) +#define EFM32_LESENSE_BUF15_DATA (EFM32_LESENSE_BASE+EFM32_LESENSE_BUF15_DATA_OFFSET) + +#define EFM32_LESENSE_CH_BASE(n) (EFM32_LESENSE_BASE+EFM32_LESENSE_CH_OFFSET(n)) +#define EFM32_LESENSE_CH0_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH0_OFFSET) +#define EFM32_LESENSE_CH1_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH1_OFFSET) +#define EFM32_LESENSE_CH2_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH2_OFFSET) +#define EFM32_LESENSE_CH3_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH3_OFFSET) +#define EFM32_LESENSE_CH4_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH4_OFFSET) +#define EFM32_LESENSE_CH5_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH5_OFFSET) +#define EFM32_LESENSE_CH6_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH6_OFFSET) +#define EFM32_LESENSE_CH7_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH7_OFFSET) +#define EFM32_LESENSE_CH8_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH8_OFFSET) +#define EFM32_LESENSE_CH9_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH9_OFFSET) +#define EFM32_LESENSE_CH10_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH10_OFFSET) +#define EFM32_LESENSE_CH11_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH11_OFFSET) +#define EFM32_LESENSE_CH12_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH12_OFFSET) +#define EFM32_LESENSE_CH13_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH13_OFFSET) +#define EFM32_LESENSE_CH14_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH14_OFFSET) +#define EFM32_LESENSE_CH15_BASE (EFM32_LESENSE_BASE+EFM32_LESENSE_CH15_OFFSET) + +#define EFM32_LESENSE_CH_TIMING(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHn_TIMING_OFFSET) +#define EFM32_LESENSE_CH_INTERACT(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHn_INTERACT_OFFSET) +#define EFM32_LESENSE_CH_EVAL(n) (EFM32_LESENSE_CH_BASE(n)+EFM32_LESENSE_CHb_EVAL_OFFSET) + +/* LESENSE Register Bit Field Definitions **************************************************************************************/ + +/* Bit fields for LESENSE CTRL */ + +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /* Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x00772EFFUL /* Mask for LESENSE_CTRL */ + +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /* Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /* Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /* Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /* Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /* Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /* Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /* Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /* Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /* Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /* Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /* Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /* Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /* Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /* Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /* Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /* Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /* Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /* Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /* Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /* Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /* Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /* Shifted mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 6 /* Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0xC0UL /* Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /* Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /* Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /* Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /* Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 6) /* Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 6) /* Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 6) /* Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 6) /* Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ACMP0INV (0x1UL << 9) /* Invert analog comparator 0 output */ +#define _LESENSE_CTRL_ACMP0INV_SHIFT 9 /* Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_CTRL_ACMP0INV_MASK 0x200UL /* Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_CTRL_ACMP0INV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ACMP0INV_DEFAULT (_LESENSE_CTRL_ACMP0INV_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ACMP1INV (0x1UL << 10) /* Invert analog comparator 1 output */ +#define _LESENSE_CTRL_ACMP1INV_SHIFT 10 /* Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_CTRL_ACMP1INV_MASK 0x400UL /* Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_CTRL_ACMP1INV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ACMP1INV_DEFAULT (_LESENSE_CTRL_ACMP1INV_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /* Alternative excitation map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /* Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /* Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /* Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ACMP 0x00000001UL /* Mode ACMP for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /* Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ACMP (_LESENSE_CTRL_ALTEXMAP_ACMP << 11) /* Shifted mode ACMP for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /* Enable dual sample mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /* Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /* Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /* Result buffer overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /* Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /* Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /* Enable storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /* Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /* Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 18) /* Result buffer interrupt and DMA trigger level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 18 /* Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x40000UL /* Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /* Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /* Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 18) /* Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 18) /* Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /* Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /* Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /* Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /* Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /* Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /* Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /* Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /* Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /* Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /* Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ + +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /* Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x00CFF773UL /* Mask for LESENSE_TIMCTRL */ + +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /* Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /* Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /* Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /* Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /* Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /* Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /* Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /* Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /* Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /* Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /* Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /* Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /* Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /* Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /* Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /* Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /* Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /* Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /* Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /* Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /* Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /* Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /* Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /* Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /* Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /* Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /* Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /* Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /* Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /* Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /* Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /* Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /* Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /* Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /* Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /* Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /* Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /* Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /* Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /* Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /* Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /* Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /* Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /* Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /* Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /* Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /* Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /* Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /* Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /* Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ + +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /* Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x0CF47FFFUL /* Mask for LESENSE_PERCTRL */ + +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 0) /* DAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 0 /* Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x1UL /* Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /* Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES 0x00000001UL /* Mode ACMPTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 0) /* Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES (_LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES << 0) /* Shifted mode ACMPTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 1) /* DAC CH1 data selection. */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 1 /* Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x2UL /* Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /* Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_ACMPTHRES 0x00000001UL /* Mode ACMPTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 1) /* Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_ACMPTHRES (_LESENSE_PERCTRL_DACCH1DATA_ACMPTHRES << 1) /* Shifted mode ACMPTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0CONV_SHIFT 2 /* Shift value for LESENSE_DACCH0CONV */ +#define _LESENSE_PERCTRL_DACCH0CONV_MASK 0xCUL /* Bit mask for LESENSE_DACCH0CONV */ +#define _LESENSE_PERCTRL_DACCH0CONV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0CONV_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0CONV_CONTINUOUS 0x00000001UL /* Mode CONTINUOUS for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0CONV_SAMPLEHOLD 0x00000002UL /* Mode SAMPLEHOLD for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF 0x00000003UL /* Mode SAMPLEOFF for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0CONV_DEFAULT (_LESENSE_PERCTRL_DACCH0CONV_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0CONV_DISABLE (_LESENSE_PERCTRL_DACCH0CONV_DISABLE << 2) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0CONV_CONTINUOUS (_LESENSE_PERCTRL_DACCH0CONV_CONTINUOUS << 2) /* Shifted mode CONTINUOUS for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0CONV_SAMPLEHOLD (_LESENSE_PERCTRL_DACCH0CONV_SAMPLEHOLD << 2) /* Shifted mode SAMPLEHOLD for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF (_LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF << 2) /* Shifted mode SAMPLEOFF for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1CONV_SHIFT 4 /* Shift value for LESENSE_DACCH1CONV */ +#define _LESENSE_PERCTRL_DACCH1CONV_MASK 0x30UL /* Bit mask for LESENSE_DACCH1CONV */ +#define _LESENSE_PERCTRL_DACCH1CONV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1CONV_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1CONV_CONTINUOUS 0x00000001UL /* Mode CONTINUOUS for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1CONV_SAMPLEHOLD 0x00000002UL /* Mode SAMPLEHOLD for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1CONV_SAMPLEOFF 0x00000003UL /* Mode SAMPLEOFF for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1CONV_DEFAULT (_LESENSE_PERCTRL_DACCH1CONV_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1CONV_DISABLE (_LESENSE_PERCTRL_DACCH1CONV_DISABLE << 4) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1CONV_CONTINUOUS (_LESENSE_PERCTRL_DACCH1CONV_CONTINUOUS << 4) /* Shifted mode CONTINUOUS for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1CONV_SAMPLEHOLD (_LESENSE_PERCTRL_DACCH1CONV_SAMPLEHOLD << 4) /* Shifted mode SAMPLEHOLD for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1CONV_SAMPLEOFF (_LESENSE_PERCTRL_DACCH1CONV_SAMPLEOFF << 4) /* Shifted mode SAMPLEOFF for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0OUT_SHIFT 6 /* Shift value for LESENSE_DACCH0OUT */ +#define _LESENSE_PERCTRL_DACCH0OUT_MASK 0xC0UL /* Bit mask for LESENSE_DACCH0OUT */ +#define _LESENSE_PERCTRL_DACCH0OUT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0OUT_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0OUT_PIN 0x00000001UL /* Mode PIN for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0OUT_ADCACMP 0x00000002UL /* Mode ADCACMP for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0OUT_PINADCACMP 0x00000003UL /* Mode PINADCACMP for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0OUT_DEFAULT (_LESENSE_PERCTRL_DACCH0OUT_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0OUT_DISABLE (_LESENSE_PERCTRL_DACCH0OUT_DISABLE << 6) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0OUT_PIN (_LESENSE_PERCTRL_DACCH0OUT_PIN << 6) /* Shifted mode PIN for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0OUT_ADCACMP (_LESENSE_PERCTRL_DACCH0OUT_ADCACMP << 6) /* Shifted mode ADCACMP for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0OUT_PINADCACMP (_LESENSE_PERCTRL_DACCH0OUT_PINADCACMP << 6) /* Shifted mode PINADCACMP for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1OUT_SHIFT 8 /* Shift value for LESENSE_DACCH1OUT */ +#define _LESENSE_PERCTRL_DACCH1OUT_MASK 0x300UL /* Bit mask for LESENSE_DACCH1OUT */ +#define _LESENSE_PERCTRL_DACCH1OUT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1OUT_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1OUT_PIN 0x00000001UL /* Mode PIN for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1OUT_ADCACMP 0x00000002UL /* Mode ADCACMP for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1OUT_PINADCACMP 0x00000003UL /* Mode PINADCACMP for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1OUT_DEFAULT (_LESENSE_PERCTRL_DACCH1OUT_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1OUT_DISABLE (_LESENSE_PERCTRL_DACCH1OUT_DISABLE << 8) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1OUT_PIN (_LESENSE_PERCTRL_DACCH1OUT_PIN << 8) /* Shifted mode PIN for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1OUT_ADCACMP (_LESENSE_PERCTRL_DACCH1OUT_ADCACMP << 8) /* Shifted mode ADCACMP for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1OUT_PINADCACMP (_LESENSE_PERCTRL_DACCH1OUT_PINADCACMP << 8) /* Shifted mode PINADCACMP for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACPRESC_SHIFT 10 /* Shift value for LESENSE_DACPRESC */ +#define _LESENSE_PERCTRL_DACPRESC_MASK 0x7C00UL /* Bit mask for LESENSE_DACPRESC */ +#define _LESENSE_PERCTRL_DACPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACPRESC_DEFAULT (_LESENSE_PERCTRL_DACPRESC_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACREF (0x1UL << 18) /* DAC bandgap reference used */ +#define _LESENSE_PERCTRL_DACREF_SHIFT 18 /* Shift value for LESENSE_DACREF */ +#define _LESENSE_PERCTRL_DACREF_MASK 0x40000UL /* Bit mask for LESENSE_DACREF */ +#define _LESENSE_PERCTRL_DACREF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACREF_VDD 0x00000000UL /* Mode VDD for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACREF_BANDGAP 0x00000001UL /* Mode BANDGAP for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACREF_DEFAULT (_LESENSE_PERCTRL_DACREF_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACREF_VDD (_LESENSE_PERCTRL_DACREF_VDD << 18) /* Shifted mode VDD for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACREF_BANDGAP (_LESENSE_PERCTRL_DACREF_BANDGAP << 18) /* Shifted mode BANDGAP for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /* Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /* Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /* Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /* Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /* Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /* Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /* Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /* Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /* Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /* Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /* Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /* Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /* Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 26 /* Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0xC000000UL /* Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /* Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /* Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /* Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /* Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 26) /* Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 26) /* Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 26) /* Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 26) /* Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 26) /* Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ + +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /* Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x03FFFDFFUL /* Mask for LESENSE_DECCTRL */ + +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /* Disable the decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /* Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /* Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /* Enable check of current state */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /* Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /* Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /* Enable decoder to channel interrupt mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /* Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /* Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /* Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /* Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /* Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /* Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /* Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /* Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /* Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /* Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /* Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /* Enable decoder hysteresis on interrupt requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /* Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /* Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /* Enable count mode on decoder PRS channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /* Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /* Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /* */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /* Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /* Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /* Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /* Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /* Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /* Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /* Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /* Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /* Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /* Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /* Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /* Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /* Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /* Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /* Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /* Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /* Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /* Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /* Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /* Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /* Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /* Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /* Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /* Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /* Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /* Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /* Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /* Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /* Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /* Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /* Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /* Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 14 /* Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x3C000UL /* Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /* Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /* Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /* Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /* Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /* Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /* Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /* Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /* Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /* Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /* Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /* Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /* Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 14) /* Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 14) /* Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 14) /* Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 14) /* Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 14) /* Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 14) /* Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 14) /* Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 14) /* Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 14) /* Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 14) /* Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 14) /* Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 14) /* Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 18 /* Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0x3C0000UL /* Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /* Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /* Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /* Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /* Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /* Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /* Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /* Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /* Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /* Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /* Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /* Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /* Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 18) /* Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 18) /* Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 18) /* Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 18) /* Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 18) /* Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 18) /* Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 18) /* Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 18) /* Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 18) /* Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 18) /* Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 18) /* Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 18) /* Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 22 /* Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x3C00000UL /* Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /* Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /* Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /* Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /* Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /* Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /* Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /* Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /* Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /* Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /* Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /* Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /* Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 22) /* Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 22) /* Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 22) /* Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 22) /* Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 22) /* Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 22) /* Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 22) /* Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 22) /* Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 22) /* Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 22) /* Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 22) /* Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 22) /* Shifted mode PRSCH11 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ + +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /* Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /* Mask for LESENSE_BIASCTRL */ + +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /* Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /* Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000000UL /* Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000001UL /* Mode HIGHACC for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000002UL /* Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /* Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /* Shifted mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /* Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE CMD */ + +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /* Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /* Mask for LESENSE_CMD */ + +#define LESENSE_CMD_START (0x1UL << 0) /* Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /* Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /* Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /* Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /* Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /* Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /* Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /* Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /* Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /* Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /* Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /* Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ + +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /* Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /* Mask for LESENSE_CHEN */ + +#define _LESENSE_CHEN_CHEN_SHIFT 0 /* Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /* Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ + +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /* Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0x0000FFFFUL /* Mask for LESENSE_SCANRES */ + +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /* Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /* Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ + +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /* Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /* Mask for LESENSE_STATUS */ + +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /* Result data valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /* Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /* Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /* Result buffer half full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /* Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /* Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /* Result buffer full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /* Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /* Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /* LESENSE is active */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /* Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /* Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /* LESENSE is currently interfacing sensors. */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /* Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /* Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /* LESENSE DAC interface is active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /* Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /* Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ + +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /* Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000001EFUL /* Mask for LESENSE_PTR */ + +#define _LESENSE_PTR_RD_SHIFT 0 /* Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /* Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 5 /* Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0x1E0UL /* Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ + +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /* Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x0000FFFFUL /* Mask for LESENSE_BUFDATA */ + +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /* Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /* Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ + +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /* Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /* Mask for LESENSE_CURCH */ + +#define _LESENSE_CURCH_CURCH_SHIFT 0 /* Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /* Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ + +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /* Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000000FUL /* Mask for LESENSE_DECSTATE */ + +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /* Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0xFUL /* Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ + +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /* Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /* Mask for LESENSE_SENSORSTATE */ + +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /* Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /* Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ + +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /* Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /* Mask for LESENSE_IDLECONF */ + +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /* Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /* Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DACCH0 0x00000003UL /* Mode DACCH0 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DACCH0 (_LESENSE_IDLECONF_CH0_DACCH0 << 0) /* Shifted mode DACCH0 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /* Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /* Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DACCH0 0x00000003UL /* Mode DACCH0 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DACCH0 (_LESENSE_IDLECONF_CH1_DACCH0 << 2) /* Shifted mode DACCH0 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /* Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /* Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DACCH0 0x00000003UL /* Mode DACCH0 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DACCH0 (_LESENSE_IDLECONF_CH2_DACCH0 << 4) /* Shifted mode DACCH0 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /* Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /* Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DACCH0 0x00000003UL /* Mode DACCH0 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DACCH0 (_LESENSE_IDLECONF_CH3_DACCH0 << 6) /* Shifted mode DACCH0 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /* Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /* Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /* Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /* Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /* Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /* Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /* Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /* Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /* Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /* Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /* Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /* Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /* Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /* Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /* Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /* Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /* Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /* Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DACCH1 0x00000003UL /* Mode DACCH1 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DACCH1 (_LESENSE_IDLECONF_CH12_DACCH1 << 24) /* Shifted mode DACCH1 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /* Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /* Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DACCH1 0x00000003UL /* Mode DACCH1 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DACCH1 (_LESENSE_IDLECONF_CH13_DACCH1 << 26) /* Shifted mode DACCH1 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /* Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /* Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DACCH1 0x00000003UL /* Mode DACCH1 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DACCH1 (_LESENSE_IDLECONF_CH14_DACCH1 << 28) /* Shifted mode DACCH1 for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /* Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /* Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /* Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /* Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DACCH1 0x00000003UL /* Mode DACCH1 for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /* Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /* Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /* Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /* Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DACCH1 (_LESENSE_IDLECONF_CH15_DACCH1 << 30) /* Shifted mode DACCH1 for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ + +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /* Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /* Mask for LESENSE_ALTEXCONF */ + +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /* Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /* Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /* Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /* Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /* Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /* Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /* Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /* Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /* Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /* Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /* Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /* Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /* Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /* Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /* Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /* Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /* Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /* Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /* Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /* Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /* Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /* ALTEX0 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /* Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /* Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /* ALTEX1 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /* Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /* Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /* ALTEX2 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /* Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /* Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /* ALTEX3 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /* Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /* Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /* ALTEX4 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /* Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /* Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /* ALTEX5 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /* Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /* Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /* ALTEX6 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /* Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /* Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /* ALTEX7 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /* Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /* Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /* Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ + +#define _LESENSE_IF_RESETVALUE 0x00000000UL /* Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /* Mask for LESENSE_IF */ + +#define LESENSE_IF_CH0 (0x1UL << 0) /* */ +#define _LESENSE_IF_CH0_SHIFT 0 /* Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /* Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /* */ +#define _LESENSE_IF_CH1_SHIFT 1 /* Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /* Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /* */ +#define _LESENSE_IF_CH2_SHIFT 2 /* Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /* Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /* */ +#define _LESENSE_IF_CH3_SHIFT 3 /* Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /* Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /* */ +#define _LESENSE_IF_CH4_SHIFT 4 /* Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /* Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /* */ +#define _LESENSE_IF_CH5_SHIFT 5 /* Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /* Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /* */ +#define _LESENSE_IF_CH6_SHIFT 6 /* Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /* Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /* */ +#define _LESENSE_IF_CH7_SHIFT 7 /* Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /* Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /* */ +#define _LESENSE_IF_CH8_SHIFT 8 /* Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /* Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /* */ +#define _LESENSE_IF_CH9_SHIFT 9 /* Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /* Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /* */ +#define _LESENSE_IF_CH10_SHIFT 10 /* Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /* Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /* */ +#define _LESENSE_IF_CH11_SHIFT 11 /* Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /* Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /* */ +#define _LESENSE_IF_CH12_SHIFT 12 /* Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /* Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /* */ +#define _LESENSE_IF_CH13_SHIFT 13 /* Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /* Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /* */ +#define _LESENSE_IF_CH14_SHIFT 14 /* Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /* Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /* */ +#define _LESENSE_IF_CH15_SHIFT 15 /* Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /* Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /* */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /* Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /* Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /* */ +#define _LESENSE_IF_DEC_SHIFT 17 /* Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /* Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /* */ +#define _LESENSE_IF_DECERR_SHIFT 18 /* Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /* Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /* */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /* Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /* Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /* */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /* Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /* Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /* */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /* Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /* Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /* */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /* Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /* Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFC */ + +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /* Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /* Mask for LESENSE_IFC */ + +#define LESENSE_IFC_CH0 (0x1UL << 0) /* */ +#define _LESENSE_IFC_CH0_SHIFT 0 /* Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /* Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /* */ +#define _LESENSE_IFC_CH1_SHIFT 1 /* Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /* Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /* */ +#define _LESENSE_IFC_CH2_SHIFT 2 /* Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /* Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /* */ +#define _LESENSE_IFC_CH3_SHIFT 3 /* Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /* Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /* */ +#define _LESENSE_IFC_CH4_SHIFT 4 /* Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /* Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /* */ +#define _LESENSE_IFC_CH5_SHIFT 5 /* Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /* Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /* */ +#define _LESENSE_IFC_CH6_SHIFT 6 /* Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /* Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /* */ +#define _LESENSE_IFC_CH7_SHIFT 7 /* Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /* Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /* */ +#define _LESENSE_IFC_CH8_SHIFT 8 /* Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /* Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /* */ +#define _LESENSE_IFC_CH9_SHIFT 9 /* Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /* Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /* */ +#define _LESENSE_IFC_CH10_SHIFT 10 /* Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /* Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /* */ +#define _LESENSE_IFC_CH11_SHIFT 11 /* Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /* Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /* */ +#define _LESENSE_IFC_CH12_SHIFT 12 /* Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /* Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /* */ +#define _LESENSE_IFC_CH13_SHIFT 13 /* Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /* Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /* */ +#define _LESENSE_IFC_CH14_SHIFT 14 /* Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /* Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /* */ +#define _LESENSE_IFC_CH15_SHIFT 15 /* Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /* Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /* */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /* Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /* Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /* */ +#define _LESENSE_IFC_DEC_SHIFT 17 /* Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /* Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /* */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /* Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /* Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /* */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /* Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /* Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /* */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /* Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /* Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /* */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /* Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /* Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /* */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /* Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /* Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IFS */ + +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /* Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /* Mask for LESENSE_IFS */ + +#define LESENSE_IFS_CH0 (0x1UL << 0) /* */ +#define _LESENSE_IFS_CH0_SHIFT 0 /* Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /* Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /* */ +#define _LESENSE_IFS_CH1_SHIFT 1 /* Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /* Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /* */ +#define _LESENSE_IFS_CH2_SHIFT 2 /* Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /* Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /* */ +#define _LESENSE_IFS_CH3_SHIFT 3 /* Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /* Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /* */ +#define _LESENSE_IFS_CH4_SHIFT 4 /* Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /* Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /* */ +#define _LESENSE_IFS_CH5_SHIFT 5 /* Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /* Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /* */ +#define _LESENSE_IFS_CH6_SHIFT 6 /* Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /* Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /* */ +#define _LESENSE_IFS_CH7_SHIFT 7 /* Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /* Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /* */ +#define _LESENSE_IFS_CH8_SHIFT 8 /* Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /* Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /* */ +#define _LESENSE_IFS_CH9_SHIFT 9 /* Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /* Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /* */ +#define _LESENSE_IFS_CH10_SHIFT 10 /* Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /* Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /* */ +#define _LESENSE_IFS_CH11_SHIFT 11 /* Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /* Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /* */ +#define _LESENSE_IFS_CH12_SHIFT 12 /* Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /* Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /* */ +#define _LESENSE_IFS_CH13_SHIFT 13 /* Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /* Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /* */ +#define _LESENSE_IFS_CH14_SHIFT 14 /* Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /* Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /* */ +#define _LESENSE_IFS_CH15_SHIFT 15 /* Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /* Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /* */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /* Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /* Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /* */ +#define _LESENSE_IFS_DEC_SHIFT 17 /* Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /* Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /* */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /* Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /* Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /* */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /* Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /* Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /* */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /* Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /* Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /* */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /* Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /* Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /* */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /* Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /* Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IEN */ + +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /* Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /* Mask for LESENSE_IEN */ + +#define LESENSE_IEN_CH0 (0x1UL << 0) /* */ +#define _LESENSE_IEN_CH0_SHIFT 0 /* Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /* Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /* */ +#define _LESENSE_IEN_CH1_SHIFT 1 /* Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /* Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /* */ +#define _LESENSE_IEN_CH2_SHIFT 2 /* Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /* Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /* */ +#define _LESENSE_IEN_CH3_SHIFT 3 /* Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /* Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /* */ +#define _LESENSE_IEN_CH4_SHIFT 4 /* Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /* Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /* */ +#define _LESENSE_IEN_CH5_SHIFT 5 /* Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /* Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /* */ +#define _LESENSE_IEN_CH6_SHIFT 6 /* Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /* Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /* */ +#define _LESENSE_IEN_CH7_SHIFT 7 /* Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /* Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /* */ +#define _LESENSE_IEN_CH8_SHIFT 8 /* Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /* Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /* */ +#define _LESENSE_IEN_CH9_SHIFT 9 /* Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /* Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /* */ +#define _LESENSE_IEN_CH10_SHIFT 10 /* Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /* Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /* */ +#define _LESENSE_IEN_CH11_SHIFT 11 /* Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /* Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /* */ +#define _LESENSE_IEN_CH12_SHIFT 12 /* Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /* Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /* */ +#define _LESENSE_IEN_CH13_SHIFT 13 /* Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /* Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /* */ +#define _LESENSE_IEN_CH14_SHIFT 14 /* Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /* Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /* */ +#define _LESENSE_IEN_CH15_SHIFT 15 /* Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /* Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /* */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /* Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /* Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /* */ +#define _LESENSE_IEN_DEC_SHIFT 17 /* Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /* Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /* */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /* Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /* Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /* */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /* Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /* Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /* */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /* Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /* Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /* */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /* Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /* Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /* */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /* Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /* Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ + +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x07E3FFFFUL /* Mask for LESENSE_SYNCBUSY */ + +#define LESENSE_SYNCBUSY_CTRL (0x1UL << 0) /* LESENSE_CTRL Register Busy */ +#define _LESENSE_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for LESENSE_CTRL */ +#define _LESENSE_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for LESENSE_CTRL */ +#define _LESENSE_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CTRL_DEFAULT (_LESENSE_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TIMCTRL (0x1UL << 1) /* LESENSE_TIMCTRL Register Busy */ +#define _LESENSE_SYNCBUSY_TIMCTRL_SHIFT 1 /* Shift value for LESENSE_TIMCTRL */ +#define _LESENSE_SYNCBUSY_TIMCTRL_MASK 0x2UL /* Bit mask for LESENSE_TIMCTRL */ +#define _LESENSE_SYNCBUSY_TIMCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TIMCTRL_DEFAULT (_LESENSE_SYNCBUSY_TIMCTRL_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_PERCTRL (0x1UL << 2) /* LESENSE_PERCTRL Register Busy */ +#define _LESENSE_SYNCBUSY_PERCTRL_SHIFT 2 /* Shift value for LESENSE_PERCTRL */ +#define _LESENSE_SYNCBUSY_PERCTRL_MASK 0x4UL /* Bit mask for LESENSE_PERCTRL */ +#define _LESENSE_SYNCBUSY_PERCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_PERCTRL_DEFAULT (_LESENSE_SYNCBUSY_PERCTRL_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DECCTRL (0x1UL << 3) /* LESENSE_DECCTRL Register Busy */ +#define _LESENSE_SYNCBUSY_DECCTRL_SHIFT 3 /* Shift value for LESENSE_DECCTRL */ +#define _LESENSE_SYNCBUSY_DECCTRL_MASK 0x8UL /* Bit mask for LESENSE_DECCTRL */ +#define _LESENSE_SYNCBUSY_DECCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DECCTRL_DEFAULT (_LESENSE_SYNCBUSY_DECCTRL_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_BIASCTRL (0x1UL << 4) /* LESENSE_BIASCTRL Register Busy */ +#define _LESENSE_SYNCBUSY_BIASCTRL_SHIFT 4 /* Shift value for LESENSE_BIASCTRL */ +#define _LESENSE_SYNCBUSY_BIASCTRL_MASK 0x10UL /* Bit mask for LESENSE_BIASCTRL */ +#define _LESENSE_SYNCBUSY_BIASCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_BIASCTRL_DEFAULT (_LESENSE_SYNCBUSY_BIASCTRL_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 5) /* LESENSE_CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 5 /* Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x20UL /* Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CHEN (0x1UL << 6) /* LESENSE_CHEN Register Busy */ +#define _LESENSE_SYNCBUSY_CHEN_SHIFT 6 /* Shift value for LESENSE_CHEN */ +#define _LESENSE_SYNCBUSY_CHEN_MASK 0x40UL /* Bit mask for LESENSE_CHEN */ +#define _LESENSE_SYNCBUSY_CHEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CHEN_DEFAULT (_LESENSE_SYNCBUSY_CHEN_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_SCANRES (0x1UL << 7) /* LESENSE_SCANRES Register Busy */ +#define _LESENSE_SYNCBUSY_SCANRES_SHIFT 7 /* Shift value for LESENSE_SCANRES */ +#define _LESENSE_SYNCBUSY_SCANRES_MASK 0x80UL /* Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SYNCBUSY_SCANRES_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_SCANRES_DEFAULT (_LESENSE_SYNCBUSY_SCANRES_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_STATUS (0x1UL << 8) /* LESENSE_STATUS Register Busy */ +#define _LESENSE_SYNCBUSY_STATUS_SHIFT 8 /* Shift value for LESENSE_STATUS */ +#define _LESENSE_SYNCBUSY_STATUS_MASK 0x100UL /* Bit mask for LESENSE_STATUS */ +#define _LESENSE_SYNCBUSY_STATUS_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_STATUS_DEFAULT (_LESENSE_SYNCBUSY_STATUS_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_PTR (0x1UL << 9) /* LESENSE_PTR Register Busy */ +#define _LESENSE_SYNCBUSY_PTR_SHIFT 9 /* Shift value for LESENSE_PTR */ +#define _LESENSE_SYNCBUSY_PTR_MASK 0x200UL /* Bit mask for LESENSE_PTR */ +#define _LESENSE_SYNCBUSY_PTR_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_PTR_DEFAULT (_LESENSE_SYNCBUSY_PTR_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_BUFDATA (0x1UL << 10) /* LESENSE_BUFDATA Register Busy */ +#define _LESENSE_SYNCBUSY_BUFDATA_SHIFT 10 /* Shift value for LESENSE_BUFDATA */ +#define _LESENSE_SYNCBUSY_BUFDATA_MASK 0x400UL /* Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_SYNCBUSY_BUFDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_BUFDATA_DEFAULT (_LESENSE_SYNCBUSY_BUFDATA_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CURCH (0x1UL << 11) /* LESENSE_CURCH Register Busy */ +#define _LESENSE_SYNCBUSY_CURCH_SHIFT 11 /* Shift value for LESENSE_CURCH */ +#define _LESENSE_SYNCBUSY_CURCH_MASK 0x800UL /* Bit mask for LESENSE_CURCH */ +#define _LESENSE_SYNCBUSY_CURCH_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CURCH_DEFAULT (_LESENSE_SYNCBUSY_CURCH_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DECSTATE (0x1UL << 12) /* LESENSE_DECSTATE Register Busy */ +#define _LESENSE_SYNCBUSY_DECSTATE_SHIFT 12 /* Shift value for LESENSE_DECSTATE */ +#define _LESENSE_SYNCBUSY_DECSTATE_MASK 0x1000UL /* Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_SYNCBUSY_DECSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DECSTATE_DEFAULT (_LESENSE_SYNCBUSY_DECSTATE_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_SENSORSTATE (0x1UL << 13) /* LESENSE_SENSORSTATE Register Busy */ +#define _LESENSE_SYNCBUSY_SENSORSTATE_SHIFT 13 /* Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SYNCBUSY_SENSORSTATE_MASK 0x2000UL /* Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SYNCBUSY_SENSORSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_SENSORSTATE_DEFAULT (_LESENSE_SYNCBUSY_SENSORSTATE_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_IDLECONF (0x1UL << 14) /* LESENSE_IDLECONF Register Busy */ +#define _LESENSE_SYNCBUSY_IDLECONF_SHIFT 14 /* Shift value for LESENSE_IDLECONF */ +#define _LESENSE_SYNCBUSY_IDLECONF_MASK 0x4000UL /* Bit mask for LESENSE_IDLECONF */ +#define _LESENSE_SYNCBUSY_IDLECONF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_IDLECONF_DEFAULT (_LESENSE_SYNCBUSY_IDLECONF_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_ALTEXCONF (0x1UL << 15) /* LESENSE_ALTEXCONF Register Busy */ +#define _LESENSE_SYNCBUSY_ALTEXCONF_SHIFT 15 /* Shift value for LESENSE_ALTEXCONF */ +#define _LESENSE_SYNCBUSY_ALTEXCONF_MASK 0x8000UL /* Bit mask for LESENSE_ALTEXCONF */ +#define _LESENSE_SYNCBUSY_ALTEXCONF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_ALTEXCONF_DEFAULT (_LESENSE_SYNCBUSY_ALTEXCONF_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_ROUTE (0x1UL << 16) /* LESENSE_ROUTE Register Busy */ +#define _LESENSE_SYNCBUSY_ROUTE_SHIFT 16 /* Shift value for LESENSE_ROUTE */ +#define _LESENSE_SYNCBUSY_ROUTE_MASK 0x10000UL /* Bit mask for LESENSE_ROUTE */ +#define _LESENSE_SYNCBUSY_ROUTE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_ROUTE_DEFAULT (_LESENSE_SYNCBUSY_ROUTE_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_POWERDOWN (0x1UL << 17) /* LESENSE_POWERDOWN Register Busy */ +#define _LESENSE_SYNCBUSY_POWERDOWN_SHIFT 17 /* Shift value for LESENSE_POWERDOWN */ +#define _LESENSE_SYNCBUSY_POWERDOWN_MASK 0x20000UL /* Bit mask for LESENSE_POWERDOWN */ +#define _LESENSE_SYNCBUSY_POWERDOWN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_POWERDOWN_DEFAULT (_LESENSE_SYNCBUSY_POWERDOWN_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TCONFA (0x1UL << 21) /* LESENSE_STx_TCONFA Register Busy */ +#define _LESENSE_SYNCBUSY_TCONFA_SHIFT 21 /* Shift value for LESENSE_TCONFA */ +#define _LESENSE_SYNCBUSY_TCONFA_MASK 0x200000UL /* Bit mask for LESENSE_TCONFA */ +#define _LESENSE_SYNCBUSY_TCONFA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TCONFA_DEFAULT (_LESENSE_SYNCBUSY_TCONFA_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TCONFB (0x1UL << 22) /* LESENSE_STx_TCONFB Register Busy */ +#define _LESENSE_SYNCBUSY_TCONFB_SHIFT 22 /* Shift value for LESENSE_TCONFB */ +#define _LESENSE_SYNCBUSY_TCONFB_MASK 0x400000UL /* Bit mask for LESENSE_TCONFB */ +#define _LESENSE_SYNCBUSY_TCONFB_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TCONFB_DEFAULT (_LESENSE_SYNCBUSY_TCONFB_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DATA (0x1UL << 23) /* LESENSE_BUFx_DATA Register Busy */ +#define _LESENSE_SYNCBUSY_DATA_SHIFT 23 /* Shift value for LESENSE_DATA */ +#define _LESENSE_SYNCBUSY_DATA_MASK 0x800000UL /* Bit mask for LESENSE_DATA */ +#define _LESENSE_SYNCBUSY_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_DATA_DEFAULT (_LESENSE_SYNCBUSY_DATA_DEFAULT << 23) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TIMING (0x1UL << 24) /* LESENSE_CHx_TIMING Register Busy */ +#define _LESENSE_SYNCBUSY_TIMING_SHIFT 24 /* Shift value for LESENSE_TIMING */ +#define _LESENSE_SYNCBUSY_TIMING_MASK 0x1000000UL /* Bit mask for LESENSE_TIMING */ +#define _LESENSE_SYNCBUSY_TIMING_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_TIMING_DEFAULT (_LESENSE_SYNCBUSY_TIMING_DEFAULT << 24) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_INTERACT (0x1UL << 25) /* LESENSE_CHx_INTERACT Register Busy */ +#define _LESENSE_SYNCBUSY_INTERACT_SHIFT 25 /* Shift value for LESENSE_INTERACT */ +#define _LESENSE_SYNCBUSY_INTERACT_MASK 0x2000000UL /* Bit mask for LESENSE_INTERACT */ +#define _LESENSE_SYNCBUSY_INTERACT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_INTERACT_DEFAULT (_LESENSE_SYNCBUSY_INTERACT_DEFAULT << 25) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_EVAL (0x1UL << 26) /* LESENSE_CHx_EVAL Register Busy */ +#define _LESENSE_SYNCBUSY_EVAL_SHIFT 26 /* Shift value for LESENSE_EVAL */ +#define _LESENSE_SYNCBUSY_EVAL_MASK 0x4000000UL /* Bit mask for LESENSE_EVAL */ +#define _LESENSE_SYNCBUSY_EVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_EVAL_DEFAULT (_LESENSE_SYNCBUSY_EVAL_DEFAULT << 26) /* Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTE */ + +#define _LESENSE_ROUTE_RESETVALUE 0x00000000UL /* Default value for LESENSE_ROUTE */ +#define _LESENSE_ROUTE_MASK 0x00FFFFFFUL /* Mask for LESENSE_ROUTE */ + +#define LESENSE_ROUTE_CH0PEN (0x1UL << 0) /* CH0 Pin Enable */ +#define _LESENSE_ROUTE_CH0PEN_SHIFT 0 /* Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTE_CH0PEN_MASK 0x1UL /* Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTE_CH0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH0PEN_DEFAULT (_LESENSE_ROUTE_CH0PEN_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH1PEN (0x1UL << 1) /* CH0 Pin Enable */ +#define _LESENSE_ROUTE_CH1PEN_SHIFT 1 /* Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTE_CH1PEN_MASK 0x2UL /* Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTE_CH1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH1PEN_DEFAULT (_LESENSE_ROUTE_CH1PEN_DEFAULT << 1) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH2PEN (0x1UL << 2) /* CH2 Pin Enable */ +#define _LESENSE_ROUTE_CH2PEN_SHIFT 2 /* Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTE_CH2PEN_MASK 0x4UL /* Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTE_CH2PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH2PEN_DEFAULT (_LESENSE_ROUTE_CH2PEN_DEFAULT << 2) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH3PEN (0x1UL << 3) /* CH3 Pin Enable */ +#define _LESENSE_ROUTE_CH3PEN_SHIFT 3 /* Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTE_CH3PEN_MASK 0x8UL /* Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTE_CH3PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH3PEN_DEFAULT (_LESENSE_ROUTE_CH3PEN_DEFAULT << 3) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH4PEN (0x1UL << 4) /* CH4 Pin Enable */ +#define _LESENSE_ROUTE_CH4PEN_SHIFT 4 /* Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTE_CH4PEN_MASK 0x10UL /* Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTE_CH4PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH4PEN_DEFAULT (_LESENSE_ROUTE_CH4PEN_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH5PEN (0x1UL << 5) /* CH5 Pin Enable */ +#define _LESENSE_ROUTE_CH5PEN_SHIFT 5 /* Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTE_CH5PEN_MASK 0x20UL /* Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTE_CH5PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH5PEN_DEFAULT (_LESENSE_ROUTE_CH5PEN_DEFAULT << 5) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH6PEN (0x1UL << 6) /* CH6 Pin Enable */ +#define _LESENSE_ROUTE_CH6PEN_SHIFT 6 /* Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTE_CH6PEN_MASK 0x40UL /* Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTE_CH6PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH6PEN_DEFAULT (_LESENSE_ROUTE_CH6PEN_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH7PEN (0x1UL << 7) /* CH7 Pin Enable */ +#define _LESENSE_ROUTE_CH7PEN_SHIFT 7 /* Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTE_CH7PEN_MASK 0x80UL /* Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTE_CH7PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH7PEN_DEFAULT (_LESENSE_ROUTE_CH7PEN_DEFAULT << 7) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH8PEN (0x1UL << 8) /* CH8 Pin Enable */ +#define _LESENSE_ROUTE_CH8PEN_SHIFT 8 /* Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTE_CH8PEN_MASK 0x100UL /* Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTE_CH8PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH8PEN_DEFAULT (_LESENSE_ROUTE_CH8PEN_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH9PEN (0x1UL << 9) /* CH9 Pin Enable */ +#define _LESENSE_ROUTE_CH9PEN_SHIFT 9 /* Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTE_CH9PEN_MASK 0x200UL /* Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTE_CH9PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH9PEN_DEFAULT (_LESENSE_ROUTE_CH9PEN_DEFAULT << 9) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH10PEN (0x1UL << 10) /* CH10 Pin Enable */ +#define _LESENSE_ROUTE_CH10PEN_SHIFT 10 /* Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTE_CH10PEN_MASK 0x400UL /* Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTE_CH10PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH10PEN_DEFAULT (_LESENSE_ROUTE_CH10PEN_DEFAULT << 10) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH11PEN (0x1UL << 11) /* CH11 Pin Enable */ +#define _LESENSE_ROUTE_CH11PEN_SHIFT 11 /* Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTE_CH11PEN_MASK 0x800UL /* Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTE_CH11PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH11PEN_DEFAULT (_LESENSE_ROUTE_CH11PEN_DEFAULT << 11) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH12PEN (0x1UL << 12) /* CH12 Pin Enable */ +#define _LESENSE_ROUTE_CH12PEN_SHIFT 12 /* Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTE_CH12PEN_MASK 0x1000UL /* Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTE_CH12PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH12PEN_DEFAULT (_LESENSE_ROUTE_CH12PEN_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH13PEN (0x1UL << 13) /* CH13 Pin Enable */ +#define _LESENSE_ROUTE_CH13PEN_SHIFT 13 /* Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTE_CH13PEN_MASK 0x2000UL /* Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTE_CH13PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH13PEN_DEFAULT (_LESENSE_ROUTE_CH13PEN_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH14PEN (0x1UL << 14) /* CH14 Pin Enable */ +#define _LESENSE_ROUTE_CH14PEN_SHIFT 14 /* Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTE_CH14PEN_MASK 0x4000UL /* Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTE_CH14PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH14PEN_DEFAULT (_LESENSE_ROUTE_CH14PEN_DEFAULT << 14) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH15PEN (0x1UL << 15) /* CH15 Pin Enable */ +#define _LESENSE_ROUTE_CH15PEN_SHIFT 15 /* Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTE_CH15PEN_MASK 0x8000UL /* Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTE_CH15PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_CH15PEN_DEFAULT (_LESENSE_ROUTE_CH15PEN_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX0PEN (0x1UL << 16) /* ALTEX0 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX0PEN_SHIFT 16 /* Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTE_ALTEX0PEN_MASK 0x10000UL /* Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTE_ALTEX0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX0PEN_DEFAULT (_LESENSE_ROUTE_ALTEX0PEN_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX1PEN (0x1UL << 17) /* ALTEX1 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX1PEN_SHIFT 17 /* Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTE_ALTEX1PEN_MASK 0x20000UL /* Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTE_ALTEX1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX1PEN_DEFAULT (_LESENSE_ROUTE_ALTEX1PEN_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX2PEN (0x1UL << 18) /* ALTEX2 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX2PEN_SHIFT 18 /* Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTE_ALTEX2PEN_MASK 0x40000UL /* Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTE_ALTEX2PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX2PEN_DEFAULT (_LESENSE_ROUTE_ALTEX2PEN_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX3PEN (0x1UL << 19) /* ALTEX3 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX3PEN_SHIFT 19 /* Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTE_ALTEX3PEN_MASK 0x80000UL /* Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTE_ALTEX3PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX3PEN_DEFAULT (_LESENSE_ROUTE_ALTEX3PEN_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX4PEN (0x1UL << 20) /* ALTEX4 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX4PEN_SHIFT 20 /* Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTE_ALTEX4PEN_MASK 0x100000UL /* Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTE_ALTEX4PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX4PEN_DEFAULT (_LESENSE_ROUTE_ALTEX4PEN_DEFAULT << 20) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX5PEN (0x1UL << 21) /* ALTEX5 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX5PEN_SHIFT 21 /* Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTE_ALTEX5PEN_MASK 0x200000UL /* Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTE_ALTEX5PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX5PEN_DEFAULT (_LESENSE_ROUTE_ALTEX5PEN_DEFAULT << 21) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX6PEN (0x1UL << 22) /* ALTEX6 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX6PEN_SHIFT 22 /* Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTE_ALTEX6PEN_MASK 0x400000UL /* Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTE_ALTEX6PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX6PEN_DEFAULT (_LESENSE_ROUTE_ALTEX6PEN_DEFAULT << 22) /* Shifted mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX7PEN (0x1UL << 23) /* ALTEX7 Pin Enable */ +#define _LESENSE_ROUTE_ALTEX7PEN_SHIFT 23 /* Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTE_ALTEX7PEN_MASK 0x800000UL /* Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTE_ALTEX7PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ROUTE */ +#define LESENSE_ROUTE_ALTEX7PEN_DEFAULT (_LESENSE_ROUTE_ALTEX7PEN_DEFAULT << 23) /* Shifted mode DEFAULT for LESENSE_ROUTE */ + +/* Bit fields for LESENSE POWERDOWN */ + +#define _LESENSE_POWERDOWN_RESETVALUE 0x00000000UL /* Default value for LESENSE_POWERDOWN */ +#define _LESENSE_POWERDOWN_MASK 0x00000001UL /* Mask for LESENSE_POWERDOWN */ + +#define LESENSE_POWERDOWN_RAM (0x1UL << 0) /* LESENSE RAM power-down */ +#define _LESENSE_POWERDOWN_RAM_SHIFT 0 /* Shift value for LESENSE_RAM */ +#define _LESENSE_POWERDOWN_RAM_MASK 0x1UL /* Bit mask for LESENSE_RAM */ +#define _LESENSE_POWERDOWN_RAM_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_POWERDOWN */ +#define LESENSE_POWERDOWN_RAM_DEFAULT (_LESENSE_POWERDOWN_RAM_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_POWERDOWN */ + +/* Bit fields for LESENSE ST_TCONFA */ + +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /* Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x00057FFFUL /* Mask for LESENSE_ST_TCONFA */ + +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /* Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /* Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /* Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /* Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /* Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0xF00UL /* Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 12 /* Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x7000UL /* Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /* Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /* Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /* Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /* Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /* Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /* Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /* Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /* Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /* Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /* Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /* Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /* Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 12) /* Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 12) /* Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 12) /* Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 12) /* Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 12) /* Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 12) /* Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 12) /* Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 12) /* Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 12) /* Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 12) /* Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 12) /* Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 12) /* Shifted mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 16) /* Set interrupt flag enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 16 /* Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x10000UL /* Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 18) /* Enable state descriptor chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 18 /* Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x40000UL /* Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ + +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /* Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00017FFFUL /* Mask for LESENSE_ST_TCONFB */ + +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /* Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /* Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /* Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /* Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /* Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /* Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0xF00UL /* Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /* Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 12 /* Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x7000UL /* Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /* Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /* Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /* Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /* Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /* Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /* Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /* Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /* Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /* Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /* Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /* Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /* Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 12) /* Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 12) /* Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 12) /* Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 12) /* Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 12) /* Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 12) /* Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 12) /* Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 12) /* Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 12) /* Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 12) /* Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 12) /* Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 12) /* Shifted mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 16) /* Set interrupt flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 16 /* Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x10000UL /* Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ + +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /* Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x0000FFFFUL /* Mask for LESENSE_BUF_DATA */ + +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /* Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /* Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ + +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /* Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x000FFFFFUL /* Mask for LESENSE_CH_TIMING */ + +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /* Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /* Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /* Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x1FC0UL /* Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /* Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 13 /* Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFE000UL /* Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ + +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /* Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x000FFFFFUL /* Mask for LESENSE_CH_INTERACT */ + +#define _LESENSE_CH_INTERACT_ACMPTHRES_SHIFT 0 /* Shift value for LESENSE_ACMPTHRES */ +#define _LESENSE_CH_INTERACT_ACMPTHRES_MASK 0xFFFUL /* Bit mask for LESENSE_ACMPTHRES */ +#define _LESENSE_CH_INTERACT_ACMPTHRES_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ACMPTHRES_DEFAULT (_LESENSE_CH_INTERACT_ACMPTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE (0x1UL << 12) /* Select sample mode */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /* Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x1000UL /* Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_COUNTER 0x00000000UL /* Mode COUNTER for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /* Mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_COUNTER (_LESENSE_CH_INTERACT_SAMPLE_COUNTER << 12) /* Shifted mode COUNTER for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /* Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 13 /* Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x6000UL /* Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /* Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /* Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /* Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /* Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 13) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 13) /* Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 13) /* Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 13) /* Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 13) /* Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 15 /* Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x18000UL /* Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /* Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /* Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /* Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /* Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 15) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 15) /* Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 15) /* Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 15) /* Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 15) /* Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 17) /* Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 17 /* Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x20000UL /* Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /* Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /* Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 17) /* Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 17) /* Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 18) /* Select clock used for timing of sample delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 18 /* Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x40000UL /* Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /* Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /* Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 18) /* Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 18) /* Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 19) /* Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 19 /* Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x80000UL /* Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ + +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /* Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x000FFFFFUL /* Mask for LESENSE_CH_EVAL */ + +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /* Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /* Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /* Select mode for counter comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /* Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /* Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /* Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /* Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /* Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /* Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /* Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /* Send result to decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /* Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /* Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /* Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE (0x1UL << 18) /* Select if counter result should be stored */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /* Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0x40000UL /* Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /* Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 19) /* Enable inversion of result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 19 /* Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x80000UL /* Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /* Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 19) /* Shifted mode DEFAULT for LESENSE_CH_EVAL */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LESENSE_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_letimer.h b/nuttx/arch/arm/src/efm32/chip/efm32_letimer.h new file mode 100644 index 000000000..3b877d448 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_letimer.h @@ -0,0 +1,488 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_letimer.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* LETIMER Register Offsets ****************************************************************************************************/ + +#define EFM32_LETIMER_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_LETIMER_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_LETIMER_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_LETIMER_CNT_OFFSET 0x000c /* Counter Value Register */ +#define EFM32_LETIMER_COMP0_OFFSET 0x0010 /* Compare Value Register */ 0 +#define EFM32_LETIMER_COMP1_OFFSET 0x0014 /* Compare Value Register */ 1 +#define EFM32_LETIMER_REP0_OFFSET 0x0018 /* Repeat Counter Register 0 */ +#define EFM32_LETIMER_REP1_OFFSET 0x001c /* Repeat Counter Register 1 */ +#define EFM32_LETIMER_IF_OFFSET 0x0020 /* Interrupt Flag Register */ +#define EFM32_LETIMER_IFS_OFFSET 0x0024 /* Interrupt Flag Set Register */ +#define EFM32_LETIMER_IFC_OFFSET 0x0028 /* Interrupt Flag Clear Register */ +#define EFM32_LETIMER_IEN_OFFSET 0x002c /* Interrupt Enable Register */ +#define EFM32_LETIMER_FREEZE_OFFSET 0x0030 /* Freeze Register */ +#define EFM32_LETIMER_SYNCBUSY_OFFSET 0x0034 /* Synchronization Busy Register */ +#define EFM32_LETIMER_ROUTE_OFFSET 0x0040 /* I/O Routing Register */ + +/* LETIMER Register Addresses **************************************************************************************************/ + +#define EFM32_LETIMER0_CTRL (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CTRL_OFFSET) +#define EFM32_LETIMER0_CMD (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CMD_OFFSET) +#define EFM32_LETIMER0_STATUS (EFM32_LETIMER0_BASE+EFM32_LETIMER0_STATUS_OFFSET) +#define EFM32_LETIMER0_CNT (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CNT_OFFSET) +#define EFM32_LETIMER0_COMP0 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_COMP0_OFFSET) +#define EFM32_LETIMER0_COMP1 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_COMP1_OFFSET) +#define EFM32_LETIMER0_REP0 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_REP0_OFFSET) +#define EFM32_LETIMER0_REP1 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_REP1_OFFSET) +#define EFM32_LETIMER0_IF (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IF_OFFSET) +#define EFM32_LETIMER0_IFS (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IFS_OFFSET) +#define EFM32_LETIMER0_IFC (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IFC_OFFSET) +#define EFM32_LETIMER0_IEN (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IEN_OFFSET) +#define EFM32_LETIMER0_FREEZE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_FREEZE_OFFSET) +#define EFM32_LETIMER0_SYNCBUSY (EFM32_LETIMER0_BASE+EFM32_LETIMER0_SYNCBUSY_OFFSET) +#define EFM32_LETIMER0_ROUTE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_ROUTE_OFFSET) + +/* LETIMER Register Bit Field Definitions **************************************************************************************/ + +/* Bit fields for LETIMER CTRL */ + +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /* Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x00001FFFUL /* Mask for LETIMER_CTRL */ + +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /* Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /* Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /* Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /* Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /* Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /* Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /* Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /* Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /* Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /* Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /* Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /* Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /* Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /* Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /* Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /* Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /* Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /* Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /* Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /* Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /* Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /* Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /* Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /* Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /* Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /* Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /* Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /* Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /* Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /* Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /* Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /* Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /* Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /* Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /* Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /* Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /* Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /* Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /* Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /* Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /* Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /* Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC0TEN (0x1UL << 10) /* RTC Compare 0 Trigger Enable */ +#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /* Shift value for LETIMER_RTCC0TEN */ +#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /* Bit mask for LETIMER_RTCC0TEN */ +#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC1TEN (0x1UL << 11) /* RTC Compare 1 Trigger Enable */ +#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /* Shift value for LETIMER_RTCC1TEN */ +#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /* Bit mask for LETIMER_RTCC1TEN */ +#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11) /* Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /* Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /* Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /* Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /* Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ + +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /* Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /* Mask for LETIMER_CMD */ + +#define LETIMER_CMD_START (0x1UL << 0) /* Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /* Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /* Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /* Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /* Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /* Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /* Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /* Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /* Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /* Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /* Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /* Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /* Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /* Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /* Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ + +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /* Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /* Mask for LETIMER_STATUS */ + +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /* LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /* Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /* Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ + +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /* Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /* Mask for LETIMER_CNT */ + +#define _LETIMER_CNT_CNT_SHIFT 0 /* Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /* Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ + +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /* Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /* Mask for LETIMER_COMP0 */ + +#define _LETIMER_COMP0_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ + +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /* Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /* Mask for LETIMER_COMP1 */ + +#define _LETIMER_COMP1_COMP1_SHIFT 0 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ + +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /* Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /* Mask for LETIMER_REP0 */ + +#define _LETIMER_REP0_REP0_SHIFT 0 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ + +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /* Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /* Mask for LETIMER_REP1 */ + +#define _LETIMER_REP1_REP1_SHIFT 0 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ + +#define _LETIMER_IF_RESETVALUE 0x00000000UL /* Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /* Mask for LETIMER_IF */ + +#define LETIMER_IF_COMP0 (0x1UL << 0) /* Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /* Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /* Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /* Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /* Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /* Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ + +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /* Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /* Mask for LETIMER_IFS */ + +#define LETIMER_IFS_COMP0 (0x1UL << 0) /* Set Compare Match 0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /* Set Compare Match 1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /* Set Underflow Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /* Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /* Set Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /* Set Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ + +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /* Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /* Mask for LETIMER_IFC */ + +#define LETIMER_IFC_COMP0 (0x1UL << 0) /* Clear Compare Match 0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /* Clear Compare Match 1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /* Clear Underflow Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /* Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /* Clear Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /* Clear Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ + +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /* Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /* Mask for LETIMER_IEN */ + +#define LETIMER_IEN_COMP0 (0x1UL << 0) /* Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /* Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /* Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /* Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /* Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /* Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER FREEZE */ + +#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /* Default value for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_MASK 0x00000001UL /* Mask for LETIMER_FREEZE */ + +#define LETIMER_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */ +#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for LETIMER_REGFREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for LETIMER_REGFREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for LETIMER_FREEZE */ +#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for LETIMER_FREEZE */ + +/* Bit fields for LETIMER SYNCBUSY */ + +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /* Mask for LETIMER_SYNCBUSY */ + +#define LETIMER_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */ +#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for LETIMER_CTRL */ +#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for LETIMER_CTRL */ +#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /* CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /* Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /* Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP0 (0x1UL << 2) /* COMP0 Register Busy */ +#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /* Shift value for LETIMER_COMP0 */ +#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /* Bit mask for LETIMER_COMP0 */ +#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP1 (0x1UL << 3) /* COMP1 Register Busy */ +#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /* Shift value for LETIMER_COMP1 */ +#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /* Bit mask for LETIMER_COMP1 */ +#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 4) /* REP0 Register Busy */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /* Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /* Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 5) /* REP1 Register Busy */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /* Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /* Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTE */ + +#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /* Default value for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_MASK 0x00000703UL /* Mask for LETIMER_ROUTE */ + +#define LETIMER_ROUTE_OUT0PEN (0x1UL << 0) /* Output 0 Pin Enable */ +#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /* Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /* Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_OUT1PEN (0x1UL << 1) /* Output 1 Pin Enable */ +#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /* Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /* Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /* Shift value for LETIMER_LOCATION */ +#define _LETIMER_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for LETIMER_LOCATION */ +#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for LETIMER_ROUTE */ +#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /* Mode LOC3 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /* Shifted mode LOC3 for LETIMER_ROUTE */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_leuart.h b/nuttx/arch/arm/src/efm32/chip/efm32_leuart.h index 421689505..be5b1bc0d 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_leuart.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_leuart.h @@ -68,6 +68,10 @@ #include <nuttx/config.h> #include "chip/efm32_memorymap.h" +#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G) +# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture +#endif + /******************************************************************************************************************************* * Pre-processor Definitions *******************************************************************************************************************************/ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_pcnt.h b/nuttx/arch/arm/src/efm32/chip/efm32_pcnt.h new file mode 100644 index 000000000..e9947f5ba --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_pcnt.h @@ -0,0 +1,529 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_pcnt.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* PCNT Register Offsets *******************************************************************************************************/ + +#define EFM32_PCNT_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_PCNT_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_PCNT_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_PCNT_CNT_OFFSET 0x000c /* Counter Value Register */ +#define EFM32_PCNT_TOP_OFFSET 0x0010 /* Top Value Register */ +#define EFM32_PCNT_TOPB_OFFSET 0x0014 /* Top Value Buffer Register */ +#define EFM32_PCNT_IF_OFFSET 0x0018 /* Interrupt Flag Register */ +#define EFM32_PCNT_IFS_OFFSET 0x001c /* Interrupt Flag Set Register */ +#define EFM32_PCNT_IFC_OFFSET 0x0020 /* Interrupt Flag Clear Register */ +#define EFM32_PCNT_IEN_OFFSET 0x0024 /* Interrupt Enable Register */ +#define EFM32_PCNT_ROUTE_OFFSET 0x0028 /* I/O Routing Register */ +#define EFM32_PCNT_FREEZE_OFFSET 0x002c /* Freeze Register */ +#define EFM32_PCNT_SYNCBUSY_OFFSET 0x0030 /* Synchronization Busy Register */ +#define EFM32_PCNT_AUXCNT_OFFSET 0x0038 /* Auxillary Counter Value Register */ +#define EFM32_PCNT_INPUT_OFFSET 0x003c /* PCNT Input Register */ + +/* PCNT Register Addresses *****************************************************************************************************/ + +#define EFM32_PCNT0_CTRL (EFM32_PCNT0_BASE+EFM32_PCNT_CTRL_OFFSET) +#define EFM32_PCNT0_CMD (EFM32_PCNT0_BASE+EFM32_PCNT_CMD_OFFSET) +#define EFM32_PCNT0_STATUS (EFM32_PCNT0_BASE+EFM32_PCNT_STATUS_OFFSET) +#define EFM32_PCNT0_CNT (EFM32_PCNT0_BASE+EFM32_PCNT_CNT_OFFSET) +#define EFM32_PCNT0_TOP (EFM32_PCNT0_BASE+EFM32_PCNT_TOP_OFFSET) +#define EFM32_PCNT0_TOPB (EFM32_PCNT0_BASE+EFM32_PCNT_TOPB_OFFSET) +#define EFM32_PCNT0_IF (EFM32_PCNT0_BASE+EFM32_PCNT_IF_OFFSET) +#define EFM32_PCNT0_IFS (EFM32_PCNT0_BASE+EFM32_PCNT_IFS_OFFSET) +#define EFM32_PCNT0_IFC (EFM32_PCNT0_BASE+EFM32_PCNT_IFC_OFFSET) +#define EFM32_PCNT0_IEN (EFM32_PCNT0_BASE+EFM32_PCNT_IEN_OFFSET) +#define EFM32_PCNT0_ROUTE (EFM32_PCNT0_BASE+EFM32_PCNT_ROUTE_OFFSET) +#define EFM32_PCNT0_FREEZE (EFM32_PCNT0_BASE+EFM32_PCNT_FREEZE_OFFSET) +#define EFM32_PCNT0_SYNCBUSY (EFM32_PCNT0_BASE+EFM32_PCNT_SYNCBUSY_OFFSET) +#define EFM32_PCNT0_AUXCNT (EFM32_PCNT0_BASE+EFM32_PCNT_AUXCNT_OFFSET) +#define EFM32_PCNT0_INPUT (EFM32_PCNT0_BASE+EFM32_PCNT_INPUT_OFFSET) + +#define EFM32_PCNT1_CTRL (EFM32_PCNT1_BASE+EFM32_PCNT_CTRL_OFFSET) +#define EFM32_PCNT1_CMD (EFM32_PCNT1_BASE+EFM32_PCNT_CMD_OFFSET) +#define EFM32_PCNT1_STATUS (EFM32_PCNT1_BASE+EFM32_PCNT_STATUS_OFFSET) +#define EFM32_PCNT1_CNT (EFM32_PCNT1_BASE+EFM32_PCNT_CNT_OFFSET) +#define EFM32_PCNT1_TOP (EFM32_PCNT1_BASE+EFM32_PCNT_TOP_OFFSET) +#define EFM32_PCNT1_TOPB (EFM32_PCNT1_BASE+EFM32_PCNT_TOPB_OFFSET) +#define EFM32_PCNT1_IF (EFM32_PCNT1_BASE+EFM32_PCNT_IF_OFFSET) +#define EFM32_PCNT1_IFS (EFM32_PCNT1_BASE+EFM32_PCNT_IFS_OFFSET) +#define EFM32_PCNT1_IFC (EFM32_PCNT1_BASE+EFM32_PCNT_IFC_OFFSET) +#define EFM32_PCNT1_IEN (EFM32_PCNT1_BASE+EFM32_PCNT_IEN_OFFSET) +#define EFM32_PCNT1_ROUTE (EFM32_PCNT1_BASE+EFM32_PCNT_ROUTE_OFFSET) +#define EFM32_PCNT1_FREEZE (EFM32_PCNT1_BASE+EFM32_PCNT_FREEZE_OFFSET) +#define EFM32_PCNT1_SYNCBUSY (EFM32_PCNT1_BASE+EFM32_PCNT_SYNCBUSY_OFFSET) +#define EFM32_PCNT1_AUXCNT (EFM32_PCNT1_BASE+EFM32_PCNT_AUXCNT_OFFSET) +#define EFM32_PCNT1_INPUT (EFM32_PCNT1_BASE+EFM32_PCNT_INPUT_OFFSET) + +#define EFM32_PCNT2_CTRL (EFM32_PCNT2_BASE+EFM32_PCNT_CTRL_OFFSET) +#define EFM32_PCNT2_CMD (EFM32_PCNT2_BASE+EFM32_PCNT_CMD_OFFSET) +#define EFM32_PCNT2_STATUS (EFM32_PCNT2_BASE+EFM32_PCNT_STATUS_OFFSET) +#define EFM32_PCNT2_CNT (EFM32_PCNT2_BASE+EFM32_PCNT_CNT_OFFSET) +#define EFM32_PCNT2_TOP (EFM32_PCNT2_BASE+EFM32_PCNT_TOP_OFFSET) +#define EFM32_PCNT2_TOPB (EFM32_PCNT2_BASE+EFM32_PCNT_TOPB_OFFSET) +#define EFM32_PCNT2_IF (EFM32_PCNT2_BASE+EFM32_PCNT_IF_OFFSET) +#define EFM32_PCNT2_IFS (EFM32_PCNT2_BASE+EFM32_PCNT_IFS_OFFSET) +#define EFM32_PCNT2_IFC (EFM32_PCNT2_BASE+EFM32_PCNT_IFC_OFFSET) +#define EFM32_PCNT2_IEN (EFM32_PCNT2_BASE+EFM32_PCNT_IEN_OFFSET) +#define EFM32_PCNT2_ROUTE (EFM32_PCNT2_BASE+EFM32_PCNT_ROUTE_OFFSET) +#define EFM32_PCNT2_FREEZE (EFM32_PCNT2_BASE+EFM32_PCNT_FREEZE_OFFSET) +#define EFM32_PCNT2_SYNCBUSY (EFM32_PCNT2_BASE+EFM32_PCNT_SYNCBUSY_OFFSET) +#define EFM32_PCNT2_AUXCNT (EFM32_PCNT2_BASE+EFM32_PCNT_AUXCNT_OFFSET) +#define EFM32_PCNT2_INPUT (EFM32_PCNT2_BASE+EFM32_PCNT_INPUT_OFFSET) + +/* PCNT Register Bit Field Definitions *****************************************************************************************/ + +/* Bit fields for PCNT CTRL */ + +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /* Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x0000CF3FUL /* Mask for PCNT_CTRL */ + +#define _PCNT_CTRL_MODE_SHIFT 0 /* Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x3UL /* Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /* Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /* Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /* Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /* Mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /* Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /* Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /* Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /* Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 2) /* Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 2 /* Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4UL /* Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /* Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /* Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2) /* Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2) /* Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 3) /* Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 3 /* Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8UL /* Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /* Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /* Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3) /* Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3) /* Shifted mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 4) /* Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 4 /* Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x10UL /* Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 5) /* Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 5 /* Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x20UL /* Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /* Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /* Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /* Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /* Count direction determined by S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /* Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /* Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /* Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /* Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /* Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /* Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /* Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /* Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /* Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /* Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /* Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /* Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 14 /* Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0xC000UL /* Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /* Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /* Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /* Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /* Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 14) /* Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 14) /* Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 14) /* Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 14) /* Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 14) /* Shifted mode BOTH for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ + +#define _PCNT_CMD_RESETVALUE 0x00000000UL /* Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /* Mask for PCNT_CMD */ + +#define PCNT_CMD_LCNTIM (0x1UL << 0) /* Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /* Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /* Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /* Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /* Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /* Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ + +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /* Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /* Mask for PCNT_STATUS */ + +#define PCNT_STATUS_DIR (0x1UL << 0) /* Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /* Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /* Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /* Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /* Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /* Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /* Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ + +#define _PCNT_CNT_RESETVALUE 0x00000000UL /* Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /* Mask for PCNT_CNT */ + +#define _PCNT_CNT_CNT_SHIFT 0 /* Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /* Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ + +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /* Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /* Mask for PCNT_TOP */ + +#define _PCNT_TOP_TOP_SHIFT 0 /* Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /* Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /* Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ + +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /* Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /* Mask for PCNT_TOPB */ + +#define _PCNT_TOPB_TOPB_SHIFT 0 /* Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /* Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /* Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ + +#define _PCNT_IF_RESETVALUE 0x00000000UL /* Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000000FUL /* Mask for PCNT_IF */ + +#define PCNT_IF_UF (0x1UL << 0) /* Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /* Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /* Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /* Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /* Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /* Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /* Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /* Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /* Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /* Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /* Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /* Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /* Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ + +#define _PCNT_IFS_RESETVALUE 0x00000000UL /* Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000000FUL /* Mask for PCNT_IFS */ + +#define PCNT_IFS_UF (0x1UL << 0) /* Underflow interrupt set */ +#define _PCNT_IFS_UF_SHIFT 0 /* Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /* Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /* Overflow Interrupt Set */ +#define _PCNT_IFS_OF_SHIFT 1 /* Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /* Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /* Direction Change Detect Interrupt Set */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /* Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /* Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /* Auxiliary Overflow Interrupt Set */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /* Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /* Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /* Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ + +#define _PCNT_IFC_RESETVALUE 0x00000000UL /* Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000000FUL /* Mask for PCNT_IFC */ + +#define PCNT_IFC_UF (0x1UL << 0) /* Underflow Interrupt Clear */ +#define _PCNT_IFC_UF_SHIFT 0 /* Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /* Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /* Overflow Interrupt Clear */ +#define _PCNT_IFC_OF_SHIFT 1 /* Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /* Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /* Direction Change Detect Interrupt Clear */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /* Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /* Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /* Auxiliary Overflow Interrupt Clear */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /* Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /* Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /* Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ + +#define _PCNT_IEN_RESETVALUE 0x00000000UL /* Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000000FUL /* Mask for PCNT_IEN */ + +#define PCNT_IEN_UF (0x1UL << 0) /* Underflow Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /* Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /* Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /* Overflow Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /* Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /* Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /* Direction Change Detect Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /* Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /* Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /* Auxiliary Overflow Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /* Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /* Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /* Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTE */ + +#define _PCNT_ROUTE_RESETVALUE 0x00000000UL /* Default value for PCNT_ROUTE */ +#define _PCNT_ROUTE_MASK 0x00000700UL /* Mask for PCNT_ROUTE */ + +#define _PCNT_ROUTE_LOCATION_SHIFT 8 /* Shift value for PCNT_LOCATION */ +#define _PCNT_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for PCNT_LOCATION */ +#define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for PCNT_ROUTE */ +#define _PCNT_ROUTE_LOCATION_LOC3 0x00000003UL /* Mode LOC3 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for PCNT_ROUTE */ +#define PCNT_ROUTE_LOCATION_LOC3 (_PCNT_ROUTE_LOCATION_LOC3 << 8) /* Shifted mode LOC3 for PCNT_ROUTE */ + +/* Bit fields for PCNT FREEZE */ + +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /* Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /* Mask for PCNT_FREEZE */ + +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ + +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x00000007UL /* Mask for PCNT_SYNCBUSY */ + +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /* CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /* Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /* Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /* Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /* TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /* Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /* Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /* Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ + +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /* Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /* Mask for PCNT_AUXCNT */ + +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /* Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /* Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ + +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /* Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x000007DFUL /* Mask for PCNT_INPUT */ + +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /* Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /* Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /* Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /* Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /* Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /* Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /* Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /* Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /* Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /* Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /* Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /* Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /* Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /* Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 4) /* S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 4 /* Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x10UL /* Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 4) /* Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /* Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /* Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /* Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /* Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /* Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /* Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /* Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /* Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /* Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /* Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /* Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /* Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /* Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /* Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /* Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 10) /* S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 10 /* Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x400UL /* Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /* Shifted mode DEFAULT for PCNT_INPUT */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PCNT_H*/ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_prs.h b/nuttx/arch/arm/src/efm32/chip/efm32_prs.h new file mode 100644 index 000000000..b0d8d6e01 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_prs.h @@ -0,0 +1,610 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_prs.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* PRS Register Offsets ********************************************************************************************************/ + +#define EFM32_PRS_SWPULSE_OFFSET 0x0000 /* Software Pulse Register */ +#define EFM32_PRS_SWLEVEL_OFFSET 0x0004 /* Software Level Register */ +#define EFM32_PRS_ROUTE_OFFSET 0x0008 /* I/O Routing Register + +#define EFM32_PRS_CH_CTRL_OFFSET(n) (0x0010 + ((n) << 2)) +#define EFM32_PRS_CH0_CTRL_OFFSET 0x0010 /* Channel 0 Control Register */ +#define EFM32_PRS_CH1_CTRL_OFFSET 0x0014 /* Channel 1 Control Register */ +#define EFM32_PRS_CH2_CTRL_OFFSET 0x0018 /* Channel 2 Control Register */ +#define EFM32_PRS_CH3_CTRL_OFFSET 0x001c /* Channel 3 Control Register */ +#define EFM32_PRS_CH4_CTRL_OFFSET 0x0010 /* Channel 4 Control Register */ +#define EFM32_PRS_CH5_CTRL_OFFSET 0x0014 /* Channel 5 Control Register */ +#define EFM32_PRS_CH6_CTRL_OFFSET 0x0018 /* Channel 6 Control Register */ +#define EFM32_PRS_CH7_CTRL_OFFSET 0x001c /* Channel 7 Control Register */ +#define EFM32_PRS_CH8_CTRL_OFFSET 0x0010 /* Channel 8 Control Register */ +#define EFM32_PRS_CH9_CTRL_OFFSET 0x0014 /* Channel 9 Control Register */ +#define EFM32_PRS_CH10_CTRL_OFFSET 0x0018 /* Channel 10 Control Register */ +#define EFM32_PRS_CH11_CTRL_OFFSET 0x003c /* Channel 11 Control Register */ + +/* PRS Register Addresses ******************************************************************************************************/ + +#define EFM32_PRS_SWPULSE (EFM32_PRS_BASE+EFM32_PRS_SWPULSE_OFFSET) +#define EFM32_PRS_SWLEVEL (EFM32_PRS_BASE+EFM32_PRS_SWLEVEL_OFFSET) +#define EFM32_PRS_ROUTE (EFM32_PRS_BASE+EFM32_PRS_ROUTE_OFFSET) + +#define EFM32_PRS_CH_CTRL(n) (EFM32_PRS_BASE+EFM32_PRS_CH_CTRL_OFFSET(n)) +#define EFM32_PRS_CH0_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH0_CTRL_OFFSET) +#define EFM32_PRS_CH1_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH1_CTRL_OFFSET) +#define EFM32_PRS_CH2_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH2_CTRL_OFFSET) +#define EFM32_PRS_CH3_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH3_CTRL_OFFSET) +#define EFM32_PRS_CH4_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH4_CTRL_OFFSET) +#define EFM32_PRS_CH5_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH5_CTRL_OFFSET) +#define EFM32_PRS_CH6_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH6_CTRL_OFFSET) +#define EFM32_PRS_CH7_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH7_CTRL_OFFSET) +#define EFM32_PRS_CH8_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH8_CTRL_OFFSET) +#define EFM32_PRS_CH9_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH9_CTRL_OFFSET) +#define EFM32_PRS_CH10_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH10_CTRL_OFFSET) +#define EFM32_PRS_CH11_CTRL (EFM32_PRS_BASE+EFM32_PRS_CH11_CTRL_OFFSET) + +/* PRS Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for PRS SWPULSE */ + +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /* Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00000FFFUL /* Mask for PRS_SWPULSE */ + +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /* Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /* Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /* Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /* Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /* Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /* Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /* Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /* Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /* Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /* Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /* Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /* Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /* Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /* Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /* Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /* Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /* Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /* Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /* Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /* Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /* Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /* Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /* Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /* Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /* Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /* Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /* Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /* Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /* Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /* Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /* Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /* Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /* Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /* Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /* Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /* Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /* Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /* Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ + +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /* Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00000FFFUL /* Mask for PRS_SWLEVEL */ + +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /* Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /* Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /* Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /* Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /* Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /* Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /* Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /* Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /* Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /* Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /* Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /* Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /* Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /* Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /* Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /* Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /* Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /* Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /* Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /* Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /* Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /* Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /* Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /* Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /* Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /* Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /* Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /* Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /* Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /* Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /* Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /* Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /* Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /* Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /* Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /* Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /* Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /* Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTE */ + +#define _PRS_ROUTE_RESETVALUE 0x00000000UL /* Default value for PRS_ROUTE */ +#define _PRS_ROUTE_MASK 0x0000070FUL /* Mask for PRS_ROUTE */ + +#define PRS_ROUTE_CH0PEN (0x1UL << 0) /* CH0 Pin Enable */ +#define _PRS_ROUTE_CH0PEN_SHIFT 0 /* Shift value for PRS_CH0PEN */ +#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /* Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /* Shifted mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH1PEN (0x1UL << 1) /* CH1 Pin Enable */ +#define _PRS_ROUTE_CH1PEN_SHIFT 1 /* Shift value for PRS_CH1PEN */ +#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /* Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /* Shifted mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH2PEN (0x1UL << 2) /* CH2 Pin Enable */ +#define _PRS_ROUTE_CH2PEN_SHIFT 2 /* Shift value for PRS_CH2PEN */ +#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /* Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /* Shifted mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH3PEN (0x1UL << 3) /* CH3 Pin Enable */ +#define _PRS_ROUTE_CH3PEN_SHIFT 3 /* Shift value for PRS_CH3PEN */ +#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /* Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /* Shifted mode DEFAULT for PRS_ROUTE */ +#define _PRS_ROUTE_LOCATION_SHIFT 8 /* Shift value for PRS_LOCATION */ +#define _PRS_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for PRS_LOCATION */ +#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for PRS_ROUTE */ +#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_ROUTE */ +#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for PRS_ROUTE */ +#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for PRS_ROUTE */ +#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for PRS_ROUTE */ +#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for PRS_ROUTE */ + +/* Bit fields for PRS CH_CTRL */ + +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /* Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x133F0007UL /* Mask for PRS_CH_CTRL */ + +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /* Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /* Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /* Mode VCMPOUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /* Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /* Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /* Mode DAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /* Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /* Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /* Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /* Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /* Mode TIMER2UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /* Mode TIMER3UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /* Mode USBSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /* Mode RTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /* Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /* Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /* Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /* Mode BURTCOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /* Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /* Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /* Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /* Mode DAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /* Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /* Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /* Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /* Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /* Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /* Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /* Mode TIMER2OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /* Mode TIMER3OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /* Mode USBSOFSR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /* Mode RTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /* Mode UART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /* Mode UART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /* Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /* Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /* Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /* Mode BURTCCOMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /* Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /* Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /* Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /* Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /* Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /* Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /* Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /* Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /* Mode TIMER2CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /* Mode TIMER3CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /* Mode RTCCOMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /* Mode UART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /* Mode UART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /* Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /* Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /* Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /* Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /* Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /* Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /* Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /* Mode TIMER2CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /* Mode TIMER3CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /* Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /* Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /* Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /* Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /* Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /* Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /* Mode TIMER2CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /* Mode TIMER3CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /* Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /* Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /* Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /* Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /* Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /* Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /* Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /* Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /* Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /* Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /* Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /* Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /* Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /* Mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /* Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /* Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /* Shifted mode VCMPOUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /* Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /* Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /* Shifted mode DAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /* Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /* Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /* Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /* Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /* Shifted mode TIMER2UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /* Shifted mode TIMER3UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /* Shifted mode USBSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /* Shifted mode RTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /* Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /* Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /* Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /* Shifted mode BURTCOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /* Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /* Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /* Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /* Shifted mode DAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /* Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /* Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /* Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /* Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /* Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /* Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /* Shifted mode TIMER2OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /* Shifted mode TIMER3OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /* Shifted mode USBSOFSR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /* Shifted mode RTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /* Shifted mode UART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /* Shifted mode UART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /* Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /* Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /* Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /* Shifted mode BURTCCOMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /* Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /* Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /* Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /* Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /* Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /* Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /* Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /* Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /* Shifted mode TIMER2CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /* Shifted mode TIMER3CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /* Shifted mode RTCCOMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /* Shifted mode UART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /* Shifted mode UART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /* Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /* Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /* Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /* Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /* Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /* Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /* Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /* Shifted mode TIMER2CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /* Shifted mode TIMER3CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /* Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /* Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /* Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /* Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /* Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /* Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /* Shifted mode TIMER2CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /* Shifted mode TIMER3CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /* Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /* Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /* Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /* Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /* Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /* Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /* Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /* Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /* Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /* Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /* Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /* Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /* Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /* Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /* Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /* Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /* Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /* Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /* Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /* Mode VCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /* Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /* Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /* Mode DAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /* Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /* Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /* Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /* Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /* Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /* Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /* Mode TIMER2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /* Mode TIMER3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /* Mode USB for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /* Mode RTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /* Mode UART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /* Mode UART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /* Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /* Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /* Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /* Mode BURTC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /* Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /* Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /* Mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /* Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /* Shifted mode VCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /* Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /* Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /* Shifted mode DAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /* Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /* Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /* Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /* Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /* Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /* Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /* Shifted mode TIMER2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /* Shifted mode TIMER3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /* Shifted mode USB for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /* Shifted mode RTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /* Shifted mode UART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /* Shifted mode UART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /* Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /* Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /* Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /* Shifted mode BURTC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /* Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /* Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /* Shifted mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /* Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /* Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /* Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /* Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /* Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /* Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /* Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /* Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /* Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /* Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /* Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /* Asynchronous reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /* Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /* Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /* Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /* Shifted mode DEFAULT for PRS_CH_CTRL */ + +/* PRS Signals *****************************************************************************************************************/ + +#define PRS_VCMP_OUT ((1 << 16) + 0) /* PRS Voltage comparator output */ +#define PRS_ACMP0_OUT ((2 << 16) + 0) /* PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((3 << 16) + 0) /* PRS Analog comparator output */ +#define PRS_DAC0_CH0 ((6 << 16) + 0) /* PRS DAC ch0 conversion done */ +#define PRS_DAC0_CH1 ((6 << 16) + 1) /* PRS DAC ch1 conversion done */ +#define PRS_ADC0_SINGLE ((8 << 16) + 0) /* PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((8 << 16) + 1) /* PRS ADC scan conversion done */ +#define PRS_USART0_IRTX ((16 << 16) + 0) /* PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((16 << 16) + 1) /* PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((16 << 16) + 2) /* PRS USART 0 RX Data Valid */ +#define PRS_USART1_TXC ((17 << 16) + 1) /* PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((17 << 16) + 2) /* PRS USART 1 RX Data Valid */ +#define PRS_USART2_TXC ((18 << 16) + 1) /* PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((18 << 16) + 2) /* PRS USART 2 RX Data Valid */ +#define PRS_TIMER0_UF ((28 << 16) + 0) /* PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((28 << 16) + 1) /* PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((28 << 16) + 2) /* PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((28 << 16) + 3) /* PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((28 << 16) + 4) /* PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((29 << 16) + 0) /* PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((29 << 16) + 1) /* PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((29 << 16) + 2) /* PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((29 << 16) + 3) /* PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((29 << 16) + 4) /* PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER2_UF ((30 << 16) + 0) /* PRS Timer 2 Underflow */ +#define PRS_TIMER2_OF ((30 << 16) + 1) /* PRS Timer 2 Overflow */ +#define PRS_TIMER2_CC0 ((30 << 16) + 2) /* PRS Timer 2 Compare/Capture 0 */ +#define PRS_TIMER2_CC1 ((30 << 16) + 3) /* PRS Timer 2 Compare/Capture 1 */ +#define PRS_TIMER2_CC2 ((30 << 16) + 4) /* PRS Timer 2 Compare/Capture 2 */ +#define PRS_TIMER3_UF ((31 << 16) + 0) /* PRS Timer 3 Underflow */ +#define PRS_TIMER3_OF ((31 << 16) + 1) /* PRS Timer 3 Overflow */ +#define PRS_TIMER3_CC0 ((31 << 16) + 2) /* PRS Timer 3 Compare/Capture 0 */ +#define PRS_TIMER3_CC1 ((31 << 16) + 3) /* PRS Timer 3 Compare/Capture 1 */ +#define PRS_TIMER3_CC2 ((31 << 16) + 4) /* PRS Timer 3 Compare/Capture 2 */ +#define PRS_USB_SOF ((36 << 16) + 0) /* PRS USB Start of Frame */ +#define PRS_USB_SOFSR ((36 << 16) + 1) /* PRS USB Start of Frame Sent/Received */ +#define PRS_RTC_OF ((40 << 16) + 0) /* PRS RTC Overflow */ +#define PRS_RTC_COMP0 ((40 << 16) + 1) /* PRS RTC Compare 0 */ +#define PRS_RTC_COMP1 ((40 << 16) + 2) /* PRS RTC Compare 1 */ +#define PRS_UART0_TXC ((41 << 16) + 1) /* PRS USART 0 TX complete */ +#define PRS_UART0_RXDATAV ((41 << 16) + 2) /* PRS USART 0 RX Data Valid */ +#define PRS_UART1_TXC ((42 << 16) + 1) /* PRS USART 0 TX complete */ +#define PRS_UART1_RXDATAV ((42 << 16) + 2) /* PRS USART 0 RX Data Valid */ +#define PRS_GPIO_PIN0 ((48 << 16) + 0) /* PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((48 << 16) + 1) /* PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((48 << 16) + 2) /* PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((48 << 16) + 3) /* PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((48 << 16) + 4) /* PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((48 << 16) + 5) /* PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((48 << 16) + 6) /* PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((48 << 16) + 7) /* PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((49 << 16) + 0) /* PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((49 << 16) + 1) /* PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((49 << 16) + 2) /* PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((49 << 16) + 3) /* PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((49 << 16) + 4) /* PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((49 << 16) + 5) /* PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((49 << 16) + 6) /* PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((49 << 16) + 7) /* PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /* PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /* PRS LETIMER CH1 Out */ +#define PRS_BURTC_OF ((55 << 16) + 0) /* PRS BURTC Overflow */ +#define PRS_BURTC_COMP0 ((55 << 16) + 1) /* PRS BURTC Compare 0 */ +#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /* PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /* PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /* PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /* PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /* PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /* PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /* PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /* PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /* PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /* PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /* PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /* PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /* PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /* PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /* PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /* PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /* PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /* PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /* PRS LESENSE Decoder PRS out 2 */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_PRS_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_rmu.h b/nuttx/arch/arm/src/efm32/chip/efm32_rmu.h new file mode 100644 index 000000000..e383cce13 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_rmu.h @@ -0,0 +1,205 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_rmu.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* RMU Register Offsets ********************************************************************************************************/ + +#define EFM32_RMU_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_RMU_RSTCAUSE_OFFSET 0x0004 /* Reset Cause Register */ +#define EFM32_RMU_CMD_OFFSET 0x0008 /* Command Register */ + +/* RMU Register Addresses ******************************************************************************************************/ + +#define EFM32_RMU_CTRL (EFM32_RMU_BASE+EFM32_RMU_CTRL_OFFSET) +#define EFM32_RMU_RSTCAUSE (EFM32_RMU_BASE+EFM32_RMU_RSTCAUSE_OFFSET) +#define EFM32_RMU_CMD (EFM32_RMU_BASE+EFM32_RMU_CMD_OFFSET) + +/* RMU Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for RMU CTRL */ + +#define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */ + +#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */ +#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */ +#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */ +#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */ +#define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */ +#define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */ +#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ + +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */ + +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */ +#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */ +#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */ +#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */ +#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */ +#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */ +#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */ +#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */ +#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */ +#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */ +#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */ +#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */ +#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */ +#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */ +#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */ +#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */ +#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */ +#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */ +#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */ +#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */ +#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */ +#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */ +#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */ +#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */ +#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */ +#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */ +#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */ +#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */ +#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */ +#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */ +#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ + +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ + +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_romtable.h b/nuttx/arch/arm/src/efm32/chip/efm32_romtable.h new file mode 100644 index 000000000..209fbd7d8 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_romtable.h @@ -0,0 +1,114 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_romtable.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ + +#define ROMTABLE ((const struct efm32_romtable_s *)EFM32_ROMTABLE_BASE) + +/* Bit fields for struct efm32_romtable_s */ + +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /* Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /* Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /* CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /* CHIP MAJOR Revison, shift */ + +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /* Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /* Most Significant Bits [5:2] of CHIP FAMILY, shift */ + +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /* Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /* Most Significant Bits [7:4] of CHIP MINOR revision, mask */ + +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /* Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /* Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/******************************************************************************************************************************* + * Public Type Definitions + *******************************************************************************************************************************/ + +struct efm32_romtable_s +{ + const uint32_t pid4; /* JEP_106_BANK */ + const uint32_t pid5; /* Unused */ + const uint32_t pid6; /* Unused */ + const uint32_t pid7; /* Unused */ + const uint32_t pid0; /* Chip family LSB, chip major revision */ + const uint32_t pid1; /* JEP_106_NO, Chip family MSB */ + const uint32_t pid2; /* Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + const uint32_t pid3; /* Chip minor rev LSB */ + const uint32_t cid0; /* Unused */ +}; + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_rtc.h b/nuttx/arch/arm/src/efm32/chip/efm32_rtc.h new file mode 100644 index 000000000..044efae97 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_rtc.h @@ -0,0 +1,281 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_rtc.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* RTC Register Offsets ********************************************************************************************************/ + +#define EFM32_RTC_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_RTC_CNT_OFFSET 0x0004 /* Counter Value Register */ +#define EFM32_RTC_COMP0_OFFSET 0x0008 /* Compare Value Register 0 */ +#define EFM32_RTC_COMP1_OFFSET 0x000c /* Compare Value Register 1 */ +#define EFM32_RTC_IF_OFFSET 0x0010 /* Interrupt Flag Register */ +#define EFM32_RTC_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ +#define EFM32_RTC_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ +#define EFM32_RTC_IEN_OFFSET 0x001c /* Interrupt Enable Register */ +#define EFM32_RTC_FREEZE_OFFSET 0x0020 /* Freeze Register */ +#define EFM32_RTC_SYNCBUSY_OFFSET 0x0024 /* Synchronization Busy Register */ + +/* RTC Register Addresses ******************************************************************************************************/ + +#define EFM32_RTC_CTRL (EFM32_RTC_BASE+EFM32_RTC_CTRL_OFFSET) +#define EFM32_RTC_CNT (EFM32_RTC_BASE+EFM32_RTC_CNT_OFFSET) +#define EFM32_RTC_COMP0 (EFM32_RTC_BASE+EFM32_RTC_COMP0_OFFSET) +#define EFM32_RTC_COMP1 (EFM32_RTC_BASE+EFM32_RTC_COMP1_OFFSET) +#define EFM32_RTC_IF (EFM32_RTC_BASE+EFM32_RTC_IF_OFFSET) +#define EFM32_RTC_IFS (EFM32_RTC_BASE+EFM32_RTC_IFS_OFFSET) +#define EFM32_RTC_IFC (EFM32_RTC_BASE+EFM32_RTC_IFC_OFFSET) +#define EFM32_RTC_IEN (EFM32_RTC_BASE+EFM32_RTC_IEN_OFFSET) +#define EFM32_RTC_FREEZE (EFM32_RTC_BASE+EFM32_RTC_FREEZE_OFFSET) +#define EFM32_RTC_SYNCBUSY (EFM32_RTC_BASE+EFM32_RTC_SYNCBUSY_OFFSET) + +/* RTC Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for RTC CTRL */ + +#define _RTC_CTRL_RESETVALUE 0x00000000UL /* Default value for RTC_CTRL */ +#define _RTC_CTRL_MASK 0x00000007UL /* Mask for RTC_CTRL */ + +#define RTC_CTRL_EN (0x1UL << 0) /* RTC Enable */ +#define _RTC_CTRL_EN_SHIFT 0 /* Shift value for RTC_EN */ +#define _RTC_CTRL_EN_MASK 0x1UL /* Bit mask for RTC_EN */ +#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_DEBUGRUN (0x1UL << 1) /* Debug Mode Run Enable */ +#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /* Shift value for RTC_DEBUGRUN */ +#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /* Bit mask for RTC_DEBUGRUN */ +#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP (0x1UL << 2) /* Compare Channel 0 is Top Value */ +#define _RTC_CTRL_COMP0TOP_SHIFT 2 /* Shift value for RTC_COMP0TOP */ +#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /* Bit mask for RTC_COMP0TOP */ +#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /* Mode DISABLE for RTC_CTRL */ +#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /* Mode ENABLE for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /* Shifted mode DISABLE for RTC_CTRL */ +#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /* Shifted mode ENABLE for RTC_CTRL */ + +/* Bit fields for RTC CNT */ + +#define _RTC_CNT_RESETVALUE 0x00000000UL /* Default value for RTC_CNT */ +#define _RTC_CNT_MASK 0x00FFFFFFUL /* Mask for RTC_CNT */ + +#define _RTC_CNT_CNT_SHIFT 0 /* Shift value for RTC_CNT */ +#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /* Bit mask for RTC_CNT */ +#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CNT */ +#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_CNT */ + +/* Bit fields for RTC COMP0 */ + +#define _RTC_COMP0_RESETVALUE 0x00000000UL /* Default value for RTC_COMP0 */ +#define _RTC_COMP0_MASK 0x00FFFFFFUL /* Mask for RTC_COMP0 */ + +#define _RTC_COMP0_COMP0_SHIFT 0 /* Shift value for RTC_COMP0 */ +#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /* Bit mask for RTC_COMP0 */ +#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_COMP0 */ +#define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_COMP0 */ + +/* Bit fields for RTC COMP1 */ + +#define _RTC_COMP1_RESETVALUE 0x00000000UL /* Default value for RTC_COMP1 */ +#define _RTC_COMP1_MASK 0x00FFFFFFUL /* Mask for RTC_COMP1 */ + +#define _RTC_COMP1_COMP1_SHIFT 0 /* Shift value for RTC_COMP1 */ +#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /* Bit mask for RTC_COMP1 */ +#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_COMP1 */ +#define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_COMP1 */ + +/* Bit fields for RTC IF */ + +#define _RTC_IF_RESETVALUE 0x00000000UL /* Default value for RTC_IF */ +#define _RTC_IF_MASK 0x00000007UL /* Mask for RTC_IF */ + +#define RTC_IF_OF (0x1UL << 0) /* Overflow Interrupt Flag */ +#define _RTC_IF_OF_SHIFT 0 /* Shift value for RTC_OF */ +#define _RTC_IF_OF_MASK 0x1UL /* Bit mask for RTC_OF */ +#define _RTC_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */ +#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP0 (0x1UL << 1) /* Compare Match 0 Interrupt Flag */ +#define _RTC_IF_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */ +#define _RTC_IF_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */ +#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP1 (0x1UL << 2) /* Compare Match 1 Interrupt Flag */ +#define _RTC_IF_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */ +#define _RTC_IF_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */ +#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */ +#define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IF */ + +/* Bit fields for RTC IFS */ + +#define _RTC_IFS_RESETVALUE 0x00000000UL /* Default value for RTC_IFS */ +#define _RTC_IFS_MASK 0x00000007UL /* Mask for RTC_IFS */ + +#define RTC_IFS_OF (0x1UL << 0) /* Set Overflow Interrupt Flag */ +#define _RTC_IFS_OF_SHIFT 0 /* Shift value for RTC_OF */ +#define _RTC_IFS_OF_MASK 0x1UL /* Bit mask for RTC_OF */ +#define _RTC_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP0 (0x1UL << 1) /* Set Compare match 0 Interrupt Flag */ +#define _RTC_IFS_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */ +#define _RTC_IFS_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */ +#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP1 (0x1UL << 2) /* Set Compare match 1 Interrupt Flag */ +#define _RTC_IFS_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */ +#define _RTC_IFS_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */ +#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */ +#define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IFS */ + +/* Bit fields for RTC IFC */ + +#define _RTC_IFC_RESETVALUE 0x00000000UL /* Default value for RTC_IFC */ +#define _RTC_IFC_MASK 0x00000007UL /* Mask for RTC_IFC */ + +#define RTC_IFC_OF (0x1UL << 0) /* Clear Overflow Interrupt Flag */ +#define _RTC_IFC_OF_SHIFT 0 /* Shift value for RTC_OF */ +#define _RTC_IFC_OF_MASK 0x1UL /* Bit mask for RTC_OF */ +#define _RTC_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP0 (0x1UL << 1) /* Clear Compare match 0 Interrupt Flag */ +#define _RTC_IFC_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */ +#define _RTC_IFC_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */ +#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP1 (0x1UL << 2) /* Clear Compare match 1 Interrupt Flag */ +#define _RTC_IFC_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */ +#define _RTC_IFC_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */ +#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */ +#define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IFC */ + +/* Bit fields for RTC IEN */ + +#define _RTC_IEN_RESETVALUE 0x00000000UL /* Default value for RTC_IEN */ +#define _RTC_IEN_MASK 0x00000007UL /* Mask for RTC_IEN */ + +#define RTC_IEN_OF (0x1UL << 0) /* Overflow Interrupt Enable */ +#define _RTC_IEN_OF_SHIFT 0 /* Shift value for RTC_OF */ +#define _RTC_IEN_OF_MASK 0x1UL /* Bit mask for RTC_OF */ +#define _RTC_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP0 (0x1UL << 1) /* Compare Match 0 Interrupt Enable */ +#define _RTC_IEN_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */ +#define _RTC_IEN_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */ +#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP1 (0x1UL << 2) /* Compare Match 1 Interrupt Enable */ +#define _RTC_IEN_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */ +#define _RTC_IEN_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */ +#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */ +#define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IEN */ + +/* Bit fields for RTC FREEZE */ + +#define _RTC_FREEZE_RESETVALUE 0x00000000UL /* Default value for RTC_FREEZE */ +#define _RTC_FREEZE_MASK 0x00000001UL /* Mask for RTC_FREEZE */ + +#define RTC_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */ +#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for RTC_REGFREEZE */ +#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for RTC_REGFREEZE */ +#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_FREEZE */ +#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for RTC_FREEZE */ +#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for RTC_FREEZE */ + +/* Bit fields for RTC SYNCBUSY */ + +#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for RTC_SYNCBUSY */ +#define _RTC_SYNCBUSY_MASK 0x00000007UL /* Mask for RTC_SYNCBUSY */ + +#define RTC_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */ +#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for RTC_CTRL */ +#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for RTC_CTRL */ +#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /* COMP0 Register Busy */ +#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */ +#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */ +#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /* COMP1 Register Busy */ +#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */ +#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */ +#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_SYNCBUSY */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_timer.h b/nuttx/arch/arm/src/efm32/chip/efm32_timer.h new file mode 100644 index 000000000..d312dd4ea --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_timer.h @@ -0,0 +1,1219 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_timer.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_TIMER_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_TIMER_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ + +#define EFM32_TIMER_NCC 3 /* Three control channels */ + +/* TIMER Register Offsets ******************************************************************************************************/ + +#define EFM32_TIMER_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_TIMER_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_TIMER_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_TIMER_IEN_OFFSET 0x000c /* Interrupt Enable Register */ +#define EFM32_TIMER_IF_OFFSET 0x0010 /* Interrupt Flag Register */ +#define EFM32_TIMER_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ +#define EFM32_TIMER_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ +#define EFM32_TIMER_TOP_OFFSET 0x001c /* Counter Top Value Register */ +#define EFM32_TIMER_TOPB_OFFSET 0x0020 /* Counter Top Value Buffer Register */ +#define EFM32_TIMER_CNT_OFFSET 0x0024 /* Counter Value Register */ +#define EFM32_TIMER_ROUTE_OFFSET 0x0028 /* I/O Routing Register */ + +#define EFM32_TIMER_CC_OFFSET(n) (0x0030 +((n) << 4)) +#define EFM32_TIMER_CC_CTRL_OFFSET 0x0000 /* CC Channel Control Register */ +#define EFM32_TIMER_CC_CCV_OFFSET 0x0004 /* CC Channel Value Register */ +#define EFM32_TIMER_CC_CCVP_OFFSET 0x0008 /* CC Channel Value Peek Register */ +#define EFM32_TIMER_CC_CCVB_OFFSET 0x000c /* CC Channel Buffer Register */ + +#define EFM32_TIMER_CC0_CTRL_OFFSET 0x0030 /* CC Channel Control Register */ +#define EFM32_TIMER_CC0_CCV_OFFSET 0x0034 /* CC Channel Value Register */ +#define EFM32_TIMER_CC0_CCVP_OFFSET 0x0038 /* CC Channel Value Peek Register */ +#define EFM32_TIMER_CC0_CCVB_OFFSET 0x003c /* CC Channel Buffer Register */ +#define EFM32_TIMER_CC1_CTRL_OFFSET 0x0040 /* CC Channel Control Register */ +#define EFM32_TIMER_CC1_CCV_OFFSET 0x0044 /* CC Channel Value Register */ +#define EFM32_TIMER_CC1_CCVP_OFFSET 0x0048 /* CC Channel Value Peek Register */ +#define EFM32_TIMER_CC1_CCVB_OFFSET 0x004c /* CC Channel Buffer Register */ +#define EFM32_TIMER_CC2_CTRL_OFFSET 0x0050 /* CC Channel Control Register */ +#define EFM32_TIMER_CC2_CCV_OFFSET 0x0054 /* CC Channel Value Register */ +#define EFM32_TIMER_CC2_CCVP_OFFSET 0x0058 /* CC Channel Value Peek Register */ +#define EFM32_TIMER_CC2_CCVB_OFFSET 0x005c /* CC Channel Buffer Register */ + +#define EFM32_TIMER_DTCTRL_OFFSET 0x0070 /* DTI Control Register */ +#define EFM32_TIMER_DTTIME_OFFSET 0x0074 /* DTI Time Control Register */ +#define EFM32_TIMER_DTFC_OFFSET 0x0078 /* DTI Fault Configuration Register */ +#define EFM32_TIMER_DTOGEN_OFFSET 0x007c /* DTI Output Generation Enable Register */ +#define EFM32_TIMER_DTFAULT_OFFSET 0x0080 /* DTI Fault Register */ +#define EFM32_TIMER_DTFAULTC_OFFSET 0x0084 /* DTI Fault Clear Register */ +#define EFM32_TIMER_DTLOCK_OFFSET 0x0088 /* DTI Configuration Lock Register */ + +/* TIMER Register Addresses ****************************************************************************************************/ + +#define EFM32_TIMER0_CTRL (EFM32_TIMER0_BASE+EFM32_TIMER_CTRL_OFFSET) +#define EFM32_TIMER0_CMD_ (EFM32_TIMER0_BASE+EFM32_TIMER_CMD_OFFSET) +#define EFM32_TIMER0_STATUS (EFM32_TIMER0_BASE+EFM32_TIMER_STATUS_OFFSET) +#define EFM32_TIMER0_IEN (EFM32_TIMER0_BASE+EFM32_TIMER_IEN_OFFSET) +#define EFM32_TIMER0_IF (EFM32_TIMER0_BASE+EFM32_TIMER_IF_OFFSET) +#define EFM32_TIMER0_IFS (EFM32_TIMER0_BASE+EFM32_TIMER_IFS_OFFSET) +#define EFM32_TIMER0_IFC (EFM32_TIMER0_BASE+EFM32_TIMER_IFC_OFFSET) +#define EFM32_TIMER0_TOP (EFM32_TIMER0_BASE+EFM32_TIMER_TOP_OFFSET) +#define EFM32_TIMER0_TOPB (EFM32_TIMER0_BASE+EFM32_TIMER_TOPB_OFFSET) +#define EFM32_TIMER0_CNT (EFM32_TIMER0_BASE+EFM32_TIMER_CNT_OFFSET) +#define EFM32_TIMER0_ROUTE (EFM32_TIMER0_BASE+EFM32_TIMER_ROUTE_OFFSET) + +#define EFM32_TIMER0_CC(n) (EFM32_TIMER0_BASE+EFM32_TIMER_CC_OFFSET(n)) +#define EFM32_TIMER0_CC_CTRL(n) (EFM32_TIMER0_CC(n)+EFM32_TIMER_CC_CTRL_OFFSET) +#define EFM32_TIMER0_CC_CCV(n) (EFM32_TIMER0_CC(n)+EFM32_TIMER_CC_CCV_OFFSET) +#define EFM32_TIMER0_CC_CCVP(n) (EFM32_TIMER0_CC(n)+EFM32_TIMER_CC_CCVP_OFFSET) +#define EFM32_TIMER0_CC_CCVB(n) (EFM32_TIMER0_CC(n)+EFM32_TIMER_CC_CCVB_OFFSET) + +#define EFM32_TIMER0_CC0_CTRL (EFM32_TIMER0_BASE+EFM32_TIMER_CC0_CTRL_OFFSET) +#define EFM32_TIMER0_CC0_CCV (EFM32_TIMER0_BASE+EFM32_TIMER_CC0_CCV_OFFSET) +#define EFM32_TIMER0_CC0_CCVP (EFM32_TIMER0_BASE+EFM32_TIMER_CC0_CCVP_OFFSET) +#define EFM32_TIMER0_CC0_CCVB (EFM32_TIMER0_BASE+EFM32_TIMER_CC0_CCVB_OFFSET) +#define EFM32_TIMER0_CC1_CTRL (EFM32_TIMER0_BASE+EFM32_TIMER_CC1_CTRL_OFFSET) +#define EFM32_TIMER0_CC1_CCV (EFM32_TIMER0_BASE+EFM32_TIMER_CC1_CCV_OFFSET) +#define EFM32_TIMER0_CC1_CCVP (EFM32_TIMER0_BASE+EFM32_TIMER_CC1_CCVP_OFFSET) +#define EFM32_TIMER0_CC1_CCVB (EFM32_TIMER0_BASE+EFM32_TIMER_CC1_CCVB_OFFSET) +#define EFM32_TIMER0_CC2_CTRL (EFM32_TIMER0_BASE+EFM32_TIMER_CC2_CTRL_OFFSET) +#define EFM32_TIMER0_CC2_CCV (EFM32_TIMER0_BASE+EFM32_TIMER_CC2_CCV_OFFSET) +#define EFM32_TIMER0_CC2_CCVP (EFM32_TIMER0_BASE+EFM32_TIMER_CC2_CCVP_OFFSET) +#define EFM32_TIMER0_CC2_CCVB (EFM32_TIMER0_BASE+EFM32_TIMER_CC2_CCVB_OFFSET) + +#define EFM32_TIMER0_DTCTRL (EFM32_TIMER0_BASE+EFM32_TIMER_DTCTRL_OFFSET) +#define EFM32_TIMER0_DTTIME (EFM32_TIMER0_BASE+EFM32_TIMER_DTTIME_OFFSET) +#define EFM32_TIMER0_DTFC (EFM32_TIMER0_BASE+EFM32_TIMER_DTFC_OFFSET) +#define EFM32_TIMER0_DTOGEN (EFM32_TIMER0_BASE+EFM32_TIMER_DTOGEN_OFFSET) +#define EFM32_TIMER0_DTFAULT (EFM32_TIMER0_BASE+EFM32_TIMER_DTFAULT_OFFSET) +#define EFM32_TIMER0_DTFAULTC (EFM32_TIMER0_BASE+EFM32_TIMER_DTFAULTC_OFFSET) +#define EFM32_TIMER0_DTLOCK (EFM32_TIMER0_BASE+EFM32_TIMER_DTLOCK_OFFSET) + +#define EFM32_TIMER1_CTRL (EFM32_TIMER1_BASE+EFM32_TIMER_CTRL_OFFSET) +#define EFM32_TIMER1_CMD_ (EFM32_TIMER1_BASE+EFM32_TIMER_CMD_OFFSET) +#define EFM32_TIMER1_STATUS (EFM32_TIMER1_BASE+EFM32_TIMER_STATUS_OFFSET) +#define EFM32_TIMER1_IEN (EFM32_TIMER1_BASE+EFM32_TIMER_IEN_OFFSET) +#define EFM32_TIMER1_IF (EFM32_TIMER1_BASE+EFM32_TIMER_IF_OFFSET) +#define EFM32_TIMER1_IFS (EFM32_TIMER1_BASE+EFM32_TIMER_IFS_OFFSET) +#define EFM32_TIMER1_IFC (EFM32_TIMER1_BASE+EFM32_TIMER_IFC_OFFSET) +#define EFM32_TIMER1_TOP (EFM32_TIMER1_BASE+EFM32_TIMER_TOP_OFFSET) +#define EFM32_TIMER1_TOPB (EFM32_TIMER1_BASE+EFM32_TIMER_TOPB_OFFSET) +#define EFM32_TIMER1_CNT (EFM32_TIMER1_BASE+EFM32_TIMER_CNT_OFFSET) +#define EFM32_TIMER1_ROUTE (EFM32_TIMER1_BASE+EFM32_TIMER_ROUTE_OFFSET) + +#define EFM32_TIMER1_CC(n) (EFM32_TIMER1_BASE+EFM32_TIMER_CC_OFFSET(n)) +#define EFM32_TIMER1_CC_CTRL(n) (EFM32_TIMER1_CC(n)+EFM32_TIMER_CC_CTRL_OFFSET) +#define EFM32_TIMER1_CC_CCV(n) (EFM32_TIMER1_CC(n)+EFM32_TIMER_CC_CCV_OFFSET) +#define EFM32_TIMER1_CC_CCVP(n) (EFM32_TIMER1_CC(n)+EFM32_TIMER_CC_CCVP_OFFSET) +#define EFM32_TIMER1_CC_CCVB(n) (EFM32_TIMER1_CC(n)+EFM32_TIMER_CC_CCVB_OFFSET) + +#define EFM32_TIMER1_CC0_CTRL (EFM32_TIMER1_BASE+EFM32_TIMER_CC0_CTRL_OFFSET) +#define EFM32_TIMER1_CC0_CCV (EFM32_TIMER1_BASE+EFM32_TIMER_CC0_CCV_OFFSET) +#define EFM32_TIMER1_CC0_CCVP (EFM32_TIMER1_BASE+EFM32_TIMER_CC0_CCVP_OFFSET) +#define EFM32_TIMER1_CC0_CCVB (EFM32_TIMER1_BASE+EFM32_TIMER_CC0_CCVB_OFFSET) +#define EFM32_TIMER1_CC1_CTRL (EFM32_TIMER1_BASE+EFM32_TIMER_CC1_CTRL_OFFSET) +#define EFM32_TIMER1_CC1_CCV (EFM32_TIMER1_BASE+EFM32_TIMER_CC1_CCV_OFFSET) +#define EFM32_TIMER1_CC1_CCVP (EFM32_TIMER1_BASE+EFM32_TIMER_CC1_CCVP_OFFSET) +#define EFM32_TIMER1_CC1_CCVB (EFM32_TIMER1_BASE+EFM32_TIMER_CC1_CCVB_OFFSET) +#define EFM32_TIMER1_CC2_CTRL (EFM32_TIMER1_BASE+EFM32_TIMER_CC2_CTRL_OFFSET) +#define EFM32_TIMER1_CC2_CCV (EFM32_TIMER1_BASE+EFM32_TIMER_CC2_CCV_OFFSET) +#define EFM32_TIMER1_CC2_CCVP (EFM32_TIMER1_BASE+EFM32_TIMER_CC2_CCVP_OFFSET) +#define EFM32_TIMER1_CC2_CCVB (EFM32_TIMER1_BASE+EFM32_TIMER_CC2_CCVB_OFFSET) + +#define EFM32_TIMER1_DTCTRL (EFM32_TIMER1_BASE+EFM32_TIMER_DTCTRL_OFFSET) +#define EFM32_TIMER1_DTTIME (EFM32_TIMER1_BASE+EFM32_TIMER_DTTIME_OFFSET) +#define EFM32_TIMER1_DTFC (EFM32_TIMER1_BASE+EFM32_TIMER_DTFC_OFFSET) +#define EFM32_TIMER1_DTOGEN (EFM32_TIMER1_BASE+EFM32_TIMER_DTOGEN_OFFSET) +#define EFM32_TIMER1_DTFAULT (EFM32_TIMER1_BASE+EFM32_TIMER_DTFAULT_OFFSET) +#define EFM32_TIMER1_DTFAULTC (EFM32_TIMER1_BASE+EFM32_TIMER_DTFAULTC_OFFSET) +#define EFM32_TIMER1_DTLOCK (EFM32_TIMER1_BASE+EFM32_TIMER_DTLOCK_OFFSET) + +#define EFM32_TIMER2_CTRL (EFM32_TIMER2_BASE+EFM32_TIMER_CTRL_OFFSET) +#define EFM32_TIMER2_CMD_ (EFM32_TIMER2_BASE+EFM32_TIMER_CMD_OFFSET) +#define EFM32_TIMER2_STATUS (EFM32_TIMER2_BASE+EFM32_TIMER_STATUS_OFFSET) +#define EFM32_TIMER2_IEN (EFM32_TIMER2_BASE+EFM32_TIMER_IEN_OFFSET) +#define EFM32_TIMER2_IF (EFM32_TIMER2_BASE+EFM32_TIMER_IF_OFFSET) +#define EFM32_TIMER2_IFS (EFM32_TIMER2_BASE+EFM32_TIMER_IFS_OFFSET) +#define EFM32_TIMER2_IFC (EFM32_TIMER2_BASE+EFM32_TIMER_IFC_OFFSET) +#define EFM32_TIMER2_TOP (EFM32_TIMER2_BASE+EFM32_TIMER_TOP_OFFSET) +#define EFM32_TIMER2_TOPB (EFM32_TIMER2_BASE+EFM32_TIMER_TOPB_OFFSET) +#define EFM32_TIMER2_CNT (EFM32_TIMER2_BASE+EFM32_TIMER_CNT_OFFSET) +#define EFM32_TIMER2_ROUTE (EFM32_TIMER2_BASE+EFM32_TIMER_ROUTE_OFFSET) + +#define EFM32_TIMER2_CC(n) (EFM32_TIMER2_BASE+EFM32_TIMER_CC_OFFSET(n)) +#define EFM32_TIMER2_CC_CTRL(n) (EFM32_TIMER2_CC(n)+EFM32_TIMER_CC_CTRL_OFFSET) +#define EFM32_TIMER2_CC_CCV(n) (EFM32_TIMER2_CC(n)+EFM32_TIMER_CC_CCV_OFFSET) +#define EFM32_TIMER2_CC_CCVP(n) (EFM32_TIMER2_CC(n)+EFM32_TIMER_CC_CCVP_OFFSET) +#define EFM32_TIMER2_CC_CCVB(n) (EFM32_TIMER2_CC(n)+EFM32_TIMER_CC_CCVB_OFFSET) + +#define EFM32_TIMER2_CC0_CTRL (EFM32_TIMER2_BASE+EFM32_TIMER_CC0_CTRL_OFFSET) +#define EFM32_TIMER2_CC0_CCV (EFM32_TIMER2_BASE+EFM32_TIMER_CC0_CCV_OFFSET) +#define EFM32_TIMER2_CC0_CCVP (EFM32_TIMER2_BASE+EFM32_TIMER_CC0_CCVP_OFFSET) +#define EFM32_TIMER2_CC0_CCVB (EFM32_TIMER2_BASE+EFM32_TIMER_CC0_CCVB_OFFSET) +#define EFM32_TIMER2_CC1_CTRL (EFM32_TIMER2_BASE+EFM32_TIMER_CC1_CTRL_OFFSET) +#define EFM32_TIMER2_CC1_CCV (EFM32_TIMER2_BASE+EFM32_TIMER_CC1_CCV_OFFSET) +#define EFM32_TIMER2_CC1_CCVP (EFM32_TIMER2_BASE+EFM32_TIMER_CC1_CCVP_OFFSET) +#define EFM32_TIMER2_CC1_CCVB (EFM32_TIMER2_BASE+EFM32_TIMER_CC1_CCVB_OFFSET) +#define EFM32_TIMER2_CC2_CTRL (EFM32_TIMER2_BASE+EFM32_TIMER_CC2_CTRL_OFFSET) +#define EFM32_TIMER2_CC2_CCV (EFM32_TIMER2_BASE+EFM32_TIMER_CC2_CCV_OFFSET) +#define EFM32_TIMER2_CC2_CCVP (EFM32_TIMER2_BASE+EFM32_TIMER_CC2_CCVP_OFFSET) +#define EFM32_TIMER2_CC2_CCVB (EFM32_TIMER2_BASE+EFM32_TIMER_CC2_CCVB_OFFSET) + +#define EFM32_TIMER2_DTCTRL (EFM32_TIMER2_BASE+EFM32_TIMER_DTCTRL_OFFSET) +#define EFM32_TIMER2_DTTIME (EFM32_TIMER2_BASE+EFM32_TIMER_DTTIME_OFFSET) +#define EFM32_TIMER2_DTFC (EFM32_TIMER2_BASE+EFM32_TIMER_DTFC_OFFSET) +#define EFM32_TIMER2_DTOGEN (EFM32_TIMER2_BASE+EFM32_TIMER_DTOGEN_OFFSET) +#define EFM32_TIMER2_DTFAULT (EFM32_TIMER2_BASE+EFM32_TIMER_DTFAULT_OFFSET) +#define EFM32_TIMER2_DTFAULTC (EFM32_TIMER2_BASE+EFM32_TIMER_DTFAULTC_OFFSET) +#define EFM32_TIMER2_DTLOCK (EFM32_TIMER2_BASE+EFM32_TIMER_DTLOCK_OFFSET) + +#define EFM32_TIMER3_CTRL (EFM32_TIMER3_BASE+EFM32_TIMER_CTRL_OFFSET) +#define EFM32_TIMER3_CMD_ (EFM32_TIMER3_BASE+EFM32_TIMER_CMD_OFFSET) +#define EFM32_TIMER3_STATUS (EFM32_TIMER3_BASE+EFM32_TIMER_STATUS_OFFSET) +#define EFM32_TIMER3_IEN (EFM32_TIMER3_BASE+EFM32_TIMER_IEN_OFFSET) +#define EFM32_TIMER3_IF (EFM32_TIMER3_BASE+EFM32_TIMER_IF_OFFSET) +#define EFM32_TIMER3_IFS (EFM32_TIMER3_BASE+EFM32_TIMER_IFS_OFFSET) +#define EFM32_TIMER3_IFC (EFM32_TIMER3_BASE+EFM32_TIMER_IFC_OFFSET) +#define EFM32_TIMER3_TOP (EFM32_TIMER3_BASE+EFM32_TIMER_TOP_OFFSET) +#define EFM32_TIMER3_TOPB (EFM32_TIMER3_BASE+EFM32_TIMER_TOPB_OFFSET) +#define EFM32_TIMER3_CNT (EFM32_TIMER3_BASE+EFM32_TIMER_CNT_OFFSET) +#define EFM32_TIMER3_ROUTE (EFM32_TIMER3_BASE+EFM32_TIMER_ROUTE_OFFSET) + +#define EFM32_TIMER3_CC(n) (EFM32_TIMER3_BASE+EFM32_TIMER_CC_OFFSET(n)) +#define EFM32_TIMER3_CC_CTRL(n) (EFM32_TIMER3_CC(n)+EFM32_TIMER_CC_CTRL_OFFSET) +#define EFM32_TIMER3_CC_CCV(n) (EFM32_TIMER3_CC(n)+EFM32_TIMER_CC_CCV_OFFSET) +#define EFM32_TIMER3_CC_CCVP(n) (EFM32_TIMER3_CC(n)+EFM32_TIMER_CC_CCVP_OFFSET) +#define EFM32_TIMER3_CC_CCVB(n) (EFM32_TIMER3_CC(n)+EFM32_TIMER_CC_CCVB_OFFSET) + +#define EFM32_TIMER3_CC0_CTRL (EFM32_TIMER3_BASE+EFM32_TIMER_CC0_CTRL_OFFSET) +#define EFM32_TIMER3_CC0_CCV (EFM32_TIMER3_BASE+EFM32_TIMER_CC0_CCV_OFFSET) +#define EFM32_TIMER3_CC0_CCVP (EFM32_TIMER3_BASE+EFM32_TIMER_CC0_CCVP_OFFSET) +#define EFM32_TIMER3_CC0_CCVB (EFM32_TIMER3_BASE+EFM32_TIMER_CC0_CCVB_OFFSET) +#define EFM32_TIMER3_CC1_CTRL (EFM32_TIMER3_BASE+EFM32_TIMER_CC1_CTRL_OFFSET) +#define EFM32_TIMER3_CC1_CCV (EFM32_TIMER3_BASE+EFM32_TIMER_CC1_CCV_OFFSET) +#define EFM32_TIMER3_CC1_CCVP (EFM32_TIMER3_BASE+EFM32_TIMER_CC1_CCVP_OFFSET) +#define EFM32_TIMER3_CC1_CCVB (EFM32_TIMER3_BASE+EFM32_TIMER_CC1_CCVB_OFFSET) +#define EFM32_TIMER3_CC2_CTRL (EFM32_TIMER3_BASE+EFM32_TIMER_CC2_CTRL_OFFSET) +#define EFM32_TIMER3_CC2_CCV (EFM32_TIMER3_BASE+EFM32_TIMER_CC2_CCV_OFFSET) +#define EFM32_TIMER3_CC2_CCVP (EFM32_TIMER3_BASE+EFM32_TIMER_CC2_CCVP_OFFSET) +#define EFM32_TIMER3_CC2_CCVB (EFM32_TIMER3_BASE+EFM32_TIMER_CC2_CCVB_OFFSET) + +#define EFM32_TIMER3_DTCTRL (EFM32_TIMER3_BASE+EFM32_TIMER_DTCTRL_OFFSET) +#define EFM32_TIMER3_DTTIME (EFM32_TIMER3_BASE+EFM32_TIMER_DTTIME_OFFSET) +#define EFM32_TIMER3_DTFC (EFM32_TIMER3_BASE+EFM32_TIMER_DTFC_OFFSET) +#define EFM32_TIMER3_DTOGEN (EFM32_TIMER3_BASE+EFM32_TIMER_DTOGEN_OFFSET) +#define EFM32_TIMER3_DTFAULT (EFM32_TIMER3_BASE+EFM32_TIMER_DTFAULT_OFFSET) +#define EFM32_TIMER3_DTFAULTC (EFM32_TIMER3_BASE+EFM32_TIMER_DTFAULTC_OFFSET) +#define EFM32_TIMER3_DTLOCK (EFM32_TIMER3_BASE+EFM32_TIMER_DTLOCK_OFFSET) + +/* TIMER Register Bit Field Definitions ****************************************************************************************/ + +/* Bit fields for TIMER CTRL */ + +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /* Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F032FFBUL /* Mask for TIMER_CTRL */ + +#define _TIMER_CTRL_MODE_SHIFT 0 /* Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /* Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /* Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /* Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /* Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /* Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /* Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /* Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /* Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /* Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /* Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /* Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /* Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /* One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /* Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /* Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /* Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /* Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /* Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /* Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /* Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /* Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /* Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /* Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /* Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /* Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /* DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /* Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /* Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /* Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /* Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /* Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /* Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /* Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /* Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /* Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /* Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /* Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /* Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /* Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /* Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /* Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /* Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /* Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /* Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /* Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /* Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /* Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /* Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /* 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /* Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /* Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /* Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /* Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /* Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /* Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /* Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /* Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /* Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /* Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /* Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /* Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /* Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /* Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /* Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /* Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /* Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /* Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /* Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /* Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /* Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /* Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /* Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /* Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /* Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /* Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /* Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /* Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /* Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /* Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /* Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /* Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /* Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /* Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /* Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /* Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /* Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /* Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /* Reload-Start Sets Compare Ouptut initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /* Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /* Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /* Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ + +#define _TIMER_CMD_RESETVALUE 0x00000000UL /* Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /* Mask for TIMER_CMD */ + +#define TIMER_CMD_START (0x1UL << 0) /* Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /* Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /* Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /* Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /* Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /* Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ + +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /* Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070707UL /* Mask for TIMER_STATUS */ + +#define TIMER_STATUS_RUNNING (0x1UL << 0) /* Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /* Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /* Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /* Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /* Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /* Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /* Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /* Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /* Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /* Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /* TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /* Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /* Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /* CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /* Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /* Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /* CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /* Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /* Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /* CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /* Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /* Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /* CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /* Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /* Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /* CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /* Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /* Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /* CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /* Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /* Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /* CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /* Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /* Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /* Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /* Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /* Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /* Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /* CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /* Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /* Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /* Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /* Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /* Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /* Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /* CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /* Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /* Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /* Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /* Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /* Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /* Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /* Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IEN */ + +#define _TIMER_IEN_RESETVALUE 0x00000000UL /* Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000773UL /* Mask for TIMER_IEN */ + +#define TIMER_IEN_OF (0x1UL << 0) /* Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /* Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /* Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /* Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /* Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /* Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /* CC Channel 0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /* Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /* Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /* CC Channel 1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /* Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /* Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /* CC Channel 2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /* Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /* Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /* CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /* Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /* Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /* CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /* Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /* Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /* CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /* Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /* Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER IF */ + +#define _TIMER_IF_RESETVALUE 0x00000000UL /* Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000773UL /* Mask for TIMER_IF */ + +#define TIMER_IF_OF (0x1UL << 0) /* Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /* Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /* Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /* Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /* Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /* Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /* CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /* Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /* Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /* CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /* Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /* Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /* CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /* Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /* Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /* CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /* Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /* Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /* CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /* Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /* Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /* CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /* Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /* Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ + +#define _TIMER_IFS_RESETVALUE 0x00000000UL /* Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000773UL /* Mask for TIMER_IFS */ + +#define TIMER_IFS_OF (0x1UL << 0) /* Overflow Interrupt Flag Set */ +#define _TIMER_IFS_OF_SHIFT 0 /* Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /* Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /* Underflow Interrupt Flag Set */ +#define _TIMER_IFS_UF_SHIFT 1 /* Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /* Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /* CC Channel 0 Interrupt Flag Set */ +#define _TIMER_IFS_CC0_SHIFT 4 /* Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /* Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /* CC Channel 1 Interrupt Flag Set */ +#define _TIMER_IFS_CC1_SHIFT 5 /* Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /* Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /* CC Channel 2 Interrupt Flag Set */ +#define _TIMER_IFS_CC2_SHIFT 6 /* Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /* Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /* CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /* Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /* Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /* CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /* Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /* Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /* CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /* Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /* Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ + +#define _TIMER_IFC_RESETVALUE 0x00000000UL /* Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000773UL /* Mask for TIMER_IFC */ + +#define TIMER_IFC_OF (0x1UL << 0) /* Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_OF_SHIFT 0 /* Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /* Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /* Underflow Interrupt Flag Clear */ +#define _TIMER_IFC_UF_SHIFT 1 /* Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /* Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /* CC Channel 0 Interrupt Flag Clear */ +#define _TIMER_IFC_CC0_SHIFT 4 /* Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /* Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /* CC Channel 1 Interrupt Flag Clear */ +#define _TIMER_IFC_CC1_SHIFT 5 /* Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /* Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /* CC Channel 2 Interrupt Flag Clear */ +#define _TIMER_IFC_CC2_SHIFT 6 /* Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /* Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /* CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /* Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /* Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /* CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /* Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /* Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /* CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /* Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /* Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER TOP */ + +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /* Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /* Mask for TIMER_TOP */ + +#define _TIMER_TOP_TOP_SHIFT 0 /* Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /* Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /* Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ + +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /* Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /* Mask for TIMER_TOPB */ + +#define _TIMER_TOPB_TOPB_SHIFT 0 /* Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /* Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ + +#define _TIMER_CNT_RESETVALUE 0x00000000UL /* Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /* Mask for TIMER_CNT */ + +#define _TIMER_CNT_CNT_SHIFT 0 /* Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /* Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER ROUTE */ + +#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /* Default value for TIMER_ROUTE */ +#define _TIMER_ROUTE_MASK 0x00070707UL /* Mask for TIMER_ROUTE */ + +#define TIMER_ROUTE_CC0PEN (0x1UL << 0) /* CC Channel 0 Pin Enable */ +#define _TIMER_ROUTE_CC0PEN_SHIFT 0 /* Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTE_CC0PEN_MASK 0x1UL /* Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CC1PEN (0x1UL << 1) /* CC Channel 1 Pin Enable */ +#define _TIMER_ROUTE_CC1PEN_SHIFT 1 /* Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTE_CC1PEN_MASK 0x2UL /* Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CC2PEN (0x1UL << 2) /* CC Channel 2 Pin Enable */ +#define _TIMER_ROUTE_CC2PEN_SHIFT 2 /* Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTE_CC2PEN_MASK 0x4UL /* Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) /* CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 /* Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL /* Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) /* CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 /* Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL /* Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) /* CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 /* Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL /* Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_SHIFT 16 /* Shift value for TIMER_LOCATION */ +#define _TIMER_ROUTE_LOCATION_MASK 0x70000UL /* Bit mask for TIMER_LOCATION */ +#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /* Mode LOC3 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC4 0x00000004UL /* Mode LOC4 for TIMER_ROUTE */ +#define _TIMER_ROUTE_LOCATION_LOC5 0x00000005UL /* Mode LOC5 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /* Shifted mode LOC0 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /* Shifted mode LOC1 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /* Shifted mode LOC2 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /* Shifted mode LOC3 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC4 (_TIMER_ROUTE_LOCATION_LOC4 << 16) /* Shifted mode LOC4 for TIMER_ROUTE */ +#define TIMER_ROUTE_LOCATION_LOC5 (_TIMER_ROUTE_LOCATION_LOC5 << 16) /* Shifted mode LOC5 for TIMER_ROUTE */ + +/* Bit fields for TIMER CC_CTRL */ + +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /* Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F3F3F17UL /* Mask for TIMER_CC_CTRL */ + +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /* Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /* Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /* Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /* Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /* Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /* Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /* Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /* Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /* Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /* Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /* Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /* Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /* Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /* Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /* Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /* Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /* Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /* Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /* Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /* Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /* Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /* Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /* Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /* Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /* Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /* Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /* Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /* Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /* Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /* Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /* Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /* Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /* Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /* Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /* Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /* Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /* Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /* Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /* Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /* Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /* Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /* Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /* Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /* Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /* Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /* Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /* Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /* Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /* Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /* Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /* Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /* Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /* Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /* Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /* Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /* Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /* Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /* Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /* Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /* Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 20) /* Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /* Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /* Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /* Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /* Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) /* Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) /* Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 21) /* Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 21 /* Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /* Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /* Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /* Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) /* Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) /* Shifted mode ENABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /* Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /* Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /* Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /* Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /* Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /* Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /* Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /* Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /* Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /* Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /* Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /* Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /* Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /* Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /* Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /* Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /* Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /* Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /* Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /* Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /* Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ + +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /* Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /* Mask for TIMER_CC_CCV */ + +#define _TIMER_CC_CCV_CCV_SHIFT 0 /* Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /* Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ + +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /* Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /* Mask for TIMER_CC_CCVP */ + +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /* Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /* Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ + +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /* Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /* Mask for TIMER_CC_CCVB */ + +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /* Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /* Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ + +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /* Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010000FFUL /* Mask for TIMER_DTCTRL */ + +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /* DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /* Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /* Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /* DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /* Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /* Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /* Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /* Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /* Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /* Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /* DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /* Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /* Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /* DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /* Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /* Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /* Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /* Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /* Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /* Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /* Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /* Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /* Mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /* Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /* Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /* Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /* Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /* Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /* Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /* Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /* Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /* Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /* Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /* Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /* Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /* DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /* Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /* Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /* Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ + +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /* Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /* Mask for TIMER_DTTIME */ + +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /* Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /* Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /* Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /* Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /* Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /* Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /* Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /* Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /* Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /* Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /* Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /* Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /* Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /* Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /* Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /* Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /* Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /* Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /* Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /* Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /* Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /* Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /* Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /* Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /* Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /* Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /* Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /* Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ + +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /* Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030707UL /* Mask for TIMER_DTFC */ + +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /* Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL /* Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /* Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /* Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /* Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /* Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /* Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /* Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /* Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /* Shifted mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /* Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL /* Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /* Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /* Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /* Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /* Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /* Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /* Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /* Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /* Mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /* Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /* Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /* Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /* Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /* Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /* Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /* Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /* Shifted mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /* Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /* Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /* Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /* Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /* Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /* Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /* Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /* Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /* Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /* Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /* DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /* Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /* Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /* DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /* Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /* Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /* DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /* Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /* Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /* Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /* DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /* Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /* Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /* Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ + +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /* Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /* Mask for TIMER_DTOGEN */ + +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /* DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /* Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /* Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /* DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /* Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /* Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /* DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /* Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /* Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /* DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /* Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /* Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /* Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /* DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /* Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /* Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /* Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /* DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /* Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /* Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /* Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ + +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /* Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /* Mask for TIMER_DTFAULT */ + +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /* DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /* Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /* Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /* DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /* Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /* Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /* DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /* Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /* Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /* DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /* Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /* Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /* Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ + +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /* Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /* Mask for TIMER_DTFAULTC */ + +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /* DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /* Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /* Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /* DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /* Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /* Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /* Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /* DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /* Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /* Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /* Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /* DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /* Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /* Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /* Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ + +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /* Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /* Mask for TIMER_DTLOCK */ + +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /* Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /* Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /* Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /* Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /* Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /* Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /* Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /* Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /* Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /* Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for TIMER_DTLOCK */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_TIMER_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_usart.h b/nuttx/arch/arm/src/efm32/chip/efm32_usart.h index e2d8fa8f9..6cd1372c3 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_usart.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_usart.h @@ -65,8 +65,13 @@ * Included Files *******************************************************************************************************************************/ +#include <nuttx/config.h> #include "chip/efm32_memorymap.h" +#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G) +# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture +#endif + /******************************************************************************************************************************* * Pre-processor Definitions *******************************************************************************************************************************/ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_usb.h b/nuttx/arch/arm/src/efm32/chip/efm32_usb.h new file mode 100644 index 000000000..f6df7516e --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_usb.h @@ -0,0 +1,3114 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_usb.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USB_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USB_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* USB Register Offsets ********************************************************************************************************/ + +#define EFM32_USB_CTRL_OFFSET 0x00000 /* System Control Register */ +#define EFM32_USB_STATUS_OFFSET 0x00004 /* System Status Register */ +#define EFM32_USB_IF_OFFSET 0x00008 /* Interrupt Flag Register */ +#define EFM32_USB_IFS_OFFSET 0x0000c /* Interrupt Flag Set Register */ +#define EFM32_USB_IFC_OFFSET 0x00010 /* Interrupt Flag Clear Register */ +#define EFM32_USB_IEN_OFFSET 0x00014 /* Interrupt Enable Register */ +#define EFM32_USB_ROUTE_OFFSET 0x00018 /* I/O Routing Register */ + +#define EFM32_USB_GOTGCTL_OFFSET 0x3c000 /* OTG Control and Status Register */ +#define EFM32_USB_GOTGINT_OFFSET 0x3c004 /* OTG Interrupt Register */ +#define EFM32_USB_GAHBCFG_OFFSET 0x3c008 /* AHB Configuration Register */ +#define EFM32_USB_GUSBCFG_OFFSET 0x3c00c /* USB Configuration Register */ +#define EFM32_USB_GRSTCTL_OFFSET 0x3c010 /* Reset Register */ +#define EFM32_USB_GINTSTS_OFFSET 0x3c014 /* Interrupt Register */ +#define EFM32_USB_GINTMSK_OFFSET 0x3c018 /* Interrupt Mask Register */ +#define EFM32_USB_GRXSTSR_OFFSET 0x3c01c /* Receive Status Debug Read Register */ +#define EFM32_USB_GRXSTSP_OFFSET 0x3c020 /* Receive Status Read and Pop Register */ +#define EFM32_USB_GRXFSIZ_OFFSET 0x3c024 /* Receive FIFO Size Register */ +#define EFM32_USB_GNPTXFSIZ_OFFSET 0x3c028 /* Non-periodic Transmit FIFO Size Register */ +#define EFM32_USB_GNPTXSTS_OFFSET 0x3c02c /* Non-periodic Transmit FIFO/Queue Status Register */ +#define EFM32_USB_GDFIFOCFG_OFFSET 0x3c05c /* Global DFIFO Configuration Register */ +#define EFM32_USB_HPTXFSIZ_OFFSET 0x3c100 /* Host Periodic Transmit FIFO Size Register */ + +#define EFM32_USB_DIEPTXF_OFFSET(n) (0x3c104 + ((n) << 2)) +#define EFM32_USB_DIEPTXF1_OFFSET 0x3c104 /* Device IN Endpoint Transmit FIFO 1 Size Register */ +#define EFM32_USB_DIEPTXF2_OFFSET 0x3c108 /* Device IN Endpoint Transmit FIFO 2 Size Register */ +#define EFM32_USB_DIEPTXF3_OFFSET 0x3c10c /* Device IN Endpoint Transmit FIFO 3 Size Register */ +#define EFM32_USB_DIEPTXF4_OFFSET 0x3c110 /* Device IN Endpoint Transmit FIFO 4 Size Register */ +#define EFM32_USB_DIEPTXF5_OFFSET 0x3c114 /* Device IN Endpoint Transmit FIFO 5 Size Register */ +#define EFM32_USB_DIEPTXF6_OFFSET 0x3c118 /* Device IN Endpoint Transmit FIFO 6 Size Register */ + +#define EFM32_USB_HCFG_OFFSET 0x3c400 /* Host Configuration Register */ +#define EFM32_USB_HFIR_OFFSET 0x3c404 /* Host Frame Interval Register */ +#define EFM32_USB_HFNUM_OFFSET 0x3c408 /* Host Frame Number/Frame Time Remaining Register */ +#define EFM32_USB_HPTXSTS_OFFSET 0x3c410 /* Host Periodic Transmit FIFO/Queue Status Register */ +#define EFM32_USB_HAINT_OFFSET 0x3c414 /* Host All Channels Interrupt Register */ +#define EFM32_USB_HAINTMSK_OFFSET 0x3c418 /* Host All Channels Interrupt Mask Register */ +#define EFM32_USB_HPRT_OFFSET 0x3c440 /* Host Port Control and Status Register */ + +#define EFM32_USB_HCn_OFFSET(n) (0x3c500 + ((n) << 5)) +#define EFM32_USB_HC0_OFFSET 0x3c500 /* Host Channel 0 Offset */ +#define EFM32_USB_HC1_OFFSET 0x3c520 /* Host Channel 1 Offset */ +#define EFM32_USB_HC2_OFFSET 0x3c540 /* Host Channel 2 Offset */ +#define EFM32_USB_HC3_OFFSET 0x3c560 /* Host Channel 3 Offset */ +#define EFM32_USB_HC4_OFFSET 0x3c580 /* Host Channel 4 Offset */ +#define EFM32_USB_HC5_OFFSET 0x3c5a0 /* Host Channel 5 Offset */ +#define EFM32_USB_HC6_OFFSET 0x3c5c0 /* Host Channel 6 Offset */ +#define EFM32_USB_HC7_OFFSET 0x3c5e0 /* Host Channel 7 Offset */ +#define EFM32_USB_HC8_OFFSET 0x3c600 /* Host Channel 8 Offset */ +#define EFM32_USB_HC9_OFFSET 0x3c620 /* Host Channel 9 Offset */ +#define EFM32_USB_HC10_OFFSET 0x3c640 /* Host Channel 10 Offset */ +#define EFM32_USB_HC11_OFFSET 0x3c660 /* Host Channel 11 Offset */ +#define EFM32_USB_HC12_OFFSET 0x3c680 /* Host Channel 12 Offset */ +#define EFM32_USB_HC13_OFFSET 0x3c6a0 /* Host Channel 13 Offset */ + +#define EFM32_USB_HCn_CHAR_OFFSET 0x00000 /* Host Channel n Characteristics Register */ +#define EFM32_USB_HCn_INT_OFFSET 0x00008 /* Host Channel n Interrupt Register */ +#define EFM32_USB_HCn_INTMSK_OFFSET 0x0000c /* Host Channel n Interrupt Mask Register */ +#define EFM32_USB_HCn_TSIZ_OFFSET 0x00010 /* Host Channel n Transfer Size Register */ +#define EFM32_USB_HCn_DMAADDR_OFFSET 0x00014 /* Host Channel n DMA Address Register */ + +#define EFM32_USB_DCFG_OFFSET 0x3c800 /* Device Configuration Register */ +#define EFM32_USB_DCTL_OFFSET 0x3c804 /* Device Control Register */ +#define EFM32_USB_DSTS_OFFSET 0x3c808 /* Device Status Register */ +#define EFM32_USB_DIEPMSK_OFFSET 0x3c810 /* Device IN Endpoint Common Interrupt Mask Register */ +#define EFM32_USB_DOEPMSK_OFFSET 0x3c814 /* Device OUT Endpoint Common Interrupt Mask Register */ +#define EFM32_USB_DAINT_OFFSET 0x3c818 /* Device All Endpoints Interrupt Register */ +#define EFM32_USB_DAINTMSK_OFFSET 0x3c81c /* Device All Endpoints Interrupt Mask Register */ +#define EFM32_USB_DVBUSDIS_OFFSET 0x3c828 /* Device VBUS Discharge Time Register */ +#define EFM32_USB_DVBUSPULSE_OFFSET 0x3c82C /* Device VBUS Pulsing Time Register */ +#define EFM32_USB_DIEPEMPMSK_OFFSET 0x3c834 /* Device IN Endpoint FIFO Empty Interrupt Mask Register */ + +#define EFM32_USB_DIEP_OFFSET(n) (0x3c900 + ((n) << 5)) +#define EFM32_USB_DIEP0_OFFSET 0x3c900 /* Device IN Endpoint 0 */ +#define EFM32_USB_DIEP1_OFFSET 0x3c920 /* Device IN Endpoint 1 */ +#define EFM32_USB_DIEP2_OFFSET 0x3c940 /* Device IN Endpoint 2 */ +#define EFM32_USB_DIEP3_OFFSET 0x3c960 /* Device IN Endpoint 3 */ +#define EFM32_USB_DIEP4_OFFSET 0x3c980 /* Device IN Endpoint 4 */ +#define EFM32_USB_DIEP5_OFFSET 0x3c9a0 /* Device IN Endpoint 5 */ +#define EFM32_USB_DIEP6_OFFSET 0x3c9c0 /* Device IN Endpoint 6 */ + +#define EFM32_USB_DIEPn_CTL_OFFSET 0x00000 /* Device IN Endpoint n Control Register */ +#define EFM32_USB_DIEPn_INT_OFFSET 0x00008 /* Device IN Endpoint n Interrupt Register */ +#define EFM32_USB_DIEPn_TSIZ_OFFSET 0x00010 /* Device IN Endpoint n Transfer Size Register */ +#define EFM32_USB_DIEPn_DMAADDR_OFFSET 0x00014 /* Device IN Endpoint n DMA Address Register */ +#define EFM32_USB_DIEPn_TXFSTS_OFFSET 0x00018 /* Device IN Endpoint n Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP0_CTL_OFFSET 0x3c900 /* Device IN Endpoint 0 Control Register */ +#define EFM32_USB_DIEP0_INT_OFFSET 0x3c908 /* Device IN Endpoint 0 Interrupt Register */ +#define EFM32_USB_DIEP0_TSIZ_OFFSET 0x3c910 /* Device IN Endpoint 0 Transfer Size Register */ +#define EFM32_USB_DIEP0_DMAADDR_OFFSET 0x3c914 /* Device IN Endpoint 0 DMA Address Register */ +#define EFM32_USB_DIEP0_TXFSTS_OFFSET 0x3c918 /* Device IN Endpoint 0 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP1_CTL_OFFSET 0x3c920 /* Device IN Endpoint 1 Control Register */ +#define EFM32_USB_DIEP1_INT_OFFSET 0x3c928 /* Device IN Endpoint 1 Interrupt Register */ +#define EFM32_USB_DIEP1_TSIZ_OFFSET 0x3c930 /* Device IN Endpoint 1 Transfer Size Register */ +#define EFM32_USB_DIEP1_DMAADDR_OFFSET 0x3c934 /* Device IN Endpoint 1 DMA Address Register */ +#define EFM32_USB_DIEP1_TXFSTS_OFFSET 0x3c938 /* Device IN Endpoint 1 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP2_CTL_OFFSET 0x3c940 /* Device IN Endpoint 2 Control Register */ +#define EFM32_USB_DIEP2_INT_OFFSET 0x3c948 /* Device IN Endpoint 2 Interrupt Register */ +#define EFM32_USB_DIEP2_TSIZ_OFFSET 0x3c950 /* Device IN Endpoint 2 Transfer Size Register */ +#define EFM32_USB_DIEP2_DMAADDR_OFFSET 0x3c954 /* Device IN Endpoint 2 DMA Address Register */ +#define EFM32_USB_DIEP2_TXFSTS_OFFSET 0x3c958 /* Device IN Endpoint 2 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP3_CTL_OFFSET 0x3c960 /* Device IN Endpoint 3 Control Register */ +#define EFM32_USB_DIEP3_INT_OFFSET 0x3c968 /* Device IN Endpoint 3 Interrupt Register */ +#define EFM32_USB_DIEP3_TSIZ_OFFSET 0x3c970 /* Device IN Endpoint 3 Transfer Size Register */ +#define EFM32_USB_DIEP3_DMAADDR_OFFSET 0x3c974 /* Device IN Endpoint 3 DMA Address Register */ +#define EFM32_USB_DIEP3_TXFSTS_OFFSET 0x3c978 /* Device IN Endpoint 3 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP4_CTL_OFFSET 0x3c980 /* Device IN Endpoint 4 Control Register */ +#define EFM32_USB_DIEP4_INT_OFFSET 0x3c988 /* Device IN Endpoint 4 Interrupt Register */ +#define EFM32_USB_DIEP4_TSIZ_OFFSET 0x3c990 /* Device IN Endpoint 4 Transfer Size Register */ +#define EFM32_USB_DIEP4_DMAADDR_OFFSET 0x3c994 /* Device IN Endpoint 4 DMA Address Register */ +#define EFM32_USB_DIEP4_TXFSTS_OFFSET 0x3c998 /* Device IN Endpoint 4 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP5_CTL_OFFSET 0x3c9a0 /* Device IN Endpoint 5 Control Register */ +#define EFM32_USB_DIEP5_INT_OFFSET 0x3c9a8 /* Device IN Endpoint 5 Interrupt Register */ +#define EFM32_USB_DIEP5_TSIZ_OFFSET 0x3c9b0 /* Device IN Endpoint 5 Transfer Size Register */ +#define EFM32_USB_DIEP5_DMAADDR_OFFSET 0x3c9b4 /* Device IN Endpoint 5 DMA Address Register */ +#define EFM32_USB_DIEP5_TXFSTS_OFFSET 0x3c9b8 /* Device IN Endpoint 5 Transmit FIFO Status Register */ + +#define EFM32_USB_DIEP6_CTL_OFFSET 0x3c9c0 /* Device IN Endpoint 6 Control Register */ +#define EFM32_USB_DIEP6_INT_OFFSET 0x3c9c8 /* Device IN Endpoint 6 Interrupt Register */ +#define EFM32_USB_DIEP6_TSIZ_OFFSET 0x3c9d0 /* Device IN Endpoint 6 Transfer Size Register */ +#define EFM32_USB_DIEP6_DMAADDR_OFFSET 0x3c9d4 /* Device IN Endpoint 6 DMA Address Register */ +#define EFM32_USB_DIEP6_TXFSTS_OFFSET 0x3c9d8 /* Device IN Endpoint 6 Transmit FIFO Status Register */ + +#define EFM32_USB_DOEP_OFFSET(n) (0x3c900 + ((n) << 5)) +#define EFM32_USB_DOEP0_OFFSET 0x3c900 /* Device OUT Endpoint 0 */ +#define EFM32_USB_DOEP1_OFFSET 0x3c920 /* Device OUT Endpoint 1 */ +#define EFM32_USB_DOEP2_OFFSET 0x3c940 /* Device OUT Endpoint 2 */ +#define EFM32_USB_DOEP3_OFFSET 0x3c960 /* Device OUT Endpoint 3 */ +#define EFM32_USB_DOEP4_OFFSET 0x3c980 /* Device OUT Endpoint 4 */ +#define EFM32_USB_DOEP5_OFFSET 0x3c9a0 /* Device OUT Endpoint 5 */ +#define EFM32_USB_DOEP6_OFFSET 0x3c9c0 /* Device OUT Endpoint 6 */ + +#define EFM32_USB_DOEPn_CTL_OFFSET 0x00000 /* Device OUT Endpoint n Control Register */ +#define EFM32_USB_DOEPn_INT_OFFSET 0x00008 /* Device OUT Endpoint n Interrupt Register */ +#define EFM32_USB_DOEPn_TSIZ_OFFSET 0x00010 /* Device OUT Endpoint n Transfer Size Register */ +#define EFM32_USB_DOEPn_DMAADDR_OFFSET 0x00014 /* Device OUT Endpoint n DMA Address Register */ + +#define EFM32_USB_DOEP0_CTL_OFFSET 0x3cb00 /* Device OUT Endpoint 0 Control Register */ +#define EFM32_USB_DOEP0_INT_OFFSET 0x3cb08 /* Device OUT Endpoint 0 Interrupt Register */ +#define EFM32_USB_DOEP0_TSIZ_OFFSET 0x3cb10 /* Device OUT Endpoint 0 Transfer Size Register */ +#define EFM32_USB_DOEP0_DMAADDR_OFFSET 0x3cb14 /* Device OUT Endpoint 0 DMA Address Register */ + +#define EFM32_USB_DOEP1_CTL_OFFSET 0x3cb20 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP1_INT_OFFSET 0x3cb28 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP1_TSIZ_OFFSET 0x3cb30 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP1_DMAADDR_OFFSET 0x3cb34 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_DOEP2_CTL_OFFSET 0x3cb40 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP2_INT_OFFSET 0x3cb48 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP2_TSIZ_OFFSET 0x3cb50 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP2_DMAADDR_OFFSET 0x3cb54 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_DOEP3_CTL_OFFSET 0x3cb60 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP3_INT_OFFSET 0x3cb68 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP3_TSIZ_OFFSET 0x3cb70 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP3_DMAADDR_OFFSET 0x3cb74 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_DOEP4_CTL_OFFSET 0x3cb80 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP4_INT_OFFSET 0x3cb88 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP4_TSIZ_OFFSET 0x3cb90 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP4_DMAADDR_OFFSET 0x3cb94 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_DOEP5_CTL_OFFSET 0x3cba0 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP5_INT_OFFSET 0x3cba8 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP5_TSIZ_OFFSET 0x3cbb0 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP5_DMAADDR_OFFSET 0x3cbb4 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_DOEP6_CTL_OFFSET 0x3cbc0 /* Device OUT Endpoint x Control Register */ +#define EFM32_USB_DOEP6_INT_OFFSET 0x3cbc8 /* Device OUT Endpoint x Interrupt Register */ +#define EFM32_USB_DOEP6_TSIZ_OFFSET 0x3cbd0 /* Device OUT Endpoint x Transfer Size Register */ +#define EFM32_USB_DOEP6_DMAADDR_OFFSET 0x3cbd4 /* Device OUT Endpoint x DMA Address Register */ + +#define EFM32_USB_PCGCCTL_OFFSET 0x3ce00 /* Power and Clock Gating Control Register */ + +/* Device EP/Host Channel FIFOs */ + +#define EFM32_USB_FIFO_OFFSET(n) (0x3d000 + ((n) << 12)) +#define EFM32_USB_FIFO0_OFFSET 0x3d000 +#define EFM32_USB_FIFO1_OFFSET 0x3e000 +#define EFM32_USB_FIFO2_OFFSET 0x3f000 +#define EFM32_USB_FIFO3_OFFSET 0x40000 +#define EFM32_USB_FIFO4_OFFSET 0x41000 +#define EFM32_USB_FIFO5_OFFSET 0x42000 +#define EFM32_USB_FIFO6_OFFSET 0x43000 +#define EFM32_USB_FIFO7_OFFSET 0x44000 +#define EFM32_USB_FIFO8_OFFSET 0x45000 +#define EFM32_USB_FIFO9_OFFSET 0x46000 +#define EFM32_USB_FIFO10_OFFSET 0x47000 +#define EFM32_USB_FIFO11_OFFSET 0x48000 +#define EFM32_USB_FIFO12_OFFSET 0x49000 +#define EFM32_USB_FIFO13_OFFSET 0x4a000 + +#define EFM32_USB_FIFOD_OFFSET(n,d) (EFM32_USB_FIFO_OFFSET(n) + ((d) << 2)) +#define EFM32_FIFORAM_OFFSET(d) (0x5c000 + ((d) << 2)) + +/* USB Register Addresses ******************************************************************************************************/ + +#define EFM32_USB_CTRL (EFM32_USB_BASE+EFM32_USB_CTRL_OFFSET) +#define EFM32_USB_STATUS (EFM32_USB_BASE+EFM32_USB_STATUS_OFFSET) +#define EFM32_USB_IF (EFM32_USB_BASE+EFM32_USB_IF_OFFSET) +#define EFM32_USB_IFS (EFM32_USB_BASE+EFM32_USB_IFS_OFFSET) +#define EFM32_USB_IFC (EFM32_USB_BASE+EFM32_USB_IFC_OFFSET) +#define EFM32_USB_IEN (EFM32_USB_BASE+EFM32_USB_IEN_OFFSET) +#define EFM32_USB_ROUTE (EFM32_USB_BASE+EFM32_USB_ROUTE_OFFSET) + +#define EFM32_USB_GOTGCTL (EFM32_USB_BASE+EFM32_USB_GOTGCTL_OFFSET) +#define EFM32_USB_GOTGINT (EFM32_USB_BASE+EFM32_USB_GOTGINT_OFFSET) +#define EFM32_USB_GAHBCFG (EFM32_USB_BASE+EFM32_USB_GAHBCFG_OFFSET) +#define EFM32_USB_GUSBCFG (EFM32_USB_BASE+EFM32_USB_GUSBCFG_OFFSET) +#define EFM32_USB_GRSTCTL (EFM32_USB_BASE+EFM32_USB_GRSTCTL_OFFSET) +#define EFM32_USB_GINTSTS (EFM32_USB_BASE+EFM32_USB_GINTSTS_OFFSET) +#define EFM32_USB_GINTMSK (EFM32_USB_BASE+EFM32_USB_GINTMSK_OFFSET) +#define EFM32_USB_GRXSTSR (EFM32_USB_BASE+EFM32_USB_GRXSTSR_OFFSET) +#define EFM32_USB_GRXSTSP (EFM32_USB_BASE+EFM32_USB_GRXSTSP_OFFSET) +#define EFM32_USB_GRXFSIZ (EFM32_USB_BASE+EFM32_USB_GRXFSIZ_OFFSET) +#define EFM32_USB_GNPTXFSIZ (EFM32_USB_BASE+EFM32_USB_GNPTXFSIZ_OFFSET) +#define EFM32_USB_GNPTXSTS (EFM32_USB_BASE+EFM32_USB_GNPTXSTS_OFFSET) +#define EFM32_USB_GDFIFOCFG (EFM32_USB_BASE+EFM32_USB_GDFIFOCFG_OFFSET) +#define EFM32_USB_HPTXFSIZ (EFM32_USB_BASE+EFM32_USB_HPTXFSIZ_OFFSET) + +#define EFM32_USB_DIEPTXF_BASE(n) (EFM32_USB_BASE+EFM32_USB_DIEPTXF_OFFSET(n)) +#define EFM32_USB_DIEPTXF1_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF1_OFFSET) +#define EFM32_USB_DIEPTXF2_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF2_OFFSET) +#define EFM32_USB_DIEPTXF3_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF3_OFFSET) +#define EFM32_USB_DIEPTXF4_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF4_OFFSET) +#define EFM32_USB_DIEPTXF5_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF5_OFFSET) +#define EFM32_USB_DIEPTXF6_BASE (EFM32_USB_BASE+EFM32_USB_DIEPTXF6_OFFSET) + +#define EFM32_USB_HCFG (EFM32_USB_BASE+EFM32_USB_HCFG_OFFSET) +#define EFM32_USB_HFIR (EFM32_USB_BASE+EFM32_USB_HFIR_OFFSET) +#define EFM32_USB_HFNUM (EFM32_USB_BASE+EFM32_USB_HFNUM_OFFSET) +#define EFM32_USB_HPTXSTS (EFM32_USB_BASE+EFM32_USB_HPTXSTS_OFFSET) +#define EFM32_USB_HAINT (EFM32_USB_BASE+EFM32_USB_HAINT_OFFSET) +#define EFM32_USB_HAINTMSK (EFM32_USB_BASE+EFM32_USB_HAINTMSK_OFFSET) +#define EFM32_USB_HPRT (EFM32_USB_BASE+EFM32_USB_HPRT_OFFSET) + +#define EFM32_USB_HCn_BASE(n) (EFM32_USB_BASE+EFM32_USB_HCn_OFFSET(n)) +#define EFM32_USB_HC0_BASE (EFM32_USB_BASE+EFM32_USB_HC0_OFFSET) +#define EFM32_USB_HC1_BASE (EFM32_USB_BASE+EFM32_USB_HC1_OFFSET) +#define EFM32_USB_HC2_BASE (EFM32_USB_BASE+EFM32_USB_HC2_OFFSET) +#define EFM32_USB_HC3_BASE (EFM32_USB_BASE+EFM32_USB_HC3_OFFSET) +#define EFM32_USB_HC4_BASE (EFM32_USB_BASE+EFM32_USB_HC4_OFFSET) +#define EFM32_USB_HC5_BASE (EFM32_USB_BASE+EFM32_USB_HC5_OFFSET) +#define EFM32_USB_HC6_BASE (EFM32_USB_BASE+EFM32_USB_HC6_OFFSET) +#define EFM32_USB_HC7_BASE (EFM32_USB_BASE+EFM32_USB_HC7_OFFSET) +#define EFM32_USB_HC8_BASE (EFM32_USB_BASE+EFM32_USB_HC8_OFFSET) +#define EFM32_USB_HC9_BASE (EFM32_USB_BASE+EFM32_USB_HC9_OFFSET) +#define EFM32_USB_HC10_BASE (EFM32_USB_BASE+EFM32_USB_HC10_OFFSET) +#define EFM32_USB_HC11_BASE (EFM32_USB_BASE+EFM32_USB_HC11_OFFSET) +#define EFM32_USB_HC12_BASE (EFM32_USB_BASE+EFM32_USB_HC12_OFFSET) +#define EFM32_USB_HC13_BASE (EFM32_USB_BASE+EFM32_USB_HC13_OFFSET) + +#define EFM32_USB_HCn_CHAR(n) (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_CHAR_OFFSET) +#define EFM32_USB_HCn_INT(n) (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_INT_OFFSET) +#define EFM32_USB_HCn_INTMSK(n) (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_INTMSK_OFFSET) +#define EFM32_USB_HCn_TSIZ(n) (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_TSIZ_OFFSET) +#define EFM32_USB_HCn_DMAADDR(n) (EFM32_USB_HCn_BASE(n)+EFM32_USB_HCn_DMAADDR_OFFSET) + +#define EFM32_USB_DCFG (EFM32_USB_BASE+EFM32_USB_DCFG_OFFSET) +#define EFM32_USB_DCTL (EFM32_USB_BASE+EFM32_USB_DCTL_OFFSET) +#define EFM32_USB_DSTS (EFM32_USB_BASE+EFM32_USB_DSTS_OFFSET) +#define EFM32_USB_DIEPMSK (EFM32_USB_BASE+EFM32_USB_DIEPMSK_OFFSET) +#define EFM32_USB_DOEPMSK (EFM32_USB_BASE+EFM32_USB_DOEPMSK_OFFSET) +#define EFM32_USB_DAINT (EFM32_USB_BASE+EFM32_USB_DAINT_OFFSET) +#define EFM32_USB_DAINTMSK (EFM32_USB_BASE+EFM32_USB_DAINTMSK_OFFSET) +#define EFM32_USB_DVBUSDIS (EFM32_USB_BASE+EFM32_USB_DVBUSDIS_OFFSET) +#define EFM32_USB_DVBUSPULSE (EFM32_USB_BASE+EFM32_USB_DVBUSPULSE_OFFSET) +#define EFM32_USB_DIEPEMPMSK (EFM32_USB_BASE+EFM32_USB_DIEPEMPMSK_OFFSET) + +#define EFM32_USB_DIEP_BASE(n) (EFM32_USB_BASE+EFM32_USB_DIEP_OFFSET(n)) +#define EFM32_USB_DIEP0_BASE (EFM32_USB_BASE+EFM32_USB_DIEP0_OFFSET) +#define EFM32_USB_DIEP1_BASE (EFM32_USB_BASE+EFM32_USB_DIEP1_OFFSET) +#define EFM32_USB_DIEP2_BASE (EFM32_USB_BASE+EFM32_USB_DIEP2_OFFSET) +#define EFM32_USB_DIEP3_BASE (EFM32_USB_BASE+EFM32_USB_DIEP3_OFFSET) +#define EFM32_USB_DIEP4_BASE (EFM32_USB_BASE+EFM32_USB_DIEP4_OFFSET) +#define EFM32_USB_DIEP5_BASE (EFM32_USB_BASE+EFM32_USB_DIEP5_OFFSET) +#define EFM32_USB_DIEP6_BASE (EFM32_USB_BASE+EFM32_USB_DIEP6_OFFSET) + +#define EFM32_USB_DIEP_CTL(n) (EFM32_USB_DIEP_BASE(n)+EFM32_USB_DIEPn_CTL_OFFSET) +#define EFM32_USB_DIEP_INT(n) (EFM32_USB_DIEP_BASE(n)+EFM32_USB_DIEPn_INT_OFFSET) +#define EFM32_USB_DIEP_TSIZ(n) (EFM32_USB_DIEP_BASE(n)+EFM32_USB_DIEPn_TSIZ_OFFSET) +#define EFM32_USB_DIEP_DMAADDR(n) (EFM32_USB_DIEP_BASE(n)+EFM32_USB_DIEPn_DMAADDR_OFFSET) +#define EFM32_USB_DIEP_TXFSTS(n) (EFM32_USB_DIEP_BASE(n)+EFM32_USB_DIEPn_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP0_CTL (EFM32_USB_BASE+EFM32_USB_DIEP0_CTL_OFFSET) +#define EFM32_USB_DIEP0_INT (EFM32_USB_BASE+EFM32_USB_DIEP0_INT_OFFSET) +#define EFM32_USB_DIEP0_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP0_TSIZ_OFFSET) +#define EFM32_USB_DIEP0_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP0_DMAADDR_OFFSET) +#define EFM32_USB_DIEP0_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP0_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP1_CTL (EFM32_USB_BASE+EFM32_USB_DIEP1_CTL_OFFSET) +#define EFM32_USB_DIEP1_INT (EFM32_USB_BASE+EFM32_USB_DIEP1_INT_OFFSET) +#define EFM32_USB_DIEP1_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP1_TSIZ_OFFSET) +#define EFM32_USB_DIEP1_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP1_DMAADDR_OFFSET) +#define EFM32_USB_DIEP1_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP1_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP2_CTL (EFM32_USB_BASE+EFM32_USB_DIEP2_CTL_OFFSET) +#define EFM32_USB_DIEP2_INT (EFM32_USB_BASE+EFM32_USB_DIEP2_INT_OFFSET) +#define EFM32_USB_DIEP2_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP2_TSIZ_OFFSET) +#define EFM32_USB_DIEP2_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP2_DMAADDR_OFFSET) +#define EFM32_USB_DIEP2_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP2_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP3_CTL (EFM32_USB_BASE+EFM32_USB_DIEP3_CTL_OFFSET) +#define EFM32_USB_DIEP3_INT (EFM32_USB_BASE+EFM32_USB_DIEP3_INT_OFFSET) +#define EFM32_USB_DIEP3_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP3_TSIZ_OFFSET) +#define EFM32_USB_DIEP3_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP3_DMAADDR_OFFSET) +#define EFM32_USB_DIEP3_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP3_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP4_CTL (EFM32_USB_BASE+EFM32_USB_DIEP4_CTL_OFFSET) +#define EFM32_USB_DIEP4_INT (EFM32_USB_BASE+EFM32_USB_DIEP4_INT_OFFSET) +#define EFM32_USB_DIEP4_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP4_TSIZ_OFFSET) +#define EFM32_USB_DIEP4_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP4_DMAADDR_OFFSET) +#define EFM32_USB_DIEP4_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP4_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP5_CTL (EFM32_USB_BASE+EFM32_USB_DIEP5_CTL_OFFSET) +#define EFM32_USB_DIEP5_INT (EFM32_USB_BASE+EFM32_USB_DIEP5_INT_OFFSET) +#define EFM32_USB_DIEP5_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP5_TSIZ_OFFSET) +#define EFM32_USB_DIEP5_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP5_DMAADDR_OFFSET) +#define EFM32_USB_DIEP5_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP5_TXFSTS_OFFSET) + +#define EFM32_USB_DIEP6_CTL (EFM32_USB_BASE+EFM32_USB_DIEP6_CTL_OFFSET) +#define EFM32_USB_DIEP6_INT (EFM32_USB_BASE+EFM32_USB_DIEP6_INT_OFFSET) +#define EFM32_USB_DIEP6_TSIZ (EFM32_USB_BASE+EFM32_USB_DIEP6_TSIZ_OFFSET) +#define EFM32_USB_DIEP6_DMAADDR (EFM32_USB_BASE+EFM32_USB_DIEP6_DMAADDR_OFFSET) +#define EFM32_USB_DIEP6_TXFSTS (EFM32_USB_BASE+EFM32_USB_DIEP6_TXFSTS_OFFSET) + +#define EFM32_USB_DOEP_BASE(n) (EFM32_USB_BASE+EFM32_USB_DOEP_OFFSET(n)) +#define EFM32_USB_DOEP0_BASE (EFM32_USB_BASE+EFM32_USB_DOEP0_OFFSET) +#define EFM32_USB_DOEP1_BASE (EFM32_USB_BASE+EFM32_USB_DOEP1_OFFSET) +#define EFM32_USB_DOEP2_BASE (EFM32_USB_BASE+EFM32_USB_DOEP2_OFFSET) +#define EFM32_USB_DOEP3_BASE (EFM32_USB_BASE+EFM32_USB_DOEP3_OFFSET) +#define EFM32_USB_DOEP4_BASE (EFM32_USB_BASE+EFM32_USB_DOEP4_OFFSET) +#define EFM32_USB_DOEP5_BASE (EFM32_USB_BASE+EFM32_USB_DOEP5_OFFSET) +#define EFM32_USB_DOEP6_BASE (EFM32_USB_BASE+EFM32_USB_DOEP6_OFFSET) + +#define EFM32_USB_DOEP_CTL(n) (EFM32_USB_DOEP_BASE(n)+EFM32_USB_DOEPn_CTL_OFFSET) +#define EFM32_USB_DOEP_INT(n) (EFM32_USB_DOEP_BASE(n)+EFM32_USB_DOEPn_INT_OFFSET) +#define EFM32_USB_DOEP_TSIZ(n) (EFM32_USB_DOEP_BASE(n)+EFM32_USB_DOEPn_TSIZ_OFFSET) +#define EFM32_USB_DOEP_DMAADDR(n) (EFM32_USB_DOEP_BASE(n)+EFM32_USB_DOEPn_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP0_CTL (EFM32_USB_BASE+EFM32_USB_DOEP0_CTL_OFFSET) +#define EFM32_USB_DOEP0_INT (EFM32_USB_BASE+EFM32_USB_DOEP0_INT_OFFSET) +#define EFM32_USB_DOEP0_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP0_TSIZ_OFFSET) +#define EFM32_USB_DOEP0_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP0_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP1_CTL (EFM32_USB_BASE+EFM32_USB_DOEP1_CTL_OFFSET) +#define EFM32_USB_DOEP1_INT (EFM32_USB_BASE+EFM32_USB_DOEP1_INT_OFFSET) +#define EFM32_USB_DOEP1_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP1_TSIZ_OFFSET) +#define EFM32_USB_DOEP1_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP1_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP2_CTL (EFM32_USB_BASE+EFM32_USB_DOEP2_CTL_OFFSET) +#define EFM32_USB_DOEP2_INT (EFM32_USB_BASE+EFM32_USB_DOEP2_INT_OFFSET) +#define EFM32_USB_DOEP2_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP2_TSIZ_OFFSET) +#define EFM32_USB_DOEP2_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP2_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP3_CTL (EFM32_USB_BASE+EFM32_USB_DOEP3_CTL_OFFSET) +#define EFM32_USB_DOEP3_INT (EFM32_USB_BASE+EFM32_USB_DOEP3_INT_OFFSET) +#define EFM32_USB_DOEP3_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP3_TSIZ_OFFSET) +#define EFM32_USB_DOEP3_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP3_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP4_CTL (EFM32_USB_BASE+EFM32_USB_DOEP4_CTL_OFFSET) +#define EFM32_USB_DOEP4_INT (EFM32_USB_BASE+EFM32_USB_DOEP4_INT_OFFSET) +#define EFM32_USB_DOEP4_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP4_TSIZ_OFFSET) +#define EFM32_USB_DOEP4_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP4_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP5_CTL (EFM32_USB_BASE+EFM32_USB_DOEP5_CTL_OFFSET) +#define EFM32_USB_DOEP5_INT (EFM32_USB_BASE+EFM32_USB_DOEP5_INT_OFFSET) +#define EFM32_USB_DOEP5_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP5_TSIZ_OFFSET) +#define EFM32_USB_DOEP5_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP5_DMAADDR_OFFSET) + +#define EFM32_USB_DOEP6_CTL (EFM32_USB_BASE+EFM32_USB_DOEP6_CTL_OFFSET) +#define EFM32_USB_DOEP6_INT (EFM32_USB_BASE+EFM32_USB_DOEP6_INT_OFFSET) +#define EFM32_USB_DOEP6_TSIZ (EFM32_USB_BASE+EFM32_USB_DOEP6_TSIZ_OFFSET) +#define EFM32_USB_DOEP6_DMAADDR (EFM32_USB_BASE+EFM32_USB_DOEP6_DMAADDR_OFFSET) + +#define EFM32_USB_PCGCCTL (EFM32_USB_BASE+EFM32_USB_PCGCCTL_OFFSET) + +/* Device EP/Host Channel FIFOs */ + +#define EFM32_USB_FIFO_BASE(n) (EFM32_USB_BASE+EFM32_USB_FIFO_OFFSET(n)) +#define EFM32_USB_FIFO0_BASE (EFM32_USB_BASE+EFM32_USB_FIFO0_OFFSET) +#define EFM32_USB_FIFO1_BASE (EFM32_USB_BASE+EFM32_USB_FIFO1_OFFSET) +#define EFM32_USB_FIFO2_BASE (EFM32_USB_BASE+EFM32_USB_FIFO2_OFFSET) +#define EFM32_USB_FIFO3_BASE (EFM32_USB_BASE+EFM32_USB_FIFO3_OFFSET) +#define EFM32_USB_FIFO4_BASE (EFM32_USB_BASE+EFM32_USB_FIFO4_OFFSET) +#define EFM32_USB_FIFO5_BASE (EFM32_USB_BASE+EFM32_USB_FIFO5_OFFSET) +#define EFM32_USB_FIFO6_BASE (EFM32_USB_BASE+EFM32_USB_FIFO6_OFFSET) +#define EFM32_USB_FIFO7_BASE (EFM32_USB_BASE+EFM32_USB_FIFO7_OFFSET) +#define EFM32_USB_FIFO8_BASE (EFM32_USB_BASE+EFM32_USB_FIFO8_OFFSET) +#define EFM32_USB_FIFO9_BASE (EFM32_USB_BASE+EFM32_USB_FIFO9_OFFSET) +#define EFM32_USB_FIFO10_BASE (EFM32_USB_BASE+EFM32_USB_FIFO10_OFFSET) +#define EFM32_USB_FIFO11_BASE (EFM32_USB_BASE+EFM32_USB_FIFO11_OFFSET) +#define EFM32_USB_FIFO12_BASE (EFM32_USB_BASE+EFM32_USB_FIFO12_OFFSET) +#define EFM32_USB_FIFO13_BASE (EFM32_USB_BASE+EFM32_USB_FIFO13_OFFSET) + +#define EFM32_USB_FIFOD(n,d) (EFM32_USB_BASE+EFM32_USB_FIFOD_OFFSET(n,d)) +#define EFM32_FIFORAM(d) (EFM32_USB_BASE+EFM32_FIFORAM_OFFSET(d)) + +/* USB Register Bit Field Definitions ******************************************************************************************/ + +/* Bit fields for USB CTRL */ + +#define _USB_CTRL_RESETVALUE 0x00000000UL /* Default value for USB_CTRL */ +#define _USB_CTRL_MASK 0x03330003UL /* Mask for USB_CTRL */ + +#define USB_CTRL_VBUSENAP (0x1UL << 0) /* VBUSEN Active Polarity */ +#define _USB_CTRL_VBUSENAP_SHIFT 0 /* Shift value for USB_VBUSENAP */ +#define _USB_CTRL_VBUSENAP_MASK 0x1UL /* Bit mask for USB_VBUSENAP */ +#define _USB_CTRL_VBUSENAP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_VBUSENAP_LOW 0x00000000UL /* Mode LOW for USB_CTRL */ +#define _USB_CTRL_VBUSENAP_HIGH 0x00000001UL /* Mode HIGH for USB_CTRL */ +#define USB_CTRL_VBUSENAP_DEFAULT (_USB_CTRL_VBUSENAP_DEFAULT << 0) /* Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_VBUSENAP_LOW (_USB_CTRL_VBUSENAP_LOW << 0) /* Shifted mode LOW for USB_CTRL */ +#define USB_CTRL_VBUSENAP_HIGH (_USB_CTRL_VBUSENAP_HIGH << 0) /* Shifted mode HIGH for USB_CTRL */ +#define USB_CTRL_DMPUAP (0x1UL << 1) /* DMPU Active Polarity */ +#define _USB_CTRL_DMPUAP_SHIFT 1 /* Shift value for USB_DMPUAP */ +#define _USB_CTRL_DMPUAP_MASK 0x2UL /* Bit mask for USB_DMPUAP */ +#define _USB_CTRL_DMPUAP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_DMPUAP_LOW 0x00000000UL /* Mode LOW for USB_CTRL */ +#define _USB_CTRL_DMPUAP_HIGH 0x00000001UL /* Mode HIGH for USB_CTRL */ +#define USB_CTRL_DMPUAP_DEFAULT (_USB_CTRL_DMPUAP_DEFAULT << 1) /* Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_DMPUAP_LOW (_USB_CTRL_DMPUAP_LOW << 1) /* Shifted mode LOW for USB_CTRL */ +#define USB_CTRL_DMPUAP_HIGH (_USB_CTRL_DMPUAP_HIGH << 1) /* Shifted mode HIGH for USB_CTRL */ +#define USB_CTRL_VREGDIS (0x1UL << 16) /* Voltage Regulator Disable */ +#define _USB_CTRL_VREGDIS_SHIFT 16 /* Shift value for USB_VREGDIS */ +#define _USB_CTRL_VREGDIS_MASK 0x10000UL /* Bit mask for USB_VREGDIS */ +#define _USB_CTRL_VREGDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_VREGDIS_DEFAULT (_USB_CTRL_VREGDIS_DEFAULT << 16) /* Shifted mode DEFAULT for USB_CTRL */ +#define USB_CTRL_VREGOSEN (0x1UL << 17) /* VREGO Sense Enable */ +#define _USB_CTRL_VREGOSEN_SHIFT 17 /* Shift value for USB_VREGOSEN */ +#define _USB_CTRL_VREGOSEN_MASK 0x20000UL /* Bit mask for USB_VREGOSEN */ +#define _USB_CTRL_VREGOSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_VREGOSEN_DEFAULT (_USB_CTRL_VREGOSEN_DEFAULT << 17) /* Shifted mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_BIASPROGEM01_SHIFT 20 /* Shift value for USB_BIASPROGEM01 */ +#define _USB_CTRL_BIASPROGEM01_MASK 0x300000UL /* Bit mask for USB_BIASPROGEM01 */ +#define _USB_CTRL_BIASPROGEM01_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_BIASPROGEM01_DEFAULT (_USB_CTRL_BIASPROGEM01_DEFAULT << 20) /* Shifted mode DEFAULT for USB_CTRL */ +#define _USB_CTRL_BIASPROGEM23_SHIFT 24 /* Shift value for USB_BIASPROGEM23 */ +#define _USB_CTRL_BIASPROGEM23_MASK 0x3000000UL /* Bit mask for USB_BIASPROGEM23 */ +#define _USB_CTRL_BIASPROGEM23_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_CTRL */ +#define USB_CTRL_BIASPROGEM23_DEFAULT (_USB_CTRL_BIASPROGEM23_DEFAULT << 24) /* Shifted mode DEFAULT for USB_CTRL */ + +/* Bit fields for USB STATUS */ + +#define _USB_STATUS_RESETVALUE 0x00000000UL /* Default value for USB_STATUS */ +#define _USB_STATUS_MASK 0x00000001UL /* Mask for USB_STATUS */ + +#define USB_STATUS_VREGOS (0x1UL << 0) /* VREGO Sense Output */ +#define _USB_STATUS_VREGOS_SHIFT 0 /* Shift value for USB_VREGOS */ +#define _USB_STATUS_VREGOS_MASK 0x1UL /* Bit mask for USB_VREGOS */ +#define _USB_STATUS_VREGOS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_STATUS */ +#define USB_STATUS_VREGOS_DEFAULT (_USB_STATUS_VREGOS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_STATUS */ + +/* Bit fields for USB IF */ + +#define _USB_IF_RESETVALUE 0x00000003UL /* Default value for USB_IF */ +#define _USB_IF_MASK 0x00000003UL /* Mask for USB_IF */ + +#define USB_IF_VREGOSH (0x1UL << 0) /* VREGO Sense High Interrupt Flag */ +#define _USB_IF_VREGOSH_SHIFT 0 /* Shift value for USB_VREGOSH */ +#define _USB_IF_VREGOSH_MASK 0x1UL /* Bit mask for USB_VREGOSH */ +#define _USB_IF_VREGOSH_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_IF */ +#define USB_IF_VREGOSH_DEFAULT (_USB_IF_VREGOSH_DEFAULT << 0) /* Shifted mode DEFAULT for USB_IF */ +#define USB_IF_VREGOSL (0x1UL << 1) /* VREGO Sense Low Interrupt Flag */ +#define _USB_IF_VREGOSL_SHIFT 1 /* Shift value for USB_VREGOSL */ +#define _USB_IF_VREGOSL_MASK 0x2UL /* Bit mask for USB_VREGOSL */ +#define _USB_IF_VREGOSL_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_IF */ +#define USB_IF_VREGOSL_DEFAULT (_USB_IF_VREGOSL_DEFAULT << 1) /* Shifted mode DEFAULT for USB_IF */ + +/* Bit fields for USB IFS */ + +#define _USB_IFS_RESETVALUE 0x00000000UL /* Default value for USB_IFS */ +#define _USB_IFS_MASK 0x00000003UL /* Mask for USB_IFS */ + +#define USB_IFS_VREGOSH (0x1UL << 0) /* Set VREGO Sense High Interrupt Flag */ +#define _USB_IFS_VREGOSH_SHIFT 0 /* Shift value for USB_VREGOSH */ +#define _USB_IFS_VREGOSH_MASK 0x1UL /* Bit mask for USB_VREGOSH */ +#define _USB_IFS_VREGOSH_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IFS */ +#define USB_IFS_VREGOSH_DEFAULT (_USB_IFS_VREGOSH_DEFAULT << 0) /* Shifted mode DEFAULT for USB_IFS */ +#define USB_IFS_VREGOSL (0x1UL << 1) /* Set VREGO Sense Low Interrupt Flag */ +#define _USB_IFS_VREGOSL_SHIFT 1 /* Shift value for USB_VREGOSL */ +#define _USB_IFS_VREGOSL_MASK 0x2UL /* Bit mask for USB_VREGOSL */ +#define _USB_IFS_VREGOSL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IFS */ +#define USB_IFS_VREGOSL_DEFAULT (_USB_IFS_VREGOSL_DEFAULT << 1) /* Shifted mode DEFAULT for USB_IFS */ + +/* Bit fields for USB IFC */ + +#define _USB_IFC_RESETVALUE 0x00000000UL /* Default value for USB_IFC */ +#define _USB_IFC_MASK 0x00000003UL /* Mask for USB_IFC */ + +#define USB_IFC_VREGOSH (0x1UL << 0) /* Clear VREGO Sense High Interrupt Flag */ +#define _USB_IFC_VREGOSH_SHIFT 0 /* Shift value for USB_VREGOSH */ +#define _USB_IFC_VREGOSH_MASK 0x1UL /* Bit mask for USB_VREGOSH */ +#define _USB_IFC_VREGOSH_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IFC */ +#define USB_IFC_VREGOSH_DEFAULT (_USB_IFC_VREGOSH_DEFAULT << 0) /* Shifted mode DEFAULT for USB_IFC */ +#define USB_IFC_VREGOSL (0x1UL << 1) /* Clear VREGO Sense Low Interrupt Flag */ +#define _USB_IFC_VREGOSL_SHIFT 1 /* Shift value for USB_VREGOSL */ +#define _USB_IFC_VREGOSL_MASK 0x2UL /* Bit mask for USB_VREGOSL */ +#define _USB_IFC_VREGOSL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IFC */ +#define USB_IFC_VREGOSL_DEFAULT (_USB_IFC_VREGOSL_DEFAULT << 1) /* Shifted mode DEFAULT for USB_IFC */ + +/* Bit fields for USB IEN */ + +#define _USB_IEN_RESETVALUE 0x00000000UL /* Default value for USB_IEN */ +#define _USB_IEN_MASK 0x00000003UL /* Mask for USB_IEN */ + +#define USB_IEN_VREGOSH (0x1UL << 0) /* VREGO Sense High Interrupt Enable */ +#define _USB_IEN_VREGOSH_SHIFT 0 /* Shift value for USB_VREGOSH */ +#define _USB_IEN_VREGOSH_MASK 0x1UL /* Bit mask for USB_VREGOSH */ +#define _USB_IEN_VREGOSH_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IEN */ +#define USB_IEN_VREGOSH_DEFAULT (_USB_IEN_VREGOSH_DEFAULT << 0) /* Shifted mode DEFAULT for USB_IEN */ +#define USB_IEN_VREGOSL (0x1UL << 1) /* VREGO Sense Low Interrupt Enable */ +#define _USB_IEN_VREGOSL_SHIFT 1 /* Shift value for USB_VREGOSL */ +#define _USB_IEN_VREGOSL_MASK 0x2UL /* Bit mask for USB_VREGOSL */ +#define _USB_IEN_VREGOSL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_IEN */ +#define USB_IEN_VREGOSL_DEFAULT (_USB_IEN_VREGOSL_DEFAULT << 1) /* Shifted mode DEFAULT for USB_IEN */ + +/* Bit fields for USB ROUTE */ + +#define _USB_ROUTE_RESETVALUE 0x00000000UL /* Default value for USB_ROUTE */ +#define _USB_ROUTE_MASK 0x00000007UL /* Mask for USB_ROUTE */ + +#define USB_ROUTE_PHYPEN (0x1UL << 0) /* USB PHY Pin Enable */ +#define _USB_ROUTE_PHYPEN_SHIFT 0 /* Shift value for USB_PHYPEN */ +#define _USB_ROUTE_PHYPEN_MASK 0x1UL /* Bit mask for USB_PHYPEN */ +#define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /* Shifted mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_VBUSENPEN (0x1UL << 1) /* VBUSEN Pin Enable */ +#define _USB_ROUTE_VBUSENPEN_SHIFT 1 /* Shift value for USB_VBUSENPEN */ +#define _USB_ROUTE_VBUSENPEN_MASK 0x2UL /* Bit mask for USB_VBUSENPEN */ +#define _USB_ROUTE_VBUSENPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_VBUSENPEN_DEFAULT (_USB_ROUTE_VBUSENPEN_DEFAULT << 1) /* Shifted mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_DMPUPEN (0x1UL << 2) /* DMPU Pin Enable */ +#define _USB_ROUTE_DMPUPEN_SHIFT 2 /* Shift value for USB_DMPUPEN */ +#define _USB_ROUTE_DMPUPEN_MASK 0x4UL /* Bit mask for USB_DMPUPEN */ +#define _USB_ROUTE_DMPUPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_ROUTE */ +#define USB_ROUTE_DMPUPEN_DEFAULT (_USB_ROUTE_DMPUPEN_DEFAULT << 2) /* Shifted mode DEFAULT for USB_ROUTE */ + +/* Bit fields for USB GOTGCTL */ + +#define _USB_GOTGCTL_RESETVALUE 0x00010000UL /* Default value for USB_GOTGCTL */ +#define _USB_GOTGCTL_MASK 0x001F0FFFUL /* Mask for USB_GOTGCTL */ + +#define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /* Session Request Success (device only) */ +#define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /* Shift value for USB_SESREQSCS */ +#define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /* Bit mask for USB_SESREQSCS */ +#define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQ (0x1UL << 1) /* Session Request (device only) */ +#define _USB_GOTGCTL_SESREQ_SHIFT 1 /* Shift value for USB_SESREQ */ +#define _USB_GOTGCTL_SESREQ_MASK 0x2UL /* Bit mask for USB_SESREQ */ +#define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_SESREQ_DEFAULT (_USB_GOTGCTL_SESREQ_DEFAULT << 1) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVEN (0x1UL << 2) /* VBUS-Valid Override Enable */ +#define _USB_GOTGCTL_VBVALIDOVEN_SHIFT 2 /* Shift value for USB_VBVALIDOVEN */ +#define _USB_GOTGCTL_VBVALIDOVEN_MASK 0x4UL /* Bit mask for USB_VBVALIDOVEN */ +#define _USB_GOTGCTL_VBVALIDOVEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVEN_DEFAULT (_USB_GOTGCTL_VBVALIDOVEN_DEFAULT << 2) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVVAL (0x1UL << 3) /* VBUS Valid Override Value */ +#define _USB_GOTGCTL_VBVALIDOVVAL_SHIFT 3 /* Shift value for USB_VBVALIDOVVAL */ +#define _USB_GOTGCTL_VBVALIDOVVAL_MASK 0x8UL /* Bit mask for USB_VBVALIDOVVAL */ +#define _USB_GOTGCTL_VBVALIDOVVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_VBVALIDOVVAL_DEFAULT (_USB_GOTGCTL_VBVALIDOVVAL_DEFAULT << 3) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVEN (0x1UL << 4) /* BValid Override Enable */ +#define _USB_GOTGCTL_BVALIDOVEN_SHIFT 4 /* Shift value for USB_BVALIDOVEN */ +#define _USB_GOTGCTL_BVALIDOVEN_MASK 0x10UL /* Bit mask for USB_BVALIDOVEN */ +#define _USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVEN_DEFAULT (_USB_GOTGCTL_BVALIDOVEN_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVVAL (0x1UL << 5) /* Bvalid Override Value */ +#define _USB_GOTGCTL_BVALIDOVVAL_SHIFT 5 /* Shift value for USB_BVALIDOVVAL */ +#define _USB_GOTGCTL_BVALIDOVVAL_MASK 0x20UL /* Bit mask for USB_BVALIDOVVAL */ +#define _USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BVALIDOVVAL_DEFAULT (_USB_GOTGCTL_BVALIDOVVAL_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVEN (0x1UL << 6) /* AValid Override Enable */ +#define _USB_GOTGCTL_AVALIDOVEN_SHIFT 6 /* Shift value for USB_AVALIDOVEN */ +#define _USB_GOTGCTL_AVALIDOVEN_MASK 0x40UL /* Bit mask for USB_AVALIDOVEN */ +#define _USB_GOTGCTL_AVALIDOVEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVEN_DEFAULT (_USB_GOTGCTL_AVALIDOVEN_DEFAULT << 6) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVVAL (0x1UL << 7) /* Avalid Override Value */ +#define _USB_GOTGCTL_AVALIDOVVAL_SHIFT 7 /* Shift value for USB_AVALIDOVVAL */ +#define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x80UL /* Bit mask for USB_AVALIDOVVAL */ +#define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /* Host Negotiation Success (device only) */ +#define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /* Shift value for USB_HSTNEGSCS */ +#define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /* Bit mask for USB_HSTNEGSCS */ +#define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HNPREQ (0x1UL << 9) /* HNP Request (device only) */ +#define _USB_GOTGCTL_HNPREQ_SHIFT 9 /* Shift value for USB_HNPREQ */ +#define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /* Bit mask for USB_HNPREQ */ +#define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /* Host Set HNP Enable (host only) */ +#define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /* Shift value for USB_HSTSETHNPEN */ +#define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /* Bit mask for USB_HSTSETHNPEN */ +#define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /* Device HNP Enabled (device only) */ +#define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /* Shift value for USB_DEVHNPEN */ +#define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /* Bit mask for USB_DEVHNPEN */ +#define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /* Connector ID Status (host and device) */ +#define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /* Shift value for USB_CONIDSTS */ +#define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /* Bit mask for USB_CONIDSTS */ +#define _USB_GOTGCTL_CONIDSTS_A 0x00000000UL /* Mode A for USB_GOTGCTL */ +#define _USB_GOTGCTL_CONIDSTS_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_GOTGCTL */ +#define _USB_GOTGCTL_CONIDSTS_B 0x00000001UL /* Mode B for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS_A (_USB_GOTGCTL_CONIDSTS_A << 16) /* Shifted mode A for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_CONIDSTS_B (_USB_GOTGCTL_CONIDSTS_B << 16) /* Shifted mode B for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /* Long/Short Debounce Time (host only) */ +#define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /* Shift value for USB_DBNCTIME */ +#define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /* Bit mask for USB_DBNCTIME */ +#define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define _USB_GOTGCTL_DBNCTIME_LONG 0x00000000UL /* Mode LONG for USB_GOTGCTL */ +#define _USB_GOTGCTL_DBNCTIME_SHORT 0x00000001UL /* Mode SHORT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME_LONG (_USB_GOTGCTL_DBNCTIME_LONG << 17) /* Shifted mode LONG for USB_GOTGCTL */ +#define USB_GOTGCTL_DBNCTIME_SHORT (_USB_GOTGCTL_DBNCTIME_SHORT << 17) /* Shifted mode SHORT for USB_GOTGCTL */ +#define USB_GOTGCTL_ASESVLD (0x1UL << 18) /* A-Session Valid (host only) */ +#define _USB_GOTGCTL_ASESVLD_SHIFT 18 /* Shift value for USB_ASESVLD */ +#define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /* Bit mask for USB_ASESVLD */ +#define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BSESVLD (0x1UL << 19) /* B-Session Valid (device only) */ +#define _USB_GOTGCTL_BSESVLD_SHIFT 19 /* Shift value for USB_BSESVLD */ +#define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /* Bit mask for USB_BSESVLD */ +#define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_BSESVLD_DEFAULT (_USB_GOTGCTL_BSESVLD_DEFAULT << 19) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER (0x1UL << 20) /* OTG Version */ +#define _USB_GOTGCTL_OTGVER_SHIFT 20 /* Shift value for USB_OTGVER */ +#define _USB_GOTGCTL_OTGVER_MASK 0x100000UL /* Bit mask for USB_OTGVER */ +#define _USB_GOTGCTL_OTGVER_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGCTL */ +#define _USB_GOTGCTL_OTGVER_OTG13 0x00000000UL /* Mode OTG13 for USB_GOTGCTL */ +#define _USB_GOTGCTL_OTGVER_OTG20 0x00000001UL /* Mode OTG20 for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER_DEFAULT (_USB_GOTGCTL_OTGVER_DEFAULT << 20) /* Shifted mode DEFAULT for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER_OTG13 (_USB_GOTGCTL_OTGVER_OTG13 << 20) /* Shifted mode OTG13 for USB_GOTGCTL */ +#define USB_GOTGCTL_OTGVER_OTG20 (_USB_GOTGCTL_OTGVER_OTG20 << 20) /* Shifted mode OTG20 for USB_GOTGCTL */ + +/* Bit fields for USB GOTGINT */ + +#define _USB_GOTGINT_RESETVALUE 0x00000000UL /* Default value for USB_GOTGINT */ +#define _USB_GOTGINT_MASK 0x000E0304UL /* Mask for USB_GOTGINT */ + +#define USB_GOTGINT_SESENDDET (0x1UL << 2) /* Session End Detected (host and device) */ +#define _USB_GOTGINT_SESENDDET_SHIFT 2 /* Shift value for USB_SESENDDET */ +#define _USB_GOTGINT_SESENDDET_MASK 0x4UL /* Bit mask for USB_SESENDDET */ +#define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /* Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /* Session Request Success Status Change (host and device) */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /* Shift value for USB_SESREQSUCSTSCHNG */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /* Bit mask for USB_SESREQSUCSTSCHNG */ +#define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /* Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /* Host Negotiation Success Status Change (host and device) */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /* Shift value for USB_HSTNEGSUCSTSCHNG */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /* Bit mask for USB_HSTNEGSUCSTSCHNG */ +#define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /* Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /* Host Negotiation Detected (host and device) */ +#define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /* Shift value for USB_HSTNEGDET */ +#define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /* Bit mask for USB_HSTNEGDET */ +#define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /* Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /* A-Device Timeout Change (host and device) */ +#define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /* Shift value for USB_ADEVTOUTCHG */ +#define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /* Bit mask for USB_ADEVTOUTCHG */ +#define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /* Shifted mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /* Debounce Done (host only) */ +#define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /* Shift value for USB_DBNCEDONE */ +#define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /* Bit mask for USB_DBNCEDONE */ +#define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GOTGINT */ +#define USB_GOTGINT_DBNCEDONE_DEFAULT (_USB_GOTGINT_DBNCEDONE_DEFAULT << 19) /* Shifted mode DEFAULT for USB_GOTGINT */ + +/* Bit fields for USB GAHBCFG */ + +#define _USB_GAHBCFG_RESETVALUE 0x00000000UL /* Default value for USB_GAHBCFG */ +#define _USB_GAHBCFG_MASK 0x006001BFUL /* Mask for USB_GAHBCFG */ + +#define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /* Global Interrupt Mask (host and device) */ +#define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /* Shift value for USB_GLBLINTRMSK */ +#define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /* Bit mask for USB_GLBLINTRMSK */ +#define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /* Shift value for USB_HBSTLEN */ +#define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /* Bit mask for USB_HBSTLEN */ +#define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /* Mode SINGLE for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /* Mode INCR for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /* Mode INCR4 for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /* Mode INCR8 for USB_GAHBCFG */ +#define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /* Mode INCR16 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /* Shifted mode SINGLE for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /* Shifted mode INCR for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /* Shifted mode INCR4 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /* Shifted mode INCR8 for USB_GAHBCFG */ +#define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /* Shifted mode INCR16 for USB_GAHBCFG */ +#define USB_GAHBCFG_DMAEN (0x1UL << 5) /* DMA Enable (host and device) */ +#define _USB_GAHBCFG_DMAEN_SHIFT 5 /* Shift value for USB_DMAEN */ +#define _USB_GAHBCFG_DMAEN_MASK 0x20UL /* Bit mask for USB_DMAEN */ +#define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /* Non-Periodic TxFIFO Empty Level (host and device) */ +#define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /* Shift value for USB_NPTXFEMPLVL */ +#define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /* Bit mask for USB_NPTXFEMPLVL */ +#define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /* Mode HALFEMPTY for USB_GAHBCFG */ +#define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /* Mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /* Shifted mode HALFEMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /* Shifted mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /* Periodic TxFIFO Empty Level (host only) */ +#define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /* Shift value for USB_PTXFEMPLVL */ +#define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /* Bit mask for USB_PTXFEMPLVL */ +#define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define _USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY 0x00000000UL /* Mode HALFEMPTY for USB_GAHBCFG */ +#define _USB_GAHBCFG_PTXFEMPLVL_EMPTY 0x00000001UL /* Mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_DEFAULT (_USB_GAHBCFG_PTXFEMPLVL_DEFAULT << 8) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY << 8) /* Shifted mode HALFEMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_PTXFEMPLVL_EMPTY (_USB_GAHBCFG_PTXFEMPLVL_EMPTY << 8) /* Shifted mode EMPTY for USB_GAHBCFG */ +#define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /* Remote Memory Support */ +#define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /* Shift value for USB_REMMEMSUPP */ +#define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /* Bit mask for USB_REMMEMSUPP */ +#define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /* Shifted mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /* Notify All DMA Writes */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /* Shift value for USB_NOTIALLDMAWRIT */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /* Bit mask for USB_NOTIALLDMAWRIT */ +#define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GAHBCFG */ +#define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /* Shifted mode DEFAULT for USB_GAHBCFG */ + +/* Bit fields for USB GUSBCFG */ + +#define _USB_GUSBCFG_RESETVALUE 0x00001440UL /* Default value for USB_GUSBCFG */ +#define _USB_GUSBCFG_MASK 0xF0403F27UL /* Mask for USB_GUSBCFG */ + +#define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /* Shift value for USB_TOUTCAL */ +#define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /* Bit mask for USB_TOUTCAL */ +#define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FSINTF (0x1UL << 5) /* Full-Speed Serial Interface Select (host and device) */ +#define _USB_GUSBCFG_FSINTF_SHIFT 5 /* Shift value for USB_FSINTF */ +#define _USB_GUSBCFG_FSINTF_MASK 0x20UL /* Bit mask for USB_FSINTF */ +#define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_SRPCAP (0x1UL << 8) /* SRP-Capable (host and device) */ +#define _USB_GUSBCFG_SRPCAP_SHIFT 8 /* Shift value for USB_SRPCAP */ +#define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /* Bit mask for USB_SRPCAP */ +#define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_HNPCAP (0x1UL << 9) /* HNP-Capable (host and device) */ +#define _USB_GUSBCFG_HNPCAP_SHIFT 9 /* Shift value for USB_HNPCAP */ +#define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /* Bit mask for USB_HNPCAP */ +#define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_HNPCAP_DEFAULT (_USB_GUSBCFG_HNPCAP_DEFAULT << 9) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /* Shift value for USB_USBTRDTIM */ +#define _USB_GUSBCFG_USBTRDTIM_MASK 0x3c00UL /* Bit mask for USB_USBTRDTIM */ +#define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /* TermSel DLine Pulsing Selection (device only) */ +#define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /* Shift value for USB_TERMSELDLPULSE */ +#define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /* Bit mask for USB_TERMSELDLPULSE */ +#define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /* Mode TXVALID for USB_GUSBCFG */ +#define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /* Mode TERMSEL for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /* Shifted mode TXVALID for USB_GUSBCFG */ +#define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /* Shifted mode TERMSEL for USB_GUSBCFG */ +#define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /* Tx End Delay (device only) */ +#define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /* Shift value for USB_TXENDDELAY */ +#define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /* Bit mask for USB_TXENDDELAY */ +#define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /* Force Host Mode (host and device) */ +#define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /* Shift value for USB_FORCEHSTMODE */ +#define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /* Bit mask for USB_FORCEHSTMODE */ +#define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /* Force Device Mode (host and device) */ +#define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /* Shift value for USB_FORCEDEVMODE */ +#define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /* Bit mask for USB_FORCEDEVMODE */ +#define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /* Shifted mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /* Corrupt Tx packet (host and device) */ +#define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /* Shift value for USB_CORRUPTTXPKT */ +#define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /* Bit mask for USB_CORRUPTTXPKT */ +#define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GUSBCFG */ +#define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /* Shifted mode DEFAULT for USB_GUSBCFG */ + +/* Bit fields for USB GRSTCTL */ + +#define _USB_GRSTCTL_RESETVALUE 0x80000000UL /* Default value for USB_GRSTCTL */ +#define _USB_GRSTCTL_MASK 0xC00007F5UL /* Mask for USB_GRSTCTL */ + +#define USB_GRSTCTL_CSFTRST (0x1UL << 0) /* Core Soft Reset (host and device) */ +#define _USB_GRSTCTL_CSFTRST_SHIFT 0 /* Shift value for USB_CSFTRST */ +#define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /* Bit mask for USB_CSFTRST */ +#define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /* Host Frame Counter Reset (host only) */ +#define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /* Shift value for USB_FRMCNTRRST */ +#define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /* Bit mask for USB_FRMCNTRRST */ +#define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /* RxFIFO Flush (host and device) */ +#define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /* Shift value for USB_RXFFLSH */ +#define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /* Bit mask for USB_RXFFLSH */ +#define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /* TxFIFO Flush (host and device) */ +#define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /* Shift value for USB_TXFFLSH */ +#define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /* Bit mask for USB_TXFFLSH */ +#define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_SHIFT 6 /* Shift value for USB_TXFNUM */ +#define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /* Bit mask for USB_TXFNUM */ +#define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /* Mode F0 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /* Mode F1 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /* Mode F2 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /* Mode F3 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /* Mode F4 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /* Mode F5 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /* Mode F6 for USB_GRSTCTL */ +#define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /* Mode FALL for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /* Shifted mode F0 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /* Shifted mode F1 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /* Shifted mode F2 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /* Shifted mode F3 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /* Shifted mode F4 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /* Shifted mode F5 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /* Shifted mode F6 for USB_GRSTCTL */ +#define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /* Shifted mode FALL for USB_GRSTCTL */ +#define USB_GRSTCTL_DMAREQ (0x1UL << 30) /* DMA Request Signal (host and device) */ +#define _USB_GRSTCTL_DMAREQ_SHIFT 30 /* Shift value for USB_DMAREQ */ +#define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /* Bit mask for USB_DMAREQ */ +#define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /* Shifted mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /* AHB Master Idle (host and device) */ +#define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /* Shift value for USB_AHBIDLE */ +#define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /* Bit mask for USB_AHBIDLE */ +#define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_GRSTCTL */ +#define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /* Shifted mode DEFAULT for USB_GRSTCTL */ + +/* Bit fields for USB GINTSTS */ + +#define _USB_GINTSTS_RESETVALUE 0x14000020UL /* Default value for USB_GINTSTS */ +#define _USB_GINTSTS_MASK 0xF7FC7CFFUL /* Mask for USB_GINTSTS */ + +#define USB_GINTSTS_CURMOD (0x1UL << 0) /* Current Mode of Operation (host and device) */ +#define _USB_GINTSTS_CURMOD_SHIFT 0 /* Shift value for USB_CURMOD */ +#define _USB_GINTSTS_CURMOD_MASK 0x1UL /* Bit mask for USB_CURMOD */ +#define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /* Mode DEVICE for USB_GINTSTS */ +#define _USB_GINTSTS_CURMOD_HOST 0x00000001UL /* Mode HOST for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /* Shifted mode DEVICE for USB_GINTSTS */ +#define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /* Shifted mode HOST for USB_GINTSTS */ +#define USB_GINTSTS_MODEMIS (0x1UL << 1) /* Mode Mismatch Interrupt (host and device) */ +#define _USB_GINTSTS_MODEMIS_SHIFT 1 /* Shift value for USB_MODEMIS */ +#define _USB_GINTSTS_MODEMIS_MASK 0x2UL /* Bit mask for USB_MODEMIS */ +#define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OTGINT (0x1UL << 2) /* OTG Interrupt (host and device) */ +#define _USB_GINTSTS_OTGINT_SHIFT 2 /* Shift value for USB_OTGINT */ +#define _USB_GINTSTS_OTGINT_MASK 0x4UL /* Bit mask for USB_OTGINT */ +#define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SOF (0x1UL << 3) /* Start of Frame (host and device) */ +#define _USB_GINTSTS_SOF_SHIFT 3 /* Shift value for USB_SOF */ +#define _USB_GINTSTS_SOF_MASK 0x8UL /* Bit mask for USB_SOF */ +#define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RXFLVL (0x1UL << 4) /* RxFIFO Non-Empty (host and device) */ +#define _USB_GINTSTS_RXFLVL_SHIFT 4 /* Shift value for USB_RXFLVL */ +#define _USB_GINTSTS_RXFLVL_MASK 0x10UL /* Bit mask for USB_RXFLVL */ +#define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /* Non-Periodic TxFIFO Empty (host only) */ +#define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /* Shift value for USB_NPTXFEMP */ +#define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /* Bit mask for USB_NPTXFEMP */ +#define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /* Global IN Non-periodic NAK Effective (device only) */ +#define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /* Shift value for USB_GINNAKEFF */ +#define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /* Bit mask for USB_GINNAKEFF */ +#define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /* Global OUT NAK Effective (device only) */ +#define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /* Shift value for USB_GOUTNAKEFF */ +#define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /* Bit mask for USB_GOUTNAKEFF */ +#define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /* Early Suspend (device only) */ +#define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /* Shift value for USB_ERLYSUSP */ +#define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /* Bit mask for USB_ERLYSUSP */ +#define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBSUSP (0x1UL << 11) /* USB Suspend (device only) */ +#define _USB_GINTSTS_USBSUSP_SHIFT 11 /* Shift value for USB_USBSUSP */ +#define _USB_GINTSTS_USBSUSP_MASK 0x800UL /* Bit mask for USB_USBSUSP */ +#define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBRST (0x1UL << 12) /* USB Reset (device only) */ +#define _USB_GINTSTS_USBRST_SHIFT 12 /* Shift value for USB_USBRST */ +#define _USB_GINTSTS_USBRST_MASK 0x1000UL /* Bit mask for USB_USBRST */ +#define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ENUMDONE (0x1UL << 13) /* Enumeration Done (device only) */ +#define _USB_GINTSTS_ENUMDONE_SHIFT 13 /* Shift value for USB_ENUMDONE */ +#define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /* Bit mask for USB_ENUMDONE */ +#define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /* Isochronous OUT Packet Dropped Interrupt (device only) */ +#define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /* Shift value for USB_ISOOUTDROP */ +#define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /* Bit mask for USB_ISOOUTDROP */ +#define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_IEPINT (0x1UL << 18) /* IN Endpoints Interrupt (device only) */ +#define _USB_GINTSTS_IEPINT_SHIFT 18 /* Shift value for USB_IEPINT */ +#define _USB_GINTSTS_IEPINT_MASK 0x40000UL /* Bit mask for USB_IEPINT */ +#define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OEPINT (0x1UL << 19) /* OUT Endpoints Interrupt (device only) */ +#define _USB_GINTSTS_OEPINT_SHIFT 19 /* Shift value for USB_OEPINT */ +#define _USB_GINTSTS_OEPINT_MASK 0x80000UL /* Bit mask for USB_OEPINT */ +#define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /* Incomplete Isochronous IN Transfer (device only) */ +#define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /* Shift value for USB_INCOMPISOIN */ +#define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /* Bit mask for USB_INCOMPISOIN */ +#define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPLP (0x1UL << 21) /* Incomplete Periodic Transfer (device only) */ +#define _USB_GINTSTS_INCOMPLP_SHIFT 21 /* Shift value for USB_INCOMPLP */ +#define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /* Bit mask for USB_INCOMPLP */ +#define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_FETSUSP (0x1UL << 22) /* Data Fetch Suspended (device only) */ +#define _USB_GINTSTS_FETSUSP_SHIFT 22 /* Shift value for USB_FETSUSP */ +#define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /* Bit mask for USB_FETSUSP */ +#define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RESETDET (0x1UL << 23) /* Reset detected Interrupt (device only) */ +#define _USB_GINTSTS_RESETDET_SHIFT 23 /* Shift value for USB_RESETDET */ +#define _USB_GINTSTS_RESETDET_MASK 0x800000UL /* Bit mask for USB_RESETDET */ +#define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PRTINT (0x1UL << 24) /* Host Port Interrupt (host only) */ +#define _USB_GINTSTS_PRTINT_SHIFT 24 /* Shift value for USB_PRTINT */ +#define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /* Bit mask for USB_PRTINT */ +#define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_HCHINT (0x1UL << 25) /* Host Channels Interrupt (host only) */ +#define _USB_GINTSTS_HCHINT_SHIFT 25 /* Shift value for USB_HCHINT */ +#define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /* Bit mask for USB_HCHINT */ +#define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PTXFEMP (0x1UL << 26) /* Periodic TxFIFO Empty (host only) */ +#define _USB_GINTSTS_PTXFEMP_SHIFT 26 /* Shift value for USB_PTXFEMP */ +#define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /* Bit mask for USB_PTXFEMP */ +#define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /* Connector ID Status Change (host and device) */ +#define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /* Shift value for USB_CONIDSTSCHNG */ +#define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /* Bit mask for USB_CONIDSTSCHNG */ +#define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_DISCONNINT (0x1UL << 29) /* Disconnect Detected Interrupt (host only) */ +#define _USB_GINTSTS_DISCONNINT_SHIFT 29 /* Shift value for USB_DISCONNINT */ +#define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /* Bit mask for USB_DISCONNINT */ +#define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SESSREQINT (0x1UL << 30) /* Session Request/New Session Detected Interrupt (host and device) */ +#define _USB_GINTSTS_SESSREQINT_SHIFT 30 /* Shift value for USB_SESSREQINT */ +#define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /* Bit mask for USB_SESSREQINT */ +#define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /* Shifted mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_WKUPINT (0x1UL << 31) /* Resume/Remote Wakeup Detected Interrupt (host and device) */ +#define _USB_GINTSTS_WKUPINT_SHIFT 31 /* Shift value for USB_WKUPINT */ +#define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /* Bit mask for USB_WKUPINT */ +#define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTSTS */ +#define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /* Shifted mode DEFAULT for USB_GINTSTS */ + +/* Bit fields for USB GINTMSK */ + +#define _USB_GINTMSK_RESETVALUE 0x00000000UL /* Default value for USB_GINTMSK */ +#define _USB_GINTMSK_MASK 0xF7FC7CFEUL /* Mask for USB_GINTMSK */ + +#define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /* Mode Mismatch Interrupt Mask (host and device) */ +#define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /* Shift value for USB_MODEMISMSK */ +#define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /* Bit mask for USB_MODEMISMSK */ +#define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /* OTG Interrupt Mask (host and device) */ +#define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /* Shift value for USB_OTGINTMSK */ +#define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /* Bit mask for USB_OTGINTMSK */ +#define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SOFMSK (0x1UL << 3) /* Start of Frame Mask (host and device) */ +#define _USB_GINTMSK_SOFMSK_SHIFT 3 /* Shift value for USB_SOFMSK */ +#define _USB_GINTMSK_SOFMSK_MASK 0x8UL /* Bit mask for USB_SOFMSK */ +#define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /* Receive FIFO Non-Empty Mask (host and device) */ +#define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /* Shift value for USB_RXFLVLMSK */ +#define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /* Bit mask for USB_RXFLVLMSK */ +#define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /* Non-Periodic TxFIFO Empty Mask (host only) */ +#define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /* Shift value for USB_NPTXFEMPMSK */ +#define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /* Bit mask for USB_NPTXFEMPMSK */ +#define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /* Global Non-periodic IN NAK Effective Mask (device only) */ +#define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /* Shift value for USB_GINNAKEFFMSK */ +#define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /* Bit mask for USB_GINNAKEFFMSK */ +#define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /* Global OUT NAK Effective Mask (device only) */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /* Shift value for USB_GOUTNAKEFFMSK */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /* Bit mask for USB_GOUTNAKEFFMSK */ +#define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /* Early Suspend Mask (device only) */ +#define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /* Shift value for USB_ERLYSUSPMSK */ +#define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /* Bit mask for USB_ERLYSUSPMSK */ +#define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /* USB Suspend Mask (device only) */ +#define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /* Shift value for USB_USBSUSPMSK */ +#define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /* Bit mask for USB_USBSUSPMSK */ +#define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /* USB Reset Mask (device only) */ +#define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /* Shift value for USB_USBRSTMSK */ +#define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /* Bit mask for USB_USBRSTMSK */ +#define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /* Enumeration Done Mask (device only) */ +#define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /* Shift value for USB_ENUMDONEMSK */ +#define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /* Bit mask for USB_ENUMDONEMSK */ +#define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /* Isochronous OUT Packet Dropped Interrupt Mask (device only) */ +#define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /* Shift value for USB_ISOOUTDROPMSK */ +#define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /* Bit mask for USB_ISOOUTDROPMSK */ +#define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /* IN Endpoints Interrupt Mask (device only) */ +#define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /* Shift value for USB_IEPINTMSK */ +#define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /* Bit mask for USB_IEPINTMSK */ +#define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /* OUT Endpoints Interrupt Mask (device only) */ +#define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /* Shift value for USB_OEPINTMSK */ +#define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /* Bit mask for USB_OEPINTMSK */ +#define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /* Incomplete Isochronous IN Transfer Mask (device only) */ +#define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /* Shift value for USB_INCOMPISOINMSK */ +#define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /* Bit mask for USB_INCOMPISOINMSK */ +#define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /* Incomplete Periodic Transfer Mask (host only) */ +#define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /* Shift value for USB_INCOMPLPMSK */ +#define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /* Bit mask for USB_INCOMPLPMSK */ +#define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /* Data Fetch Suspended Mask (device only) */ +#define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /* Shift value for USB_FETSUSPMSK */ +#define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /* Bit mask for USB_FETSUSPMSK */ +#define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /* Reset detected Interrupt Mask (device only) */ +#define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /* Shift value for USB_RESETDETMSK */ +#define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /* Bit mask for USB_RESETDETMSK */ +#define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /* Host Port Interrupt Mask (host only) */ +#define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /* Shift value for USB_PRTINTMSK */ +#define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /* Bit mask for USB_PRTINTMSK */ +#define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /* Host Channels Interrupt Mask (host only) */ +#define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /* Shift value for USB_HCHINTMSK */ +#define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /* Bit mask for USB_HCHINTMSK */ +#define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /* Periodic TxFIFO Empty Mask (host only) */ +#define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /* Shift value for USB_PTXFEMPMSK */ +#define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /* Bit mask for USB_PTXFEMPMSK */ +#define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /* Connector ID Status Change Mask (host and device) */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /* Shift value for USB_CONIDSTSCHNGMSK */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /* Bit mask for USB_CONIDSTSCHNGMSK */ +#define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /* Disconnect Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /* Shift value for USB_DISCONNINTMSK */ +#define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /* Bit mask for USB_DISCONNINTMSK */ +#define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /* Session Request/New Session Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /* Shift value for USB_SESSREQINTMSK */ +#define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /* Bit mask for USB_SESSREQINTMSK */ +#define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /* Shifted mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /* Resume/Remote Wakeup Detected Interrupt Mask (host and device) */ +#define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /* Shift value for USB_WKUPINTMSK */ +#define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /* Bit mask for USB_WKUPINTMSK */ +#define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GINTMSK */ +#define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /* Shifted mode DEFAULT for USB_GINTMSK */ + +/* Bit fields for USB GRXSTSR */ + +#define _USB_GRXSTSR_RESETVALUE 0x00000000UL /* Default value for USB_GRXSTSR */ +#define _USB_GRXSTSR_MASK 0x0F1FFFFFUL /* Mask for USB_GRXSTSR */ + +#define _USB_GRXSTSR_CHEPNUM_SHIFT 0 /* Shift value for USB_CHEPNUM */ +#define _USB_GRXSTSR_CHEPNUM_MASK 0xFUL /* Bit mask for USB_CHEPNUM */ +#define _USB_GRXSTSR_CHEPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_CHEPNUM_DEFAULT (_USB_GRXSTSR_CHEPNUM_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_BCNT_SHIFT 4 /* Shift value for USB_BCNT */ +#define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /* Bit mask for USB_BCNT */ +#define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_SHIFT 15 /* Shift value for USB_DPID */ +#define _USB_GRXSTSR_DPID_MASK 0x18000UL /* Bit mask for USB_DPID */ +#define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /* Mode DATA0 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /* Mode DATA1 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /* Mode DATA2 for USB_GRXSTSR */ +#define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /* Mode MDATA for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /* Shifted mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /* Shifted mode DATA0 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /* Shifted mode DATA1 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /* Shifted mode DATA2 for USB_GRXSTSR */ +#define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /* Shifted mode MDATA for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SHIFT 17 /* Shift value for USB_PKTSTS */ +#define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /* Bit mask for USB_PKTSTS */ +#define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /* Mode GOUTNAK for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /* Mode PKTRCV for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /* Mode XFERCOMPL for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /* Mode SETUPCOMPL for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /* Mode TGLERR for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /* Mode SETUPRCV for USB_GRXSTSR */ +#define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /* Mode CHLT for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /* Shifted mode GOUTNAK for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /* Shifted mode PKTRCV for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /* Shifted mode XFERCOMPL for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /* Shifted mode SETUPCOMPL for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /* Shifted mode TGLERR for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /* Shifted mode SETUPRCV for USB_GRXSTSR */ +#define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /* Shifted mode CHLT for USB_GRXSTSR */ +#define _USB_GRXSTSR_FN_SHIFT 24 /* Shift value for USB_FN */ +#define _USB_GRXSTSR_FN_MASK 0xF000000UL /* Bit mask for USB_FN */ +#define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSR */ +#define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 24) /* Shifted mode DEFAULT for USB_GRXSTSR */ + +/* Bit fields for USB GRXSTSP */ + +#define _USB_GRXSTSP_RESETVALUE 0x00000000UL /* Default value for USB_GRXSTSP */ +#define _USB_GRXSTSP_MASK 0x01FFFFFFUL /* Mask for USB_GRXSTSP */ + +#define _USB_GRXSTSP_CHEPNUM_SHIFT 0 /* Shift value for USB_CHEPNUM */ +#define _USB_GRXSTSP_CHEPNUM_MASK 0xFUL /* Bit mask for USB_CHEPNUM */ +#define _USB_GRXSTSP_CHEPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_CHEPNUM_DEFAULT (_USB_GRXSTSP_CHEPNUM_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_BCNT_SHIFT 4 /* Shift value for USB_BCNT */ +#define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /* Bit mask for USB_BCNT */ +#define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /* Shifted mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_SHIFT 15 /* Shift value for USB_DPID */ +#define _USB_GRXSTSP_DPID_MASK 0x18000UL /* Bit mask for USB_DPID */ +#define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /* Mode DATA0 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /* Mode DATA1 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /* Mode DATA2 for USB_GRXSTSP */ +#define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /* Mode MDATA for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /* Shifted mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /* Shifted mode DATA0 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /* Shifted mode DATA1 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /* Shifted mode DATA2 for USB_GRXSTSP */ +#define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /* Shifted mode MDATA for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SHIFT 17 /* Shift value for USB_PKTSTS */ +#define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /* Bit mask for USB_PKTSTS */ +#define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /* Mode GOUTNAK for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /* Mode PKTRCV for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /* Mode XFERCOMPL for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /* Mode SETUPCOMPL for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /* Mode TGLERR for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /* Mode SETUPRCV for USB_GRXSTSP */ +#define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /* Mode CHLT for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /* Shifted mode GOUTNAK for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /* Shifted mode PKTRCV for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /* Shifted mode XFERCOMPL for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /* Shifted mode SETUPCOMPL for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /* Shifted mode TGLERR for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /* Shifted mode SETUPRCV for USB_GRXSTSP */ +#define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /* Shifted mode CHLT for USB_GRXSTSP */ +#define _USB_GRXSTSP_FN_SHIFT 21 /* Shift value for USB_FN */ +#define _USB_GRXSTSP_FN_MASK 0x1E00000UL /* Bit mask for USB_FN */ +#define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GRXSTSP */ +#define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /* Shifted mode DEFAULT for USB_GRXSTSP */ + +/* Bit fields for USB GRXFSIZ */ + +#define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /* Default value for USB_GRXFSIZ */ +#define _USB_GRXFSIZ_MASK 0x000003FFUL /* Mask for USB_GRXFSIZ */ + +#define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /* Shift value for USB_RXFDEP */ +#define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /* Bit mask for USB_RXFDEP */ +#define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GRXFSIZ */ +#define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GRXFSIZ */ + +/* Bit fields for USB GNPTXFSIZ */ + +#define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /* Default value for USB_GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_MASK 0xFFFF03FFUL /* Mask for USB_GNPTXFSIZ */ + +#define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /* Shift value for USB_NPTXFSTADDR */ +#define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0x3FFUL /* Bit mask for USB_NPTXFSTADDR */ +#define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXFSIZ */ +#define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GNPTXFSIZ */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /* Shift value for USB_NPTXFINEPTXF0DEP */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /* Bit mask for USB_NPTXFINEPTXF0DEP */ +#define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXFSIZ */ +#define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GNPTXFSIZ */ + +/* Bit fields for USB GNPTXSTS */ + +#define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /* Default value for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_MASK 0x7FFFFFFFUL /* Mask for USB_GNPTXSTS */ + +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 /* Shift value for USB_NPTXFSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_MASK 0xFFFFUL /* Bit mask for USB_NPTXFSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 /* Shift value for USB_NPTXQSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_MASK 0xFF0000UL /* Bit mask for USB_NPTXQSPCAVAIL */ +#define _USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT 0x00000008UL /* Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GNPTXSTS */ +#define _USB_GNPTXSTS_NPTXQTOP_SHIFT 24 /* Shift value for USB_NPTXQTOP */ +#define _USB_GNPTXSTS_NPTXQTOP_MASK 0x7F000000UL /* Bit mask for USB_NPTXQTOP */ +#define _USB_GNPTXSTS_NPTXQTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_GNPTXSTS */ +#define USB_GNPTXSTS_NPTXQTOP_DEFAULT (_USB_GNPTXSTS_NPTXQTOP_DEFAULT << 24) /* Shifted mode DEFAULT for USB_GNPTXSTS */ + +/* Bit fields for USB GDFIFOCFG */ + +#define _USB_GDFIFOCFG_RESETVALUE 0x01F20200UL /* Default value for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /* Mask for USB_GDFIFOCFG */ + +#define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /* Shift value for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /* Bit mask for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_GDFIFOCFG */ +#define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /* Shifted mode DEFAULT for USB_GDFIFOCFG */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /* Shift value for USB_EPINFOBASEADDR */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /* Bit mask for USB_EPINFOBASEADDR */ +#define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000001F2UL /* Mode DEFAULT for USB_GDFIFOCFG */ +#define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /* Shifted mode DEFAULT for USB_GDFIFOCFG */ + +/* Bit fields for USB HPTXFSIZ */ + +#define _USB_HPTXFSIZ_RESETVALUE 0x02000400UL /* Default value for USB_HPTXFSIZ */ +#define _USB_HPTXFSIZ_MASK 0x03FF07FFUL /* Mask for USB_HPTXFSIZ */ + +#define _USB_HPTXFSIZ_PTXFSTADDR_SHIFT 0 /* Shift value for USB_PTXFSTADDR */ +#define _USB_HPTXFSIZ_PTXFSTADDR_MASK 0x7FFUL /* Bit mask for USB_PTXFSTADDR */ +#define _USB_HPTXFSIZ_PTXFSTADDR_DEFAULT 0x00000400UL /* Mode DEFAULT for USB_HPTXFSIZ */ +#define USB_HPTXFSIZ_PTXFSTADDR_DEFAULT (_USB_HPTXFSIZ_PTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HPTXFSIZ */ +#define _USB_HPTXFSIZ_PTXFSIZE_SHIFT 16 /* Shift value for USB_PTXFSIZE */ +#define _USB_HPTXFSIZ_PTXFSIZE_MASK 0x3FF0000UL /* Bit mask for USB_PTXFSIZE */ +#define _USB_HPTXFSIZ_PTXFSIZE_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_HPTXFSIZ */ +#define USB_HPTXFSIZ_PTXFSIZE_DEFAULT (_USB_HPTXFSIZ_PTXFSIZE_DEFAULT << 16) /* Shifted mode DEFAULT for USB_HPTXFSIZ */ + +/* Bit fields for USB DIEPTXF1 */ + +#define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /* Default value for USB_DIEPTXF1 */ +#define _USB_DIEPTXF1_MASK 0x03FF07FFUL /* Mask for USB_DIEPTXF1 */ + +#define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /* Mode DEFAULT for USB_DIEPTXF1 */ +#define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF1 */ +#define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF1 */ +#define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF1 */ + +/* Bit fields for USB DIEPTXF2 */ + +#define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /* Default value for USB_DIEPTXF2 */ +#define _USB_DIEPTXF2_MASK 0x03FF07FFUL /* Mask for USB_DIEPTXF2 */ + +#define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /* Mode DEFAULT for USB_DIEPTXF2 */ +#define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF2 */ +#define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF2 */ +#define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF2 */ + +/* Bit fields for USB DIEPTXF3 */ + +#define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /* Default value for USB_DIEPTXF3 */ +#define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /* Mask for USB_DIEPTXF3 */ + +#define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /* Mode DEFAULT for USB_DIEPTXF3 */ +#define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF3 */ +#define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF3 */ +#define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF3 */ + +/* Bit fields for USB DIEPTXF4 */ + +#define _USB_DIEPTXF4_RESETVALUE 0x02000A00UL /* Default value for USB_DIEPTXF4 */ +#define _USB_DIEPTXF4_MASK 0x03FF0FFFUL /* Mask for USB_DIEPTXF4 */ + +#define _USB_DIEPTXF4_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0xFFFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x00000A00UL /* Mode DEFAULT for USB_DIEPTXF4 */ +#define USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF4 */ +#define _USB_DIEPTXF4_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF4 */ +#define USB_DIEPTXF4_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF4 */ + +/* Bit fields for USB DIEPTXF5 */ + +#define _USB_DIEPTXF5_RESETVALUE 0x02000C00UL /* Default value for USB_DIEPTXF5 */ +#define _USB_DIEPTXF5_MASK 0x03FF0FFFUL /* Mask for USB_DIEPTXF5 */ + +#define _USB_DIEPTXF5_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0xFFFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x00000C00UL /* Mode DEFAULT for USB_DIEPTXF5 */ +#define USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF5 */ +#define _USB_DIEPTXF5_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF5 */ +#define USB_DIEPTXF5_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF5 */ + +/* Bit fields for USB DIEPTXF6 */ + +#define _USB_DIEPTXF6_RESETVALUE 0x02000E00UL /* Default value for USB_DIEPTXF6 */ +#define _USB_DIEPTXF6_MASK 0x03FF0FFFUL /* Mask for USB_DIEPTXF6 */ + +#define _USB_DIEPTXF6_INEPNTXFSTADDR_SHIFT 0 /* Shift value for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0xFFFUL /* Bit mask for USB_INEPNTXFSTADDR */ +#define _USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x00000E00UL /* Mode DEFAULT for USB_DIEPTXF6 */ +#define USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPTXF6 */ +#define _USB_DIEPTXF6_INEPNTXFDEP_SHIFT 16 /* Shift value for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3FF0000UL /* Bit mask for USB_INEPNTXFDEP */ +#define _USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEPTXF6 */ +#define USB_DIEPTXF6_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEPTXF6 */ + +/* Bit fields for USB HCFG */ + +#define _USB_HCFG_RESETVALUE 0x00200000UL /* Default value for USB_HCFG */ +#define _USB_HCFG_MASK 0x8000FF87UL /* Mask for USB_HCFG */ + +#define _USB_HCFG_FSLSPCLKSEL_SHIFT 0 /* Shift value for USB_FSLSPCLKSEL */ +#define _USB_HCFG_FSLSPCLKSEL_MASK 0x3UL /* Bit mask for USB_FSLSPCLKSEL */ +#define _USB_HCFG_FSLSPCLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_FSLSPCLKSEL_DIV1 0x00000001UL /* Mode DIV1 for USB_HCFG */ +#define _USB_HCFG_FSLSPCLKSEL_DIV8 0x00000002UL /* Mode DIV8 for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DEFAULT (_USB_HCFG_FSLSPCLKSEL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DIV1 (_USB_HCFG_FSLSPCLKSEL_DIV1 << 0) /* Shifted mode DIV1 for USB_HCFG */ +#define USB_HCFG_FSLSPCLKSEL_DIV8 (_USB_HCFG_FSLSPCLKSEL_DIV8 << 0) /* Shifted mode DIV8 for USB_HCFG */ +#define USB_HCFG_FSLSSUPP (0x1UL << 2) /* FS- and LS-Only Support */ +#define _USB_HCFG_FSLSSUPP_SHIFT 2 /* Shift value for USB_FSLSSUPP */ +#define _USB_HCFG_FSLSSUPP_MASK 0x4UL /* Bit mask for USB_FSLSSUPP */ +#define _USB_HCFG_FSLSSUPP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_FSLSSUPP_HSFSLS 0x00000000UL /* Mode HSFSLS for USB_HCFG */ +#define _USB_HCFG_FSLSSUPP_FSLS 0x00000001UL /* Mode FSLS for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_DEFAULT (_USB_HCFG_FSLSSUPP_DEFAULT << 2) /* Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_HSFSLS (_USB_HCFG_FSLSSUPP_HSFSLS << 2) /* Shifted mode HSFSLS for USB_HCFG */ +#define USB_HCFG_FSLSSUPP_FSLS (_USB_HCFG_FSLSSUPP_FSLS << 2) /* Shifted mode FSLS for USB_HCFG */ +#define USB_HCFG_ENA32KHZS (0x1UL << 7) /* Enable 32 KHz Suspend mode */ +#define _USB_HCFG_ENA32KHZS_SHIFT 7 /* Shift value for USB_ENA32KHZS */ +#define _USB_HCFG_ENA32KHZS_MASK 0x80UL /* Bit mask for USB_ENA32KHZS */ +#define _USB_HCFG_ENA32KHZS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_ENA32KHZS_DEFAULT (_USB_HCFG_ENA32KHZS_DEFAULT << 7) /* Shifted mode DEFAULT for USB_HCFG */ +#define _USB_HCFG_RESVALID_SHIFT 8 /* Shift value for USB_RESVALID */ +#define _USB_HCFG_RESVALID_MASK 0xFF00UL /* Bit mask for USB_RESVALID */ +#define _USB_HCFG_RESVALID_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_RESVALID_DEFAULT (_USB_HCFG_RESVALID_DEFAULT << 8) /* Shifted mode DEFAULT for USB_HCFG */ +#define USB_HCFG_MODECHTIMEN (0x1UL << 31) /* Mode Change Time */ +#define _USB_HCFG_MODECHTIMEN_SHIFT 31 /* Shift value for USB_MODECHTIMEN */ +#define _USB_HCFG_MODECHTIMEN_MASK 0x80000000UL /* Bit mask for USB_MODECHTIMEN */ +#define _USB_HCFG_MODECHTIMEN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HCFG */ +#define USB_HCFG_MODECHTIMEN_DEFAULT (_USB_HCFG_MODECHTIMEN_DEFAULT << 31) /* Shifted mode DEFAULT for USB_HCFG */ + +/* Bit fields for USB HFIR */ + +#define _USB_HFIR_RESETVALUE 0x000017D7UL /* Default value for USB_HFIR */ +#define _USB_HFIR_MASK 0x0001FFFFUL /* Mask for USB_HFIR */ + +#define _USB_HFIR_FRINT_SHIFT 0 /* Shift value for USB_FRINT */ +#define _USB_HFIR_FRINT_MASK 0xFFFFUL /* Bit mask for USB_FRINT */ +#define _USB_HFIR_FRINT_DEFAULT 0x000017D7UL /* Mode DEFAULT for USB_HFIR */ +#define USB_HFIR_FRINT_DEFAULT (_USB_HFIR_FRINT_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL (0x1UL << 16) /* Reload Control */ +#define _USB_HFIR_HFIRRLDCTRL_SHIFT 16 /* Shift value for USB_HFIRRLDCTRL */ +#define _USB_HFIR_HFIRRLDCTRL_MASK 0x10000UL /* Bit mask for USB_HFIRRLDCTRL */ +#define _USB_HFIR_HFIRRLDCTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HFIR */ +#define _USB_HFIR_HFIRRLDCTRL_STATIC 0x00000000UL /* Mode STATIC for USB_HFIR */ +#define _USB_HFIR_HFIRRLDCTRL_DYNAMIC 0x00000001UL /* Mode DYNAMIC for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_DEFAULT (_USB_HFIR_HFIRRLDCTRL_DEFAULT << 16) /* Shifted mode DEFAULT for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_STATIC (_USB_HFIR_HFIRRLDCTRL_STATIC << 16) /* Shifted mode STATIC for USB_HFIR */ +#define USB_HFIR_HFIRRLDCTRL_DYNAMIC (_USB_HFIR_HFIRRLDCTRL_DYNAMIC << 16) /* Shifted mode DYNAMIC for USB_HFIR */ + +/* Bit fields for USB HFNUM */ + +#define _USB_HFNUM_RESETVALUE 0x00003FFFUL /* Default value for USB_HFNUM */ +#define _USB_HFNUM_MASK 0xFFFFFFFFUL /* Mask for USB_HFNUM */ + +#define _USB_HFNUM_FRNUM_SHIFT 0 /* Shift value for USB_FRNUM */ +#define _USB_HFNUM_FRNUM_MASK 0xFFFFUL /* Bit mask for USB_FRNUM */ +#define _USB_HFNUM_FRNUM_DEFAULT 0x00003FFFUL /* Mode DEFAULT for USB_HFNUM */ +#define USB_HFNUM_FRNUM_DEFAULT (_USB_HFNUM_FRNUM_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HFNUM */ +#define _USB_HFNUM_FRREM_SHIFT 16 /* Shift value for USB_FRREM */ +#define _USB_HFNUM_FRREM_MASK 0xFFFF0000UL /* Bit mask for USB_FRREM */ +#define _USB_HFNUM_FRREM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HFNUM */ +#define USB_HFNUM_FRREM_DEFAULT (_USB_HFNUM_FRREM_DEFAULT << 16) /* Shifted mode DEFAULT for USB_HFNUM */ + +/* Bit fields for USB HPTXSTS */ + +#define _USB_HPTXSTS_RESETVALUE 0x00080200UL /* Default value for USB_HPTXSTS */ +#define _USB_HPTXSTS_MASK 0xFFFFFFFFUL /* Mask for USB_HPTXSTS */ + +#define _USB_HPTXSTS_PTXFSPCAVAIL_SHIFT 0 /* Shift value for USB_PTXFSPCAVAIL */ +#define _USB_HPTXSTS_PTXFSPCAVAIL_MASK 0xFFFFUL /* Bit mask for USB_PTXFSPCAVAIL */ +#define _USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HPTXSTS */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_SHIFT 16 /* Shift value for USB_PTXQSPCAVAIL */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_MASK 0xFF0000UL /* Bit mask for USB_PTXQSPCAVAIL */ +#define _USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT 0x00000008UL /* Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT << 16) /* Shifted mode DEFAULT for USB_HPTXSTS */ +#define _USB_HPTXSTS_PTXQTOP_SHIFT 24 /* Shift value for USB_PTXQTOP */ +#define _USB_HPTXSTS_PTXQTOP_MASK 0xFF000000UL /* Bit mask for USB_PTXQTOP */ +#define _USB_HPTXSTS_PTXQTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPTXSTS */ +#define USB_HPTXSTS_PTXQTOP_DEFAULT (_USB_HPTXSTS_PTXQTOP_DEFAULT << 24) /* Shifted mode DEFAULT for USB_HPTXSTS */ + +/* Bit fields for USB HAINT */ + +#define _USB_HAINT_RESETVALUE 0x00000000UL /* Default value for USB_HAINT */ +#define _USB_HAINT_MASK 0x00003FFFUL /* Mask for USB_HAINT */ + +#define _USB_HAINT_HAINT_SHIFT 0 /* Shift value for USB_HAINT */ +#define _USB_HAINT_HAINT_MASK 0x3FFFUL /* Bit mask for USB_HAINT */ +#define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HAINT */ +#define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HAINT */ + +/* Bit fields for USB HAINTMSK */ + +#define _USB_HAINTMSK_RESETVALUE 0x00000000UL /* Default value for USB_HAINTMSK */ +#define _USB_HAINTMSK_MASK 0x00003FFFUL /* Mask for USB_HAINTMSK */ + +#define _USB_HAINTMSK_HAINTMSK_SHIFT 0 /* Shift value for USB_HAINTMSK */ +#define _USB_HAINTMSK_HAINTMSK_MASK 0x3FFFUL /* Bit mask for USB_HAINTMSK */ +#define _USB_HAINTMSK_HAINTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HAINTMSK */ +#define USB_HAINTMSK_HAINTMSK_DEFAULT (_USB_HAINTMSK_HAINTMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HAINTMSK */ + +/* Bit fields for USB HPRT */ + +#define _USB_HPRT_RESETVALUE 0x00000000UL /* Default value for USB_HPRT */ +#define _USB_HPRT_MASK 0x0007FDFFUL /* Mask for USB_HPRT */ + +#define USB_HPRT_PRTCONNSTS (0x1UL << 0) /* Port Connect Status */ +#define _USB_HPRT_PRTCONNSTS_SHIFT 0 /* Shift value for USB_PRTCONNSTS */ +#define _USB_HPRT_PRTCONNSTS_MASK 0x1UL /* Bit mask for USB_PRTCONNSTS */ +#define _USB_HPRT_PRTCONNSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNSTS_DEFAULT (_USB_HPRT_PRTCONNSTS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNDET (0x1UL << 1) /* Port Connect Detected */ +#define _USB_HPRT_PRTCONNDET_SHIFT 1 /* Shift value for USB_PRTCONNDET */ +#define _USB_HPRT_PRTCONNDET_MASK 0x2UL /* Bit mask for USB_PRTCONNDET */ +#define _USB_HPRT_PRTCONNDET_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTCONNDET_DEFAULT (_USB_HPRT_PRTCONNDET_DEFAULT << 1) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENA (0x1UL << 2) /* Port Enable */ +#define _USB_HPRT_PRTENA_SHIFT 2 /* Shift value for USB_PRTENA */ +#define _USB_HPRT_PRTENA_MASK 0x4UL /* Bit mask for USB_PRTENA */ +#define _USB_HPRT_PRTENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENA_DEFAULT (_USB_HPRT_PRTENA_DEFAULT << 2) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENCHNG (0x1UL << 3) /* Port Enable/Disable Change */ +#define _USB_HPRT_PRTENCHNG_SHIFT 3 /* Shift value for USB_PRTENCHNG */ +#define _USB_HPRT_PRTENCHNG_MASK 0x8UL /* Bit mask for USB_PRTENCHNG */ +#define _USB_HPRT_PRTENCHNG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTENCHNG_DEFAULT (_USB_HPRT_PRTENCHNG_DEFAULT << 3) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRACT (0x1UL << 4) /* Port Overcurrent Active */ +#define _USB_HPRT_PRTOVRCURRACT_SHIFT 4 /* Shift value for USB_PRTOVRCURRACT */ +#define _USB_HPRT_PRTOVRCURRACT_MASK 0x10UL /* Bit mask for USB_PRTOVRCURRACT */ +#define _USB_HPRT_PRTOVRCURRACT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRACT_DEFAULT (_USB_HPRT_PRTOVRCURRACT_DEFAULT << 4) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRCHNG (0x1UL << 5) /* Port Overcurrent Change */ +#define _USB_HPRT_PRTOVRCURRCHNG_SHIFT 5 /* Shift value for USB_PRTOVRCURRCHNG */ +#define _USB_HPRT_PRTOVRCURRCHNG_MASK 0x20UL /* Bit mask for USB_PRTOVRCURRCHNG */ +#define _USB_HPRT_PRTOVRCURRCHNG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTOVRCURRCHNG_DEFAULT (_USB_HPRT_PRTOVRCURRCHNG_DEFAULT << 5) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRES (0x1UL << 6) /* Port Resume */ +#define _USB_HPRT_PRTRES_SHIFT 6 /* Shift value for USB_PRTRES */ +#define _USB_HPRT_PRTRES_MASK 0x40UL /* Bit mask for USB_PRTRES */ +#define _USB_HPRT_PRTRES_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRES_DEFAULT (_USB_HPRT_PRTRES_DEFAULT << 6) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSUSP (0x1UL << 7) /* Port Suspend */ +#define _USB_HPRT_PRTSUSP_SHIFT 7 /* Shift value for USB_PRTSUSP */ +#define _USB_HPRT_PRTSUSP_MASK 0x80UL /* Bit mask for USB_PRTSUSP */ +#define _USB_HPRT_PRTSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSUSP_DEFAULT (_USB_HPRT_PRTSUSP_DEFAULT << 7) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRST (0x1UL << 8) /* Port Reset */ +#define _USB_HPRT_PRTRST_SHIFT 8 /* Shift value for USB_PRTRST */ +#define _USB_HPRT_PRTRST_MASK 0x100UL /* Bit mask for USB_PRTRST */ +#define _USB_HPRT_PRTRST_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTRST_DEFAULT (_USB_HPRT_PRTRST_DEFAULT << 8) /* Shifted mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTLNSTS_SHIFT 10 /* Shift value for USB_PRTLNSTS */ +#define _USB_HPRT_PRTLNSTS_MASK 0xC00UL /* Bit mask for USB_PRTLNSTS */ +#define _USB_HPRT_PRTLNSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTLNSTS_DEFAULT (_USB_HPRT_PRTLNSTS_DEFAULT << 10) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTPWR (0x1UL << 12) /* Port Power */ +#define _USB_HPRT_PRTPWR_SHIFT 12 /* Shift value for USB_PRTPWR */ +#define _USB_HPRT_PRTPWR_MASK 0x1000UL /* Bit mask for USB_PRTPWR */ +#define _USB_HPRT_PRTPWR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTPWR_OFF 0x00000000UL /* Mode OFF for USB_HPRT */ +#define _USB_HPRT_PRTPWR_ON 0x00000001UL /* Mode ON for USB_HPRT */ +#define USB_HPRT_PRTPWR_DEFAULT (_USB_HPRT_PRTPWR_DEFAULT << 12) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTPWR_OFF (_USB_HPRT_PRTPWR_OFF << 12) /* Shifted mode OFF for USB_HPRT */ +#define USB_HPRT_PRTPWR_ON (_USB_HPRT_PRTPWR_ON << 12) /* Shifted mode ON for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_SHIFT 13 /* Shift value for USB_PRTTSTCTL */ +#define _USB_HPRT_PRTTSTCTL_MASK 0x1E000UL /* Bit mask for USB_PRTTSTCTL */ +#define _USB_HPRT_PRTTSTCTL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_DISABLE 0x00000000UL /* Mode DISABLE for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_J 0x00000001UL /* Mode J for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_K 0x00000002UL /* Mode K for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_SE0NAK 0x00000003UL /* Mode SE0NAK for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_PACKET 0x00000004UL /* Mode PACKET for USB_HPRT */ +#define _USB_HPRT_PRTTSTCTL_FORCE 0x00000005UL /* Mode FORCE for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_DEFAULT (_USB_HPRT_PRTTSTCTL_DEFAULT << 13) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_DISABLE (_USB_HPRT_PRTTSTCTL_DISABLE << 13) /* Shifted mode DISABLE for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_J (_USB_HPRT_PRTTSTCTL_J << 13) /* Shifted mode J for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_K (_USB_HPRT_PRTTSTCTL_K << 13) /* Shifted mode K for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_SE0NAK (_USB_HPRT_PRTTSTCTL_SE0NAK << 13) /* Shifted mode SE0NAK for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_PACKET (_USB_HPRT_PRTTSTCTL_PACKET << 13) /* Shifted mode PACKET for USB_HPRT */ +#define USB_HPRT_PRTTSTCTL_FORCE (_USB_HPRT_PRTTSTCTL_FORCE << 13) /* Shifted mode FORCE for USB_HPRT */ +#define _USB_HPRT_PRTSPD_SHIFT 17 /* Shift value for USB_PRTSPD */ +#define _USB_HPRT_PRTSPD_MASK 0x60000UL /* Bit mask for USB_PRTSPD */ +#define _USB_HPRT_PRTSPD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HPRT */ +#define _USB_HPRT_PRTSPD_HS 0x00000000UL /* Mode HS for USB_HPRT */ +#define _USB_HPRT_PRTSPD_FS 0x00000001UL /* Mode FS for USB_HPRT */ +#define _USB_HPRT_PRTSPD_LS 0x00000002UL /* Mode LS for USB_HPRT */ +#define USB_HPRT_PRTSPD_DEFAULT (_USB_HPRT_PRTSPD_DEFAULT << 17) /* Shifted mode DEFAULT for USB_HPRT */ +#define USB_HPRT_PRTSPD_HS (_USB_HPRT_PRTSPD_HS << 17) /* Shifted mode HS for USB_HPRT */ +#define USB_HPRT_PRTSPD_FS (_USB_HPRT_PRTSPD_FS << 17) /* Shifted mode FS for USB_HPRT */ +#define USB_HPRT_PRTSPD_LS (_USB_HPRT_PRTSPD_LS << 17) /* Shifted mode LS for USB_HPRT */ + +/* Bit fields for USB HC_CHAR */ + +#define _USB_HC_CHAR_RESETVALUE 0x00000000UL /* Default value for USB_HC_CHAR */ +#define _USB_HC_CHAR_MASK 0xFFFEFFFFUL /* Mask for USB_HC_CHAR */ + +#define _USB_HC_CHAR_MPS_SHIFT 0 /* Shift value for USB_MPS */ +#define _USB_HC_CHAR_MPS_MASK 0x7FFUL /* Bit mask for USB_MPS */ +#define _USB_HC_CHAR_MPS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_MPS_DEFAULT (_USB_HC_CHAR_MPS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPNUM_SHIFT 11 /* Shift value for USB_EPNUM */ +#define _USB_HC_CHAR_EPNUM_MASK 0x7800UL /* Bit mask for USB_EPNUM */ +#define _USB_HC_CHAR_EPNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPNUM_DEFAULT (_USB_HC_CHAR_EPNUM_DEFAULT << 11) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR (0x1UL << 15) /* Endpoint Direction */ +#define _USB_HC_CHAR_EPDIR_SHIFT 15 /* Shift value for USB_EPDIR */ +#define _USB_HC_CHAR_EPDIR_MASK 0x8000UL /* Bit mask for USB_EPDIR */ +#define _USB_HC_CHAR_EPDIR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPDIR_OUT 0x00000000UL /* Mode OUT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPDIR_IN 0x00000001UL /* Mode IN for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_DEFAULT (_USB_HC_CHAR_EPDIR_DEFAULT << 15) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_OUT (_USB_HC_CHAR_EPDIR_OUT << 15) /* Shifted mode OUT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPDIR_IN (_USB_HC_CHAR_EPDIR_IN << 15) /* Shifted mode IN for USB_HC_CHAR */ +#define USB_HC_CHAR_LSPDDEV (0x1UL << 17) /* Low-Speed Device */ +#define _USB_HC_CHAR_LSPDDEV_SHIFT 17 /* Shift value for USB_LSPDDEV */ +#define _USB_HC_CHAR_LSPDDEV_MASK 0x20000UL /* Bit mask for USB_LSPDDEV */ +#define _USB_HC_CHAR_LSPDDEV_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_LSPDDEV_DEFAULT (_USB_HC_CHAR_LSPDDEV_DEFAULT << 17) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_SHIFT 18 /* Shift value for USB_EPTYPE */ +#define _USB_HC_CHAR_EPTYPE_MASK 0xC0000UL /* Bit mask for USB_EPTYPE */ +#define _USB_HC_CHAR_EPTYPE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_CONTROL 0x00000000UL /* Mode CONTROL for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_ISO 0x00000001UL /* Mode ISO for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_BULK 0x00000002UL /* Mode BULK for USB_HC_CHAR */ +#define _USB_HC_CHAR_EPTYPE_INT 0x00000003UL /* Mode INT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_DEFAULT (_USB_HC_CHAR_EPTYPE_DEFAULT << 18) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_CONTROL (_USB_HC_CHAR_EPTYPE_CONTROL << 18) /* Shifted mode CONTROL for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_ISO (_USB_HC_CHAR_EPTYPE_ISO << 18) /* Shifted mode ISO for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_BULK (_USB_HC_CHAR_EPTYPE_BULK << 18) /* Shifted mode BULK for USB_HC_CHAR */ +#define USB_HC_CHAR_EPTYPE_INT (_USB_HC_CHAR_EPTYPE_INT << 18) /* Shifted mode INT for USB_HC_CHAR */ +#define _USB_HC_CHAR_MC_SHIFT 20 /* Shift value for USB_MC */ +#define _USB_HC_CHAR_MC_MASK 0x300000UL /* Bit mask for USB_MC */ +#define _USB_HC_CHAR_MC_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_MC_DEFAULT (_USB_HC_CHAR_MC_DEFAULT << 20) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define _USB_HC_CHAR_DEVADDR_SHIFT 22 /* Shift value for USB_DEVADDR */ +#define _USB_HC_CHAR_DEVADDR_MASK 0x1FC00000UL /* Bit mask for USB_DEVADDR */ +#define _USB_HC_CHAR_DEVADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_DEVADDR_DEFAULT (_USB_HC_CHAR_DEVADDR_DEFAULT << 22) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_ODDFRM (0x1UL << 29) /* Odd Frame */ +#define _USB_HC_CHAR_ODDFRM_SHIFT 29 /* Shift value for USB_ODDFRM */ +#define _USB_HC_CHAR_ODDFRM_MASK 0x20000000UL /* Bit mask for USB_ODDFRM */ +#define _USB_HC_CHAR_ODDFRM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_ODDFRM_DEFAULT (_USB_HC_CHAR_ODDFRM_DEFAULT << 29) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHDIS (0x1UL << 30) /* Channel Disable */ +#define _USB_HC_CHAR_CHDIS_SHIFT 30 /* Shift value for USB_CHDIS */ +#define _USB_HC_CHAR_CHDIS_MASK 0x40000000UL /* Bit mask for USB_CHDIS */ +#define _USB_HC_CHAR_CHDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHDIS_DEFAULT (_USB_HC_CHAR_CHDIS_DEFAULT << 30) /* Shifted mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHENA (0x1UL << 31) /* Channel Enable */ +#define _USB_HC_CHAR_CHENA_SHIFT 31 /* Shift value for USB_CHENA */ +#define _USB_HC_CHAR_CHENA_MASK 0x80000000UL /* Bit mask for USB_CHENA */ +#define _USB_HC_CHAR_CHENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_CHAR */ +#define USB_HC_CHAR_CHENA_DEFAULT (_USB_HC_CHAR_CHENA_DEFAULT << 31) /* Shifted mode DEFAULT for USB_HC_CHAR */ + +/* Bit fields for USB HC_INT */ + +#define _USB_HC_INT_RESETVALUE 0x00000000UL /* Default value for USB_HC_INT */ +#define _USB_HC_INT_MASK 0x000007BFUL /* Mask for USB_HC_INT */ + +#define USB_HC_INT_XFERCOMPL (0x1UL << 0) /* Transfer Completed */ +#define _USB_HC_INT_XFERCOMPL_SHIFT 0 /* Shift value for USB_XFERCOMPL */ +#define _USB_HC_INT_XFERCOMPL_MASK 0x1UL /* Bit mask for USB_XFERCOMPL */ +#define _USB_HC_INT_XFERCOMPL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XFERCOMPL_DEFAULT (_USB_HC_INT_XFERCOMPL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_CHHLTD (0x1UL << 1) /* Channel Halted */ +#define _USB_HC_INT_CHHLTD_SHIFT 1 /* Shift value for USB_CHHLTD */ +#define _USB_HC_INT_CHHLTD_MASK 0x2UL /* Bit mask for USB_CHHLTD */ +#define _USB_HC_INT_CHHLTD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_CHHLTD_DEFAULT (_USB_HC_INT_CHHLTD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_AHBERR (0x1UL << 2) /* AHB Error */ +#define _USB_HC_INT_AHBERR_SHIFT 2 /* Shift value for USB_AHBERR */ +#define _USB_HC_INT_AHBERR_MASK 0x4UL /* Bit mask for USB_AHBERR */ +#define _USB_HC_INT_AHBERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_AHBERR_DEFAULT (_USB_HC_INT_AHBERR_DEFAULT << 2) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_STALL (0x1UL << 3) /* STALL Response Received Interrupt */ +#define _USB_HC_INT_STALL_SHIFT 3 /* Shift value for USB_STALL */ +#define _USB_HC_INT_STALL_MASK 0x8UL /* Bit mask for USB_STALL */ +#define _USB_HC_INT_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_STALL_DEFAULT (_USB_HC_INT_STALL_DEFAULT << 3) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_NAK (0x1UL << 4) /* NAK Response Received Interrupt */ +#define _USB_HC_INT_NAK_SHIFT 4 /* Shift value for USB_NAK */ +#define _USB_HC_INT_NAK_MASK 0x10UL /* Bit mask for USB_NAK */ +#define _USB_HC_INT_NAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_NAK_DEFAULT (_USB_HC_INT_NAK_DEFAULT << 4) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_ACK (0x1UL << 5) /* ACK Response Received/Transmitted Interrupt */ +#define _USB_HC_INT_ACK_SHIFT 5 /* Shift value for USB_ACK */ +#define _USB_HC_INT_ACK_MASK 0x20UL /* Bit mask for USB_ACK */ +#define _USB_HC_INT_ACK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_ACK_DEFAULT (_USB_HC_INT_ACK_DEFAULT << 5) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XACTERR (0x1UL << 7) /* Transaction Error */ +#define _USB_HC_INT_XACTERR_SHIFT 7 /* Shift value for USB_XACTERR */ +#define _USB_HC_INT_XACTERR_MASK 0x80UL /* Bit mask for USB_XACTERR */ +#define _USB_HC_INT_XACTERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_XACTERR_DEFAULT (_USB_HC_INT_XACTERR_DEFAULT << 7) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_BBLERR (0x1UL << 8) /* Babble Error */ +#define _USB_HC_INT_BBLERR_SHIFT 8 /* Shift value for USB_BBLERR */ +#define _USB_HC_INT_BBLERR_MASK 0x100UL /* Bit mask for USB_BBLERR */ +#define _USB_HC_INT_BBLERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_BBLERR_DEFAULT (_USB_HC_INT_BBLERR_DEFAULT << 8) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_FRMOVRUN (0x1UL << 9) /* Frame Overrun */ +#define _USB_HC_INT_FRMOVRUN_SHIFT 9 /* Shift value for USB_FRMOVRUN */ +#define _USB_HC_INT_FRMOVRUN_MASK 0x200UL /* Bit mask for USB_FRMOVRUN */ +#define _USB_HC_INT_FRMOVRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_FRMOVRUN_DEFAULT (_USB_HC_INT_FRMOVRUN_DEFAULT << 9) /* Shifted mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_DATATGLERR (0x1UL << 10) /* Data Toggle Error */ +#define _USB_HC_INT_DATATGLERR_SHIFT 10 /* Shift value for USB_DATATGLERR */ +#define _USB_HC_INT_DATATGLERR_MASK 0x400UL /* Bit mask for USB_DATATGLERR */ +#define _USB_HC_INT_DATATGLERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INT */ +#define USB_HC_INT_DATATGLERR_DEFAULT (_USB_HC_INT_DATATGLERR_DEFAULT << 10) /* Shifted mode DEFAULT for USB_HC_INT */ + +/* Bit fields for USB HC_INTMSK */ + +#define _USB_HC_INTMSK_RESETVALUE 0x00000000UL /* Default value for USB_HC_INTMSK */ +#define _USB_HC_INTMSK_MASK 0x000007BFUL /* Mask for USB_HC_INTMSK */ + +#define USB_HC_INTMSK_XFERCOMPLMSK (0x1UL << 0) /* Transfer Completed Mask */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_SHIFT 0 /* Shift value for USB_XFERCOMPLMSK */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_MASK 0x1UL /* Bit mask for USB_XFERCOMPLMSK */ +#define _USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT (_USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_CHHLTDMSK (0x1UL << 1) /* Channel Halted Mask */ +#define _USB_HC_INTMSK_CHHLTDMSK_SHIFT 1 /* Shift value for USB_CHHLTDMSK */ +#define _USB_HC_INTMSK_CHHLTDMSK_MASK 0x2UL /* Bit mask for USB_CHHLTDMSK */ +#define _USB_HC_INTMSK_CHHLTDMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_CHHLTDMSK_DEFAULT (_USB_HC_INTMSK_CHHLTDMSK_DEFAULT << 1) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_AHBERRMSK (0x1UL << 2) /* AHB Error Mask */ +#define _USB_HC_INTMSK_AHBERRMSK_SHIFT 2 /* Shift value for USB_AHBERRMSK */ +#define _USB_HC_INTMSK_AHBERRMSK_MASK 0x4UL /* Bit mask for USB_AHBERRMSK */ +#define _USB_HC_INTMSK_AHBERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_AHBERRMSK_DEFAULT (_USB_HC_INTMSK_AHBERRMSK_DEFAULT << 2) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_STALLMSK (0x1UL << 3) /* STALL Response Received Interrupt Mask */ +#define _USB_HC_INTMSK_STALLMSK_SHIFT 3 /* Shift value for USB_STALLMSK */ +#define _USB_HC_INTMSK_STALLMSK_MASK 0x8UL /* Bit mask for USB_STALLMSK */ +#define _USB_HC_INTMSK_STALLMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_STALLMSK_DEFAULT (_USB_HC_INTMSK_STALLMSK_DEFAULT << 3) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_NAKMSK (0x1UL << 4) /* NAK Response Received Interrupt Mask */ +#define _USB_HC_INTMSK_NAKMSK_SHIFT 4 /* Shift value for USB_NAKMSK */ +#define _USB_HC_INTMSK_NAKMSK_MASK 0x10UL /* Bit mask for USB_NAKMSK */ +#define _USB_HC_INTMSK_NAKMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_NAKMSK_DEFAULT (_USB_HC_INTMSK_NAKMSK_DEFAULT << 4) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_ACKMSK (0x1UL << 5) /* ACK Response Received/Transmitted Interrupt Mask */ +#define _USB_HC_INTMSK_ACKMSK_SHIFT 5 /* Shift value for USB_ACKMSK */ +#define _USB_HC_INTMSK_ACKMSK_MASK 0x20UL /* Bit mask for USB_ACKMSK */ +#define _USB_HC_INTMSK_ACKMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_ACKMSK_DEFAULT (_USB_HC_INTMSK_ACKMSK_DEFAULT << 5) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XACTERRMSK (0x1UL << 7) /* Transaction Error Mask */ +#define _USB_HC_INTMSK_XACTERRMSK_SHIFT 7 /* Shift value for USB_XACTERRMSK */ +#define _USB_HC_INTMSK_XACTERRMSK_MASK 0x80UL /* Bit mask for USB_XACTERRMSK */ +#define _USB_HC_INTMSK_XACTERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_XACTERRMSK_DEFAULT (_USB_HC_INTMSK_XACTERRMSK_DEFAULT << 7) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_BBLERRMSK (0x1UL << 8) /* Babble Error Mask */ +#define _USB_HC_INTMSK_BBLERRMSK_SHIFT 8 /* Shift value for USB_BBLERRMSK */ +#define _USB_HC_INTMSK_BBLERRMSK_MASK 0x100UL /* Bit mask for USB_BBLERRMSK */ +#define _USB_HC_INTMSK_BBLERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_BBLERRMSK_DEFAULT (_USB_HC_INTMSK_BBLERRMSK_DEFAULT << 8) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_FRMOVRUNMSK (0x1UL << 9) /* Frame Overrun Mask */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_SHIFT 9 /* Shift value for USB_FRMOVRUNMSK */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_MASK 0x200UL /* Bit mask for USB_FRMOVRUNMSK */ +#define _USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT (_USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT << 9) /* Shifted mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_DATATGLERRMSK (0x1UL << 10) /* Data Toggle Error Mask */ +#define _USB_HC_INTMSK_DATATGLERRMSK_SHIFT 10 /* Shift value for USB_DATATGLERRMSK */ +#define _USB_HC_INTMSK_DATATGLERRMSK_MASK 0x400UL /* Bit mask for USB_DATATGLERRMSK */ +#define _USB_HC_INTMSK_DATATGLERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_INTMSK */ +#define USB_HC_INTMSK_DATATGLERRMSK_DEFAULT (_USB_HC_INTMSK_DATATGLERRMSK_DEFAULT << 10) /* Shifted mode DEFAULT for USB_HC_INTMSK */ + +/* Bit fields for USB HC_TSIZ */ + +#define _USB_HC_TSIZ_RESETVALUE 0x00000000UL /* Default value for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_MASK 0x7FFFFFFFUL /* Mask for USB_HC_TSIZ */ + +#define _USB_HC_TSIZ_XFERSIZE_SHIFT 0 /* Shift value for USB_XFERSIZE */ +#define _USB_HC_TSIZ_XFERSIZE_MASK 0x7FFFFUL /* Bit mask for USB_XFERSIZE */ +#define _USB_HC_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_XFERSIZE_DEFAULT (_USB_HC_TSIZ_XFERSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PKTCNT_SHIFT 19 /* Shift value for USB_PKTCNT */ +#define _USB_HC_TSIZ_PKTCNT_MASK 0x1FF80000UL /* Bit mask for USB_PKTCNT */ +#define _USB_HC_TSIZ_PKTCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PKTCNT_DEFAULT (_USB_HC_TSIZ_PKTCNT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_SHIFT 29 /* Shift value for USB_PID */ +#define _USB_HC_TSIZ_PID_MASK 0x60000000UL /* Bit mask for USB_PID */ +#define _USB_HC_TSIZ_PID_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA0 0x00000000UL /* Mode DATA0 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA2 0x00000001UL /* Mode DATA2 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_DATA1 0x00000002UL /* Mode DATA1 for USB_HC_TSIZ */ +#define _USB_HC_TSIZ_PID_MDATA 0x00000003UL /* Mode MDATA for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DEFAULT (_USB_HC_TSIZ_PID_DEFAULT << 29) /* Shifted mode DEFAULT for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA0 (_USB_HC_TSIZ_PID_DATA0 << 29) /* Shifted mode DATA0 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA2 (_USB_HC_TSIZ_PID_DATA2 << 29) /* Shifted mode DATA2 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_DATA1 (_USB_HC_TSIZ_PID_DATA1 << 29) /* Shifted mode DATA1 for USB_HC_TSIZ */ +#define USB_HC_TSIZ_PID_MDATA (_USB_HC_TSIZ_PID_MDATA << 29) /* Shifted mode MDATA for USB_HC_TSIZ */ + +/* Bit fields for USB HC_DMAADDR */ + +#define _USB_HC_DMAADDR_RESETVALUE 0x00000000UL /* Default value for USB_HC_DMAADDR */ +#define _USB_HC_DMAADDR_MASK 0xFFFFFFFFUL /* Mask for USB_HC_DMAADDR */ + +#define _USB_HC_DMAADDR_DMAADDR_SHIFT 0 /* Shift value for USB_DMAADDR */ +#define _USB_HC_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /* Bit mask for USB_DMAADDR */ +#define _USB_HC_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HC_DMAADDR */ +#define USB_HC_DMAADDR_DMAADDR_DEFAULT (_USB_HC_DMAADDR_DMAADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HC_DMAADDR */ + +/* Bit fields for USB DCFG */ + +#define _USB_DCFG_RESETVALUE 0x08200000UL /* Default value for USB_DCFG */ +#define _USB_DCFG_MASK 0xFC001FFFUL /* Mask for USB_DCFG */ + +#define _USB_DCFG_DEVSPD_SHIFT 0 /* Shift value for USB_DEVSPD */ +#define _USB_DCFG_DEVSPD_MASK 0x3UL /* Bit mask for USB_DEVSPD */ +#define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_DEVSPD_LS 0x00000002UL /* Mode LS for USB_DCFG */ +#define _USB_DCFG_DEVSPD_FS 0x00000003UL /* Mode FS for USB_DCFG */ +#define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /* Shifted mode LS for USB_DCFG */ +#define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /* Shifted mode FS for USB_DCFG */ +#define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /* Non-Zero-Length Status OUT Handshake */ +#define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /* Shift value for USB_NZSTSOUTHSHK */ +#define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /* Bit mask for USB_NZSTSOUTHSHK */ +#define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /* Enable 32 KHz Suspend mode */ +#define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /* Shift value for USB_ENA32KHZSUSP */ +#define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /* Bit mask for USB_ENA32KHZSUSP */ +#define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_DEVADDR_SHIFT 4 /* Shift value for USB_DEVADDR */ +#define _USB_DCFG_DEVADDR_MASK 0x7F0UL /* Bit mask for USB_DEVADDR */ +#define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_SHIFT 11 /* Shift value for USB_PERFRINT */ +#define _USB_DCFG_PERFRINT_MASK 0x1800UL /* Bit mask for USB_PERFRINT */ +#define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /* Mode 80PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /* Mode 85PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /* Mode 90PCNT for USB_DCFG */ +#define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /* Mode 95PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DCFG */ +#define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /* Shifted mode 80PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /* Shifted mode 85PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /* Shifted mode 90PCNT for USB_DCFG */ +#define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /* Shifted mode 95PCNT for USB_DCFG */ +#define _USB_DCFG_RESVALID_SHIFT 26 /* Shift value for USB_RESVALID */ +#define _USB_DCFG_RESVALID_MASK 0xFC000000UL /* Bit mask for USB_RESVALID */ +#define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /* Mode DEFAULT for USB_DCFG */ +#define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /* Shifted mode DEFAULT for USB_DCFG */ + +/* Bit fields for USB DCTL */ + +#define _USB_DCTL_RESETVALUE 0x00000000UL /* Default value for USB_DCTL */ +#define _USB_DCTL_MASK 0x00018FFFUL /* Mask for USB_DCTL */ + +#define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /* Remote Wakeup Signaling */ +#define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /* Shift value for USB_RMTWKUPSIG */ +#define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /* Bit mask for USB_RMTWKUPSIG */ +#define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SFTDISCON (0x1UL << 1) /* Soft Disconnect */ +#define _USB_DCTL_SFTDISCON_SHIFT 1 /* Shift value for USB_SFTDISCON */ +#define _USB_DCTL_SFTDISCON_MASK 0x2UL /* Bit mask for USB_SFTDISCON */ +#define _USB_DCTL_SFTDISCON_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /* Global Non-periodic IN NAK Status */ +#define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /* Shift value for USB_GNPINNAKSTS */ +#define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /* Bit mask for USB_GNPINNAKSTS */ +#define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /* Global OUT NAK Status */ +#define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /* Shift value for USB_GOUTNAKSTS */ +#define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /* Bit mask for USB_GOUTNAKSTS */ +#define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DCTL */ +#define _USB_DCTL_TSTCTL_SHIFT 4 /* Shift value for USB_TSTCTL */ +#define _USB_DCTL_TSTCTL_MASK 0x70UL /* Bit mask for USB_TSTCTL */ +#define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /* Mode DISABLE for USB_DCTL */ +#define _USB_DCTL_TSTCTL_J 0x00000001UL /* Mode J for USB_DCTL */ +#define _USB_DCTL_TSTCTL_K 0x00000002UL /* Mode K for USB_DCTL */ +#define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /* Mode SE0NAK for USB_DCTL */ +#define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /* Mode PACKET for USB_DCTL */ +#define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /* Mode FORCE for USB_DCTL */ +#define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /* Shifted mode DISABLE for USB_DCTL */ +#define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /* Shifted mode J for USB_DCTL */ +#define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /* Shifted mode K for USB_DCTL */ +#define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /* Shifted mode SE0NAK for USB_DCTL */ +#define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /* Shifted mode PACKET for USB_DCTL */ +#define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /* Shifted mode FORCE for USB_DCTL */ +#define USB_DCTL_SGNPINNAK (0x1UL << 7) /* Set Global Non-periodic IN NAK */ +#define _USB_DCTL_SGNPINNAK_SHIFT 7 /* Shift value for USB_SGNPINNAK */ +#define _USB_DCTL_SGNPINNAK_MASK 0x80UL /* Bit mask for USB_SGNPINNAK */ +#define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGNPINNAK (0x1UL << 8) /* Clear Global Non-periodic IN NAK */ +#define _USB_DCTL_CGNPINNAK_SHIFT 8 /* Shift value for USB_CGNPINNAK */ +#define _USB_DCTL_CGNPINNAK_MASK 0x100UL /* Bit mask for USB_CGNPINNAK */ +#define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGOUTNAK (0x1UL << 9) /* Set Global OUT NAK */ +#define _USB_DCTL_SGOUTNAK_SHIFT 9 /* Shift value for USB_SGOUTNAK */ +#define _USB_DCTL_SGOUTNAK_MASK 0x200UL /* Bit mask for USB_SGOUTNAK */ +#define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGOUTNAK (0x1UL << 10) /* Clear Global OUT NAK */ +#define _USB_DCTL_CGOUTNAK_SHIFT 10 /* Shift value for USB_CGOUTNAK */ +#define _USB_DCTL_CGOUTNAK_MASK 0x400UL /* Bit mask for USB_CGOUTNAK */ +#define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /* Power-On Programming Done */ +#define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /* Shift value for USB_PWRONPRGDONE */ +#define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /* Bit mask for USB_PWRONPRGDONE */ +#define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /* Ignore Frame number For Isochronous End points */ +#define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /* Shift value for USB_IGNRFRMNUM */ +#define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /* Bit mask for USB_IGNRFRMNUM */ +#define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /* Shifted mode DEFAULT for USB_DCTL */ +#define USB_DCTL_NAKONBBLE (0x1UL << 16) /* NAK on Babble Error */ +#define _USB_DCTL_NAKONBBLE_SHIFT 16 /* Shift value for USB_NAKONBBLE */ +#define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /* Bit mask for USB_NAKONBBLE */ +#define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DCTL */ +#define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DCTL */ + +/* Bit fields for USB DSTS */ + +#define _USB_DSTS_RESETVALUE 0x00000002UL /* Default value for USB_DSTS */ +#define _USB_DSTS_MASK 0x003FFF0FUL /* Mask for USB_DSTS */ + +#define USB_DSTS_SUSPSTS (0x1UL << 0) /* Suspend Status */ +#define _USB_DSTS_SUSPSTS_SHIFT 0 /* Shift value for USB_SUSPSTS */ +#define _USB_DSTS_SUSPSTS_MASK 0x1UL /* Bit mask for USB_SUSPSTS */ +#define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_SHIFT 1 /* Shift value for USB_ENUMSPD */ +#define _USB_DSTS_ENUMSPD_MASK 0x6UL /* Bit mask for USB_ENUMSPD */ +#define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_LS 0x00000002UL /* Mode LS for USB_DSTS */ +#define _USB_DSTS_ENUMSPD_FS 0x00000003UL /* Mode FS for USB_DSTS */ +#define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DSTS */ +#define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /* Shifted mode LS for USB_DSTS */ +#define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /* Shifted mode FS for USB_DSTS */ +#define USB_DSTS_ERRTICERR (0x1UL << 3) /* Erratic Error */ +#define _USB_DSTS_ERRTICERR_SHIFT 3 /* Shift value for USB_ERRTICERR */ +#define _USB_DSTS_ERRTICERR_MASK 0x8UL /* Bit mask for USB_ERRTICERR */ +#define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DSTS */ +#define _USB_DSTS_SOFFN_SHIFT 8 /* Shift value for USB_SOFFN */ +#define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /* Bit mask for USB_SOFFN */ +#define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DSTS */ +#define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /* Shifted mode DEFAULT for USB_DSTS */ + +/* Bit fields for USB DIEPMSK */ + +#define _USB_DIEPMSK_RESETVALUE 0x00000000UL /* Default value for USB_DIEPMSK */ +#define _USB_DIEPMSK_MASK 0x0000215FUL /* Mask for USB_DIEPMSK */ + +#define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /* Transfer Completed Interrupt Mask */ +#define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /* Shift value for USB_XFERCOMPLMSK */ +#define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /* Bit mask for USB_XFERCOMPLMSK */ +#define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /* Endpoint Disabled Interrupt Mask */ +#define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /* Shift value for USB_EPDISBLDMSK */ +#define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /* Bit mask for USB_EPDISBLDMSK */ +#define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /* AHB Error Mask */ +#define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /* Shift value for USB_AHBERRMSK */ +#define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /* Bit mask for USB_AHBERRMSK */ +#define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /* Timeout Condition Mask */ +#define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /* Shift value for USB_TIMEOUTMSK */ +#define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /* Bit mask for USB_TIMEOUTMSK */ +#define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /* IN Token Received When TxFIFO Empty Mask */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /* Shift value for USB_INTKNTXFEMPMSK */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /* Bit mask for USB_INTKNTXFEMPMSK */ +#define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /* IN Endpoint NAK Effective Mask */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /* Shift value for USB_INEPNAKEFFMSK */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /* Bit mask for USB_INEPNAKEFFMSK */ +#define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /* Fifo Underrun Mask */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /* Shift value for USB_TXFIFOUNDRNMSK */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /* Bit mask for USB_TXFIFOUNDRNMSK */ +#define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /* Shifted mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_NAKMSK (0x1UL << 13) /* NAK interrupt Mask */ +#define _USB_DIEPMSK_NAKMSK_SHIFT 13 /* Shift value for USB_NAKMSK */ +#define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /* Bit mask for USB_NAKMSK */ +#define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPMSK */ +#define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DIEPMSK */ + +/* Bit fields for USB DOEPMSK */ + +#define _USB_DOEPMSK_RESETVALUE 0x00000000UL /* Default value for USB_DOEPMSK */ +#define _USB_DOEPMSK_MASK 0x0000315FUL /* Mask for USB_DOEPMSK */ + +#define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /* Transfer Completed Interrupt Mask */ +#define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /* Shift value for USB_XFERCOMPLMSK */ +#define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /* Bit mask for USB_XFERCOMPLMSK */ +#define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /* Endpoint Disabled Interrupt Mask */ +#define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /* Shift value for USB_EPDISBLDMSK */ +#define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /* Bit mask for USB_EPDISBLDMSK */ +#define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /* AHB Error */ +#define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /* Shift value for USB_AHBERRMSK */ +#define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /* Bit mask for USB_AHBERRMSK */ +#define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /* SETUP Phase Done Mask */ +#define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /* Shift value for USB_SETUPMSK */ +#define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /* Bit mask for USB_SETUPMSK */ +#define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /* OUT Token Received when Endpoint Disabled Mask */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /* Shift value for USB_OUTTKNEPDISMSK */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /* Bit mask for USB_OUTTKNEPDISMSK */ +#define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /* Back-to-Back SETUP Packets Received Mask */ +#define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /* Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /* Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /* OUT Packet Error Mask */ +#define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /* Shift value for USB_OUTPKTERRMSK */ +#define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /* Bit mask for USB_OUTPKTERRMSK */ +#define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /* Babble Error interrupt Mask */ +#define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /* Shift value for USB_BBLEERRMSK */ +#define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /* Bit mask for USB_BBLEERRMSK */ +#define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /* Shifted mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_NAKMSK (0x1UL << 13) /* NAK interrupt Mask */ +#define _USB_DOEPMSK_NAKMSK_SHIFT 13 /* Shift value for USB_NAKMSK */ +#define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /* Bit mask for USB_NAKMSK */ +#define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEPMSK */ +#define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DOEPMSK */ + +/* Bit fields for USB DAINT */ + +#define _USB_DAINT_RESETVALUE 0x00000000UL /* Default value for USB_DAINT */ +#define _USB_DAINT_MASK 0x007F007FUL /* Mask for USB_DAINT */ + +#define USB_DAINT_INEPINT0 (0x1UL << 0) /* IN Endpoint 0 Interrupt Bit */ +#define _USB_DAINT_INEPINT0_SHIFT 0 /* Shift value for USB_INEPINT0 */ +#define _USB_DAINT_INEPINT0_MASK 0x1UL /* Bit mask for USB_INEPINT0 */ +#define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT1 (0x1UL << 1) /* IN Endpoint 1 Interrupt Bit */ +#define _USB_DAINT_INEPINT1_SHIFT 1 /* Shift value for USB_INEPINT1 */ +#define _USB_DAINT_INEPINT1_MASK 0x2UL /* Bit mask for USB_INEPINT1 */ +#define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT2 (0x1UL << 2) /* IN Endpoint 2 Interrupt Bit */ +#define _USB_DAINT_INEPINT2_SHIFT 2 /* Shift value for USB_INEPINT2 */ +#define _USB_DAINT_INEPINT2_MASK 0x4UL /* Bit mask for USB_INEPINT2 */ +#define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT3 (0x1UL << 3) /* IN Endpoint 3 Interrupt Bit */ +#define _USB_DAINT_INEPINT3_SHIFT 3 /* Shift value for USB_INEPINT3 */ +#define _USB_DAINT_INEPINT3_MASK 0x8UL /* Bit mask for USB_INEPINT3 */ +#define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT4 (0x1UL << 4) /* IN Endpoint 4 Interrupt Bit */ +#define _USB_DAINT_INEPINT4_SHIFT 4 /* Shift value for USB_INEPINT4 */ +#define _USB_DAINT_INEPINT4_MASK 0x10UL /* Bit mask for USB_INEPINT4 */ +#define _USB_DAINT_INEPINT4_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT4_DEFAULT (_USB_DAINT_INEPINT4_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT5 (0x1UL << 5) /* IN Endpoint 5 Interrupt Bit */ +#define _USB_DAINT_INEPINT5_SHIFT 5 /* Shift value for USB_INEPINT5 */ +#define _USB_DAINT_INEPINT5_MASK 0x20UL /* Bit mask for USB_INEPINT5 */ +#define _USB_DAINT_INEPINT5_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT5_DEFAULT (_USB_DAINT_INEPINT5_DEFAULT << 5) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT6 (0x1UL << 6) /* IN Endpoint 6 Interrupt Bit */ +#define _USB_DAINT_INEPINT6_SHIFT 6 /* Shift value for USB_INEPINT6 */ +#define _USB_DAINT_INEPINT6_MASK 0x40UL /* Bit mask for USB_INEPINT6 */ +#define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT0 (0x1UL << 16) /* OUT Endpoint 0 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT0_SHIFT 16 /* Shift value for USB_OUTEPINT0 */ +#define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /* Bit mask for USB_OUTEPINT0 */ +#define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT1 (0x1UL << 17) /* OUT Endpoint 1 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT1_SHIFT 17 /* Shift value for USB_OUTEPINT1 */ +#define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /* Bit mask for USB_OUTEPINT1 */ +#define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT2 (0x1UL << 18) /* OUT Endpoint 2 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT2_SHIFT 18 /* Shift value for USB_OUTEPINT2 */ +#define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /* Bit mask for USB_OUTEPINT2 */ +#define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT3 (0x1UL << 19) /* OUT Endpoint 3 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT3_SHIFT 19 /* Shift value for USB_OUTEPINT3 */ +#define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /* Bit mask for USB_OUTEPINT3 */ +#define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT4 (0x1UL << 20) /* OUT Endpoint 4 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT4_SHIFT 20 /* Shift value for USB_OUTEPINT4 */ +#define _USB_DAINT_OUTEPINT4_MASK 0x100000UL /* Bit mask for USB_OUTEPINT4 */ +#define _USB_DAINT_OUTEPINT4_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT4_DEFAULT (_USB_DAINT_OUTEPINT4_DEFAULT << 20) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT5 (0x1UL << 21) /* OUT Endpoint 5 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT5_SHIFT 21 /* Shift value for USB_OUTEPINT5 */ +#define _USB_DAINT_OUTEPINT5_MASK 0x200000UL /* Bit mask for USB_OUTEPINT5 */ +#define _USB_DAINT_OUTEPINT5_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT5_DEFAULT (_USB_DAINT_OUTEPINT5_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT6 (0x1UL << 22) /* OUT Endpoint 6 Interrupt Bit */ +#define _USB_DAINT_OUTEPINT6_SHIFT 22 /* Shift value for USB_OUTEPINT6 */ +#define _USB_DAINT_OUTEPINT6_MASK 0x400000UL /* Bit mask for USB_OUTEPINT6 */ +#define _USB_DAINT_OUTEPINT6_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */ +#define USB_DAINT_OUTEPINT6_DEFAULT (_USB_DAINT_OUTEPINT6_DEFAULT << 22) /* Shifted mode DEFAULT for USB_DAINT */ + +/* Bit fields for USB DAINTMSK */ + +#define _USB_DAINTMSK_RESETVALUE 0x00000000UL /* Default value for USB_DAINTMSK */ +#define _USB_DAINTMSK_MASK 0x007F007FUL /* Mask for USB_DAINTMSK */ + +#define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /* IN Endpoint 0 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /* Shift value for USB_INEPMSK0 */ +#define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /* Bit mask for USB_INEPMSK0 */ +#define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /* IN Endpoint 1 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /* Shift value for USB_INEPMSK1 */ +#define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /* Bit mask for USB_INEPMSK1 */ +#define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /* IN Endpoint 2 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /* Shift value for USB_INEPMSK2 */ +#define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /* Bit mask for USB_INEPMSK2 */ +#define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /* IN Endpoint 3 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /* Shift value for USB_INEPMSK3 */ +#define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /* Bit mask for USB_INEPMSK3 */ +#define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK4 (0x1UL << 4) /* IN Endpoint 4 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK4_SHIFT 4 /* Shift value for USB_INEPMSK4 */ +#define _USB_DAINTMSK_INEPMSK4_MASK 0x10UL /* Bit mask for USB_INEPMSK4 */ +#define _USB_DAINTMSK_INEPMSK4_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK4_DEFAULT (_USB_DAINTMSK_INEPMSK4_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK5 (0x1UL << 5) /* IN Endpoint 5 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK5_SHIFT 5 /* Shift value for USB_INEPMSK5 */ +#define _USB_DAINTMSK_INEPMSK5_MASK 0x20UL /* Bit mask for USB_INEPMSK5 */ +#define _USB_DAINTMSK_INEPMSK5_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK5_DEFAULT (_USB_DAINTMSK_INEPMSK5_DEFAULT << 5) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK6 (0x1UL << 6) /* IN Endpoint 6 Interrupt mask Bit */ +#define _USB_DAINTMSK_INEPMSK6_SHIFT 6 /* Shift value for USB_INEPMSK6 */ +#define _USB_DAINTMSK_INEPMSK6_MASK 0x40UL /* Bit mask for USB_INEPMSK6 */ +#define _USB_DAINTMSK_INEPMSK6_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_INEPMSK6_DEFAULT (_USB_DAINTMSK_INEPMSK6_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /* OUT Endpoint 0 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /* Shift value for USB_OUTEPMSK0 */ +#define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /* Bit mask for USB_OUTEPMSK0 */ +#define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /* OUT Endpoint 1 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /* Shift value for USB_OUTEPMSK1 */ +#define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /* Bit mask for USB_OUTEPMSK1 */ +#define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /* OUT Endpoint 2 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /* Shift value for USB_OUTEPMSK2 */ +#define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /* Bit mask for USB_OUTEPMSK2 */ +#define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /* OUT Endpoint 3 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /* Shift value for USB_OUTEPMSK3 */ +#define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /* Bit mask for USB_OUTEPMSK3 */ +#define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK4 (0x1UL << 20) /* OUT Endpoint 4 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK4_SHIFT 20 /* Shift value for USB_OUTEPMSK4 */ +#define _USB_DAINTMSK_OUTEPMSK4_MASK 0x100000UL /* Bit mask for USB_OUTEPMSK4 */ +#define _USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK4_DEFAULT (_USB_DAINTMSK_OUTEPMSK4_DEFAULT << 20) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK5 (0x1UL << 21) /* OUT Endpoint 5 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK5_SHIFT 21 /* Shift value for USB_OUTEPMSK5 */ +#define _USB_DAINTMSK_OUTEPMSK5_MASK 0x200000UL /* Bit mask for USB_OUTEPMSK5 */ +#define _USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK5_DEFAULT (_USB_DAINTMSK_OUTEPMSK5_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK6 (0x1UL << 22) /* OUT Endpoint 6 Interrupt mask Bit */ +#define _USB_DAINTMSK_OUTEPMSK6_SHIFT 22 /* Shift value for USB_OUTEPMSK6 */ +#define _USB_DAINTMSK_OUTEPMSK6_MASK 0x400000UL /* Bit mask for USB_OUTEPMSK6 */ +#define _USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINTMSK */ +#define USB_DAINTMSK_OUTEPMSK6_DEFAULT (_USB_DAINTMSK_OUTEPMSK6_DEFAULT << 22) /* Shifted mode DEFAULT for USB_DAINTMSK */ + +/* Bit fields for USB DVBUSDIS */ + +#define _USB_DVBUSDIS_RESETVALUE 0x000017D7UL /* Default value for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_MASK 0x0000FFFFUL /* Mask for USB_DVBUSDIS */ + +#define _USB_DVBUSDIS_DVBUSDIS_SHIFT 0 /* Shift value for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_DVBUSDIS_MASK 0xFFFFUL /* Bit mask for USB_DVBUSDIS */ +#define _USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x000017D7UL /* Mode DEFAULT for USB_DVBUSDIS */ +#define USB_DVBUSDIS_DVBUSDIS_DEFAULT (_USB_DVBUSDIS_DVBUSDIS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DVBUSDIS */ + +/* Bit fields for USB DVBUSPULSE */ + +#define _USB_DVBUSPULSE_RESETVALUE 0x000005B8UL /* Default value for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_MASK 0x00000FFFUL /* Mask for USB_DVBUSPULSE */ + +#define _USB_DVBUSPULSE_DVBUSPULSE_SHIFT 0 /* Shift value for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_DVBUSPULSE_MASK 0xFFFUL /* Bit mask for USB_DVBUSPULSE */ +#define _USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x000005B8UL /* Mode DEFAULT for USB_DVBUSPULSE */ +#define USB_DVBUSPULSE_DVBUSPULSE_DEFAULT (_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DVBUSPULSE */ + +/* Bit fields for USB DIEPEMPMSK */ + +#define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /* Default value for USB_DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /* Mask for USB_DIEPEMPMSK */ + +#define _USB_DIEPEMPMSK_DIEPEMPMSK_SHIFT 0 /* Shift value for USB_DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_DIEPEMPMSK_MASK 0xFFFFUL /* Bit mask for USB_DIEPEMPMSK */ +#define _USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPEMPMSK */ +#define USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT (_USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPEMPMSK */ + +/* Bit fields for USB DIEP0CTL */ + +#define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /* Default value for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MASK 0xCFEE8003UL /* Mask for USB_DIEP0CTL */ + +#define _USB_DIEP0CTL_MPS_SHIFT 0 /* Shift value for USB_MPS */ +#define _USB_DIEP0CTL_MPS_MASK 0x3UL /* Bit mask for USB_MPS */ +#define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_64B 0x00000000UL /* Mode 64B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_32B 0x00000001UL /* Mode 32B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_16B 0x00000002UL /* Mode 16B for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_MPS_8B 0x00000003UL /* Mode 8B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /* Shifted mode 64B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /* Shifted mode 32B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /* Shifted mode 16B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /* Shifted mode 8B for USB_DIEP0CTL */ +#define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /* USB Active Endpoint */ +#define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /* Shift value for USB_USBACTEP */ +#define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /* Bit mask for USB_USBACTEP */ +#define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /* NAK Status */ +#define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /* Shift value for USB_NAKSTS */ +#define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /* Bit mask for USB_NAKSTS */ +#define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /* Shift value for USB_EPTYPE */ +#define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /* Bit mask for USB_EPTYPE */ +#define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_STALL (0x1UL << 21) /* Handshake */ +#define _USB_DIEP0CTL_STALL_SHIFT 21 /* Shift value for USB_STALL */ +#define _USB_DIEP0CTL_STALL_MASK 0x200000UL /* Bit mask for USB_STALL */ +#define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /* Shift value for USB_TXFNUM */ +#define _USB_DIEP0CTL_TXFNUM_MASK 0x3c00000UL /* Bit mask for USB_TXFNUM */ +#define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_CNAK (0x1UL << 26) /* Clear NAK */ +#define _USB_DIEP0CTL_CNAK_SHIFT 26 /* Shift value for USB_CNAK */ +#define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /* Bit mask for USB_CNAK */ +#define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_SNAK (0x1UL << 27) /* Set NAK */ +#define _USB_DIEP0CTL_SNAK_SHIFT 27 /* Shift value for USB_SNAK */ +#define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /* Bit mask for USB_SNAK */ +#define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPDIS (0x1UL << 30) /* Endpoint Disable */ +#define _USB_DIEP0CTL_EPDIS_SHIFT 30 /* Shift value for USB_EPDIS */ +#define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /* Bit mask for USB_EPDIS */ +#define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /* Shifted mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPENA (0x1UL << 31) /* Endpoint Enable */ +#define _USB_DIEP0CTL_EPENA_SHIFT 31 /* Shift value for USB_EPENA */ +#define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /* Bit mask for USB_EPENA */ +#define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0CTL */ +#define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /* Shifted mode DEFAULT for USB_DIEP0CTL */ + +/* Bit fields for USB DIEP0INT */ + +#define _USB_DIEP0INT_RESETVALUE 0x00000080UL /* Default value for USB_DIEP0INT */ +#define _USB_DIEP0INT_MASK 0x000038DFUL /* Mask for USB_DIEP0INT */ + +#define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /* Transfer Completed Interrupt */ +#define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /* Shift value for USB_XFERCOMPL */ +#define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /* Bit mask for USB_XFERCOMPL */ +#define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /* Endpoint Disabled Interrupt */ +#define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /* Shift value for USB_EPDISBLD */ +#define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /* Bit mask for USB_EPDISBLD */ +#define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_AHBERR (0x1UL << 2) /* AHB Error */ +#define _USB_DIEP0INT_AHBERR_SHIFT 2 /* Shift value for USB_AHBERR */ +#define _USB_DIEP0INT_AHBERR_MASK 0x4UL /* Bit mask for USB_AHBERR */ +#define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /* Timeout Condition */ +#define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /* Shift value for USB_TIMEOUT */ +#define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /* Bit mask for USB_TIMEOUT */ +#define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /* IN Token Received When TxFIFO is Empty */ +#define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /* Shift value for USB_INTKNTXFEMP */ +#define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /* Bit mask for USB_INTKNTXFEMP */ +#define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /* IN Endpoint NAK Effective */ +#define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /* Shift value for USB_INEPNAKEFF */ +#define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /* Bit mask for USB_INEPNAKEFF */ +#define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFEMP (0x1UL << 7) /* Transmit FIFO Empty */ +#define _USB_DIEP0INT_TXFEMP_SHIFT 7 /* Shift value for USB_TXFEMP */ +#define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /* Bit mask for USB_TXFEMP */ +#define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /* Packet Drop Status */ +#define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /* Shift value for USB_PKTDRPSTS */ +#define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /* Bit mask for USB_PKTDRPSTS */ +#define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_BBLEERR (0x1UL << 12) /* NAK Interrupt */ +#define _USB_DIEP0INT_BBLEERR_SHIFT 12 /* Shift value for USB_BBLEERR */ +#define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /* Bit mask for USB_BBLEERR */ +#define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /* Shifted mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /* NAK Interrupt */ +#define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /* Shift value for USB_NAKINTRPT */ +#define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /* Bit mask for USB_NAKINTRPT */ +#define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0INT */ +#define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DIEP0INT */ + +/* Bit fields for USB DIEP0TSIZ */ + +#define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /* Default value for USB_DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_MASK 0x0018007FUL /* Mask for USB_DIEP0TSIZ */ + +#define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /* Shift value for USB_XFERSIZE */ +#define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /* Bit mask for USB_XFERSIZE */ +#define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0TSIZ */ +#define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP0TSIZ */ +#define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /* Shift value for USB_PKTCNT */ +#define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /* Bit mask for USB_PKTCNT */ +#define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0TSIZ */ +#define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DIEP0TSIZ */ + +/* Bit fields for USB DIEP0DMAADDR */ + +#define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /* Default value for USB_DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /* Mask for USB_DIEP0DMAADDR */ + +#define _USB_DIEP0DMAADDR_DIEP0DMAADDR_SHIFT 0 /* Shift value for USB_DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /* Bit mask for USB_DIEP0DMAADDR */ +#define _USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP0DMAADDR */ +#define USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP0DMAADDR */ + +/* Bit fields for USB DIEP0TXFSTS */ + +#define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /* Default value for USB_DIEP0TXFSTS */ +#define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /* Mask for USB_DIEP0TXFSTS */ + +#define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /* Shift value for USB_SPCAVAIL */ +#define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /* Bit mask for USB_SPCAVAIL */ +#define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEP0TXFSTS */ +#define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP0TXFSTS */ + +/* Bit fields for USB DIEP_CTL */ + +#define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /* Default value for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /* Mask for USB_DIEP_CTL */ + +#define _USB_DIEP_CTL_MPS_SHIFT 0 /* Shift value for USB_MPS */ +#define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /* Bit mask for USB_MPS */ +#define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /* USB Active Endpoint */ +#define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /* Shift value for USB_USBACTEP */ +#define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /* Bit mask for USB_USBACTEP */ +#define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /* Endpoint Data PID / Even or Odd Frame */ +#define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /* Shift value for USB_DPIDEOF */ +#define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /* Bit mask for USB_DPIDEOF */ +#define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /* Mode DATA0EVEN for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /* Mode DATA1ODD for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /* Shifted mode DATA0EVEN for USB_DIEP_CTL */ +#define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /* Shifted mode DATA1ODD for USB_DIEP_CTL */ +#define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /* NAK Status */ +#define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /* Shift value for USB_NAKSTS */ +#define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /* Bit mask for USB_NAKSTS */ +#define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /* Shift value for USB_EPTYPE */ +#define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /* Bit mask for USB_EPTYPE */ +#define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /* Mode CONTROL for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /* Mode ISO for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /* Mode BULK for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /* Mode INT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /* Shifted mode CONTROL for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /* Shifted mode ISO for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /* Shifted mode BULK for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /* Shifted mode INT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_STALL (0x1UL << 21) /* Handshake */ +#define _USB_DIEP_CTL_STALL_SHIFT 21 /* Shift value for USB_STALL */ +#define _USB_DIEP_CTL_STALL_MASK 0x200000UL /* Bit mask for USB_STALL */ +#define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /* Shift value for USB_TXFNUM */ +#define _USB_DIEP_CTL_TXFNUM_MASK 0x3c00000UL /* Bit mask for USB_TXFNUM */ +#define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_CNAK (0x1UL << 26) /* Clear NAK */ +#define _USB_DIEP_CTL_CNAK_SHIFT 26 /* Shift value for USB_CNAK */ +#define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /* Bit mask for USB_CNAK */ +#define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SNAK (0x1UL << 27) /* Set NAK */ +#define _USB_DIEP_CTL_SNAK_SHIFT 27 /* Shift value for USB_SNAK */ +#define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /* Bit mask for USB_SNAK */ +#define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /* Set DATA0 PID / Even Frame */ +#define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /* Shift value for USB_SETD0PIDEF */ +#define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /* Bit mask for USB_SETD0PIDEF */ +#define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /* Set DATA1 PID / Odd Frame */ +#define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /* Shift value for USB_SETD1PIDOF */ +#define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /* Bit mask for USB_SETD1PIDOF */ +#define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPDIS (0x1UL << 30) /* Endpoint Disable */ +#define _USB_DIEP_CTL_EPDIS_SHIFT 30 /* Shift value for USB_EPDIS */ +#define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /* Bit mask for USB_EPDIS */ +#define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /* Shifted mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPENA (0x1UL << 31) /* Endpoint Enable */ +#define _USB_DIEP_CTL_EPENA_SHIFT 31 /* Shift value for USB_EPENA */ +#define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /* Bit mask for USB_EPENA */ +#define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_CTL */ +#define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /* Shifted mode DEFAULT for USB_DIEP_CTL */ + +/* Bit fields for USB DIEP_INT */ + +#define _USB_DIEP_INT_RESETVALUE 0x00000080UL /* Default value for USB_DIEP_INT */ +#define _USB_DIEP_INT_MASK 0x000038DFUL /* Mask for USB_DIEP_INT */ + +#define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /* Transfer Completed Interrupt */ +#define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /* Shift value for USB_XFERCOMPL */ +#define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /* Bit mask for USB_XFERCOMPL */ +#define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /* Endpoint Disabled Interrupt */ +#define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /* Shift value for USB_EPDISBLD */ +#define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /* Bit mask for USB_EPDISBLD */ +#define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_AHBERR (0x1UL << 2) /* AHB Error */ +#define _USB_DIEP_INT_AHBERR_SHIFT 2 /* Shift value for USB_AHBERR */ +#define _USB_DIEP_INT_AHBERR_MASK 0x4UL /* Bit mask for USB_AHBERR */ +#define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /* Timeout Condition */ +#define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /* Shift value for USB_TIMEOUT */ +#define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /* Bit mask for USB_TIMEOUT */ +#define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /* IN Token Received When TxFIFO is Empty */ +#define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /* Shift value for USB_INTKNTXFEMP */ +#define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /* Bit mask for USB_INTKNTXFEMP */ +#define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /* IN Endpoint NAK Effective */ +#define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /* Shift value for USB_INEPNAKEFF */ +#define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /* Bit mask for USB_INEPNAKEFF */ +#define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFEMP (0x1UL << 7) /* Transmit FIFO Empty */ +#define _USB_DIEP_INT_TXFEMP_SHIFT 7 /* Shift value for USB_TXFEMP */ +#define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /* Bit mask for USB_TXFEMP */ +#define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /* Packet Drop Status */ +#define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /* Shift value for USB_PKTDRPSTS */ +#define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /* Bit mask for USB_PKTDRPSTS */ +#define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_BBLEERR (0x1UL << 12) /* NAK Interrupt */ +#define _USB_DIEP_INT_BBLEERR_SHIFT 12 /* Shift value for USB_BBLEERR */ +#define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /* Bit mask for USB_BBLEERR */ +#define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /* Shifted mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /* NAK Interrupt */ +#define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /* Shift value for USB_NAKINTRPT */ +#define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /* Bit mask for USB_NAKINTRPT */ +#define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_INT */ +#define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DIEP_INT */ + +/* Bit fields for USB DIEP_TSIZ */ + +#define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /* Default value for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /* Mask for USB_DIEP_TSIZ */ + +#define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /* Shift value for USB_XFERSIZE */ +#define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /* Bit mask for USB_XFERSIZE */ +#define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /* Shift value for USB_PKTCNT */ +#define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /* Bit mask for USB_PKTCNT */ +#define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DIEP_TSIZ */ +#define _USB_DIEP_TSIZ_MC_SHIFT 29 /* Shift value for USB_MC */ +#define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /* Bit mask for USB_MC */ +#define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_TSIZ */ +#define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /* Shifted mode DEFAULT for USB_DIEP_TSIZ */ + +/* Bit fields for USB DIEP_DMAADDR */ + +#define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /* Default value for USB_DIEP_DMAADDR */ +#define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /* Mask for USB_DIEP_DMAADDR */ + +#define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /* Shift value for USB_DMAADDR */ +#define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /* Bit mask for USB_DMAADDR */ +#define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEP_DMAADDR */ +#define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP_DMAADDR */ + +/* Bit fields for USB DIEP_TXFSTS */ + +#define _USB_DIEP_TXFSTS_RESETVALUE 0x00000200UL /* Default value for USB_DIEP_TXFSTS */ +#define _USB_DIEP_TXFSTS_MASK 0x0000FFFFUL /* Mask for USB_DIEP_TXFSTS */ + +#define _USB_DIEP_TXFSTS_SPCAVAIL_SHIFT 0 /* Shift value for USB_SPCAVAIL */ +#define _USB_DIEP_TXFSTS_SPCAVAIL_MASK 0xFFFFUL /* Bit mask for USB_SPCAVAIL */ +#define _USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /* Mode DEFAULT for USB_DIEP_TXFSTS */ +#define USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEP_TXFSTS */ + +/* Bit fields for USB DOEP0CTL */ + +#define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /* Default value for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MASK 0xCC3E8003UL /* Mask for USB_DOEP0CTL */ + +#define _USB_DOEP0CTL_MPS_SHIFT 0 /* Shift value for USB_MPS */ +#define _USB_DOEP0CTL_MPS_MASK 0x3UL /* Bit mask for USB_MPS */ +#define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_64B 0x00000000UL /* Mode 64B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_32B 0x00000001UL /* Mode 32B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_16B 0x00000002UL /* Mode 16B for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_MPS_8B 0x00000003UL /* Mode 8B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /* Shifted mode 64B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /* Shifted mode 32B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /* Shifted mode 16B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /* Shifted mode 8B for USB_DOEP0CTL */ +#define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /* USB Active Endpoint */ +#define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /* Shift value for USB_USBACTEP */ +#define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /* Bit mask for USB_USBACTEP */ +#define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /* NAK Status */ +#define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /* Shift value for USB_NAKSTS */ +#define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /* Bit mask for USB_NAKSTS */ +#define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /* Shift value for USB_EPTYPE */ +#define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /* Bit mask for USB_EPTYPE */ +#define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNP (0x1UL << 20) /* Snoop Mode */ +#define _USB_DOEP0CTL_SNP_SHIFT 20 /* Shift value for USB_SNP */ +#define _USB_DOEP0CTL_SNP_MASK 0x100000UL /* Bit mask for USB_SNP */ +#define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_STALL (0x1UL << 21) /* Handshake */ +#define _USB_DOEP0CTL_STALL_SHIFT 21 /* Shift value for USB_STALL */ +#define _USB_DOEP0CTL_STALL_MASK 0x200000UL /* Bit mask for USB_STALL */ +#define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_CNAK (0x1UL << 26) /* Clear NAK */ +#define _USB_DOEP0CTL_CNAK_SHIFT 26 /* Shift value for USB_CNAK */ +#define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /* Bit mask for USB_CNAK */ +#define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNAK (0x1UL << 27) /* Set NAK */ +#define _USB_DOEP0CTL_SNAK_SHIFT 27 /* Shift value for USB_SNAK */ +#define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /* Bit mask for USB_SNAK */ +#define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPDIS (0x1UL << 30) /* Endpoint Disable */ +#define _USB_DOEP0CTL_EPDIS_SHIFT 30 /* Shift value for USB_EPDIS */ +#define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /* Bit mask for USB_EPDIS */ +#define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /* Shifted mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPENA (0x1UL << 31) /* Endpoint Enable */ +#define _USB_DOEP0CTL_EPENA_SHIFT 31 /* Shift value for USB_EPENA */ +#define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /* Bit mask for USB_EPENA */ +#define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0CTL */ +#define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /* Shifted mode DEFAULT for USB_DOEP0CTL */ + +/* Bit fields for USB DOEP0INT */ + +#define _USB_DOEP0INT_RESETVALUE 0x00000000UL /* Default value for USB_DOEP0INT */ +#define _USB_DOEP0INT_MASK 0x0000385FUL /* Mask for USB_DOEP0INT */ + +#define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /* Transfer Completed Interrupt */ +#define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /* Shift value for USB_XFERCOMPL */ +#define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /* Bit mask for USB_XFERCOMPL */ +#define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /* Endpoint Disabled Interrupt */ +#define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /* Shift value for USB_EPDISBLD */ +#define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /* Bit mask for USB_EPDISBLD */ +#define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_AHBERR (0x1UL << 2) /* AHB Error */ +#define _USB_DOEP0INT_AHBERR_SHIFT 2 /* Shift value for USB_AHBERR */ +#define _USB_DOEP0INT_AHBERR_MASK 0x4UL /* Bit mask for USB_AHBERR */ +#define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_SETUP (0x1UL << 3) /* Setup Phase Done */ +#define _USB_DOEP0INT_SETUP_SHIFT 3 /* Shift value for USB_SETUP */ +#define _USB_DOEP0INT_SETUP_MASK 0x8UL /* Bit mask for USB_SETUP */ +#define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /* OUT Token Received When Endpoint Disabled */ +#define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /* Shift value for USB_OUTTKNEPDIS */ +#define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /* Bit mask for USB_OUTTKNEPDIS */ +#define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /* Back-to-Back SETUP Packets Received */ +#define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /* Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /* Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /* Packet Drop Status */ +#define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /* Shift value for USB_PKTDRPSTS */ +#define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /* Bit mask for USB_PKTDRPSTS */ +#define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BBLEERR (0x1UL << 12) /* NAK Interrupt */ +#define _USB_DOEP0INT_BBLEERR_SHIFT 12 /* Shift value for USB_BBLEERR */ +#define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /* Bit mask for USB_BBLEERR */ +#define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /* Shifted mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /* NAK Interrupt */ +#define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /* Shift value for USB_NAKINTRPT */ +#define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /* Bit mask for USB_NAKINTRPT */ +#define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0INT */ +#define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DOEP0INT */ + +/* Bit fields for USB DOEP0TSIZ */ + +#define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /* Default value for USB_DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_MASK 0x6008007FUL /* Mask for USB_DOEP0TSIZ */ + +#define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /* Shift value for USB_XFERSIZE */ +#define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /* Bit mask for USB_XFERSIZE */ +#define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /* Packet Count */ +#define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /* Shift value for USB_PKTCNT */ +#define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /* Bit mask for USB_PKTCNT */ +#define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DOEP0TSIZ */ +#define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /* Shift value for USB_SUPCNT */ +#define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /* Bit mask for USB_SUPCNT */ +#define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0TSIZ */ +#define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /* Shifted mode DEFAULT for USB_DOEP0TSIZ */ + +/* Bit fields for USB DOEP0DMAADDR */ + +#define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /* Default value for USB_DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /* Mask for USB_DOEP0DMAADDR */ + +#define _USB_DOEP0DMAADDR_DOEP0DMAADDR_SHIFT 0 /* Shift value for USB_DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /* Bit mask for USB_DOEP0DMAADDR */ +#define _USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP0DMAADDR */ +#define USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP0DMAADDR */ + +/* Bit fields for USB DOEP_CTL */ + +#define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /* Default value for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /* Mask for USB_DOEP_CTL */ + +#define _USB_DOEP_CTL_MPS_SHIFT 0 /* Shift value for USB_MPS */ +#define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /* Bit mask for USB_MPS */ +#define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /* USB Active Endpoint */ +#define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /* Shift value for USB_USBACTEP */ +#define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /* Bit mask for USB_USBACTEP */ +#define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /* Endpoint Data PID / Even-odd Frame */ +#define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /* Shift value for USB_DPIDEOF */ +#define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /* Bit mask for USB_DPIDEOF */ +#define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /* Mode DATA0EVEN for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /* Mode DATA1ODD for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /* Shifted mode DATA0EVEN for USB_DOEP_CTL */ +#define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /* Shifted mode DATA1ODD for USB_DOEP_CTL */ +#define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /* NAK Status */ +#define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /* Shift value for USB_NAKSTS */ +#define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /* Bit mask for USB_NAKSTS */ +#define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /* Shift value for USB_EPTYPE */ +#define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /* Bit mask for USB_EPTYPE */ +#define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /* Mode CONTROL for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /* Mode ISO for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /* Mode BULK for USB_DOEP_CTL */ +#define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /* Mode INT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /* Shifted mode CONTROL for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /* Shifted mode ISO for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /* Shifted mode BULK for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /* Shifted mode INT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNP (0x1UL << 20) /* Snoop Mode */ +#define _USB_DOEP_CTL_SNP_SHIFT 20 /* Shift value for USB_SNP */ +#define _USB_DOEP_CTL_SNP_MASK 0x100000UL /* Bit mask for USB_SNP */ +#define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_STALL (0x1UL << 21) /* STALL Handshake */ +#define _USB_DOEP_CTL_STALL_SHIFT 21 /* Shift value for USB_STALL */ +#define _USB_DOEP_CTL_STALL_MASK 0x200000UL /* Bit mask for USB_STALL */ +#define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_CNAK (0x1UL << 26) /* Clear NAK */ +#define _USB_DOEP_CTL_CNAK_SHIFT 26 /* Shift value for USB_CNAK */ +#define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /* Bit mask for USB_CNAK */ +#define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNAK (0x1UL << 27) /* Set NAK */ +#define _USB_DOEP_CTL_SNAK_SHIFT 27 /* Shift value for USB_SNAK */ +#define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /* Bit mask for USB_SNAK */ +#define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /* Set DATA0 PID / Even Frame */ +#define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /* Shift value for USB_SETD0PIDEF */ +#define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /* Bit mask for USB_SETD0PIDEF */ +#define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /* Set DATA1 PID / Odd Frame */ +#define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /* Shift value for USB_SETD1PIDOF */ +#define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /* Bit mask for USB_SETD1PIDOF */ +#define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPDIS (0x1UL << 30) /* Endpoint Disable */ +#define _USB_DOEP_CTL_EPDIS_SHIFT 30 /* Shift value for USB_EPDIS */ +#define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /* Bit mask for USB_EPDIS */ +#define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /* Shifted mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPENA (0x1UL << 31) /* Endpoint Enable */ +#define _USB_DOEP_CTL_EPENA_SHIFT 31 /* Shift value for USB_EPENA */ +#define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /* Bit mask for USB_EPENA */ +#define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_CTL */ +#define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /* Shifted mode DEFAULT for USB_DOEP_CTL */ + +/* Bit fields for USB DOEP_INT */ + +#define _USB_DOEP_INT_RESETVALUE 0x00000000UL /* Default value for USB_DOEP_INT */ +#define _USB_DOEP_INT_MASK 0x0000385FUL /* Mask for USB_DOEP_INT */ + +#define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /* Transfer Completed Interrupt */ +#define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /* Shift value for USB_XFERCOMPL */ +#define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /* Bit mask for USB_XFERCOMPL */ +#define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /* Endpoint Disabled Interrupt */ +#define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /* Shift value for USB_EPDISBLD */ +#define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /* Bit mask for USB_EPDISBLD */ +#define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_AHBERR (0x1UL << 2) /* AHB Error */ +#define _USB_DOEP_INT_AHBERR_SHIFT 2 /* Shift value for USB_AHBERR */ +#define _USB_DOEP_INT_AHBERR_MASK 0x4UL /* Bit mask for USB_AHBERR */ +#define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_SETUP (0x1UL << 3) /* Setup Phase Done */ +#define _USB_DOEP_INT_SETUP_SHIFT 3 /* Shift value for USB_SETUP */ +#define _USB_DOEP_INT_SETUP_MASK 0x8UL /* Bit mask for USB_SETUP */ +#define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /* OUT Token Received When Endpoint Disabled */ +#define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /* Shift value for USB_OUTTKNEPDIS */ +#define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /* Bit mask for USB_OUTTKNEPDIS */ +#define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /* Back-to-Back SETUP Packets Received */ +#define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /* Shift value for USB_BACK2BACKSETUP */ +#define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /* Bit mask for USB_BACK2BACKSETUP */ +#define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /* Packet Drop Status */ +#define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /* Shift value for USB_PKTDRPSTS */ +#define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /* Bit mask for USB_PKTDRPSTS */ +#define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BBLEERR (0x1UL << 12) /* Babble Error */ +#define _USB_DOEP_INT_BBLEERR_SHIFT 12 /* Shift value for USB_BBLEERR */ +#define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /* Bit mask for USB_BBLEERR */ +#define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /* Shifted mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /* NAK Interrupt */ +#define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /* Shift value for USB_NAKINTRPT */ +#define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /* Bit mask for USB_NAKINTRPT */ +#define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_INT */ +#define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /* Shifted mode DEFAULT for USB_DOEP_INT */ + +/* Bit fields for USB DOEP_TSIZ */ + +#define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /* Default value for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /* Mask for USB_DOEP_TSIZ */ + +#define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /* Shift value for USB_XFERSIZE */ +#define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /* Bit mask for USB_XFERSIZE */ +#define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /* Shift value for USB_PKTCNT */ +#define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /* Bit mask for USB_PKTCNT */ +#define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /* Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /* Shift value for USB_RXDPIDSUPCNT */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /* Bit mask for USB_RXDPIDSUPCNT */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /* Mode DATA0 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /* Mode DATA2 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /* Mode DATA1 for USB_DOEP_TSIZ */ +#define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /* Mode MDATA for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /* Shifted mode DEFAULT for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /* Shifted mode DATA0 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /* Shifted mode DATA2 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /* Shifted mode DATA1 for USB_DOEP_TSIZ */ +#define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /* Shifted mode MDATA for USB_DOEP_TSIZ */ + +/* Bit fields for USB DOEP_DMAADDR */ + +#define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /* Default value for USB_DOEP_DMAADDR */ +#define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /* Mask for USB_DOEP_DMAADDR */ + +#define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /* Shift value for USB_DMAADDR */ +#define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /* Bit mask for USB_DMAADDR */ +#define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DOEP_DMAADDR */ +#define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DOEP_DMAADDR */ + +/* Bit fields for USB PCGCCTL */ + +#define _USB_PCGCCTL_RESETVALUE 0x00000000UL /* Default value for USB_PCGCCTL */ +#define _USB_PCGCCTL_MASK 0x0000014FUL /* Mask for USB_PCGCCTL */ + +#define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /* Stop PHY clock */ +#define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /* Shift value for USB_STOPPCLK */ +#define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /* Bit mask for USB_STOPPCLK */ +#define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /* Gate HCLK */ +#define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /* Shift value for USB_GATEHCLK */ +#define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /* Bit mask for USB_GATEHCLK */ +#define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /* Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /* Power Clamp */ +#define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /* Shift value for USB_PWRCLMP */ +#define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /* Bit mask for USB_PWRCLMP */ +#define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /* Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /* Reset Power-Down Modules */ +#define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /* Shift value for USB_RSTPDWNMODULE */ +#define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /* Bit mask for USB_RSTPDWNMODULE */ +#define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /* Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /* PHY In Sleep */ +#define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /* Shift value for USB_PHYSLEEP */ +#define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /* Bit mask for USB_PHYSLEEP */ +#define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /* Shifted mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RESETAFTERSUSP (0x1UL << 8) /* Reset after suspend */ +#define _USB_PCGCCTL_RESETAFTERSUSP_SHIFT 8 /* Shift value for USB_RESETAFTERSUSP */ +#define _USB_PCGCCTL_RESETAFTERSUSP_MASK 0x100UL /* Bit mask for USB_RESETAFTERSUSP */ +#define _USB_PCGCCTL_RESETAFTERSUSP_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_PCGCCTL */ +#define USB_PCGCCTL_RESETAFTERSUSP_DEFAULT (_USB_PCGCCTL_RESETAFTERSUSP_DEFAULT << 8) /* Shifted mode DEFAULT for USB_PCGCCTL */ + +/* Bit fields for USB FIFO0D */ + +#define _USB_FIFO0D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO0D */ +#define _USB_FIFO0D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO0D */ + +#define _USB_FIFO0D_FIFO0D_SHIFT 0 /* Shift value for USB_FIFO0D */ +#define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO0D */ +#define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO0D */ +#define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO0D */ + +/* Bit fields for USB FIFO1D */ + +#define _USB_FIFO1D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO1D */ +#define _USB_FIFO1D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO1D */ + +#define _USB_FIFO1D_FIFO1D_SHIFT 0 /* Shift value for USB_FIFO1D */ +#define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO1D */ +#define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO1D */ +#define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO1D */ + +/* Bit fields for USB FIFO2D */ + +#define _USB_FIFO2D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO2D */ +#define _USB_FIFO2D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO2D */ + +#define _USB_FIFO2D_FIFO2D_SHIFT 0 /* Shift value for USB_FIFO2D */ +#define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO2D */ +#define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO2D */ +#define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO2D */ + +/* Bit fields for USB FIFO3D */ + +#define _USB_FIFO3D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO3D */ +#define _USB_FIFO3D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO3D */ + +#define _USB_FIFO3D_FIFO3D_SHIFT 0 /* Shift value for USB_FIFO3D */ +#define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO3D */ +#define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO3D */ +#define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO3D */ + +/* Bit fields for USB FIFO4D */ + +#define _USB_FIFO4D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO4D */ +#define _USB_FIFO4D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO4D */ + +#define _USB_FIFO4D_FIFO4D_SHIFT 0 /* Shift value for USB_FIFO4D */ +#define _USB_FIFO4D_FIFO4D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO4D */ +#define _USB_FIFO4D_FIFO4D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO4D */ +#define USB_FIFO4D_FIFO4D_DEFAULT (_USB_FIFO4D_FIFO4D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO4D */ + +/* Bit fields for USB FIFO5D */ + +#define _USB_FIFO5D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO5D */ +#define _USB_FIFO5D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO5D */ + +#define _USB_FIFO5D_FIFO5D_SHIFT 0 /* Shift value for USB_FIFO5D */ +#define _USB_FIFO5D_FIFO5D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO5D */ +#define _USB_FIFO5D_FIFO5D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO5D */ +#define USB_FIFO5D_FIFO5D_DEFAULT (_USB_FIFO5D_FIFO5D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO5D */ + +/* Bit fields for USB FIFO6D */ + +#define _USB_FIFO6D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO6D */ +#define _USB_FIFO6D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO6D */ + +#define _USB_FIFO6D_FIFO6D_SHIFT 0 /* Shift value for USB_FIFO6D */ +#define _USB_FIFO6D_FIFO6D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO6D */ +#define _USB_FIFO6D_FIFO6D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO6D */ +#define USB_FIFO6D_FIFO6D_DEFAULT (_USB_FIFO6D_FIFO6D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO6D */ + +/* Bit fields for USB FIFO7D */ + +#define _USB_FIFO7D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO7D */ +#define _USB_FIFO7D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO7D */ + +#define _USB_FIFO7D_FIFO7D_SHIFT 0 /* Shift value for USB_FIFO7D */ +#define _USB_FIFO7D_FIFO7D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO7D */ +#define _USB_FIFO7D_FIFO7D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO7D */ +#define USB_FIFO7D_FIFO7D_DEFAULT (_USB_FIFO7D_FIFO7D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO7D */ + +/* Bit fields for USB FIFO8D */ + +#define _USB_FIFO8D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO8D */ +#define _USB_FIFO8D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO8D */ + +#define _USB_FIFO8D_FIFO8D_SHIFT 0 /* Shift value for USB_FIFO8D */ +#define _USB_FIFO8D_FIFO8D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO8D */ +#define _USB_FIFO8D_FIFO8D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO8D */ +#define USB_FIFO8D_FIFO8D_DEFAULT (_USB_FIFO8D_FIFO8D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO8D */ + +/* Bit fields for USB FIFO9D */ + +#define _USB_FIFO9D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO9D */ +#define _USB_FIFO9D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO9D */ + +#define _USB_FIFO9D_FIFO9D_SHIFT 0 /* Shift value for USB_FIFO9D */ +#define _USB_FIFO9D_FIFO9D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO9D */ +#define _USB_FIFO9D_FIFO9D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO9D */ +#define USB_FIFO9D_FIFO9D_DEFAULT (_USB_FIFO9D_FIFO9D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO9D */ + +/* Bit fields for USB FIFO10D */ + +#define _USB_FIFO10D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO10D */ +#define _USB_FIFO10D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO10D */ + +#define _USB_FIFO10D_FIFO10D_SHIFT 0 /* Shift value for USB_FIFO10D */ +#define _USB_FIFO10D_FIFO10D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO10D */ +#define _USB_FIFO10D_FIFO10D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO10D */ +#define USB_FIFO10D_FIFO10D_DEFAULT (_USB_FIFO10D_FIFO10D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO10D */ + +/* Bit fields for USB FIFO11D */ + +#define _USB_FIFO11D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO11D */ +#define _USB_FIFO11D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO11D */ + +#define _USB_FIFO11D_FIFO11D_SHIFT 0 /* Shift value for USB_FIFO11D */ +#define _USB_FIFO11D_FIFO11D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO11D */ +#define _USB_FIFO11D_FIFO11D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO11D */ +#define USB_FIFO11D_FIFO11D_DEFAULT (_USB_FIFO11D_FIFO11D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO11D */ + +/* Bit fields for USB FIFO12D */ + +#define _USB_FIFO12D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO12D */ +#define _USB_FIFO12D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO12D */ + +#define _USB_FIFO12D_FIFO12D_SHIFT 0 /* Shift value for USB_FIFO12D */ +#define _USB_FIFO12D_FIFO12D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO12D */ +#define _USB_FIFO12D_FIFO12D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO12D */ +#define USB_FIFO12D_FIFO12D_DEFAULT (_USB_FIFO12D_FIFO12D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO12D */ + +/* Bit fields for USB FIFO13D */ + +#define _USB_FIFO13D_RESETVALUE 0x00000000UL /* Default value for USB_FIFO13D */ +#define _USB_FIFO13D_MASK 0xFFFFFFFFUL /* Mask for USB_FIFO13D */ + +#define _USB_FIFO13D_FIFO13D_SHIFT 0 /* Shift value for USB_FIFO13D */ +#define _USB_FIFO13D_FIFO13D_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFO13D */ +#define _USB_FIFO13D_FIFO13D_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFO13D */ +#define USB_FIFO13D_FIFO13D_DEFAULT (_USB_FIFO13D_FIFO13D_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFO13D */ + +/* Bit fields for USB FIFORAM */ + +#define _USB_FIFORAM_RESETVALUE 0x00000000UL /* Default value for USB_FIFORAM */ +#define _USB_FIFORAM_MASK 0xFFFFFFFFUL /* Mask for USB_FIFORAM */ + +#define _USB_FIFORAM_FIFORAM_SHIFT 0 /* Shift value for USB_FIFORAM */ +#define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /* Bit mask for USB_FIFORAM */ +#define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_FIFORAM */ +#define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /* Shifted mode DEFAULT for USB_FIFORAM */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_USB_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_vcmp.h b/nuttx/arch/arm/src/efm32/chip/efm32_vcmp.h new file mode 100644 index 000000000..ec71abd87 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_vcmp.h @@ -0,0 +1,255 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_vcmp.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* VCMP Register Offsets *******************************************************************************************************/ + +#define EFM32_VCMP_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_VCMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */ +#define EFM32_VCMP_STATUS_OFFSET 0x0008 /* Status Register */ +#define EFM32_VCMP_IEN_OFFSET 0x000c /* Interrupt Enable Register */ +#define EFM32_VCMP_IF_OFFSET 0x0010 /* Interrupt Flag Register */ +#define EFM32_VCMP_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */ +#define EFM32_VCMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */ + +/* VCMP Register Addresses *****************************************************************************************************/ + +#define EFM32_VCMP_CTRL (EFM32_VCMP_BASE+EFM32_VCMP_CTRL_OFFSET) +#define EFM32_VCMP_INPUTSEL (EFM32_VCMP_BASE+EFM32_VCMP_INPUTSEL_OFFSET) +#define EFM32_VCMP_STATUS (EFM32_VCMP_BASE+EFM32_VCMP_STATUS_OFFSET) +#define EFM32_VCMP_IEN (EFM32_VCMP_BASE+EFM32_VCMP_IEN_OFFSET) +#define EFM32_VCMP_IF (EFM32_VCMP_BASE+EFM32_VCMP_IF_OFFSET) +#define EFM32_VCMP_IFS (EFM32_VCMP_BASE+EFM32_VCMP_IFS_OFFSET) +#define EFM32_VCMP_IFC (EFM32_VCMP_BASE+EFM32_VCMP_IFC_OFFSET) + +/* VCMP Register Bit Field Definitions *****************************************************************************************/ + +/* Bit fields for VCMP CTRL */ + +#define _VCMP_CTRL_RESETVALUE 0x47000000UL /* Default value for VCMP_CTRL */ +#define _VCMP_CTRL_MASK 0x4F030715UL /* Mask for VCMP_CTRL */ + +#define VCMP_CTRL_EN (0x1UL << 0) /* Voltage Supply Comparator Enable */ +#define _VCMP_CTRL_EN_SHIFT 0 /* Shift value for VCMP_EN */ +#define _VCMP_CTRL_EN_MASK 0x1UL /* Bit mask for VCMP_EN */ +#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_INACTVAL (0x1UL << 2) /* Inactive Value */ +#define _VCMP_CTRL_INACTVAL_SHIFT 2 /* Shift value for VCMP_INACTVAL */ +#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /* Bit mask for VCMP_INACTVAL */ +#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HYSTEN (0x1UL << 4) /* Hysteresis Enable */ +#define _VCMP_CTRL_HYSTEN_SHIFT 4 /* Shift value for VCMP_HYSTEN */ +#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /* Bit mask for VCMP_HYSTEN */ +#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_SHIFT 8 /* Shift value for VCMP_WARMTIME */ +#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /* Bit mask for VCMP_WARMTIME */ +#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /* Mode 4CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /* Mode 8CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /* Mode 16CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /* Mode 32CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /* Mode 64CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /* Mode 128CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /* Mode 256CYCLES for VCMP_CTRL */ +#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /* Mode 512CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /* Shifted mode 4CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /* Shifted mode 8CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /* Shifted mode 16CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /* Shifted mode 32CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /* Shifted mode 64CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /* Shifted mode 128CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /* Shifted mode 256CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /* Shifted mode 512CYCLES for VCMP_CTRL */ +#define VCMP_CTRL_IRISE (0x1UL << 16) /* Rising Edge Interrupt Sense */ +#define _VCMP_CTRL_IRISE_SHIFT 16 /* Shift value for VCMP_IRISE */ +#define _VCMP_CTRL_IRISE_MASK 0x10000UL /* Bit mask for VCMP_IRISE */ +#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_IFALL (0x1UL << 17) /* Falling Edge Interrupt Sense */ +#define _VCMP_CTRL_IFALL_SHIFT 17 /* Shift value for VCMP_IFALL */ +#define _VCMP_CTRL_IFALL_MASK 0x20000UL /* Bit mask for VCMP_IFALL */ +#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define _VCMP_CTRL_BIASPROG_SHIFT 24 /* Shift value for VCMP_BIASPROG */ +#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /* Bit mask for VCMP_BIASPROG */ +#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /* Shifted mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HALFBIAS (0x1UL << 30) /* Half Bias Current */ +#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /* Shift value for VCMP_HALFBIAS */ +#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /* Bit mask for VCMP_HALFBIAS */ +#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for VCMP_CTRL */ +#define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /* Shifted mode DEFAULT for VCMP_CTRL */ + +/* Bit fields for VCMP INPUTSEL */ + +#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /* Default value for VCMP_INPUTSEL */ +#define _VCMP_INPUTSEL_MASK 0x0000013FUL /* Mask for VCMP_INPUTSEL */ + +#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /* Shift value for VCMP_TRIGLEVEL */ +#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /* Bit mask for VCMP_TRIGLEVEL */ +#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_INPUTSEL */ +#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_INPUTSEL */ +#define VCMP_INPUTSEL_LPREF (0x1UL << 8) /* Low Power Reference */ +#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /* Shift value for VCMP_LPREF */ +#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /* Bit mask for VCMP_LPREF */ +#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_INPUTSEL */ +#define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /* Shifted mode DEFAULT for VCMP_INPUTSEL */ + +/* Bit fields for VCMP STATUS */ + +#define _VCMP_STATUS_RESETVALUE 0x00000000UL /* Default value for VCMP_STATUS */ +#define _VCMP_STATUS_MASK 0x00000003UL /* Mask for VCMP_STATUS */ + +#define VCMP_STATUS_VCMPACT (0x1UL << 0) /* Voltage Supply Comparator Active */ +#define _VCMP_STATUS_VCMPACT_SHIFT 0 /* Shift value for VCMP_VCMPACT */ +#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /* Bit mask for VCMP_VCMPACT */ +#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_STATUS */ +#define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_STATUS */ +#define VCMP_STATUS_VCMPOUT (0x1UL << 1) /* Voltage Supply Comparator Output */ +#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /* Shift value for VCMP_VCMPOUT */ +#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /* Bit mask for VCMP_VCMPOUT */ +#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_STATUS */ +#define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_STATUS */ + +/* Bit fields for VCMP IEN */ + +#define _VCMP_IEN_RESETVALUE 0x00000000UL /* Default value for VCMP_IEN */ +#define _VCMP_IEN_MASK 0x00000003UL /* Mask for VCMP_IEN */ + +#define VCMP_IEN_EDGE (0x1UL << 0) /* Edge Trigger Interrupt Enable */ +#define _VCMP_IEN_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */ +#define _VCMP_IEN_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */ +#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IEN */ +#define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IEN */ +#define VCMP_IEN_WARMUP (0x1UL << 1) /* Warm-up Interrupt Enable */ +#define _VCMP_IEN_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */ +#define _VCMP_IEN_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */ +#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IEN */ +#define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IEN */ + +/* Bit fields for VCMP IF */ + +#define _VCMP_IF_RESETVALUE 0x00000000UL /* Default value for VCMP_IF */ +#define _VCMP_IF_MASK 0x00000003UL /* Mask for VCMP_IF */ + +#define VCMP_IF_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag */ +#define _VCMP_IF_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */ +#define _VCMP_IF_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */ +#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IF */ +#define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IF */ +#define VCMP_IF_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag */ +#define _VCMP_IF_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */ +#define _VCMP_IF_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */ +#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IF */ +#define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IF */ + +/* Bit fields for VCMP IFS */ + +#define _VCMP_IFS_RESETVALUE 0x00000000UL /* Default value for VCMP_IFS */ +#define _VCMP_IFS_MASK 0x00000003UL /* Mask for VCMP_IFS */ + +#define VCMP_IFS_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Set */ +#define _VCMP_IFS_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */ +#define _VCMP_IFS_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */ +#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFS */ +#define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IFS */ +#define VCMP_IFS_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Set */ +#define _VCMP_IFS_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */ +#define _VCMP_IFS_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */ +#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFS */ +#define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IFS */ + +/* Bit fields for VCMP IFC */ + +#define _VCMP_IFC_RESETVALUE 0x00000000UL /* Default value for VCMP_IFC */ +#define _VCMP_IFC_MASK 0x00000003UL /* Mask for VCMP_IFC */ + +#define VCMP_IFC_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Clear */ +#define _VCMP_IFC_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */ +#define _VCMP_IFC_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */ +#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFC */ +#define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IFC */ +#define VCMP_IFC_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Clear */ +#define _VCMP_IFC_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */ +#define _VCMP_IFC_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */ +#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFC */ +#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IFC */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_wdog.h b/nuttx/arch/arm/src/efm32/chip/efm32_wdog.h new file mode 100644 index 000000000..4568dee15 --- /dev/null +++ b/nuttx/arch/arm/src/efm32/chip/efm32_wdog.h @@ -0,0 +1,178 @@ +/******************************************************************************************************************************* + * arch/arm/src/efm32/chip/efm32_wdog.h + * + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + * Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved. + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Authors: Pierre-noel Bouteville <pnb990@gmail.com> + * Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H +#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H + +/******************************************************************************************************************************* + * Included Files + *******************************************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip/efm32_memorymap.h" + +#if !defined(CONFIG_EFM32_EFM32GG) +# warning This is the EFM32GG header file; Review/modification needed for this archtecture +#endif + +/******************************************************************************************************************************* + * Pre-processor Definitions + *******************************************************************************************************************************/ +/* WDOG Register Offsets *******************************************************************************************************/ + +#define EFM32_WDOG_CTRL_OFFSET 0x0000 /* Control Register */ +#define EFM32_WDOG_CMD_OFFSET 0x0004 /* Command Register */ +#define EFM32_WDOG_SYNCBUSY_OFFSET 0x0008 /* Synchronization Busy Register */ + +/* WDOG Register Addresses *****************************************************************************************************/ + +#define EFM32_WDOG_CTRL (EFM32_WDOG_BASE+EFM32_WDOG_CTRL_OFFSET) +#define EFM32_WDOG_CMD (EFM32_WDOG_BASE+EFM32_WDOG_CMD_OFFSET) +#define EFM32_WDOG_SYNCBUSY (EFM32_WDOG_BASE+EFM32_WDOG_SYNCBUSY_OFFSET) + +/* WDOG Register Bit Field Definitions *****************************************************************************************/ + +/* Bit fields for WDOG CTRL */ + +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /* Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0x00003F7FUL /* Mask for WDOG_CTRL */ + +#define WDOG_CTRL_EN (0x1UL << 0) /* Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /* Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /* Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /* Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /* Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /* Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /* Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /* Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /* Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /* Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /* Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /* Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /* Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /* Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /* Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /* Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /* Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /* Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /* Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /* Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /* Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /* Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /* Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /* Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /* Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /* Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /* Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /* Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /* Mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /* Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /* Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /* Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /* Shifted mode LFXO for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ + +#define _WDOG_CMD_RESETVALUE 0x00000000UL /* Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /* Mask for WDOG_CMD */ + +#define WDOG_CMD_CLEAR (0x1UL << 0) /* Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /* Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /* Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /* Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /* Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /* Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /* Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ + +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000003UL /* Mask for WDOG_SYNCBUSY */ + +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /* CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /* Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /* Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /* Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H */ diff --git a/nuttx/arch/arm/src/efm32/chip/efm32g_memorymap.h b/nuttx/arch/arm/src/efm32/chip/efm32g_memorymap.h index 595bd9688..18fc11d24 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32g_memorymap.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32g_memorymap.h @@ -77,7 +77,7 @@ #define EFM32_USART0_BASE 0x4000c000 /* USART0 base address */ #define EFM32_USART1_BASE 0x4000c400 /* USART1 base address */ #define EFM32_USART2_BASE 0x4000c800 /* USART2 base address */ -#define EFM32_UART0_BASE 0x4000e00 /* UART0 base address */ +#define EFM32_UART0_BASE 0x4000e000 /* UART0 base address */ #define EFM32_TIMER0_BASE 0x40010000 /* TIMER0 base address */ #define EFM32_TIMER1_BASE 0x40010400 /* TIMER1 base address */ #define EFM32_TIMER2_BASE 0x40010800 /* TIMER2 base address */ diff --git a/nuttx/arch/arm/src/efm32/efm32_clockconfig.c b/nuttx/arch/arm/src/efm32/efm32_clockconfig.c index db6171926..014642939 100644 --- a/nuttx/arch/arm/src/efm32/efm32_clockconfig.c +++ b/nuttx/arch/arm/src/efm32/efm32_clockconfig.c @@ -166,7 +166,7 @@ static void efm32_enable_lfxo(void) { /* Enable the LFXO */ - putreg32(CMU_OSCENCMD_LFRCOEN, EFM32_CMU_OSCENCMD); + putreg32(CMU_OSCENCMD_LFXOEN, EFM32_CMU_OSCENCMD); efm32_statuswait(CMU_STATUS_LFXORDY); } @@ -550,8 +550,23 @@ static inline uint32_t efm32_hfcoreclk_config(uint32_t hfcoreclkdiv, static inline uint32_t efm32_hfperclk_config(uint32_t hfperclkdiv, uint32_t hfclk) { - /* REVISIT: Divider not currently used */ - return hfclk; + uint32_t regval; + unsigned int divider; + + DEBUGASSERT(hfperclkdiv <= _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512); + + /* Set the divider and enable the HFPERCLK */ + + regval = (hfperclkdiv << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) | + CMU_HFPERCLKDIV_HFPERCLKEN; + putreg32(regval, EFM32_CMU_HFPERCLKDIV); + + /* The value of hfperclkdiv is log2 of the arithmetic divisor: + * 0->1, 1->2, 2->4, 3->8, ... 9->512. + */ + + divider = 1 << hfperclkdiv; + return hfclk / divider; } /**************************************************************************** @@ -610,6 +625,7 @@ static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco, case CMU_LFCLKSEL_LFA_LFRCO: { efm32_enable_lfrco(); + lfaclk = BOARD_LFRCO_FREQUENCY; } break; @@ -642,11 +658,18 @@ static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco, /* Enable the LFA clock in the LFCLKSEL register */ regval = getreg32(EFM32_CMU_LFCLKSEL); - regval &= ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK); + +#ifdef CMU_LFCLKSEL_LFAE + regval &= ~_CMU_LFCLKSEL_LFAE_MASK; +#endif + + regval &= ~_CMU_LFCLKSEL_LFA_MASK; regval |= (lfaclksel << _CMU_LFCLKSEL_LFA_SHIFT); + #ifdef CMU_LFCLKSEL_LFAE_ULFRCO regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFAE_SHIFT); #endif + putreg32(regval, EFM32_CMU_LFCLKSEL); return lfaclk; @@ -736,11 +759,18 @@ static inline uint32_t efm32_lfbclk_config(uint32_t lfbclksel, bool ulfrco, /* Enable the LFB clock in the LFCLKSEL register */ regval = getreg32(EFM32_CMU_LFCLKSEL); - regval &= ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK); + +#ifdef CMU_LFCLKSEL_LFBE + regval &= ~_CMU_LFCLKSEL_LFBE_MASK; +#endif + + regval &= ~_CMU_LFCLKSEL_LFB_MASK; regval |= (lfbclksel << _CMU_LFCLKSEL_LFB_SHIFT); + #ifdef CMU_LFCLKSEL_LFBE_ULFRCO regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFBE_SHIFT); #endif + putreg32(regval, EFM32_CMU_LFCLKSEL); return lfbclk; @@ -845,7 +875,7 @@ static inline void efm32_itm_syslog(void) */ regval = getreg32(EFM32_GPIO_ROUTE); - regval &= _GPIO_ROUTE_SWLOCATION_MASK; + regval &= ~_GPIO_ROUTE_SWLOCATION_MASK; regval |= GPIO_ROUTE_SWOPEN; regval |= ((uint32_t)BOARD_SWOPORT_LOCATION << _GPIO_ROUTE_SWLOCATION_SHIFT); putreg32(regval, EFM32_GPIO_ROUTE); diff --git a/nuttx/arch/arm/src/efm32/efm32_gpio.c b/nuttx/arch/arm/src/efm32/efm32_gpio.c index 32bc200b0..847520fab 100644 --- a/nuttx/arch/arm/src/efm32/efm32_gpio.c +++ b/nuttx/arch/arm/src/efm32/efm32_gpio.c @@ -266,7 +266,7 @@ static inline void efm32_setmode(uintptr_t base, uint8_t pin, uint8_t mode) regval = getreg32(regaddr); regval &= ~((uint32_t)15 << shift); - regval |= ~((uint32_t)mode << shift); + regval |= (uint32_t)mode << shift; putreg32(regval, regaddr); } diff --git a/nuttx/arch/arm/src/efm32/efm32_leserial.c b/nuttx/arch/arm/src/efm32/efm32_leserial.c index b40e3d2b0..8284a6410 100644 --- a/nuttx/arch/arm/src/efm32/efm32_leserial.c +++ b/nuttx/arch/arm/src/efm32/efm32_leserial.c @@ -127,7 +127,6 @@ # define EFM32_RX_INTS LEUART_IEN_RXDATAV #endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -217,7 +216,7 @@ static char g_leuart1txbuffer[CONFIG_LEUART1_TXBUFSIZE]; /* This describes the state of the EFM32 LEUART0 port. */ #ifdef CONFIG_EFM32_LEUART0 -static const struct efm32_leuart_s g_leuart0config = +static const struct efm32_config_s g_leuart0config = { .uartbase = EFM32_LEUART0_BASE, .handler = efm32_leuart0_interrupt, diff --git a/nuttx/arch/arm/src/efm32/efm32_lowputc.c b/nuttx/arch/arm/src/efm32/efm32_lowputc.c index d5ca32f2e..f343d341a 100644 --- a/nuttx/arch/arm/src/efm32/efm32_lowputc.c +++ b/nuttx/arch/arm/src/efm32/efm32_lowputc.c @@ -51,6 +51,8 @@ #include "chip/efm32_usart.h" #include "chip/efm32_leuart.h" #include "chip/efm32_cmu.h" + +#include "efm32_gpio.h" #include "efm32_lowputc.h" /**************************************************************************** @@ -159,7 +161,7 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud) * baud = 2400.0 */ - maxover = ((BOARD_HFPERCLK_FREQUENCY << 8) / 280) / baud; + maxover = (((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) / 280) / baud; if (maxover >= 16) { DEBUGASSERT(baud <= (BOARD_HFPERCLK_FREQUENCY / 16)); @@ -204,17 +206,16 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud) clkdiv = 0; } - DEBUGASSERT(clkdiv <= _USART_CLKDIV_MASK); - - /* Set up the selected oversampling and baud */ + /* Set up the selected oversampling and baud divisor */ - regval = getreg32(base + EFM32_USART_CTRL_OFFSET); - regval &= ~_USART_CTRL_OVS_MASK; - regval |= ovs; + regval = getreg32(base + EFM32_USART_CTRL_OFFSET); + regval &= ~_USART_CTRL_OVS_MASK; + regval |= ovs; putreg32(regval, base + EFM32_USART_CTRL_OFFSET); - putreg32((uint32_t)clkdiv & _USART_CLKDIV_DIV_MASK, - base + EFM32_USART_CLKDIV_OFFSET); + regval = (uint32_t)clkdiv << _USART_CLKDIV_DIV_SHIFT; + DEBUGASSERT((regval & _USART_CLKDIV_MASK) == regval); + putreg32(regval, base + EFM32_USART_CLKDIV_OFFSET); } #endif @@ -322,9 +323,15 @@ void efm32_lowsetup(void) #endif /* HAVE_UART_DEVICE */ #ifdef HAVE_LEUART_DEVICE + /* Enable the LE interface clock must be enabled in CMU_HFCORECLKEN0 */ + + regval = getreg32(EFM32_CMU_HFCORECLKEN0); + regval |= CMU_HFCORECLKEN0_LE; + putreg32(regval, EFM32_CMU_HFCORECLKEN0); + /* Enable clocking to configured LEUART interfaces */ - regval = getreg32(EFM32_CMU_LFBCLKEN0); + regval = getreg32(EFM32_CMU_LFBCLKEN0); regval &= ~(CMU_LFBCLKEN0_LEUART0 #ifdef CONFIG_EFM32_LEUART1 | CMU_LFBCLKEN0_LEUART1 @@ -342,9 +349,71 @@ void efm32_lowsetup(void) putreg32(regval, EFM32_CMU_LFBCLKEN0); #endif /* HAVE_LEUART_DEVICE */ - /* Set location in the ROUTE register */ +#if defined(HAVE_UART_DEVICE) || defined(HAVE_SPI_DEVICE) + /* Enable output on U[S]ART output pins */ + +#ifdef CONFIG_EFM32_USART0 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART0_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART0_TX_GPIO); +#ifdef CONFIG_EFM32_USART0_ISSPI + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART0_CLK_GPIO); +#endif +#endif + +#ifdef CONFIG_EFM32_USART1 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART1_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART1_TX_GPIO); +#ifdef CONFIG_EFM32_USART1_ISSPI + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART1_CLK_GPIO); +#endif +#endif + +#ifdef CONFIG_EFM32_USART2 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_USART2_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART2_TX_GPIO); +#ifdef CONFIG_EFM32_USART2_ISSPI + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_USART2_CLK_GPIO); +#endif +#endif + +#ifdef CONFIG_EFM32_UART0 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_UART0_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_UART0_TX_GPIO); +#endif + +#ifdef CONFIG_EFM32_UART1 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_UART1_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_UART1_TX_GPIO); +#endif +#endif /* HAVE_UART_DEVICE */ + +#ifdef HAVE_LEUART_DEVICE + /* Enable output on LEUART output pins */ + +#ifdef CONFIG_EFM32_LEUART0 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_LEUART0_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_LEUART0_TX_GPIO); +#endif + +#ifdef CONFIG_EFM32_LEUART1 + efm32_configgpio(GPIO_INPUT | GPIO_INT_NONE | BOARD_LEUART1_RX_GPIO); + efm32_configgpio(GPIO_OUTPUT_PUSHPULL | GPIO_OUTPUT_CLEAR | + GPIO_DRIVE_STANDARD | BOARD_LEUART1_TX_GPIO); +#endif +#endif /* HAVE_LEUART_DEVICE */ + +#if defined(HAVE_UART_DEVICE) || defined(HAVE_SPI_DEVICE) + /* Set location in the U[S]ART ROUTE registers */ -#ifdef HAVE_UART_DEVICE #ifdef CONFIG_EFM32_USART0 regval = (USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | (BOARD_USART0_ROUTE_LOCATION << _USART_ROUTE_LOCATION_SHIFT)); @@ -386,13 +455,15 @@ void efm32_lowsetup(void) #endif /* HAVE_UART_DEVICE */ #ifdef HAVE_LEUART_DEVICE -#ifdef CONFIG_EFM32_UART0 + /* Set location in the LEUART ROUTE registers */ + +#ifdef CONFIG_EFM32_LEUART0 regval = (LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | (BOARD_LEUART0_ROUTE_LOCATION << _LEUART_ROUTE_LOCATION_SHIFT)); putreg32(regval, EFM32_LEUART0_ROUTE); #endif -#ifdef CONFIG_EFM32_UART1 +#ifdef CONFIG_EFM32_LEUART1 regval = (LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | (BOARD_LEUART1_ROUTE_LOCATION << _LEUART_ROUTE_LOCATION_SHIFT)); putreg32(regval, EFM32_LEUART1_ROUTE); @@ -547,7 +618,6 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, case 2: regval |= USART_FRAME_PARITY_EVEN; break; - } /* Configure stop bits */ diff --git a/nuttx/arch/arm/src/efm32/efm32_serial.c b/nuttx/arch/arm/src/efm32/efm32_serial.c index a3dafd3b0..06e16af93 100644 --- a/nuttx/arch/arm/src/efm32/efm32_serial.c +++ b/nuttx/arch/arm/src/efm32/efm32_serial.c @@ -100,7 +100,7 @@ #elif defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart0port /* UART0 is console */ # define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define UART1_ASSIGNED 1 +# define UART0_ASSIGNED 1 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1port /* UART1 is console */ # define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ @@ -198,8 +198,7 @@ #define EFM32_TXERR_INTS (USART_IEN_TXOF) #define EFM32_RXERR_INTS (USART_IEN_RXOF | USART_IEN_RXUF | \ - USART_IEN_TXUF | USART_IEN_PERR | \ - USART_IEN_FERR) + USART_IEN_PERR | USART_IEN_FERR) #ifdef CONFIG_DEBUG # define EFM32_TX_INTS (USART_IEN_TXBL | EFM32_TXERR_INTS) # define EFM32_RX_INTS (USART_IEN_RXDATAV | EFM32_RXERR_INTS) @@ -241,7 +240,9 @@ static inline void efm32_serialout(struct efm32_usart_s *priv, int offset, static inline void efm32_setuartint(struct efm32_usart_s *priv); static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien); +#ifdef HAVE_UART_CONSOLE static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien); +#endif static int efm32_setup(struct uart_dev_s *dev); static void efm32_shutdown(struct uart_dev_s *dev); static int efm32_attach(struct uart_dev_s *dev); @@ -359,15 +360,15 @@ static struct uart_dev_s g_usart0port = .recv = { .size = CONFIG_USART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, + .buffer = g_usart0rxbuffer, }, .xmit = { .size = CONFIG_USART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, + .buffer = g_usart0txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart0priv, + .priv = &g_usart0priv, }; #endif @@ -397,15 +398,15 @@ static struct uart_dev_s g_usart1port = .recv = { .size = CONFIG_USART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, + .buffer = g_usart1rxbuffer, }, .xmit = { .size = CONFIG_USART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, + .buffer = g_usart1txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart1priv, + .priv = &g_usart1priv, }; #endif @@ -435,15 +436,15 @@ static struct uart_dev_s g_usart2port = .recv = { .size = CONFIG_USART2_RXBUFSIZE, - .buffer = g_uart2rxbuffer, + .buffer = g_usart2rxbuffer, }, .xmit = { .size = CONFIG_USART2_TXBUFSIZE, - .buffer = g_uart2txbuffer, + .buffer = g_usart2txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart2priv, + .priv = &g_usart2priv, }; #endif @@ -575,6 +576,7 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien) * Name: efm32_disableuartint ****************************************************************************/ +#ifdef HAVE_UART_CONSOLE static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien) { irqstate_t flags; @@ -588,6 +590,7 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien) efm32_restoreuartint(priv, 0); irqrestore(flags); } +#endif /**************************************************************************** * Name: efm32_setup @@ -1126,6 +1129,7 @@ static bool efm32_txempty(struct uart_dev_s *dev) * ****************************************************************************/ +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void) { /* Disable interrupts from all UARTS. The console is enabled in @@ -1153,6 +1157,7 @@ void up_earlyserialinit(void) efm32_setup(&CONSOLE_DEV); #endif } +#endif /**************************************************************************** * Name: up_serialinit diff --git a/nuttx/arch/arm/src/efm32/efm32_spi.c b/nuttx/arch/arm/src/efm32/efm32_spi.c index 9a5fc1f59..6a427281b 100644 --- a/nuttx/arch/arm/src/efm32/efm32_spi.c +++ b/nuttx/arch/arm/src/efm32/efm32_spi.c @@ -60,6 +60,7 @@ #include "up_arch.h" #include "chip.h" +#include "chip/efm32_usart.h" #include "efm32_config.h" #include "efm32_dma.h" #include "efm32_lowputc.h" diff --git a/nuttx/arch/arm/src/efm32/efm32_start.c b/nuttx/arch/arm/src/efm32/efm32_start.c index 655e4e10f..eab75ae3b 100644 --- a/nuttx/arch/arm/src/efm32/efm32_start.c +++ b/nuttx/arch/arm/src/efm32/efm32_start.c @@ -51,15 +51,23 @@ #include "up_arch.h" #include "up_internal.h" + #include "efm32_config.h" #include "efm32_lowputc.h" #include "efm32_clockconfig.h" #include "efm32_start.h" +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + /**************************************************************************** * Private Function prototypes ****************************************************************************/ +#ifdef CONFIG_ARCH_FPU +static inline void efm32_fpuconfig(void); +#endif #ifdef CONFIG_DEBUG_STACK static void go_os_start(void *pv, unsigned int nbytes) __attribute__ ((naked,no_instrument_function,noreturn)); @@ -90,6 +98,96 @@ static void go_os_start(void *pv, unsigned int nbytes) #endif /**************************************************************************** + * Name: efm32_fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#ifdef CONFIG_ARMV7M_CMNVECTOR + +static inline void efm32_fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#else + +static inline void efm32_fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#endif + +#else +# define efm32_fpuconfig() +#endif + +/**************************************************************************** * Name: go_os_start * * Description: @@ -149,6 +247,7 @@ void __start(void) /* Configure the uart so that we can get debug output as soon as possible */ efm32_clockconfig(); + efm32_fpuconfig(); efm32_lowsetup(); showprogress('A'); @@ -179,7 +278,6 @@ void __start(void) /* Perform early serial initialization */ up_earlyserialinit(); - showprogress('D'); /* For the case of the separate user-/kernel-space build, perform whatever @@ -193,6 +291,11 @@ void __start(void) showprogress('E'); #endif + /* Initialize onboard resources */ + + efm32_boardinitialize(); + showprogress('F'); + /* Then start NuttX */ showprogress('\r'); diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index fa4b7bd99..464bec6b7 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -583,12 +583,14 @@ config SAM34_UART0 default y depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E select ARCH_HAVE_UART0 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_UART1 bool "UART 1" default n depends on ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_UDP bool "USB Device Full Speed (UDP)" @@ -615,23 +617,27 @@ config SAM34_USART0 bool "USART 0" default n select ARCH_HAVE_USART0 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_USART1 bool "USART 1" default n select ARCH_HAVE_USART1 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_USART2 bool "USART 2" default n - select ARCH_HAVE_USART2 depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L + select ARCH_HAVE_USART2 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_USART3 bool "USART 3" default n - select ARCH_HAVE_USART3 depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4CM || ARCH_CHIP_SAM4L + select ARCH_HAVE_USART3 + select ARCH_HAVE_SERIAL_TERMIOS config SAM34_WDT bool "Watchdog Timer (WDT)" diff --git a/nuttx/arch/arm/src/sam34/chip/sam_tc.h b/nuttx/arch/arm/src/sam34/chip/sam_tc.h index 9e6002d3e..42dd58cc8 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_tc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_tc.h @@ -370,11 +370,11 @@ #if defined(CONFIG_ARCH_CHIP_SAM4E) #define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */ #define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT) -# define TC_CMR_SBSMPLR_ ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */ -# define TC_CMR_SBSMPLR_ HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */ -# define TC_CMR_SBSMPLR_ 4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */ -# define TC_CMR_SBSMPLR_ 8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */ -# define TC_CMR_SBSMPLR_ 16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */ +# define TC_CMR_SBSMPLR_ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */ +# define TC_CMR_SBSMPLR_HALF (1 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 2 selected edges */ +# define TC_CMR_SBSMPLR_4TH (2 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 4 selected edges */ +# define TC_CMR_SBSMPLR_8TH (3 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 8 selected edges */ +# define TC_CMR_SBSMPLR_16TH (4 << TC_CMR_SBSMPLR_SHIFT) /* Load on every 16 selected edges */ #endif /* TC Channel Mode Register -- Waveform mode only */ diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index 745fada33..4395de517 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -48,6 +48,10 @@ #include <errno.h> #include <debug.h> +#ifdef CONFIG_SERIAL_TERMIOS +# include <termios.h> +#endif + #include <nuttx/irq.h> #include <nuttx/arch.h> #include <nuttx/serial/serial.h> @@ -71,7 +75,7 @@ #endif /**************************************************************************** - * Definitions + * Pre-processor Definitions ****************************************************************************/ /* Some sanity checks *******************************************************/ @@ -106,6 +110,17 @@ # define HAVE_USART #endif +/* Hardware flow control requires using the PDC or DMAC channel for reception */ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +# warning PDC or DMAC support is required for RTS hardware flow control +# undef CONFIG_SERIAL_IFLOWCONTROL +# undef CONFIG_USART0_IFLOWCONTROL +# undef CONFIG_USART1_IFLOWCONTROL +# undef CONFIG_USART2_IFLOWCONTROL +# undef CONFIG_USART3_IFLOWCONTROL +#endif + /* Is there a serial console? It could be on UART0-1 or USART0-3 */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) @@ -339,13 +354,16 @@ struct up_dev_s { - uint32_t usartbase; /* Base address of USART registers */ - uint32_t baud; /* Configured baud */ - uint32_t sr; /* Saved status bits */ - uint8_t irq; /* IRQ associated with this USART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + const uint32_t usartbase; /* Base address of USART registers */ + uint32_t baud; /* Configured baud */ + uint32_t sr; /* Saved status bits */ + uint8_t irq; /* IRQ associated with this USART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; /* input flow control (RTS) enabled */ +#endif }; /**************************************************************************** @@ -487,6 +505,9 @@ static struct up_dev_s g_usart0priv = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .stopbits2 = CONFIG_USART0_2STOP, +#if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL) + .flowc = true, +#endif }; static uart_dev_t g_usart0port = @@ -517,6 +538,9 @@ static struct up_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, +#if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL) + .flowc = true, +#endif }; static uart_dev_t g_usart1port = @@ -547,6 +571,9 @@ static struct up_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, +#if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL) + .flowc = true, +#endif }; static uart_dev_t g_usart2port = @@ -577,6 +604,9 @@ static struct up_dev_s g_usart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, +#if defined(CONFIG_USART3_OFLOWCONTROL) || defined(CONFIG_USART3_IFLOWCONTROL) + .flowc = true, +#endif }; static uart_dev_t g_usart3port = @@ -680,7 +710,28 @@ static int up_setup(struct uart_dev_s *dev) * as the timing source */ - regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS); +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + /* "Setting the USART to operate with hardware handshaking is performed by + * writing the USART_MODE field in the Mode Register (US_MR) to the value + * 0x2. ... Using this mode requires using the PDC or DMAC channel for + * reception. The transmitter can handle hardware handshaking in any case." + */ + + if (priv->flowc) + { + /* Enable hardware flow control and MCK as the timing source */ + + regval = (UART_MR_MODE_HWHS | SAM_MR_USCLKS); + } + else +#endif + { + /* Set up the mode register. Start with normal UART mode and the MCK + * as the timing source + */ + + regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS); + } /* OR in settings for the selected number of bits */ @@ -760,6 +811,7 @@ static int up_setup(struct uart_dev_s *dev) up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN)); #endif + return OK; } @@ -959,7 +1011,7 @@ static int up_interrupt(int irq, void *context) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif @@ -983,6 +1035,159 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios*)arg; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0; +#endif + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + + case 9: + termiosp->c_cflag |= CS8 /* CS9 */; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios*)arg; + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t baud; + uint8_t parity; + uint8_t nbits; + bool stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; +#endif + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; +#if 0 + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Decode flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0; +#endif + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + priv->flowc = flowc; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + ret = up_setup(dev); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + default: ret = -ENOTTY; break; @@ -1154,6 +1359,7 @@ static bool up_txempty(struct uart_dev_s *dev) * ****************************************************************************/ +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void) { /* NOTE: All GPIO configuration for the USARTs was performed in @@ -1186,6 +1392,7 @@ void up_earlyserialinit(void) up_setup(&CONSOLE_DEV); #endif } +#endif /**************************************************************************** * Name: up_serialinit diff --git a/nuttx/arch/sim/include/limits.h b/nuttx/arch/sim/include/limits.h index 5a8d7c54e..fabb97d8e 100644 --- a/nuttx/arch/sim/include/limits.h +++ b/nuttx/arch/sim/include/limits.h @@ -77,10 +77,15 @@ #define LLONG_MAX 9223372036854775807LL #define ULLONG_MAX 18446744073709551615ULL -/* A pointer is 4 bytes */ +/* A pointer is 4 or 8 bytes */ #define PTR_MIN (-PTR_MAX - 1) -#define PTR_MAX 2147483647 -#define UPTR_MAX 4294967295U +#if !defined(CONFIG_HOST_X86_64) || defined(CONFIG_SIM_M32) +# define PTR_MAX 2147483647 +# define UPTR_MAX 4294967295U +#else +# define PTR_MAX 9223372036854775807LL +# define UPTR_MAX 18446744073709551615ULL +#endif #endif /* __ARCH_SIM_INCLUDE_LIMITS_H */ diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index dad113ed3..9941eaf63 100755 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -985,7 +985,7 @@ config BOARD_CUSTOM_BUTTONS bool "Custom board buttons" default n select ARCH_HAVE_BUTTONS - select ARCH__BUTTONS + select ARCH_BUTTONS config BOARD_CUSTOM_IRQBUTTONS bool "Custom Board IRQ buttons" diff --git a/nuttx/configs/efm32-g8xx-stk/README.txt b/nuttx/configs/efm32-g8xx-stk/README.txt index 2ce5d1718..958e35c0f 100644 --- a/nuttx/configs/efm32-g8xx-stk/README.txt +++ b/nuttx/configs/efm32-g8xx-stk/README.txt @@ -16,11 +16,47 @@ README • On-board SEGGER J-Link USB emulator • ARM 20 pin JTAG/SWD standard Debug in/out connector +CONTENTS +======= + + • Status + • LEDs + • Serial Console + • Using the J-Link GDB Server + • Configurations + STATUS ====== - My board is on order and has not arrived as of this writing. So no debug - has yet been done. So the status is code-complete but untested. + 2014-10-28. At this point all basic boot operations are successful: The + LEDs work and the application tasks appear to be successfully started. + LED2 is on and LED0 is glowing (meaning that interrupts are being + processed). However, I get no output on PE0. Data appears to be sent + (at least by efm32_lowputc()). However, no signal activity is present + on PE0. + + 2014-10-29: The NuttX is running on the EFM32 Gecko Starter Kit. There + are not many peripherals to test in that configuration, but the NuttShell + (NSH) is working over LEUART0 at 2400 baud (certainly that could go up + to 4800. The documentation says that 9600 is also possible on the + LEUART, but I am not sure how). + + I originally planned to use UART0 at 115200 baud, but I never could get + any output from the board. I reviewd my pin configuration and clocking + carefully and the USART seems to think it is working correctly. So I + am thinking that there is some board issue that prohibits that option + (probably because UART0 is used with the board controller???). Pins + are not available for other U[S]ARTs on the board. + + DMA and USART-based SPI supported are included, but not yet tested. + + 2014-10-29: Calibrated the delays loops. + + 2014-10-29: The start-up time is long -- about a second. I have traced + this to the default delay in bringing up the LFCLK in efm32_clockconfig. + The default, reset setting of the LFXOTIMEOUT field of the CMU_CTRL + register is 3 which corresponds to a delay of 32768 cycles, or a full + second. I have not experimented to see if this delay can be reduced. LEDs ==== @@ -45,7 +81,7 @@ LEDs include/board.h and src/efm32_autoleds.c. The LEDs are used to encode OS-related events as follows: - SYMBOL Meaning LED1* LED2 LED3 LED4 + SYMBOL Meaning LED0* LED1 LED2 LED3 ----------------- ----------------------- ------ ----- ----- ------ LED_STARTED NuttX has been started ON OFF OFF OFF LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF @@ -57,14 +93,14 @@ LEDs LED_PANIC The system has crashed N/C N/C N/C ON LED_IDLE STM32 is is sleep mode (Optional, not used) - * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot + * If LED0, LED1, LED2 are statically on, then NuttX probably failed to boot and these LEDs will give you some indication of where the failure was - ** The normal state is LED3 ON and LED1 faintly glowing. This faint glow + ** The normal state is LED2 ON and LED3 faintly glowing. This faint glow is because of timer interrupt that result in the LED being illuminated on a small proportion of the time. -*** LED2 may also flicker normally if signals are processed. +*** LED1 may also flicker normally if signals are processed. -Serial Console +SERIAL CONSOLE ============== Pin Availability @@ -122,8 +158,15 @@ Serial Console Default Serial Console ---------------------- - UART0 is configured as the default serial console at 115200 8N1 - on pins PE0 and PE1. + LEUART0 is configured as the default serial console at 2400 8N1 + on pins PD5 and PD4. It certainly be possible to go to 4800 baud + and the documentation claims that 9600 baud is possible (although + I am not sure how). + + It should also be possible to use UART0 is configured at 115200 8N1 + on pins PE0 and PE1. However, my attempts to use USART0 were + unsuccessful -- I see no activity on PE0 and PE1 and have not yet + figured out why that is. Communication through the Board Controller ------------------------------------------ @@ -133,8 +176,58 @@ Serial Console send commands to the BC. When EFM_BC_EN is low, EFM_BC_TX and EFM_BC_RX can be used by other applications. -Configurations +USING THE J-LINK GDB SERVER +=========================== + + 1. Star the J-Link GDB server. You should see the start-up confiration + window. SelectL + + a. Target device = EFM32G880F128 + b. Select Target interface = SWD + + 2. Press OK. The GDB server should start and the last message in the Log + output should be "Waiting for GDB connection". + + 3. In a terminal window, start GDB: + + arm-none-eabi-gdb + + 4. Connect to the J-Link GDB serer: + + (gdb) target remote local host + + 5. Load and run nuttx + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset go + + I had to tinker with the setup a few times repeating the same steps above + before things finally began to work. Don't know why. + + To debug code already burned into FLASH: + + 1. Start the GDB server as above. + + 2. In a terminal window, start GDB: + + arm-none-eabi-gdb + + 3. Connect to the J-Link GDB serer: + + (gdb) target remote local host + + 3. Load the nuttx symbol file, reset, and debug + + (gdb) mon halt + (gdb) file nuttx + (gdb) mon reset + (gdb) s + ... + +CONFIGURATIONS ============== + Each EFM32 Gecko Starter Kit configuration is maintained in a sub-directory and can be selected as follow: @@ -153,9 +246,7 @@ Configurations nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. The - Configuration enables the serial interfaces on UART0. Support for - built-in applications is enabled, but in the base configuration no - built-in applications are selected (see NOTES below). + Configuration enables the serial interfaces on LEUART0 at 2400 8N1. NOTES: diff --git a/nuttx/configs/efm32-g8xx-stk/include/board.h b/nuttx/configs/efm32-g8xx-stk/include/board.h index 62035cc82..ffcd64f2b 100644 --- a/nuttx/configs/efm32-g8xx-stk/include/board.h +++ b/nuttx/configs/efm32-g8xx-stk/include/board.h @@ -172,37 +172,32 @@ /* LED index values for use with efm32_setled() */ -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 +#define BOARD_LED0 0 +#define BOARD_LED1 1 +#define BOARD_LED2 2 +#define BOARD_LED3 3 #define BOARD_NLEDS 4 -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_BLUE BOARD_LED4 - /* LED bits for use with efm32_setleds() */ +#define BOARD_LED0_BIT (1 << BOARD_LED0) #define BOARD_LED1_BIT (1 << BOARD_LED1) #define BOARD_LED2_BIT (1 << BOARD_LED2) #define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on * board the EFM32 Gecko Starter Kit. The following definitions describe * how NuttX controls the LEDs in this configuration: */ -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ +#define LED_STARTED 0 /* LED0 */ +#define LED_HEAPALLOCATE 1 /* LED1 */ +#define LED_IRQSENABLED 2 /* LED0 + LED1 */ +#define LED_STACKCREATED 3 /* LED2 */ +#define LED_INIRQ 4 /* LED0 + LED2 */ +#define LED_SIGNAL 5 /* LED1 + LED3 */ +#define LED_ASSERTION 6 /* LED0 + LED2 + LED2 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED3 */ /* Pin routing **************************************************************/ /* UART0: @@ -211,8 +206,20 @@ * U0_TX #1 PE0 **AVAILABLE at TP129** */ +#define BOARD_UART0_RX_GPIO (GPIO_PORTE|GPIO_PIN1) +#define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0) #define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1 +/* LEUART0: + * + * LEU0_RX #0 PD5 **AVAILABLE at TP123 and EXP port pin 14** + * LEU0_TX #0 PD4 **AVAILABLE at TP122 and EXP port pin 12** + */ + +#define BOARD_LEUART0_RX_GPIO (GPIO_PORTD|GPIO_PIN5) +#define BOARD_LEUART0_TX_GPIO (GPIO_PORTD|GPIO_PIN4) +#define BOARD_LEUART0_ROUTE_LOCATION _LEUART_ROUTE_LOCATION_LOC0 + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/nuttx/configs/efm32-g8xx-stk/nsh/defconfig b/nuttx/configs/efm32-g8xx-stk/nsh/defconfig index 753669d80..afcc12342 100644 --- a/nuttx/configs/efm32-g8xx-stk/nsh/defconfig +++ b/nuttx/configs/efm32-g8xx-stk/nsh/defconfig @@ -141,17 +141,29 @@ CONFIG_EFM32_HAVE_UART0=y CONFIG_EFM32_HAVE_LEUART1=y # CONFIG_EFM32_USART_ISUART is not set # CONFIG_EFM32_USART_ISSPI is not set -CONFIG_EFM32_UART=y -# CONFIG_EFM32_LEUART is not set +# CONFIG_EFM32_UART is not set +CONFIG_EFM32_LEUART=y # CONFIG_EFM32_DMA is not set # CONFIG_EFM32_USART0 is not set # CONFIG_EFM32_USART1 is not set # CONFIG_EFM32_USART2 is not set -CONFIG_EFM32_UART0=y +# CONFIG_EFM32_UART0 is not set # CONFIG_EFM32_UART1 is not set -# CONFIG_EFM32_LEUART0 is not set +CONFIG_EFM32_LEUART0=y # CONFIG_EFM32_LEUART1 is not set CONFIG_EFM32_GPIO_IRQ=y +CONFIG_LEUART0_SERIAL_CONSOLE=y +# CONFIG_NO_LEUART_SERIAL_CONSOLE is not set + +# +# LEUART0 Configuration +# +CONFIG_LEUART0_RXBUFSIZE=64 +CONFIG_LEUART0_TXBUFSIZE=64 +CONFIG_LEUART0_BAUD=2400 +CONFIG_LEUART0_BITS=8 +CONFIG_LEUART0_PARITY=0 +CONFIG_LEUART0_2STOP=0 # # Architecture Options @@ -180,7 +192,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4531 +CONFIG_BOARD_LOOPSPERMSEC=2662 # CONFIG_ARCH_CALIBRATION is not set # @@ -374,7 +386,7 @@ CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set # CONFIG_ARCH_HAVE_UART is not set -CONFIG_ARCH_HAVE_UART0=y +# CONFIG_ARCH_HAVE_UART0 is not set # CONFIG_ARCH_HAVE_UART1 is not set # CONFIG_ARCH_HAVE_UART2 is not set # CONFIG_ARCH_HAVE_UART3 is not set @@ -394,7 +406,7 @@ CONFIG_ARCH_HAVE_UART0=y # CONFIG_ARCH_HAVE_USART6 is not set # CONFIG_ARCH_HAVE_USART7 is not set # CONFIG_ARCH_HAVE_USART8 is not set -# CONFIG_ARCH_HAVE_OTHER_UART is not set +CONFIG_ARCH_HAVE_OTHER_UART=y # # USART Configuration @@ -402,21 +414,9 @@ CONFIG_ARCH_HAVE_UART0=y CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_UART0_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_UART0_SERIAL_CONSOLE is not set +CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART0 Configuration -# -CONFIG_UART0_RXBUFSIZE=64 -CONFIG_UART0_TXBUFSIZE=64 -CONFIG_UART0_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART0_2STOP=0 -# CONFIG_UART0_IFLOWCONTROL is not set -# CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_USBDEV is not set diff --git a/nuttx/configs/efm32-g8xx-stk/src/efm32-g8xx-stk.h b/nuttx/configs/efm32-g8xx-stk/src/efm32-g8xx-stk.h index aa4876007..ea11a95db 100644 --- a/nuttx/configs/efm32-g8xx-stk/src/efm32-g8xx-stk.h +++ b/nuttx/configs/efm32-g8xx-stk/src/efm32-g8xx-stk.h @@ -78,13 +78,13 @@ * value to the LED. */ -#define GPIO_LED1 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ +#define GPIO_LED0 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN0) -#define GPIO_LED2 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ +#define GPIO_LED1 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN1) -#define GPIO_LED3 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ +#define GPIO_LED2 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN2) -#define GPIO_LED4 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ +#define GPIO_LED3 (GPIO_OUTPUT_WIREDOR_PULLDOWN|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN3) /**************************************************************************** diff --git a/nuttx/configs/efm32-g8xx-stk/src/efm32_autoleds.c b/nuttx/configs/efm32-g8xx-stk/src/efm32_autoleds.c index 1860281c2..6681e2e51 100644 --- a/nuttx/configs/efm32-g8xx-stk/src/efm32_autoleds.c +++ b/nuttx/configs/efm32-g8xx-stk/src/efm32_autoleds.c @@ -72,10 +72,10 @@ /* The following definitions map the encoded LED setting to GPIO settings */ -#define EFM32F4_LED1 (1 << 0) -#define EFM32F4_LED2 (1 << 1) -#define EFM32F4_LED3 (1 << 2) -#define EFM32F4_LED4 (1 << 3) +#define EFM32_LED0 (1 << 0) +#define EFM32_LED1 (1 << 1) +#define EFM32_LED2 (1 << 2) +#define EFM32_LED3 (1 << 3) #define ON_SETBITS_SHIFT (0) #define ON_CLRBITS_SHIFT (4) @@ -92,45 +92,45 @@ #define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) #define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) -#define LED_STARTED_ON_SETBITS ((EFM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_ON_SETBITS ((EFM32_LED0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((EFM32_LED1|EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT) #define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((EFM32F4_LED1|EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((EFM32_LED0|EFM32_LED1|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_SETBITS ((EFM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((EFM32F4_LED1|EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((EFM32F4_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((EFM32F4_LED2|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_SETBITS ((EFM32_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((EFM32_LED0|EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((EFM32_LED0) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((EFM32_LED1|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT) -#define LED_IRQSENABLED_ON_SETBITS ((EFM32F4_LED1|EFM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((EFM32F4_LED3|EFM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((EFM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((EFM32F4_LED1|EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_IRQSENABLED_ON_SETBITS ((EFM32_LED0|EFM32_LED1) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((EFM32_LED2|EFM32_LED3) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((EFM32_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((EFM32_LED0|EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT) -#define LED_STACKCREATED_ON_SETBITS ((EFM32F4_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((EFM32F4_LED1|EFM32F4_LED2|EFM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((EFM32F4_LED1|EFM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((EFM32F4_LED3|EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_STACKCREATED_ON_SETBITS ((EFM32_LED2) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((EFM32_LED0|EFM32_LED1|EFM32_LED3) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((EFM32_LED0|EFM32_LED1) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((EFM32_LED2|EFM32_LED3) << OFF_CLRBITS_SHIFT) -#define LED_INIRQ_ON_SETBITS ((EFM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_SETBITS ((EFM32_LED0) << ON_SETBITS_SHIFT) #define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) #define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((EFM32F4_LED1) << OFF_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((EFM32_LED0) << OFF_CLRBITS_SHIFT) -#define LED_SIGNAL_ON_SETBITS ((EFM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_SETBITS ((EFM32_LED1) << ON_SETBITS_SHIFT) #define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) #define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((EFM32F4_LED2) << OFF_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((EFM32_LED1) << OFF_CLRBITS_SHIFT) -#define LED_ASSERTION_ON_SETBITS ((EFM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_SETBITS ((EFM32_LED3) << ON_SETBITS_SHIFT) #define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) #define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((EFM32_LED3) << OFF_CLRBITS_SHIFT) -#define LED_PANIC_ON_SETBITS ((EFM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_SETBITS ((EFM32_LED3) << ON_SETBITS_SHIFT) #define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) #define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((EFM32F4_LED4) << OFF_CLRBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((EFM32_LED3) << OFF_CLRBITS_SHIFT) /**************************************************************************** * Private Data @@ -169,47 +169,47 @@ static const uint16_t g_ledbits[8] = static inline void led_clrbits(unsigned int clrbits) { - if ((clrbits & EFM32F4_LED1) != 0) + if ((clrbits & EFM32_LED0) != 0) { - efm32_gpiowrite(GPIO_LED1, false); + efm32_gpiowrite(GPIO_LED0, false); } - if ((clrbits & EFM32F4_LED2) != 0) + if ((clrbits & EFM32_LED1) != 0) { - efm32_gpiowrite(GPIO_LED2, false); + efm32_gpiowrite(GPIO_LED1, false); } - if ((clrbits & EFM32F4_LED3) != 0) + if ((clrbits & EFM32_LED2) != 0) { - efm32_gpiowrite(GPIO_LED3, false); + efm32_gpiowrite(GPIO_LED2, false); } - if ((clrbits & EFM32F4_LED4) != 0) + if ((clrbits & EFM32_LED3) != 0) { - efm32_gpiowrite(GPIO_LED4, false); + efm32_gpiowrite(GPIO_LED3, false); } } static inline void led_setbits(unsigned int setbits) { - if ((setbits & EFM32F4_LED1) != 0) + if ((setbits & EFM32_LED0) != 0) { - efm32_gpiowrite(GPIO_LED1, true); + efm32_gpiowrite(GPIO_LED0, true); } - if ((setbits & EFM32F4_LED2) != 0) + if ((setbits & EFM32_LED1) != 0) { - efm32_gpiowrite(GPIO_LED2, true); + efm32_gpiowrite(GPIO_LED1, true); } - if ((setbits & EFM32F4_LED3) != 0) + if ((setbits & EFM32_LED2) != 0) { - efm32_gpiowrite(GPIO_LED3, true); + efm32_gpiowrite(GPIO_LED2, true); } - if ((setbits & EFM32F4_LED4) != 0) + if ((setbits & EFM32_LED3) != 0) { - efm32_gpiowrite(GPIO_LED4, true); + efm32_gpiowrite(GPIO_LED3, true); } } @@ -229,12 +229,12 @@ static void led_setonoff(unsigned int bits) void board_led_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED0-4 GPIOs for output */ + efm32_configgpio(GPIO_LED0); efm32_configgpio(GPIO_LED1); efm32_configgpio(GPIO_LED2); efm32_configgpio(GPIO_LED3); - efm32_configgpio(GPIO_LED4); } /**************************************************************************** diff --git a/nuttx/configs/efm32-g8xx-stk/src/efm32_userleds.c b/nuttx/configs/efm32-g8xx-stk/src/efm32_userleds.c index 503e17aec..4d35200f3 100644 --- a/nuttx/configs/efm32-g8xx-stk/src/efm32_userleds.c +++ b/nuttx/configs/efm32-g8xx-stk/src/efm32_userleds.c @@ -78,7 +78,7 @@ static gpio_pinset_t g_ledcfg[BOARD_NLEDS] = { - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 + GPIO_LED0, GPIO_LED1, GPIO_LED2, GPIO_LED3 }; /**************************************************************************** @@ -193,12 +193,12 @@ static int led_pm_prepare(struct pm_callback_s *cb , enum pm_state_e pmstate) void efm32_ledinit(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED0-4 GPIOs for output */ + efm32_configgpio(GPIO_LED0); efm32_configgpio(GPIO_LED1); efm32_configgpio(GPIO_LED2); efm32_configgpio(GPIO_LED3); - efm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -219,10 +219,10 @@ void efm32_setled(int led, bool ledon) void efm32_setleds(uint8_t ledset) { - efm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - efm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - efm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - efm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); + efm32_gpiowrite(GPIO_LED0, (ledset & BOARD_LED0_BIT) != 0); + efm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + efm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + efm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); } /**************************************************************************** diff --git a/nuttx/configs/mcu123-lpc214x/README.txt b/nuttx/configs/mcu123-lpc214x/README.txt index 8ce4534ab..228499438 100644 --- a/nuttx/configs/mcu123-lpc214x/README.txt +++ b/nuttx/configs/mcu123-lpc214x/README.txt @@ -146,7 +146,7 @@ LPC21ISP (Linux) (ca. 2008) I use the lpc21isp tool to load NuttX into FLASH. That tool is available -in the files section at http://tech.groups.yahoo.com/group/lpc21isp/. In +in the files section at https://groups.yahoo.com/neo/groups/lpc21isp/info. In the older version 1.60 of lpc21isp for Linux, I had to make several changes. This changes are shown in lpc21ips-1.60.diff. diff --git a/nuttx/configs/mirtoo/README.txt b/nuttx/configs/mirtoo/README.txt index 150017b56..80723b82f 100644 --- a/nuttx/configs/mirtoo/README.txt +++ b/nuttx/configs/mirtoo/README.txt @@ -390,7 +390,7 @@ Toolchains well. This toolchain can be downloded from the Pinguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Pinguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 Support for the Pinguino mips-elf toolchain has been included in the Mirtoo configurations. Use one of these configuration options to select the Pinguino @@ -426,7 +426,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/configs/olimex-efm32g880f128-stk/include/board.h b/nuttx/configs/olimex-efm32g880f128-stk/include/board.h index 45fd4fa15..f2d844fde 100644 --- a/nuttx/configs/olimex-efm32g880f128-stk/include/board.h +++ b/nuttx/configs/olimex-efm32g880f128-stk/include/board.h @@ -237,6 +237,8 @@ * U0_TX #1 PE0 **AVAILABLE at EXT-18** */ +#define BOARD_UART0_RX_GPIO (GPIO_PORTE|GPIO_PIN1) +#define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0) #define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1 /* LEUART1: @@ -245,6 +247,8 @@ * LEU1_TX #0 PC6 LEU1_TX to DB-9 connector */ +#define BOARD_LEUART1_RX_GPIO (GPIO_PORTC|GPIO_PIN7) +#define BOARD_LEUART1_TX_GPIO (GPIO_PORTC|GPIO_PIN6) #define BOARD_LEUART1_ROUTE_LOCATION _LEUART_ROUTE_LOCATION_LOC0 /**************************************************************************** diff --git a/nuttx/configs/olimex-efm32g880f128-stk/nsh/defconfig b/nuttx/configs/olimex-efm32g880f128-stk/nsh/defconfig index 065e7ffab..b7a8dd310 100644 --- a/nuttx/configs/olimex-efm32g880f128-stk/nsh/defconfig +++ b/nuttx/configs/olimex-efm32g880f128-stk/nsh/defconfig @@ -189,7 +189,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4531 +CONFIG_BOARD_LOOPSPERMSEC=2662 # CONFIG_ARCH_CALIBRATION is not set # diff --git a/nuttx/configs/pcblogic-pic32mx/README.txt b/nuttx/configs/pcblogic-pic32mx/README.txt index 323d51d3e..5d329b672 100644 --- a/nuttx/configs/pcblogic-pic32mx/README.txt +++ b/nuttx/configs/pcblogic-pic32mx/README.txt @@ -220,7 +220,7 @@ Toolchains well. This toolchain can be downloded from the Pinguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Pinguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 See also configs/mirtoo/README.txt. There is an experimental (untested) configuration for the Mirtoo platform in that directory. @@ -246,7 +246,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/configs/pic32-starterkit/README.txt b/nuttx/configs/pic32-starterkit/README.txt index 0f0a545e4..e02a593ba 100644 --- a/nuttx/configs/pic32-starterkit/README.txt +++ b/nuttx/configs/pic32-starterkit/README.txt @@ -436,7 +436,7 @@ Toolchains well. This toolchain can be downloded from the Pinguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Pinguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 See also configs/mirtoo/README.txt. There is an experimental (untested) configuration for the Mirtoo platform in that directory. @@ -462,7 +462,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/configs/pic32mx7mmb/README.txt b/nuttx/configs/pic32mx7mmb/README.txt index c9024461f..d48a852c1 100644 --- a/nuttx/configs/pic32mx7mmb/README.txt +++ b/nuttx/configs/pic32mx7mmb/README.txt @@ -204,7 +204,7 @@ Toolchains well. This toolchain can be downloded from the Pinguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Pinguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 See also configs/mirtoo/README.txt. There is an experimental (untested) configuration for the Mirtoo platform in that directory. @@ -230,7 +230,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/configs/sam4e-ek/src/sam4e-ek.h b/nuttx/configs/sam4e-ek/src/sam4e-ek.h index 25184e589..ff642b9fc 100644 --- a/nuttx/configs/sam4e-ek/src/sam4e-ek.h +++ b/nuttx/configs/sam4e-ek/src/sam4e-ek.h @@ -304,9 +304,9 @@ */ #define GPIO_RS232_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \ - GPIO_OUTPUT_CLEAR | GPIO_PORT_PIOA | GPIO_PIN21) + GPIO_OUTPUT_CLEAR | GPIO_PORT_PIOA | GPIO_PIN23) #define GPIO_RS485_ENABLE (GPIO_OUTPUT | GPIO_CFG_DEFAULT | \ - GPIO_OUTPUT_SET | GPIO_PORT_PIOA | GPIO_PIN21) + GPIO_OUTPUT_SET | GPIO_PORT_PIOA | GPIO_PIN23) /* HSMCI SD Card Detect * diff --git a/nuttx/configs/sure-pic32mx/README.txt b/nuttx/configs/sure-pic32mx/README.txt index 0c0b99427..52ba8f54e 100644 --- a/nuttx/configs/sure-pic32mx/README.txt +++ b/nuttx/configs/sure-pic32mx/README.txt @@ -291,7 +291,7 @@ Toolchains well. This toolchain can be downloded from the Penguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Penguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 See also configs/mirtoo/README.txt. There is an experimental (untested) configuration for the Mirtoo platform in that directory. @@ -317,7 +317,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/configs/ubw32/README.txt b/nuttx/configs/ubw32/README.txt index e3e2a511c..e1a0a3785 100644 --- a/nuttx/configs/ubw32/README.txt +++ b/nuttx/configs/ubw32/README.txt @@ -229,7 +229,7 @@ Toolchains well. This toolchain can be downloded from the Pinguino website: http://wiki.pinguino.cc/index.php/Main_Page#Download . There is some general information about using the Pinguino mips-elf toolchain in this thread: - http://tech.groups.yahoo.com/group/nuttx/message/1821 + https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1821 See also configs/mirtoo/README.txt. There is an experimental (untested) configuration for the Mirtoo platform in that directory. @@ -256,7 +256,7 @@ Toolchains Even then, there are more warnings from the linker and some undefined symbols for non-NuttX code that resides in the unused Microchip libraries. See this - email thread at http://tech.groups.yahoo.com/group/nuttx/message/1458 for more + email thread at https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/1458 for more information. You will have to solve at least this undefined symbol problem if you want to used the XC32 toolchain. diff --git a/nuttx/drivers/serial/serial.c b/nuttx/drivers/serial/serial.c index 6a48b4fda..3cc779874 100644 --- a/nuttx/drivers/serial/serial.c +++ b/nuttx/drivers/serial/serial.c @@ -1376,7 +1376,7 @@ void uart_connected(FAR uart_dev_t *dev, bool connected) (void)sem_post(&dev->recvsem); } - /* Notify all poll/select waiters that and hangup occurred */ + /* Notify all poll/select waiters that a hangup occurred */ uart_pollnotify(dev, (POLLERR|POLLHUP)); } diff --git a/nuttx/fs/Kconfig b/nuttx/fs/Kconfig index 0dba7f80a..8de3f51b0 100644 --- a/nuttx/fs/Kconfig +++ b/nuttx/fs/Kconfig @@ -73,6 +73,12 @@ config SYSLOG console (like printf()). This setting is required to enable customization of the basic system loggin capability. +config SYSLOG_TIMESTAMP + bool "Prepend timestamp to syslog message" + default n + ---help--- + Prepend timestamp to syslog message. + if SYSLOG config SYSLOG_CHAR diff --git a/nuttx/fs/vfs/fs_open.c b/nuttx/fs/vfs/fs_open.c index fd6562ac3..1fb0cb538 100644 --- a/nuttx/fs/vfs/fs_open.c +++ b/nuttx/fs/vfs/fs_open.c @@ -107,7 +107,7 @@ int open(const char *path, int oflags, ...) /* If the file is opened for creation, then get the mode bits */ - if (oflags & (O_WRONLY|O_CREAT) != 0) + if ((oflags & (O_WRONLY|O_CREAT)) != 0) { va_list ap; va_start(ap, oflags); diff --git a/nuttx/include/nuttx/mm/mm.h b/nuttx/include/nuttx/mm/mm.h index 707d7f7da..97c260f50 100644 --- a/nuttx/include/nuttx/mm/mm.h +++ b/nuttx/include/nuttx/mm/mm.h @@ -112,24 +112,44 @@ /* These definitions define the characteristics of allocator * * MM_MIN_SHIFT is used to define MM_MIN_CHUNK. - * MM_MIN_CHUNK - is the smallest physical chunk that can - * be allocated. It must be at least a large as - * sizeof(struct mm_freenode_s). Larger values may - * improve performance slightly, but will waste memory - * due to quantization losses. + * MM_MIN_CHUNK - is the smallest physical chunk that can be allocated. It + * must be at least a large as sizeof(struct mm_freenode_s). Larger values + * may improve performance slightly, but will waste memory due to + * quantization losses. * * MM_MAX_SHIFT is used to define MM_MAX_CHUNK - * MM_MAX_CHUNK is the largest, contiguous chunk of memory - * that can be allocated. It can range from 16-bytes to - * 4Gb. Larger values of MM_MAX_SHIFT can cause larger - * data structure sizes and, perhaps, minor performance - * losses. + * MM_MAX_CHUNK is the largest, contiguous chunk of memory that can be + * allocated. It can range from 16-bytes to 4Gb. Larger values of + * MM_MAX_SHIFT can cause larger data structure sizes and, perhaps, + * minor performance losses. + */ + +#if defined(CONFIG_MM_SMALL) && UINTPTR_MAX <= UINT32_MAX +/* Two byte offsets; Pointers may be 2 or 4 bytes; + * sizeof(struct mm_freenode_s) is 8 or 12 bytes. + * REVISIT: We could do better on machines with 16-bit addressing. */ -#ifdef CONFIG_MM_SMALL # define MM_MIN_SHIFT 4 /* 16 bytes */ # define MM_MAX_SHIFT 15 /* 32 Kb */ + +#elif defined(CONFIG_HAVE_LONG_LONG) +/* Four byte offsets; Pointers may be 4 or 8 bytes + * sizeof(struct mm_freenode_s) is 16 or 24 bytes. + */ + +# if UINTPTR_MAX <= UINT32_MAX +# define MM_MIN_SHIFT 4 /* 16 bytes */ +# elif UINTPTR_MAX <= UINT64_MAX +# define MM_MIN_SHIFT 5 /* 32 bytes */ +# endif +# define MM_MAX_SHIFT 22 /* 4 Mb */ + #else +/* Four byte offsets; Pointers must be 4 bytes. + * sizeof(struct mm_freenode_s) is 16 bytes. + */ + # define MM_MIN_SHIFT 4 /* 16 bytes */ # define MM_MAX_SHIFT 22 /* 4 Mb */ #endif diff --git a/nuttx/libc/syslog/lib_syslog.c b/nuttx/libc/syslog/lib_syslog.c index 63441fd9e..70e8e13de 100644 --- a/nuttx/libc/syslog/lib_syslog.c +++ b/nuttx/libc/syslog/lib_syslog.c @@ -42,6 +42,7 @@ #include <stdio.h> #include <syslog.h> +#include <nuttx/clock.h> #include <nuttx/streams.h> #include "syslog/syslog.h" @@ -94,41 +95,85 @@ static inline int vsyslog_internal(FAR const char *fmt, va_list ap) { #if defined(CONFIG_SYSLOG) - struct lib_outstream_s stream; +#elif CONFIG_NFILE_DESCRIPTORS > 0 + struct lib_rawoutstream_s stream; +#elif defined(CONFIG_ARCH_LOWPUTC) + struct lib_outstream_s stream; +#endif +#if defined(CONFIG_SYSLOG_TIMESTAMP) + struct timespec ts; + int ret; + + /* Get the current time */ + + ret = clock_systimespec(&ts); +#endif + +#if defined(CONFIG_SYSLOG) /* Wrap the low-level output in a stream object and let lib_vsprintf * do the work. */ lib_syslogstream((FAR struct lib_outstream_s *)&stream); - return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap); -#elif CONFIG_NFILE_DESCRIPTORS > 0 +#if defined(CONFIG_SYSLOG_TIMESTAMP) + /* Pre-pend the message with the current time */ - struct lib_rawoutstream_s rawoutstream; + if (ret == OK) + { + (void)lib_sprintf((FAR struct lib_outstream_s *)&stream, + "[%6d.%06d]", + ts.tv_sec, ts.tv_nsec/1000); + } +#endif + return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap); + +#elif CONFIG_NFILE_DESCRIPTORS > 0 /* Wrap the stdout in a stream object and let lib_vsprintf * do the work. */ - lib_rawoutstream(&rawoutstream, 1); - return lib_vsprintf(&rawoutstream.public, fmt, ap); + lib_rawoutstream(&stream, 1); -#elif defined(CONFIG_ARCH_LOWPUTC) +#if defined(CONFIG_SYSLOG_TIMESTAMP) + /* Pre-pend the message with the current time */ - struct lib_outstream_s stream; + if (ret == OK) + { + (void)lib_sprintf((FAR struct lib_outstream_s *)&stream, + "[%6d.%06d]", + ts.tv_sec, ts.tv_nsec/1000); + } +#endif + + return lib_vsprintf(&stream.public, fmt, ap); +#elif defined(CONFIG_ARCH_LOWPUTC) /* Wrap the low-level output in a stream object and let lib_vsprintf * do the work. */ lib_lowoutstream((FAR struct lib_outstream_s *)&stream); + +#if defined(CONFIG_SYSLOG_TIMESTAMP) + /* Pre-pend the message with the current time */ + + if (ret == OK) + { + (void)lib_sprintf((FAR struct lib_outstream_s *)&stream, + "[%6d.%06d]", + ts.tv_sec, ts.tv_nsec/1000); + } +#endif + return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap); -#else +#else /* CONFIG_SYSLOG */ return 0; -#endif +#endif /* CONFIG_SYSLOG */ } /**************************************************************************** diff --git a/nuttx/libc/termios/lib_tcsetattr.c b/nuttx/libc/termios/lib_tcsetattr.c index ec38ec845..8d7b5ccb0 100644 --- a/nuttx/libc/termios/lib_tcsetattr.c +++ b/nuttx/libc/termios/lib_tcsetattr.c @@ -118,5 +118,6 @@ int tcsetattr(int fd, int options, FAR const struct termios *termiosp) { return ioctl(fd, TCSETS, (unsigned long)termiosp); } + return -ENOSYS; } |