From 088146b90eee5b614ea6386a64dae343a49a5172 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 11 Jun 2014 15:49:54 -0600 Subject: STM32: Handle setting of USART CR1_M when 8 bits of data plus parity --- nuttx/arch/arm/src/stm32/stm32_serial.c | 46 +++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index 336fb3a9c..e3b841403 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -1274,17 +1274,32 @@ static void up_set_format(struct uart_dev_s *dev) /* Configure parity mode */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_PCE|USART_CR1_PS); + regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); if (priv->parity == 1) /* Odd parity */ { - regval |= (USART_CR1_PCE|USART_CR1_PS); + regval |= (USART_CR1_PCE | USART_CR1_PS); } else if (priv->parity == 2) /* Even parity */ { regval |= USART_CR1_PCE; } + /* Configure word length (parity uses one of configured bits) + * + * Default: 1 start, 8 data (no parity), n stop, OR + * 1 start, 7 data + parity, n stop + */ + + if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0)) + { + /* Select: 1 start, 8 data + parity, n stop, OR + * 1 start, 9 data (no parity), n stop. + */ + + regval |= USART_CR1_M; + } + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ @@ -1378,9 +1393,9 @@ static int up_setup(struct uart_dev_s *dev) /* Configure CR2 */ /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = up_serialin(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL| - USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE); + regval = up_serialin(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); /* Configure STOP bits */ @@ -1392,17 +1407,10 @@ static int up_setup(struct uart_dev_s *dev) up_serialout(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ - /* Clear M, TE, REm and all interrupt enable bits */ + /* Clear TE, REm and all interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_M|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS); - - /* Configure word length */ - - if (priv->bits == 9) /* Default: 1 start, 8 data, n stop */ - { - regval |= USART_CR1_M; /* 1 start, 9 data, n stop */ - } + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); @@ -1410,7 +1418,7 @@ static int up_setup(struct uart_dev_s *dev) /* Clear CTSE, RTSE, and all interrupt enable bits */ regval = up_serialin(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); up_serialout(priv, STM32_USART_CR3_OFFSET, regval); @@ -1421,7 +1429,7 @@ static int up_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); /* Set up the cached interrupt enables value */ @@ -1513,7 +1521,7 @@ static void up_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ regval = up_serialin(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE|USART_CR1_TE|USART_CR1_RE); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); up_serialout(priv, STM32_USART_CR1_OFFSET, regval); } @@ -1992,7 +2000,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS #ifdef CONFIG_USART_ERRINTS - ie |= (USART_CR1_RXNEIE|USART_CR1_PEIE|USART_CR3_EIE); + ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); #else ie |= USART_CR1_RXNEIE; #endif @@ -2000,7 +2008,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) } else { - ie &= ~(USART_CR1_RXNEIE|USART_CR1_PEIE|USART_CR3_EIE); + ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE); } /* Then set the new interrupt state */ -- cgit v1.2.3