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authorGregory Nutt <gnutt@nuttx.org>2015-01-08 18:12:06 -0600
committerGregory Nutt <gnutt@nuttx.org>2015-01-08 18:12:06 -0600
commit11ee53875937c677dca56788756a6775979a36f2 (patch)
tree70920155a11e7c875e682abfb9ca08b710da290e
parent3b5b9cbbb3ef2a757f8a41d71b7344925cec65e2 (diff)
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STM32 SDIO: CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE should not be available unless CONFIG_MMCSD_SDIO=y
-rwxr-xr-xnuttx/drivers/mmcsd/Kconfig44
-rwxr-xr-xnuttx/include/nuttx/sdio.h15
2 files changed, 28 insertions, 31 deletions
diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig
index 33f70bb4b..3bce55afb 100755
--- a/nuttx/drivers/mmcsd/Kconfig
+++ b/nuttx/drivers/mmcsd/Kconfig
@@ -38,28 +38,6 @@ config MMCSD_HAVECARDDETECT
SDIO driver card detection is
100% accurate
-config ARCH_HAVE_SDIOWAIT_WRCOMPLETE
- bool
- default n
-
-config MMCSD_SDIOWAIT_WRCOMPLETE
- bool "Use SDIO_D Busy to detect Write Complete"
- default n
- depends on ARCH_HAVE_SDIOWAIT_WRCOMPLETE
- ---help---
- SDIO driver will use SDIO_D Busy signalling to detect Write Complete.
- This option when selected, will enable the MMCSD driver to use the
- underlying (stm32_sdio only) drivers implementation of the SD specs
- SDIO_D Busy signalling to detect Write Complete. This will avoid
- potentially very long (600Ms+) busy waiting in the MMCSD driver.
-
- To implement SDIO_D Busy signalling, the underlying driver must
- be capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
- interrupt pin. It must then, condition that pin to detect the rising edge
- on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
- return it back to regular SDIO mode, when either the ISR fires or pin is
- found to be high in the SDIO_EVENTWAIT call.
-
config MMCSD_SPI
bool "MMC/SD SPI transfer support"
default y
@@ -111,6 +89,28 @@ config SDIO_MUXBUS
Set this SDIO interface if the SDIO interface
or hardware resources are shared with other drivers.
+config ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+ bool
+ default n
+
+config MMCSD_SDIOWAIT_WRCOMPLETE
+ bool "Use D0 Busy to detect Write Complete"
+ default n
+ depends on ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+ ---help---
+ SDIO driver will use D0 Busy signalling to detect Write Complete.
+ This option when selected, will enable the MMCSD driver to use the
+ underlying SDIO drivers implementation of the SD specification's
+ D0 Busy signalling to detect Write Complete. This will avoid
+ potentially very long (600Ms+) busy waiting in the MMCSD driver.
+
+ To implement D0 Busy signalling, the underlying driver must
+ be capable of switching the D0 GPIO to be a rising edge sensitive
+ interrupt pin. It must then, condition that pin to detect the rising edge
+ on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
+ return it back to regular SDIO mode, when either the ISR fires or pin is
+ found to be high in the SDIO_EVENTWAIT call.
+
config SDIO_WIDTH_D1_ONLY
bool "SDIO 1-bit transfer"
default n
diff --git a/nuttx/include/nuttx/sdio.h b/nuttx/include/nuttx/sdio.h
index 258fe14c8..94c413308 100755
--- a/nuttx/include/nuttx/sdio.h
+++ b/nuttx/include/nuttx/sdio.h
@@ -63,15 +63,12 @@
#define SDIOWAIT_TIMEOUT (1 << 3) /* Bit 3: Timeout */
#define SDIOWAIT_ERROR (1 << 4) /* Bit 4: Some other error occurred */
-/* SDIOWAIT_WRCOMPLETE (optional) : SDIO driver will use SDIO_D Busy
- * signalling to detect Write Complete. This option when selected, will
- * enable the MMCSD driver to use the underlying (stm32_sdio only) drivers
- * implementation of the SD specs SDIO_D Busy signalling to detect Write
- * Complete. This will avoid potentially very long (600Ms+) busy waiting
- * in the MMCSD driver.
- *
- * To implement SDIO_D Busy signalling, the underlying driver must be
- * capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
+/* SDIOWAIT_WRCOMPLETE (optional) : Certain SDIO driver can use D0 busy
+ * signalling to detect Write Complete. Used of D0 busy signalling will
+ * avoid potentially very long (600Ms+) busy waiting in the MMCSD driver.
+ *
+ * To implement D0 Busy signalling, the underlying SDIO driver must be
+ * capable of switching the the D0 GPIO to be a rising edge sensitive
* interrupt pin. It must then, condition that pin to detect the rising
* edge on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
* return it back to regular SDIO mode, when either the ISR fires or pin