Control and Status

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3269 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 113 insertions, 27 deletions

diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_atd10b8cv3.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_atd10b8cv3.h
index f5d792907..23c99883d 100755
--- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_atd10b8cv3.h
+++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_atd10b8cv3.h
@@ -154,25 +154,111 @@
 /* Register Bit-Field Definitions ***************************************************/
 
 /* ATD control register 0 */
-#define ATD_CTL0_
+
+#define ATD_CTL0_WRAP_SHIFT             (0)       /* Bits 0-2: Wrap around channel select */
+#define ATD_CTL0_WRAP_MASK              (7)
+#  define ATD_CTL0_WRAP_AN(n)           (n)
+#  define ATD_CTL0_WRAP_AN1             (1)
+#  define ATD_CTL0_WRAP_AN2             (2)
+#  define ATD_CTL0_WRAP_AN3             (3)
+#  define ATD_CTL0_WRAP_AN4             (4)
+#  define ATD_CTL0_WRAP_AN5             (5)
+#  define ATD_CTL0_WRAP_AN6             (6)
+#  define ATD_CTL0_WRAP_AN7             (7)
 
 /* ATD control register 1 */
-#define ATD_CTL1_
+
+#define ATD_CTL1_ETRIGCH_SHIFT          (0)       /* Bits 0-2: External channel select */
+#define ATD_CTL1_ETRIGCH_MASK           (7)
+#  define ATD_CTL2_ETRIGCH_AN(n)        (n)
+#  define ATD_CTL2_ETRIGCH_AN0          (0)
+#  define ATD_CTL2_ETRIGCH_AN1          (1)
+#  define ATD_CTL2_ETRIGCH_AN2          (2)
+#  define ATD_CTL2_ETRIGCH_AN3          (3)
+#  define ATD_CTL2_ETRIGCH_AN4          (4)
+#  define ATD_CTL2_ETRIGCH_AN5          (5)
+#  define ATD_CTL2_ETRIGCH_AN6          (6)
+#  define ATD_CTL2_ETRIGCH_AN7          (7)
+#  define ATD_CTL2_ETRIGCH_ETRIG(n)     (n)
+#  define ATD_CTL2_ETRIGCH_ETRIG0       (0)
+#  define ATD_CTL2_ETRIGCH_ETRIG1       (1)
+#  define ATD_CTL2_ETRIGCH_ETRIG2       (2)
+#  define ATD_CTL2_ETRIGCH_ETRIG3       (3)
+#define ATD_CTL1_ETRIGSEL               (1 << 7)  /* Bit 7: External trigger source select */
 
 /* ATD control register 2 */
-#define ATD_CTL2_
+
+#define ATD_CTL2_ASCIF                  (1 << 0)  /* Bit 0: ATD Sequence Complete Interrup */
+#define ATD_CTL2_ASCIE                  (1 << 1)  /* Bit 1: ATD Sequence Complete Interrupt Enable */
+#define ATD_CTL2_ETRIG                  (1 << 1)  /* Bit 2: External Trigger Mode Enable */
+#define ATD_CTL2_ETRIG_SHIFT            (3)       /* Bits 3-4: External Trigger Mode */
+#define ATD_CTL2_ETRIG_MASK             (0 << ATD_CTL2_ETRIG_SHIFT)
+#  define ATD_CTL2_ETRIG_FALLING        (0 << ATD_CTL2_ETRIG_SHIFT)
+#  define ATD_CTL2_ETRIG_RISING         (1 << ATD_CTL2_ETRIG_SHIFT)
+#  define ATD_CTL2_ETRIG_LOW            (2 << ATD_CTL2_ETRIG_SHIFT)
+#  define ATD_CTL2_ETRIG_HIGH           (3 << ATD_CTL2_ETRIG_SHIFT)
+#define ATD_CTL2_AWAI                   (1 << 5)  /* Bit 5: ATD Power Down inWait Mode */
+#define ATD_CTL2_AFFC                   (1 << 6)  /* Bit 6: ATD Fast Flag Clear All */
+#define ATD_CTL2_ADPU                   (1 << 7)  /* Bit 7: ATD Power Up */
 
 /* ATD control register 3 */
-#define ATD_CTL3_
+
+#define ATD_CTL3_FRZ_SHIFT              (0)       /* Bits 0-1: Background Debug Freeze Enable */
+#define ATD_CTL3_FRZ_MASK               (3)
+#  define ATD_CTL3_FRZ_CONTINUE         (0)       /* Continue conversion */
+#  define ATD_CTL3_FRZ_FINISH           (2)       /* Finish current conversion, then freeze */
+#  define ATD_CTL3_FRZ_IMMEDIATE        (3)       /* Freeze Immediately */
+#define ATD_CTL3_FIFO                   (1 << 2)  /* Bit 2: Result Register FIFO Mode */
+#define ATD_CTL3_SC_SHIFT               (3)       /* Bits 3-6: Conversion Sequence Length */
+#define ATD_CTL3_SC_MASK                (15 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC(n)                ((n) << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC1                  (1 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC2                  (2 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC3                  (3 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC4                  (4 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC5                  (5 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC6                  (6 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC7                  (7 << ATD_CTL3_SC_SHIFT)
+#  define ATD_CTL3_SC8                  (8 << ATD_CTL3_SC_SHIFT)
 
 /* ATD control register 4 */
-#define ATD_CTL4_
+
+#define ATD_CTL4_PRS_SHIFT              (0)       /* Bits 0-4: ATD Clock Prescaler */
+#define ATD_CTL4_PRS_MASK               (31 << ATD_CTL4_PRS_SHIFT)
+#  define ATD_CTL4_PRS_DIV(n)           ((((n)-2) >> 1) << ATD_CTL4_PRS_SHIFT) /* Divide by n={2,4,6,...,64} */
+#define ATD_CTL4_SMP_SHIFT              (5)       /* Bits 5-6: Sample Time Select */
+#define ATD_CTL4_SMP_MASK               (3 << ATD_CTL4_SMP_SHIFT)
+#  define ATD_CTL4_SMP2                 (0 << ATD_CTL4_SMP_SHIFT) /* 2 A/D conversion clock periods */
+#  define ATD_CTL4_SMP4                 (1 << ATD_CTL4_SMP_SHIFT) /* 4 A/D conversion clock periods */
+#  define ATD_CTL4_SMP8                 (2 << ATD_CTL4_SMP_SHIFT) /* 8 A/D conversion clock periods */
+#  define ATD_CTL4_SMP16                (3 << ATD_CTL4_SMP_SHIFT) /* 16 A/D conversion clock periods */
+#define ATD_CTL4_SRES8                  (1 << 7)  /* Bit 7: A/D Resolution Select */
 
 /* ATD control register 5 */
-#define ATD_CTL5_
+
+#define ATD_CTL5_C_SHIFT                (0)      /* Bits 0-2: Analog Input Channel Select Code */
+#define ATD_CTL5_C_MASK                 (7 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN(n)              ((n) << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN0                (0 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN1                (1 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN2                (2 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN3                (3 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN4                (4 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN5                (5 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN6                (6 << ATD_CTL5_C_SHIFT)
+#  define ATD_CTL5_C_AN7                (7 << ATD_CTL5_C_SHIFT)
+#define ATD_CTL5_MULT                   (1 << 4)  /* Bit 4: Multi-Channel Sample Mode */
+#define ATD_CTL5_SCAN                   (1 << 5)  /* Bit 5: Continuous Conversion Sequence Mode */
+#define ATD_CTL5_DSGN                   (1 << 6)  /* Bit 6: Result Register Data Signed or Unsigned Representation */
+#define ATD_CTL5_DJM                    (1 << 7)  /* Bit 7: Result Register Data Justification */
 
 /* ATD status register 0 */
-#define ATD_STAT0_
+
+#define ATD_STAT0_CC_SHIFT              (0)       /* Bits 0-2: Conversion counter */
+#define ATD_STAT0_CC_MASK               (7)
+#define ATD_STAT0_FIFOR                 (1 << 4)  /* Bit 4: FIFO Over Run Flag */
+#define ATD_STAT0_ETORF                 (1 << 5)  /* Bit 5: External Trigger Overrun Flag */
+#define ATD_STAT0_SCF                   (1 << 7)  /* Bit 7: Sequence Complete Flag */
 
 /* ATD test register 0 -- 8 MS bits of data written in special mode */
 /* ATD test register 1 */
@@ -194,32 +280,32 @@
 
 /* ATD Input enable register */
 
-#define ATD_IEN(n)                     (1 << (n)) /* Bit n: ATD Digital Input Enable on channel n */
-#define ATD_IEN0                       (1 << 0)  /* Bit 0: ATD Digital Input Enable on channel 0 */
-#define ATD_IEN1                       (1 << 1)  /* Bit 1: ATD Digital Input Enable on channel 1 */
-#define ATD_IEN2                       (1 << 2)  /* Bit 2: ATD Digital Input Enable on channel 2 */
-#define ATD_IEN3                       (1 << 3)  /* Bit 3: ATD Digital Input Enable on channel 3 */
-#define ATD_IEN4                       (1 << 4)  /* Bit 4: ATD Digital Input Enable on channel 4 */
-#define ATD_IEN5                       (1 << 5)  /* Bit 5: ATD Digital Input Enable on channel 5 */
-#define ATD_IEN6                       (1 << 6)  /* Bit 6: ATD Digital Input Enable on channel 6 */
-#define ATD_IEN7                       (1 << 7)  /* Bit 7: ATD Digital Input Enable on channel 7 */
+#define ATD_IEN(n)                      (1 << (n)) /* Bit n: ATD Digital Input Enable on channel n */
+#define ATD_IEN0                        (1 << 0)  /* Bit 0: ATD Digital Input Enable on channel 0 */
+#define ATD_IEN1                        (1 << 1)  /* Bit 1: ATD Digital Input Enable on channel 1 */
+#define ATD_IEN2                        (1 << 2)  /* Bit 2: ATD Digital Input Enable on channel 2 */
+#define ATD_IEN3                        (1 << 3)  /* Bit 3: ATD Digital Input Enable on channel 3 */
+#define ATD_IEN4                        (1 << 4)  /* Bit 4: ATD Digital Input Enable on channel 4 */
+#define ATD_IEN5                        (1 << 5)  /* Bit 5: ATD Digital Input Enable on channel 5 */
+#define ATD_IEN6                        (1 << 6)  /* Bit 6: ATD Digital Input Enable on channel 6 */
+#define ATD_IEN7                        (1 << 7)  /* Bit 7: ATD Digital Input Enable on channel 7 */
 
 /* Port data register */
 
-#define ATD_PORTAD(n)                     (1 << (n)) /* Bit n: A/D Channel n (ANn) Digital Input */
-#define ATD_PORTAD0                       (1 << 0)  /* Bit 0: A/D Channel 0 (AN0) Digital Input */
-#define ATD_PORTAD1                       (1 << 1)  /* Bit 1: A/D Channel 1 (AN1) Digital Input */
-#define ATD_PORTAD2                       (1 << 2)  /* Bit 2: A/D Channel 2 (AN2) Digital Input */
-#define ATD_PORTAD3                       (1 << 3)  /* Bit 3: A/D Channel 3 (AN3) Digital Input */
-#define ATD_PORTAD4                       (1 << 4)  /* Bit 4: A/D Channel 4 (AN4) Digital Input */
-#define ATD_PORTAD5                       (1 << 5)  /* Bit 5: A/D Channel 5 (AN5) Digital Input */
-#define ATD_PORTAD6                       (1 << 6)  /* Bit 6: A/D Channel 6 (AN6) Digital Input */
-#define ATD_PORTAD7                       (1 << 7)  /* Bit 7: A/D Channel 7 (AN7) Digital Input */
+#define ATD_PORTAD(n)                   (1 << (n)) /* Bit n: A/D Channel n (ANn) Digital Input */
+#define ATD_PORTAD0                     (1 << 0)  /* Bit 0: A/D Channel 0 (AN0) Digital Input */
+#define ATD_PORTAD1                     (1 << 1)  /* Bit 1: A/D Channel 1 (AN1) Digital Input */
+#define ATD_PORTAD2                     (1 << 2)  /* Bit 2: A/D Channel 2 (AN2) Digital Input */
+#define ATD_PORTAD3                     (1 << 3)  /* Bit 3: A/D Channel 3 (AN3) Digital Input */
+#define ATD_PORTAD4                     (1 << 4)  /* Bit 4: A/D Channel 4 (AN4) Digital Input */
+#define ATD_PORTAD5                     (1 << 5)  /* Bit 5: A/D Channel 5 (AN5) Digital Input */
+#define ATD_PORTAD6                     (1 << 6)  /* Bit 6: A/D Channel 6 (AN6) Digital Input */
+#define ATD_PORTAD7                     (1 << 7)  /* Bit 7: A/D Channel 7 (AN7) Digital Input */
 
 /* ATD conversion result register 0-7 (high/l;ow) */
 
-#define ATD_DLL_MASK 0xc0  /* Bits 6-7: LS bits of left justified data */
-#define ATD_DRH_MASK 0x03  /* Bits 0-1: MS bits of right justified data */
+#define ATD_DLL_MASK                    0xc0      /* Bits 6-7: LS bits of left justified data */
+#define ATD_DRH_MASK                    0x03      /* Bits 0-1: MS bits of right justified data */
 
 /************************************************************************************
  * Public Types