From 36052c9b70ae9fb8ad6e4f6c91094c26f749cf68 Mon Sep 17 00:00:00 2001
From: patacongo
Date: Mon, 13 Apr 2009 23:24:37 +0000
Subject: Add interrupt decode logic for i.MX
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1701 42af7a65-404d-4744-a932-0658087f49c3
---
nuttx/Documentation/NuttX.html | 23 +++++-
nuttx/arch/arm/src/dm320/dm320_decodeirq.c | 10 ++-
nuttx/arch/arm/src/imx/Make.defs | 2 +-
nuttx/arch/arm/src/imx/imx_aitc.h | 6 ++
nuttx/arch/arm/src/imx/imx_decodeirq.c | 123 +++++++++++++++++++++++++++++
5 files changed, 158 insertions(+), 6 deletions(-)
create mode 100644 nuttx/arch/arm/src/imx/imx_decodeirq.c
diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html
index 17f79e23c..bb5c3eac7 100644
--- a/nuttx/Documentation/NuttX.html
+++ b/nuttx/Documentation/NuttX.html
@@ -790,6 +790,27 @@
+
+ ![](favicon.ico) |
+
+ ARM920T.
+ |
+
+
+
|
+
+
+ Freescale MC9328MX1 or i.MX1.
+ This port uses the Freescale MX1ADS development board with a GNU arm-elf toolchain*
+ under either Linux or Cygwin.
+
+
+ STATUS:
+ This port is in progress. Coding is complete on the basic port (timer, serial console).
+ Verified support for the i.MX1 will be announced in a future release of NuttX.
+
+ |
+
![](favicon.ico) |
@@ -1433,7 +1454,7 @@ buildroot-0.1.4 2009-xx-xx <spudmonkey@racsa.co.cr>
|
- - ARM, ARM7 ARM7TDMI, ARM9, ARM926EJS are trademarks of Advanced RISC Machines, Limited.
+ - ARM, ARM7 ARM7TDMI, ARM9, ARM920T, ARM926EJS are trademarks of Advanced RISC Machines, Limited.
- Cygwin is a trademark of Red Hat, Incorporated.
- Linux is a registered trademark of Linus Torvalds.
- LPC2148 is a trademark of NXP Semiconductors.
diff --git a/nuttx/arch/arm/src/dm320/dm320_decodeirq.c b/nuttx/arch/arm/src/dm320/dm320_decodeirq.c
index fad9f0faf..1b5ac401f 100644
--- a/nuttx/arch/arm/src/dm320/dm320_decodeirq.c
+++ b/nuttx/arch/arm/src/dm320/dm320_decodeirq.c
@@ -1,7 +1,8 @@
/********************************************************************************
- * dm320/dm320_decodeirq.c
+ * arch/arm/src/dm320/dm320_decodeirq.c
+ * arch/arm/src/chip/dm320_decodeirq.c
*
- * Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -14,7 +15,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ * 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
@@ -43,6 +44,7 @@
#include
#include
#include
+
#include "up_arch.h"
#include "os_internal.h"
#include "up_internal.h"
@@ -86,7 +88,7 @@ void up_decodeirq(uint32* regs)
int irq = (irqentry >> 2) - 1;
- /* Verify that the resulting IRQ number is valie */
+ /* Verify that the resulting IRQ number is valid */
if ((unsigned)irq < NR_IRQS)
{
diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs
index 60250c473..b7019260c 100644
--- a/nuttx/arch/arm/src/imx/Make.defs
+++ b/nuttx/arch/arm/src/imx/Make.defs
@@ -47,7 +47,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
CHIP_ASRCS = imx_lowputc.S
CHIP_CSRCS = imx_boot.c imx_gpio.c imx_allocateheap.c imx_irq.c \
- imx_serial.c imx_timerisr.c # imx_decodeirq.c imx_framebuffer.c
+ imx_serial.c imx_timerisr.c imx_decodeirq.c #imx_framebuffer.c
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += imx_usbdev.c
diff --git a/nuttx/arch/arm/src/imx/imx_aitc.h b/nuttx/arch/arm/src/imx/imx_aitc.h
index b73e70fa9..fdd8a5cf3 100644
--- a/nuttx/arch/arm/src/imx/imx_aitc.h
+++ b/nuttx/arch/arm/src/imx/imx_aitc.h
@@ -106,6 +106,12 @@
/* AITC Register Bit Definitions ****************************************************/
+
+#define AITC_NIVECSR_NIPRILVL_SHIFT 0 /* Bits 15–0: Priority of highest priority interrupt */
+#define AITC_NIVECSR_NIPRILVL_MASK (0x0000ffff << AITC_NIVECSR_NIPRILVL_SHIFT);
+#define AITC_NIVECSR_NIVECTOR_SHIFT 16 /* Bits 31–16: Vector index of highest priority interrupt */
+#define AITC_NIVECSR_NIVECTOR_MASK (0x0000ffff << AITC_NIVECSR_NIVECTOR_SHIFT);
+
/************************************************************************************
* Inline Functions
************************************************************************************/
diff --git a/nuttx/arch/arm/src/imx/imx_decodeirq.c b/nuttx/arch/arm/src/imx/imx_decodeirq.c
new file mode 100644
index 000000000..f6a38b934
--- /dev/null
+++ b/nuttx/arch/arm/src/imx/imx_decodeirq.c
@@ -0,0 +1,123 @@
+/********************************************************************************
+ * arch/arm/src/imx/imx_decodeirq.c
+ * arch/arm/src/chip/imx_decodeirq.c
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************/
+
+/********************************************************************************
+ * Included Files
+ ********************************************************************************/
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/********************************************************************************
+ * Definitions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Functions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Funtions
+ ********************************************************************************/
+
+void up_decodeirq(uint32* regs)
+{
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ lib_lowprintf("Unexpected IRQ\n");
+ current_regs = regs;
+ PANIC(OSERR_ERREXCEPTION);
+#else
+ uint32 regval;
+ int irq;
+
+ /* Decode the interrupt. First, fetch the NIVECSR register. */
+
+ regval = getreg32(IMX_AITC_NIVECSR);
+
+ /* The MS 16 bits of the NIVECSR register contains vector index for the
+ * highest pending normal interrupt.
+ */
+
+ irq = regval >> AITC_NIVECSR_NIVECTOR_SHIFT;
+
+ /* If irq < 64, then this is the IRQ. If there is no pending interrupt,
+ * then irq will be >= 64 (it will be 0xffff for illegal source).
+ */
+
+ if (irq < NR_IRQS)
+ {
+ /* Mask and acknowledge the interrupt */
+
+ up_maskack_irq(irq);
+
+ /* Current regs non-zero indicates that we are processing an interrupt;
+ * current_regs is also used to manage interrupt level context switches.
+ */
+
+ current_regs = regs;
+
+ /* Deliver the IRQ */
+
+ irq_dispatch(irq, regs);
+
+ /* Indicate that we are no long in an interrupt handler */
+
+ current_regs = NULL;
+
+ /* Unmask the last interrupt (global interrupts are still
+ * disabled.
+ */
+
+ up_enable_irq(irq);
+ }
+#endif
+}
--
cgit v1.2.3