From 88c4630e4897e7ffac04ccc6788e06dc62b42069 Mon Sep 17 00:00:00 2001 From: Jakob Odersky Date: Tue, 13 Jan 2015 17:12:19 +0100 Subject: port memorymap and vectors to kinetis k20 --- nuttx/arch/arm/src/kinetis/kinetis_memorymap.h | 118 +++++++++++++++- nuttx/arch/arm/src/kinetis/kinetis_vectors.S | 181 ++++++++++++++++++++++++- 2 files changed, 296 insertions(+), 3 deletions(-) diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h index ef1d22265..df290daaa 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h @@ -48,6 +48,122 @@ * Pre-processor Definitions ************************************************************************************/ +/* Memory Map ***********************************************************************/ +/* K20 Family + * + * The memory map for the following parts is defined in Freescale document + * K20P64M72SF1RM + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ +# if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ +# endif + /* 0x18000000 * –0x1bffffff Reserved */ +# define KINETIS_SRAML_BASE 0x1C000000 /* –0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * –0x21ffffff Reserved */ +# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * –0x3fffffff Reserved */ +# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * –0x41ffffff Reserved */ +# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * –0xdfffffff Reserved */ +# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ + /* 0xe0100000 * –0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ +# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */ +# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */ +# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +# define KINETIS_CRC_BASE 0x40032000 /* CRC */ +# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */ +# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */ +# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */ +# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ + +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + /* Memory Map ***********************************************************************/ /* K40 Family * @@ -55,7 +171,7 @@ * K40P144M100SF2RM */ -#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) diff --git a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S index ed0ba52a1..671733d8e 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S +++ b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S @@ -154,13 +154,116 @@ _vectors: .word kinetis_systick /* Vector 15: System tick */ /* External Interrupts **************************************************************************/ +/* K20 Family *********************************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale document + * K20P64M72SF1RM + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ + .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ + .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ + .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ + .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ + .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ + .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ + .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ + .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ + .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ + .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ + .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ + .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ + .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ + .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ + .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ + .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ + .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ + .word kinetis_flashcc /* Vector 34: Flash memory command complete */ + .word kinetis_flashrc /* Vector 35: Flash memory read collision */ + .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ + .word kinetis_wdog /* Vector 38: Watchdog */ + .word kinetis_reserved /* Vector 39: Reserved */ + .word kinetis_i2c0 /* Vector 40: I2C0 */ + .word kinetis_i2c1 /* Vector 41: I2C1 */ + .word kinetis_spi0 /* Vector 42: SPI0 all sources */ + .word kinetis_spi1 /* Vector 43: SPI1 all sources */ + .word kinetis_reserved /* Vector 44: Reserved */ + .word kinetis_can0mb /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ + .word kinetis_can0bo /* Vector 46: CAN0 Bus Off */ + .word kinetis_can0err /* Vector 47: CAN0 Error */ + .word kinetis_can0tw /* Vector 48: CAN0 Transmit Warning */ + .word kinetis_can0rw /* Vector 49: CAN0 Receive Warning */ + .word kinetis_can0wu /* Vector 50: CAN0 Wake UP */ + .word kinetis_reserved /* Vector 51: Reserved */ + .word kinetis_reserved /* Vector 52: Reserved */ + .word kinetis_reserved /* Vector 53: Reserved */ + .word kinetis_reserved /* Vector 54: Reserved */ + .word kinetis_reserved /* Vector 55: Reserved */ + .word kinetis_reserved /* Vector 56: Reserved */ + .word kinetis_reserved /* Vector 57: Reserved */ + .word kinetis_reserved /* Vector 58: Reserved */ + .word kinetis_reserved /* Vector 59: Reserved */ + .word kinetis_reserved /* Vector 60: Reserved */ + .word kinetis_uart0s /* Vector 61: UART0 status */ + .word kinetis_uart0e /* Vector 62: UART0 error */ + .word kinetis_uart1s /* Vector 63: UART1 status */ + .word kinetis_uart1e /* Vector 64: UART1 error */ + .word kinetis_uart2s /* Vector 65: UART2 status */ + .word kinetis_uart2e /* Vector 66: UART2 error */ + .word kinetis_reserved /* Vector 67: Reserved */ + .word kinetis_reserved /* Vector 68: Reserved */ + .word kinetis_reserved /* Vector 69: Reserved */ + .word kinetis_reserved /* Vector 70: Reserved */ + .word kinetis_reserved /* Vector 71: Reserved */ + .word kinetis_reserved /* Vector 72: Reserved */ + .word kinetis_adc0 /* Vector 73: ADC0 */ + .word kinetis_adc1 /* Vector 74: ADC1 */ + .word kinetis_cmp0 /* Vector 75: CMP0 */ + .word kinetis_cmp1 /* Vector 76: CMP1 */ + .word kinetis_cmp2 /* Vector 77: CMP2 */ + .word kinetis_ftm0 /* Vector 78: FTM0 all sources */ + .word kinetis_ftm1 /* Vector 79: FTM1 all sources */ + .word kinetis_ftm2 /* Vector 80: FTM2 all sources */ + .word kinetis_cmt /* Vector 81: CMT */ + .word kinetis_rtc /* Vector 82: RTC alarm interrupt */ + .word kinetis_reserved /* Vector 83: Reserved */ + .word kinetis_pitch0 /* Vector 84: PIT channel 0 */ + .word kinetis_pitch1 /* Vector 85: PIT channel 1 */ + .word kinetis_pitch2 /* Vector 86: PIT channel 2 */ + .word kinetis_pitch3 /* Vector 87: PIT channel 3 */ + .word kinetis_pdb /* Vector 88: PDB */ + .word kinetis_usbotg /* Vector 88: USB OTG */ + .word kinetis_usbcd /* Vector 90: USB charger detect */ + .word kinetis_reserved /* Vector 91: Reserved */ + .word kinetis_reserved /* Vector 92: Reserved */ + .word kinetis_reserved /* Vector 93: Reserved */ + .word kinetis_reserved /* Vector 94: Reserved */ + .word kinetis_reserved /* Vector 95: Reserved */ + .word kinetis_reserved /* Vector 96: Reserved */ + .word kinetis_dac0 /* Vector 97: DAC0 */ + .word kinetis_reserved /* Vector 98: Reserved */ + .word kinetis_tsi /* Vector 99: TSI all sources */ + .word kinetis_mcg /* Vector 100: MCG */ + .word kinetis_lpt /* Vector 101: Low power timer */ + .word kinetis_slcd /* Vector 102: Segment LCD all sources */ + .word kinetis_porta /* Vector 103: Pin detect port A */ + .word kinetis_portb /* Vector 104: Pin detect port B */ + .word kinetis_portc /* Vector 105: Pin detect port C */ + .word kinetis_portd /* Vector 106: Pin detect port D */ + .word kinetis_porte /* Vector 107: Pin detect port E */ + .word kinetis_reserved /* Vector 108: Reserved */ + .word kinetis_reserved /* Vector 109: Reserved */ + .word kinetis_swi /* Vector 110: Software interrupt */ + /* K40 Family *********************************************************************************** * * The interrupt vectors for the following parts is defined in Freescale document * K40P144M100SF2RM */ -#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) @@ -401,13 +504,87 @@ handlers: HANDLER kinetis_systick, KINETIS_IRQ_SYSTICK /* Vector 15: System tick */ /* External Interrupts **************************************************************************/ +/* K40 Family *********************************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale document + * K20P64M72SF1RM + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + + HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ + HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ + HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ + HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ + HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ + HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ + HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ + HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ + HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ + HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ + HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ + HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ + HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ + HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ + HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ + HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ + HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ + HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ + HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ + HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ + HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ + HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ + HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ + HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ + HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ + HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ + HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 46: CAN0 Bus Off */ + HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 47: CAN0 Error */ + HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 48: CAN0 Transmit Warning */ + HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 49: CAN0 Receive Warning */ + HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 50: CAN0 Wake UP */ + HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 61: UART0 status */ + HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 62: UART0 error */ + HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 63: UART1 status */ + HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 64: UART1 error */ + HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 65: UART2 status */ + HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 66: UART2 error */ + HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 73: ADC0 */ + HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 74: ADC1 */ + HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 75: CMP0 */ + HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 76: CMP1 */ + HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 77: CMP2 */ + HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 78: FTM0 all sources */ + HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 79: FTM1 all sources */ + HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 80: FTM2 all sources */ + HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 81: CMT */ + HANDLER kinetis_rtc, KINETIS_IRQ_RTC /* Vector 82: RTC alarm interrupt */ + HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 84: PIT channel 0 */ + HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 85: PIT channel 1 */ + HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 86: PIT channel 2 */ + HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 87: PIT channel 3 */ + HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 88: PDB */ + HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 88: USB OTG */ + HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 90: USB charger detect */ + HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 97: DAC0 */ + HANDLER kinetis_tsi, KINETIS_IRQ_TSI /* Vector 97: TSI all sources */ + HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 100: MCG */ + HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 101: Low power timer */ + HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 103: Pin detect port A */ + HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 104: Pin detect port B */ + HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 105: Pin detect port C */ + HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ + HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ + HANDLER kinetis_swi, KINETIS_IRQ_SWI /* Vector 110: Software interrupt */ + /* K40 Family *********************************************************************************** * * The interrupt vectors for the following parts is defined in Freescale document * K40P144M100SF2RM */ -#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) -- cgit v1.2.3