From 89daf669c7d24c8d4ff951aec75a0b153351735a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Feb 2014 08:46:16 -0600 Subject: SAM4E: Add vector definition header files --- nuttx/ChangeLog | 2 + nuttx/arch/arm/include/sam34/sam4e_irq.h | 10 +- nuttx/arch/arm/src/sam34/Make.defs | 2 +- nuttx/arch/arm/src/sam34/chip.h | 4 +- nuttx/arch/arm/src/sam34/chip/sam4e_vectors.h | 103 +++++ nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h | 4 +- nuttx/arch/arm/src/sam34/sam3u_clockconfig.c | 340 ---------------- nuttx/arch/arm/src/sam34/sam3u_gpio.c | 534 -------------------------- nuttx/arch/arm/src/sam34/sam_clockconfig.c | 340 ++++++++++++++++ nuttx/arch/arm/src/sam34/sam_gpio.c | 534 ++++++++++++++++++++++++++ nuttx/arch/arm/src/sam34/sam_vectors.S | 6 +- nuttx/configs/samd20-xplained/README.txt | 10 +- 12 files changed, 1005 insertions(+), 884 deletions(-) create mode 100644 nuttx/arch/arm/src/sam34/chip/sam4e_vectors.h delete mode 100644 nuttx/arch/arm/src/sam34/sam3u_clockconfig.c delete mode 100644 nuttx/arch/arm/src/sam34/sam3u_gpio.c create mode 100644 nuttx/arch/arm/src/sam34/sam_clockconfig.c create mode 100644 nuttx/arch/arm/src/sam34/sam_gpio.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 45c4e2a56..8d9bfa74e 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -6641,4 +6641,6 @@ fs/Kconfig and in apps/. It turns out this this is not very useful if you are modifying existing configurations because then the defaults do not apply (2014-2-20). + * arch/arm/src/sam34/chip/sam4e_vectors.h: Add vector definitions + for the SAM4E (2014-2-21). diff --git a/nuttx/arch/arm/include/sam34/sam4e_irq.h b/nuttx/arch/arm/include/sam34/sam4e_irq.h index d0800d45d..6fa9464e1 100755 --- a/nuttx/arch/arm/include/sam34/sam4e_irq.h +++ b/nuttx/arch/arm/include/sam34/sam4e_irq.h @@ -1,7 +1,7 @@ /**************************************************************************************** * arch/arm/include/sam34/sam4e_irq.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -90,9 +90,11 @@ #define SAM_PID_CAN0 (37) /* CAN0 */ #define SAM_PID_CAN1 (38) /* CAN1 */ #define SAM_PID_AES (39) /* AES */ + /* 40-43: Reserved #define SAM_PID_EMAC (44) /* EMAC */ #define SAM_PID_UART1 (45) /* UART */ -#define NR_PIDS (46) /* Number of peripheral identifiers */ + /* 46: Reserved */ +#define NR_PIDS (47) /* Number of peripheral identifiers */ /* External interrupts (priority levels >= 256*/ @@ -106,6 +108,7 @@ #define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */ #define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ #define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ + #define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */ #define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */ #define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */ @@ -136,7 +139,8 @@ #define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+SAM_PID_CAN1) /* CAN1 */ #define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* AES */ #define SAM_IRQ_EMAC (SAM_IRQ_EXTINT+SAM_PID_EMAC) /* EMAC */ -#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* UART */ +#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* UART1 */ + #define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ #define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs index 725070805..db235cad5 100644 --- a/nuttx/arch/arm/src/sam34/Make.defs +++ b/nuttx/arch/arm/src/sam34/Make.defs @@ -85,7 +85,7 @@ CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y) CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c else -CHIP_CSRCS += sam3u_clockconfig.c sam3u_gpio.c +CHIP_CSRCS += sam_clockconfig.c sam_gpio.c endif ifeq ($(CONFIG_NUTTX_KERNEL),y) diff --git a/nuttx/arch/arm/src/sam34/chip.h b/nuttx/arch/arm/src/sam34/chip.h index 7b22d6d55..829ded7aa 100644 --- a/nuttx/arch/arm/src/sam34/chip.h +++ b/nuttx/arch/arm/src/sam34/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sam34/chip.h * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -58,6 +58,8 @@ # include "chip/sam3u_vectors.h" # elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # include "chip/sam3x_vectors.h" +# elif defined(CONFIG_ARCH_CHIP_SAM4E) +# include "chip/sam4e_vectors.h" # elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" # elif defined(CONFIG_ARCH_CHIP_SAM4S) diff --git a/nuttx/arch/arm/src/sam34/chip/sam4e_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam4e_vectors.h new file mode 100644 index 000000000..b881233f9 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4e_vectors.h @@ -0,0 +1,103 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4e_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that supplies each SAM4E + * vector in terms of a (lower-case) ISR label and an (upper-case) IRQ number as defined in + * arch/arm/include/sam/sam3u_irq.h. sam_vectors.S will defined the VECTOR in different ways in + * order to generate the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 35 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 47 + +#else + VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */ + VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */ + VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */ + VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */ + VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ + VECTOR(sam_eefc, SAM_IRQ_EEFC) /* Vector 16+6: Enhanced Embedded Flash Controller */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+7: Universal Asynchronous Receiver Transmitter 0 */ + UNUSED(SAM_IRQ_RESERVED_8) /* Vector 16+8: Static Memory Controller (no vector) */ + VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+9: Parallel I/O Controller A */ + VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+10: Parallel I/O Controller B */ + VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+11: Parallel I/O Controller C */ + VECTOR(sam_piod, SAM_IRQ_PIOD) /* Vector 16+12: Parallel I/O Controller C */ + VECTOR(sam_pioe, SAM_IRQ_PIOE) /* Vector 16+13: Parallel I/O Controller C */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */ + VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+16: High Speed Multimedia Card Interface */ + VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+17: Two-Wire Interface 0 */ + VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+18: Two-Wire Interface 1 */ + VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+19: Serial Peripheral Interface */ + VECTOR(sam_dmac, SAM_IRQ_DMAC) /* Vector 16+20: DMA controller */ + VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+21: Timer Counter 0 */ + VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+22: Timer Counter 1 */ + VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+23: Timer Counter 2 */ + VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+24: Timer Counter 3 */ + VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+25: Timer Counter 4 */ + VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+26: Timer Counter 5 */ + VECTOR(sam_tc5, SAM_IRQ_TC6) /* Vector 16+27: Timer Counter 6 */ + VECTOR(sam_tc5, SAM_IRQ_TC7) /* Vector 16+28: Timer Counter 7 */ + VECTOR(sam_tc5, SAM_IRQ_TC8) /* Vector 16+29: Timer Counter 8 */ + VECTOR(sam_afec0, SAM_IRQ_AFEC0) /* Vector 16+30: Analog Front End 0 */ + VECTOR(sam_afec1, SAM_IRQ_AFEC1) /* Vector 16+31: Analog Front End 1 */ + VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+32: Digital To Analog Converter */ + VECTOR(sam_acc, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */ + VECTOR(sam_arm, SAM_IRQ_ARM) /* Vector 16+34: FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */ + VECTOR(sam_udp, SAM_IRQ_UDP) /* Vector 16+35: USB Device Port */ + VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+36: Pulse Width Modulation */ + VECTOR(sam_can0, SAM_IRQ_CAN0) /* Vector 16+37: CAN0 */ + VECTOR(sam_can1, SAM_IRQ_CAN1) /* Vector 16+38: CAN1 */ + VECTOR(sam_aes, SAM_IRQ_AES) /* Vector 16+39: AES */ + UNUSED(SAM_IRQ_RESERVED_40) /* Vector 16+40: Reserved */ + UNUSED(SAM_IRQ_RESERVED_41) /* Vector 16+41: Reserved */ + UNUSED(SAM_IRQ_RESERVED_42) /* Vector 16+42: Reserved */ + UNUSED(SAM_IRQ_RESERVED_43) /* Vector 16+43: Reserved */ + VECTOR(sam_emac, SAM_IRQ_EMAC) /* Vector 16+44: EMAC */ + VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+45: UART1 */ + UNUSED(SAM_IRQ_RESERVED_46) /* Vector 16+46: Reserved */ +#endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h index 5146cd3cc..420dbfcb6 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_vectors.h @@ -1,5 +1,5 @@ /************************************************************************************************ - * arch/arm/src/sam34/chip/sam42_vectors.h + * arch/arm/src/sam34/chip/sam4s_vectors.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -37,7 +37,7 @@ * Pre-processor Definitions ************************************************************************************************/ /* This file is included by sam_vectors.S. It provides the macro VECTOR that - * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * supplies ach SAM4S vector in terms of a (lower-case) ISR label and an * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. * sam_vectors.S will defined the VECTOR in different ways in order to generate * the interrupt vectors and handlers in their final form. diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c deleted file mode 100644 index 0f7285504..000000000 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * arch/arm/src/chip/sam3u_clockconfig.c - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "sam_clockconfig.h" -#include "chip/sam3u_pmc.h" -#include "chip/sam3u_eefc.h" -#include "chip/sam3u_wdt.h" -#include "chip/sam3u_supc.h" -#include "chip/sam3u_matrix.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* PMC register settings based on the board configuration values defined - * in board.h - */ - -#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ - PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) - -#if defined(CONFIG_ARCH_CHIP_SAM3U) -# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ - BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \ - BOARD_CKGR_PLLAR_DIV) -#elif defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3X) -# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ - BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) -#elif defined(CONFIG_ARCH_CHIP_SAM4S) -# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ - BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) -#endif - -#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) -#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) - -#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_efcsetup - * - * Description: - * Configure 2 waitstates for embedded flash access - * - ****************************************************************************/ - -static inline void sam_efcsetup(void) -{ - putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); - putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); -} - -/**************************************************************************** - * Name: sam_wdtsetup - * - * Description: - * Disable the watchdog timer - * - ****************************************************************************/ - -static inline void sam_wdtsetup(void) -{ - putreg32(WDT_MR_WDDIS, SAM_WDT_MR); -} - -/**************************************************************************** - * Name: sam_supcsetup - * - * Description: - * Select the external slow clock - * - ****************************************************************************/ - -static inline void sam_supcsetup(void) -{ - /* Check if the 32-kHz is already selected */ - - if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0) - { - uint32_t delay; - putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR); - for (delay = 0; - (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; - delay++); - } -} - -/**************************************************************************** - * Name: sam_pmcwait - * - * Description: - * Wait for the specide PMC status bit to become "1" - * - ****************************************************************************/ - -static void sam_pmcwait(uint32_t bit) -{ - volatile uint32_t delay; - - for (delay = 0; - (getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX; - delay++); -} - -/**************************************************************************** - * Name: sam_pmcsetup - * - * Description: - * Initialize clocking - * - ****************************************************************************/ - -static inline void sam_pmcsetup(void) -{ - uint32_t regval; - - /* Enable main oscillator (if it has not already been selected) */ - - if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) - { - /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to - * enable the main oscillator, the MOSCXTS bit in the Power Management - * Controller Status Register (PMC_SR) is cleared and the counter starts - * counting down on the slow clock divided by 8 from the MOSCXTCNT - * value. ... When the counter reaches 0, the MOSCXTS bit is set, - * indicating that the main clock is valid." - */ - - putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); - sam_pmcwait(PMC_INT_MOSCXTS); - } - - /* "Switch to the main oscillator. The selection is made by writing the - * MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of - * the Main Clock source is glitch free, so there is no need to run out - * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS - * bit of the power Management Controller Status Register (PMC_SR) allows - * knowing when the switch sequence is done." - * - * MOSCSELS: Main Oscillator Selection Status - * 0 = Selection is done - * 1 = Selection is in progress - */ - - putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); - sam_pmcwait(PMC_INT_MOSCSELS); - - /* "Select the master clock. "The Master Clock selection is made by writing - * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). - * The prescaler supports the division by a power of 2 of the selected clock - * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs - * the prescaler. Each time PMC_MCKR is written to define a new Master Clock, - * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is - * established. - */ - - regval = getreg32(SAM_PMC_MCKR); - regval &= ~PMC_MCKR_CSS_MASK; - regval |= PMC_MCKR_CSS_MAIN; - putreg32(regval, SAM_PMC_MCKR); - sam_pmcwait(PMC_INT_MCKRDY); - - /* Setup PLLA and wait for LOCKA */ - - putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); - sam_pmcwait(PMC_INT_LOCKA); - - /* Setup UTMI for USB and wait for LOCKU */ - -#ifdef CONFIG_USBDEV - regval = getreg32(SAM_PMC_CKGR_UCKR); - regval |= BOARD_CKGR_UCKR; - putreg32(regval, SAM_PMC_CKGR_UCKR); - sam_pmcwait(PMC_INT_LOCKU); -#endif - - /* Switch to the fast clock and wait for MCKRDY */ - - putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR); - sam_pmcwait(PMC_INT_MCKRDY); - - putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR); - sam_pmcwait(PMC_INT_MCKRDY); -} - -/**************************************************************************** - * Name: sam_enabledefaultmaster and sam_disabledefaultmaster - * - * Description: - * Enable/disable default master access - * - ****************************************************************************/ - -static inline void sam_enabledefaultmaster(void) -{ - uint32_t regval; - - /* Set default master: SRAM0 -> Cortex-M3 System */ - - regval = getreg32(SAM_MATRIX_SCFG0); - regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); - putreg32(regval, SAM_MATRIX_SCFG0); - - /* Set default master: SRAM1 -> Cortex-M3 System */ - - regval = getreg32(SAM_MATRIX_SCFG1); - regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); - putreg32(regval, SAM_MATRIX_SCFG1); - - /* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */ - - regval = getreg32(SAM_MATRIX_SCFG3); - regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED); - putreg32(regval, SAM_MATRIX_SCFG3); -} - -#if 0 /* Not used */ -static inline void sam_disabledefaultmaster(void) -{ - uint32_t regval; - - /* Clear default master: SRAM0 -> Cortex-M3 System */ - - regval = getreg32(SAM_MATRIX_SCFG0); - regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; - putreg32(regval, SAM_MATRIX_SCFG0); - - /* Clear default master: SRAM1 -> Cortex-M3 System */ - - regval = getreg32(SAM_MATRIX_SCFG1); - regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; - putreg32(regval, SAM_MATRIX_SCFG1); - - /* Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data */ - - regval = getreg32(SAM_MATRIX_SCFG3); - regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; - putreg32(regval, SAM_MATRIX_SCFG3); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/************************************************************************************ - * Name: sam_clockconfig - * - * Description: - * Called to initialize the SAM3/4. This does whatever setup is needed to put the - * SoC in a usable state. This includes the initialization of clocking using the - * settings in board.h. (After power-on reset, the SAM3/4 is initially running on - * a 4MHz internal RC clock). This function also performs other low-level chip - * initialization of the chip including EFC, master clock, IRQ & watchdog - * configuration. - * - ************************************************************************************/ - -void sam_clockconfig(void) -{ - /* Configure embedded flash access */ - - sam_efcsetup(); - - /* Configure the watchdog timer */ - - sam_wdtsetup(); - - /* Setup the supply controller to use the external slow clock */ - - sam_supcsetup(); - - /* Initialize clocking */ - - sam_pmcsetup(); - - /* Optimize CPU setting for speed */ - - sam_enabledefaultmaster(); -} - diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c deleted file mode 100644 index abaec84da..000000000 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ /dev/null @@ -1,534 +0,0 @@ -/**************************************************************************** - * arch/arm/src/sam34/sam3u_gpio.c - * General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S - * - * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "sam_gpio.h" - -#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ - defined(CONFIG_ARCH_CHIP_SAM3A) -# include "chip/sam3u_pio.h" -#elif defined(CONFIG_ARCH_CHIP_SAM4S) -# include "chip/sam4s_pio.h" -#else -# error Unrecognized SAM architecture -#endif - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO -static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ -/**************************************************************************** - * Name: sam_gpiobase - * - * Description: - * Return the base address of the GPIO register set - * - ****************************************************************************/ - -static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset) -{ - int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - return SAM_PION_BASE(port); -} - -/**************************************************************************** - * Name: sam_gpiopin - * - * Description: - * Returun the base address of the GPIO register set - * - ****************************************************************************/ - -static inline int sam_gpiopin(gpio_pinset_t cfgset) -{ - return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); -} - -/**************************************************************************** - * Name: sam_configinput - * - * Description: - * Configure a GPIO input pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -static inline int sam_configinput(uintptr_t base, uint32_t pin, - gpio_pinset_t cfgset) -{ -#ifdef GPIO_HAVE_SCHMITT - uint32_t regval; -#endif - - /* Disable interrupts on the pin */ - - putreg32(pin, base + SAM_PIO_IDR_OFFSET); - - /* Enable/disable the pull-up as requested */ - - if ((cfgset & GPIO_CFG_PULLUP) != 0) - { - putreg32(pin, base + SAM_PIO_PUER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PUDR_OFFSET); - } - -#ifdef GPIO_HAVE_PULLDOWN - /* Enable/disable the pull-down as requested */ - - if ((cfgset & GPIO_CFG_PULLDOWN) != 0) - { - putreg32(pin, base + SAM_PIO_PPDER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); - } -#endif - - /* Check if filtering should be enabled */ - - if ((cfgset & GPIO_CFG_DEGLITCH) != 0) - { - putreg32(pin, base + SAM_PIO_IFER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_IFDR_OFFSET); - } - -#ifdef GPIO_HAVE_SCHMITT - /* Enable/disable the Schmitt trigger */ - - regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET); - if ((cfgset & GPIO_CFG_PULLDOWN) != 0) - { - regval |= pin; - } - else - { - regval &= ~pin; - } - putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET); -#endif - - /* Configure the pin as an input and enable the GPIO function */ - - putreg32(pin, base + SAM_PIO_ODR_OFFSET); - putreg32(pin, base + SAM_PIO_PER_OFFSET); - - /* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and - * IFDGSR registers. This would probably best be done with - * another, new API... perhaps sam_configfilter() - */ - - return OK; -} - -/**************************************************************************** - * Name: sam_configoutput - * - * Description: - * Configure a GPIO output pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -static inline int sam_configoutput(uintptr_t base, uint32_t pin, - gpio_pinset_t cfgset) -{ - /* Disable interrupts on the pin */ - - putreg32(pin, base + SAM_PIO_IDR_OFFSET); - - /* Enable/disable the pull-up as requested */ - - if ((cfgset & GPIO_CFG_PULLUP) != 0) - { - putreg32(pin, base + SAM_PIO_PUER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PUDR_OFFSET); - } - -#ifdef GPIO_HAVE_PULLDOWN - /* Enable/disable the pull-down as requested */ - - if ((cfgset & GPIO_CFG_PULLDOWN) != 0) - { - putreg32(pin, base + SAM_PIO_PPDER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); - } -#endif - - /* Enable the open drain driver if requrested */ - - if ((cfgset & GPIO_CFG_OPENDRAIN) != 0) - { - putreg32(pin, base + SAM_PIO_MDER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_MDDR_OFFSET); - } - - /* Set default value */ - - if ((cfgset & GPIO_OUTPUT_SET) != 0) - { - putreg32(pin, base + SAM_PIO_SODR_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_CODR_OFFSET); - } - - /* Configure the pin as an output and enable the GPIO function */ - - putreg32(pin, base + SAM_PIO_OER_OFFSET); - putreg32(pin, base + SAM_PIO_PER_OFFSET); - return OK; -} - -/**************************************************************************** - * Name: sam_configperiph - * - * Description: - * Configure a GPIO pin driven by a peripheral A or B signal based on - * bit-encoded description of the pin. - * - ****************************************************************************/ - -static inline int sam_configperiph(uintptr_t base, uint32_t pin, - gpio_pinset_t cfgset) -{ - uint32_t regval; - - /* Disable interrupts on the pin */ - - putreg32(pin, base + SAM_PIO_IDR_OFFSET); - - /* Enable/disable the pull-up as requested */ - - if ((cfgset & GPIO_CFG_PULLUP) != 0) - { - putreg32(pin, base + SAM_PIO_PUER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PUDR_OFFSET); - } - -#ifdef GPIO_HAVE_PULLDOWN - /* Enable/disable the pull-down as requested */ - - if ((cfgset & GPIO_CFG_PULLDOWN) != 0) - { - putreg32(pin, base + SAM_PIO_PPDER_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); - } -#endif - -#ifdef GPIO_HAVE_PERIPHCD - /* Configure pin, depending upon the peripheral A, B, C or D - * - * PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0 - * PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0 - * PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1 - * PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1 - */ - - regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET); - if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || - (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC) - { - regval &= ~pin; - } - else - { - regval |= pin; - } - putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET); - - regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET); - if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || - (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB) - { - regval &= ~pin; - } - else - { - regval |= pin; - } - putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET); - -#else - /* Configure pin, depending upon the peripheral A or B: - * - * PERIPHA: ABSR[n] = 0 - * PERIPHB: ABSR[n] = 1 - */ - - regval = getreg32(base + SAM_PIO_ABSR_OFFSET); - if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA) - { - regval &= ~pin; - } - else - { - regval |= pin; - } - putreg32(regval, base + SAM_PIO_ABSR_OFFSET); -#endif - - /* Disable PIO functionality */ - - putreg32(pin, base + SAM_PIO_PDR_OFFSET); - return OK; -} - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -int sam_configgpio(gpio_pinset_t cfgset) -{ - uintptr_t base = sam_gpiobase(cfgset); - uint32_t pin = sam_gpiopin(cfgset); - irqstate_t flags; - int ret; - - /* Disable interrupts to prohibit re-entrance. */ - - flags = irqsave(); - - /* Enable writing to GPIO registers */ - - putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); - - /* Handle the pin configuration according to pin type */ - - switch (cfgset & GPIO_MODE_MASK) - { - case GPIO_INPUT: - ret = sam_configinput(base, pin, cfgset); - break; - - case GPIO_OUTPUT: - ret = sam_configoutput(base, pin, cfgset); - break; - - case GPIO_PERIPHA: - case GPIO_PERIPHB: -#ifdef GPIO_HAVE_PERIPHCD - case GPIO_PERIPHC: - case GPIO_PERIPHD: -#endif - ret = sam_configperiph(base, pin, cfgset); - break; - - default: - ret = -EINVAL; - break; - } - - /* Disable writing to GPIO registers */ - - putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); - irqrestore(flags); - - return ret; -} - -/**************************************************************************** - * Name: sam_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void sam_gpiowrite(gpio_pinset_t pinset, bool value) -{ - uintptr_t base = sam_gpiobase(pinset); - uint32_t pin = sam_gpiopin(pinset); - - if (value) - { - putreg32(pin, base + SAM_PIO_SODR_OFFSET); - } - else - { - putreg32(pin, base + SAM_PIO_CODR_OFFSET); - } -} - -/**************************************************************************** - * Name: sam_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool sam_gpioread(gpio_pinset_t pinset) -{ - uintptr_t base = sam_gpiobase(pinset); - uint32_t pin = sam_gpiopin(pinset); - uint32_t regval; - - if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT) - { - regval = getreg32(base + SAM_PIO_ODSR_OFFSET); - } - else - { - regval = getreg32(base + SAM_PIO_PDSR_OFFSET); - } - - return (regval & pin) != 0; -} - -/************************************************************************************ - * Function: sam_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO -int sam_dumpgpio(uint32_t pinset, const char *msg) -{ - irqstate_t flags; - uintptr_t base; - unsigned int pin; - unsigned int port; - - /* Get the base address associated with the PIO port */ - - pin = sam_gpiopin(pinset); - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - base = SAM_PION_BASE(port); - - /* The following requires exclusive access to the GPIO registers */ - - flags = irqsave(); - lldbg("PIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); - lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), - getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET)); - lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", - getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), - getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); -#if defined(CONFIG_ARCH_CHIP_ATSAM3U) - lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n", - getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET), - getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET)); -#elif defined(CONFIG_ARCH_CHIP_ATSAM4S) - lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", - getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), - getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR)); -#endif - lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", - getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), - getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); - lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", - getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), - getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET)); - lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", - getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), - getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); -#if defined(CONFIG_ARCH_CHIP_ATSAM4S) - lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", - getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), - getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); - lldbg("SCHMITT: %08x\n", - getreg32(base + SAM_PIO_SCHMITT_OFFSET)); -#endif - irqrestore(flags); - return OK; -} -#endif - diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.c b/nuttx/arch/arm/src/sam34/sam_clockconfig.c new file mode 100644 index 000000000..ebe7dc0c3 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * arch/arm/src/chip/sam_clockconfig.c + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "sam_clockconfig.h" +#include "chip/sam3u_pmc.h" +#include "chip/sam3u_eefc.h" +#include "chip/sam3u_wdt.h" +#include "chip/sam3u_supc.h" +#include "chip/sam3u_matrix.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PMC register settings based on the board configuration values defined + * in board.h + */ + +#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ + PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \ + BOARD_CKGR_PLLAR_DIV) +#elif defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3X) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) +#endif + +#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) +#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) + +#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_efcsetup + * + * Description: + * Configure 2 waitstates for embedded flash access + * + ****************************************************************************/ + +static inline void sam_efcsetup(void) +{ + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR); + putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR); +} + +/**************************************************************************** + * Name: sam_wdtsetup + * + * Description: + * Disable the watchdog timer + * + ****************************************************************************/ + +static inline void sam_wdtsetup(void) +{ + putreg32(WDT_MR_WDDIS, SAM_WDT_MR); +} + +/**************************************************************************** + * Name: sam_supcsetup + * + * Description: + * Select the external slow clock + * + ****************************************************************************/ + +static inline void sam_supcsetup(void) +{ + /* Check if the 32-kHz is already selected */ + + if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0) + { + uint32_t delay; + putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR); + for (delay = 0; + (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; + delay++); + } +} + +/**************************************************************************** + * Name: sam_pmcwait + * + * Description: + * Wait for the specide PMC status bit to become "1" + * + ****************************************************************************/ + +static void sam_pmcwait(uint32_t bit) +{ + volatile uint32_t delay; + + for (delay = 0; + (getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX; + delay++); +} + +/**************************************************************************** + * Name: sam_pmcsetup + * + * Description: + * Initialize clocking + * + ****************************************************************************/ + +static inline void sam_pmcsetup(void) +{ + uint32_t regval; + + /* Enable main oscillator (if it has not already been selected) */ + + if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) + { + /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to + * enable the main oscillator, the MOSCXTS bit in the Power Management + * Controller Status Register (PMC_SR) is cleared and the counter starts + * counting down on the slow clock divided by 8 from the MOSCXTCNT + * value. ... When the counter reaches 0, the MOSCXTS bit is set, + * indicating that the main clock is valid." + */ + + putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); + sam_pmcwait(PMC_INT_MOSCXTS); + } + + /* "Switch to the main oscillator. The selection is made by writing the + * MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of + * the Main Clock source is glitch free, so there is no need to run out + * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS + * bit of the power Management Controller Status Register (PMC_SR) allows + * knowing when the switch sequence is done." + * + * MOSCSELS: Main Oscillator Selection Status + * 0 = Selection is done + * 1 = Selection is in progress + */ + + putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); + sam_pmcwait(PMC_INT_MOSCSELS); + + /* "Select the master clock. "The Master Clock selection is made by writing + * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). + * The prescaler supports the division by a power of 2 of the selected clock + * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs + * the prescaler. Each time PMC_MCKR is written to define a new Master Clock, + * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is + * established. + */ + + regval = getreg32(SAM_PMC_MCKR); + regval &= ~PMC_MCKR_CSS_MASK; + regval |= PMC_MCKR_CSS_MAIN; + putreg32(regval, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); + + /* Setup PLLA and wait for LOCKA */ + + putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); + sam_pmcwait(PMC_INT_LOCKA); + + /* Setup UTMI for USB and wait for LOCKU */ + +#ifdef CONFIG_USBDEV + regval = getreg32(SAM_PMC_CKGR_UCKR); + regval |= BOARD_CKGR_UCKR; + putreg32(regval, SAM_PMC_CKGR_UCKR); + sam_pmcwait(PMC_INT_LOCKU); +#endif + + /* Switch to the fast clock and wait for MCKRDY */ + + putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); + + putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); +} + +/**************************************************************************** + * Name: sam_enabledefaultmaster and sam_disabledefaultmaster + * + * Description: + * Enable/disable default master access + * + ****************************************************************************/ + +static inline void sam_enabledefaultmaster(void) +{ + uint32_t regval; + + /* Set default master: SRAM0 -> Cortex-M3 System */ + + regval = getreg32(SAM_MATRIX_SCFG0); + regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG0); + + /* Set default master: SRAM1 -> Cortex-M3 System */ + + regval = getreg32(SAM_MATRIX_SCFG1); + regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG1); + + /* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */ + + regval = getreg32(SAM_MATRIX_SCFG3); + regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG3); +} + +#if 0 /* Not used */ +static inline void sam_disabledefaultmaster(void) +{ + uint32_t regval; + + /* Clear default master: SRAM0 -> Cortex-M3 System */ + + regval = getreg32(SAM_MATRIX_SCFG0); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG0); + + /* Clear default master: SRAM1 -> Cortex-M3 System */ + + regval = getreg32(SAM_MATRIX_SCFG1); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG1); + + /* Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data */ + + regval = getreg32(SAM_MATRIX_SCFG3); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG3); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: sam_clockconfig + * + * Description: + * Called to initialize the SAM3/4. This does whatever setup is needed to put the + * SoC in a usable state. This includes the initialization of clocking using the + * settings in board.h. (After power-on reset, the SAM3/4 is initially running on + * a 4MHz internal RC clock). This function also performs other low-level chip + * initialization of the chip including EFC, master clock, IRQ & watchdog + * configuration. + * + ************************************************************************************/ + +void sam_clockconfig(void) +{ + /* Configure embedded flash access */ + + sam_efcsetup(); + + /* Configure the watchdog timer */ + + sam_wdtsetup(); + + /* Setup the supply controller to use the external slow clock */ + + sam_supcsetup(); + + /* Initialize clocking */ + + sam_pmcsetup(); + + /* Optimize CPU setting for speed */ + + sam_enabledefaultmaster(); +} + diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.c b/nuttx/arch/arm/src/sam34/sam_gpio.c new file mode 100644 index 000000000..6ad18298c --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam_gpio.c @@ -0,0 +1,534 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam_gpio.c + * General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "sam_gpio.h" + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ + defined(CONFIG_ARCH_CHIP_SAM3A) +# include "chip/sam3u_pio.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam4s_pio.h" +#else +# error Unrecognized SAM architecture +#endif + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/**************************************************************************** + * Name: sam_gpiobase + * + * Description: + * Return the base address of the GPIO register set + * + ****************************************************************************/ + +static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset) +{ + int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + return SAM_PION_BASE(port); +} + +/**************************************************************************** + * Name: sam_gpiopin + * + * Description: + * Returun the base address of the GPIO register set + * + ****************************************************************************/ + +static inline int sam_gpiopin(gpio_pinset_t cfgset) +{ + return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Name: sam_configinput + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int sam_configinput(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ +#ifdef GPIO_HAVE_SCHMITT + uint32_t regval; +#endif + + /* Disable interrupts on the pin */ + + putreg32(pin, base + SAM_PIO_IDR_OFFSET); + + /* Enable/disable the pull-up as requested */ + + if ((cfgset & GPIO_CFG_PULLUP) != 0) + { + putreg32(pin, base + SAM_PIO_PUER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PUDR_OFFSET); + } + +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + + /* Check if filtering should be enabled */ + + if ((cfgset & GPIO_CFG_DEGLITCH) != 0) + { + putreg32(pin, base + SAM_PIO_IFER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_IFDR_OFFSET); + } + +#ifdef GPIO_HAVE_SCHMITT + /* Enable/disable the Schmitt trigger */ + + regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET); + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + regval |= pin; + } + else + { + regval &= ~pin; + } + putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET); +#endif + + /* Configure the pin as an input and enable the GPIO function */ + + putreg32(pin, base + SAM_PIO_ODR_OFFSET); + putreg32(pin, base + SAM_PIO_PER_OFFSET); + + /* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and + * IFDGSR registers. This would probably best be done with + * another, new API... perhaps sam_configfilter() + */ + + return OK; +} + +/**************************************************************************** + * Name: sam_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int sam_configoutput(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + /* Disable interrupts on the pin */ + + putreg32(pin, base + SAM_PIO_IDR_OFFSET); + + /* Enable/disable the pull-up as requested */ + + if ((cfgset & GPIO_CFG_PULLUP) != 0) + { + putreg32(pin, base + SAM_PIO_PUER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PUDR_OFFSET); + } + +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + + /* Enable the open drain driver if requrested */ + + if ((cfgset & GPIO_CFG_OPENDRAIN) != 0) + { + putreg32(pin, base + SAM_PIO_MDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_MDDR_OFFSET); + } + + /* Set default value */ + + if ((cfgset & GPIO_OUTPUT_SET) != 0) + { + putreg32(pin, base + SAM_PIO_SODR_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_CODR_OFFSET); + } + + /* Configure the pin as an output and enable the GPIO function */ + + putreg32(pin, base + SAM_PIO_OER_OFFSET); + putreg32(pin, base + SAM_PIO_PER_OFFSET); + return OK; +} + +/**************************************************************************** + * Name: sam_configperiph + * + * Description: + * Configure a GPIO pin driven by a peripheral A or B signal based on + * bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int sam_configperiph(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + uint32_t regval; + + /* Disable interrupts on the pin */ + + putreg32(pin, base + SAM_PIO_IDR_OFFSET); + + /* Enable/disable the pull-up as requested */ + + if ((cfgset & GPIO_CFG_PULLUP) != 0) + { + putreg32(pin, base + SAM_PIO_PUER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PUDR_OFFSET); + } + +#ifdef GPIO_HAVE_PULLDOWN + /* Enable/disable the pull-down as requested */ + + if ((cfgset & GPIO_CFG_PULLDOWN) != 0) + { + putreg32(pin, base + SAM_PIO_PPDER_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_PPDDR_OFFSET); + } +#endif + +#ifdef GPIO_HAVE_PERIPHCD + /* Configure pin, depending upon the peripheral A, B, C or D + * + * PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0 + * PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0 + * PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1 + * PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1 + */ + + regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET); + + regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA || + (cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET); + +#else + /* Configure pin, depending upon the peripheral A or B: + * + * PERIPHA: ABSR[n] = 0 + * PERIPHB: ABSR[n] = 1 + */ + + regval = getreg32(base + SAM_PIO_ABSR_OFFSET); + if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA) + { + regval &= ~pin; + } + else + { + regval |= pin; + } + putreg32(regval, base + SAM_PIO_ABSR_OFFSET); +#endif + + /* Disable PIO functionality */ + + putreg32(pin, base + SAM_PIO_PDR_OFFSET); + return OK; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int sam_configgpio(gpio_pinset_t cfgset) +{ + uintptr_t base = sam_gpiobase(cfgset); + uint32_t pin = sam_gpiopin(cfgset); + irqstate_t flags; + int ret; + + /* Disable interrupts to prohibit re-entrance. */ + + flags = irqsave(); + + /* Enable writing to GPIO registers */ + + putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); + + /* Handle the pin configuration according to pin type */ + + switch (cfgset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + ret = sam_configinput(base, pin, cfgset); + break; + + case GPIO_OUTPUT: + ret = sam_configoutput(base, pin, cfgset); + break; + + case GPIO_PERIPHA: + case GPIO_PERIPHB: +#ifdef GPIO_HAVE_PERIPHCD + case GPIO_PERIPHC: + case GPIO_PERIPHD: +#endif + ret = sam_configperiph(base, pin, cfgset); + break; + + default: + ret = -EINVAL; + break; + } + + /* Disable writing to GPIO registers */ + + putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); + irqrestore(flags); + + return ret; +} + +/**************************************************************************** + * Name: sam_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void sam_gpiowrite(gpio_pinset_t pinset, bool value) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + + if (value) + { + putreg32(pin, base + SAM_PIO_SODR_OFFSET); + } + else + { + putreg32(pin, base + SAM_PIO_CODR_OFFSET); + } +} + +/**************************************************************************** + * Name: sam_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool sam_gpioread(gpio_pinset_t pinset) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + uint32_t regval; + + if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT) + { + regval = getreg32(base + SAM_PIO_ODSR_OFFSET); + } + else + { + regval = getreg32(base + SAM_PIO_PDSR_OFFSET); + } + + return (regval & pin) != 0; +} + +/************************************************************************************ + * Function: sam_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int sam_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uintptr_t base; + unsigned int pin; + unsigned int port; + + /* Get the base address associated with the PIO port */ + + pin = sam_gpiopin(pinset); + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + base = SAM_PION_BASE(port); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + lldbg("PIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n", + getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET)); + lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", + getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), + getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); +#if defined(CONFIG_ARCH_CHIP_SAM3U) + lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n", + getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET), + getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET)); +#elif defined(CONFIG_ARCH_CHIP_SAM4S) + lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), + getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR)); +#endif + lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", + getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), + getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); + lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", + getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), + getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET)); + lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", + getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), + getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); +#if defined(CONFIG_ARCH_CHIP_SAM4S) + lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", + getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + lldbg("SCHMITT: %08x\n", + getreg32(base + SAM_PIO_SCHMITT_OFFSET)); +#endif + irqrestore(flags); + return OK; +} +#endif + diff --git a/nuttx/arch/arm/src/sam34/sam_vectors.S b/nuttx/arch/arm/src/sam34/sam_vectors.S index 74d0dafb4..fa008b67b 100644 --- a/nuttx/arch/arm/src/sam34/sam_vectors.S +++ b/nuttx/arch/arm/src/sam34/sam_vectors.S @@ -1,7 +1,7 @@ /************************************************************************************************ * arch/arm/src/sam34/sam_vectors.S * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -166,6 +166,8 @@ _vectors: # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # include "chip/sam3x_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4E) +# include "chip/sam4e_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4S) @@ -205,6 +207,8 @@ handlers: # include "chip/sam3u_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # include "chip/sam3x_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4E) +# include "chip/sam4e_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_vectors.h" #elif defined(CONFIG_ARCH_CHIP_SAM4S) diff --git a/nuttx/configs/samd20-xplained/README.txt b/nuttx/configs/samd20-xplained/README.txt index 8467ff7f3..0bd59701c 100644 --- a/nuttx/configs/samd20-xplained/README.txt +++ b/nuttx/configs/samd20-xplained/README.txt @@ -883,8 +883,14 @@ Configuration sub-directories be clock related??? - The program seems to be running normally, just producing bad output. - 3. SPI current hangs so no much progress has been made tested the I/O1 - module. + 3. SPI current hangs so not much progress has been made testing the I/O1 + module. The hang occurs because the SPI is waiting for SYNCBUSY to + be cleared after enabling the SPI. This even does not happen and so + causes the hang. + + Another note: Enabling the SPI on SERCOM0 also seems to interfere + with the USART output on SERCOM4. Both symptoms imply some clock- + related issue. The configuration suggests CONFIG_MMCSD_HAVECARDDETECT=y, but as of this writing, there is no support for EIC pin interrupts. -- cgit v1.2.3