From 8ffb4dd5280b7309ba7be1392794405124ac16ae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 9 Jun 2014 10:07:00 -0600 Subject: SAMA5D4: More header file changes --- nuttx/arch/arm/src/sama5/chip/sam_spi.h | 22 ++++++++++++++++++++- nuttx/arch/arm/src/sama5/chip/sam_ssc.h | 10 +++++----- nuttx/arch/arm/src/sama5/chip/sam_uart.h | 34 ++++++++++++++++---------------- 3 files changed, 43 insertions(+), 23 deletions(-) diff --git a/nuttx/arch/arm/src/sama5/chip/sam_spi.h b/nuttx/arch/arm/src/sama5/chip/sam_spi.h index 48ccf3ab4..b9a7bcf17 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_spi.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_spi.h @@ -2,7 +2,7 @@ * arch/arm/src/sama5/chip/sam_spi.h * Serial Peripheral Interface (SPI) definitions for the SAMA5 * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -105,6 +105,23 @@ #define SAM_SPI1_WPCR (SAM_SPI1_VBASE+SAM_SPI_WPCR_OFFSET) #define SAM_SPI1_WPSR (SAM_SPI1_VBASE+SAM_SPI_WPSR_OFFSET) +#ifdef CONFIG_SAMA5_HAVE_SPI2 +# define SAM_SPI2_CR (SAM_SPI2_VBASE+SAM_SPI_CR_OFFSET) +# define SAM_SPI2_MR (SAM_SPI2_VBASE+SAM_SPI_MR_OFFSET) +# define SAM_SPI2_RDR (SAM_SPI2_VBASE+SAM_SPI_RDR_OFFSET) +# define SAM_SPI2_TDR (SAM_SPI2_VBASE+SAM_SPI_TDR_OFFSET) +# define SAM_SPI2_SR (SAM_SPI2_VBASE+SAM_SPI_SR_OFFSET) +# define SAM_SPI2_IER (SAM_SPI2_VBASE+SAM_SPI_IER_OFFSET) +# define SAM_SPI2_IDR (SAM_SPI2_VBASE+SAM_SPI_IDR_OFFSET) +# define SAM_SPI2_IMR (SAM_SPI2_VBASE+SAM_SPI_IMR_OFFSET) +# define SAM_SPI2_CSR0 (SAM_SPI2_VBASE+SAM_SPI_CSR0_OFFSET) +# define SAM_SPI2_CSR1 (SAM_SPI2_VBASE+SAM_SPI_CSR1_OFFSET) +# define SAM_SPI2_CSR2 (SAM_SPI2_VBASE+SAM_SPI_CSR2_OFFSET) +# define SAM_SPI2_CSR3 (SAM_SPI2_VBASE+SAM_SPI_CSR3_OFFSET) +# define SAM_SPI2_WPCR (SAM_SPI2_VBASE+SAM_SPI_WPCR_OFFSET) +# define SAM_SPI2_WPSR (SAM_SPI2_VBASE+SAM_SPI_WPSR_OFFSET) +#endif + /* SPI register bit definitions *********************************************************/ /* SPI Control Register */ @@ -187,10 +204,13 @@ # define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ #define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ #define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) +# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) #define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */ #define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT) +# define SPI_CSR_DLYBS(n) ((uint32_t)(n) << SPI_CSR_DLYBS_SHIFT) #define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */ #define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT) +# define SPI_CSR_DLYBCT(n) ((uint32_t)(n) << SPI_CSR_DLYBCT_SHIFT) /* SPI Write Protection Control Register */ diff --git a/nuttx/arch/arm/src/sama5/chip/sam_ssc.h b/nuttx/arch/arm/src/sama5/chip/sam_ssc.h index 69f423306..558805027 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_ssc.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_ssc.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/chip/sam_ssc.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -199,8 +199,8 @@ # define SSC_TCMR_CKS_MCK (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_TCMR_CKS_RK (1 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ # define SSC_TCMR_CKS_TK (2 << SSC_TCMR_CKS_SHIFT) /* TK pin */ -#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-3: Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKO_MASK (3 << SSC_TCMR_CKO_SHIFT) +#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) # define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None, TK pin is an input */ # define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock, TK pin is an output */ # define SSC_TCMR_CKO_TRANSFER (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock during transfers, TK pin is an output */ @@ -295,8 +295,8 @@ #define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define SSC_WPMR_WPKEY_MASK (0xffffff << SSC_WPMR_WPKEY_SHIFT) -# define SSC_WPMR_WPKEY (0x535343 << SSC_WPMR_WPKEY_SHIFT) /* "SSC" in ASCII */ +#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) +# define SSC_WPMR_WPKEY (0x00535343 << SSC_WPMR_WPKEY_SHIFT) /* "SSC" in ASCII */ /* Write Protect Status Register */ diff --git a/nuttx/arch/arm/src/sama5/chip/sam_uart.h b/nuttx/arch/arm/src/sama5/chip/sam_uart.h index 211c9ecb3..81327cfe7 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_uart.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_uart.h @@ -188,23 +188,23 @@ #define SAM_USART3_WPSR (SAM_USART3_VBASE+SAM_UART_WPSR_OFFSET) #ifdef CONFIG_SAMA5_HAVE_USART4 -# define SAM_USART4_CR (SAM_USART4_VBASE+SAM_UART_CR_OFFSET) -# define SAM_USART4_MR (SAM_USART4_VBASE+SAM_UART_MR_OFFSET) -# define SAM_USART4_IER (SAM_USART4_VBASE+SAM_UART_IER_OFFSET) -# define SAM_USART4_IDR (SAM_USART4_VBASE+SAM_UART_IDR_OFFSET) -# define SAM_USART4_IMR (SAM_USART4_VBASE+SAM_UART_IMR_OFFSET) -# define SAM_USART4_SR (SAM_USART4_VBASE+SAM_UART_SR_OFFSET) -# define SAM_USART4_RHR (SAM_USART4_VBASE+SAM_UART_RHR_OFFSET) -# define SAM_USART4_THR (SAM_USART4_VBASE+SAM_UART_THR_OFFSET) -# define SAM_USART4_BRGR (SAM_USART4_VBASE+SAM_UART_BRGR_OFFSET) -# define SAM_USART4_RTOR (SAM_USART4_VBASE+SAM_UART_RTOR_OFFSET) -# define SAM_USART4_TTGR (SAM_USART4_VBASE+SAM_UART_TTGR_OFFSET) -# define SAM_USART4_FIDI (SAM_USART4_VBASE+SAM_UART_FIDI_OFFSET) -# define SAM_USART4_NER (SAM_USART4_VBASE+SAM_UART_NER_OFFSET) -# define SAM_USART4_IFR (SAM_USART4_VBASE+SAM_UART_IFR_OFFSET) -# define SAM_USART4_MAN (SAM_USART4_VBASE+SAM_UART_MAN_OFFSET) -# define SAM_USART4_WPMR (SAM_USART4_VBASE+SAM_UART_WPMR_OFFSET) -# define SAM_USART4_WPSR (SAM_USART4_VBASE+SAM_UART_WPSR_OFFSET) +# define SAM_USART4_CR (SAM_USART4_VBASE+SAM_UART_CR_OFFSET) +# define SAM_USART4_MR (SAM_USART4_VBASE+SAM_UART_MR_OFFSET) +# define SAM_USART4_IER (SAM_USART4_VBASE+SAM_UART_IER_OFFSET) +# define SAM_USART4_IDR (SAM_USART4_VBASE+SAM_UART_IDR_OFFSET) +# define SAM_USART4_IMR (SAM_USART4_VBASE+SAM_UART_IMR_OFFSET) +# define SAM_USART4_SR (SAM_USART4_VBASE+SAM_UART_SR_OFFSET) +# define SAM_USART4_RHR (SAM_USART4_VBASE+SAM_UART_RHR_OFFSET) +# define SAM_USART4_THR (SAM_USART4_VBASE+SAM_UART_THR_OFFSET) +# define SAM_USART4_BRGR (SAM_USART4_VBASE+SAM_UART_BRGR_OFFSET) +# define SAM_USART4_RTOR (SAM_USART4_VBASE+SAM_UART_RTOR_OFFSET) +# define SAM_USART4_TTGR (SAM_USART4_VBASE+SAM_UART_TTGR_OFFSET) +# define SAM_USART4_FIDI (SAM_USART4_VBASE+SAM_UART_FIDI_OFFSET) +# define SAM_USART4_NER (SAM_USART4_VBASE+SAM_UART_NER_OFFSET) +# define SAM_USART4_IFR (SAM_USART4_VBASE+SAM_UART_IFR_OFFSET) +# define SAM_USART4_MAN (SAM_USART4_VBASE+SAM_UART_MAN_OFFSET) +# define SAM_USART4_WPMR (SAM_USART4_VBASE+SAM_UART_WPMR_OFFSET) +# define SAM_USART4_WPSR (SAM_USART4_VBASE+SAM_UART_WPSR_OFFSET) #endif /* UART register bit definitions ****************************************************************/ -- cgit v1.2.3