From d32f956730f3e4ffa9e244163f9646d9f6049305 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 13 Feb 2013 15:19:47 +0000 Subject: A few fixes for LPC1788 compilation (more needed) git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5649 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc17xx/chip.h | 36 +-- nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h | 4 +- nuttx/configs/open1788/ostest/defconfig | 18 +- nuttx/configs/open1788/src/lpc17_nsh.c | 329 +++++++++++++++++++++++ 4 files changed, 363 insertions(+), 24 deletions(-) create mode 100644 nuttx/configs/open1788/src/lpc17_nsh.c diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h index c22c6aa60..3880268c9 100644 --- a/nuttx/arch/arm/include/lpc17xx/chip.h +++ b/nuttx/arch/arm/include/lpc17xx/chip.h @@ -218,8 +218,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ @@ -234,8 +234,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ # undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ @@ -250,8 +250,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ @@ -266,8 +266,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ # undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ @@ -282,8 +282,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ @@ -298,8 +298,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ # undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ @@ -314,8 +314,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ @@ -330,8 +330,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ # undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ @@ -346,8 +346,8 @@ # undef LPC176x /* Not LPC175/6 family */ # define LPC178x 1 /* LPC177/8 family */ # define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */ +# define LPC17_CPUSRAM_SIZE (64*1024) # define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ # define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ # define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h index dc272528d..d930896ac 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h @@ -276,7 +276,7 @@ #define SYSCON_EMCDIV (1 << 0) /* Bit 0: EMC Clock rate relative to CPU */ /* 0: EMC uses same clock as CPU */ /* 1: EMC uses half the rate of CPU */ - /* Bits 1-31: Reserved + /* Bits 1-31: Reserved */ /* CPU Clock Configuration register */ #define SYSCON_CCLKCFG_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ @@ -387,7 +387,7 @@ #define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ #define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ #define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ -#define SYSCON_PCONP_PCSSP0 (1 << 20) /* Bit 20: SSP2 power/clock control */ +#define SYSCON_PCONP_PCSSP2 (1 << 20) /* Bit 20: SSP2 power/clock control */ #define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ #define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ #define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ diff --git a/nuttx/configs/open1788/ostest/defconfig b/nuttx/configs/open1788/ostest/defconfig index 357285314..1639cf033 100644 --- a/nuttx/configs/open1788/ostest/defconfig +++ b/nuttx/configs/open1788/ostest/defconfig @@ -77,6 +77,9 @@ CONFIG_ARCH_CHIP_LPC17XX=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lpc17xx" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=8079 @@ -123,6 +126,7 @@ CONFIG_ARCH_FAMILY_LPC178X=y CONFIG_LPC17_MAINOSC=y CONFIG_LPC17_PLL0=y CONFIG_LPC17_PLL1=y +# CONFIG_LPC17_EMC is not set # CONFIG_LPC17_ETHERNET is not set # CONFIG_LPC17_USBHOST is not set # CONFIG_LPC17_USBDEV is not set @@ -269,6 +273,7 @@ CONFIG_DEV_CONSOLE=y CONFIG_SDCLONE_DISABLE=y # CONFIG_SCHED_WORKQUEUE is not set # CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set CONFIG_USER_ENTRYPOINT="ostest_main" @@ -278,9 +283,7 @@ CONFIG_DISABLE_OS_API=y # CONFIG_DISABLE_PTHREAD is not set # CONFIG_DISABLE_SIGNALS is not set # CONFIG_DISABLE_MQUEUE is not set -CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_POLL=y # # Signal Numbers @@ -316,6 +319,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # # Device Drivers # +CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set # CONFIG_LOOP is not set @@ -379,11 +383,13 @@ CONFIG_UART0_2STOP=0 # # File system configuration # +CONFIG_DISABLE_MOUNTPOINT=y # CONFIG_FS_RAMMAP is not set # # System Logging # +# CONFIG_SYSLOG_ENABLE is not set # CONFIG_SYSLOG is not set # @@ -426,6 +432,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y # CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y @@ -457,7 +465,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CDCACM is not set # CONFIG_EXAMPLES_COMPOSITE is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -473,7 +480,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MOUNT is not set # CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_NETTEST is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set @@ -602,3 +608,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # Sysinfo # # CONFIG_SYSTEM_SYSINFO is not set + +# +# USB Monitor +# diff --git a/nuttx/configs/open1788/src/lpc17_nsh.c b/nuttx/configs/open1788/src/lpc17_nsh.c new file mode 100644 index 000000000..3e143df88 --- /dev/null +++ b/nuttx/configs/open1788/src/lpc17_nsh.c @@ -0,0 +1,329 @@ +/**************************************************************************** + * config/open1788/src/lpc17_nsh.c + * arch/arm/src/board/lpc17_nsh.c + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "lpc17_gpio.h" +#include "open1788.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_OPEN1788 +# define NSH_HAVEMMCSD 1 +# define NSH_HAVEUSBHOST 1 +# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1 +# error "The Open1788 MMC/SD is on SSP1" +# undef CONFIG_NSH_MMCSDSPIPORTNO +# define CONFIG_NSH_MMCSDSPIPORTNO 1 +# endif +# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0 +# error "The Open1788 MMC/SD is only one slot (0)" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +# ifndef CONFIG_LPC17_SSP1 +# warning "CONFIG_LPC17_SSP1 is not enabled" +# undef NSH_HAVEMMCSD +# endif +#else +# error "Unrecognized board" +# undef NSH_HAVEMMCSD +# undef NSH_HAVEUSBHOST +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/* USB Host */ + +#ifdef CONFIG_USBHOST +# ifndef CONFIG_LPC17_USBHOST +# error "CONFIG_LPC17_USBHOST is not selected" +# endif +#endif + +#ifdef CONFIG_LPC17_USBHOST +# ifndef CONFIG_USBHOST +# warning "CONFIG_USBHOST is not selected" +# endif +#endif + +#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST) +# undef NSH_HAVEUSBHOST +#endif + +#ifdef NSH_HAVEUSBHOST +# ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +# endif +# ifndef CONFIG_USBHOST_STACKSIZE +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_CPP_HAVE_VARARGS +# ifdef CONFIG_DEBUG +# define message(...) lowsyslog(__VA_ARGS__) +# else +# define message(...) printf(__VA_ARGS__) +# endif +#else +# ifdef CONFIG_DEBUG +# define message lowsyslog +# else +# define message printf +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVEUSBHOST +static struct usbhost_driver_s *g_drvr; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef NSH_HAVEUSBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + bool connected = false; + int ret; + + message("nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + ret = DRVR_WAIT(g_drvr, connected); + DEBUGASSERT(ret == OK); + + connected = !connected; + message("nsh_waiter: %s\n", connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)DRVR_ENUMERATE(g_drvr); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static int nsh_sdinitialize(void) +{ + FAR struct spi_dev_s *ssp; + int ret; + + /* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */ + + lpc17_gpiowrite(OPEN1788_MMC_PWR, false); + + /* Get the SSP port */ + + ssp = up_spiinitialize(CONFIG_NSH_MMCSDSPIPORTNO); + if (!ssp) + { + message("nsh_archinitialize: Failed to initialize SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + ret = -ENODEV; + goto errout; + } + + message("Successfully initialized SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + + /* Bind the SSP port to the slot */ + + ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, + CONFIG_NSH_MMCSDSLOTNO, ssp); + if (ret < 0) + { + message("nsh_sdinitialize: " + "Failed to bind SSP port %d to MMC/SD slot %d: %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, + CONFIG_NSH_MMCSDSLOTNO, ret); + goto errout; + } + + message("Successfuly bound SSP port %d to MMC/SD slot %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, + CONFIG_NSH_MMCSDSLOTNO); + return OK; + + /* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */ + +errout: + lpc17_gpiowrite(OPEN1788_MMC_PWR, true); + return ret; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVEUSBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + message("nsh_usbhostinitialize: Register class drivers\n"); + ret = usbhost_storageinit(); + if (ret != OK) + { + message("nsh_usbhostinitialize: Failed to register the mass storage class\n"); + } + + /* Then get an instance of the USB host interface */ + + message("nsh_usbhostinitialize: Initialize USB host\n"); + g_drvr = usbhost_initialize(0); + if (g_drvr) + { + /* Start a thread to handle device connection. */ + + message("nsh_usbhostinitialize: Start nsh_waiter\n"); + +#ifndef CONFIG_CUSTOM_STACK + pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); +#else + pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO, + (main_t)nsh_waiter, (FAR char * const *)NULL); +#endif + return pid < 0 ? -ENOEXEC : OK; + } + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_archinitialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int nsh_archinitialize(void) +{ + int ret; + + /* Initialize SPI-based microSD */ + + ret = nsh_sdinitialize(); + if (ret == OK) + { + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + } + return ret; +} -- cgit v1.2.3