From ed5182498e0f7e99c65763c8993ae0a6588fde99 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 21 Sep 2013 15:47:00 -0600 Subject: ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations --- nuttx/ChangeLog | 4 ++++ nuttx/arch/arm/src/armv7-a/cp15_clean_dcache.S | 2 +- nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 6ab09c760..a674d064f 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5610,3 +5610,7 @@ needed to be flushed to data cache; Fix another where a virual address was being used in a register where a physical address was required (2013-9-20). + * arch/arm/src/armv7-a/cp15_clean_dcache.S and cp15_flush_dcache.S: + fix an error in the alignment of addresses to cache line boundaries + (2013-9-21). + diff --git a/nuttx/arch/arm/src/armv7-a/cp15_clean_dcache.S b/nuttx/arch/arm/src/armv7-a/cp15_clean_dcache.S index fdc7513ed..6a244dac9 100755 --- a/nuttx/arch/arm/src/armv7-a/cp15_clean_dcache.S +++ b/nuttx/arch/arm/src/armv7-a/cp15_clean_dcache.S @@ -99,7 +99,7 @@ cp15_clean_dcache: mov r2, r2, lsl r3 /* Get the cache line size in bytes */ sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ + bic r0, r0, r3 /* R0=aligned start address */ /* Loop, cleaning each cache line by writing its contents to memory */ diff --git a/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S b/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S index 2e21db598..ba5b753ba 100755 --- a/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S +++ b/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S @@ -99,7 +99,7 @@ cp15_flush_dcache: mov r2, r2, lsl r3 /* Get the cache line size in bytes */ sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ + bic r0, r0, r3 /* R0=aligned start address */ /* Loop, cleaning and invaliding each D cache line in the address range */ -- cgit v1.2.3