From febd235e77df36985b82064d31911fc29e0265ad Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Apr 2014 16:27:00 -0600 Subject: SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping --- nuttx/ChangeLog | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'nuttx/ChangeLog') diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 139e4f604..6683cad09 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -7113,3 +7113,12 @@ from kfrolov (2014-4-2). * arch/arm/src/sama5/sam_boot.c, sam_irq.c, chip/sama5d3x_memorymap.h: When running from SDRAM, vectors must lie in SRAM (2014-4-2). + * arch/arm/src/armv7-a/arm_head.S and cache.h: On start-up, make + certain the the MMU and caches are disabled (probably un-necessary) + (2014-4-2). + * arch/arm/src/sama5/sam_boot.c: If we have to copy vectors, then + make sure to clean the DCache to be sure that the copied vectors are + in the physical RAM (2014-4-2). + * arch/arm/src/sama5/sam_irq.c: After we modify the AXI MATRIX, make + sure to invalidate all caches and TLBs (probably un-necessary) + (2014-4-2). -- cgit v1.2.3