From 08299566b26bff3f1941fa1a8bc46a3e0b6c6193 Mon Sep 17 00:00:00 2001 From: Matthias Zenger Date: Fri, 13 Feb 2004 13:20:16 +0000 Subject: - Downgraded to the old, bulky val syntax. --- test/files/run/Course-2002-08.scala | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'test/files/run') diff --git a/test/files/run/Course-2002-08.scala b/test/files/run/Course-2002-08.scala index d50d98ffc6..de6b497fde 100644 --- a/test/files/run/Course-2002-08.scala +++ b/test/files/run/Course-2002-08.scala @@ -506,7 +506,9 @@ abstract class BasicCircuitSimulator() extends Simulator() { } def orGate2(a1: Wire, a2: Wire, output: Wire) = { - val w1, w2, w3 = new Wire(); + val w1 = new Wire(); + val w2 = new Wire(); + val w3 = new Wire(); inverter(a1, w1); inverter(a2, w2); andGate(w1, w2, w3); @@ -517,7 +519,10 @@ abstract class BasicCircuitSimulator() extends Simulator() { abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux2(in: Wire, ctrl: List[Wire], out: List[Wire]) : Unit = { val ctrlN = ctrl.map(w => { val iw = new Wire(); inverter(w,iw); iw}); - val w0, w1, w2, w3 = new Wire(); + val w0 = new Wire(); + val w1 = new Wire(); + val w2 = new Wire(); + val w3 = new Wire(); andGate(in, ctrl(1), w3); andGate(in, ctrl(1), w2); @@ -537,7 +542,9 @@ abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux(in: Wire, ctrl: List[Wire], out: List[Wire]): Unit = ctrl match { case List() => connect(in, out.head); case c :: rest => - val c_, w1, w2 = new Wire(); + val c_ = new Wire(); + val w1 = new Wire(); + val w2 = new Wire(); inverter(c, c_); andGate(in, c_, w1); andGate(in, c, w2); -- cgit v1.2.3