From c67fdb87f7f731d13050f752acf1c35e51766c05 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 21 Dec 2012 20:09:32 +0000 Subject: Patches from Petteri Aimonen (plus a few other things) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5448 42af7a65-404d-4744-a932-0658087f49c3 --- NxWidgets/ChangeLog.txt | 32 + NxWidgets/Kconfig | 261 +++- NxWidgets/ReleaseNotes.txt | 2 +- NxWidgets/UnitTests/CButton/Makefile | 2 +- NxWidgets/UnitTests/CButtonArray/Makefile | 2 +- NxWidgets/UnitTests/CCheckBox/Makefile | 2 +- NxWidgets/UnitTests/CGlyphButton/Makefile | 2 +- NxWidgets/UnitTests/CImage/Makefile | 2 +- NxWidgets/UnitTests/CKeypad/Makefile | 2 +- NxWidgets/UnitTests/CLabel/Makefile | 2 +- NxWidgets/UnitTests/CLatchButton/Makefile | 2 +- NxWidgets/UnitTests/CLatchButtonArray/Makefile | 2 +- NxWidgets/UnitTests/CListBox/Makefile | 2 +- NxWidgets/UnitTests/CProgressBar/Makefile | 2 +- NxWidgets/UnitTests/CRadioButton/Makefile | 2 +- NxWidgets/UnitTests/CScrollbarHorizontal/Makefile | 2 +- NxWidgets/UnitTests/CScrollbarVertical/Makefile | 2 +- NxWidgets/UnitTests/CSliderHorizonal/Makefile | 2 +- NxWidgets/UnitTests/CSliderVertical/Makefile | 2 +- NxWidgets/UnitTests/CTextBox/Makefile | 2 +- NxWidgets/UnitTests/nxwm/Makefile | 2 +- NxWidgets/libnxwidgets/include/cgraphicsport.hxx | 34 + NxWidgets/libnxwidgets/include/cscrollingpanel.hxx | 3 +- NxWidgets/libnxwidgets/src/ccyclebutton.cxx | 19 - NxWidgets/libnxwidgets/src/cgraphicsport.cxx | 108 +- NxWidgets/libnxwidgets/src/clabel.cxx | 23 +- NxWidgets/libnxwidgets/src/cscrollingpanel.cxx | 40 +- apps/NxWidgets/Kconfig | 261 +++- nuttx/ChangeLog | 7 + nuttx/Documentation/NuttX.html | 2 +- nuttx/TODO | 13 +- nuttx/configs/shenzhou/nxwm/defconfig | 412 ++---- nuttx/configs/stm3220g-eval/README.txt | 15 + nuttx/configs/stm3220g-eval/nxwm/appconfig | 53 - nuttx/configs/stm3220g-eval/nxwm/defconfig | 1432 +++++++++++--------- nuttx/configs/stm3220g-eval/nxwm/setenv.sh | 2 +- nuttx/drivers/input/Kconfig | 19 + nuttx/graphics/Makefile | 3 + nuttx/graphics/nxfonts/Make.defs | 6 + nuttx/graphics/nxfonts/Makefile.sources | 7 + nuttx/graphics/nxfonts/nxfonts_bitmaps.c | 2 + nuttx/graphics/nxfonts/nxfonts_getfont.c | 12 + nuttx/graphics/nxfonts/nxfonts_mono5x8.h | 815 +++++++++++ nuttx/include/nuttx/nx/nxfonts.h | 6 + nuttx/include/pthread.h | 4 +- nuttx/include/stdbool.h | 4 +- nuttx/tools/bdf-converter.c | 1 + 47 files changed, 2502 insertions(+), 1132 deletions(-) delete mode 100644 nuttx/configs/stm3220g-eval/nxwm/appconfig create mode 100644 nuttx/graphics/nxfonts/nxfonts_mono5x8.h diff --git a/NxWidgets/ChangeLog.txt b/NxWidgets/ChangeLog.txt index df9fb2d41..744584ed4 100644 --- a/NxWidgets/ChangeLog.txt +++ b/NxWidgets/ChangeLog.txt @@ -220,3 +220,35 @@ classing easier (from Petteri Aimonen). 1.5 2013-xx-xx Gregory Nutt + +* NxWidgets::CGraphicsPort::move(): Fix typo bug in bounding rectangle + calculation (from Petteri Aimonen). +* NxWM::CScrollingPanel::scrollChildren(): Avoid unnecessary redraws in + CScrollingPanel (contributed by Petteri Aimonen). +* NxWM::CCycleButton: Remove the separator from CCycleButton. It draws in + wrong place, and doesnt look very good in the correct place either. + (from Petteri Aimonen). +* NxWidgets::CGraphicsPort: Many times we only want a constant background. + In that case the old code fills the background, reads it back, renders + the text and then writes it back. When used with LCD's (instead of + framebuffers) this causes unnecessary delay and screen flicker. + This commit adds a variant of drawText that takes background color, + so that the background and text can both be rendered at one go. + The old functions still function as before (Petteri Aimonen). +* NxWidgets::CLabel: The label was drawn as a single rectangular region, + then a text was added to the on top of this. The result is that the + text would flicker when the CLabel was updated. With this change, the + two step update is replaced with a five step update: The background + is updated as four rectangulear regions (leaving the previous text in + place), then the new text is updated. This eliminates the flicker + (Petteri Aimonen). +* Kconfig: Many NxWidgets/NxWM settings do not have meaningful, generic + default values. Colors, for example, depend on pixel depth. Some + geometry settings depending on other geometry settings. Font IDs are + not know-able by the configuration system. etc. In these cases, it + is best if the settings are just not undefined so that the system can + calculate a reasonable default. however, if no default is provided + in the .config file, mconf will complain and generate errors. So work + around this, I added several "enabling" settings to override the + default setting. This is awkward and I preferred the configuration as + it was before, but this avoids the mconf errors and warnings. diff --git a/NxWidgets/Kconfig b/NxWidgets/Kconfig index 59d8856bc..656399199 100644 --- a/NxWidgets/Kconfig +++ b/NxWidgets/Kconfig @@ -13,6 +13,18 @@ config NXWIDGETS if NXWIDGETS comment "NX Server/Device Configuration" +config NXWIDGETS_FLICKERFREE + bool "Enable Flicker Reduction Logic" + default y if NX_LCDDRIVER + default n if !NX_LCDDRIVER + ---help--- + Because of their performance an in the manner in which they are + updated, LCDs may be prone to "flicker" in the displays when Widgets + are updated. Often more complex (and slower) options are availble + to reduce the flicker. Enabling this option will enabled those + lower-performance flicker-reductions measures where-ever thay may + be available. + config NXWIDGETS_DEVNO int "LCD Device Number" default 0 @@ -96,10 +108,20 @@ config NXWIDGETS_SIZEOFCHAR comment "NXWidget Default Values" +config NXWIDGETS_SYSTEM_CUSTOM_FONTID + bool "Use a Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXFONT_DEFAULT). + +if NXWIDGETS_SYSTEM_CUSTOM_FONTID config NXWIDGETS_DEFAULT_FONTID int "Default Font ID" + default 0 ---help--- - Default font ID. Default: NXFONT_DEFAULT + Use this default NxWidgets font ID instead of the system font ID + (NXFONT_DEFAULT). Default: 0 +endif config NXWIDGETS_TNXARRAY_INITIALSIZE int "Initial Size of Dynamic Arrays" @@ -113,53 +135,88 @@ config NXWIDGETS_TNXARRAY_SIZEINCREMENT ---help--- Default dynamic array realloctino increment (in entries). Default: 8 +config NXWIDGETS_CUSTOM_FILLCOLORS + bool "Custom Default Fill Colors" + default n + ---help--- + Select custom default colors for the widget background. If defined, + the hexadecimal values for all filled colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWIDGETS_CUSTOM_FILLCOLORS config NXWIDGETS_DEFAULT_BACKGROUNDCOLOR - hex "Normal Background Color" + hex "Default Normal Background Color" ---help--- Normal background color. Default: RGB(148,189,215) config NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR - hex "Selected Background Color" + hex "Default Selected Background Color" ---help--- Default selected background color. Default: RGB(206,227,241) +config NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR + hex "Default Highlight Color" + ---help--- + Highlight color. Currently this color is only used in clist + boxes, progress bars, and slider grips. Default: RGB(192,192,192) +endif + +config NXWIDGETS_CUSTOM_EDGECOLORS + bool "Custom Default Edge Colors" + default n + ---help--- + Select custom default colors for the widget edges. If defined, + then hexadecimal values for all edge colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. + +if NXWIDGETS_CUSTOM_EDGECOLORS config NXWIDGETS_DEFAULT_SHINEEDGECOLOR - hex "Shiny Edge Color" + hex "Default Shiny Edge Color" ---help--- Shiny side boarder color. Default: RGB(248,248,248) config NXWIDGETS_DEFAULT_SHADOWEDGECOLOR - hex "Shadow Edge Color" + hex "Default Shadow Edge Color" ---help--- Shadowed side border color. Default: RGB(35,58,73) +endif -config NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR - hex "Highlight Color" +config NXWIDGETS_CUSTOM_TEXTCOLORS + bool "Custom Default Text colors" + default n ---help--- - Highlight color. Default: RGB(192,192,192) + Select custom colors for the widget text. If defined, then + hexadecimal values for all text colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. +if NXWIDGETS_CUSTOM_TEXTCOLORS config NXWIDGETS_DEFAULT_DISABLEDTEXTCOLOR - hex "Disabled Text Color" + hex "Default Disabled Text Color" ---help--- Text color on a disabled widget: Default: RGB(192,192,192) config NXWIDGETS_DEFAULT_ENABLEDTEXTCOLOR - hex "Enabled Text Color" + hex "Default Enabled Text Color" ---help--- Text color on a enabled widget. Default: RGB(248,248,248) config NXWIDGETS_DEFAULT_SELECTEDTEXTCOLOR - hex "Selected Text Color" + hex "Default Selected Text Color" ---help--- Text color on a selected widget. Default: RGB(0,0,0) config NXWIDGETS_DEFAULT_FONTCOLOR - hex "Default Font Color" + hex "Default Default Font Color" ---help--- Default font color. Default: RGB(255,255,255) +endif config NXWIDGETS_TRANSPARENT_COLOR hex "Transparent Color" + default 0x0 ---help--- Transparent color. Default: RGB(0,0,0) @@ -220,10 +277,20 @@ config NXWM if NXWM comment "General settings" +config NXWM_SYSTEM_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXFONT_DEFAULT). + +if NXWM_SYSTEM_CUSTOM_FONTID config NXWM_DEFAULT_FONTID int "Font ID" + default 0 ---help--- - The NxWM default font ID. Default: NXFONT_DEFAULT + Use this NxWM default font ID instead of the system font ID + (NXFONT_DEFAULT). Default: 0 +endif config NXWM_UNITTEST bool "NxWM Unit Test" @@ -233,6 +300,16 @@ config NXWM_UNITTEST comment "Color configuration" +config NXWM_CUSTOM_FILLCOLORS + bool "Custom Default Fill Colors" + default n + ---help--- + Select custom default colors for the widget background. If defined, + the hexadecimal values for all filled colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWM_CUSTOM_FILLCOLORS config NXWM_DEFAULT_BACKGROUNDCOLOR hex "Background Color" ---help--- @@ -242,7 +319,18 @@ config NXWM_DEFAULT_SELECTEDBACKGROUNDCOLOR hex "Normal Background Color" ---help--- Select background color. Default: RGB(206,227,241) +endif +config NXWM_CUSTOM_EDGECOLORS + bool "Custom Default Edge Colors" + default n + ---help--- + Select custom default colors for the widget edges. If defined, + then hexadecimal values for all edge colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. + +if NXWM_CUSTOM_EDGECOLORS config NXWM_DEFAULT_SHINEEDGECOLOR hex "Shiny Edge Color" ---help--- @@ -252,7 +340,18 @@ config NXWM_DEFAULT_SHADOWEDGECOLOR hex "Shadow Edge Color" ---help--- Color of the shadowed edge of a border. Default: RGB(0,0,0) +endif + +config NXWM_CUSTOM_TEXTCOLORS + bool "Custom Default Text colors" + default n + ---help--- + Select custom colors for the widget text. If defined, then + hexadecimal values for all text colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. +if NXWM_CUSTOM_TEXTCOLORS config NXWM_DEFAULT_FONTCOLOR hex "Default Font Color" ---help--- @@ -260,8 +359,10 @@ config NXWM_DEFAULT_FONTCOLOR config NXWM_TRANSPARENT_COLOR hex "Transparent Color" + default 0x0 ---help--- The "transparent" color. Default: RGB(0,0,0) +endif comment "Horizontal and vertical spacing of icons in the task bar" @@ -303,27 +404,48 @@ config NXWM_TASKBAR_RIGHT endchoice +config NXWM_CUSTOM_TASKBAR_WIDTH + bool "Use Custom Taskbar width" + default n + ---help--- + Set to override the default taskbar thickness (either vertical or + horizontal). The default depends on the selected horizontal or + vertical spacing. Default: 25 + 2*spacing + +if NXWM_CUSTOM_TASKBAR_WIDTH config NXWM_TASKBAR_WIDTH int "Taskbar Width" + default 29 ---help--- - Task bar thickness (either vertical or horizontal). Default: 25 + 2*spacing + Task bar thickness (either vertical or horizontal). Default: 25 + 2*2 +endif config NXWM_DISABLE_MINIMIZE bool "Disable Minimize Button" default n ---help--- - If the "desktop" is empty, users have no need to minimize any windows. If the buttons - are small, it's easy to hit minimize button accidentally when trying to close an - application. + If the "desktop" is empty, users have no need to minimize any + windows. If the buttons are small, it's easy to hit minimize + button accidentally when trying to close an application. comment "Tool Bar Configuration" +config NXWM_CUSTOM_TOOLBAR_HEIGHT + bool "Use Custom Toolbar Height" + default n + ---help--- + Set to override the default tooldar height The default depends on + the selected horizontal or vertical spacing. Default: 21 + 2*spacing + +if NXWM_CUSTOM_TOOLBAR_HEIGHT config NXWM_TOOLBAR_HEIGHT int "Toolbar Height" + default 25 ---help--- The height of the tool bar in each application window. At present, all icons are 21 pixels in height and, hence, require a task bar of - at least that size. + at least that size. Default: 21 + 2*2 +endif comment "Background Image" @@ -357,10 +479,19 @@ config NXWM_STARTWINDOW_HSPACING ---help--- Horizontal spacing. Default: 4 rows +config NXWM_CUSTOM_STARTWINDOW_ICON + bool "Custom Start Window Icon" + default n + ---help--- + Select to override the default Start Window Icon: NxWM::g_playBitmap + +if NXWM_CUSTOM_STARTWINDOW_ICON config NXWM_STARTWINDOW_ICON string "StartWindow Icon" + default "NxWM::g_playBitmap" ---help--- The glyph to use as the start window icon. Default: NxWM::g_playBitmap +endif config NXWM_STARTWINDOW_MQNAME string "Message Queue Name" @@ -417,6 +548,16 @@ config NXWM_NXCONSOLE_STACKSIZE The stack size to use when starting the NxConsole task. Default: 2048 bytes. +config NXWM_NXCONSOLE_CUSTOM_COLORS + bool "Custom NxConsole Colors" + default n + ---help--- + Select custom default colors for the NxConsole window. If defined, + the hexadecimal values for all NxConsole colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWM_NXCONSOLE_CUSTOM_COLORS config NXWM_NXCONSOLE_WCOLOR hex "NxConsole Background Color" ---help--- @@ -428,17 +569,36 @@ config NXWM_NXCONSOLE_FONTCOLOR ---help--- The color of the fonts to use in the NxConsole window. Default: RGB(0,0,0) +endif +config NXWM_NXCONSOLE_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXWM_DEFAULT_FONTID). + +if NXWM_NXCONSOLE_CUSTOM_FONTID config NXWM_NXCONSOLE_FONTID int "NxConsole Font ID" + default 0 ---help--- - The ID of the font to use in the NxConsole window. Default: - NXWM_DEFAULT_FONTID + Use this default font ID in the NxConsole window instead of the + NxWM font ID (NXWM_DEFAULT_FONTID). Default: 0 +endif +config NXWM_CUSTOM_NXCONSOLE_ICON + bool "Custom NxConsole Icon" + default n + ---help--- + Select to override the default NxConsole Window Icon: NxWM::g_cmdBitmap + +if NXWM_CUSTOM_NXCONSOLE_ICON config NXWM_NXCONSOLE_ICON string "NxConsole Icon" + default "NxWM::g_cmdBitmap" ---help--- The glyph to use as the NxConsole icon. Default: NxWM::g_cmdBitmap +endif config NXWM_TOUCHSCREEN bool "Touchscreen Support" @@ -478,6 +638,7 @@ config NXWM_TOUCHSCREEN_LISTENERPRIO config NXWM_TOUCHSCREEN_LISTENERSTACK int "Touchscreen Listener Task Stack Size" + default 1024 ---help--- Touchscreen listener thread stack size. Default 1024 @@ -527,6 +688,17 @@ endif comment "Calibration display settings" +config NXWM_CALIBRATION_CUSTOM_COLORS + bool "Custom Calibration Colors" + default n + ---help--- + Select custom default colors for the calibration window. If + defined, the hexadecimal values for all calibration window + colors must be provided (there are no default colors because + the hexadecimal representation of the default colors depend + on the pixel depth). Default: n + +if NXWM_CALIBRATION_CUSTOM_COLORS config NXWM_CALIBRATION_BACKGROUNDCOLOR hex "Background Color" ---help--- @@ -550,12 +722,23 @@ config NXWM_CALIBRATION_TOUCHEDCOLOR ---help--- The color of the circle in the touchscreen calibration display after the touch is recorder. Default: RGB(255, 255, 96) (very light yellow) +endif + +config NXWM_CUSTOM_CALIBRATION_ICON + bool "Custom Calibration Icon" + default n + ---help--- + Select to override the default Calibration Window Icon: + NxWM::g_calibrationBitmap +if NXWM_CUSTOM_CALIBRATION_ICON config NXWM_CALIBRATION_ICON string "Callibration Icon" + default "NxWM::g_calibrationBitmap" ---help--- The ICON to use for the touchscreen calibration application. Default: NxWM::g_calibrationBitmap +endif config NXWM_CALIBRATION_SIGNO int "Calibration Signal Number" @@ -576,23 +759,55 @@ config NXWM_CALIBRATION_LISTENERSTACK ---help--- Calibration listener thread stack size. Default 2048 -comment "Calibration display settings" +comment "Hex Calculator display settings" +config NXWM_HEXCALCULATOR_CUSTOM_COLORS + bool "Custom Hex Calculator Colors" + default n + ---help--- + Select custom default colors for the Hex Calcualtor window. If + defined, the hexadecimal values for all hex calculator colors + must be provided (there are no default colors because the + hexadecimal representation of the default colors depend on the + pixel depth). Default: n + +if NXWM_HEXCALCULATOR_CUSTOM_COLORS config NXWM_HEXCALCULATOR_BACKGROUNDCOLOR hex "Calculator Background Color" ---help--- The background color of the calculator display. Default: Same as NXWM_DEFAULT_BACKGROUNDCOLOR +endif +config NXWM_CUSTOM_HEXCALCULATOR_ICON + bool "Custom Hex Calculator Icon" + default n + ---help--- + Select to override the default Hex Calculator Window Icon: + NxWM::g_calculatorBitmap + +if NXWM_CUSTOM_HEXCALCULATOR_ICON config NXWM_HEXCALCULATOR_ICON string "Calculator Icon" + default "NxWM::g_calculatorBitmap" ---help--- The ICON to use for the hex calculator application. Default: - NxWM::g_calculatorBitmap + "NxWM::g_calculatorBitmap" +endif +config NXWM_HEXCALCULATOR_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXWM_DEFAULT_FONTID). + +if NXWM_HEXCALCULATOR_CUSTOM_FONTID config NXWM_HEXCALCULATOR_FONTID int "Calculator Font ID" + default 0 ---help--- - The font used with the calculator. Default: NXWM_DEFAULT_FONTID + Use this default font ID in the calculator window instead of the + NxWM font ID (NXWM_DEFAULT_FONTID). Default: 0 +endif endif diff --git a/NxWidgets/ReleaseNotes.txt b/NxWidgets/ReleaseNotes.txt index 4b155c50e..aaaefe6eb 100644 --- a/NxWidgets/ReleaseNotes.txt +++ b/NxWidgets/ReleaseNotes.txt @@ -116,7 +116,7 @@ NxWidgets-1.4 ============= The 5th release of the NxWidgets package was made on December 20, 2012. This -release depends on NuttX-6.22 or above and should not be used with older +release depends on NuttX-6.24 or above and should not be used with older NuttX releases. This release corresponds to SVN revision r5447. Note: Nearly all changes between 1.3 and 1.4 were the result of the efforts diff --git a/NxWidgets/UnitTests/CButton/Makefile b/NxWidgets/UnitTests/CButton/Makefile index d80ef3c76..ea7b5cf25 100644 --- a/NxWidgets/UnitTests/CButton/Makefile +++ b/NxWidgets/UnitTests/CButton/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CButtonArray/Makefile b/NxWidgets/UnitTests/CButtonArray/Makefile index b4a3b0571..6bb490e34 100644 --- a/NxWidgets/UnitTests/CButtonArray/Makefile +++ b/NxWidgets/UnitTests/CButtonArray/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CCheckBox/Makefile b/NxWidgets/UnitTests/CCheckBox/Makefile index 21e007b3d..bd8293983 100644 --- a/NxWidgets/UnitTests/CCheckBox/Makefile +++ b/NxWidgets/UnitTests/CCheckBox/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CGlyphButton/Makefile b/NxWidgets/UnitTests/CGlyphButton/Makefile index 1e7faf026..b69382133 100644 --- a/NxWidgets/UnitTests/CGlyphButton/Makefile +++ b/NxWidgets/UnitTests/CGlyphButton/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CImage/Makefile b/NxWidgets/UnitTests/CImage/Makefile index 61978147e..08e22772f 100644 --- a/NxWidgets/UnitTests/CImage/Makefile +++ b/NxWidgets/UnitTests/CImage/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CKeypad/Makefile b/NxWidgets/UnitTests/CKeypad/Makefile index d27b90192..0bbf837d8 100644 --- a/NxWidgets/UnitTests/CKeypad/Makefile +++ b/NxWidgets/UnitTests/CKeypad/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CLabel/Makefile b/NxWidgets/UnitTests/CLabel/Makefile index 14e8897d2..4cd3d05d8 100644 --- a/NxWidgets/UnitTests/CLabel/Makefile +++ b/NxWidgets/UnitTests/CLabel/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CLatchButton/Makefile b/NxWidgets/UnitTests/CLatchButton/Makefile index 435a4c3cd..92909ab62 100644 --- a/NxWidgets/UnitTests/CLatchButton/Makefile +++ b/NxWidgets/UnitTests/CLatchButton/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CLatchButtonArray/Makefile b/NxWidgets/UnitTests/CLatchButtonArray/Makefile index 0f6fe639f..412174ea2 100644 --- a/NxWidgets/UnitTests/CLatchButtonArray/Makefile +++ b/NxWidgets/UnitTests/CLatchButtonArray/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CListBox/Makefile b/NxWidgets/UnitTests/CListBox/Makefile index 301424c47..58d313b4f 100644 --- a/NxWidgets/UnitTests/CListBox/Makefile +++ b/NxWidgets/UnitTests/CListBox/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CProgressBar/Makefile b/NxWidgets/UnitTests/CProgressBar/Makefile index d50d3ed05..c57b0cf6e 100644 --- a/NxWidgets/UnitTests/CProgressBar/Makefile +++ b/NxWidgets/UnitTests/CProgressBar/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CRadioButton/Makefile b/NxWidgets/UnitTests/CRadioButton/Makefile index ff6c2d247..1278c8f53 100644 --- a/NxWidgets/UnitTests/CRadioButton/Makefile +++ b/NxWidgets/UnitTests/CRadioButton/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CScrollbarHorizontal/Makefile b/NxWidgets/UnitTests/CScrollbarHorizontal/Makefile index a5fab0dda..c1edc8936 100644 --- a/NxWidgets/UnitTests/CScrollbarHorizontal/Makefile +++ b/NxWidgets/UnitTests/CScrollbarHorizontal/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CScrollbarVertical/Makefile b/NxWidgets/UnitTests/CScrollbarVertical/Makefile index 204b90a52..e3367e167 100644 --- a/NxWidgets/UnitTests/CScrollbarVertical/Makefile +++ b/NxWidgets/UnitTests/CScrollbarVertical/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CSliderHorizonal/Makefile b/NxWidgets/UnitTests/CSliderHorizonal/Makefile index 67f00f622..c739fef96 100644 --- a/NxWidgets/UnitTests/CSliderHorizonal/Makefile +++ b/NxWidgets/UnitTests/CSliderHorizonal/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CSliderVertical/Makefile b/NxWidgets/UnitTests/CSliderVertical/Makefile index 409f361fd..82f9c6fc6 100644 --- a/NxWidgets/UnitTests/CSliderVertical/Makefile +++ b/NxWidgets/UnitTests/CSliderVertical/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/CTextBox/Makefile b/NxWidgets/UnitTests/CTextBox/Makefile index a4c752e6c..ddd16e95a 100644 --- a/NxWidgets/UnitTests/CTextBox/Makefile +++ b/NxWidgets/UnitTests/CTextBox/Makefile @@ -134,7 +134,7 @@ chklib: $(NXWIDGETS_LIB): # Just to keep make happy. chklib does the work. .built: chkcxx chklib $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) else diff --git a/NxWidgets/UnitTests/nxwm/Makefile b/NxWidgets/UnitTests/nxwm/Makefile index 338b83e54..76007da1c 100644 --- a/NxWidgets/UnitTests/nxwm/Makefile +++ b/NxWidgets/UnitTests/nxwm/Makefile @@ -162,7 +162,7 @@ $(NXWIDGETS_LIB): # Just to keep make happy. chklibnxwidgets does the work. $(NXWM_LIB): # Just to keep make happy. chklibnxwm does the work. .built: $(OBJS) $(NXWIDGETS_LIB) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $(BIN), $(OBJS)) ifeq ($(WINTOOL),y) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWIDGETS_DIR) $(Q) $(ARCHIVER) -w -p "$(CROSSDEV)" $(BIN) $(NXWM_DIR) diff --git a/NxWidgets/libnxwidgets/include/cgraphicsport.hxx b/NxWidgets/libnxwidgets/include/cgraphicsport.hxx index b9fbc4d41..d3d9e6114 100644 --- a/NxWidgets/libnxwidgets/include/cgraphicsport.hxx +++ b/NxWidgets/libnxwidgets/include/cgraphicsport.hxx @@ -111,6 +111,22 @@ namespace NXWidgets nxgl_mxpixel_t m_backColor; /**< The background color to use */ #endif + /** + * The underlying implementation for drawText functions + * @param pos The window-relative x/y coordinate of the string. + * @param bound The window-relative bounds of the string. + * @param font The font to draw with. + * @param string The string to output. + * @param startIndex The start index within the string from which + * drawing will commence. + * @param length The number of characters to draw. + * @param background Color to use for background if transparent is false. + * @param transparent Whether to fill the background. + */ + void drawText(struct nxgl_point_s *pos, CRect *bound, CNxFont *font, + const CNxString &string, int startIndex, int length, + nxgl_mxpixel_t background, bool transparent); + public: /** * Constructor. @@ -329,6 +345,24 @@ namespace NXWidgets void drawText(struct nxgl_point_s *pos, CRect *bound, CNxFont *font, const CNxString &string, int startIndex, int length); + /** + * Draw a portion of a string to the window and fill the background + * in one go. + * @param pos The window-relative x/y coordinate of the string. + * @param bound The window-relative bounds of the string. + * @param font The font to draw with. + * @param string The string to output. + * @param startIndex The start index within the string from which + * drawing will commence. + * @param length The number of characters to draw. + * @param color Foreground color + * @param background Background color + */ + + void drawText(struct nxgl_point_s *pos, CRect *bound, CNxFont *font, + const CNxString &string, int startIndex, int length, + nxgl_mxpixel_t color, nxgl_mxpixel_t background); + /** * Draw an opaque bitmap to the window. * diff --git a/NxWidgets/libnxwidgets/include/cscrollingpanel.hxx b/NxWidgets/libnxwidgets/include/cscrollingpanel.hxx index 90dcc1ac9..b27176e2f 100644 --- a/NxWidgets/libnxwidgets/include/cscrollingpanel.hxx +++ b/NxWidgets/libnxwidgets/include/cscrollingpanel.hxx @@ -168,9 +168,10 @@ namespace NXWidgets * * @param dx The horizontal distance to scroll. * @param dy The vertical distance to scroll. + * @param do_redraw Redraw widgets after moving. */ - void scrollChildren(int32_t dx, int32_t dy); + void scrollChildren(int32_t dx, int32_t dy, bool do_redraw); /** * Destructor. diff --git a/NxWidgets/libnxwidgets/src/ccyclebutton.cxx b/NxWidgets/libnxwidgets/src/ccyclebutton.cxx index b5f96683d..0fdbba73c 100644 --- a/NxWidgets/libnxwidgets/src/ccyclebutton.cxx +++ b/NxWidgets/libnxwidgets/src/ccyclebutton.cxx @@ -309,30 +309,21 @@ void CCycleButton::drawContents(CGraphicsPort *port) CRect rect; getRect(rect); - nxgl_coord_t glyphSpace = m_borderSize.left - 1; nxgl_coord_t glyphYOffset = (rect.getHeight() - g_cycle.height) >> 1; nxwidget_pixel_t textColor; - nxwidget_pixel_t separatorLeftColor; - nxwidget_pixel_t separatorRightColor; if (!isEnabled()) { textColor = getDisabledTextColor(); - separatorLeftColor = getShadowEdgeColor(); - separatorRightColor = getShineEdgeColor(); } else if (!isClicked()) { textColor = getEnabledTextColor(); - separatorLeftColor = getShadowEdgeColor(); - separatorRightColor = getShineEdgeColor(); } else { textColor = getSelectedTextColor(); - separatorLeftColor = getShineEdgeColor(); - separatorRightColor = getShadowEdgeColor(); } // Draw cycle glyph @@ -341,16 +332,6 @@ void CCycleButton::drawContents(CGraphicsPort *port) g_cycle.width, g_cycle.height, &g_cycle, 0, 0, CONFIG_NXWIDGETS_TRANSPARENT_COLOR); - // Draw separator - - nxgl_coord_t x = getX() + glyphSpace + g_cycle.width; - nxgl_coord_t y = getY(); - nxgl_coord_t w = glyphSpace + g_cycle.width; - nxgl_coord_t h = rect.getHeight() - 1; - - port->drawLine(x, y, w, h, separatorLeftColor); - port->drawLine(x+1, y, w+1, h, separatorRightColor); - // Only draw text if option is selected if (m_options.getSelectedItem() != NULL) diff --git a/NxWidgets/libnxwidgets/src/cgraphicsport.cxx b/NxWidgets/libnxwidgets/src/cgraphicsport.cxx index d43f3bdfa..73f2352eb 100644 --- a/NxWidgets/libnxwidgets/src/cgraphicsport.cxx +++ b/NxWidgets/libnxwidgets/src/cgraphicsport.cxx @@ -653,6 +653,55 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, CNxFont *font, const CNxString &string, int startIndex, int length) +{ + drawText(pos, bound, font, string, startIndex, length, 0, true); +} + +/** + * Draw a portion of a string to the window and fill the background + * in one go. + * @param pos The window-relative x/y coordinate of the string. + * @param bound The window-relative bounds of the string. + * @param font The font to draw with. + * @param string The string to output. + * @param startIndex The start index within the string from which + * drawing will commence. + * @param length The number of characters to draw. + * @param color Foreground color + * @param background Background color + */ + +void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, + CNxFont *font, const CNxString &string, + int startIndex, int length, + nxgl_mxpixel_t color, + nxgl_mxpixel_t background) +{ + nxgl_mxpixel_t savedColor = font->getColor(); + font->setColor(color); + + drawText(pos, bound, font, string, startIndex, length, background, false); + + font->setColor(savedColor); +} + +/** + * The underlying implementation for drawText functions + * @param pos The window-relative x/y coordinate of the string. + * @param bound The window-relative bounds of the string. + * @param font The font to draw with. + * @param string The string to output. + * @param startIndex The start index within the string from which + * drawing will commence. + * @param length The number of characters to draw. + * @param background Color to use for background if transparent is false. + * @param transparent Whether to fill the background. + */ +void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, + CNxFont *font, const CNxString &string, + int startIndex, int length, + nxgl_mxpixel_t background, + bool transparent) { // Verify index and length @@ -668,6 +717,16 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, endIndex = stringLength; } +#ifdef CONFIG_NX_WRITEONLY + if (transparent) + { + // Can't render transparently without reading memory. + + transparent = false; + background = m_backColor; + } +#endif + // Allocate a bit of memory to hold the largest rendered font unsigned int bmWidth = ((unsigned int)font->getMaxWidth() * CONFIG_NXWIDGETS_BPP + 7) >> 3; @@ -680,7 +739,7 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, struct nxgl_rect_s boundingBox; bound->getNxRect(&boundingBox); - + // Loop setup struct SBitmap bitmap; @@ -707,16 +766,12 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, // Does the letter have height? Spaces have width, but no height - if (metrics.height > 0) + if (metrics.height > 0 || !transparent) { - // Get the height of the font - - nxgl_coord_t fontHeight = (nxgl_coord_t)(metrics.height + metrics.yoffset); - // Set the current, effective size of the bitmap bitmap.width = fontWidth; - bitmap.height = fontHeight; + bitmap.height = bmHeight; bitmap.stride = (fontWidth * bitmap.bpp + 7) >> 3; // Describe the destination of the font as a bounding box @@ -725,7 +780,7 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, dest.pt1.x = pos->x; dest.pt1.y = pos->y; dest.pt2.x = pos->x + fontWidth - 1; - dest.pt2.y = pos->y + fontHeight - 1; + dest.pt2.y = pos->y + bmHeight - 1; // Get the interection of the font box and the bounding box @@ -737,25 +792,28 @@ void CGraphicsPort::drawText(struct nxgl_point_s *pos, CRect *bound, if (!nxgl_nullrect(&intersection)) { - // Initialize the bitmap memory by reading from the display. The - // font renderer always renders the fonts on a transparent background. - // Sometimes a solid background works, sometimes not. But reading - // from graphics memory always works. - -#ifdef CONFIG_NX_WRITEONLY - // Set the glyph memory to the background color - - nxwidget_pixel_t *bmPtr = (nxwidget_pixel_t *)bitmap.data; - unsigned int npixels = fontWidth * fontHeight; - for (unsigned int j = 0; j < npixels; j++) + // If we have been given a background color, use it to fill the array. + // Otherwise initialize the bitmap memory by reading from the display. + // The font renderer always renders the fonts on a transparent background. + + if (!transparent) { - *bmPtr++ = m_backColor; + // Set the glyph memory to the background color + + nxwidget_pixel_t *bmPtr = (nxwidget_pixel_t *)bitmap.data; + unsigned int npixels = fontWidth * bmHeight; + for (unsigned int j = 0; j < npixels; j++) + { + *bmPtr++ = background; + } + } + else + { + // Read the current contents of the destination into the glyph memory + + m_pNxWnd->getRectangle(&dest, &bitmap); } -#else - // Read the current contents of the destination into the glyph memory - m_pNxWnd->getRectangle(&dest, &bitmap); -#endif // Render the font into the initialized bitmap font->drawChar(&bitmap, letter); @@ -827,7 +885,7 @@ void CGraphicsPort::move(nxgl_coord_t x, nxgl_coord_t y, rect.pt1.x = x; rect.pt1.y = y; rect.pt2.x = x + width - 1; - rect.pt2.y = y = height -1; + rect.pt2.y = y + height - 1; struct nxgl_point_s offset; offset.x = deltaX; diff --git a/NxWidgets/libnxwidgets/src/clabel.cxx b/NxWidgets/libnxwidgets/src/clabel.cxx index 4c7ea3554..be4fe902d 100644 --- a/NxWidgets/libnxwidgets/src/clabel.cxx +++ b/NxWidgets/libnxwidgets/src/clabel.cxx @@ -303,8 +303,10 @@ void CLabel::drawContents(CGraphicsPort *port) // Draw the background (excluding the border) +#ifdef CONFIG_NXWIDGETS_FLICKERFREE port->drawFilledRect(rect.getX(), rect.getY(), rect.getWidth(), rect.getHeight(), backColor); +#endif // Get the X/Y position of the text within the Label @@ -312,10 +314,27 @@ void CLabel::drawContents(CGraphicsPort *port) pos.x = rect.getX() + m_align.x; pos.y = rect.getY() + m_align.y; - // Add the text using the selected color +#ifdef CONFIG_NXWIDGETS_FLICKERFREE + CNxFont* font = getFont(); + int height = font->getHeight(); + int width = font->getStringWidth(m_text); + + // Draw the background (excluding the border and the text area) + + port->drawFilledRect(rect.getX(), rect.getY(), + pos.x - rect.getX(), rect.getHeight(), backColor); // Left + port->drawFilledRect(pos.x + width, rect.getY(), + rect.getX2() - (pos.x + width) + 1, rect.getHeight(), backColor); // Right + port->drawFilledRect(pos.x, rect.getY(), + width, pos.y - rect.getY(), backColor); // Top + port->drawFilledRect(pos.x, pos.y + height, + width, rect.getY2() - (pos.y + height) + 1, backColor); // Bottom +#endif + + // Add the text using the selected color and background color port->drawText(&pos, &rect, getFont(), m_text, 0, m_text.getLength(), - textColor); + textColor, backColor); } /** diff --git a/NxWidgets/libnxwidgets/src/cscrollingpanel.cxx b/NxWidgets/libnxwidgets/src/cscrollingpanel.cxx index b7c507bb2..2541bb572 100644 --- a/NxWidgets/libnxwidgets/src/cscrollingpanel.cxx +++ b/NxWidgets/libnxwidgets/src/cscrollingpanel.cxx @@ -215,10 +215,13 @@ void CScrollingPanel::scroll(int32_t dx, int32_t dy) m_canvasY += dy; m_canvasX += dx; + // Move children but do not redraw. + + scrollChildren(dx, dy, false); + if (revealedRects.size() > 0) { // Draw background to revealed sections - // Children will redraw themselves in moveTo. for (int i = 0; i < revealedRects.size(); ++i) { @@ -231,6 +234,18 @@ void CScrollingPanel::scroll(int32_t dx, int32_t dy) port->drawFilledRect(rrect.getX(), rrect.getY(), rrect.getWidth(), rrect.getHeight(), getBackgroundColor()); + + // Check if any children intersect this region. + // If it does, it should be redrawn. + + for (int j = 0; j < m_children.size(); ++j) + { + CRect crect = m_children[j]->getBoundingBox(); + if (crect.intersects(rrect)) + { + m_children[j]->redraw(); + } + } } } } @@ -240,11 +255,11 @@ void CScrollingPanel::scroll(int32_t dx, int32_t dy) m_canvasY += dy; m_canvasX += dx; - } - - // Scroll all child widgets + + // Scroll all child widgets and redraw them - scrollChildren(dx, dy); + scrollChildren(dx, dy, true); + } // Notify event handlers @@ -332,9 +347,10 @@ void CScrollingPanel::onClick(nxgl_coord_t x, nxgl_coord_t y) * * @param dx The horizontal distance to scroll. * @param dy The vertical distance to scroll. + * @param do_redraw Redraw widgets after moving. */ -void CScrollingPanel::scrollChildren(int32_t dx, int32_t dy) +void CScrollingPanel::scrollChildren(int32_t dx, int32_t dy, bool do_redraw) { nxgl_coord_t widgetX = 0; nxgl_coord_t widgetY = 0; @@ -345,8 +361,20 @@ void CScrollingPanel::scrollChildren(int32_t dx, int32_t dy) for (int32_t i = 0; i < m_children.size(); i++) { widget = m_children[i]; + bool oldstate = widget->isDrawingEnabled(); + + if (!do_redraw) + { + widget->disableDrawing(); + } + widgetX = (widget->getX() - thisX) + dx; widgetY = (widget->getY() - thisY) + dy; widget->moveTo(widgetX, widgetY); + + if (!do_redraw && oldstate) + { + widget->enableDrawing(); + } } } diff --git a/apps/NxWidgets/Kconfig b/apps/NxWidgets/Kconfig index 59d8856bc..656399199 100644 --- a/apps/NxWidgets/Kconfig +++ b/apps/NxWidgets/Kconfig @@ -13,6 +13,18 @@ config NXWIDGETS if NXWIDGETS comment "NX Server/Device Configuration" +config NXWIDGETS_FLICKERFREE + bool "Enable Flicker Reduction Logic" + default y if NX_LCDDRIVER + default n if !NX_LCDDRIVER + ---help--- + Because of their performance an in the manner in which they are + updated, LCDs may be prone to "flicker" in the displays when Widgets + are updated. Often more complex (and slower) options are availble + to reduce the flicker. Enabling this option will enabled those + lower-performance flicker-reductions measures where-ever thay may + be available. + config NXWIDGETS_DEVNO int "LCD Device Number" default 0 @@ -96,10 +108,20 @@ config NXWIDGETS_SIZEOFCHAR comment "NXWidget Default Values" +config NXWIDGETS_SYSTEM_CUSTOM_FONTID + bool "Use a Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXFONT_DEFAULT). + +if NXWIDGETS_SYSTEM_CUSTOM_FONTID config NXWIDGETS_DEFAULT_FONTID int "Default Font ID" + default 0 ---help--- - Default font ID. Default: NXFONT_DEFAULT + Use this default NxWidgets font ID instead of the system font ID + (NXFONT_DEFAULT). Default: 0 +endif config NXWIDGETS_TNXARRAY_INITIALSIZE int "Initial Size of Dynamic Arrays" @@ -113,53 +135,88 @@ config NXWIDGETS_TNXARRAY_SIZEINCREMENT ---help--- Default dynamic array realloctino increment (in entries). Default: 8 +config NXWIDGETS_CUSTOM_FILLCOLORS + bool "Custom Default Fill Colors" + default n + ---help--- + Select custom default colors for the widget background. If defined, + the hexadecimal values for all filled colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWIDGETS_CUSTOM_FILLCOLORS config NXWIDGETS_DEFAULT_BACKGROUNDCOLOR - hex "Normal Background Color" + hex "Default Normal Background Color" ---help--- Normal background color. Default: RGB(148,189,215) config NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR - hex "Selected Background Color" + hex "Default Selected Background Color" ---help--- Default selected background color. Default: RGB(206,227,241) +config NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR + hex "Default Highlight Color" + ---help--- + Highlight color. Currently this color is only used in clist + boxes, progress bars, and slider grips. Default: RGB(192,192,192) +endif + +config NXWIDGETS_CUSTOM_EDGECOLORS + bool "Custom Default Edge Colors" + default n + ---help--- + Select custom default colors for the widget edges. If defined, + then hexadecimal values for all edge colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. + +if NXWIDGETS_CUSTOM_EDGECOLORS config NXWIDGETS_DEFAULT_SHINEEDGECOLOR - hex "Shiny Edge Color" + hex "Default Shiny Edge Color" ---help--- Shiny side boarder color. Default: RGB(248,248,248) config NXWIDGETS_DEFAULT_SHADOWEDGECOLOR - hex "Shadow Edge Color" + hex "Default Shadow Edge Color" ---help--- Shadowed side border color. Default: RGB(35,58,73) +endif -config NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR - hex "Highlight Color" +config NXWIDGETS_CUSTOM_TEXTCOLORS + bool "Custom Default Text colors" + default n ---help--- - Highlight color. Default: RGB(192,192,192) + Select custom colors for the widget text. If defined, then + hexadecimal values for all text colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. +if NXWIDGETS_CUSTOM_TEXTCOLORS config NXWIDGETS_DEFAULT_DISABLEDTEXTCOLOR - hex "Disabled Text Color" + hex "Default Disabled Text Color" ---help--- Text color on a disabled widget: Default: RGB(192,192,192) config NXWIDGETS_DEFAULT_ENABLEDTEXTCOLOR - hex "Enabled Text Color" + hex "Default Enabled Text Color" ---help--- Text color on a enabled widget. Default: RGB(248,248,248) config NXWIDGETS_DEFAULT_SELECTEDTEXTCOLOR - hex "Selected Text Color" + hex "Default Selected Text Color" ---help--- Text color on a selected widget. Default: RGB(0,0,0) config NXWIDGETS_DEFAULT_FONTCOLOR - hex "Default Font Color" + hex "Default Default Font Color" ---help--- Default font color. Default: RGB(255,255,255) +endif config NXWIDGETS_TRANSPARENT_COLOR hex "Transparent Color" + default 0x0 ---help--- Transparent color. Default: RGB(0,0,0) @@ -220,10 +277,20 @@ config NXWM if NXWM comment "General settings" +config NXWM_SYSTEM_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXFONT_DEFAULT). + +if NXWM_SYSTEM_CUSTOM_FONTID config NXWM_DEFAULT_FONTID int "Font ID" + default 0 ---help--- - The NxWM default font ID. Default: NXFONT_DEFAULT + Use this NxWM default font ID instead of the system font ID + (NXFONT_DEFAULT). Default: 0 +endif config NXWM_UNITTEST bool "NxWM Unit Test" @@ -233,6 +300,16 @@ config NXWM_UNITTEST comment "Color configuration" +config NXWM_CUSTOM_FILLCOLORS + bool "Custom Default Fill Colors" + default n + ---help--- + Select custom default colors for the widget background. If defined, + the hexadecimal values for all filled colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWM_CUSTOM_FILLCOLORS config NXWM_DEFAULT_BACKGROUNDCOLOR hex "Background Color" ---help--- @@ -242,7 +319,18 @@ config NXWM_DEFAULT_SELECTEDBACKGROUNDCOLOR hex "Normal Background Color" ---help--- Select background color. Default: RGB(206,227,241) +endif +config NXWM_CUSTOM_EDGECOLORS + bool "Custom Default Edge Colors" + default n + ---help--- + Select custom default colors for the widget edges. If defined, + then hexadecimal values for all edge colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. + +if NXWM_CUSTOM_EDGECOLORS config NXWM_DEFAULT_SHINEEDGECOLOR hex "Shiny Edge Color" ---help--- @@ -252,7 +340,18 @@ config NXWM_DEFAULT_SHADOWEDGECOLOR hex "Shadow Edge Color" ---help--- Color of the shadowed edge of a border. Default: RGB(0,0,0) +endif + +config NXWM_CUSTOM_TEXTCOLORS + bool "Custom Default Text colors" + default n + ---help--- + Select custom colors for the widget text. If defined, then + hexadecimal values for all text colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n. +if NXWM_CUSTOM_TEXTCOLORS config NXWM_DEFAULT_FONTCOLOR hex "Default Font Color" ---help--- @@ -260,8 +359,10 @@ config NXWM_DEFAULT_FONTCOLOR config NXWM_TRANSPARENT_COLOR hex "Transparent Color" + default 0x0 ---help--- The "transparent" color. Default: RGB(0,0,0) +endif comment "Horizontal and vertical spacing of icons in the task bar" @@ -303,27 +404,48 @@ config NXWM_TASKBAR_RIGHT endchoice +config NXWM_CUSTOM_TASKBAR_WIDTH + bool "Use Custom Taskbar width" + default n + ---help--- + Set to override the default taskbar thickness (either vertical or + horizontal). The default depends on the selected horizontal or + vertical spacing. Default: 25 + 2*spacing + +if NXWM_CUSTOM_TASKBAR_WIDTH config NXWM_TASKBAR_WIDTH int "Taskbar Width" + default 29 ---help--- - Task bar thickness (either vertical or horizontal). Default: 25 + 2*spacing + Task bar thickness (either vertical or horizontal). Default: 25 + 2*2 +endif config NXWM_DISABLE_MINIMIZE bool "Disable Minimize Button" default n ---help--- - If the "desktop" is empty, users have no need to minimize any windows. If the buttons - are small, it's easy to hit minimize button accidentally when trying to close an - application. + If the "desktop" is empty, users have no need to minimize any + windows. If the buttons are small, it's easy to hit minimize + button accidentally when trying to close an application. comment "Tool Bar Configuration" +config NXWM_CUSTOM_TOOLBAR_HEIGHT + bool "Use Custom Toolbar Height" + default n + ---help--- + Set to override the default tooldar height The default depends on + the selected horizontal or vertical spacing. Default: 21 + 2*spacing + +if NXWM_CUSTOM_TOOLBAR_HEIGHT config NXWM_TOOLBAR_HEIGHT int "Toolbar Height" + default 25 ---help--- The height of the tool bar in each application window. At present, all icons are 21 pixels in height and, hence, require a task bar of - at least that size. + at least that size. Default: 21 + 2*2 +endif comment "Background Image" @@ -357,10 +479,19 @@ config NXWM_STARTWINDOW_HSPACING ---help--- Horizontal spacing. Default: 4 rows +config NXWM_CUSTOM_STARTWINDOW_ICON + bool "Custom Start Window Icon" + default n + ---help--- + Select to override the default Start Window Icon: NxWM::g_playBitmap + +if NXWM_CUSTOM_STARTWINDOW_ICON config NXWM_STARTWINDOW_ICON string "StartWindow Icon" + default "NxWM::g_playBitmap" ---help--- The glyph to use as the start window icon. Default: NxWM::g_playBitmap +endif config NXWM_STARTWINDOW_MQNAME string "Message Queue Name" @@ -417,6 +548,16 @@ config NXWM_NXCONSOLE_STACKSIZE The stack size to use when starting the NxConsole task. Default: 2048 bytes. +config NXWM_NXCONSOLE_CUSTOM_COLORS + bool "Custom NxConsole Colors" + default n + ---help--- + Select custom default colors for the NxConsole window. If defined, + the hexadecimal values for all NxConsole colors must be provided + (there are no default colors because the hexadecimal representation + of the default colors depend on the pixel depth). Default: n + +if NXWM_NXCONSOLE_CUSTOM_COLORS config NXWM_NXCONSOLE_WCOLOR hex "NxConsole Background Color" ---help--- @@ -428,17 +569,36 @@ config NXWM_NXCONSOLE_FONTCOLOR ---help--- The color of the fonts to use in the NxConsole window. Default: RGB(0,0,0) +endif +config NXWM_NXCONSOLE_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXWM_DEFAULT_FONTID). + +if NXWM_NXCONSOLE_CUSTOM_FONTID config NXWM_NXCONSOLE_FONTID int "NxConsole Font ID" + default 0 ---help--- - The ID of the font to use in the NxConsole window. Default: - NXWM_DEFAULT_FONTID + Use this default font ID in the NxConsole window instead of the + NxWM font ID (NXWM_DEFAULT_FONTID). Default: 0 +endif +config NXWM_CUSTOM_NXCONSOLE_ICON + bool "Custom NxConsole Icon" + default n + ---help--- + Select to override the default NxConsole Window Icon: NxWM::g_cmdBitmap + +if NXWM_CUSTOM_NXCONSOLE_ICON config NXWM_NXCONSOLE_ICON string "NxConsole Icon" + default "NxWM::g_cmdBitmap" ---help--- The glyph to use as the NxConsole icon. Default: NxWM::g_cmdBitmap +endif config NXWM_TOUCHSCREEN bool "Touchscreen Support" @@ -478,6 +638,7 @@ config NXWM_TOUCHSCREEN_LISTENERPRIO config NXWM_TOUCHSCREEN_LISTENERSTACK int "Touchscreen Listener Task Stack Size" + default 1024 ---help--- Touchscreen listener thread stack size. Default 1024 @@ -527,6 +688,17 @@ endif comment "Calibration display settings" +config NXWM_CALIBRATION_CUSTOM_COLORS + bool "Custom Calibration Colors" + default n + ---help--- + Select custom default colors for the calibration window. If + defined, the hexadecimal values for all calibration window + colors must be provided (there are no default colors because + the hexadecimal representation of the default colors depend + on the pixel depth). Default: n + +if NXWM_CALIBRATION_CUSTOM_COLORS config NXWM_CALIBRATION_BACKGROUNDCOLOR hex "Background Color" ---help--- @@ -550,12 +722,23 @@ config NXWM_CALIBRATION_TOUCHEDCOLOR ---help--- The color of the circle in the touchscreen calibration display after the touch is recorder. Default: RGB(255, 255, 96) (very light yellow) +endif + +config NXWM_CUSTOM_CALIBRATION_ICON + bool "Custom Calibration Icon" + default n + ---help--- + Select to override the default Calibration Window Icon: + NxWM::g_calibrationBitmap +if NXWM_CUSTOM_CALIBRATION_ICON config NXWM_CALIBRATION_ICON string "Callibration Icon" + default "NxWM::g_calibrationBitmap" ---help--- The ICON to use for the touchscreen calibration application. Default: NxWM::g_calibrationBitmap +endif config NXWM_CALIBRATION_SIGNO int "Calibration Signal Number" @@ -576,23 +759,55 @@ config NXWM_CALIBRATION_LISTENERSTACK ---help--- Calibration listener thread stack size. Default 2048 -comment "Calibration display settings" +comment "Hex Calculator display settings" +config NXWM_HEXCALCULATOR_CUSTOM_COLORS + bool "Custom Hex Calculator Colors" + default n + ---help--- + Select custom default colors for the Hex Calcualtor window. If + defined, the hexadecimal values for all hex calculator colors + must be provided (there are no default colors because the + hexadecimal representation of the default colors depend on the + pixel depth). Default: n + +if NXWM_HEXCALCULATOR_CUSTOM_COLORS config NXWM_HEXCALCULATOR_BACKGROUNDCOLOR hex "Calculator Background Color" ---help--- The background color of the calculator display. Default: Same as NXWM_DEFAULT_BACKGROUNDCOLOR +endif +config NXWM_CUSTOM_HEXCALCULATOR_ICON + bool "Custom Hex Calculator Icon" + default n + ---help--- + Select to override the default Hex Calculator Window Icon: + NxWM::g_calculatorBitmap + +if NXWM_CUSTOM_HEXCALCULATOR_ICON config NXWM_HEXCALCULATOR_ICON string "Calculator Icon" + default "NxWM::g_calculatorBitmap" ---help--- The ICON to use for the hex calculator application. Default: - NxWM::g_calculatorBitmap + "NxWM::g_calculatorBitmap" +endif +config NXWM_HEXCALCULATOR_CUSTOM_FONTID + bool "Use Custom Default Font" + default n + ---help--- + Set to override the system default font id (NXWM_DEFAULT_FONTID). + +if NXWM_HEXCALCULATOR_CUSTOM_FONTID config NXWM_HEXCALCULATOR_FONTID int "Calculator Font ID" + default 0 ---help--- - The font used with the calculator. Default: NXWM_DEFAULT_FONTID + Use this default font ID in the calculator window instead of the + NxWM font ID (NXWM_DEFAULT_FONTID). Default: 0 +endif endif diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index ed1cf39dc..c4a06af5e 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3801,3 +3801,10 @@ to find executables using a relative path. 6.25 2013-xx-xx Gregory Nutt + + * graphics/: Adds 5x8 monospace font. This tiny font is useful for graph + labels and for small bitmapped display. Contributed by Petteri + Aimonen. + * configs/stm3220g-eval/nxwm: Converted to use the kconfig-fronteds + configuration tool. + diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 5d9d3af3b..f48994bab 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -373,7 +373,7 @@

-

  • May be built either as an open, flat embedded RTOS or as a separtely built, secure micro-kernel with a system call interface.
    • +
  • May be built either as an open, flat embedded RTOS or as a separately built, secure micro-kernel with a system call interface.

    • diff --git a/nuttx/TODO b/nuttx/TODO index 6c28bfd43..6162431dc 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated November 25, 2012) +NuttX TODO List (Last updated December 20, 2012) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -15,7 +15,7 @@ nuttx/ (6) Binary loaders (binfmt/) (17) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) - (11) Libraries (libc/, ) + (12) Libraries (libc/, ) (9) File system/Generic drivers (fs/, drivers/) (5) Graphics subystem (graphics/) (1) Pascal add-on (pcode/) @@ -637,6 +637,15 @@ o USB (drivers/usbdev, drivers/usbhost) o Libraries (libc/) ^^^^^^^^^^^^^^^^^ + Title: SIGNED time_t + Description: The NuttX time_t is type uint32_t. I think this is consistent + with all standards and with normal usage of time_t. However, + according to Wikipedia, time_t is usually implemented as a + signed 32-bit value. + Status: Open + Priority: Very low unless there is some compelling issue that I do not + know about. + Title: ENVIRON Description: The definition of environ in stdlib.h is bogus and will not work as it should. This is because the underlying diff --git a/nuttx/configs/shenzhou/nxwm/defconfig b/nuttx/configs/shenzhou/nxwm/defconfig index 86d17c3ee..0f100ed5e 100644 --- a/nuttx/configs/shenzhou/nxwm/defconfig +++ b/nuttx/configs/shenzhou/nxwm/defconfig @@ -8,6 +8,14 @@ CONFIG_NUTTX_NEWCONFIG=y # Build Setup # # CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set # # Build Configuration @@ -28,6 +36,7 @@ CONFIG_INTELHEX_BINARY=y # # CONFIG_ARCH_STDBOOL_H is not set # CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set # CONFIG_ARCH_STDARG_H is not set # @@ -51,6 +60,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" + +# +# ARM Options +# # CONFIG_ARCH_CHIP_C5471 is not set # CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set @@ -68,11 +81,23 @@ CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set -CONFIG_ARCH_IRQPRIO=y CONFIG_BOARD_LOOPSPERMSEC=5483 # CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # CONFIG_SERIAL_TERMIOS is not set # CONFIG_NET_MULTICAST is not set @@ -83,8 +108,14 @@ CONFIG_BOARD_LOOPSPERMSEC=5483 # CONFIG_ARCH_CHIP_STM32F100CB is not set # CONFIG_ARCH_CHIP_STM32F100R8 is not set # CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set # CONFIG_ARCH_CHIP_STM32F100V8 is not set # CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set # CONFIG_ARCH_CHIP_STM32F103RET6 is not set # CONFIG_ARCH_CHIP_STM32F103VCT6 is not set # CONFIG_ARCH_CHIP_STM32F103VET6 is not set @@ -103,13 +134,6 @@ CONFIG_ARCH_CHIP_STM32F107VC=y # CONFIG_ARCH_CHIP_STM32F407IG is not set CONFIG_STM32_STM32F10XX=y CONFIG_STM32_CONNECTIVITYLINE=y -CONFIG_STM32_CODESOURCERYW=y -# CONFIG_STM32_CODESOURCERYL is not set -# CONFIG_STM32_ATOLLIC_LITE is not set -# CONFIG_STM32_ATOLLIC_PRO is not set -# CONFIG_STM32_DEVKITARM is not set -# CONFIG_STM32_RAISONANCE is not set -# CONFIG_STM32_BUILDROOT is not set # CONFIG_STM32_DFU is not set # @@ -118,11 +142,11 @@ CONFIG_STM32_CODESOURCERYW=y # CONFIG_STM32_ADC1 is not set # CONFIG_STM32_ADC2 is not set # CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set # CONFIG_STM32_CRC is not set # CONFIG_STM32_DMA1 is not set # CONFIG_STM32_DMA2 is not set -# CONFIG_STM32_BKP is not set -# CONFIG_STM32_CAN1 is not set # CONFIG_STM32_DAC1 is not set # CONFIG_STM32_DAC2 is not set CONFIG_STM32_ETHMAC=y @@ -153,9 +177,9 @@ CONFIG_STM32_SPI=y # # Alternate Pin Mapping # -CONFIG_STM32_USART2_REMAP=y -CONFIG_STM32_SPI3_REMAP=y CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_SPI3_REMAP=y +CONFIG_STM32_USART2_REMAP=y # CONFIG_STM32_JTAG_DISABLE is not set CONFIG_STM32_JTAG_FULL_ENABLE=y # CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set @@ -163,6 +187,11 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y # CONFIG_STM32_FORCEPOWER is not set # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# +# U[S]ART Configuration +# +# CONFIG_USART2_RS485 is not set + # # SPI Configuration # @@ -173,6 +202,7 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y # Ethernet MAC configuration # CONFIG_STM32_PHYADDR=0 +# CONFIG_STM32_PHYINIT is not set # CONFIG_STM32_MII is not set CONFIG_STM32_AUTONEG=y CONFIG_STM32_PHYSR=17 @@ -196,7 +226,11 @@ CONFIG_STM32_RMII_MCO=y # # CONFIG_ARCH_NOINTC is not set # CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # # Board Settings @@ -218,6 +252,7 @@ CONFIG_BOOT_RUNFROMFLASH=y # # Board Selection # +# CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set CONFIG_ARCH_BOARD_SHENZHOU=y # CONFIG_ARCH_BOARD_CUSTOM is not set @@ -309,7 +344,6 @@ CONFIG_PREALLOC_TIMERS=4 # # Stack and heap information # -# CONFIG_CUSTOM_STACK is not set CONFIG_IDLETHREAD_STACKSIZE=1024 CONFIG_USERMAIN_STACKSIZE=1024 CONFIG_PTHREAD_STACK_MIN=256 @@ -351,6 +385,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_P14201 is not set # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_UG2864AMBAG01 is not set CONFIG_LCD_SSD1289=y CONFIG_SSD1289_PROFILE1=y # CONFIG_SSD1289_PROFILE2 is not set @@ -544,6 +579,16 @@ CONFIG_NX_MXCLIENTMSGS=16 CONFIG_MM_REGIONS=1 # CONFIG_GRAN is not set +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + # # Library Routines # @@ -551,6 +596,7 @@ CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_EOL_IS_CR is not set @@ -563,10 +609,20 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_CXX_NEWLONG is not set +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + # # Application Configuration # @@ -579,260 +635,59 @@ CONFIG_NAMEDAPP=y # # Examples # - -# -# ADC Example -# -# CONFIG_EXAMPLES_ADC is not set - -# -# Buttons Example -# # CONFIG_EXAMPLES_BUTTONS is not set - -# -# CAN Example -# # CONFIG_EXAMPLES_CAN is not set - -# -# USB CDC/ACM Class Driver Example -# # CONFIG_EXAMPLES_CDCACM is not set - -# -# USB composite Class Driver Example -# # CONFIG_EXAMPLES_COMPOSITE is not set - -# -# DHCP Server Example -# +# CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set - -# -# FTP Client Example -# +# CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set - -# -# FTP Server Example -# # CONFIG_EXAMPLES_FTPD is not set - -# -# "Hello, World!" Example -# # CONFIG_EXAMPLES_HELLO is not set - -# -# "Hello, World!" C++ Example -# # CONFIG_EXAMPLES_HELLOXX is not set - -# -# USB HID Keyboard Example -# +# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set - -# -# IGMP Example -# +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set - -# -# LCD Read/Write Example -# # CONFIG_EXAMPLES_LCDRW is not set - -# -# Memory Management Example -# # CONFIG_EXAMPLES_MM is not set - -# -# File System Mount Example -# # CONFIG_EXAMPLES_MOUNT is not set - -# -# FreeModBus Example -# # CONFIG_EXAMPLES_MODBUS is not set - -# -# Network Test Example -# # CONFIG_EXAMPLES_NETTEST is not set - -# -# NuttShell (NSH) Example -# # CONFIG_EXAMPLES_NSH is not set - -# -# NULL Example -# # CONFIG_EXAMPLES_NULL is not set - -# -# NX Graphics Example -# # CONFIG_EXAMPLES_NX is not set - -# -# NxConsole Example -# # CONFIG_EXAMPLES_NXCONSOLE is not set - -# -# NXFFS File System Example -# # CONFIG_EXAMPLES_NXFFS is not set - -# -# NXFLAT Example -# # CONFIG_EXAMPLES_NXFLAT is not set - -# -# NX Graphics "Hello, World!" Example -# # CONFIG_EXAMPLES_NXHELLO is not set - -# -# NX Graphics image Example -# # CONFIG_EXAMPLES_NXIMAGE is not set - -# -# NX Graphics lines Example -# # CONFIG_EXAMPLES_NXLINES is not set - -# -# NX Graphics Text Example -# # CONFIG_EXAMPLES_NXTEXT is not set - -# -# OS Test Example -# # CONFIG_EXAMPLES_OSTEST is not set - -# -# Pascal "Hello, World!"example -# # CONFIG_EXAMPLES_PASHELLO is not set - -# -# Pipe Example -# # CONFIG_EXAMPLES_PIPE is not set - -# -# Poll Example -# # CONFIG_EXAMPLES_POLL is not set - -# -# Pulse Width Modulation (PWM) Example -# - -# -# Quadrature Encoder Example -# # CONFIG_EXAMPLES_QENCODER is not set - -# -# RGMP Example -# # CONFIG_EXAMPLES_RGMP is not set - -# -# ROMFS Example -# # CONFIG_EXAMPLES_ROMFS is not set - -# -# sendmail Example -# # CONFIG_EXAMPLES_SENDMAIL is not set - -# -# Serial Loopback Example -# # CONFIG_EXAMPLES_SERLOOP is not set - -# -# Telnet Daemon Example -# # CONFIG_EXAMPLES_TELNETD is not set - -# -# THTTPD Web Server Example -# # CONFIG_EXAMPLES_THTTPD is not set - -# -# TIFF Generation Example -# # CONFIG_EXAMPLES_TIFF is not set - -# -# Touchscreen Example -# # CONFIG_EXAMPLES_TOUCHSCREEN is not set - -# -# UDP Example -# # CONFIG_EXAMPLES_UDP is not set - -# -# UDP Discovery Daemon Example -# # CONFIG_EXAMPLES_DISCOVER is not set - -# -# uIP Web Server Example -# # CONFIG_EXAMPLES_UIP is not set - -# -# USB Serial Test Example -# # CONFIG_EXAMPLES_USBSERIAL is not set - -# -# USB Mass Storage Class Example -# # CONFIG_EXAMPLES_USBMSC is not set - -# -# USB Serial Terminal Example -# # CONFIG_EXAMPLES_USBTERM is not set - -# -# Watchdog timer Example -# # CONFIG_EXAMPLES_WATCHDOG is not set - -# -# wget Example -# # CONFIG_EXAMPLES_WGET is not set - -# -# WLAN Example -# # CONFIG_EXAMPLES_WLAN is not set -# -# XML RPC Example -# - # # Interpreters # @@ -850,76 +705,24 @@ CONFIG_NAMEDAPP=y # # Networking Utilities # - -# -# DHCP client -# +# CONFIG_NETUTILS_CODECS is not set # CONFIG_NETUTILS_DHCPC is not set - -# -# DHCP server -# # CONFIG_NETUTILS_DHCPD is not set - -# -# FTP client -# # CONFIG_NETUTILS_FTPC is not set - -# -# FTP server -# # CONFIG_NETUTILS_FTPD is not set - -# -# Name resolution -# +# CONFIG_NETUTILS_JSON is not set CONFIG_NETUTILS_RESOLV=y CONFIG_NET_RESOLV_ENTRIES=4 - -# -# SMTP -# +CONFIG_NET_RESOLV_MAXRESPONSE=96 # CONFIG_NETUTILS_SMTP is not set - -# -# TFTP client -# CONFIG_NETUTILS_TELNETD=y - -# -# TFTP client -# CONFIG_NETUTILS_TFTPC=y - -# -# THTTPD web server -# # CONFIG_NETUTILS_THTTPD is not set - -# -# uIP support library -# CONFIG_NETUTILS_UIPLIB=y - -# -# uIP web client -# CONFIG_NETUTILS_WEBCLIENT=y - -# -# uIP web server -# +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" # CONFIG_NETUTILS_WEBSERVER is not set - -# -# UDP Discovery Utility -# # CONFIG_NETUTILS_DISCOVER is not set - -# -# XML-RPC library -# # CONFIG_NETUTILS_XMLRPC is not set # @@ -950,6 +753,7 @@ CONFIG_NSH_LIBRARY=y # CONFIG_NSH_DISABLE_FREE is not set # CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOSETUP is not set @@ -978,6 +782,7 @@ CONFIG_NSH_LIBRARY=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 @@ -993,10 +798,12 @@ CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=1596 CONFIG_NSH_TELNETD_CLIENTPRIO=100 CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=1596 CONFIG_NSH_IOBUFFER_SIZE=512 +# CONFIG_NSH_TELNET_LOGIN is not set CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 CONFIG_NSH_NOMAC=y +CONFIG_NSH_MAX_ROUNDTRIP=20 # # NxWidgets/NxWM @@ -1006,6 +813,7 @@ CONFIG_NXWIDGETS=y # # NX Server/Device Configuration # +CONFIG_NXWIDGETS_FLICKERFREE=y CONFIG_NXWIDGETS_DEVNO=0 CONFIG_NXWIDGETS_VPLANE=0 CONFIG_NXWIDGETS_SERVERPRIO=51 @@ -1025,19 +833,13 @@ CONFIG_NXWIDGETS_SIZEOFCHAR=1 # # NXWidget Default Values # -CONFIG_NXWIDGETS_DEFAULT_FONTID= +# CONFIG_NXWIDGETS_SYSTEM_CUSTOM_FONTID is not set CONFIG_NXWIDGETS_TNXARRAY_INITIALSIZE=16 CONFIG_NXWIDGETS_TNXARRAY_SIZEINCREMENT=8 -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR= -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR= -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR= -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR= -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR= -CONFIG_NXWIDGETS_DEFAULT_DISABLEDTEXTCOLOR= -CONFIG_NXWIDGETS_DEFAULT_ENABLEDTEXTCOLOR= -CONFIG_NXWIDGETS_DEFAULT_SELECTEDTEXTCOLOR= -CONFIG_NXWIDGETS_DEFAULT_FONTCOLOR= -CONFIG_NXWIDGETS_TRANSPARENT_COLOR= +# CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS is not set +# CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS is not set +# CONFIG_NXWIDGETS_CUSTOM_TEXTCOLORS is not set +CONFIG_NXWIDGETS_TRANSPARENT_COLOR=0x0 # # Keypad behavior @@ -1053,18 +855,15 @@ CONFIG_NXWM=y # # General settings # -CONFIG_NXWM_DEFAULT_FONTID= +# CONFIG_NXWM_SYSTEM_CUSTOM_FONTID is not set CONFIG_NXWM_UNITTEST=y # # Color configuration # -CONFIG_NXWM_DEFAULT_BACKGROUNDCOLOR= -CONFIG_NXWM_DEFAULT_SELECTEDBACKGROUNDCOLOR= -CONFIG_NXWM_DEFAULT_SHINEEDGECOLOR= -CONFIG_NXWM_DEFAULT_SHADOWEDGECOLOR= -CONFIG_NXWM_DEFAULT_FONTCOLOR= -CONFIG_NXWM_TRANSPARENT_COLOR= +# CONFIG_NXWM_CUSTOM_FILLCOLORS is not set +# CONFIG_NXWM_CUSTOM_EDGECOLORS is not set +# CONFIG_NXWM_CUSTOM_TEXTCOLORS is not set # # Horizontal and vertical spacing of icons in the task bar @@ -1075,16 +874,18 @@ CONFIG_NXWM_TASKBAR_HSPACING=2 # CONFIG_NXWM_TASKBAR_BOTTOM is not set CONFIG_NXWM_TASKBAR_LEFT=y # CONFIG_NXWM_TASKBAR_RIGHT is not set -CONFIG_NXWM_TASKBAR_WIDTH= +# CONFIG_NXWM_CUSTOM_TASKBAR_WIDTH is not set +# CONFIG_NXWM_DISABLE_MINIMIZE is not set # # Tool Bar Configuration # -CONFIG_NXWM_TOOLBAR_HEIGHT= +# CONFIG_NXWM_CUSTOM_TOOLBAR_HEIGHT is not set # # Background Image # +# CONFIG_NXWM_DISABLE_BACKGROUND_IMAGE is not set CONFIG_NXWM_BACKGROUND_IMAGE="" # @@ -1096,7 +897,7 @@ CONFIG_NXWM_BACKGROUND_IMAGE="" # CONFIG_NXWM_STARTWINDOW_VSPACING=4 CONFIG_NXWM_STARTWINDOW_HSPACING=4 -CONFIG_NXWM_STARTWINDOW_ICON="" +# CONFIG_NXWM_CUSTOM_STARTWINDOW_ICON is not set CONFIG_NXWM_STARTWINDOW_MQNAME="/dev/nxwm" CONFIG_NXWM_STARTWINDOW_MXMSGS=32 CONFIG_NXWM_STARTWINDOW_MXMPRIO=42 @@ -1108,10 +909,9 @@ CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 # CONFIG_NXWM_NXCONSOLE_PRIO=50 CONFIG_NXWM_NXCONSOLE_STACKSIZE=1596 -CONFIG_NXWM_NXCONSOLE_WCOLOR= -CONFIG_NXWM_NXCONSOLE_FONTCOLOR= -CONFIG_NXWM_NXCONSOLE_FONTID= -CONFIG_NXWM_NXCONSOLE_ICON="" +# CONFIG_NXWM_NXCONSOLE_CUSTOM_COLORS is not set +# CONFIG_NXWM_NXCONSOLE_CUSTOM_FONTID is not set +# CONFIG_NXWM_CUSTOM_NXCONSOLE_ICON is not set CONFIG_NXWM_TOUCHSCREEN=y # @@ -1136,20 +936,18 @@ CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 # # Calibration display settings # -CONFIG_NXWM_CALIBRATION_BACKGROUNDCOLOR= -CONFIG_NXWM_CALIBRATION_LINECOLOR= -CONFIG_NXWM_CALIBRATION_CIRCLECOLOR= -CONFIG_NXWM_CALIBRATION_TOUCHEDCOLOR= -CONFIG_NXWM_CALIBRATION_ICON="" +# CONFIG_NXWM_CALIBRATION_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_CALIBRATION_ICON is not set CONFIG_NXWM_CALIBRATION_SIGNO=5 CONFIG_NXWM_CALIBRATION_LISTENERPRIO=50 CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024 # -# Calibration display settings +# Hex Calculator display settings # -CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR= -CONFIG_NXWM_HEXCALCULATOR_ICON="" +# CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_HEXCALCULATOR_ICON is not set +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # diff --git a/nuttx/configs/stm3220g-eval/README.txt b/nuttx/configs/stm3220g-eval/README.txt index 8695dbb89..e7bdd4de0 100644 --- a/nuttx/configs/stm3220g-eval/README.txt +++ b/nuttx/configs/stm3220g-eval/README.txt @@ -1077,6 +1077,21 @@ Where is one of the following: $ cd ~/nuttx-code/nuttx $ make + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. This configuration is currently set up to build under Cygwin on + a Windows machine using the CodeSourcery Windows toolchain. + That configuration can be easy changed as described in Note 1. + ostest: ------ This configuration directory, performs a simple OS test using diff --git a/nuttx/configs/stm3220g-eval/nxwm/appconfig b/nuttx/configs/stm3220g-eval/nxwm/appconfig deleted file mode 100644 index 4ebd8137c..000000000 --- a/nuttx/configs/stm3220g-eval/nxwm/appconfig +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# configs/stm3220g-eval/nxwm/appconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# The NSH Library -- NOTE: The NxWM unit test must be installed at -# apps/external in order to build this example. See -# NxWidgets/UnitTests/README.txt for additional information - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - -# Networking libraries. - -ifeq ($(CONFIG_NET),y) -CONFIGURED_APPS += netutils/uiplib -CONFIGURED_APPS += netutils/resolv -CONFIGURED_APPS += netutils/webclient -CONFIGURED_APPS += netutils/tftpc -ifeq ($(CONFIG_NSH_TELNET),y) -CONFIGURED_APPS += netutils/telnetd -endif -endif diff --git a/nuttx/configs/stm3220g-eval/nxwm/defconfig b/nuttx/configs/stm3220g-eval/nxwm/defconfig index 065fbb137..11e88f764 100644 --- a/nuttx/configs/stm3220g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3220g-eval/nxwm/defconfig @@ -1,371 +1,338 @@ -############################################################################ -# configs/stm3220g-eval/nxwm/defconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" -CONFIG_ARCH_ARM=y -CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_DRAM_SIZE=196608 -CONFIG_DRAM_START=0x20000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y # -# Identify toolchain and linker options +# Build Setup # -CONFIG_STM32_CODESOURCERYW=y -CONFIG_STM32_CODESOURCERYL=n -CONFIG_STM32_ATOLLIC_LITE=n -CONFIG_STM32_ATOLLIC_PRO=n -CONFIG_STM32_DEVKITARM=n -CONFIG_STM32_RAISONANCE=n -CONFIG_STM32_BUILDROOT=n +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set # -# JTAG Enable settings (by default JTAG-DP and SW-DP are disabled): +# Build Configuration # -CONFIG_STM32_DFU=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n -CONFIG_STM32_JTAG_SW_ENABLE=n +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set # -# On-board FSMC SRAM configuration +# Binary Output Formats # -CONFIG_STM32_FSMC_SRAM=n -CONFIG_HEAP2_BASE=0x64000000 -CONFIG_HEAP2_SIZE=2097152 - +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + # -# Individual subsystems can be enabled: +# Customize Header Files # -# AHB1: -CONFIG_STM32_CRC=n -CONFIG_STM32_BKPSRAM=n -CONFIG_STM32_DMA1=n -CONFIG_STM32_DMA2=n +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_BOARD_LOOPSPERMSEC=10926 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_NET_MULTICAST is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103RET6 is not set +# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set +# CONFIG_ARCH_CHIP_STM32F103VET6 is not set +# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set +# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +CONFIG_ARCH_CHIP_STM32F207IG=y +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +CONFIG_STM32_STM32F20XX=y +CONFIG_STM32_DFU=y + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set CONFIG_STM32_ETHMAC=y -CONFIG_STM32_OTGHS=n -# AHB2: -CONFIG_STM32_DCMI=n -CONFIG_STM32_CRYP=n -CONFIG_STM32_HASH=n -CONFIG_STM32_RNG=n -CONFIG_STM32_OTGFS=n -# AHB3: CONFIG_STM32_FSMC=y -# APB1: -CONFIG_STM32_TIM2=n -CONFIG_STM32_TIM3=n -CONFIG_STM32_TIM4=n -CONFIG_STM32_TIM5=n -CONFIG_STM32_TIM6=n -CONFIG_STM32_TIM7=n -CONFIG_STM32_TIM12=n -CONFIG_STM32_TIM13=n -CONFIG_STM32_TIM14=n -CONFIG_STM32_WWDG=n -CONFIG_STM32_IWDG=n -CONFIG_STM32_SPI2=n -CONFIG_STM32_SPI3=n -CONFIG_STM32_USART2=n -CONFIG_STM32_USART3=y -CONFIG_STM32_UART4=n -CONFIG_STM32_UART5=n +# CONFIG_STM32_HASH is not set CONFIG_STM32_I2C1=y -CONFIG_STM32_I2C2=n -CONFIG_STM32_I2C3=n -CONFIG_STM32_CAN1=n -CONFIG_STM32_CAN2=n -CONFIG_STM32_DAC=n +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set CONFIG_STM32_PWR=y -# APB2: -CONFIG_STM32_TIM1=n -CONFIG_STM32_TIM8=n -CONFIG_STM32_USART1=n -CONFIG_STM32_USART6=n -CONFIG_STM32_ADC1=n -CONFIG_STM32_ADC2=n -CONFIG_STM32_ADC3=n -CONFIG_STM32_SDIO=n -CONFIG_STM32_SPI1=n +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set CONFIG_STM32_SYSCFG=y -CONFIG_STM32_TIM9=n -CONFIG_STM32_TIM10=n -CONFIG_STM32_TIM11=n +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +# CONFIG_STM32_USART2 is not set +CONFIG_STM32_USART3=y +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_I2C=y # -# STM32F20xxx specific serial device driver settings +# Alternate Pin Mapping # -CONFIG_USART1_SERIAL_CONSOLE=n -CONFIG_USART2_SERIAL_CONSOLE=n -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_UART4_SERIAL_CONSOLE=n -CONFIG_UART5_SERIAL_CONSOLE=n - -CONFIG_USART1_TXBUFSIZE=128 -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_UART4_TXBUFSIZE=128 -CONFIG_UART5_TXBUFSIZE=128 - -CONFIG_USART1_RXBUFSIZE=128 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_UART4_RXBUFSIZE=128 -CONFIG_UART5_RXBUFSIZE=128 - -CONFIG_USART1_BAUD=115200 -CONFIG_USART2_BAUD=115200 -CONFIG_USART3_BAUD=115200 -CONFIG_UART4_BAUD=115200 -CONFIG_UART5_BAUD=115200 - -CONFIG_USART1_BITS=8 -CONFIG_USART2_BITS=8 -CONFIG_USART3_BITS=8 -CONFIG_UART4_BITS=8 -CONFIG_UART5_BITS=8 - -CONFIG_USART1_PARITY=0 -CONFIG_USART2_PARITY=0 -CONFIG_USART3_PARITY=0 -CONFIG_UART4_PARITY=0 -CONFIG_UART5_PARITY=0 +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set +# CONFIG_STM32_FSMC_SRAM is not set -CONFIG_USART1_2STOP=0 -CONFIG_USART2_2STOP=0 -CONFIG_USART3_2STOP=0 -CONFIG_UART4_2STOP=0 -CONFIG_UART5_2STOP=0 +# +# U[S]ART Configuration +# +# CONFIG_USART3_RS485 is not set # -# STM32F20xxx specific CAN device driver settings +# I2C Configuration # -CONFIG_CAN=n -CONFIG_CAN_EXTID=n -#CONFIG_CAN_FIFOSIZE -#CONFIG_CAN_NPENDINGRTR -CONFIG_CAN_LOOPBACK=n -CONFIG_CAN1_BAUD=700000 -CONFIG_CAN2_BAUD=700000 +# CONFIG_STM32_I2C_DYNTIMEO is not set +CONFIG_STM32_I2CTIMEOSEC=0 +CONFIG_STM32_I2CTIMEOMS=500 +CONFIG_STM32_I2CTIMEOTICKS=500 +# CONFIG_STM32_I2C_DUTY16_9 is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# STM32F20xxx Ethernet device driver settings +# Ethernet MAC configuration # CONFIG_STM32_PHYADDR=1 +# CONFIG_STM32_PHYINIT is not set CONFIG_STM32_MII=y CONFIG_STM32_MII_MCO1=y -CONFIG_STM32_MII_MCO2=n -CONFIG_STM32_RMII=n +# CONFIG_STM32_MII_MCO2 is not set +# CONFIG_STM32_MII_EXTCLK is not set CONFIG_STM32_AUTONEG=y -#CONFIG_STM32_ETHFD -#CONFIG_STM32_ETH100MBPS CONFIG_STM32_PHYSR=16 +# CONFIG_STM32_PHYSR_ALTCONFIG is not set CONFIG_STM32_PHYSR_SPEED=0x0002 CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_ETH_PTP=n -CONFIG_STM32_ETHMAC_REGDEBUG=n +# CONFIG_STM32_ETH_PTP is not set # -# I2C configuration +# USB Host Configuration # -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_I2C_TRANSFER=y -CONFIG_I2C_TRACE=n # -# ADC configuration +# Architecture Options # -# Enable ADC driver support. The STM3220G-EVAL has a 10 Kohm potentiometer -# RV1 connected to PF9 of STM32F207IGH6 on the board: TIM14_CH1/ SMC_CD/ADC3_IN7 +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set + # -CONFIG_ADC=n -#CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_TIM1_ADC3=y -CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=100 +# Board Settings +# +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=196608 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 # -# PWM configuration +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + # -# The STM3220G-Eval has no real on-board PWM devices, but the board can be configured to output -# a pulse train using several options (see board.h). Here the default setup is for TIM8, CH4. -# Don't forget to enable CONFIG_PWM and CONFIG_STM32_TIM8. +# Board Selection # -CONFIG_PWM=n -CONFIG_PWM_PULSECOUNT=y -CONFIG_STM32_TIM8_PWM=y -CONFIG_STM32_TIM8_CHANNEL=4 +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm3220g-eval" # -# General build options +# Common Board Options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=y -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=n +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # -# General OS setup +# Board-Specific Options # -CONFIG_USER_ENTRYPOINT="nxwm_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_FS=n -CONFIG_DEBUG_GRAPHICS=n -CONFIG_DEBUG_LCD=n -CONFIG_DEBUG_USB=n -CONFIG_DEBUG_NET=n -CONFIG_DEBUG_RTC=n -CONFIG_DEBUG_ANALOG=n -CONFIG_DEBUG_PWM=n -CONFIG_DEBUG_CAN=n -CONFIG_DEBUG_I2C=n -CONFIG_DEBUG_INPUT=n -CONFIG_DEBUG_DMA=n +CONFIG_LCD_RDSHIFT=5 +CONFIG_STM3220G_LCD=y +# CONFIG_CONFIG_STM32_ILI9320_DISABLE is not set +# CONFIG_CONFIG_STM32_ILI9325_DISABLE is not set -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=5 CONFIG_START_DAY=28 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 CONFIG_SIG_SIGWORK=4 +# CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y -CONFIG_SCHED_ATEXIT=n +# CONFIG_SCHED_ATEXIT is not set CONFIG_SCHED_ONEXIT=y - -# -# System Logging -# - -CONFIG_SYSLOG=n -CONFIG_RAMLOG=n -CONFIG_RAMLOG_CONSOLE=n -CONFIG_RAMLOG_SYSLOG=n -#CONFIG_RAMLOG_NPOLLWAITERS -#CONFIG_RAMLOG_CONSOLE_BUFSIZE - -# -# Settings for NXFLAT -# -CONFIG_NXFLAT=n -CONFIG_NXFLAT_DUMPBUFFER=n -CONFIG_SYMTAB_ORDEREDBYNAME=y - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n +CONFIG_SCHED_ONEXIT_MAX=1 +CONFIG_USER_ENTRYPOINT="nxwm_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set CONFIG_DISABLE_POLL=y -# -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - # # Sizes of configurable things (0 disables) # @@ -375,9 +342,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=12 CONFIG_NFILE_STREAMS=12 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=32 CONFIG_MQ_MAXMSGSIZE=48 CONFIG_MAX_WDOGPARMS=2 @@ -385,505 +349,681 @@ CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_TIMERS=4 # -# Framebuffer driver options -# -CONFIG_FB_CMAP=n -CONFIG_FB_HWCURSOR=n -CONFIG_FB_HWCURSORIMAGE=n -#CONFIG_FB_HWCURSORSIZE -#CONFIG_FB_TRANSPARENCY - -# -# Filesystem configuration +# Stack and heap information # -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # -# Maintain legacy build behavior (revisit) +# Device Drivers # - +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +CONFIG_I2C=y +# CONFIG_I2C_SLAVE is not set +CONFIG_I2C_TRANSFER=y +# CONFIG_I2C_WRITEREAD is not set +CONFIG_I2C_POLLED=y +# CONFIG_I2C_TRACE is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C_RESET is not set +# CONFIG_SPI is not set +CONFIG_RTC=y +CONFIG_RTC_DATETIME=y +# CONFIG_RTC_ALARM is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +CONFIG_INPUT=y +# CONFIG_INPUT_TSC2007 is not set +# CONFIG_INPUT_ADS7843E is not set +CONFIG_INPUT_STMPE811=y +# CONFIG_STMPE811_SPI is not set +CONFIG_STMPE811_I2C=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +# CONFIG_STMPE811_TSC_DISABLE is not set +# CONFIG_STMPE811_SWAPXY is not set +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_STMPE811_ADC_DISABLE=y +CONFIG_STMPE811_GPIO_DISABLE=y +CONFIG_STMPE811_TEMP_DISABLE=y +CONFIG_LCD=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_MAXPOWER=1 +# CONFIG_LCD_P14201 is not set +# CONFIG_LCD_NOKIA6100 is not set +# CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_UG2864AMBAG01 is not set +# CONFIG_LCD_SSD1289 is not set +CONFIG_LCD_LANDSCAPE=y +# CONFIG_LCD_PORTRAIT is not set +# CONFIG_LCD_RPORTRAIT is not set +# CONFIG_LCD_RLANDSCAPE is not set CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y +CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MTD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_NET_SLIP is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_USART3=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_USART3_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set # -# SPI-based MMC/SD driver +# USART3 Configuration # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USART3_BAUD=115200 +CONFIG_USART3_BITS=8 +CONFIG_USART3_PARITY=0 +CONFIG_USART3_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set # -# Block driver buffering +# System Logging Device Options # -CONFIG_FS_READAHEAD=n -CONFIG_FS_WRITEBUFFER=n # -# STM32 SDIO-based MMC/SD driver +# System Logging # -CONFIG_SDIO_DMA=n -#CONFIG_SDIO_PRI=128 -#CONFIG_SDIO_DMAPRIO -#CONFIG_SDIO_WIDTH_D1_ONLY -CONFIG_MMCSD_MULTIBLOCK_DISABLE=y -CONFIG_MMCSD_MMCSUPPORT=n -CONFIG_MMCSD_HAVECARDDETECT=n +# CONFIG_RAMLOG is not set # -# TCP/IP and UDP support via uIP +# Networking Support # CONFIG_NET=y -CONFIG_NET_NOINTS=n +CONFIG_ARCH_HAVE_PHY=y +CONFIG_PHY_KS8721=y +# CONFIG_PHY_DP83848C is not set +# CONFIG_PHY_LAN8720 is not set +# CONFIG_PHY_DM9161 is not set +# CONFIG_NET_NOINTS is not set CONFIG_NET_MULTIBUFFER=y -CONFIG_NET_IPv6=n +# CONFIG_NET_IPv6 is not set CONFIG_NSOCKET_DESCRIPTORS=10 +CONFIG_NET_NACTIVESOCKETS=16 CONFIG_NET_SOCKOPTS=y CONFIG_NET_BUFSIZE=562 +# CONFIG_NET_TCPURGDATA is not set CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=40 -#CONFIG_NET_TCP_READAHEAD_BUFSIZE +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 +CONFIG_NET_TCP_RECVDELAY=0 CONFIG_NET_TCPBACKLOG=y -CONFIG_NET_MAX_LISTENPORTS=40 CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 +CONFIG_NET_UDP_CONNS=8 +# CONFIG_NET_BROADCAST is not set CONFIG_NET_ICMP=y CONFIG_NET_ICMP_PING=y -#CONFIG_NET_PINGADDRCONF=0 +# CONFIG_NET_PINGADDRCONF is not set +# CONFIG_NET_IGMP is not set CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -CONFIG_NET_BROADCAST=n -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_ARP_IPIN=n -CONFIG_NET_MULTICAST=n +CONFIG_NET_RECEIVE_WINDOW=562 +CONFIG_NET_ARPTAB_SIZE=16 +# CONFIG_NET_ARP_IPIN is not set # -# UIP Network Utilities +# File Systems # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 # -# FTP Server +# File system configuration # -CONFIG_FTPD_CMDBUFFERSIZE=2048 +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set # -# RTC Configuration +# System Logging # -CONFIG_RTC=y -CONFIG_RTC_DATETIME=y -CONFIG_RTC_HIRES=n -CONFIG_RTC_FREQUENCY=1 -CONFIG_RTC_ALARM=n +# CONFIG_SYSLOG is not set # -# Input device configuration +# Graphics Support # -CONFIG_INPUT=y -CONFIG_INPUT_TSC2007=n +CONFIG_NX=y +CONFIG_NX_LCDDRIVER=y +CONFIG_NX_NPLANES=1 +CONFIG_NX_WRITEONLY=y # -# STMPE811 input device configuration -# -# Prerequisites: CONFIG_INPUT=y -# Other settings that effect the driver: CONFIG_DISABLE_POLL +# Supported Pixel Depths # -CONFIG_INPUT_STMPE811=y -CONFIG_STMPE811_SPI=n -CONFIG_STMPE811_I2C=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -#CONFIG_STMPE811_NPOLLWAITERS -CONFIG_STMPE811_TSC_DISABLE=n -CONFIG_STMPE811_ADC_DISABLE=y -CONFIG_STMPE811_GPIO_DISABLE=y -CONFIG_STMPE811_GPIOINT_DISABLE=y -CONFIG_STMPE811_SWAPXY=n -CONFIG_STMPE811_TEMP_DISABLE=y -CONFIG_STMPE811_REGDEBUG=n -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 +CONFIG_NX_DISABLE_1BPP=y +CONFIG_NX_DISABLE_2BPP=y +CONFIG_NX_DISABLE_4BPP=y +CONFIG_NX_DISABLE_8BPP=y +# CONFIG_NX_DISABLE_16BPP is not set +CONFIG_NX_DISABLE_24BPP=y +CONFIG_NX_DISABLE_32BPP=y +# CONFIG_NX_PACKEDMSFIRST is not set # -# STM32 USB OTG FS Device Configuration +# Input Devices # -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 +CONFIG_NX_MOUSE=y +CONFIG_NX_KBD=y # -# STM32 USB OTG FS Host Configuration +# Framed Window Borders # -CONFIG_USBHOST=n -#CONFIG_STM32_OTGFS_RXFIFO_SIZE -#CONFIG_STM32_OTGFS_NPTXFIFO_SIZE -#CONFIG_STM32_OTGFS_PTXFIFO_SIZE -#CONFIG_STM32_OTGFS_DESCSIZE -CONFIG_STM32_OTGFS_SOFINTR=n -CONFIG_STM32_USBHOST_REGDEBUG=n -CONFIG_STM32_USBHOST_PKTDUMP=n +CONFIG_NXTK_BORDERWIDTH=4 +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +# CONFIG_NXTK_AUTORAISE is not set # -# USB Serial Device Configuration +# Font Selections # -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=3 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_NXFONTS_CHARBITS=7 +# CONFIG_NXFONT_SANS17X22 is not set +# CONFIG_NXFONT_SANS20X26 is not set +CONFIG_NXFONT_SANS23X27=y +# CONFIG_NXFONT_SANS22X29 is not set +# CONFIG_NXFONT_SANS28X37 is not set +# CONFIG_NXFONT_SANS39X48 is not set +# CONFIG_NXFONT_SANS17X23B is not set +# CONFIG_NXFONT_SANS20X27B is not set +CONFIG_NXFONT_SANS22X29B=y +# CONFIG_NXFONT_SANS28X37B is not set +# CONFIG_NXFONT_SANS40X49B is not set +# CONFIG_NXFONT_SERIF22X29 is not set +# CONFIG_NXFONT_SERIF29X37 is not set +# CONFIG_NXFONT_SERIF38X48 is not set +# CONFIG_NXFONT_SERIF22X28B is not set +# CONFIG_NXFONT_SERIF27X38B is not set +# CONFIG_NXFONT_SERIF38X49B is not set +CONFIG_NXCONSOLE=y # -# USB Storage Device Configuration +# NxConsole Output Text/Graphics Options # -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=2 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y +CONFIG_NXCONSOLE_BPP=16 +CONFIG_NXCONSOLE_CURSORCHAR=137 +CONFIG_NXCONSOLE_MXCHARS=325 +CONFIG_NXCONSOLE_CACHESIZE=32 +CONFIG_NXCONSOLE_LINESEPARATION=0 +# CONFIG_NXCONSOLE_NOWRAP is not set # -# Watchdog timer configuration +# NxConsole Input options # -CONFIG_WATCHDOG=n +CONFIG_NXCONSOLE_NXKBDIN=y +CONFIG_NXCONSOLE_KBDBUFSIZE=16 +CONFIG_NXCONSOLE_NPOLLWAITERS=4 # -# Graphics related configuration settings +# NX Multi-user only options # -CONFIG_NX=y CONFIG_NX_MULTIUSER=y -CONFIG_NX_NPLANES=1 -CONFIG_NX_DISABLE_1BPP=y -CONFIG_NX_DISABLE_2BPP=y -CONFIG_NX_DISABLE_4BPP=y -CONFIG_NX_DISABLE_8BPP=y -CONFIG_NX_DISABLE_16BPP=n -CONFIG_NX_DISABLE_24BPP=y -CONFIG_NX_DISABLE_32BPP=y -CONFIG_NX_PACKEDMSFIRST=n -CONFIG_NX_LCDDRIVER=y -CONFIG_LCD_MAXPOWER=1 -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_NX_MOUSE=y -CONFIG_NX_KBD=y -#CONFIG_NXTK_BORDERWIDTH=4 -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXTK_AUTORAISE=n -CONFIG_NXFONT_SANS17X22=n -CONFIG_NXFONT_SANS20X26=n -CONFIG_NXFONT_SANS22X29=n -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37=n -CONFIG_NXFONT_SANS17X23B=n -CONFIG_NXFONT_SANS20X27B=n -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS28X37B=n -CONFIG_NXFONT_SANS40X49B=n -CONFIG_NXFONT_SERIF22X29=n -CONFIG_NXFONT_SERIF29X37=n -CONFIG_NXFONT_SERIF38X48=n -CONFIG_NXFONT_SERIF22X28B=n -CONFIG_NXFONT_SERIF27X38B=n -CONFIG_NXFONT_SERIF38X49B=n -CONFIG_NXFONTS_CHARBITS=7 CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 # -# NxWidgets / NxWM +# Memory Management # -# Use all defaults except -# 1. 16 bits-per-pixel -# 2. Make the NxWidgets background color match the NxWM back color -# 3. Build in support for keyboard input in NxConsole -# 4. Taskbar on the left -# 5. We do have a touchscreen -# 6. We do want the NxWM keybard listener -# 7. Use a larger font with the calculator -# -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_SERVERSTACK=2048 -CONFIG_NXWIDGETS_LISTENERSTACK=2048 -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=MKRGB(148,189,215) -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=MKRGB(206,227,241) -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=MKRGB(35,58,73) +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set -CONFIG_NXCONSOLE_NXKBDIN=y +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_NXCONSOLE_STACKSIZE=2048 -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_UNITTEST=y -CONFIG_NXWM_TOUCHSCREEN=y -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +# +# Library Routines +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# NxConsole Configuration Settings: +# Basic CXX Support # -CONFIG_NXCONSOLE=y -CONFIG_NXCONSOLE_BPP=16 -CONFIG_NXCONSOLE_MXCHARS=325 -CONFIG_NXCONSOLE_CACHESIZE=32 +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library # +# CONFIG_UCLIBCXX is not set # -# STM3220G-EVAL LCD Hardware Configuration +# Application Configuration # -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_LANDSCAPE=y -CONFIG_LCD_RLANDSCAPE=n -CONFIG_LCD_PORTRAIT=n -CONFIG_LCD_RPORTRAIT=n # -# STM3220G-EVAL specific LCD settings +# Named Applications # -CONFIG_STM32_ILI9320_DISABLE=n -CONFIG_STM32_ILI9325_DISABLE=n +# CONFIG_NAMEDAPP is not set # -# Settings for examples/uip +# Examples # -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WGET is not set +# CONFIG_EXAMPLES_WLAN is not set # -# Settings for examples/nettest -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 +# Interpreters +# # -# Settings for examples/ostest +# Interpreters # -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set # -# Settings for apps/nshlib +# Network Utilities # -CONFIG_NSH_BUILTIN_APPS=n +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_RESOLV=y +CONFIG_NET_RESOLV_ENTRIES=4 +CONFIG_NET_RESOLV_MAXRESPONSE=96 +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +# CONFIG_NETUTILS_THTTPD is not set +CONFIG_NETUTILS_UIPLIB=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_DISCOVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_CONSOLE=y -#CONFIG_NSH_CONDEV="/dev/ttyS1" +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set CONFIG_NSH_TELNET=y -CONFIG_NSH_ARCHINIT=n +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=y +# CONFIG_NSH_TELNET_LOGIN is not set CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_NOMAC=y +CONFIG_NSH_MAX_ROUNDTRIP=20 # -# Architecture-specific NSH options +# NxWidgets/NxWM # -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NXWIDGETS=y # -# I2C tool settings +# NX Server/Device Configuration # -CONFIG_I2CTOOL_BUILTIN=y -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2CTOOL_MAXBUS=3 -#CONFIG_I2CTOOL_MINADDR -#CONFIG_I2CTOOL_MAXADDR -#CONFIG_I2CTOOL_MAXREGADDR -CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_NXWIDGETS_FLICKERFREE=y +CONFIG_NXWIDGETS_DEVNO=0 +CONFIG_NXWIDGETS_VPLANE=0 +CONFIG_NXWIDGETS_SERVERPRIO=51 +CONFIG_NXWIDGETS_SERVERSTACK=2048 +CONFIG_NXWIDGETS_CLIENTPRIO=50 +CONFIG_NXWIDGETS_LISTENERPRIO=50 +CONFIG_NXWIDGETS_LISTENERSTACK=2048 +# CONFIG_NXWIDGETS_EXTERNINIT is not set +# CONFIG_NXWIDGET_EVENTWAIT is not set # -# Settings for examples/usbserial +# NXWidget Configuration # -CONFIG_EXAMPLES_USBSERIAL_INONLY=n -CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n -CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n -CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n +# +# NXWidget Default Values +# +# CONFIG_NXWIDGETS_SYSTEM_CUSTOM_FONTID is not set +CONFIG_NXWIDGETS_TNXARRAY_INITIALSIZE=16 +CONFIG_NXWIDGETS_TNXARRAY_SIZEINCREMENT=8 +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +# CONFIG_NXWIDGETS_CUSTOM_TEXTCOLORS is not set +CONFIG_NXWIDGETS_TRANSPARENT_COLOR=0x0 # -# Settings for examples/adc +# Keypad behavior # +CONFIG_NXWIDGETS_FIRST_REPEAT_TIME=500 +CONFIG_NXWIDGETS_CONTINUE_REPEAT_TIME=200 +CONFIG_NXWIDGETS_DOUBLECLICK_TIME=350 +CONFIG_NXWIDGETS_KBDBUFFER_SIZE=16 +CONFIG_NXWIDGETS_CURSORCONTROL_SIZE=4 +# CONFIG_NXWIDGET_MEMMONITOR is not set +CONFIG_NXWM=y # -# Settings for examples/can +# General settings # +# CONFIG_NXWM_SYSTEM_CUSTOM_FONTID is not set +CONFIG_NXWM_UNITTEST=y # -# Settings for examples/nx +# Color configuration # -CONFIG_EXAMPLES_NX_BUILTIN=y -CONFIG_EXAMPLES_NX_VPLANE=0 -CONFIG_EXAMPLES_NX_DEVNO=0 -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_RAWWINDOWS=n -CONFIG_EXAMPLES_NX_STACKSIZE=2048 -CONFIG_EXAMPLES_NX_CLIENTPRIO=80 -CONFIG_EXAMPLES_NX_SERVERPRIO=120 -CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 -CONFIG_EXAMPLES_NX_EXTERNINIT=n +# CONFIG_NXWM_CUSTOM_FILLCOLORS is not set +# CONFIG_NXWM_CUSTOM_EDGECOLORS is not set +# CONFIG_NXWM_CUSTOM_TEXTCOLORS is not set # -# Settings for examples/nxhello +# Horizontal and vertical spacing of icons in the task bar # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y -CONFIG_EXAMPLES_NXHELLO_VPLANE=0 -CONFIG_EXAMPLES_NXHELLO_DEVNO=0 -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TASKBAR_HSPACING=2 +# CONFIG_NXWM_TASKBAR_TOP is not set +# CONFIG_NXWM_TASKBAR_BOTTOM is not set +CONFIG_NXWM_TASKBAR_LEFT=y +# CONFIG_NXWM_TASKBAR_RIGHT is not set +# CONFIG_NXWM_CUSTOM_TASKBAR_WIDTH is not set +# CONFIG_NXWM_DISABLE_MINIMIZE is not set # -# Settings for examples/nximage +# Tool Bar Configuration # -CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y -CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 -CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 -CONFIG_EXAMPLES_NXIMAGE_BPP=16 -CONFIG_EXAMPLES_NXIMAGE_XSCALEp5=n -CONFIG_EXAMPLES_NXIMAGE_XSCALE1p5=y -CONFIG_EXAMPLES_NXIMAGE_XSCALE2p0=n -CONFIG_EXAMPLES_NXIMAGE_YSCALEp5=n -CONFIG_EXAMPLES_NXIMAGE_YSCALE1p5=y -CONFIG_EXAMPLES_NXIMAGE_YSCALE2p0=n -CONFIG_EXAMPLES_NXIMAGE_EXTERNINIT=n +# CONFIG_NXWM_CUSTOM_TOOLBAR_HEIGHT is not set # -# Settings for examples/nxlines +# Background Image # -CONFIG_EXAMPLES_NXLINES_VPLANE=0 -CONFIG_EXAMPLES_NXLINES_DEVNO=0 -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb -CONFIG_EXAMPLES_NXLINES_BPP=16 -CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n +# CONFIG_NXWM_DISABLE_BACKGROUND_IMAGE is not set +CONFIG_NXWM_BACKGROUND_IMAGE="" # -# Settings for examples/touchscreen +# Start Window Configuration # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=n -CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 -CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" -CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 # -# Settings for examples/usbstorage +# Horizontal and vertical spacing of icons in the task bar # -CONFIG_EXAMPLES_USBMSC_BUILTIN=y -CONFIG_EXAMPLES_USBMSC_NLUNS=1 -CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 -CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" -CONFIG_EXAMPLES_USBMSC_DEBUGMM=n -CONFIG_EXAMPLES_USBMSC_TRACEINIT=n -CONFIG_EXAMPLES_USBMSC_TRACECLASS=n -CONFIG_EXAMPLES_USBMSC_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBMSC_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n +CONFIG_NXWM_STARTWINDOW_VSPACING=4 +CONFIG_NXWM_STARTWINDOW_HSPACING=4 +# CONFIG_NXWM_CUSTOM_STARTWINDOW_ICON is not set +CONFIG_NXWM_STARTWINDOW_MQNAME="/dev/nxwm" +CONFIG_NXWM_STARTWINDOW_MXMSGS=32 +CONFIG_NXWM_STARTWINDOW_MXMPRIO=42 +CONFIG_NXWM_STARTWINDOW_PRIO=50 +CONFIG_NXWM_STARTWINDOW_STACKSIZE=2048 # -# Settings for examples/watchdog +# NxConsole Window Configuration +# +CONFIG_NXWM_NXCONSOLE_PRIO=50 +CONFIG_NXWM_NXCONSOLE_STACKSIZE=2048 +# CONFIG_NXWM_NXCONSOLE_CUSTOM_COLORS is not set +# CONFIG_NXWM_NXCONSOLE_CUSTOM_FONTID is not set +# CONFIG_NXWM_CUSTOM_NXCONSOLE_ICON is not set +CONFIG_NXWM_TOUCHSCREEN=y + +# +# Touchscreen device settings +# +CONFIG_NXWM_TOUCHSCREEN_DEVNO=0 +CONFIG_NXWM_TOUCHSCREEN_DEVPATH="/dev/input0" +CONFIG_NXWM_TOUCHSCREEN_SIGNO=5 +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=50 +CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1024 +CONFIG_NXWM_KEYBOARD=y + # -# This test depends on these specific Watchdog/NSH configurations settings (your -# specific watchdog hardware settings might require additional settings). +# Keyboard device settings # +CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/console" +CONFIG_NXWM_KEYBOARD_SIGNO=6 +CONFIG_NXWM_KEYBOARD_BUFSIZE=16 +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=50 +CONFIG_NXWM_KEYBOARD_LISTENERSTACK=2048 # -# Settings for examples/pwm +# Calibration display settings # +# CONFIG_NXWM_CALIBRATION_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_CALIBRATION_ICON is not set +CONFIG_NXWM_CALIBRATION_SIGNO=5 +CONFIG_NXWM_CALIBRATION_LISTENERPRIO=50 +CONFIG_NXWM_CALIBRATION_LISTENERSTACK=2048 # -# Settings for examples/ftpd +# Calibration display settings # +# CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_HEXCALCULATOR_ICON is not set +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # -# Settings for examples/watchdog +# System NSH Add-Ons # -# This test depends on these specific Watchdog/NSH configurations settings (your -# specific watchdog hardware settings might require additional settings). + # +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set # -# Stack and heap information +# I2C tool # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= +# CONFIG_SYSTEM_I2CTOOL is not set + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/stm3220g-eval/nxwm/setenv.sh b/nuttx/configs/stm3220g-eval/nxwm/setenv.sh index 858531391..7326fad47 100755 --- a/nuttx/configs/stm3220g-eval/nxwm/setenv.sh +++ b/nuttx/configs/stm3220g-eval/nxwm/setenv.sh @@ -67,7 +67,7 @@ export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ # This is the Cygwin path to the location where I build the buildroot # toolchain. -export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" # Add the path to the toolchain to the PATH variable export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" diff --git a/nuttx/drivers/input/Kconfig b/nuttx/drivers/input/Kconfig index 1f345ee14..6da3a9f39 100644 --- a/nuttx/drivers/input/Kconfig +++ b/nuttx/drivers/input/Kconfig @@ -123,6 +123,25 @@ config STMPE811_I2C endchoice +config STMPE811_ACTIVELOW + bool "Active Low Interrupt" + default n + ---help--- + The STMPE811 interrupt is provided by a discrete input (usually a + GPIO interrupt on most MCU architectures). This setting determines + whether the interrupt is active high (or rising edge triggered) or + active low (or falling edge triggered). Default: Active + high/rising edge. + +config STMPE811_EDGE + bool "Edge triggered Interrupt" + default n + ---help--- + The STMPE811 interrupt is provided by a discrete input (usually a + GPIO interrupt on most MCU architectures). This setting determines + whether the interrupt is edge or level triggered. Default: Level + triggered. + config STMPE811_MULTIPLE bool "Multiple STMPE811 Devices" default n diff --git a/nuttx/graphics/Makefile b/nuttx/graphics/Makefile index 238e14df4..aa402bfa4 100644 --- a/nuttx/graphics/Makefile +++ b/nuttx/graphics/Makefile @@ -124,6 +124,9 @@ gen32bppsources: $(Q) $(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_BITSPERPIXEL=32 EXTRADEFINES=$(EXTRADEFINES) genfontsources: +ifeq ($(CONFIG_NXFONT_MONO5X8),y) + @$(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=18 EXTRADEFINES=$(EXTRADEFINES) +endif ifeq ($(CONFIG_NXFONT_SANS23X27),y) $(Q) $(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=1 EXTRADEFINES=$(EXTRADEFINES) endif diff --git a/nuttx/graphics/nxfonts/Make.defs b/nuttx/graphics/nxfonts/Make.defs index bc65d7ad7..def092825 100644 --- a/nuttx/graphics/nxfonts/Make.defs +++ b/nuttx/graphics/nxfonts/Make.defs @@ -42,6 +42,12 @@ NXFCONV_CSRCS = nxfonts_convert_1bpp.c nxfonts_convert_2bpp.c \ NXFSET_ASRCS = NXFSET_CSRCS = +# Monospace fonts + +ifeq ($(CONFIG_NXFONT_MONO5X8),y) +NXFSET_CSRCS += nxfonts_bitmaps_mono5x8.c +endif + # Sans serif fonts ifeq ($(CONFIG_NXFONT_SANS17X22),y) diff --git a/nuttx/graphics/nxfonts/Makefile.sources b/nuttx/graphics/nxfonts/Makefile.sources index 76a099dcb..2e41fc704 100644 --- a/nuttx/graphics/nxfonts/Makefile.sources +++ b/nuttx/graphics/nxfonts/Makefile.sources @@ -72,6 +72,13 @@ endif ifdef NXFONTS_FONTID +# MONO + +ifeq ($(NXFONTS_FONTID),18) +NXFONTS_PREFIX := g_mono5x8_ +GEN_CSRC = nxfonts_bitmaps_mono5x8.c +endif + # SANS ifeq ($(NXFONTS_FONTID),14) diff --git a/nuttx/graphics/nxfonts/nxfonts_bitmaps.c b/nuttx/graphics/nxfonts/nxfonts_bitmaps.c index 2efc34b87..b089ec038 100644 --- a/nuttx/graphics/nxfonts/nxfonts_bitmaps.c +++ b/nuttx/graphics/nxfonts/nxfonts_bitmaps.c @@ -80,6 +80,8 @@ # include "nxfonts_sans17x23b.h" #elif NXFONTS_FONTID == 17 # include "nxfonts_sans20x27b.h" +#elif NXFONTS_FONTID == 18 +# include "nxfonts_mono5x8.h" #else # error "No font ID specified" #endif diff --git a/nuttx/graphics/nxfonts/nxfonts_getfont.c b/nuttx/graphics/nxfonts/nxfonts_getfont.c index 23e5c4474..c2af977f2 100644 --- a/nuttx/graphics/nxfonts/nxfonts_getfont.c +++ b/nuttx/graphics/nxfonts/nxfonts_getfont.c @@ -60,6 +60,12 @@ * Private Data ****************************************************************************/ +/* MONO */ + +#ifdef CONFIG_NXFONT_MONO5X8 +extern const struct nx_fontpackage_s g_mono5x8_package; +#endif + /* SANS */ #ifdef CONFIG_NXFONT_SANS17X22 @@ -139,6 +145,12 @@ extern const struct nx_fontpackage_s g_serif38x49b_package; static FAR const struct nx_fontpackage_s *g_fontpackages[] = { +/* MONO */ + +#ifdef CONFIG_NXFONT_MONO5X8 + &g_mono5x8_package, +#endif + /* SANS */ #ifdef CONFIG_NXFONT_SANS17X22 diff --git a/nuttx/graphics/nxfonts/nxfonts_mono5x8.h b/nuttx/graphics/nxfonts/nxfonts_mono5x8.h new file mode 100644 index 000000000..739437e62 --- /dev/null +++ b/nuttx/graphics/nxfonts/nxfonts_mono5x8.h @@ -0,0 +1,815 @@ +/**************************************************************************** + * graphics/nxfonts/nxfonts_mono5x8.h + * + * Copyright (C) 2011-2012 NX Engineering, S.A., All rights reserved. + * Author: Petteri Aimonen + * + * Based on 5x8.pcf.gz from xfonts-base. The file is marked as + * COPYRIGHT "Public domain font. Share and enjoy." + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT} + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING} + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __GRAPHICS_NXFONTS_NXFONTS_MONO5X8_H +#define __GRAPHICS_NXFONTS_NXFONTS_MONO5X8_H + +#define NXFONT_ID FONTID_MONO5X8 + +#define NXFONT_MIN7BIT 33 +#define NXFONT_MAX7BIT 126 + +#define NXFONT_MIN8BIT 161 +#define NXFONT_MAX8BIT 255 + +/* Maximum height and width of any glyph in the set */ + +#define NXFONT_MAXHEIGHT 8 +#define NXFONT_MAXWIDTH 5 + +/* The width of a space */ + +#define NXFONT_SPACEWIDTH 5 + +/* exclam (33) */ +#define NXFONT_METRICS_33 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_33 {0x0, 0x20, 0x20, 0x20, 0x20, 0x0, 0x20, 0x0} + +/* quotedbl (34) */ +#define NXFONT_METRICS_34 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_34 {0x0, 0x50, 0x50, 0x50, 0x0, 0x0, 0x0, 0x0} + +/* numbersign (35) */ +#define NXFONT_METRICS_35 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_35 {0x50, 0x50, 0xf8, 0x50, 0xf8, 0x50, 0x50, 0x0} + +/* dollar (36) */ +#define NXFONT_METRICS_36 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_36 {0x20, 0x70, 0xa0, 0x70, 0x28, 0x70, 0x20, 0x0} + +/* percent (37) */ +#define NXFONT_METRICS_37 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_37 {0x0, 0x40, 0x50, 0x20, 0x50, 0x10, 0x0, 0x0} + +/* ampersand (38) */ +#define NXFONT_METRICS_38 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_38 {0x40, 0xa0, 0xa0, 0x40, 0xa0, 0xa0, 0x50, 0x0} + +/* quotesingle (39) */ +#define NXFONT_METRICS_39 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_39 {0x0, 0x20, 0x20, 0x20, 0x0, 0x0, 0x0, 0x0} + +/* parenleft (40) */ +#define NXFONT_METRICS_40 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_40 {0x0, 0x20, 0x40, 0x40, 0x40, 0x40, 0x20, 0x0} + +/* parenright (41) */ +#define NXFONT_METRICS_41 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_41 {0x0, 0x40, 0x20, 0x20, 0x20, 0x20, 0x40, 0x0} + +/* asterisk (42) */ +#define NXFONT_METRICS_42 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_42 {0x0, 0x0, 0x90, 0x60, 0xf0, 0x60, 0x90, 0x0} + +/* plus (43) */ +#define NXFONT_METRICS_43 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_43 {0x0, 0x0, 0x20, 0x20, 0xf8, 0x20, 0x20, 0x0} + +/* comma (44) */ +#define NXFONT_METRICS_44 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_44 {0x0, 0x0, 0x0, 0x0, 0x0, 0x30, 0x20, 0x40} + +/* hyphen (45) */ +#define NXFONT_METRICS_45 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_45 {0x0, 0x0, 0x0, 0x0, 0xf0, 0x0, 0x0, 0x0} + +/* period (46) */ +#define NXFONT_METRICS_46 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_46 {0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x70, 0x20} + +/* slash (47) */ +#define NXFONT_METRICS_47 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_47 {0x0, 0x10, 0x10, 0x20, 0x40, 0x80, 0x80, 0x0} + +/* zero (48) */ +#define NXFONT_METRICS_48 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_48 {0x0, 0x20, 0x50, 0x50, 0x50, 0x50, 0x20, 0x0} + +/* one (49) */ +#define NXFONT_METRICS_49 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_49 {0x0, 0x20, 0x60, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* two (50) */ +#define NXFONT_METRICS_50 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_50 {0x0, 0x60, 0x90, 0x10, 0x60, 0x80, 0xf0, 0x0} + +/* three (51) */ +#define NXFONT_METRICS_51 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_51 {0x0, 0xf0, 0x20, 0x60, 0x10, 0x90, 0x60, 0x0} + +/* four (52) */ +#define NXFONT_METRICS_52 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_52 {0x0, 0x20, 0x60, 0xa0, 0xf0, 0x20, 0x20, 0x0} + +/* five (53) */ +#define NXFONT_METRICS_53 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_53 {0x0, 0xf0, 0x80, 0xe0, 0x10, 0x90, 0x60, 0x0} + +/* six (54) */ +#define NXFONT_METRICS_54 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_54 {0x0, 0x60, 0x80, 0xe0, 0x90, 0x90, 0x60, 0x0} + +/* seven (55) */ +#define NXFONT_METRICS_55 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_55 {0x0, 0xf0, 0x10, 0x20, 0x20, 0x40, 0x40, 0x0} + +/* eight (56) */ +#define NXFONT_METRICS_56 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_56 {0x0, 0x60, 0x90, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* nine (57) */ +#define NXFONT_METRICS_57 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_57 {0x0, 0x60, 0x90, 0x90, 0x70, 0x10, 0x60, 0x0} + +/* colon (58) */ +#define NXFONT_METRICS_58 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_58 {0x0, 0x0, 0x60, 0x60, 0x0, 0x60, 0x60, 0x0} + +/* semicolon (59) */ +#define NXFONT_METRICS_59 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_59 {0x0, 0x0, 0x30, 0x30, 0x0, 0x30, 0x20, 0x40} + +/* less (60) */ +#define NXFONT_METRICS_60 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_60 {0x0, 0x10, 0x20, 0x40, 0x40, 0x20, 0x10, 0x0} + +/* equal (61) */ +#define NXFONT_METRICS_61 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_61 {0x0, 0x0, 0x0, 0xf0, 0x0, 0xf0, 0x0, 0x0} + +/* greater (62) */ +#define NXFONT_METRICS_62 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_62 {0x0, 0x40, 0x20, 0x10, 0x10, 0x20, 0x40, 0x0} + +/* question (63) */ +#define NXFONT_METRICS_63 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_63 {0x0, 0x20, 0x50, 0x10, 0x20, 0x0, 0x20, 0x0} + +/* at (64) */ +#define NXFONT_METRICS_64 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_64 {0x30, 0x48, 0x98, 0xa8, 0xa8, 0x90, 0x40, 0x30} + +/* A (65) */ +#define NXFONT_METRICS_65 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_65 {0x0, 0x60, 0x90, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* B (66) */ +#define NXFONT_METRICS_66 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_66 {0x0, 0xe0, 0x90, 0xe0, 0x90, 0x90, 0xe0, 0x0} + +/* C (67) */ +#define NXFONT_METRICS_67 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_67 {0x0, 0x60, 0x90, 0x80, 0x80, 0x90, 0x60, 0x0} + +/* D (68) */ +#define NXFONT_METRICS_68 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_68 {0x0, 0xe0, 0x90, 0x90, 0x90, 0x90, 0xe0, 0x0} + +/* E (69) */ +#define NXFONT_METRICS_69 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_69 {0x0, 0xf0, 0x80, 0xe0, 0x80, 0x80, 0xf0, 0x0} + +/* F (70) */ +#define NXFONT_METRICS_70 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_70 {0x0, 0xf0, 0x80, 0xe0, 0x80, 0x80, 0x80, 0x0} + +/* G (71) */ +#define NXFONT_METRICS_71 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_71 {0x0, 0x60, 0x90, 0x80, 0xb0, 0x90, 0x60, 0x0} + +/* H (72) */ +#define NXFONT_METRICS_72 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_72 {0x0, 0x90, 0x90, 0xf0, 0x90, 0x90, 0x90, 0x0} + +/* I (73) */ +#define NXFONT_METRICS_73 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_73 {0x0, 0x70, 0x20, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* J (74) */ +#define NXFONT_METRICS_74 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_74 {0x0, 0x70, 0x20, 0x20, 0x20, 0xa0, 0x40, 0x0} + +/* K (75) */ +#define NXFONT_METRICS_75 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_75 {0x0, 0x90, 0xa0, 0xc0, 0xa0, 0xa0, 0x90, 0x0} + +/* L (76) */ +#define NXFONT_METRICS_76 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_76 {0x0, 0x80, 0x80, 0x80, 0x80, 0x80, 0xf0, 0x0} + +/* M (77) */ +#define NXFONT_METRICS_77 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_77 {0x0, 0x90, 0xf0, 0xf0, 0x90, 0x90, 0x90, 0x0} + +/* N (78) */ +#define NXFONT_METRICS_78 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_78 {0x0, 0x90, 0xd0, 0xf0, 0xb0, 0xb0, 0x90, 0x0} + +/* O (79) */ +#define NXFONT_METRICS_79 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_79 {0x0, 0x60, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* P (80) */ +#define NXFONT_METRICS_80 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_80 {0x0, 0xe0, 0x90, 0x90, 0xe0, 0x80, 0x80, 0x0} + +/* Q (81) */ +#define NXFONT_METRICS_81 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_81 {0x0, 0x60, 0x90, 0x90, 0xd0, 0xb0, 0x60, 0x10} + +/* R (82) */ +#define NXFONT_METRICS_82 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_82 {0x0, 0xe0, 0x90, 0x90, 0xe0, 0x90, 0x90, 0x0} + +/* S (83) */ +#define NXFONT_METRICS_83 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_83 {0x0, 0x60, 0x90, 0x40, 0x20, 0x90, 0x60, 0x0} + +/* T (84) */ +#define NXFONT_METRICS_84 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_84 {0x0, 0x70, 0x20, 0x20, 0x20, 0x20, 0x20, 0x0} + +/* U (85) */ +#define NXFONT_METRICS_85 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_85 {0x0, 0x90, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* V (86) */ +#define NXFONT_METRICS_86 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_86 {0x0, 0x90, 0x90, 0x90, 0x90, 0x60, 0x60, 0x0} + +/* W (87) */ +#define NXFONT_METRICS_87 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_87 {0x0, 0x90, 0x90, 0x90, 0xf0, 0xf0, 0x90, 0x0} + +/* X (88) */ +#define NXFONT_METRICS_88 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_88 {0x0, 0x90, 0x90, 0x60, 0x60, 0x90, 0x90, 0x0} + +/* Y (89) */ +#define NXFONT_METRICS_89 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_89 {0x0, 0x88, 0x88, 0x50, 0x20, 0x20, 0x20, 0x0} + +/* Z (90) */ +#define NXFONT_METRICS_90 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_90 {0x0, 0xf0, 0x10, 0x20, 0x40, 0x80, 0xf0, 0x0} + +/* bracketleft (91) */ +#define NXFONT_METRICS_91 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_91 {0x0, 0x70, 0x40, 0x40, 0x40, 0x40, 0x70, 0x0} + +/* backslash (92) */ +#define NXFONT_METRICS_92 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_92 {0x0, 0x80, 0x80, 0x40, 0x20, 0x10, 0x10, 0x0} + +/* bracketright (93) */ +#define NXFONT_METRICS_93 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_93 {0x0, 0x70, 0x10, 0x10, 0x10, 0x10, 0x70, 0x0} + +/* asciicircum (94) */ +#define NXFONT_METRICS_94 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_94 {0x0, 0x20, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* underscore (95) */ +#define NXFONT_METRICS_95 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_95 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf0} + +/* grave (96) */ +#define NXFONT_METRICS_96 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_96 {0x0, 0x40, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* a (97) */ +#define NXFONT_METRICS_97 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_97 {0x0, 0x0, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* b (98) */ +#define NXFONT_METRICS_98 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_98 {0x0, 0x80, 0x80, 0xe0, 0x90, 0x90, 0xe0, 0x0} + +/* c (99) */ +#define NXFONT_METRICS_99 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_99 {0x0, 0x0, 0x0, 0x30, 0x40, 0x40, 0x30, 0x0} + +/* d (100) */ +#define NXFONT_METRICS_100 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_100 {0x0, 0x10, 0x10, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* e (101) */ +#define NXFONT_METRICS_101 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_101 {0x0, 0x0, 0x0, 0x60, 0xb0, 0xc0, 0x60, 0x0} + +/* f (102) */ +#define NXFONT_METRICS_102 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_102 {0x0, 0x20, 0x50, 0x40, 0xe0, 0x40, 0x40, 0x0} + +/* g (103) */ +#define NXFONT_METRICS_103 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_103 {0x0, 0x0, 0x0, 0x60, 0x90, 0x70, 0x10, 0x60} + +/* h (104) */ +#define NXFONT_METRICS_104 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_104 {0x0, 0x80, 0x80, 0xe0, 0x90, 0x90, 0x90, 0x0} + +/* i (105) */ +#define NXFONT_METRICS_105 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_105 {0x0, 0x20, 0x0, 0x60, 0x20, 0x20, 0x70, 0x0} + +/* j (106) */ +#define NXFONT_METRICS_106 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_106 {0x0, 0x10, 0x0, 0x10, 0x10, 0x10, 0x50, 0x20} + +/* k (107) */ +#define NXFONT_METRICS_107 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_107 {0x0, 0x80, 0x80, 0x90, 0xe0, 0x90, 0x90, 0x0} + +/* l (108) */ +#define NXFONT_METRICS_108 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_108 {0x0, 0x60, 0x20, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* m (109) */ +#define NXFONT_METRICS_109 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_109 {0x0, 0x0, 0x0, 0xd0, 0xa8, 0xa8, 0xa8, 0x0} + +/* n (110) */ +#define NXFONT_METRICS_110 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_110 {0x0, 0x0, 0x0, 0xe0, 0x90, 0x90, 0x90, 0x0} + +/* o (111) */ +#define NXFONT_METRICS_111 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_111 {0x0, 0x0, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* p (112) */ +#define NXFONT_METRICS_112 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_112 {0x0, 0x0, 0x0, 0xe0, 0x90, 0xe0, 0x80, 0x80} + +/* q (113) */ +#define NXFONT_METRICS_113 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_113 {0x0, 0x0, 0x0, 0x70, 0x90, 0x70, 0x10, 0x10} + +/* r (114) */ +#define NXFONT_METRICS_114 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_114 {0x0, 0x0, 0x0, 0xa0, 0xd0, 0x80, 0x80, 0x0} + +/* s (115) */ +#define NXFONT_METRICS_115 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_115 {0x0, 0x0, 0x0, 0x30, 0x60, 0x10, 0x60, 0x0} + +/* t (116) */ +#define NXFONT_METRICS_116 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_116 {0x0, 0x40, 0x40, 0xe0, 0x40, 0x50, 0x20, 0x0} + +/* u (117) */ +#define NXFONT_METRICS_117 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_117 {0x0, 0x0, 0x0, 0x90, 0x90, 0x90, 0x70, 0x0} + +/* v (118) */ +#define NXFONT_METRICS_118 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_118 {0x0, 0x0, 0x0, 0x50, 0x50, 0x50, 0x20, 0x0} + +/* w (119) */ +#define NXFONT_METRICS_119 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_119 {0x0, 0x0, 0x0, 0x88, 0xa8, 0xa8, 0x50, 0x0} + +/* x (120) */ +#define NXFONT_METRICS_120 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_120 {0x0, 0x0, 0x0, 0x90, 0x60, 0x60, 0x90, 0x0} + +/* y (121) */ +#define NXFONT_METRICS_121 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_121 {0x0, 0x0, 0x0, 0x90, 0x90, 0x70, 0x90, 0x60} + +/* z (122) */ +#define NXFONT_METRICS_122 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_122 {0x0, 0x0, 0x0, 0xf0, 0x20, 0x40, 0xf0, 0x0} + +/* braceleft (123) */ +#define NXFONT_METRICS_123 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_123 {0x30, 0x40, 0x20, 0xc0, 0x20, 0x40, 0x30, 0x0} + +/* bar (124) */ +#define NXFONT_METRICS_124 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_124 {0x0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x0} + +/* braceright (125) */ +#define NXFONT_METRICS_125 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_125 {0xc0, 0x20, 0x40, 0x30, 0x40, 0x20, 0xc0, 0x0} + +/* asciitilde (126) */ +#define NXFONT_METRICS_126 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_126 {0x0, 0x50, 0xa0, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* exclamdown (161) */ +#define NXFONT_METRICS_161 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_161 {0x0, 0x20, 0x0, 0x20, 0x20, 0x20, 0x20, 0x0} + +/* cent (162) */ +#define NXFONT_METRICS_162 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_162 {0x0, 0x0, 0x20, 0x70, 0xa0, 0xa0, 0x70, 0x20} + +/* sterling (163) */ +#define NXFONT_METRICS_163 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_163 {0x0, 0x20, 0x50, 0xe0, 0x40, 0x50, 0xa0, 0x0} + +/* currency (164) */ +#define NXFONT_METRICS_164 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_164 {0x0, 0x0, 0x88, 0x70, 0x50, 0x70, 0x88, 0x0} + +/* yen (165) */ +#define NXFONT_METRICS_165 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_165 {0x0, 0x88, 0x50, 0xf8, 0x20, 0xf8, 0x20, 0x0} + +/* brokenbar (166) */ +#define NXFONT_METRICS_166 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_166 {0x20, 0x20, 0x20, 0x0, 0x20, 0x20, 0x20, 0x0} + +/* section (167) */ +#define NXFONT_METRICS_167 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_167 {0x70, 0x80, 0xe0, 0x90, 0x70, 0x10, 0xe0, 0x0} + +/* dieresis (168) */ +#define NXFONT_METRICS_168 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_168 {0x0, 0x50, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* copyright (169) */ +#define NXFONT_METRICS_169 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_169 {0x0, 0x70, 0xa8, 0xc8, 0xc8, 0xa8, 0x70, 0x0} + +/* ordfeminine (170) */ +#define NXFONT_METRICS_170 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_170 {0x30, 0x50, 0x30, 0x0, 0x70, 0x0, 0x0, 0x0} + +/* guillemotleft (171) */ +#define NXFONT_METRICS_171 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_171 {0x0, 0x0, 0x0, 0x50, 0xa0, 0x50, 0x0, 0x0} + +/* logicalnot (172) */ +#define NXFONT_METRICS_172 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_172 {0x0, 0x0, 0x0, 0x0, 0x70, 0x10, 0x10, 0x0} + +/* hyphen (173) */ +#define NXFONT_METRICS_173 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_173 {0x0, 0x0, 0x0, 0x0, 0x70, 0x0, 0x0, 0x0} + +/* registered (174) */ +#define NXFONT_METRICS_174 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_174 {0x0, 0x70, 0xe8, 0xd8, 0xe8, 0xd8, 0x70, 0x0} + +/* macron (175) */ +#define NXFONT_METRICS_175 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_175 {0x0, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* degree (176) */ +#define NXFONT_METRICS_176 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_176 {0x0, 0x20, 0x50, 0x20, 0x0, 0x0, 0x0, 0x0} + +/* plusminus (177) */ +#define NXFONT_METRICS_177 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_177 {0x0, 0x0, 0x20, 0x70, 0x20, 0x0, 0x70, 0x0} + +/* twosuperior (178) */ +#define NXFONT_METRICS_178 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_178 {0x20, 0x50, 0x10, 0x20, 0x70, 0x0, 0x0, 0x0} + +/* threesuperior (179) */ +#define NXFONT_METRICS_179 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_179 {0x60, 0x10, 0x60, 0x10, 0x60, 0x0, 0x0, 0x0} + +/* acute (180) */ +#define NXFONT_METRICS_180 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_180 {0x0, 0x20, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0} + +/* mu (181) */ +#define NXFONT_METRICS_181 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_181 {0x0, 0x0, 0x0, 0x90, 0x90, 0x90, 0xe0, 0x80} + +/* paragraph (182) */ +#define NXFONT_METRICS_182 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_182 {0x0, 0x78, 0xe8, 0xe8, 0x68, 0x28, 0x28, 0x0} + +/* periodcentered (183) */ +#define NXFONT_METRICS_183 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_183 {0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0} + +/* cedilla (184) */ +#define NXFONT_METRICS_184 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_184 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x40} + +/* onesuperior (185) */ +#define NXFONT_METRICS_185 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_185 {0x20, 0x60, 0x20, 0x20, 0x70, 0x0, 0x0, 0x0} + +/* ordmasculine (186) */ +#define NXFONT_METRICS_186 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_186 {0x20, 0x50, 0x20, 0x0, 0x70, 0x0, 0x0, 0x0} + +/* guillemotright (187) */ +#define NXFONT_METRICS_187 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_187 {0x0, 0x0, 0x0, 0xa0, 0x50, 0xa0, 0x0, 0x0} + +/* onequarter (188) */ +#define NXFONT_METRICS_188 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_188 {0x80, 0x80, 0x80, 0xa0, 0x60, 0xf0, 0x20, 0x0} + +/* onehalf (189) */ +#define NXFONT_METRICS_189 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_189 {0x80, 0x80, 0xa0, 0xd0, 0x10, 0x20, 0x70, 0x0} + +/* threequarters (190) */ +#define NXFONT_METRICS_190 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_190 {0x80, 0x40, 0x80, 0x60, 0xa0, 0xf0, 0x20, 0x0} + +/* questiondown (191) */ +#define NXFONT_METRICS_191 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_191 {0x0, 0x20, 0x0, 0x20, 0x40, 0x50, 0x20, 0x0} + +/* Agrave (192) */ +#define NXFONT_METRICS_192 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_192 {0x40, 0x20, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* Aacute (193) */ +#define NXFONT_METRICS_193 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_193 {0x20, 0x40, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* Acircumflex (194) */ +#define NXFONT_METRICS_194 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_194 {0x60, 0x90, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* Atilde (195) */ +#define NXFONT_METRICS_195 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_195 {0x50, 0xa0, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* Adieresis (196) */ +#define NXFONT_METRICS_196 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_196 {0x90, 0x0, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* Aring (197) */ +#define NXFONT_METRICS_197 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_197 {0x60, 0x90, 0x60, 0x90, 0xf0, 0x90, 0x90, 0x0} + +/* AE (198) */ +#define NXFONT_METRICS_198 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_198 {0x0, 0x70, 0xa0, 0xa0, 0xf0, 0xa0, 0xb0, 0x0} + +/* Ccedilla (199) */ +#define NXFONT_METRICS_199 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_199 {0x0, 0x60, 0x90, 0x80, 0x80, 0x90, 0x60, 0x40} + +/* Egrave (200) */ +#define NXFONT_METRICS_200 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_200 {0x40, 0x20, 0xf0, 0x80, 0xe0, 0x80, 0xf0, 0x0} + +/* Eacute (201) */ +#define NXFONT_METRICS_201 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_201 {0x20, 0x40, 0xf0, 0x80, 0xe0, 0x80, 0xf0, 0x0} + +/* Ecircumflex (202) */ +#define NXFONT_METRICS_202 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_202 {0x60, 0x90, 0xf0, 0x80, 0xe0, 0x80, 0xf0, 0x0} + +/* Edieresis (203) */ +#define NXFONT_METRICS_203 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_203 {0x90, 0x0, 0xf0, 0x80, 0xe0, 0x80, 0xf0, 0x0} + +/* Igrave (204) */ +#define NXFONT_METRICS_204 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_204 {0x40, 0x20, 0x70, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* Iacute (205) */ +#define NXFONT_METRICS_205 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_205 {0x10, 0x20, 0x70, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* Icircumflex (206) */ +#define NXFONT_METRICS_206 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_206 {0x20, 0x50, 0x70, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* Idieresis (207) */ +#define NXFONT_METRICS_207 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_207 {0x50, 0x0, 0x70, 0x20, 0x20, 0x20, 0x70, 0x0} + +/* Eth (208) */ +#define NXFONT_METRICS_208 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_208 {0x0, 0x70, 0x48, 0xe8, 0x48, 0x48, 0x70, 0x0} + +/* Ntilde (209) */ +#define NXFONT_METRICS_209 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_209 {0x50, 0xa0, 0x90, 0xd0, 0xb0, 0x90, 0x90, 0x0} + +/* Ograve (210) */ +#define NXFONT_METRICS_210 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_210 {0x40, 0x20, 0x60, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Oacute (211) */ +#define NXFONT_METRICS_211 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_211 {0x20, 0x40, 0x60, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Ocircumflex (212) */ +#define NXFONT_METRICS_212 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_212 {0x60, 0x90, 0x60, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Otilde (213) */ +#define NXFONT_METRICS_213 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_213 {0x50, 0xa0, 0x60, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Odieresis (214) */ +#define NXFONT_METRICS_214 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_214 {0x90, 0x0, 0x60, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* multiply (215) */ +#define NXFONT_METRICS_215 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_215 {0x0, 0x0, 0x0, 0x0, 0x50, 0x20, 0x50, 0x0} + +/* Oslash (216) */ +#define NXFONT_METRICS_216 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_216 {0x0, 0x70, 0xb0, 0xb0, 0xd0, 0xd0, 0xe0, 0x0} + +/* Ugrave (217) */ +#define NXFONT_METRICS_217 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_217 {0x40, 0x20, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Uacute (218) */ +#define NXFONT_METRICS_218 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_218 {0x20, 0x40, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Ucircumflex (219) */ +#define NXFONT_METRICS_219 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_219 {0x60, 0x90, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Udieresis (220) */ +#define NXFONT_METRICS_220 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_220 {0x90, 0x0, 0x90, 0x90, 0x90, 0x90, 0x60, 0x0} + +/* Yacute (221) */ +#define NXFONT_METRICS_221 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_221 {0x10, 0x20, 0x88, 0x50, 0x20, 0x20, 0x20, 0x0} + +/* Thorn (222) */ +#define NXFONT_METRICS_222 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_222 {0x0, 0x80, 0xe0, 0x90, 0x90, 0xe0, 0x80, 0x0} + +/* germandbls (223) */ +#define NXFONT_METRICS_223 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_223 {0x0, 0x60, 0x90, 0xa0, 0xa0, 0x90, 0xa0, 0x0} + +/* agrave (224) */ +#define NXFONT_METRICS_224 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_224 {0x40, 0x20, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* aacute (225) */ +#define NXFONT_METRICS_225 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_225 {0x20, 0x40, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* acircumflex (226) */ +#define NXFONT_METRICS_226 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_226 {0x20, 0x50, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* atilde (227) */ +#define NXFONT_METRICS_227 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_227 {0x50, 0xa0, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* adieresis (228) */ +#define NXFONT_METRICS_228 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_228 {0x0, 0x50, 0x0, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* aring (229) */ +#define NXFONT_METRICS_229 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_229 {0x60, 0x90, 0x60, 0x70, 0x90, 0x90, 0x70, 0x0} + +/* ae (230) */ +#define NXFONT_METRICS_230 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_230 {0x0, 0x0, 0x0, 0xf0, 0x68, 0xb0, 0x78, 0x0} + +/* ccedilla (231) */ +#define NXFONT_METRICS_231 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_231 {0x0, 0x0, 0x0, 0x30, 0x40, 0x40, 0x30, 0x20} + +/* egrave (232) */ +#define NXFONT_METRICS_232 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_232 {0x40, 0x20, 0x0, 0x60, 0xb0, 0xc0, 0x60, 0x0} + +/* eacute (233) */ +#define NXFONT_METRICS_233 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_233 {0x20, 0x40, 0x0, 0x60, 0xb0, 0xc0, 0x60, 0x0} + +/* ecircumflex (234) */ +#define NXFONT_METRICS_234 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_234 {0x60, 0x90, 0x0, 0x60, 0xb0, 0xc0, 0x60, 0x0} + +/* edieresis (235) */ +#define NXFONT_METRICS_235 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_235 {0x0, 0x50, 0x0, 0x60, 0xb0, 0xc0, 0x60, 0x0} + +/* igrave (236) */ +#define NXFONT_METRICS_236 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_236 {0x40, 0x20, 0x0, 0x60, 0x20, 0x20, 0x70, 0x0} + +/* iacute (237) */ +#define NXFONT_METRICS_237 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_237 {0x10, 0x20, 0x0, 0x60, 0x20, 0x20, 0x70, 0x0} + +/* icircumflex (238) */ +#define NXFONT_METRICS_238 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_238 {0x20, 0x50, 0x0, 0x60, 0x20, 0x20, 0x70, 0x0} + +/* idieresis (239) */ +#define NXFONT_METRICS_239 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_239 {0x0, 0x50, 0x0, 0x60, 0x20, 0x20, 0x70, 0x0} + +/* eth (240) */ +#define NXFONT_METRICS_240 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_240 {0xa0, 0x40, 0xa0, 0x10, 0x70, 0x90, 0x60, 0x0} + +/* ntilde (241) */ +#define NXFONT_METRICS_241 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_241 {0x50, 0xa0, 0x0, 0xe0, 0x90, 0x90, 0x90, 0x0} + +/* ograve (242) */ +#define NXFONT_METRICS_242 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_242 {0x40, 0x20, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* oacute (243) */ +#define NXFONT_METRICS_243 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_243 {0x20, 0x40, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* ocircumflex (244) */ +#define NXFONT_METRICS_244 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_244 {0x60, 0x90, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* otilde (245) */ +#define NXFONT_METRICS_245 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_245 {0x50, 0xa0, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* odieresis (246) */ +#define NXFONT_METRICS_246 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_246 {0x0, 0x90, 0x0, 0x60, 0x90, 0x90, 0x60, 0x0} + +/* divide (247) */ +#define NXFONT_METRICS_247 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_247 {0x0, 0x0, 0x20, 0x0, 0x70, 0x0, 0x20, 0x0} + +/* oslash (248) */ +#define NXFONT_METRICS_248 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_248 {0x0, 0x0, 0x0, 0x70, 0xb0, 0xd0, 0xe0, 0x0} + +/* ugrave (249) */ +#define NXFONT_METRICS_249 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_249 {0x40, 0x20, 0x0, 0x90, 0x90, 0x90, 0x70, 0x0} + +/* uacute (250) */ +#define NXFONT_METRICS_250 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_250 {0x20, 0x40, 0x0, 0x90, 0x90, 0x90, 0x70, 0x0} + +/* ucircumflex (251) */ +#define NXFONT_METRICS_251 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_251 {0x60, 0x90, 0x0, 0x90, 0x90, 0x90, 0x70, 0x0} + +/* udieresis (252) */ +#define NXFONT_METRICS_252 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_252 {0x0, 0x90, 0x0, 0x90, 0x90, 0x90, 0x70, 0x0} + +/* yacute (253) */ +#define NXFONT_METRICS_253 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_253 {0x20, 0x40, 0x0, 0x90, 0x90, 0x70, 0x90, 0x60} + +/* thorn (254) */ +#define NXFONT_METRICS_254 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_254 {0x0, 0x80, 0x80, 0xe0, 0x90, 0xe0, 0x80, 0x80} + +/* ydieresis (255) */ +#define NXFONT_METRICS_255 {1, 5, 8, 0, 0, 0} +#define NXFONT_BITMAP_255 {0x0, 0x90, 0x0, 0x90, 0x90, 0x70, 0x90, 0x60} + +#endif diff --git a/nuttx/include/nuttx/nx/nxfonts.h b/nuttx/include/nuttx/nx/nxfonts.h index f1aecb9e5..8e7289b2a 100644 --- a/nuttx/include/nuttx/nx/nxfonts.h +++ b/nuttx/include/nuttx/nx/nxfonts.h @@ -125,6 +125,12 @@ enum nx_fontid_e { FONTID_DEFAULT = 0 /* The default font */ +/* Monospace fonts */ + +#ifdef CONFIG_NXFONT_MONO5X8 + , FONTID_MONO5X8 = 18 /* The 5x8 monospace font */ +#endif + /* Sans Serif fonts */ #ifdef CONFIG_NXFONT_SANS17X22 diff --git a/nuttx/include/pthread.h b/nuttx/include/pthread.h index 5a08f13b6..5066275b4 100644 --- a/nuttx/include/pthread.h +++ b/nuttx/include/pthread.h @@ -41,15 +41,15 @@ ********************************************************************************/ #include /* Default settings */ -#include /* Compiler settings */ +#include /* Compiler settings, noreturn_function */ #include /* Needed for general types */ #include /* C99 fixed width integer types */ #include /* C99 boolean types */ +#include /* For getpid */ #include /* Needed for sem_t */ #include /* Needed for sigset_t */ #include /* Needed for struct timespec */ -#include /* For noreturn_function */ /******************************************************************************** * Compilation Switches diff --git a/nuttx/include/stdbool.h b/nuttx/include/stdbool.h index 9c16aee29..6c3302549 100644 --- a/nuttx/include/stdbool.h +++ b/nuttx/include/stdbool.h @@ -90,8 +90,8 @@ # define bool _Bool8 #endif -#define true 1 -#define false 0 +#define true (bool)1 +#define false (bool)0 #define __bool_true_false_are_defined 1 diff --git a/nuttx/tools/bdf-converter.c b/nuttx/tools/bdf-converter.c index b32209fcf..a03faa93e 100644 --- a/nuttx/tools/bdf-converter.c +++ b/nuttx/tools/bdf-converter.c @@ -43,6 +43,7 @@ * Included Files ****************************************************************************/ +#include #include #include #include -- cgit v1.2.3 From 247ad37c4bd0c27e3cf358df30fa29517f033260 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 21 Dec 2012 21:30:33 +0000 Subject: configs/sim/nxwm now uses kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5449 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 7 +- nuttx/arch/sim/Kconfig | 2 +- nuttx/configs/sim/README.txt | 83 ++-- nuttx/configs/sim/nxwm/appconfig | 40 -- nuttx/configs/sim/nxwm/defconfig | 854 ++++++++++++++++++++++++++------------- nuttx/include/pthread.h | 148 +++---- 6 files changed, 705 insertions(+), 429 deletions(-) delete mode 100644 nuttx/configs/sim/nxwm/appconfig diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c4a06af5e..04f180a8b 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3805,6 +3805,9 @@ * graphics/: Adds 5x8 monospace font. This tiny font is useful for graph labels and for small bitmapped display. Contributed by Petteri Aimonen. - * configs/stm3220g-eval/nxwm: Converted to use the kconfig-fronteds + * configs/stm3220g-eval/nxwm: Converted to use the kconfig-frontends configuration tool. - + * configs/sim/nxwm: Converted to use the kconfig-frontends configuration + tool. + * include/pthread.h: In sys/prctl.h because it is needed by + pthread_[set|get]name_np() diff --git a/nuttx/arch/sim/Kconfig b/nuttx/arch/sim/Kconfig index 331f61c79..dc3a85b54 100644 --- a/nuttx/arch/sim/Kconfig +++ b/nuttx/arch/sim/Kconfig @@ -50,7 +50,7 @@ config SIM_FRAMEBUFFER config SIM_X11FB bool "Use X11 window" default n - depends on NX && FB_CMAP + depends on NX ---help--- Use an X11 graphics window to simulate the graphics device" diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 032bb39b8..f1dfd0dd2 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -461,46 +461,57 @@ nxwm nuttx-code/NxWidgets/UnitTests/READEM.txt - NOTE: There is an issue with running this example under the - simulation. In the default configuration, this example will - run the NxConsole example which waits on readline() for console - intput. When it calls readline(), the whole system blocks - waiting from input from the host OS. So, in order to get - this example to run, you must comment out the readline call in - apps/nshlib/nsh_consolemain.c like: - - Index: nsh_consolemain.c - =================================================================== - --- nsh_consolemain.c (revision 4681) - +++ nsh_consolemain.c (working copy) - @@ -117,7 +117,8 @@ - /* Execute the startup script */ + NOTES + ----- + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. There is an issue with running this example under the + simulation. In the default configuration, this example will + run the NxConsole example which waits on readline() for console + input. When it calls readline(), the whole system blocks + waiting from input from the host OS. So, in order to get + this example to run, you must comment out the readline call in + apps/nshlib/nsh_consolemain.c like: + + Index: nsh_consolemain.c + =================================================================== + --- nsh_consolemain.c (revision 4681) + +++ nsh_consolemain.c (working copy) + @@ -117,7 +117,8 @@ + /* Execute the startup script */ - #ifdef CONFIG_NSH_ROMFSETC - - (void)nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); - +// REMOVE ME - +// (void)nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); - #endif + #ifdef CONFIG_NSH_ROMFSETC + - (void)nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); + +// REMOVE ME + +// (void)nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); + #endif - /* Then enter the command line parsing loop */ - @@ -130,7 +131,8 @@ - fflush(pstate->cn_outstream); + /* Then enter the command line parsing loop */ + @@ -130,7 +131,8 @@ + fflush(pstate->cn_outstream); - /* Get the next line of input */ - - - +sleep(2); // REMOVE ME - +#if 0 // REMOVE ME - ret = readline(pstate->cn_line, CONFIG_NSH_LINELEN, - INSTREAM(pstate), OUTSTREAM(pstate)); - if (ret > 0) - @@ -153,6 +155,7 @@ - "readline", NSH_ERRNO_OF(-ret)); - nsh_exit(&pstate->cn_vtbl, 1); - } - +#endif // REMOVE ME - } + /* Get the next line of input */ + - + +sleep(2); // REMOVE ME + +#if 0 // REMOVE ME + ret = readline(pstate->cn_line, CONFIG_NSH_LINELEN, + INSTREAM(pstate), OUTSTREAM(pstate)); + if (ret > 0) + @@ -153,6 +155,7 @@ + "readline", NSH_ERRNO_OF(-ret)); + nsh_exit(&pstate->cn_vtbl, 1); + } + +#endif // REMOVE ME + } - /* Clean up */ + /* Clean up */ ostest diff --git a/nuttx/configs/sim/nxwm/appconfig b/nuttx/configs/sim/nxwm/appconfig deleted file mode 100644 index 47c290dfe..000000000 --- a/nuttx/configs/sim/nxwm/appconfig +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# configs/sim/nxwm/appconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# The NSH Library - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - diff --git a/nuttx/configs/sim/nxwm/defconfig b/nuttx/configs/sim/nxwm/defconfig index 161322da8..6a295ef4f 100644 --- a/nuttx/configs/sim/nxwm/defconfig +++ b/nuttx/configs/sim/nxwm/defconfig @@ -1,158 +1,149 @@ -############################################################################ -# sim/nxwm/defconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture selection # -CONFIG_ARCH="sim" -CONFIG_ARCH_SIM=y -CONFIG_ARCH_BOARD="sim" -CONFIG_ARCH_BOARD_SIM=y +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set # -# Framebuffer driver options +# Customize Header Files # -CONFIG_FB_CMAP=n -CONFIG_FB_HWCURSOR=n -CONFIG_FB_HWCURSORIMAGE=n -#CONFIG_FB_HWCURSORSIZE -#CONFIG_FB_TRANSPARENCY +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set # -# Simulated framebuffer configuration +# Debug Options # +# CONFIG_DEBUG is not set +CONFIG_DEBUG_SYMBOLS=y + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +CONFIG_ARCH_SIM=y +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="sim" +CONFIG_BOARD_LOOPSPERMSEC= + +# +# Simulation Configuration Options +# +# CONFIG_SIM_M32 is not set +# CONFIG_SIM_WALLTIME is not set +CONFIG_SIM_FRAMEBUFFER=y CONFIG_SIM_X11FB=y -CONFIG_SIM_FBWIDTH=480 +# CONFIG_SIM_X11NOSHM is not set CONFIG_SIM_FBHEIGHT=240 +CONFIG_SIM_FBWIDTH=480 CONFIG_SIM_FBBPP=32 # -# Simulated touchscreen configuration -# (Set both of the following to 'y' to enable) +# Architecture Options # -CONFIG_INPUT=n -CONFIG_SIM_TOUCHSCREEN=n +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +# CONFIG_ARCH_STACKDUMP is not set +# CONFIG_ENDIAN_BIG is not set # -# General OS setup +# Board Settings # -CONFIG_USER_ENTRYPOINT="nxwm_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEBUG_GRAPHICS=n -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=0 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=32 -CONFIG_START_YEAR=2012 -CONFIG_START_MONTH=5 -CONFIG_START_DAY=1 -CONFIG_JULIAN_TIME=n -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n -CONFIG_SDCLONE_DISABLE=y -CONFIG_SIG_SIGWORK=4 -CONFIG_SCHED_WORKQUEUE=n -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=8192 -CONFIG_SCHED_WAITPID=y -CONFIG_SCHED_ATEXIT=n -CONFIG_SCHED_ONEXIT=y +CONFIG_DRAM_START= +CONFIG_DRAM_SIZE= # -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. +# Boot options # -# There are certain dependency relationships in these -# features. +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + # -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. +# Board Selection # -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n -CONFIG_DISABLE_POLL=y +CONFIG_ARCH_BOARD_SIM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sim" # -# Misc libc settings +# Common Board Options # -CONFIG_NOPRINTF_FIELDWIDTH=n +CONFIG_NSH_MMCSDMINOR=0 # -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve sysem performance +# Board-Specific Options # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n # -# General build options +# RTOS Features # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_RAW_BINARY=n +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=32 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=5 +CONFIG_START_DAY=1 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_ATEXIT is not set +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_ONEXIT_MAX=1 +CONFIG_USER_ENTRYPOINT="nxwm_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +CONFIG_DISABLE_POSIX_TIMERS=y +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y # # Sizes of configurable things (0 disables) @@ -163,9 +154,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=16 CONFIG_NFILE_STREAMS=16 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=32 CONFIG_MQ_MAXMSGSIZE=48 CONFIG_MAX_WDOGPARMS=4 @@ -173,156 +161,371 @@ CONFIG_PREALLOC_WDOGS=32 CONFIG_PREALLOC_TIMERS=8 # -# Filesystem configuration +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_USERMAIN_STACKSIZE=8192 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=8192 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration # CONFIG_FS_FAT=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set CONFIG_FS_ROMFS=y # -# TCP/IP and UDP support via uIP +# System Logging # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_SYSLOG is not set # -# UIP Network Utilities +# Graphics Support # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +CONFIG_NX=y +CONFIG_NX_NPLANES=1 +# CONFIG_NX_WRITEONLY is not set # -# Graphics related configuration settings +# Supported Pixel Depths # -CONFIG_NX=y -CONFIG_NX_MULTIUSER=y -CONFIG_NX_NPLANES=1 CONFIG_NX_DISABLE_1BPP=y CONFIG_NX_DISABLE_2BPP=y CONFIG_NX_DISABLE_4BPP=y CONFIG_NX_DISABLE_8BPP=y CONFIG_NX_DISABLE_16BPP=y CONFIG_NX_DISABLE_24BPP=y -CONFIG_NX_DISABLE_32BPP=n -CONFIG_NX_PACKEDMSFIRST=n +# CONFIG_NX_DISABLE_32BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set + +# +# Input Devices +# CONFIG_NX_MOUSE=y CONFIG_NX_KBD=y -#CONFIG_NXTK_BORDERWIDTH=4 + +# +# Framed Window Borders +# +CONFIG_NXTK_BORDERWIDTH=4 CONFIG_NXTK_BORDERCOLOR1=0x005a96bd CONFIG_NXTK_BORDERCOLOR2=0x00233a49 CONFIG_NXTK_BORDERCOLOR3=0x00f8f8f8 -CONFIG_NXTK_AUTORAISE=n -CONFIG_NXFONT_SANS22X29=n +# CONFIG_NXTK_AUTORAISE is not set + +# +# Font Selections +# +CONFIG_NXFONTS_CHARBITS=7 +# CONFIG_NXFONT_SANS17X22 is not set +# CONFIG_NXFONT_SANS20X26 is not set CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37=n -CONFIG_NXFONT_SANS22X29B=n +# CONFIG_NXFONT_SANS22X29 is not set +# CONFIG_NXFONT_SANS28X37 is not set +# CONFIG_NXFONT_SANS39X48 is not set +# CONFIG_NXFONT_SANS17X23B is not set +# CONFIG_NXFONT_SANS20X27B is not set +# CONFIG_NXFONT_SANS22X29B is not set CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXFONT_SANS40X49B=n -CONFIG_NXFONT_SERIF22X29=n -CONFIG_NXFONT_SERIF29X37=n -CONFIG_NXFONT_SERIF38X48=n -CONFIG_NXFONT_SERIF22X28B=n -CONFIG_NXFONT_SERIF27X38B=n -CONFIG_NXFONT_SERIF38X49B=n -CONFIG_NXFONTS_CHARBITS=7 +# CONFIG_NXFONT_SANS40X49B is not set +# CONFIG_NXFONT_SERIF22X29 is not set +# CONFIG_NXFONT_SERIF29X37 is not set +# CONFIG_NXFONT_SERIF38X48 is not set +# CONFIG_NXFONT_SERIF22X28B is not set +# CONFIG_NXFONT_SERIF27X38B is not set +# CONFIG_NXFONT_SERIF38X49B is not set +CONFIG_NXCONSOLE=y + +# +# NxConsole Output Text/Graphics Options +# +CONFIG_NXCONSOLE_BPP=32 +CONFIG_NXCONSOLE_CURSORCHAR=137 +CONFIG_NXCONSOLE_MXCHARS=256 +CONFIG_NXCONSOLE_CACHESIZE=16 +CONFIG_NXCONSOLE_LINESEPARATION=0 +# CONFIG_NXCONSOLE_NOWRAP is not set + +# +# NxConsole Input options +# +# CONFIG_NXCONSOLE_NXKBDIN is not set +CONFIG_NXCONSOLE_KBDBUFSIZE=16 +CONFIG_NXCONSOLE_NPOLLWAITERS=4 + +# +# NX Multi-user only options +# +CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 # -# NxWidgets / NxWM +# Memory Management # -# Use all defaults except -# 1. 32 bits-per-pixel -# 2. Need an especially big server stack size to work with X -# 3. Make the NxWidgets background color match the NxWM back color -# 4. Taskbar on the left -# 5. Bigger stack for NxConsole -# 6. No touchscreen +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set + # -CONFIG_NXWIDGETS_BPP=32 -CONFIG_NXWIDGETS_SERVERSTACK=16384 -CONFIG_NXWIDGETS_LISTENERSTACK=8192 -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=MKRGB(148,189,215) -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=MKRGB(206,227,241) -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=MKRGB(35,58,73) +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_NXCONSOLE_STACKSIZE=8192 -CONFIG_NXWM_UNITTEST=y -CONFIG_NXWM_TOUCHSCREEN=n +# +# Library Routines +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# NxConsole Configuration Settings: +# Basic CXX Support # -CONFIG_NXCONSOLE=y -CONFIG_NXCONSOLE_BPP=32 -CONFIG_NXCONSOLE_MXCHARS=256 +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +# CONFIG_HAVE_CXXINITIALIZE is not set +# CONFIG_CXX_NEWLONG is not set + # +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set # -# Settings for examples/uip +# Application Configuration # -CONFIG_EXAMPLES_UIP_IPADDR=0xc0a80080 -CONFIG_EXAMPLES_UIP_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n # -# Settings for examples/nettest +# Named Applications +# +# CONFIG_NAMEDAPP is not set + # -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set # -# Settings for examples/ostest +# Interpreters # -CONFIG_EXAMPLES_OSTEST_LOOPS=100 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 # -# Settings for apps/nshlib +# Interpreters # -CONFIG_NSH_BUILTIN_APPS=n +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=80 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_ROMFSETC=y -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 CONFIG_NSH_ROMFSMOUNTPT="/etc" CONFIG_NSH_INITSCRIPT="init.d/rcS" CONFIG_NSH_ROMFSDEVNO=1 @@ -331,81 +534,176 @@ CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FATSECTSIZE=512 CONFIG_NSH_FATNSECTORS=1024 CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set # -# Settings for examples/nx +# NxWidgets/NxWM # -CONFIG_EXAMPLES_NX_BUILTIN=n -CONFIG_EXAMPLES_NX_VPLANE=0 -#CONFIG_EXAMPLES_NX_BGCOLOR -#CONFIG_EXAMPLES_NX_COLOR1 -#CONFIG_EXAMPLES_NX_COLOR2 -#CONFIG_EXAMPLES_NX_TBCOLOR -#CONFIG_EXAMPLES_NX_FONTCOLOR -CONFIG_EXAMPLES_NX_BPP=CONFIG_SIM_FBBPP -CONFIG_EXAMPLES_NX_RAWWINDOWS=n -CONFIG_EXAMPLES_NX_STACKSIZE=8192 -CONFIG_EXAMPLES_NX_CLIENTPRIO=80 -CONFIG_EXAMPLES_NX_SERVERPRIO=120 -CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 +CONFIG_NXWIDGETS=y # -# Settings for examples/nxhello +# NX Server/Device Configuration # -CONFIG_EXAMPLES_NXHELLO_BUILTIN=y -CONFIG_EXAMPLES_NXHELLO_VPLANE=0 -#CONFIG_EXAMPLES_NXHELLO_BGCOLOR -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -#CONFIG_EXAMPLES_NXHELLO_FONTCOLOR -CONFIG_EXAMPLES_NXHELLO_BPP=CONFIG_SIM_FBBPP -CONFIG_EXAMPLES_NXHELLO_EXTERNINIT=n +# CONFIG_NXWIDGETS_FLICKERFREE is not set +CONFIG_NXWIDGETS_DEVNO=0 +CONFIG_NXWIDGETS_VPLANE=0 +CONFIG_NXWIDGETS_SERVERPRIO=51 +CONFIG_NXWIDGETS_SERVERSTACK=16384 +CONFIG_NXWIDGETS_CLIENTPRIO=50 +CONFIG_NXWIDGETS_LISTENERPRIO=50 +CONFIG_NXWIDGETS_LISTENERSTACK=8192 +# CONFIG_NXWIDGETS_EXTERNINIT is not set +# CONFIG_NXWIDGET_EVENTWAIT is not set # -# Settings for examples/nxlines +# NXWidget Configuration # -CONFIG_EXAMPLES_NXLINES_VPLANE=0 -#CONFIG_EXAMPLES_NXLINES_BGCOLOR -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16 -#CONFIG_EXAMPLES_NXLINES_LINECOLOR -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 -#CONFIG_EXAMPLES_NXLINES_BORDERCOLOR -#CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR -CONFIG_EXAMPLES_NXLINES_BPP=CONFIG_SIM_FBBPP -CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n +CONFIG_NXWIDGETS_BPP=32 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 # -# Settings for examples/touchscreen +# NXWidget Default Values # -CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN=y -CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 -CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" -CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25 +# CONFIG_NXWIDGETS_SYSTEM_CUSTOM_FONTID is not set +CONFIG_NXWIDGETS_TNXARRAY_INITIALSIZE=16 +CONFIG_NXWIDGETS_TNXARRAY_SIZEINCREMENT=8 +# CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS is not set +# CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS is not set +# CONFIG_NXWIDGETS_CUSTOM_TEXTCOLORS is not set +CONFIG_NXWIDGETS_TRANSPARENT_COLOR=0x0 # -# Settings for examples/mount +# Keypad behavior # -CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" -#CONFIG_EXAMPLES_MOUNT_NSECTORS=2048 -#CONFIG_EXAMPLES_MOUNT_SECTORSIZE=512 -#CONFIG_EXAMPLES_MOUNT_RAMDEVNO=1 +CONFIG_NXWIDGETS_FIRST_REPEAT_TIME=500 +CONFIG_NXWIDGETS_CONTINUE_REPEAT_TIME=200 +CONFIG_NXWIDGETS_DOUBLECLICK_TIME=350 +CONFIG_NXWIDGETS_KBDBUFFER_SIZE=16 +CONFIG_NXWIDGETS_CURSORCONTROL_SIZE=4 +# CONFIG_NXWIDGET_MEMMONITOR is not set +CONFIG_NXWM=y # -# Stack and heap information +# General settings # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=8192 -CONFIG_USERMAIN_STACKSIZE=8192 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= +# CONFIG_NXWM_SYSTEM_CUSTOM_FONTID is not set +CONFIG_NXWM_UNITTEST=y + +# +# Color configuration +# +# CONFIG_NXWM_CUSTOM_FILLCOLORS is not set +# CONFIG_NXWM_CUSTOM_EDGECOLORS is not set +# CONFIG_NXWM_CUSTOM_TEXTCOLORS is not set + +# +# Horizontal and vertical spacing of icons in the task bar +# +CONFIG_NXWM_TASKBAR_VSPACING=2 +CONFIG_NXWM_TASKBAR_HSPACING=2 +# CONFIG_NXWM_TASKBAR_TOP is not set +# CONFIG_NXWM_TASKBAR_BOTTOM is not set +CONFIG_NXWM_TASKBAR_LEFT=y +# CONFIG_NXWM_TASKBAR_RIGHT is not set +# CONFIG_NXWM_CUSTOM_TASKBAR_WIDTH is not set +# CONFIG_NXWM_DISABLE_MINIMIZE is not set + +# +# Tool Bar Configuration +# +# CONFIG_NXWM_CUSTOM_TOOLBAR_HEIGHT is not set + +# +# Background Image +# +# CONFIG_NXWM_DISABLE_BACKGROUND_IMAGE is not set +CONFIG_NXWM_BACKGROUND_IMAGE="" + +# +# Start Window Configuration +# + +# +# Horizontal and vertical spacing of icons in the task bar +# +CONFIG_NXWM_STARTWINDOW_VSPACING=4 +CONFIG_NXWM_STARTWINDOW_HSPACING=4 +# CONFIG_NXWM_CUSTOM_STARTWINDOW_ICON is not set +CONFIG_NXWM_STARTWINDOW_MQNAME="/dev/nxwm" +CONFIG_NXWM_STARTWINDOW_MXMSGS=32 +CONFIG_NXWM_STARTWINDOW_MXMPRIO=42 +CONFIG_NXWM_STARTWINDOW_PRIO=50 +CONFIG_NXWM_STARTWINDOW_STACKSIZE=2048 + +# +# NxConsole Window Configuration +# +CONFIG_NXWM_NXCONSOLE_PRIO=50 +CONFIG_NXWM_NXCONSOLE_STACKSIZE=8192 +# CONFIG_NXWM_NXCONSOLE_CUSTOM_COLORS is not set +# CONFIG_NXWM_NXCONSOLE_CUSTOM_FONTID is not set +# CONFIG_NXWM_CUSTOM_NXCONSOLE_ICON is not set +# CONFIG_NXWM_TOUCHSCREEN is not set +# CONFIG_NXWM_KEYBOARD is not set + +# +# Calibration display settings +# +# CONFIG_NXWM_CALIBRATION_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_CALIBRATION_ICON is not set +CONFIG_NXWM_CALIBRATION_SIGNO=5 +CONFIG_NXWM_CALIBRATION_LISTENERPRIO=50 +CONFIG_NXWM_CALIBRATION_LISTENERSTACK=2048 # -# Maintain legacy build behavior (revisit) +# Hex Calculator display settings # +# CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS is not set +# CONFIG_NXWM_CUSTOM_HEXCALCULATOR_ICON is not set +# CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID is not set -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/include/pthread.h b/nuttx/include/pthread.h index 5066275b4..a98b9aaaa 100644 --- a/nuttx/include/pthread.h +++ b/nuttx/include/pthread.h @@ -44,6 +44,8 @@ #include /* Compiler settings, noreturn_function */ #include /* Needed for general types */ +#include /* Needed by pthread_[set|get]name_np */ + #include /* C99 fixed width integer types */ #include /* C99 boolean types */ #include /* For getpid */ @@ -58,10 +60,11 @@ /* Standard POSIX switches */ #ifndef _POSIX_THREADS -#define _POSIX_THREADS +# define _POSIX_THREADS #endif + #ifndef _POSIX_THREAD_ATTR_STACKSIZE -#define _POSIX_THREAD_ATTR_STACKSIZE +# define _POSIX_THREAD_ATTR_STACKSIZE #endif /******************************************************************************** @@ -153,10 +156,8 @@ ********************************************************************************/ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* pthread-specific types */ @@ -245,28 +246,29 @@ struct sched_param; /* Defined in sched.h */ * the individual attributes used by a given implementation. */ -EXTERN int pthread_attr_init(FAR pthread_attr_t *attr); +int pthread_attr_init(FAR pthread_attr_t *attr); /* An attributes object can be deleted when it is no longer needed. */ -EXTERN int pthread_attr_destroy(pthread_attr_t *attr); +int pthread_attr_destroy(pthread_attr_t *attr); /* Set or obtain the default scheduling algorithm */ -EXTERN int pthread_attr_setschedpolicy(FAR pthread_attr_t *attr, int policy); -EXTERN int pthread_attr_getschedpolicy(FAR pthread_attr_t *attr, int *policy); -EXTERN int pthread_attr_setschedparam(FAR pthread_attr_t *attr, - FAR const struct sched_param *param); -EXTERN int pthread_attr_getschedparam(FAR pthread_attr_t *attr, - FAR struct sched_param *param); -EXTERN int pthread_attr_setinheritsched(FAR pthread_attr_t *attr, int inheritsched); -EXTERN int pthread_attr_getinheritsched(FAR const pthread_attr_t *attr, - FAR int *inheritsched); +int pthread_attr_setschedpolicy(FAR pthread_attr_t *attr, int policy); +int pthread_attr_getschedpolicy(FAR pthread_attr_t *attr, int *policy); +int pthread_attr_setschedparam(FAR pthread_attr_t *attr, + FAR const struct sched_param *param); +int pthread_attr_getschedparam(FAR pthread_attr_t *attr, + FAR struct sched_param *param); +int pthread_attr_setinheritsched(FAR pthread_attr_t *attr, + int inheritsched); +int pthread_attr_getinheritsched(FAR const pthread_attr_t *attr, + FAR int *inheritsched); /* Set or obtain the default stack size */ -EXTERN int pthread_attr_setstacksize(FAR pthread_attr_t *attr, long stacksize); -EXTERN int pthread_attr_getstacksize(FAR pthread_attr_t *attr, long *stackaddr); +int pthread_attr_setstacksize(FAR pthread_attr_t *attr, long stacksize); +int pthread_attr_getstacksize(FAR pthread_attr_t *attr, long *stackaddr); /* To create a thread object and runnable thread, a routine must be specified * as the new thread's start routine. An argument may be passed to this @@ -275,34 +277,33 @@ EXTERN int pthread_attr_getstacksize(FAR pthread_attr_t *attr, long *stackaddr); * about the kind of thread being created. */ -EXTERN int pthread_create(FAR pthread_t *thread, FAR pthread_attr_t *attr, - pthread_startroutine_t startroutine, - pthread_addr_t arg); +int pthread_create(FAR pthread_t *thread, FAR pthread_attr_t *attr, + pthread_startroutine_t startroutine, pthread_addr_t arg); /* A thread object may be "detached" to specify that the return value and * completion status will not be requested. */ -EXTERN int pthread_detach(pthread_t thread); +int pthread_detach(pthread_t thread); /* A thread may terminate it's own execution or the execution of another * thread. */ -EXTERN void pthread_exit(pthread_addr_t value) noreturn_function; -EXTERN int pthread_cancel(pthread_t thread); -EXTERN int pthread_setcancelstate(int state, FAR int *oldstate); -EXTERN void pthread_testcancel(void); +void pthread_exit(pthread_addr_t value) noreturn_function; +int pthread_cancel(pthread_t thread); +int pthread_setcancelstate(int state, FAR int *oldstate); +void pthread_testcancel(void); /* A thread can await termination of another thread and retrieve the return * value of the thread. */ -EXTERN int pthread_join(pthread_t thread, FAR pthread_addr_t *value); +int pthread_join(pthread_t thread, FAR pthread_addr_t *value); /* A thread may tell the scheduler that its processor can be made available. */ -EXTERN void pthread_yield(void); +void pthread_yield(void); /* A thread may obtain a copy of its own thread handle. */ @@ -314,91 +315,94 @@ EXTERN void pthread_yield(void); /* Thread scheduling parameters */ -EXTERN int pthread_getschedparam(pthread_t thread, FAR int *policy, - FAR struct sched_param *param); -EXTERN int pthread_setschedparam(pthread_t thread, int policy, - FAR const struct sched_param *param); -EXTERN int pthread_setschedprio(pthread_t thread, int prio); +int pthread_getschedparam(pthread_t thread, FAR int *policy, + FAR struct sched_param *param); +int pthread_setschedparam(pthread_t thread, int policy, + FAR const struct sched_param *param); +int pthread_setschedprio(pthread_t thread, int prio); /* Thread-specific Data Interfaces */ -EXTERN int pthread_key_create(FAR pthread_key_t *key, - CODE void (*destructor)(FAR void*)); -EXTERN int pthread_setspecific(pthread_key_t key, FAR void *value); -EXTERN FAR void *pthread_getspecific(pthread_key_t key); -EXTERN int pthread_key_delete(pthread_key_t key); +int pthread_key_create(FAR pthread_key_t *key, + CODE void (*destructor)(FAR void*)); +int pthread_setspecific(pthread_key_t key, FAR void *value); +FAR void *pthread_getspecific(pthread_key_t key); +int pthread_key_delete(pthread_key_t key); /* Create, operate on, and destroy mutex attributes. */ -EXTERN int pthread_mutexattr_init(FAR pthread_mutexattr_t *attr); -EXTERN int pthread_mutexattr_destroy(FAR pthread_mutexattr_t *attr); -EXTERN int pthread_mutexattr_getpshared(FAR pthread_mutexattr_t *attr, FAR int *pshared); -EXTERN int pthread_mutexattr_setpshared(FAR pthread_mutexattr_t *attr, int pshared); +int pthread_mutexattr_init(FAR pthread_mutexattr_t *attr); +int pthread_mutexattr_destroy(FAR pthread_mutexattr_t *attr); +int pthread_mutexattr_getpshared(FAR pthread_mutexattr_t *attr, + FAR int *pshared); +int pthread_mutexattr_setpshared(FAR pthread_mutexattr_t *attr, + int pshared); #ifdef CONFIG_MUTEX_TYPES -EXTERN int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type); -EXTERN int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); +int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type); +int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); #endif /* The following routines create, delete, lock and unlock mutexes. */ -EXTERN int pthread_mutex_init(FAR pthread_mutex_t *mutex, FAR pthread_mutexattr_t *attr); -EXTERN int pthread_mutex_destroy(FAR pthread_mutex_t *mutex); -EXTERN int pthread_mutex_lock(FAR pthread_mutex_t *mutex); -EXTERN int pthread_mutex_trylock(FAR pthread_mutex_t *mutex); -EXTERN int pthread_mutex_unlock(FAR pthread_mutex_t *mutex); +int pthread_mutex_init(FAR pthread_mutex_t *mutex, + FAR pthread_mutexattr_t *attr); +int pthread_mutex_destroy(FAR pthread_mutex_t *mutex); +int pthread_mutex_lock(FAR pthread_mutex_t *mutex); +int pthread_mutex_trylock(FAR pthread_mutex_t *mutex); +int pthread_mutex_unlock(FAR pthread_mutex_t *mutex); /* Operations on condition variables */ -EXTERN int pthread_condattr_init(FAR pthread_condattr_t *attr); -EXTERN int pthread_condattr_destroy(FAR pthread_condattr_t *attr); +int pthread_condattr_init(FAR pthread_condattr_t *attr); +int pthread_condattr_destroy(FAR pthread_condattr_t *attr); /* A thread can create and delete condition variables. */ -EXTERN int pthread_cond_init(FAR pthread_cond_t *cond, FAR pthread_condattr_t *attr); -EXTERN int pthread_cond_destroy(FAR pthread_cond_t *cond); +int pthread_cond_init(FAR pthread_cond_t *cond, FAR pthread_condattr_t *attr); +int pthread_cond_destroy(FAR pthread_cond_t *cond); /* A thread can signal to and broadcast on a condition variable. */ -EXTERN int pthread_cond_broadcast(FAR pthread_cond_t *cond); -EXTERN int pthread_cond_signal(FAR pthread_cond_t *cond); +int pthread_cond_broadcast(FAR pthread_cond_t *cond); +int pthread_cond_signal(FAR pthread_cond_t *cond); /* A thread can wait for a condition variable to be signalled or broadcast. */ -EXTERN int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex); +int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex); /* A thread can perform a timed wait on a condition variable. */ -EXTERN int pthread_cond_timedwait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex, - FAR const struct timespec *abstime); +int pthread_cond_timedwait(FAR pthread_cond_t *cond, + FAR pthread_mutex_t *mutex, + FAR const struct timespec *abstime); /* Barrier attributes */ -EXTERN int pthread_barrierattr_destroy(FAR pthread_barrierattr_t *attr); -EXTERN int pthread_barrierattr_init(FAR pthread_barrierattr_t *attr); -EXTERN int pthread_barrierattr_getpshared(FAR const pthread_barrierattr_t *attr, - FAR int *pshared); -EXTERN int pthread_barrierattr_setpshared(FAR pthread_barrierattr_t *attr, - int pshared); +int pthread_barrierattr_destroy(FAR pthread_barrierattr_t *attr); +int pthread_barrierattr_init(FAR pthread_barrierattr_t *attr); +int pthread_barrierattr_getpshared(FAR const pthread_barrierattr_t *attr, + FAR int *pshared); +int pthread_barrierattr_setpshared(FAR pthread_barrierattr_t *attr, + int pshared); /* Barriers */ -EXTERN int pthread_barrier_destroy(FAR pthread_barrier_t *barrier); -EXTERN int pthread_barrier_init(FAR pthread_barrier_t *barrier, +int pthread_barrier_destroy(FAR pthread_barrier_t *barrier); +int pthread_barrier_init(FAR pthread_barrier_t *barrier, FAR const pthread_barrierattr_t *attr, unsigned int count); -EXTERN int pthread_barrier_wait(FAR pthread_barrier_t *barrier); +int pthread_barrier_wait(FAR pthread_barrier_t *barrier); /* Pthread initialization */ -EXTERN int pthread_once(FAR pthread_once_t *once_control, +int pthread_once(FAR pthread_once_t *once_control, CODE void (*init_routine)(void)); /* Pthread signal management APIs */ -EXTERN int pthread_kill(pthread_t thread, int sig); -EXTERN int pthread_sigmask(int how, FAR const sigset_t *set, FAR sigset_t *oset); +int pthread_kill(pthread_t thread, int sig); +int pthread_sigmask(int how, FAR const sigset_t *set, FAR sigset_t *oset); -#undef EXTERN #ifdef __cplusplus } #endif -- cgit v1.2.3 From e975043dd3f56765a2a0292784666b2246ea6211 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 22 Dec 2012 16:47:02 +0000 Subject: Add tools/kconfig.bat git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5450 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 + nuttx/Kconfig | 2 +- nuttx/Makefile.win | 17 +++--- nuttx/README.txt | 136 ++++++++++++++++++++++++++++++++---------------- nuttx/tools/README.txt | 30 +++++++++++ nuttx/tools/kconfig.bat | 131 ++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 265 insertions(+), 53 deletions(-) create mode 100755 nuttx/tools/kconfig.bat diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 04f180a8b..56edf9487 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3811,3 +3811,5 @@ tool. * include/pthread.h: In sys/prctl.h because it is needed by pthread_[set|get]name_np() + * tools/kconfig.bat: Kludge to run kconfig-frontends from a DOS shell. + diff --git a/nuttx/Kconfig b/nuttx/Kconfig index 10d624efb..2c8c9b26e 100644 --- a/nuttx/Kconfig +++ b/nuttx/Kconfig @@ -7,7 +7,7 @@ mainmenu "Nuttx/$ARCH Configuration" config APPSDIR string - option env="APPSDIR" + default "../apps" # This is a temporary kludge to let the build system know that we are using the new # configuration system diff --git a/nuttx/Makefile.win b/nuttx/Makefile.win index 34da12ad0..fcf971d32 100644 --- a/nuttx/Makefile.win +++ b/nuttx/Makefile.win @@ -252,7 +252,7 @@ LINKLIBS = $(patsubst lib\\%,%,$(NUTTXLIBS)) BIN = nuttx$(EXEEXT) all: $(BIN) -.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean +.PHONY: context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean # Target used to copy include\nuttx\math.h. If CONFIG_ARCH_MATH_H is # defined, then there is an architecture specific math.h header file @@ -647,14 +647,17 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT) # location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See # misc\tools\README.txt for additional information. -config: - $(Q) APPSDIR=${CONFIG_APPS_DIR} conf Kconfig +configenv: + $(Q) set APPSDIR=${CONFIG_APPS_DIR} -oldconfig: - $(Q) APPSDIR=${CONFIG_APPS_DIR} conf --oldconfig Kconfig +config: configenv + $(Q) conf Kconfig -menuconfig: - $(Q) APPSDIR=${CONFIG_APPS_DIR} mconf Kconfig +oldconfig: configenv + $(Q) conf --oldconfig Kconfig + +menuconfig: configenv + $(Q) mconf Kconfig # export # diff --git a/nuttx/README.txt b/nuttx/README.txt index b9210277e..b71012cd8 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -10,6 +10,7 @@ README o Configuring NuttX - Instantiating "Canned" Configurations - NuttX Configuration Tool + - NuttX Configuration Tool from DOS o Toolchains - Cross-Development Toolchains - NuttX Buildroot Toolchain @@ -249,7 +250,6 @@ easier. It is used as follows: cd ${TOPDIR}/tools ./configure.sh / - NuttX Configuration Tool ------------------------ @@ -292,6 +292,52 @@ NuttX Configuration Tool install 'mconf', make certain that your PATH variable includes a path to that installation directory. +NuttX Configuration Tool from DOS +--------------------------------- + +Recent versions of NuttX support building NuttX from a native Windows +CMD.exe shell (see "Native Windows Build" below). But kconfig-frontends +is a Linux tool. There have been some successes building a Windows +native version of the kconfig-frontends tool, but that is not ready +for prime time. + +At this point, there are only a few options for the Windows user: + + 1. You can run the configuration tool using Cygwin. However, the + Cygwin Makefile.win will complain so to do this will, you have + to manually edit the .config file: + + a. Delete the line: CONFIG_WINDOWS_NATIVE=y + b. Change the apps/ directory path, CONFIG_APPS_DIR to use Unix + style delimiters. For example, change "..\apps" to "../apps" + + And of course, after you use the configuration tool you need to + restore CONFIG_WINDOWS_NATIVE=y and the correct CONFIG_APPS_DIR. + + 2) You can, with some effort, run the the Cygwin mconf tool directly + in the CMD.exe shell. In this case, you do not have to modify the + .config file, but there are other complexities: + + a. You need to temporarily set the Cgywin directories in the PATH + variable then run mconf manually like: + + mconf Kconfig + + There is a Windows bacht file at tools/kconfig.bat that automates + these steps: + + tools/kconfig menuconfig + + b. There is an issue with accessing DOS environment variables from + the Cygwin mconf running in the CMD.exe shell. The following + change to the top-level Kconfig file seems to work around these + problems: + + config APPSDIR + string + - option env="APPSDIR" + + default "../apps" + TOOLCHAINS ^^^^^^^^^^ @@ -523,68 +569,68 @@ Native Windows Build Installing GNUWin32 ------------------- -The Windows native build will depend upon a few Unix-like tools that can be -provided either by MSYS or GNUWin32. The GNUWin32 are available from -http://gnuwin32.sourceforge.net/. GNUWin32 provides ports of tools with a -GPL or similar open source license to modern MS-Windows (Microsoft Windows -2000 / XP / 2003 / Vista / 2008 / 7). See -http://gnuwin32.sourceforge.net/packages.html for a list of all of the tools -available in the GNUWin32 package. + The Windows native build will depend upon a few Unix-like tools that can be + provided either by MSYS or GNUWin32. The GNUWin32 are available from + http://gnuwin32.sourceforge.net/. GNUWin32 provides ports of tools with a + GPL or similar open source license to modern MS-Windows (Microsoft Windows + 2000 / XP / 2003 / Vista / 2008 / 7). See + http://gnuwin32.sourceforge.net/packages.html for a list of all of the tools + available in the GNUWin32 package. -The SourceForge project is located here: -http://sourceforge.net/projects/gnuwin32/. The project is still being -actively supported (although some of the Windows ports have gotten very old). + The SourceForge project is located here: + http://sourceforge.net/projects/gnuwin32/. The project is still being + actively supported (although some of the Windows ports have gotten very old). -Some commercial toolchains include a subset of the GNUWin32 tools in the -installation. My recommendation is that you download the GNUWin32 tools -directly from the sourceforge.net website so that you will know what you are -using and can reproduce your build environment. + Some commercial toolchains include a subset of the GNUWin32 tools in the + installation. My recommendation is that you download the GNUWin32 tools + directly from the sourceforge.net website so that you will know what you are + using and can reproduce your build environment. -GNUWin32 Installation Steps: + GNUWin32 Installation Steps: -The following steps will download and execute the GNUWin32 installer. + The following steps will download and execute the GNUWin32 installer. -1. Download GetGNUWin32-x.x.x.exe from - http://sourceforge.net/projects/getgnuwin32/files/. This is the - installer. The current version as of this writing is 0.6.3. + 1. Download GetGNUWin32-x.x.x.exe from + http://sourceforge.net/projects/getgnuwin32/files/. This is the + installer. The current version as of this writing is 0.6.3. -2. Run the installer. + 2. Run the installer. -3. Accept the license. + 3. Accept the license. -4. Select the installation directory. My recommendation is the - directory that contains this README file (). + 4. Select the installation directory. My recommendation is the + directory that contains this README file (). -5. After running GetGNUWin32-0.x.x.exe, you will have a new directory - /GetGNUWin32 + 5. After running GetGNUWin32-0.x.x.exe, you will have a new directory + /GetGNUWin32 -Note the the GNUWin32 installer didn't install GNUWin32. Instead, it -installed another, smarter downloader. That downloader is the GNUWin32 -package management tool developed by the Open SSL project. + Note the the GNUWin32 installer didn't install GNUWin32. Instead, it + installed another, smarter downloader. That downloader is the GNUWin32 + package management tool developed by the Open SSL project. -The following steps probably should be performed from inside a DOS shell. + The following steps probably should be performed from inside a DOS shell. -6. Change to the directory created by GetGNUWin32-x.x.x.exe + 6. Change to the directory created by GetGNUWin32-x.x.x.exe - cd GetGNUWin32 + cd GetGNUWin32 -7. Execute the download.bat script. The download.bat script will download - about 446 packages! Enough to have a very complete Linux-like environment - under the DOS shell. This will take awhile. This step only downloads - the packages and the next step will install the packages. + 7. Execute the download.bat script. The download.bat script will download + about 446 packages! Enough to have a very complete Linux-like environment + under the DOS shell. This will take awhile. This step only downloads + the packages and the next step will install the packages. - download + download -8. This step will install the downloaded packages. The argument of the - install.bat script is the installation location. C:\gnuwin32 is the - standard install location: + 8. This step will install the downloaded packages. The argument of the + install.bat script is the installation location. C:\gnuwin32 is the + standard install location: - install C:\gnuwin32 + install C:\gnuwin32 -NOTE: This installation step will install *all* GNUWin32 packages... far -more than you will ever need. If disc space is a problem for you, you might -need to perform a manual installation of the individual ZIP files that you -will find in the /GetGNUWin32/packages directory. + NOTE: This installation step will install *all* GNUWin32 packages... far + more than you will ever need. If disc space is a problem for you, you might + need to perform a manual installation of the individual ZIP files that you + will find in the /GetGNUWin32/packages directory. CYGWIN BUILD PROBLEMS ^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/tools/README.txt b/nuttx/tools/README.txt index 2b9ac61f4..fc0332212 100644 --- a/nuttx/tools/README.txt +++ b/nuttx/tools/README.txt @@ -413,6 +413,36 @@ unlink.bat NTFS mklink.exe command instead of copying files. That logic, however, has not been verified as of this writing. +kconfig.bat +----------- + + Recent versions of NuttX support building NuttX from a native Windows + CMD.exe shell. But kconfig-frontends is a Linux tool and is not yet + available in the pure CMD.exe environment. At this point, there are + only a few options for the Windows user (see the top-level README.txt + file). + + You can, with some effort, run the the Cygwin mconf tool directly + in the CMD.exe shell. In this case, you do not have to modify the + .config file, but there are other complexities: You need to + temporarily set the Cgywin directories in the PATH variable and + then run mconf outside of the Make system. + + kconfig.bat is a Windows batch file at tools/kconfig.bat that automates + these steps. It is used from the top-level NuttX directory like: + + tools/kconfig menuconfig + + NOTE: There is an currently an issue with accessing DOS environment + variables from the Cygwin mconf running in the CMD.exe shell. The + following change to the top-level Kconfig file seems to work around + these problems: + + config APPSDIR + string + - option env="APPSDIR" + + default "../apps" + mkimage.sh ---------- diff --git a/nuttx/tools/kconfig.bat b/nuttx/tools/kconfig.bat new file mode 100755 index 000000000..65ab60506 --- /dev/null +++ b/nuttx/tools/kconfig.bat @@ -0,0 +1,131 @@ +@echo off + +rem tools/kconfig.bat +rem +rem Copyright (C) 2012 Gregory Nutt. All rights reserved. +rem Author: Gregory Nutt +rem +rem Redistribution and use in source and binary forms, with or without +rem modification, are permitted provided that the following conditions +rem are met: +rem +rem 1. Redistributions of source code must retain the above copyright +rem notice, this list of conditions and the following disclaimer. +rem 2. Redistributions in binary form must reproduce the above copyright +rem notice, this list of conditions and the following disclaimer in +rem the documentation and/or other materials provided with the +rem distribution. +rem 3. Neither the name NuttX nor the names of its contributors may be +rem used to endorse or promote products derived from this software +rem without specific prior written permission. +rem +rem THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +rem "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +rem LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +rem FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +rem COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +rem INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +rem BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +rem OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +rem AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +rem LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +rem ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +rem POSSIBILITY OF SUCH DAMAGE. +rem + +rem Remember the state of the PATH variable on entry + +set oldpath=%PATH% + +rem Handle command line options + +set action=%1 +shift +if "%action%"=="" goto :MissingArgument + +set appsdir=..\apps +set cygwindir=C:\Cygwin + +:ArgLoop + +if "%1"=="" goto :CheckArguments + +if "%1"=="-a" ( + shift + set appsdir=%1 + goto :NextArg +) + +if "%1"=="-c" ( + shift + set cygwindir=%1 + goto :NextArg +) + +echo ERROR: Unrecognized option: %1 +goto :ShowUsage + +:NextArg +shift +goto :ArgLoop + +rem Verify that all of the paths are valid + +:CheckArguments +if exist "%appsdir%" goto :CheckCygwinDir + +echo ERROR: %appsdir% does not exist +goto :ShowUsage + +:CheckCygwinDir + +if exist "%cygwindir%" goto :SetPath + +echo ERROR: %cygwindir% does not exist +goto :ShowUsage + +rem Setup some required environment variables and PATH settings + +:SetPath +set PATH=%cygwindir%\usr\local\bin;%cygwindir%\usr\bin;%cygwindir%\bin;%PATH% +set APPSDIR=%appsdir% + +rem Execute the requested action + +if "%action%"=="config" goto :DoConfig +if "%action%"=="oldconfig" goto :DoOldConfig +if "%action%"=="menuconfig" goto :DoMenuConfig + +echo ERROR: Unrecognized action: %action% +goto :ShowUsage + +:DoConfig +conf Kconfig +goto End + +:DoOldConfig +conf --oldconfig Kconfig +goto End + +:DoMenuConfig +mconf Kconfig +goto End + +:MissingArgument + +echo ERROR: Missing required argument + +:ShowUsage +echo USAGE: %0 ^ [-a ^] [-c ^] +echo Where: +echo ^ is one of config, oldconf, or menuconfig +echo ^ is the relative path to the apps\ directory. +echo This defaults to ..\apps +echo ^ is the relative path to the Cygwin installation +echo directory. This defaults to C:\Cygwin + +rem Restore the original PATH settings + +:End +set PATH=%oldpath% + -- cgit v1.2.3 From f2a0267b0724206a9aa20b4c0caba36b3eecc3fe Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 22 Dec 2012 16:51:01 +0000 Subject: Fix errors and omissions in last checkin git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5451 42af7a65-404d-4744-a932-0658087f49c3 --- misc/tools/kconfig-language.txt | 2 +- nuttx/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/misc/tools/kconfig-language.txt b/misc/tools/kconfig-language.txt index 44e2649fb..a686f9cd6 100644 --- a/misc/tools/kconfig-language.txt +++ b/misc/tools/kconfig-language.txt @@ -117,7 +117,7 @@ applicable everywhere (see syntax). This attribute is only applicable to menu blocks, if the condition is false, the menu block is not displayed to the user (the symbols contained there can still be selected by other symbols, though). It is - similar to a conditional "prompt" attribude for individual menu + similar to a conditional "prompt" attribute for individual menu entries. Default value of "visible" is true. - numerical ranges: "range" ["if" ] diff --git a/nuttx/Kconfig b/nuttx/Kconfig index 2c8c9b26e..10d624efb 100644 --- a/nuttx/Kconfig +++ b/nuttx/Kconfig @@ -7,7 +7,7 @@ mainmenu "Nuttx/$ARCH Configuration" config APPSDIR string - default "../apps" + option env="APPSDIR" # This is a temporary kludge to let the build system know that we are using the new # configuration system -- cgit v1.2.3 From c62d3d93deef9ec14e80c3a96d70f846deeff66e Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 23 Dec 2012 17:32:41 +0000 Subject: Mostly costmetic updates git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5452 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/Documentation/NuttX.html | 15 +++++------- nuttx/README.txt | 24 +++++++++++-------- nuttx/arch/arm/src/arm/up_doirq.c | 8 ++++--- nuttx/arch/arm/src/armv7-m/up_doirq.c | 8 ++++--- nuttx/arch/avr/src/avr/up_doirq.c | 8 ++++--- nuttx/arch/avr/src/avr32/up_doirq.c | 8 ++++--- nuttx/arch/hc/src/common/up_doirq.c | 8 ++++--- nuttx/arch/mips/src/mips32/up_doirq.c | 8 ++++--- nuttx/arch/sh/src/common/up_doirq.c | 9 ++++++++ nuttx/arch/z16/src/common/up_doirq.c | 9 ++++++++ nuttx/arch/z80/include/z80/chip.h | 6 ++--- nuttx/arch/z80/src/common/up_internal.h | 41 +++++++++++++++------------------ nuttx/arch/z80/src/ez80/switch.h | 26 ++++++++++++--------- nuttx/arch/z80/src/z180/switch.h | 25 ++++++++++---------- nuttx/arch/z80/src/z8/switch.h | 28 ++++++++++++---------- nuttx/arch/z80/src/z80/switch.h | 26 ++++++++++++--------- 16 files changed, 149 insertions(+), 108 deletions(-) diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index f48994bab..84f298d3a 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -1078,7 +1078,6 @@ svn checkout -r5447 svn://svn.code.sf.net/p/nuttx/code/trunk nuttx-code svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code -

    Additional new features and extended functionality

    @@ -1244,7 +1243,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code This build: (1) Uses all Windows style paths, (2) Uses primarily Windows batch commands from CMD.exe, with (3) a few extensions from GNUWin32.

    - This capability should still be considered a work in progress because: (1) it has not been verfied on all targets and tools, and (2) still lacks some of the creature-comforts of the more mature environments (like a function configure.sh script and make menuconfig support). + This capability should still be considered a work in progress because: (1) It has not been verfied on all targets and tools, and (2) it still lacks some of the creature-comforts of the more mature environments (like a functional configure.sh script and make menuconfig support).

  • Example Windows native builds for STM32F4Discovery, eZ80, z16f, z8, Z80, and Z180. @@ -1890,8 +1889,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code

    • - These ports uses a GNU arm-nuttx-elf toolchain* under either Linux or Cygwin (with native Windows GNU - tools or Cygwin-based GNU tools). + These ports uses a GNU arm-nuttx-elf toolchain* under either Linux or Cygwin (with native Windows GNU tools or Cygwin-based GNU tools).

      @@ -1999,8 +1997,7 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code Atmel AT91SAM3U. This port uses the Atmel SAM3U-EK development board that features the AT91SAM3U4E MCU. - This port uses a GNU arm-nuttx-elf or arm-eabi toolchain* under either Linux or Cygwin (with native Windows GNU - tools or Cygwin-based GNU tools). + This port uses a GNU arm-nuttx-elf or arm-eabi toolchain* under either Linux or Cygwin (with native Windows GNU tools or Cygwin-based GNU tools).

        @@ -2884,7 +2881,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1); Zilog z16f Microncontroller. This port use the Zilog z16f2800100zcog development kit and the Zilog ZDS-II Windows command line tools. - The development environment is Cygwin under WinXP. + The development environment is either Windows native or Cygwin under Windows.

          @@ -2914,7 +2911,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);

          Both boards are based on the eZ80F091 part and both use the Zilog ZDS-II Windows command line tools. - The development environment is Cygwin under WinXP. + The development environment is either Windows native or Cygwin under Windows.

            @@ -2946,7 +2943,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);

          and the Zilog ZDS-II Windows command line tools. - The development environment is Cygwin under WinXP. + The development environment is either Windows native or Cygwin under Windows.

            diff --git a/nuttx/README.txt b/nuttx/README.txt index b71012cd8..dc3c9fb67 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -10,7 +10,7 @@ README o Configuring NuttX - Instantiating "Canned" Configurations - NuttX Configuration Tool - - NuttX Configuration Tool from DOS + - NuttX Configuration Tool under DOS o Toolchains - Cross-Development Toolchains - NuttX Buildroot Toolchain @@ -292,16 +292,16 @@ NuttX Configuration Tool install 'mconf', make certain that your PATH variable includes a path to that installation directory. -NuttX Configuration Tool from DOS ---------------------------------- +NuttX Configuration Tool under DOS +---------------------------------- -Recent versions of NuttX support building NuttX from a native Windows -CMD.exe shell (see "Native Windows Build" below). But kconfig-frontends -is a Linux tool. There have been some successes building a Windows -native version of the kconfig-frontends tool, but that is not ready -for prime time. + Recent versions of NuttX support building NuttX from a native Windows + CMD.exe shell (see "Native Windows Build" below). But kconfig-frontends + is a Linux tool. There have been some successes building a Windows + native version of the kconfig-frontends tool, but that is not ready + for prime time. -At this point, there are only a few options for the Windows user: + At this point, there are only a few options for the Windows user: 1. You can run the configuration tool using Cygwin. However, the Cygwin Makefile.win will complain so to do this will, you have @@ -566,6 +566,12 @@ Native Windows Build http://www.mingw.org/. If you are using GNUWin32, then it is recommended the you not install the optional MSYS components as there may be conflicts. + This capability should still be considered a work in progress because: + (1) It has not been verfied on all targets and tools, and + (2) itstill lacks some of the creature-comforts of the more mature environments + (like a functional configure.sh script and 'make menuconfig' support. + See the section "NuttX Configuration Tool under DOS" above). + Installing GNUWin32 ------------------- diff --git a/nuttx/arch/arm/src/arm/up_doirq.c b/nuttx/arch/arm/src/arm/up_doirq.c index c82587fff..7cd1a6a1b 100644 --- a/nuttx/arch/arm/src/arm/up_doirq.c +++ b/nuttx/arch/arm/src/arm/up_doirq.c @@ -79,9 +79,11 @@ void up_doirq(int irq, uint32_t *regs) uint32_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/arm/src/armv7-m/up_doirq.c b/nuttx/arch/arm/src/armv7-m/up_doirq.c index 375054fba..6063f9ca1 100644 --- a/nuttx/arch/arm/src/armv7-m/up_doirq.c +++ b/nuttx/arch/arm/src/armv7-m/up_doirq.c @@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs) uint32_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/avr/src/avr/up_doirq.c b/nuttx/arch/avr/src/avr/up_doirq.c index e38bf7fa8..7533d2159 100644 --- a/nuttx/arch/avr/src/avr/up_doirq.c +++ b/nuttx/arch/avr/src/avr/up_doirq.c @@ -79,9 +79,11 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs) uint8_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/avr/src/avr32/up_doirq.c b/nuttx/arch/avr/src/avr32/up_doirq.c index 7ade35fad..2d4a5e14a 100644 --- a/nuttx/arch/avr/src/avr32/up_doirq.c +++ b/nuttx/arch/avr/src/avr32/up_doirq.c @@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs) uint32_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/hc/src/common/up_doirq.c b/nuttx/arch/hc/src/common/up_doirq.c index d03b007df..4a56dedbd 100644 --- a/nuttx/arch/hc/src/common/up_doirq.c +++ b/nuttx/arch/hc/src/common/up_doirq.c @@ -79,9 +79,11 @@ uint8_t *up_doirq(int irq, uint8_t *regs) uint8_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/mips/src/mips32/up_doirq.c b/nuttx/arch/mips/src/mips32/up_doirq.c index 29cdf9c60..b963881e3 100644 --- a/nuttx/arch/mips/src/mips32/up_doirq.c +++ b/nuttx/arch/mips/src/mips32/up_doirq.c @@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs) uint32_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/sh/src/common/up_doirq.c b/nuttx/arch/sh/src/common/up_doirq.c index 717196682..185fa9684 100644 --- a/nuttx/arch/sh/src/common/up_doirq.c +++ b/nuttx/arch/sh/src/common/up_doirq.c @@ -79,6 +79,15 @@ uint32_t *up_doirq(int irq, uint32_t* regs) { uint32_t *savestate; + /* Nested interrupts are not supported in this implementation. If + * you want to implement nested interrupts, you would have to (1) + * change the way that current_regs is handled and (2) the design + * associated with CONFIG_ARCH_INTERRUPTSTACK. The savestate + * variable will not work for that purpose as implemented here + * because only the outermost nested interrupt can result in a + * context switch (it can probably be deleted). + */ + /* Current regs non-zero indicates that we are processing * an interrupt; current_regs is also used to manage * interrupt level context switches. diff --git a/nuttx/arch/z16/src/common/up_doirq.c b/nuttx/arch/z16/src/common/up_doirq.c index 670e6985d..9964f4432 100644 --- a/nuttx/arch/z16/src/common/up_doirq.c +++ b/nuttx/arch/z16/src/common/up_doirq.c @@ -90,6 +90,15 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs) { FAR chipreg_t *savestate; + /* Nested interrupts are not supported in this implementation. If + * you want to implement nested interrupts, you would have to (1) change + * the way that current_regs is handled and (2) the design associated + * with CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not + * work for that purpose as implemented here because only the outermost + * nested interrupt can result in a context switch (it can probably be + * deleted). + */ + /* Current regs non-zero indicates that we are processing * an interrupt; current_regs is also used to manage * interrupt level context switches. diff --git a/nuttx/arch/z80/include/z80/chip.h b/nuttx/arch/z80/include/z80/chip.h index 5c0c61166..c355eb788 100644 --- a/nuttx/arch/z80/include/z80/chip.h +++ b/nuttx/arch/z80/include/z80/chip.h @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_Z80_SRC_Z80_CHIP_H -#define __ARCH_Z80_SRC_Z80_CHIP_H +#ifndef __ARCH_Z80_INCLUDE_Z80_CHIP_H +#define __ARCH_Z80_INCLUDE_Z80_CHIP_H /************************************************************************************ * Included Files @@ -76,4 +76,4 @@ extern "C" { #endif #endif -#endif /* __ARCH_Z80_SRC_Z80_CHIP_H */ +#endif /* __ARCH_Z80_INCLUDE_Z80_CHIP_H */ diff --git a/nuttx/arch/z80/src/common/up_internal.h b/nuttx/arch/z80/src/common/up_internal.h index def13b546..5f1750b64 100644 --- a/nuttx/arch/z80/src/common/up_internal.h +++ b/nuttx/arch/z80/src/common/up_internal.h @@ -94,28 +94,26 @@ #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* Supplied by chip- or board-specific logic */ -EXTERN void up_irqinitialize(void); -EXTERN int up_timerisr(int irq, FAR chipreg_t *regs); +void up_irqinitialize(void); +int up_timerisr(int irq, FAR chipreg_t *regs); #ifdef USE_LOWSERIALINIT -EXTERN void up_lowserialinit(void); +void up_lowserialinit(void); #endif /* Defined in up_doirq.c */ -EXTERN FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs); +FAR chipreg_t *up_doirq(uint8_t irq, FAR chipreg_t *regs); /* Define in up_sigdeliver */ -EXTERN void up_sigdeliver(void); +void up_sigdeliver(void); /* Defined in CPU-specific logic (only for Z180) */ @@ -132,7 +130,7 @@ void up_addregion(void); /* Defined in up_serial.c */ #ifdef USE_SERIALDRIVER -EXTERN void up_serialinit(void); +void up_serialinit(void); #else # define up_serialinit() #endif @@ -140,7 +138,7 @@ EXTERN void up_serialinit(void); /* Defined in drivers/lowconsole.c */ #ifdef CONFIG_DEV_LOWCONSOLE -EXTERN void lowconsole_init(void); +void lowconsole_init(void); #else # define lowconsole_init() #endif @@ -159,14 +157,14 @@ extern void up_puts(const char *str); /* Defined in up_timerisr.c */ -EXTERN void up_timerinit(void); +void up_timerinit(void); /* Defined in board/up_leds.c */ #ifdef CONFIG_ARCH_LEDS -EXTERN void up_ledinit(void); -EXTERN void up_ledon(int led); -EXTERN void up_ledoff(int led); +void up_ledinit(void); +void up_ledon(int led); +void up_ledoff(int led); #else # define up_ledinit() # define up_ledon(led) @@ -176,16 +174,16 @@ EXTERN void up_ledoff(int led); /* Architecture specific hook into the timer interrupt handler */ #ifdef CONFIG_ARCH_TIMERHOOK -EXTERN void up_timerhook(void); +void up_timerhook(void); #endif /* Defined in board/up_network.c */ #ifdef CONFIG_NET -EXTERN int up_netinitialize(void); -EXTERN void up_netuninitialize(void); +int up_netinitialize(void); +void up_netuninitialize(void); # ifdef CONFIG_ARCH_MCFILTER -EXTERN int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bool enable); +int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bool enable); # else # define up_multicastfilter(dev, mac, enable) # endif @@ -197,19 +195,18 @@ EXTERN int up_multicastfilter(FAR struct uip_driver_s *dev, FAR uint8_t *mac, bo /* Return the current value of the stack pointer (used in stack dump logic) */ -EXTERN uint16_t up_getsp(void); +uint16_t up_getsp(void); /* Dump stack and registers */ #ifdef CONFIG_ARCH_STACKDUMP -EXTERN void up_stackdump(void); +void up_stackdump(void); # define REGISTER_DUMP() _REGISTER_DUMP() #else # define up_stackdump() # define REGISTER_DUMP() #endif -#undef EXTERN #ifdef __cplusplus } #endif diff --git a/nuttx/arch/z80/src/ez80/switch.h b/nuttx/arch/z80/src/ez80/switch.h index 0bac6aed1..0970b25ce 100644 --- a/nuttx/arch/z80/src/ez80/switch.h +++ b/nuttx/arch/z80/src/ez80/switch.h @@ -67,7 +67,14 @@ #define IN_INTERRUPT() (current_regs != NULL) -/* The following macro is used when the system enters interrupt handling logic */ +/* The following macro is used when the system enters interrupt handling logic + * + * NOTE: Nested interrupts are not supported in this implementation. If you want + * to implement nested interrupts, you would have to change the way that + * current_regs is handled. The savestate variable would not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). + */ #define DECL_SAVESTATE() \ FAR chipreg_t *savestate @@ -132,33 +139,30 @@ extern volatile chipreg_t *current_regs; #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* Defined in ez80_copystate.c */ -EXTERN void ez80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); +void ez80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); /* Defined in ez80_saveusercontext.asm */ -EXTERN int ez80_saveusercontext(FAR chipreg_t *regs); +int ez80_saveusercontext(FAR chipreg_t *regs); /* Defined in ez80_restorecontext.asm */ -EXTERN void ez80_restorecontext(FAR chipreg_t *regs); +void ez80_restorecontext(FAR chipreg_t *regs); /* Defined in ez80_sigsetup.c */ -EXTERN void ez80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, chipreg_t *regs); +void ez80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, chipreg_t *regs); /* Defined in ez80_registerdump.c */ -EXTERN void ez80_registerdump(void); +void ez80_registerdump(void); -#undef EXTERN #ifdef __cplusplus } #endif diff --git a/nuttx/arch/z80/src/z180/switch.h b/nuttx/arch/z80/src/z180/switch.h index ae80f4f76..7bf851a7c 100644 --- a/nuttx/arch/z80/src/z180/switch.h +++ b/nuttx/arch/z80/src/z180/switch.h @@ -77,9 +77,11 @@ * - savestate holds the previous value of current_state. * - savecpr holds the previous value of current_cpr. * - * TODO: I think this logic is bad... I do not thing that this will really - * handle nested interrupts correctly. What if we are nested and then a - * context switch occurs? current_regs will not be updated correctly! + * NOTE: Nested interrupts are not supported in this implementation. If you want + * to implement nested interrupts, you would have to change the way that + * current_regs/cbr is handled. The savestate/savecbr variables would not work + * for that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (they can probabaly be deleted). */ #define DECL_SAVESTATE() \ @@ -203,33 +205,30 @@ extern uint8_t current_cbr; #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* Defined in z180_copystate.c */ -EXTERN void z180_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); +void z180_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); /* Defined in z180_saveusercontext.asm */ -EXTERN int z180_saveusercontext(FAR chipreg_t *regs); +int z180_saveusercontext(FAR chipreg_t *regs); /* Defined in z180_restoreusercontext.asm */ -EXTERN void z180_restoreusercontext(FAR chipreg_t *regs); +void z180_restoreusercontext(FAR chipreg_t *regs); /* Defined in z180_sigsetup.c */ -EXTERN void z180_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); +void z180_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); /* Defined in z180_registerdump.c */ -EXTERN void z180_registerdump(void); +void z180_registerdump(void); -#undef EXTERN #ifdef __cplusplus } #endif diff --git a/nuttx/arch/z80/src/z8/switch.h b/nuttx/arch/z80/src/z8/switch.h index 45089947c..17f15b6da 100644 --- a/nuttx/arch/z80/src/z8/switch.h +++ b/nuttx/arch/z80/src/z8/switch.h @@ -112,7 +112,14 @@ #define IN_INTERRUPT() \ (g_z8irqstate.state != Z8_IRQSTATE_NONE) -/* The following macro is used when the system enters interrupt handling logic */ +/* The following macro is used when the system enters interrupt handling logic + * + * NOTE: Nested interrupts are not supported in this implementation. If you want + * to implement nested interrupts, you would have to change the way that + * current_regs is handled. The savestate variable would not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). + */ #define DECL_SAVESTATE() \ struct z8_irqstate_s savestate @@ -216,37 +223,34 @@ extern struct z8_irqstate_s g_z8irqstate; #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* Defined in z8_irq.c */ -EXTERN void up_maskack_irq(int irq); +void up_maskack_irq(int irq); /* Defined in z8_saveusercontext.asm */ -EXTERN int z8_saveusercontext(FAR chipreg_t *regs); +int z8_saveusercontext(FAR chipreg_t *regs); /* Defined in z8_saveirqcontext.c */ -EXTERN void z8_saveirqcontext(FAR chipreg_t *regs); +void z8_saveirqcontext(FAR chipreg_t *regs); /* Defined in z8_restorecontext.asm */ -EXTERN void z8_restorecontext(FAR chipreg_t *regs); +void z8_restorecontext(FAR chipreg_t *regs); /* Defined in z8_sigsetup.c */ -EXTERN void z8_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); +void z8_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); /* Defined in z8_registerdump.c */ -EXTERN void z8_registerdump(void); +void z8_registerdump(void); -#undef EXTERN #ifdef __cplusplus } #endif diff --git a/nuttx/arch/z80/src/z80/switch.h b/nuttx/arch/z80/src/z80/switch.h index 3732a32a3..4a49c70ef 100644 --- a/nuttx/arch/z80/src/z80/switch.h +++ b/nuttx/arch/z80/src/z80/switch.h @@ -66,7 +66,14 @@ #define IN_INTERRUPT() (current_regs != NULL) -/* The following macro is used when the system enters interrupt handling logic */ +/* The following macro is used when the system enters interrupt handling logic + * + * NOTE: Nested interrupts are not supported in this implementation. If you want + * to implement nested interrupts, you would have to change the way that + * current_regs is handled. The savestate variable would not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). + */ #define DECL_SAVESTATE() \ FAR chipreg_t *savestate @@ -131,33 +138,30 @@ extern volatile chipreg_t *current_regs; #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /* Defined in z80_copystate.c */ -EXTERN void z80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); +void z80_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src); /* Defined in z80_saveusercontext.asm */ -EXTERN int z80_saveusercontext(FAR chipreg_t *regs); +int z80_saveusercontext(FAR chipreg_t *regs); /* Defined in z80_restoreusercontext.asm */ -EXTERN void z80_restoreusercontext(FAR chipreg_t *regs); +void z80_restoreusercontext(FAR chipreg_t *regs); /* Defined in z80_sigsetup.c */ -EXTERN void z80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); +void z80_sigsetup(FAR _TCB *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs); /* Defined in z80_registerdump.c */ -EXTERN void z80_registerdump(void); +void z80_registerdump(void); -#undef EXTERN #ifdef __cplusplus } #endif -- cgit v1.2.3 From edb3871913d4fa7d6ef0f01827a194d6362c3c71 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 23 Dec 2012 17:35:06 +0000 Subject: Remove some dependencies of distclean on clean. This should not be necessary in higher level makefiles and should speed up make distclean git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5453 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 5 +++++ apps/Makefile | 2 +- apps/examples/Makefile | 2 +- apps/interpreters/Makefile | 2 +- apps/netutils/Makefile | 2 +- apps/system/Makefile | 2 +- 6 files changed, 10 insertions(+), 5 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 0695747f8..614538ad5 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -435,3 +435,8 @@ logic to find the absolute path to the program using the PATH variable. 6.25 2013-xx-xx Gregory Nutt + + * Makefiles: Removed dependency of distclean on clean in most top-level + files. It makes sense for 'leaf' Makefiles to have this dependency, + but it does not make sense for upper-level Makefiles. + diff --git a/apps/Makefile b/apps/Makefile index 353894b7f..0973d64b5 100644 --- a/apps/Makefile +++ b/apps/Makefile @@ -177,7 +177,7 @@ endif $(call DELFILE, $(BIN)) $(call CLEAN) -distclean: # clean +distclean: ifeq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) for %%G in ($(SUBDIRS)) do ( \ $(MAKE) -C %%G distclean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" \ diff --git a/apps/examples/Makefile b/apps/examples/Makefile index bdbfd4de8..50e9596d7 100644 --- a/apps/examples/Makefile +++ b/apps/examples/Makefile @@ -120,7 +120,7 @@ depend: $(foreach SDIR, $(SUBDIRS), $(SDIR)_depend) clean: $(foreach SDIR, $(SUBDIRS), $(SDIR)_clean) -distclean: clean $(foreach SDIR, $(SUBDIRS), $(SDIR)_distclean) +distclean: $(foreach SDIR, $(SUBDIRS), $(SDIR)_distclean) -include Make.dep diff --git a/apps/interpreters/Makefile b/apps/interpreters/Makefile index 867d45f99..f78528714 100644 --- a/apps/interpreters/Makefile +++ b/apps/interpreters/Makefile @@ -73,4 +73,4 @@ depend: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_depend) clean: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_clean) -distclean: clean $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_distclean) +distclean: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_distclean) diff --git a/apps/netutils/Makefile b/apps/netutils/Makefile index 0879ada4e..781770fc1 100644 --- a/apps/netutils/Makefile +++ b/apps/netutils/Makefile @@ -64,4 +64,4 @@ depend: $(foreach SDIR, $(SUBDIRS), $(SDIR)_depend) clean: $(foreach SDIR, $(SUBDIRS), $(SDIR)_clean) -distclean: clean $(foreach SDIR, $(SUBDIRS), $(SDIR)_distclean) +distclean: $(foreach SDIR, $(SUBDIRS), $(SDIR)_distclean) diff --git a/apps/system/Makefile b/apps/system/Makefile index 9955a6b2c..057fbcf77 100644 --- a/apps/system/Makefile +++ b/apps/system/Makefile @@ -73,4 +73,4 @@ depend: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_depend) clean: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_clean) -distclean: clean $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_distclean) +distclean: $(foreach SDIR, $(INSTALLED_DIRS), $(SDIR)_distclean) -- cgit v1.2.3 From 5cfde412bb9cbd55db2854939d25c2d8e053aaa5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 23 Dec 2012 20:22:41 +0000 Subject: Rename namedapp as simply builtin git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5454 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 1 + apps/Kconfig | 4 +- apps/Make.defs | 4 +- apps/Makefile | 14 +- apps/README.txt | 30 +- apps/builtin/Kconfig | 15 + apps/builtin/Make.defs | 40 ++ apps/builtin/Makefile | 110 ++++ apps/builtin/binfs.c | 596 +++++++++++++++++++++ apps/builtin/builtin.c | 96 ++++ apps/builtin/builtin.h | 77 +++ apps/builtin/exec_builtin.c | 187 +++++++ apps/include/apps.h | 18 +- apps/namedapp/Kconfig | 15 - apps/namedapp/Make.defs | 40 -- apps/namedapp/Makefile | 110 ---- apps/namedapp/binfs.c | 596 --------------------- apps/namedapp/exec_namedapp.c | 187 ------- apps/namedapp/namedapp.c | 96 ---- apps/namedapp/namedapp.h | 78 --- apps/nshlib/Kconfig | 8 +- apps/nshlib/README.txt | 2 +- apps/nshlib/nsh_apps.c | 6 +- apps/nshlib/nsh_parse.c | 8 +- nuttx/Documentation/NuttShell.html | 79 ++- nuttx/configs/cloudctrl/nsh/defconfig | 2 +- nuttx/configs/ez80f910200kitg/ostest/defconfig | 2 +- nuttx/configs/ez80f910200zco/ostest/defconfig | 2 +- nuttx/configs/fire-stm32v2/nsh/defconfig | 2 +- nuttx/configs/p112/ostest/defconfig | 2 +- nuttx/configs/shenzhou/nsh/defconfig | 2 +- nuttx/configs/shenzhou/nxwm/defconfig | 2 +- nuttx/configs/shenzhou/thttpd/defconfig | 2 +- nuttx/configs/sim/README.txt | 6 +- nuttx/configs/sim/cxxtest/defconfig | 2 +- nuttx/configs/sim/nxwm/defconfig | 2 +- nuttx/configs/sim/ostest/defconfig | 2 +- nuttx/configs/stm3220g-eval/nxwm/defconfig | 2 +- nuttx/configs/stm3240g-eval/discover/defconfig | 2 +- nuttx/configs/stm3240g-eval/xmlrpc/defconfig | 2 +- nuttx/configs/stm32f100rc_generic/nsh/defconfig | 2 +- nuttx/configs/stm32f100rc_generic/ostest/defconfig | 2 +- nuttx/configs/stm32f4discovery/cxxtest/defconfig | 2 +- nuttx/configs/stm32f4discovery/elf/defconfig | 2 +- nuttx/configs/stm32f4discovery/nxlines/defconfig | 2 +- nuttx/configs/stm32f4discovery/ostest/defconfig | 2 +- nuttx/configs/stm32f4discovery/winbuild/defconfig | 2 +- nuttx/configs/vsn/src/README.txt | 5 +- nuttx/configs/xtrs/nsh/defconfig | 2 +- nuttx/configs/xtrs/ostest/defconfig | 2 +- nuttx/configs/xtrs/pashello/defconfig | 2 +- nuttx/configs/z16f2800100zcog/ostest/defconfig | 2 +- nuttx/configs/z16f2800100zcog/pashello/defconfig | 2 +- nuttx/configs/z80sim/nsh/defconfig | 2 +- nuttx/configs/z80sim/ostest/defconfig | 2 +- nuttx/configs/z80sim/pashello/defconfig | 2 +- nuttx/configs/z8encore000zco/ostest/defconfig | 2 +- nuttx/configs/z8f64200100kit/ostest/defconfig | 2 +- nuttx/sched/os_bringup.c | 4 +- 59 files changed, 1247 insertions(+), 1247 deletions(-) create mode 100644 apps/builtin/Kconfig create mode 100644 apps/builtin/Make.defs create mode 100644 apps/builtin/Makefile create mode 100644 apps/builtin/binfs.c create mode 100644 apps/builtin/builtin.c create mode 100644 apps/builtin/builtin.h create mode 100644 apps/builtin/exec_builtin.c delete mode 100644 apps/namedapp/Kconfig delete mode 100644 apps/namedapp/Make.defs delete mode 100644 apps/namedapp/Makefile delete mode 100644 apps/namedapp/binfs.c delete mode 100644 apps/namedapp/exec_namedapp.c delete mode 100644 apps/namedapp/namedapp.c delete mode 100644 apps/namedapp/namedapp.h diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 614538ad5..886526b18 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -439,4 +439,5 @@ * Makefiles: Removed dependency of distclean on clean in most top-level files. It makes sense for 'leaf' Makefiles to have this dependency, but it does not make sense for upper-level Makefiles. + * namedapp/: Renamed to builtins in preparation for another change. diff --git a/apps/Kconfig b/apps/Kconfig index ea9bd2d31..68c36f5a5 100644 --- a/apps/Kconfig +++ b/apps/Kconfig @@ -3,8 +3,8 @@ # see misc/tools/kconfig-language.txt. # -menu "Named Applications" -source "$APPSDIR/namedapp/Kconfig" +menu "Built-In Applications" +source "$APPSDIR/builtin/Kconfig" endmenu menu "Examples" diff --git a/apps/Make.defs b/apps/Make.defs index 53ac7f8be..12b351e7f 100644 --- a/apps/Make.defs +++ b/apps/Make.defs @@ -36,6 +36,6 @@ define REGISTER @echo "Register: $1" - @echo "{ \"$1\", $2, $3, $4 }," >> "$(APPDIR)/namedapp/namedapp_list.h" - @echo "EXTERN int $4(int argc, char *argv[]);" >> "$(APPDIR)/namedapp/namedapp_proto.h" + @echo "{ \"$1\", $2, $3, $4 }," >> "$(APPDIR)/builtin/builtin_list.h" + @echo "EXTERN int $4(int argc, char *argv[]);" >> "$(APPDIR)/builtin/builtin_proto.h" endef diff --git a/apps/Makefile b/apps/Makefile index 0973d64b5..299560195 100644 --- a/apps/Makefile +++ b/apps/Makefile @@ -44,11 +44,11 @@ APPDIR = ${shell pwd} # action. It is created by the configured appconfig file (a copy of which # appears in this directory as .config) # SUBDIRS is the list of all directories containing Makefiles. It is used -# only for cleaning. namedapp must always be the first in the list. This +# only for cleaning. builtin must always be the first in the list. This # list can be extended by the .config file as well. CONFIGURED_APPS = -SUBDIRS = examples graphics interpreters modbus namedapp nshlib netutils system +SUBDIRS = examples graphics interpreters modbus builtin nshlib netutils system # There are two different mechanisms for obtaining the list of configured # directories: @@ -69,9 +69,9 @@ SUBDIRS = examples graphics interpreters modbus namedapp nshlib netutils system ifeq ($(CONFIG_NUTTX_NEWCONFIG),y) -# namedapp/Make.defs must be included first +# builtin/Make.defs must be included first -include namedapp/Make.defs +include builtin/Make.defs include examples/Make.defs include graphics/Make.defs include interpreters/Make.defs @@ -82,7 +82,7 @@ include system/Make.defs # INSTALLED_APPS is the list of currently available application directories. It # is the same as CONFIGURED_APPS, but filtered to exclude any non-existent -# application directory. namedapp is always in the list of applications to be +# application directory. builtin is always in the list of applications to be # built. INSTALLED_APPS = @@ -94,10 +94,10 @@ else # INSTALLED_APPS is the list of currently available application directories. It # is the same as CONFIGURED_APPS, but filtered to exclude any non-existent -# application directory. namedapp is always in the list of applications to be +# application directory. builtin is always in the list of applications to be # built. -INSTALLED_APPS = namedapp +INSTALLED_APPS = builtin endif # Create the list of available applications (INSTALLED_APPS) diff --git a/apps/README.txt b/apps/README.txt index 7a379254e..4f043dcfa 100644 --- a/apps/README.txt +++ b/apps/README.txt @@ -6,12 +6,12 @@ Contents General Directory Location - Named Applications - Named Startup main() function + Built-In Applications + Built-In Startup main() function NuttShell (NSH) Built-In Commands Synchronous Built-In Commands Application Configuration File - Example Named Application + Example Built-In Application Building NuttX with Board-Specific Pieces Outside the Source Tree General @@ -47,14 +47,14 @@ ways to do that: path to the application directory on the configuration command line like: ./configure.sh -a / -Named Applications ------------------- +Built-In Applications +--------------------- NuttX also supports applications that can be started using a name string. In this case, application entry points with their requirements are gathered together in two files: - - namedapp/namedapp_proto.h Entry points, prototype function - - namedapp/namedapp_list.h Application specific information and requirements + - builtin/builtin_proto.h Entry points, prototype function + - builtin/builtin_list.h Application specific information and requirements The build occurs in several phases as different build targets are executed: (1) context, (2) depend, and (3) default (all). Application information is @@ -62,18 +62,18 @@ collected during the make context build phase. To execute an application function: - exec_namedapp() is defined in the nuttx/include/apps/apps.h + exec_builtin() is defined in the nuttx/include/apps/apps.h NuttShell (NSH) Built-In Commands --------------------------------- -One use of named applications is to provide a way of invoking your custom +One use of builtin applications is to provide a way of invoking your custom application through the NuttShell (NSH) command line. NSH will support a seamless method invoking the applications, when the following option is enabled in the NuttX configuration file: CONFIG_NSH_BUILTIN_APPS=y -Applications registered in the apps/namedapp/namedapp_list.h file will then +Applications registered in the apps/builtin/builtin_list.h file will then be accessible from the NSH command line. If you type 'help' at the NSH prompt, you will see a list of the registered commands. @@ -109,9 +109,9 @@ CONFIGURED_APPS list like: CONFIGURED_APPS += examples/hello system/poweroff -Named Start-Up main() function +Built-In Start-Up main() function ------------------------------ -A named application can even be used as the main, start-up entry point +A builtin application can even be used as the main, start-up entry point into your embedded software. When the user defines this option in the NuttX configuration file: @@ -124,10 +124,10 @@ will call: int hello_main(int argc, char *argv[]) -Example Named Application -------------------------- +Example Built-In Application +---------------------------- An example application skeleton can be found under the examples/hello -sub-directory. This example shows how a named application can be added +sub-directory. This example shows how a builtin application can be added to the project. One must define: 1. create sub-directory as: appname diff --git a/apps/builtin/Kconfig b/apps/builtin/Kconfig new file mode 100644 index 000000000..8310e6df9 --- /dev/null +++ b/apps/builtin/Kconfig @@ -0,0 +1,15 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +config BUILTIN + bool "Support Builtin Applications" + default n + ---help--- + Enable support for builtin applications. This features assigns a string + name to an application. This feature is also the underlying requirement + to support built-in applications in the NuttShell (NSH). + +if BUILTIN +endif diff --git a/apps/builtin/Make.defs b/apps/builtin/Make.defs new file mode 100644 index 000000000..ab6292cc3 --- /dev/null +++ b/apps/builtin/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# apps/builtin/Make.defs +# Adds selected applications to apps/ build +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_BUILTIN),y) +CONFIGURED_APPS += builtin +endif + diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile new file mode 100644 index 000000000..72ba0347f --- /dev/null +++ b/apps/builtin/Makefile @@ -0,0 +1,110 @@ +############################################################################ +# apps/builtin/Makefile +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/.config +-include $(TOPDIR)/Make.defs +include $(APPDIR)/Make.defs + +# NSH Library + +# Source and object files + +ASRCS = +CSRCS = builtin.c exec_builtin.c + +ifeq ($(CONFIG_APPS_BINDIR),y) +CSRCS += binfs.c +endif + +AOBJS = $(ASRCS:.S=$(OBJEXT)) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BIN = ..\libapps$(LIBEXT) +else +ifeq ($(WINTOOL),y) + BIN = ..\\libapps$(LIBEXT) +else + BIN = ../libapps$(LIBEXT) +endif +endif + +ROOTDEPPATH = --dep-path . +VPATH = + +# Build Targets + +all: .built +.PHONY: .context context depend clean distclean + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +.built: $(OBJS) + $(call ARCHIVE, $(BIN), $(OBJS)) + $(Q) touch .built + +.context: + @echo "/* List of application requirements, generated during make context. */" > builtin_list.h + @echo "/* List of application entry points, generated during make context. */" > builtin_proto.h + $(Q) touch $@ + +context: .context + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, .built) + $(call CLEAN) + +distclean: clean + $(call DELFILE, .context) + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + $(call DELFILE, builtin_list.h) + $(call DELFILE, builtin_proto.h) + +-include Make.dep + diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c new file mode 100644 index 000000000..501f0a4b9 --- /dev/null +++ b/apps/builtin/binfs.c @@ -0,0 +1,596 @@ +/**************************************************************************** + * apps/builtin/binfs.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "builtin.h" + +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_APPS_BINDIR) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the overall mountpoint state. An instance of this + * structure is retained as inode private data on each mountpoint that is + * mounted with a fat32 filesystem. + */ + +struct binfs_state_s +{ + sem_t bm_sem; /* Used to assume thread-safe access */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void binfs_semtake(struct binfs_state_s *bm); +static inline void binfs_semgive(struct binfs_state_s *bm); +static int binfs_open(FAR struct file *filep, const char *relpath, + int oflags, mode_t mode); +static int binfs_close(FAR struct file *filep); +static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); +static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + +static int binfs_opendir(struct inode *mountpt, const char *relpath, + struct fs_dirent_s *dir); +static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); +static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir); + +static int binfs_bind(FAR struct inode *blkdriver, const void *data, + void **handle); +static int binfs_unbind(void *handle, FAR struct inode **blkdriver); +static int binfs_statfs(struct inode *mountpt, struct statfs *buf); + +static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/* See fs_mount.c -- this structure is explicitly externed there. + * We use the old-fashioned kind of initializers so that this will compile + * with any compiler. + */ + +const struct mountpt_operations binfs_operations = +{ + binfs_open, /* open */ + binfs_close, /* close */ + binfs_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + binfs_ioctl, /* ioctl */ + NULL, /* sync */ + + binfs_opendir, /* opendir */ + NULL, /* closedir */ + binfs_readdir, /* readdir */ + binfs_rewinddir, /* rewinddir */ + + binfs_bind, /* bind */ + binfs_unbind, /* unbind */ + binfs_statfs, /* statfs */ + + NULL, /* unlink */ + NULL, /* mkdir */ + NULL, /* rmdir */ + NULL, /* rename */ + binfs_stat /* stat */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: binfs_semtake + ****************************************************************************/ + +static void binfs_semtake(struct binfs_state_s *bm) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&bm->bm_sem) != 0) + { + /* The only case that an error should occur here is if + * the wait was awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: binfs_semgive + ****************************************************************************/ + +static inline void binfs_semgive(struct binfs_state_s *bm) +{ + sem_post(&bm->bm_sem); +} + +/**************************************************************************** + * Name: binfs_open + ****************************************************************************/ + +static int binfs_open(FAR struct file *filep, const char *relpath, + int oflags, mode_t mode) +{ + struct binfs_state_s *bm; + int ret = -ENOSYS; + + fvdbg("Open '%s'\n", relpath); + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv == NULL && filep->f_inode != NULL); + + /* mountpoint private data from the inode reference from the file + * structure + */ + + bm = (struct binfs_state_s*)filep->f_inode->i_private; + DEBUGASSERT(bm != NULL); + + /* BINFS is read-only. Any attempt to open with any kind of write + * access is not permitted. + */ + + if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0) + { + fdbg("Only O_RDONLY supported\n"); + ret = -EACCES; + } + + /* Save open-specific state in filep->f_priv */ + + /* Opening of elements within the pseudo-file system is not yet supported */ + + return ret; +} + +/**************************************************************************** + * Name: binfs_close + ****************************************************************************/ + +static int binfs_close(FAR struct file *filep) +{ + struct binfs_state_s *bm; + int ret = -ENOSYS; + + fvdbg("Closing\n"); + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover the open file state from the struct file instance */ + /* bf = filep->f_priv; */ + + /* Recover the file system state from the inode */ + + bm = filep->f_inode->i_private; + DEBUGASSERT(bm != NULL); + + /* Free the open file state */ + /* free(bf); */ + + filep->f_priv = NULL; + + /* Since open() is not yet supported, neither is close(). */ + + return ret; +} + +/**************************************************************************** + * Name: binfs_read + ****************************************************************************/ + +static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) +{ + struct binfs_state_s *bm; + + fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover the open file state data from the struct file instance */ + /* bf = filep->f_priv; */ + + /* Recover the file system state from the inode */ + + bm = filep->f_inode->i_private; + DEBUGASSERT(bm != NULL); + + /* Since open is not yet supported, neither is reading */ + + return -ENOSYS; +} + +/**************************************************************************** + * Name: binfs_ioctl + ****************************************************************************/ + +static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + struct binfs_state_s *bm; + + fvdbg("cmd: %d arg: %08lx\n", cmd, arg); + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover the open file state from the struct file instance */ + /* bf = filep->f_priv; */ + + /* Recover the file system state from the inode */ + + bm = filep->f_inode->i_private; + DEBUGASSERT(bm != NULL); + + /* No ioctl commands yet supported */ + + return -ENOTTY; +} + +/**************************************************************************** + * Name: binfs_opendir + * + * Description: + * Open a directory for read access + * + ****************************************************************************/ + +static int binfs_opendir(struct inode *mountpt, const char *relpath, + struct fs_dirent_s *dir) +{ + struct binfs_state_s *bm; + int ret; + + fvdbg("relpath: \"%s\"\n", relpath ? relpath : "NULL"); + + /* Sanity checks */ + + DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); + + /* Recover the file system state from the inode instance */ + + bm = mountpt->i_private; + binfs_semtake(bm); + + /* The requested directory must be the volume-relative "root" directory */ + + if (relpath && relpath[0] != '\0') + { + ret = -ENOENT; + goto errout_with_semaphore; + } + + /* Set the index to the first entry */ + + dir->u.binfs.fb_index = 0; + ret = OK; + +errout_with_semaphore: + binfs_semgive(bm); + return ret; +} + +/**************************************************************************** + * Name: binfs_readdir + * + * Description: Read the next directory entry + * + ****************************************************************************/ + +static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) +{ + struct binfs_state_s *bm; + unsigned int index; + int ret; + + /* Sanity checks */ + + DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); + + /* Recover the file system state from the inode instance */ + + bm = mountpt->i_private; + binfs_semtake(bm); + + /* Have we reached the end of the directory */ + + index = dir->u.binfs.fb_index; + if (builtins[index].name == NULL) + { + /* We signal the end of the directory by returning the + * special error -ENOENT + */ + + fvdbg("Entry %d: End of directory\n", index); + ret = -ENOENT; + } + else + { + /* Save the filename and file type */ + + fvdbg("Entry %d: \"%s\"\n", index, builtins[index].name); + dir->fd_dir.d_type = DTYPE_FILE; + strncpy(dir->fd_dir.d_name, builtins[index].name, NAME_MAX+1); + + /* The application list is terminated by an entry with a NULL name. + * Therefore, there is at least one more entry in the list. + */ + + index++; + + /* Set up the next directory entry offset. NOTE that we could use the + * standard f_pos instead of our own private fb_index. + */ + + dir->u.binfs.fb_index = index; + ret = OK; + } + + binfs_semgive(bm); + return ret; +} + +/**************************************************************************** + * Name: binfs_rewindir + * + * Description: Reset directory read to the first entry + * + ****************************************************************************/ + +static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) +{ + struct binfs_state_s *bm; + + fvdbg("Entry\n"); + + /* Sanity checks */ + + DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); + + /* Recover the file system state from the inode instance */ + + bm = mountpt->i_private; + binfs_semtake(bm); + + dir->u.binfs.fb_index = 0; + + binfs_semgive(bm); + return OK; +} + +/**************************************************************************** + * Name: binfs_bind + * + * Description: This implements a portion of the mount operation. This + * function allocates and initializes the mountpoint private data and + * binds the blockdriver inode to the filesystem private data. The final + * binding of the private data (containing the blockdriver) to the + * mountpoint is performed by mount(). + * + ****************************************************************************/ + +static int binfs_bind(FAR struct inode *blkdriver, const void *data, + void **handle) +{ + struct binfs_state_s *bm; + + fvdbg("Entry\n"); + + /* Create an instance of the mountpt state structure */ + + bm = (struct binfs_state_s *)zalloc(sizeof(struct binfs_state_s)); + if (!bm) + { + fdbg("Failed to allocate mountpoint structure\n"); + return -ENOMEM; + } + + /* Initialize the allocated mountpt state structure. The filesystem is + * responsible for one reference ont the blkdriver inode and does not + * have to addref() here (but does have to release in ubind(). + */ + + sem_init(&bm->bm_sem, 0, 1); /* Initialize the semaphore that controls access */ + + /* Mounted! */ + + *handle = (void*)bm; + return OK; +} + +/**************************************************************************** + * Name: binfs_unbind + * + * Description: This implements the filesystem portion of the umount + * operation. + * + ****************************************************************************/ + +static int binfs_unbind(void *handle, FAR struct inode **blkdriver) +{ + struct binfs_state_s *bm = (struct binfs_state_s*)handle; + + fvdbg("Entry\n"); + +#ifdef CONFIG_DEBUG + if (!bm) + { + return -EINVAL; + } +#endif + + /* Check if there are sill any files opened on the filesystem. */ + + /* Release the mountpoint private data */ + + sem_destroy(&bm->bm_sem); + return OK; +} + +/**************************************************************************** + * Name: binfs_statfs + * + * Description: Return filesystem statistics + * + ****************************************************************************/ + +static int binfs_statfs(struct inode *mountpt, struct statfs *buf) +{ + struct binfs_state_s *bm; + + fvdbg("Entry\n"); + + /* Sanity checks */ + + DEBUGASSERT(mountpt && mountpt->i_private); + + /* Get the mountpoint private data from the inode structure */ + + bm = mountpt->i_private; + binfs_semtake(bm); + + /* Fill in the statfs info */ + + memset(buf, 0, sizeof(struct statfs)); + buf->f_type = BINFS_MAGIC; + buf->f_bsize = 0; + buf->f_blocks = 0; + buf->f_bfree = 0; + buf->f_bavail = 0; + buf->f_namelen = NAME_MAX; + + binfs_semgive(bm); + return OK; +} + +/**************************************************************************** + * Name: binfs_stat + * + * Description: Return information about a file or directory + * + ****************************************************************************/ + +static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) +{ + struct binfs_state_s *bm; + int ret; + + fvdbg("Entry\n"); + + /* Sanity checks */ + + DEBUGASSERT(mountpt && mountpt->i_private); + + /* Get the mountpoint private data from the inode structure */ + + bm = mountpt->i_private; + binfs_semtake(bm); + + /* The requested directory must be the volume-relative "root" directory */ + + if (relpath && relpath[0] != '\0') + { + /* Check if there is a file with this name. */ + + if (builtin_isavail(relpath) < 0) + { + ret = -ENOENT; + goto errout_with_semaphore; + } + + /* It's a execute-only file name */ + + buf->st_mode = S_IFREG|S_IXOTH|S_IXGRP|S_IXUSR; + } + else + { + /* It's a read/execute-only directory name */ + + buf->st_mode = S_IFDIR|S_IROTH|S_IRGRP|S_IRUSR|S_IXOTH|S_IXGRP|S_IXUSR; + } + + /* File/directory size, access block size */ + + buf->st_size = 0; + buf->st_blksize = 0; + buf->st_blocks = 0; + ret = OK; + +errout_with_semaphore: + binfs_semgive(bm); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_APPS_BINDIR */ + diff --git a/apps/builtin/builtin.c b/apps/builtin/builtin.c new file mode 100644 index 000000000..a6ed7dd3f --- /dev/null +++ b/apps/builtin/builtin.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * apps/builtin/builtin.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#include "builtin_proto.h" + +const struct builtin_s builtins[] = +{ +# include "builtin_list.h" + { NULL, 0, 0, 0 } +}; + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int number_builtins(void) +{ + return sizeof(builtins)/sizeof(struct builtin_s) - 1; +} + + diff --git a/apps/builtin/builtin.h b/apps/builtin/builtin.h new file mode 100644 index 000000000..3f7ddd7ce --- /dev/null +++ b/apps/builtin/builtin.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * apps/builtin/builtin.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __APPS_BUILTIN_BUILTIN_H +#define __APPS_BUILTIN_BUILTIN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +EXTERN const struct builtin_s builtins[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +EXTERN int number_builtins(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __APPS_BUILTIN_BUILTIN_H */ + diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c new file mode 100644 index 000000000..dc3630230 --- /dev/null +++ b/apps/builtin/exec_builtin.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * apps/builtin/exec_builtin.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With updates, modifications, and general maintenance by: + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Auther: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "builtin.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_getname + * + * Description: + * Return the name of the application at index in the table of builtin + * applications. + * + ****************************************************************************/ + +const char *builtin_getname(int index) +{ + if (index < 0 || index >= number_builtins()) + { + return NULL; + } + + return builtins[index].name; +} + +/**************************************************************************** + * Name: builtin_isavail + * + * Description: + * Return the index into the table of applications for the applicaiton with + * the name 'appname'. + * + ****************************************************************************/ + +int builtin_isavail(FAR const char *appname) +{ + int i; + + for (i = 0; builtins[i].name; i++) + { + if (!strcmp(builtins[i].name, appname)) + { + return i; + } + } + + set_errno(ENOENT); + return ERROR; +} + +/**************************************************************************** + * Name: builtin_isavail + * + * Description: + * Execute the application with name 'appname', providing the arguments + * in the argv[] array. + * + * Returned Value: + * On success, the task ID of the builtin application is returned. On + * failure, -1 (ERROR) is returned an the errno value is set appropriately. + * + ****************************************************************************/ + +int exec_builtin(FAR const char *appname, FAR const char **argv) +{ + pid_t pid; + int index; + + /* Verify that an application with this name exists */ + + index = builtin_isavail(appname); + if (index >= 0) + { + /* Disable pre-emption. This means that although we start the builtin + * application here, it will not actually run until pre-emption is + * re-enabled below. + */ + + sched_lock(); + + /* Start the builtin application task */ + + pid = TASK_CREATE(builtins[index].name, builtins[index].priority, + builtins[index].stacksize, builtins[index].main, + (argv) ? &argv[1] : (const char **)NULL); + + /* If robin robin scheduling is enabled, then set the scheduling policy + * of the new task to SCHED_RR before it has a chance to run. + */ + +#if CONFIG_RR_INTERVAL > 0 + if (pid > 0) + { + struct sched_param param; + + /* Pre-emption is disabled so the task creation and the + * following operation will be atomic. The priority of the + * new task cannot yet have changed from its initial value. + */ + + param.sched_priority = builtins[index].priority; + sched_setscheduler(pid, SCHED_RR, ¶m); + } +#endif + /* Now let the builtin application run */ + + sched_unlock(); + + /* Return the task ID of the new task if the task was sucessfully + * started. Otherwise, pid will be ERROR (and the errno value will + * be set appropriately). + */ + + return pid; + } + + /* Return ERROR with errno set appropriately */ + + return ERROR; +} diff --git a/apps/include/apps.h b/apps/include/apps.h index 520128203..37599ac5c 100644 --- a/apps/include/apps.h +++ b/apps/include/apps.h @@ -52,7 +52,7 @@ * Public Types ****************************************************************************/ -struct namedapp_s +struct builtin_s { const char *name; /* Invocation name and as seen under /sbin/ */ int priority; /* Use: SCHED_PRIORITY_DEFAULT */ @@ -64,7 +64,7 @@ struct namedapp_s * Public Data ****************************************************************************/ -/* The "bindir" is file system that supports access to the named applications. +/* The "bindir" is file system that supports access to the builtin applications. * It is typically mounted under /bin. */ @@ -86,7 +86,7 @@ extern "C" { #endif /**************************************************************************** - * Name: namedapp_isavail + * Name: builtin_isavail * * Description: * Checks for availabiliy of application registerred during compile time. @@ -101,10 +101,10 @@ extern "C" { * ****************************************************************************/ -EXTERN int namedapp_isavail(FAR const char *appname); +EXTERN int builtin_isavail(FAR const char *appname); /**************************************************************************** - * Name: namedapp_getname + * Name: builtin_getname * * Description: * Returns pointer to a name of built-in application pointed by the @@ -119,13 +119,13 @@ EXTERN int namedapp_isavail(FAR const char *appname); * ****************************************************************************/ -EXTERN const char *namedapp_getname(int index); +EXTERN const char *builtin_getname(int index); /**************************************************************************** - * Name: exec_namedapp + * Name: exec_builtin * * Description: - * Executes builtin named application registered during compile time. + * Executes builtin applications registered during 'make context' time. * New application is run in a separate task context (and thread). * * Input Parameter: @@ -139,7 +139,7 @@ EXTERN const char *namedapp_getname(int index); * ****************************************************************************/ -EXTERN int exec_namedapp(FAR const char *appname, FAR const char **argv); +EXTERN int exec_builtin(FAR const char *appname, FAR const char **argv); #undef EXTERN #if defined(__cplusplus) diff --git a/apps/namedapp/Kconfig b/apps/namedapp/Kconfig deleted file mode 100644 index 8d8f03421..000000000 --- a/apps/namedapp/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see misc/tools/kconfig-language.txt. -# - -config NAMEDAPP - bool "Support named applications" - default n - ---help--- - Enable support for named applications. This features assigns a string - name to an application. This feature is also the underlying requirement - to support built-in applications in the NuttShell (NSH). - -if NAMEDAPP -endif diff --git a/apps/namedapp/Make.defs b/apps/namedapp/Make.defs deleted file mode 100644 index 399fefee8..000000000 --- a/apps/namedapp/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# apps/namedapps/Make.defs -# Adds selected applications to apps/ build -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -ifeq ($(CONFIG_NAMEDAPP),y) -CONFIGURED_APPS += namedapp -endif - diff --git a/apps/namedapp/Makefile b/apps/namedapp/Makefile deleted file mode 100644 index a88c73567..000000000 --- a/apps/namedapp/Makefile +++ /dev/null @@ -1,110 +0,0 @@ -############################################################################ -# apps/nshlib/Makefile -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/.config --include $(TOPDIR)/Make.defs -include $(APPDIR)/Make.defs - -# NSH Library - -# Source and object files - -ASRCS = -CSRCS = namedapp.c exec_namedapp.c - -ifeq ($(CONFIG_APPS_BINDIR),y) -CSRCS += binfs.c -endif - -AOBJS = $(ASRCS:.S=$(OBJEXT)) -COBJS = $(CSRCS:.c=$(OBJEXT)) - -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) - -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - BIN = ..\libapps$(LIBEXT) -else -ifeq ($(WINTOOL),y) - BIN = ..\\libapps$(LIBEXT) -else - BIN = ../libapps$(LIBEXT) -endif -endif - -ROOTDEPPATH = --dep-path . -VPATH = - -# Build Targets - -all: .built -.PHONY: .context context depend clean distclean - -$(AOBJS): %$(OBJEXT): %.S - $(call ASSEMBLE, $<, $@) - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -.built: $(OBJS) - $(call ARCHIVE, $(BIN), $(OBJS)) - $(Q) touch .built - -.context: - @echo "/* List of application requirements, generated during make context. */" > namedapp_list.h - @echo "/* List of application entry points, generated during make context. */" > namedapp_proto.h - $(Q) touch $@ - -context: .context - -.depend: Makefile $(SRCS) - $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep - $(Q) touch $@ - -depend: .depend - -clean: - $(call DELFILE, .built) - $(call CLEAN) - -distclean: clean - $(call DELFILE, .context) - $(call DELFILE, Make.dep) - $(call DELFILE, .depend) - $(call DELFILE, namedapp_list.h) - $(call DELFILE, namedapp_proto.h) - --include Make.dep - diff --git a/apps/namedapp/binfs.c b/apps/namedapp/binfs.c deleted file mode 100644 index 36e3ace92..000000000 --- a/apps/namedapp/binfs.c +++ /dev/null @@ -1,596 +0,0 @@ -/**************************************************************************** - * apps/namedapps/binfs.c - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "namedapp.h" - -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_APPS_BINDIR) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure represents the overall mountpoint state. An instance of this - * structure is retained as inode private data on each mountpoint that is - * mounted with a fat32 filesystem. - */ - -struct binfs_state_s -{ - sem_t bm_sem; /* Used to assume thread-safe access */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void binfs_semtake(struct binfs_state_s *bm); -static inline void binfs_semgive(struct binfs_state_s *bm); -static int binfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode); -static int binfs_close(FAR struct file *filep); -static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); -static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); - -static int binfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir); -static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); -static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir); - -static int binfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle); -static int binfs_unbind(void *handle, FAR struct inode **blkdriver); -static int binfs_statfs(struct inode *mountpt, struct statfs *buf); - -static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf); - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -/**************************************************************************** - * Public Variables - ****************************************************************************/ - -/* See fs_mount.c -- this structure is explicitly externed there. - * We use the old-fashioned kind of initializers so that this will compile - * with any compiler. - */ - -const struct mountpt_operations binfs_operations = -{ - binfs_open, /* open */ - binfs_close, /* close */ - binfs_read, /* read */ - NULL, /* write */ - NULL, /* seek */ - binfs_ioctl, /* ioctl */ - NULL, /* sync */ - - binfs_opendir, /* opendir */ - NULL, /* closedir */ - binfs_readdir, /* readdir */ - binfs_rewinddir, /* rewinddir */ - - binfs_bind, /* bind */ - binfs_unbind, /* unbind */ - binfs_statfs, /* statfs */ - - NULL, /* unlink */ - NULL, /* mkdir */ - NULL, /* rmdir */ - NULL, /* rename */ - binfs_stat /* stat */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: binfs_semtake - ****************************************************************************/ - -static void binfs_semtake(struct binfs_state_s *bm) -{ - /* Take the semaphore (perhaps waiting) */ - - while (sem_wait(&bm->bm_sem) != 0) - { - /* The only case that an error should occur here is if - * the wait was awakened by a signal. - */ - - ASSERT(errno == EINTR); - } -} - -/**************************************************************************** - * Name: binfs_semgive - ****************************************************************************/ - -static inline void binfs_semgive(struct binfs_state_s *bm) -{ - sem_post(&bm->bm_sem); -} - -/**************************************************************************** - * Name: binfs_open - ****************************************************************************/ - -static int binfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode) -{ - struct binfs_state_s *bm; - int ret = -ENOSYS; - - fvdbg("Open '%s'\n", relpath); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv == NULL && filep->f_inode != NULL); - - /* mountpoint private data from the inode reference from the file - * structure - */ - - bm = (struct binfs_state_s*)filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* BINFS is read-only. Any attempt to open with any kind of write - * access is not permitted. - */ - - if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0) - { - fdbg("Only O_RDONLY supported\n"); - ret = -EACCES; - } - - /* Save open-specific state in filep->f_priv */ - - /* Opening of elements within the pseudo-file system is not yet supported */ - - return ret; -} - -/**************************************************************************** - * Name: binfs_close - ****************************************************************************/ - -static int binfs_close(FAR struct file *filep) -{ - struct binfs_state_s *bm; - int ret = -ENOSYS; - - fvdbg("Closing\n"); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state from the struct file instance */ - /* bf = filep->f_priv; */ - - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* Free the open file state */ - /* free(bf); */ - - filep->f_priv = NULL; - - /* Since open() is not yet supported, neither is close(). */ - - return ret; -} - -/**************************************************************************** - * Name: binfs_read - ****************************************************************************/ - -static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) -{ - struct binfs_state_s *bm; - - fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state data from the struct file instance */ - /* bf = filep->f_priv; */ - - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* Since open is not yet supported, neither is reading */ - - return -ENOSYS; -} - -/**************************************************************************** - * Name: binfs_ioctl - ****************************************************************************/ - -static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) -{ - struct binfs_state_s *bm; - - fvdbg("cmd: %d arg: %08lx\n", cmd, arg); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state from the struct file instance */ - /* bf = filep->f_priv; */ - - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* No ioctl commands yet supported */ - - return -ENOTTY; -} - -/**************************************************************************** - * Name: binfs_opendir - * - * Description: - * Open a directory for read access - * - ****************************************************************************/ - -static int binfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir) -{ - struct binfs_state_s *bm; - int ret; - - fvdbg("relpath: \"%s\"\n", relpath ? relpath : "NULL"); - - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - /* The requested directory must be the volume-relative "root" directory */ - - if (relpath && relpath[0] != '\0') - { - ret = -ENOENT; - goto errout_with_semaphore; - } - - /* Set the index to the first entry */ - - dir->u.binfs.fb_index = 0; - ret = OK; - -errout_with_semaphore: - binfs_semgive(bm); - return ret; -} - -/**************************************************************************** - * Name: binfs_readdir - * - * Description: Read the next directory entry - * - ****************************************************************************/ - -static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) -{ - struct binfs_state_s *bm; - unsigned int index; - int ret; - - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - /* Have we reached the end of the directory */ - - index = dir->u.binfs.fb_index; - if (namedapps[index].name == NULL) - { - /* We signal the end of the directory by returning the - * special error -ENOENT - */ - - fvdbg("Entry %d: End of directory\n", index); - ret = -ENOENT; - } - else - { - /* Save the filename and file type */ - - fvdbg("Entry %d: \"%s\"\n", index, namedapps[index].name); - dir->fd_dir.d_type = DTYPE_FILE; - strncpy(dir->fd_dir.d_name, namedapps[index].name, NAME_MAX+1); - - /* The application list is terminated by an entry with a NULL name. - * Therefore, there is at least one more entry in the list. - */ - - index++; - - /* Set up the next directory entry offset. NOTE that we could use the - * standard f_pos instead of our own private fb_index. - */ - - dir->u.binfs.fb_index = index; - ret = OK; - } - - binfs_semgive(bm); - return ret; -} - -/**************************************************************************** - * Name: binfs_rewindir - * - * Description: Reset directory read to the first entry - * - ****************************************************************************/ - -static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) -{ - struct binfs_state_s *bm; - - fvdbg("Entry\n"); - - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - dir->u.binfs.fb_index = 0; - - binfs_semgive(bm); - return OK; -} - -/**************************************************************************** - * Name: binfs_bind - * - * Description: This implements a portion of the mount operation. This - * function allocates and initializes the mountpoint private data and - * binds the blockdriver inode to the filesystem private data. The final - * binding of the private data (containing the blockdriver) to the - * mountpoint is performed by mount(). - * - ****************************************************************************/ - -static int binfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle) -{ - struct binfs_state_s *bm; - - fvdbg("Entry\n"); - - /* Create an instance of the mountpt state structure */ - - bm = (struct binfs_state_s *)zalloc(sizeof(struct binfs_state_s)); - if (!bm) - { - fdbg("Failed to allocate mountpoint structure\n"); - return -ENOMEM; - } - - /* Initialize the allocated mountpt state structure. The filesystem is - * responsible for one reference ont the blkdriver inode and does not - * have to addref() here (but does have to release in ubind(). - */ - - sem_init(&bm->bm_sem, 0, 1); /* Initialize the semaphore that controls access */ - - /* Mounted! */ - - *handle = (void*)bm; - return OK; -} - -/**************************************************************************** - * Name: binfs_unbind - * - * Description: This implements the filesystem portion of the umount - * operation. - * - ****************************************************************************/ - -static int binfs_unbind(void *handle, FAR struct inode **blkdriver) -{ - struct binfs_state_s *bm = (struct binfs_state_s*)handle; - - fvdbg("Entry\n"); - -#ifdef CONFIG_DEBUG - if (!bm) - { - return -EINVAL; - } -#endif - - /* Check if there are sill any files opened on the filesystem. */ - - /* Release the mountpoint private data */ - - sem_destroy(&bm->bm_sem); - return OK; -} - -/**************************************************************************** - * Name: binfs_statfs - * - * Description: Return filesystem statistics - * - ****************************************************************************/ - -static int binfs_statfs(struct inode *mountpt, struct statfs *buf) -{ - struct binfs_state_s *bm; - - fvdbg("Entry\n"); - - /* Sanity checks */ - - DEBUGASSERT(mountpt && mountpt->i_private); - - /* Get the mountpoint private data from the inode structure */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - /* Fill in the statfs info */ - - memset(buf, 0, sizeof(struct statfs)); - buf->f_type = BINFS_MAGIC; - buf->f_bsize = 0; - buf->f_blocks = 0; - buf->f_bfree = 0; - buf->f_bavail = 0; - buf->f_namelen = NAME_MAX; - - binfs_semgive(bm); - return OK; -} - -/**************************************************************************** - * Name: binfs_stat - * - * Description: Return information about a file or directory - * - ****************************************************************************/ - -static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) -{ - struct binfs_state_s *bm; - int ret; - - fvdbg("Entry\n"); - - /* Sanity checks */ - - DEBUGASSERT(mountpt && mountpt->i_private); - - /* Get the mountpoint private data from the inode structure */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - /* The requested directory must be the volume-relative "root" directory */ - - if (relpath && relpath[0] != '\0') - { - /* Check if there is a file with this name. */ - - if (namedapp_isavail(relpath) < 0) - { - ret = -ENOENT; - goto errout_with_semaphore; - } - - /* It's a execute-only file name */ - - buf->st_mode = S_IFREG|S_IXOTH|S_IXGRP|S_IXUSR; - } - else - { - /* It's a read/execute-only directory name */ - - buf->st_mode = S_IFDIR|S_IROTH|S_IRGRP|S_IRUSR|S_IXOTH|S_IXGRP|S_IXUSR; - } - - /* File/directory size, access block size */ - - buf->st_size = 0; - buf->st_blksize = 0; - buf->st_blocks = 0; - ret = OK; - -errout_with_semaphore: - binfs_semgive(bm); - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_APPS_BINDIR */ - diff --git a/apps/namedapp/exec_namedapp.c b/apps/namedapp/exec_namedapp.c deleted file mode 100644 index 264fca7b9..000000000 --- a/apps/namedapp/exec_namedapp.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * apps/namedaps/exec_namedapp.c - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * With updates, modifications, and general maintenance by: - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Auther: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "namedapp.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: namedapp_getname - * - * Description: - * Return the name of the application at index in the table of named - * applications. - * - ****************************************************************************/ - -const char *namedapp_getname(int index) -{ - if (index < 0 || index >= number_namedapps()) - { - return NULL; - } - - return namedapps[index].name; -} - -/**************************************************************************** - * Name: namedapp_isavail - * - * Description: - * Return the index into the table of applications for the applicaiton with - * the name 'appname'. - * - ****************************************************************************/ - -int namedapp_isavail(FAR const char *appname) -{ - int i; - - for (i = 0; namedapps[i].name; i++) - { - if (!strcmp(namedapps[i].name, appname)) - { - return i; - } - } - - set_errno(ENOENT); - return ERROR; -} - -/**************************************************************************** - * Name: namedapp_isavail - * - * Description: - * Execute the application with name 'appname', providing the arguments - * in the argv[] array. - * - * Returned Value: - * On success, the task ID of the named application is returned. On - * failure, -1 (ERROR) is returned an the errno value is set appropriately. - * - ****************************************************************************/ - -int exec_namedapp(FAR const char *appname, FAR const char **argv) -{ - pid_t pid; - int index; - - /* Verify that an application with this name exists */ - - index = namedapp_isavail(appname); - if (index >= 0) - { - /* Disable pre-emption. This means that although we start the named - * application here, it will not actually run until pre-emption is - * re-enabled below. - */ - - sched_lock(); - - /* Start the named application task */ - - pid = TASK_CREATE(namedapps[index].name, namedapps[index].priority, - namedapps[index].stacksize, namedapps[index].main, - (argv) ? &argv[1] : (const char **)NULL); - - /* If robin robin scheduling is enabled, then set the scheduling policy - * of the new task to SCHED_RR before it has a chance to run. - */ - -#if CONFIG_RR_INTERVAL > 0 - if (pid > 0) - { - struct sched_param param; - - /* Pre-emption is disabled so the task creation and the - * following operation will be atomic. The priority of the - * new task cannot yet have changed from its initial value. - */ - - param.sched_priority = namedapps[index].priority; - sched_setscheduler(pid, SCHED_RR, ¶m); - } -#endif - /* Now let the named application run */ - - sched_unlock(); - - /* Return the task ID of the new task if the task was sucessfully - * started. Otherwise, pid will be ERROR (and the errno value will - * be set appropriately). - */ - - return pid; - } - - /* Return ERROR with errno set appropriately */ - - return ERROR; -} diff --git a/apps/namedapp/namedapp.c b/apps/namedapp/namedapp.c deleted file mode 100644 index d59ce6e3b..000000000 --- a/apps/namedapp/namedapp.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * apps/namedaps/namedapp.c - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Authors: Uros Platise - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#include "namedapp_proto.h" - -const struct namedapp_s namedapps[] = -{ -# include "namedapp_list.h" - { NULL, 0, 0, 0 } -}; - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int number_namedapps(void) -{ - return sizeof(namedapps)/sizeof(struct namedapp_s) - 1; -} - - diff --git a/apps/namedapp/namedapp.h b/apps/namedapp/namedapp.h deleted file mode 100644 index 7fcdf42dc..000000000 --- a/apps/namedapp/namedapp.h +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * apps/namedaps/namedapp.h - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Authors: Uros Platise - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __APPS_NAMEDAPP_NAMEDAPP_H -#define __APPS_NAMEDAPP_NAMEDAPP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -EXTERN const struct namedapp_s namedapps[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -EXTERN int number_namedapps(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __APPS_NAMEDAPP_NAMEDAPP_H */ - diff --git a/apps/nshlib/Kconfig b/apps/nshlib/Kconfig index 17b107b8f..e60e9c480 100644 --- a/apps/nshlib/Kconfig +++ b/apps/nshlib/Kconfig @@ -15,12 +15,12 @@ if NSH_LIBRARY config NSH_BUILTIN_APPS bool "Enable built-in applications" default y - depends on NAMEDAPP + depends on BUILTIN ---help--- - Support external registered, "named" applications that can be + Support external registered, "built-in" applications that can be executed from the NSH command line (see apps/README.txt for - more information). This options requires support for named applications - (NAMEDAPP). + more information). This options requires support for builtin + applications (BUILTIN). menu "Disable Individual commands" diff --git a/apps/nshlib/README.txt b/apps/nshlib/README.txt index bc626e699..006839628 100644 --- a/apps/nshlib/README.txt +++ b/apps/nshlib/README.txt @@ -945,7 +945,7 @@ NSH-Specific Configuration Settings the configs//defconfig file: * CONFIG_NSH_BUILTIN_APPS - Support external registered, "named" applications that can be + Support external registered, "builtin" applications that can be executed from the NSH command line (see apps/README.txt for more information). diff --git a/apps/nshlib/nsh_apps.c b/apps/nshlib/nsh_apps.c index 7dbaf9ba8..ea8791eef 100644 --- a/apps/nshlib/nsh_apps.c +++ b/apps/nshlib/nsh_apps.c @@ -90,7 +90,7 @@ * Attempt to execute the application task whose name is 'cmd' * * Returned Value: - * <0 If exec_namedapp() fails, then the negated errno value + * <0 If exec_builtin() fails, then the negated errno value * is returned. * -1 (ERROR) if the application task corresponding to 'cmd' could not * be started (possibly because it doesn not exist). @@ -119,7 +119,7 @@ int nsh_execapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, * applications. */ - ret = exec_namedapp(cmd, (FAR const char **)argv); + ret = exec_builtin(cmd, (FAR const char **)argv); if (ret >= 0) { /* The application was successfully started (but still blocked because @@ -205,7 +205,7 @@ int nsh_execapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, sched_unlock(); - /* If exec_namedapp() or waitpid() failed, then return the negated errno + /* If exec_builtin() or waitpid() failed, then return the negated errno * value. */ diff --git a/apps/nshlib/nsh_parse.c b/apps/nshlib/nsh_parse.c index 27068acff..70fa39f62 100644 --- a/apps/nshlib/nsh_parse.c +++ b/apps/nshlib/nsh_parse.c @@ -605,7 +605,7 @@ static inline void help_builtins(FAR struct nsh_vtbl_s *vtbl) /* List the set of available built-in commands */ nsh_output(vtbl, "\nBuiltin Apps:\n"); - for (i = 0; (name = namedapp_getname(i)) != NULL; i++) + for (i = 0; (name = builtin_getname(i)) != NULL; i++) { nsh_output(vtbl, " %s\n", name); } @@ -726,7 +726,7 @@ static int cmd_exit(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) * Exectue the command in argv[0] * * Returned Value: - * <0 If exec_namedapp() fails, then the negated errno value + * <0 If exec_builtin() fails, then the negated errno value * is returned. * -1 (ERRROR) if the command was unsuccessful * 0 (OK) if the command was successful @@ -1439,13 +1439,13 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) } /* Handle the case where the command is executed in background. - * However is app is to be started as namedapp new process will + * However is app is to be started as builtin new process will * be created anyway, so skip this step. */ #ifndef CONFIG_NSH_DISABLEBG if (vtbl->np.np_bg #ifdef CONFIG_NSH_BUILTIN_APPS - && namedapp_isavail(argv[0]) < 0 + && builtin_isavail(argv[0]) < 0 #endif ) { diff --git a/nuttx/Documentation/NuttShell.html b/nuttx/Documentation/NuttShell.html index 0b5f7aa11..cc3f078dd 100644 --- a/nuttx/Documentation/NuttShell.html +++ b/nuttx/Documentation/NuttShell.html @@ -2515,7 +2515,7 @@ nsh> CONFIG_NSH_BUILTIN_APPS - Support external registered, "named" applications that can be + Support external registered, "builtin" applications that can be executed from the NSH command line (see apps/README.txt for more information). @@ -3239,48 +3239,48 @@ Builtin Apps: Note that no detailed help information beyond the name of the built-in application is provided.

            -

            4.3.1 Named Applications

            +

            4.3.1 Built-In Applications

            Overview. - The underlying logic that supports the NSH built-in applications is called "Named Applications". - The named application logic can be found at apps/namedapp. + The underlying logic that supports the NSH built-in applications is called "Built-In Applications". + The builtin application logic can be found at apps/builtin. This logic simply does the following:

            1. - It supports registration mechanism so that named applications can dynamically register themselves at build time, and + It supports registration mechanism so that builtin applications can dynamically register themselves at build time, and

            2. - Utility functions to look up, list, and execute the named applications. + Utility functions to look up, list, and execute the builtin applications.

            - Named Application Utility Functions. - The utility functions exported by the named application logic are prototyped in apps/include/apps.h. + Built-In Application Utility Functions. + The utility functions exported by the builtin application logic are prototyped in apps/include/apps.h. These utility functions include:

            • - int namedapp_isavail(FAR const char *appname); + int builtin_isavail(FAR const char *appname); Checks for availability of application registered as appname during build time.

            • - const char *namedapp_getname(int index); + const char *builtin_getname(int index); Returns a pointer to a name of built-in application pointed by the index. This is the utility function that is used by NSH in order to list the available built-in applications when "nsh> help" is entered.

            • - int exec_namedapp(FAR const char *appname, FAR const char **argv); - Executes built-in named application registered during compile time. + int exec_builtin(FAR const char *appname, FAR const char **argv); + Executes built-in builtin application registered during compile time. This is the utility function used by NSH to execute the built-in application.

            @@ -3292,23 +3292,23 @@ Builtin Apps:

            1. - apps/namedapp/namedapp_proto.h: + apps/builtin/builtin_proto.h: Prototypes of application task entry points.

            2. - apps/namedapp/namedapp_list.h: + apps/builtin/builtin_list.h: Application specific information and start-up requirements

            - Registration of Named Applications. + Registration of Built-In Applications. The NuttX build occurs in several phases as different build targets are executed: (1) context when the configuration is established, (2) depend when target dependencies are generated, and (3) default (all) when the normal compilation and link operations are performed. - Named application information is collected during the make context build phase. + Built-in application information is collected during the make context build phase.

            @@ -3376,7 +3376,7 @@ make apps_distclean

          - Logic for the context target in apps/examples/hello/Makefile registers the hello_main() application in the namedapp's namedapp_proto.hand namedapp_list.h files. + Logic for the context target in apps/examples/hello/Makefile registers the hello_main() application in the builtin's builtin_proto.hand builtin_list.h files. That logic that does that in apps/examples/hello/Makefile is abstracted below:

            @@ -3388,13 +3388,13 @@ make apps_distclean include $(APPDIR)/Make.defs

        - This defines a macro called REGISTER that adds data to the namedapp header files: + This defines a macro called REGISTER that adds data to the builtin header files: 

           define REGISTER
     @echo "Register: $1"
-    @echo "{ \"$1\", $2, $3, $4 }," >> "$(APPDIR)/namedapp/namedapp_list.h"
-    @echo "EXTERN int $4(int argc, char *argv[]);" >> "$(APPDIR)/namedapp/namedapp_proto.h"
+    @echo "{ \"$1\", $2, $3, $4 }," >> "$(APPDIR)/builtin/builtin_list.h"
+    @echo "EXTERN int $4(int argc, char *argv[]);" >> "$(APPDIR)/builtin/builtin_proto.h"
 endef

        @@ -3412,7 +3412,7 @@ STACKSIZE = 2048

      • - And finally, the Makefile invokes the REGISTER macro to added the hello_main() named application. + And finally, the Makefile invokes the REGISTER macro to added the hello_main() builtin application. Then, when the system build completes, the hello command can be executed from the NSH command line. When the hello command is executed, it will start the task with entry point hello_main() with the default priority and with a stack size of 2K.

        @@ -3424,16 +3424,16 @@ STACKSIZE = 2048

        - Other Uses of Named Application. - The primary purpose of named applications is to support command line execution of applications from NSH. - However, there are two other uses of named applications that should be mentioned. + Other Uses of Built-In Application. + The primary purpose of builtin applications is to support command line execution of applications from NSH. + However, there are two other uses of builtin applications that should be mentioned.

        1. - Named Application Start-Up main() function. - A named application can even be used as the main, start-up entry point into your embedded software. + Built-In Application Start-Up main() function. + A builtin application can even be used as the main, start-up entry point into your embedded software. When the user defines this option in the NuttX configuration file: 

            @@ -3451,11 +3451,11 @@ CONFIG_BUILTIN_APP_START=<application name>
 
   
          • 
     
            binfs.
-    binfs is a tiny file system located at apps/namedapp/binfs.c.
-     This provides an alternative what of visualizing installed named applications.
-     Without binfs, you can see the installed named applications using the NSH help command.
+    binfs is a tiny file system located at apps/builtin/binfs.c.
+     This provides an alternative what of visualizing installed builtin applications.
+     Without binfs, you can see the installed builtin applications using the NSH help command.
      binfs will create a tiny pseudo-file system mounted at /bin.
-     Using binfs, you can see the available named applications by listing the contents of  /bin directory.
+     Using binfs, you can see the available builtin applications by listing the contents of  /bin directory.
      This gives some superficial Unix compatibility, but does not really add any new functionality.
        @@ -3762,7 +3762,12 @@ mount -t vfat /dev/ram1 /tmp
      • Background command priority
      • binfs
      • Built-In applications
        • +
      • Built-In application start-up main()
      • Built-in variables
        • +
      • builtin_getname()
        • +
      • builtin_isavail()
        • +
      • builtin_list.h
        • +
      • builtin_proto.h
      • base64dec
      • base64enc
      • cat
        • @@ -3827,12 +3832,12 @@ mount -t vfat /dev/ram1 /tmp
      • echo
      • Environment Variables
      • /etc/init.d/rcS +
      +
  • exec
    • -
  • exec_namedapp()
    • +
  • exec_builtin()
  • exit
  • free
    • - -
  • g_cmdmap
  • genromfs
  • get
    • @@ -3858,12 +3863,6 @@ mount -t vfat /dev/ram1 /tmp
  • mkromfsimg.sh
  • mount
  • mv
    • -
  • Named application start-up main()
    • -
  • Named applications
    • -
  • namedapp_getname()
    • -
  • namedapp_isavail()
    • -
  • namedapp_list.h
    • -
  • namedapp_proto.h
  • nfsmount
  • nice
  • NSH library (nshlib)
    • @@ -3887,7 +3886,7 @@ mount -t vfat /dev/ram1 /tmp
  • PWD
  • rcS.template
  • Re-directed commands
    • -
  • Registration of named applications
    • +
  • Registration of builtin applications
  • rm
  • rmdir
  • ROMFS, Modifying the ROMFS image
    • diff --git a/nuttx/configs/cloudctrl/nsh/defconfig b/nuttx/configs/cloudctrl/nsh/defconfig index fbb5e8c13..99c7eb790 100644 --- a/nuttx/configs/cloudctrl/nsh/defconfig +++ b/nuttx/configs/cloudctrl/nsh/defconfig @@ -505,7 +505,7 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/ez80f910200kitg/ostest/defconfig b/nuttx/configs/ez80f910200kitg/ostest/defconfig index 50efbfdaf..80c9e682e 100644 --- a/nuttx/configs/ez80f910200kitg/ostest/defconfig +++ b/nuttx/configs/ez80f910200kitg/ostest/defconfig @@ -334,7 +334,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/ez80f910200zco/ostest/defconfig b/nuttx/configs/ez80f910200zco/ostest/defconfig index 3a1352333..88c1b7279 100644 --- a/nuttx/configs/ez80f910200zco/ostest/defconfig +++ b/nuttx/configs/ez80f910200zco/ostest/defconfig @@ -342,7 +342,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/fire-stm32v2/nsh/defconfig b/nuttx/configs/fire-stm32v2/nsh/defconfig index 2fb623a0d..c42bb1569 100644 --- a/nuttx/configs/fire-stm32v2/nsh/defconfig +++ b/nuttx/configs/fire-stm32v2/nsh/defconfig @@ -531,7 +531,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/p112/ostest/defconfig b/nuttx/configs/p112/ostest/defconfig index c30adcf22..3699475c5 100644 --- a/nuttx/configs/p112/ostest/defconfig +++ b/nuttx/configs/p112/ostest/defconfig @@ -370,7 +370,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/shenzhou/nsh/defconfig b/nuttx/configs/shenzhou/nsh/defconfig index 36f8e40fc..c54d714d0 100644 --- a/nuttx/configs/shenzhou/nsh/defconfig +++ b/nuttx/configs/shenzhou/nsh/defconfig @@ -505,7 +505,7 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/shenzhou/nxwm/defconfig b/nuttx/configs/shenzhou/nxwm/defconfig index 0f100ed5e..975327747 100644 --- a/nuttx/configs/shenzhou/nxwm/defconfig +++ b/nuttx/configs/shenzhou/nxwm/defconfig @@ -630,7 +630,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/shenzhou/thttpd/defconfig b/nuttx/configs/shenzhou/thttpd/defconfig index ccbcf9ab2..958ab02ed 100644 --- a/nuttx/configs/shenzhou/thttpd/defconfig +++ b/nuttx/configs/shenzhou/thttpd/defconfig @@ -474,7 +474,7 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index f1dfd0dd2..03f163ea5 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -148,9 +148,9 @@ If you are running X11 applications as NSH add-on programs, then the stack size of the add-on program is controlled in another way. Here are the steps for increasing the stack size in that case: - cd ../apps/namedapps # Go to the namedapps directory - vi namedapps_list.h # Edit this file and increase the stack size of the add-on - rm .built *.o # This will force the namedapps logic to rebuild + cd ../apps/builtin # Go to the builtin apps directory + vi builtin_list.h # Edit this file and increase the stack size of the add-on + rm .built *.o # This will force the builtin apps logic to rebuild Buffered I/O Issues ------------------- diff --git a/nuttx/configs/sim/cxxtest/defconfig b/nuttx/configs/sim/cxxtest/defconfig index 648a92851..6ac45d44d 100644 --- a/nuttx/configs/sim/cxxtest/defconfig +++ b/nuttx/configs/sim/cxxtest/defconfig @@ -298,7 +298,7 @@ CONFIG_UCLIBCXX_HAVE_LIBSUPCXX=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/sim/nxwm/defconfig b/nuttx/configs/sim/nxwm/defconfig index 6a295ef4f..90ee00f50 100644 --- a/nuttx/configs/sim/nxwm/defconfig +++ b/nuttx/configs/sim/nxwm/defconfig @@ -376,7 +376,7 @@ CONFIG_HAVE_CXX=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index beee30639..55687c366 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -297,7 +297,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm3220g-eval/nxwm/defconfig b/nuttx/configs/stm3220g-eval/nxwm/defconfig index 11e88f764..ab061f07a 100644 --- a/nuttx/configs/stm3220g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3220g-eval/nxwm/defconfig @@ -659,7 +659,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm3240g-eval/discover/defconfig b/nuttx/configs/stm3240g-eval/discover/defconfig index 152486d1b..e11d39ce1 100644 --- a/nuttx/configs/stm3240g-eval/discover/defconfig +++ b/nuttx/configs/stm3240g-eval/discover/defconfig @@ -494,7 +494,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm3240g-eval/xmlrpc/defconfig b/nuttx/configs/stm3240g-eval/xmlrpc/defconfig index 6b4c9af70..4f621d453 100644 --- a/nuttx/configs/stm3240g-eval/xmlrpc/defconfig +++ b/nuttx/configs/stm3240g-eval/xmlrpc/defconfig @@ -487,7 +487,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f100rc_generic/nsh/defconfig b/nuttx/configs/stm32f100rc_generic/nsh/defconfig index a0228a3de..65ac9a73d 100644 --- a/nuttx/configs/stm32f100rc_generic/nsh/defconfig +++ b/nuttx/configs/stm32f100rc_generic/nsh/defconfig @@ -428,7 +428,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -CONFIG_NAMEDAPP=y +CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/stm32f100rc_generic/ostest/defconfig b/nuttx/configs/stm32f100rc_generic/ostest/defconfig index 0041feb50..2d2842c54 100644 --- a/nuttx/configs/stm32f100rc_generic/ostest/defconfig +++ b/nuttx/configs/stm32f100rc_generic/ostest/defconfig @@ -410,7 +410,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f4discovery/cxxtest/defconfig b/nuttx/configs/stm32f4discovery/cxxtest/defconfig index 6487742cf..e7fa49954 100644 --- a/nuttx/configs/stm32f4discovery/cxxtest/defconfig +++ b/nuttx/configs/stm32f4discovery/cxxtest/defconfig @@ -426,7 +426,7 @@ CONFIG_UCLIBCXX_HAVE_LIBSUPCXX=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f4discovery/elf/defconfig b/nuttx/configs/stm32f4discovery/elf/defconfig index 9379c885b..3f5a5d0fc 100644 --- a/nuttx/configs/stm32f4discovery/elf/defconfig +++ b/nuttx/configs/stm32f4discovery/elf/defconfig @@ -460,7 +460,7 @@ CONFIG_HAVE_CXX=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f4discovery/nxlines/defconfig b/nuttx/configs/stm32f4discovery/nxlines/defconfig index 8609993ea..58eebd41f 100644 --- a/nuttx/configs/stm32f4discovery/nxlines/defconfig +++ b/nuttx/configs/stm32f4discovery/nxlines/defconfig @@ -518,7 +518,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f4discovery/ostest/defconfig b/nuttx/configs/stm32f4discovery/ostest/defconfig index b29622c8e..5fdd30f57 100644 --- a/nuttx/configs/stm32f4discovery/ostest/defconfig +++ b/nuttx/configs/stm32f4discovery/ostest/defconfig @@ -430,7 +430,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/stm32f4discovery/winbuild/defconfig b/nuttx/configs/stm32f4discovery/winbuild/defconfig index ac8a18c9b..95be14886 100644 --- a/nuttx/configs/stm32f4discovery/winbuild/defconfig +++ b/nuttx/configs/stm32f4discovery/winbuild/defconfig @@ -430,7 +430,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/vsn/src/README.txt b/nuttx/configs/vsn/src/README.txt index 4e2d50e0b..87a538a10 100644 --- a/nuttx/configs/vsn/src/README.txt +++ b/nuttx/configs/vsn/src/README.txt @@ -12,7 +12,7 @@ Execution starts in the following order: is set. It must be set for the VSN board. - boot, performs initial chip and board initialization - - sched/os_bringup.c then calls either user_start or exec_namedapp() + - sched/os_bringup.c then calls either user_start or exec_builtin() with application as set in the .config @@ -55,4 +55,5 @@ Compile notes To link-in the sif_main() utility do, in this folder: - make context TOPDIR= -This will result in registering the application into the namedapp. +This will result in registering the application into the builtin application +registry. diff --git a/nuttx/configs/xtrs/nsh/defconfig b/nuttx/configs/xtrs/nsh/defconfig index 8730ebab7..72b32d9aa 100644 --- a/nuttx/configs/xtrs/nsh/defconfig +++ b/nuttx/configs/xtrs/nsh/defconfig @@ -303,7 +303,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/xtrs/ostest/defconfig b/nuttx/configs/xtrs/ostest/defconfig index a0a100bcf..74a0199df 100644 --- a/nuttx/configs/xtrs/ostest/defconfig +++ b/nuttx/configs/xtrs/ostest/defconfig @@ -302,7 +302,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/xtrs/pashello/defconfig b/nuttx/configs/xtrs/pashello/defconfig index d23c50716..abdaf1f35 100644 --- a/nuttx/configs/xtrs/pashello/defconfig +++ b/nuttx/configs/xtrs/pashello/defconfig @@ -303,7 +303,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z16f2800100zcog/ostest/defconfig b/nuttx/configs/z16f2800100zcog/ostest/defconfig index defd3d5ef..64828738f 100644 --- a/nuttx/configs/z16f2800100zcog/ostest/defconfig +++ b/nuttx/configs/z16f2800100zcog/ostest/defconfig @@ -342,7 +342,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z16f2800100zcog/pashello/defconfig b/nuttx/configs/z16f2800100zcog/pashello/defconfig index f3067a9e7..ba99283d3 100644 --- a/nuttx/configs/z16f2800100zcog/pashello/defconfig +++ b/nuttx/configs/z16f2800100zcog/pashello/defconfig @@ -342,7 +342,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z80sim/nsh/defconfig b/nuttx/configs/z80sim/nsh/defconfig index fb9fac546..d13f0f7f7 100644 --- a/nuttx/configs/z80sim/nsh/defconfig +++ b/nuttx/configs/z80sim/nsh/defconfig @@ -303,7 +303,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z80sim/ostest/defconfig b/nuttx/configs/z80sim/ostest/defconfig index d3410d52d..bd4144821 100644 --- a/nuttx/configs/z80sim/ostest/defconfig +++ b/nuttx/configs/z80sim/ostest/defconfig @@ -302,7 +302,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z80sim/pashello/defconfig b/nuttx/configs/z80sim/pashello/defconfig index e7dee626c..58d609c4b 100644 --- a/nuttx/configs/z80sim/pashello/defconfig +++ b/nuttx/configs/z80sim/pashello/defconfig @@ -302,7 +302,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z8encore000zco/ostest/defconfig b/nuttx/configs/z8encore000zco/ostest/defconfig index 7d9b227f4..7bd512727 100644 --- a/nuttx/configs/z8encore000zco/ostest/defconfig +++ b/nuttx/configs/z8encore000zco/ostest/defconfig @@ -329,7 +329,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/configs/z8f64200100kit/ostest/defconfig b/nuttx/configs/z8f64200100kit/ostest/defconfig index a34952987..e98e41561 100644 --- a/nuttx/configs/z8f64200100kit/ostest/defconfig +++ b/nuttx/configs/z8f64200100kit/ostest/defconfig @@ -329,7 +329,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -# CONFIG_NAMEDAPP is not set +# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/sched/os_bringup.c b/nuttx/sched/os_bringup.c index e0a236bbe..4b5adcae1 100644 --- a/nuttx/sched/os_bringup.c +++ b/nuttx/sched/os_bringup.c @@ -189,11 +189,11 @@ int os_bringup(void) svdbg("Starting init thread\n"); #ifdef CONFIG_BUILTIN_APP_START - /* Start the built-in named application, passing an "init" argument, so that + /* Start the built-in application, passing an "init" argument, so that * application can distinguish different run-levels */ - init_taskid = exec_namedapp(CONFIG_BUILTIN_APP_START, argv); + init_taskid = exec_builtin(CONFIG_BUILTIN_APP_START, argv); #else /* Start the default application at CONFIG_USER_ENTRYPOINT() */ -- cgit v1.2.3 From 3fe53af6be14a28174eec48b5740dbbe7c1f818a Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 23 Dec 2012 22:17:09 +0000 Subject: Remove .context kludge from apps/ directory git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5455 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 4 +++ apps/Make.defs | 9 ++++--- apps/Makefile | 9 +------ apps/builtin/Makefile | 33 ++++++++++++++--------- apps/builtin/registry/Makefile | 54 ++++++++++++++++++++++++++++++++++++++ apps/examples/adc/Makefile | 9 ++++--- apps/examples/buttons/Makefile | 9 ++++--- apps/examples/can/Makefile | 9 ++++--- apps/examples/cdcacm/Makefile | 11 +++++--- apps/examples/composite/Makefile | 11 +++++--- apps/examples/cxxtest/Makefile | 9 ++++--- apps/examples/dhcpd/Makefile | 9 ++++--- apps/examples/discover/Makefile | 9 ++++--- apps/examples/ftpc/Makefile | 10 ++++--- apps/examples/ftpd/Makefile | 11 +++++--- apps/examples/hello/Makefile | 9 ++++--- apps/examples/helloxx/Makefile | 9 ++++--- apps/examples/json/Makefile | 9 ++++--- apps/examples/keypadtest/Makefile | 9 ++++--- apps/examples/lcdrw/Makefile | 9 ++++--- apps/examples/modbus/Makefile | 9 ++++--- apps/examples/nettest/Makefile | 9 ++++--- apps/examples/nx/Makefile | 9 ++++--- apps/examples/nxhello/Makefile | 9 ++++--- apps/examples/nximage/Makefile | 9 ++++--- apps/examples/nxlines/Makefile | 9 ++++--- apps/examples/nxtext/Makefile | 9 ++++--- apps/examples/ostest/Makefile | 9 ++++--- apps/examples/pwm/Makefile | 9 ++++--- apps/examples/qencoder/Makefile | 9 ++++--- apps/examples/relays/Makefile | 9 ++++--- apps/examples/telnetd/Makefile | 9 ++++--- apps/examples/tiff/Makefile | 9 ++++--- apps/examples/touchscreen/Makefile | 9 ++++--- apps/examples/usbstorage/Makefile | 11 +++++--- apps/examples/usbterm/Makefile | 9 ++++--- apps/examples/watchdog/Makefile | 9 ++++--- apps/examples/wgetjson/Makefile | 9 ++++--- apps/examples/xmlrpc/Makefile | 9 ++++--- apps/graphics/tiff/Makefile | 1 - apps/interpreters/ficl/Makefile | 1 - apps/modbus/Makefile | 1 - apps/nshlib/Makefile | 1 - apps/system/free/Makefile | 10 ++++--- apps/system/i2c/Makefile | 12 +++++---- apps/system/install/Makefile | 10 ++++--- apps/system/poweroff/Makefile | 10 ++++--- apps/system/ramtron/Makefile | 10 ++++--- apps/system/readline/Makefile | 1 - apps/system/sdcard/Makefile | 10 ++++--- apps/system/sysinfo/Makefile | 10 ++++--- nuttx/Documentation/NuttShell.html | 9 ++----- nuttx/configs/vsn/src/Makefile | 9 ++++--- 53 files changed, 318 insertions(+), 201 deletions(-) create mode 100644 apps/builtin/registry/Makefile diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 886526b18..8999047ef 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -440,4 +440,8 @@ files. It makes sense for 'leaf' Makefiles to have this dependency, but it does not make sense for upper-level Makefiles. * namedapp/: Renamed to builtins in preparation for another change. + * .context: Removed the .context kludge. This causes lots of problems + when changing configurations because there is no easy way to get the + system to rebuild the context. Now, the context will be rebuilt + whenever there is a change in either .config or the Makefile. diff --git a/apps/Make.defs b/apps/Make.defs index 12b351e7f..217137a29 100644 --- a/apps/Make.defs +++ b/apps/Make.defs @@ -34,8 +34,11 @@ # ############################################################################ +BUILTIN_REGISTRY = $(APPDIR)$(DELIM)builtin$(DELIM)registry + define REGISTER - @echo "Register: $1" - @echo "{ \"$1\", $2, $3, $4 }," >> "$(APPDIR)/builtin/builtin_list.h" - @echo "EXTERN int $4(int argc, char *argv[]);" >> "$(APPDIR)/builtin/builtin_proto.h" + $(Q) echo "Register: $1" + $(Q) echo "{ \"$1\", $2, $3, $4 }," > "$(BUILTIN_REGISTRY)$(DELIM)$4.bdat" + $(Q) echo "int $4(int argc, char *argv[]);" > "$(BUILTIN_REGISTRY)$(DELIM)$4.pdat" + $(Q) touch "$(BUILTIN_REGISTRY)$(DELIM).updated" endef diff --git a/apps/Makefile b/apps/Makefile index 299560195..cf6b33cd7 100644 --- a/apps/Makefile +++ b/apps/Makefile @@ -132,21 +132,16 @@ $(INSTALLED_APPS): $(BIN): $(INSTALLED_APPS) -.context: +context: ifeq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) for %%G in ($(INSTALLED_APPS)) do ( \ - if exist %%G\.context del /f /q %%G\.context \ $(MAKE) -C %%G TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" context \ ) else $(Q) for dir in $(INSTALLED_APPS) ; do \ - rm -f $$dir/.context ; \ $(MAKE) -C $$dir TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" context ; \ done endif - $(Q) touch $@ - -context: .context .depend: context Makefile $(SRCS) ifeq ($(CONFIG_WINDOWS_NATIVE),y) @@ -183,7 +178,6 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y) $(MAKE) -C %%G distclean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" \ ) $(call DELFILE, .config) - $(call DELFILE, .context) $(call DELFILE, .depend) $(Q) ( if exist external ( \ echo ********************************************************" \ @@ -195,7 +189,6 @@ else $(MAKE) -C $$dir distclean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)"; \ done $(call DELFILE, .config) - $(call DELFILE, .context) $(call DELFILE, .depend) $(Q) ( if [ -e external ]; then \ echo "********************************************************"; \ diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index 72ba0347f..6633146e9 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -33,12 +33,9 @@ # ############################################################################ --include $(TOPDIR)/.config -include $(TOPDIR)/Make.defs include $(APPDIR)/Make.defs -# NSH Library - # Source and object files ASRCS = @@ -70,7 +67,7 @@ VPATH = # Build Targets all: .built -.PHONY: .context context depend clean distclean +.PHONY: context depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -78,16 +75,27 @@ $(AOBJS): %$(OBJEXT): %.S $(COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) -.built: $(OBJS) +builtin_list.h: registry/.updated + $(call DELFILE, builtin_list.h) +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) for /f %%G in ('dir /b registry\*.bdat`) do ( type registry\%%G >> builtin_list.h ) +else + $(Q) for file in `ls registry/*.bdat`; do cat $$file >> builtin_list.h; done +endif + +builtin_proto.h: registry/.updated + $(call DELFILE, builtin_proto.h) +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) for /f %%G in ('dir /b registry\*.pdat`) do ( type registry\%%G >> builtin_proto.h ) +else + $(Q) for file in `ls registry/*.pdat`; do cat $$file >> builtin_proto.h; done +endif + +.built: builtin_list.h builtin_proto.h $(OBJS) $(call ARCHIVE, $(BIN), $(OBJS)) $(Q) touch .built -.context: - @echo "/* List of application requirements, generated during make context. */" > builtin_list.h - @echo "/* List of application entry points, generated during make context. */" > builtin_proto.h - $(Q) touch $@ - -context: .context +context: .depend: Makefile $(SRCS) $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep @@ -100,11 +108,10 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) + $(Q) $(MAKE) -C registry distclean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" $(call DELFILE, Make.dep) $(call DELFILE, .depend) $(call DELFILE, builtin_list.h) $(call DELFILE, builtin_proto.h) -include Make.dep - diff --git a/apps/builtin/registry/Makefile b/apps/builtin/registry/Makefile new file mode 100644 index 000000000..9117f53d6 --- /dev/null +++ b/apps/builtin/registry/Makefile @@ -0,0 +1,54 @@ +############################################################################ +# apps/builtin/registry/Makefile +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +include $(APPDIR)/Make.defs + +# NSH Library + +all: +.PHONY: context depend clean distclean + +context: + +depend: + +clean: + $(call CLEAN) + +distclean: clean + $(call DELFILE, *.bdat) + $(call DELFILE, *.pdat) + $(call DELFILE, .updated) diff --git a/apps/examples/adc/Makefile b/apps/examples/adc/Makefile index 69862b383..55bc259e4 100644 --- a/apps/examples/adc/Makefile +++ b/apps/examples/adc/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/buttons/Makefile b/apps/examples/buttons/Makefile index 77c1cd67d..ac1f2f05a 100644 --- a/apps/examples/buttons/Makefile +++ b/apps/examples/buttons/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/can/Makefile b/apps/examples/can/Makefile index 8924797e3..5df96e1e7 100644 --- a/apps/examples/can/Makefile +++ b/apps/examples/can/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/cdcacm/Makefile b/apps/examples/cdcacm/Makefile index e8d03807d..d9e19e906 100644 --- a/apps/examples/cdcacm/Makefile +++ b/apps/examples/cdcacm/Makefile @@ -87,12 +87,17 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) + +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) - @touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/composite/Makefile b/apps/examples/composite/Makefile index 016ccbe3e..b1fe49308 100644 --- a/apps/examples/composite/Makefile +++ b/apps/examples/composite/Makefile @@ -87,14 +87,17 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) + +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/cxxtest/Makefile b/apps/examples/cxxtest/Makefile index f0764b6e9..cba9f0a4f 100644 --- a/apps/examples/cxxtest/Makefile +++ b/apps/examples/cxxtest/Makefile @@ -100,13 +100,14 @@ $(CXXOBJS): %$(OBJEXT): %.cxx $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_HELLOXX_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CXX)" -- $(CXXFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/dhcpd/Makefile b/apps/examples/dhcpd/Makefile index a41db5cdd..0522d4cc4 100644 --- a/apps/examples/dhcpd/Makefile +++ b/apps/examples/dhcpd/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/discover/Makefile b/apps/examples/discover/Makefile index 2ce52a18e..b0285fbff 100644 --- a/apps/examples/discover/Makefile +++ b/apps/examples/discover/Makefile @@ -84,13 +84,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/ftpc/Makefile b/apps/examples/ftpc/Makefile index 29960fb94..e09779abd 100644 --- a/apps/examples/ftpc/Makefile +++ b/apps/examples/ftpc/Makefile @@ -83,11 +83,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -102,7 +105,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/examples/ftpd/Makefile b/apps/examples/ftpd/Makefile index 0b43b85a9..dc53bfdea 100644 --- a/apps/examples/ftpd/Makefile +++ b/apps/examples/ftpd/Makefile @@ -78,14 +78,17 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,ftpd_start,SCHED_PRIORITY_DEFAULT,2048,ftpd_start) + +$(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,ftpd_stop,SCHED_PRIORITY_DEFAULT,2048,ftpd_stop) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat $(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/hello/Makefile b/apps/examples/hello/Makefile index 560b0da35..c4e6f735a 100644 --- a/apps/examples/hello/Makefile +++ b/apps/examples/hello/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_HELLO_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/helloxx/Makefile b/apps/examples/helloxx/Makefile index 062da7d58..df1b360a5 100644 --- a/apps/examples/helloxx/Makefile +++ b/apps/examples/helloxx/Makefile @@ -100,13 +100,14 @@ $(CXXOBJS): %$(OBJEXT): %.cxx $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_HELLOXX_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/json/Makefile b/apps/examples/json/Makefile index c3e9203f9..1e42757b8 100644 --- a/apps/examples/json/Makefile +++ b/apps/examples/json/Makefile @@ -81,13 +81,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/keypadtest/Makefile b/apps/examples/keypadtest/Makefile index 3de0556a2..0c40a5c6c 100644 --- a/apps/examples/keypadtest/Makefile +++ b/apps/examples/keypadtest/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/lcdrw/Makefile b/apps/examples/lcdrw/Makefile index ed612e0be..61d6bcce6 100644 --- a/apps/examples/lcdrw/Makefile +++ b/apps/examples/lcdrw/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_LCDRW_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/modbus/Makefile b/apps/examples/modbus/Makefile index d6caefe81..da31c3b52 100644 --- a/apps/examples/modbus/Makefile +++ b/apps/examples/modbus/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/nettest/Makefile b/apps/examples/nettest/Makefile index 085b9406d..e6f56e765 100644 --- a/apps/examples/nettest/Makefile +++ b/apps/examples/nettest/Makefile @@ -116,13 +116,14 @@ $(HOST_BIN): $(HOST_OBJS) $(call ARCHIVE, $(BIN), $(TARG_OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(TARG_SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(TARG_SRCS) >Make.dep diff --git a/apps/examples/nx/Makefile b/apps/examples/nx/Makefile index ad2bee84e..4474a58c3 100644 --- a/apps/examples/nx/Makefile +++ b/apps/examples/nx/Makefile @@ -86,13 +86,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_NX_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/nxhello/Makefile b/apps/examples/nxhello/Makefile index b1ac6f116..52ced123d 100644 --- a/apps/examples/nxhello/Makefile +++ b/apps/examples/nxhello/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_NXHELLO_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/nximage/Makefile b/apps/examples/nximage/Makefile index e2e9201e7..98f04c2d5 100644 --- a/apps/examples/nximage/Makefile +++ b/apps/examples/nximage/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_NXIMAGE_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/nxlines/Makefile b/apps/examples/nxlines/Makefile index cdda7ad8c..9673a5520 100644 --- a/apps/examples/nxlines/Makefile +++ b/apps/examples/nxlines/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/nxtext/Makefile b/apps/examples/nxtext/Makefile index dffe66ba1..738209754 100644 --- a/apps/examples/nxtext/Makefile +++ b/apps/examples/nxtext/Makefile @@ -87,13 +87,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_NXTEXT_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile index 3e78c64e8..dfb500387 100644 --- a/apps/examples/ostest/Makefile +++ b/apps/examples/ostest/Makefile @@ -127,13 +127,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_OSTEST_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/pwm/Makefile b/apps/examples/pwm/Makefile index 3a6f2520a..d33d1c277 100644 --- a/apps/examples/pwm/Makefile +++ b/apps/examples/pwm/Makefile @@ -83,11 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/qencoder/Makefile b/apps/examples/qencoder/Makefile index 7d2427c6b..1caff2ed3 100644 --- a/apps/examples/qencoder/Makefile +++ b/apps/examples/qencoder/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/relays/Makefile b/apps/examples/relays/Makefile index 8e91ab572..17bf7a6a4 100644 --- a/apps/examples/relays/Makefile +++ b/apps/examples/relays/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/telnetd/Makefile b/apps/examples/telnetd/Makefile index 8f5e5b6d2..63876baa0 100644 --- a/apps/examples/telnetd/Makefile +++ b/apps/examples/telnetd/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/tiff/Makefile b/apps/examples/tiff/Makefile index f62209931..853e904a7 100644 --- a/apps/examples/tiff/Makefile +++ b/apps/examples/tiff/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_TIFF_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/touchscreen/Makefile b/apps/examples/touchscreen/Makefile index b3943951e..8761cc5b5 100644 --- a/apps/examples/touchscreen/Makefile +++ b/apps/examples/touchscreen/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/usbstorage/Makefile b/apps/examples/usbstorage/Makefile index 5492e47dc..a1eb77836 100644 --- a/apps/examples/usbstorage/Makefile +++ b/apps/examples/usbstorage/Makefile @@ -87,14 +87,17 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_USBMSC_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) + +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/usbterm/Makefile b/apps/examples/usbterm/Makefile index c5fb95331..3b3ca6cd7 100644 --- a/apps/examples/usbterm/Makefile +++ b/apps/examples/usbterm/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_EXAMPLES_USBTERM_BUILTIN),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/watchdog/Makefile b/apps/examples/watchdog/Makefile index 9890959fb..cf947b011 100644 --- a/apps/examples/watchdog/Makefile +++ b/apps/examples/watchdog/Makefile @@ -83,11 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/wgetjson/Makefile b/apps/examples/wgetjson/Makefile index fa8f302c6..38bd8ac04 100644 --- a/apps/examples/wgetjson/Makefile +++ b/apps/examples/wgetjson/Makefile @@ -83,13 +83,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/examples/xmlrpc/Makefile b/apps/examples/xmlrpc/Makefile index 7053f54d3..4756bfabb 100644 --- a/apps/examples/xmlrpc/Makefile +++ b/apps/examples/xmlrpc/Makefile @@ -84,13 +84,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -.context: ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - @touch $@ -endif -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep diff --git a/apps/graphics/tiff/Makefile b/apps/graphics/tiff/Makefile index e42091ad9..b5f6c5b73 100644 --- a/apps/graphics/tiff/Makefile +++ b/apps/graphics/tiff/Makefile @@ -90,7 +90,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/interpreters/ficl/Makefile b/apps/interpreters/ficl/Makefile index 990630fb8..3b2dc7ab9 100644 --- a/apps/interpreters/ficl/Makefile +++ b/apps/interpreters/ficl/Makefile @@ -108,7 +108,6 @@ context: depend: .depend clean: - $(call DELFILE, .context) $(call DELFILE, .built) $(call CLEAN) diff --git a/apps/modbus/Makefile b/apps/modbus/Makefile index d2b148162..27548f3d6 100644 --- a/apps/modbus/Makefile +++ b/apps/modbus/Makefile @@ -111,7 +111,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/nshlib/Makefile b/apps/nshlib/Makefile index 73325e899..7ddbb67bf 100644 --- a/apps/nshlib/Makefile +++ b/apps/nshlib/Makefile @@ -130,7 +130,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/free/Makefile b/apps/system/free/Makefile index dada00d99..4f6424f50 100644 --- a/apps/system/free/Makefile +++ b/apps/system/free/Makefile @@ -92,11 +92,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -111,7 +114,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/i2c/Makefile b/apps/system/i2c/Makefile index 029d2b6fe..7f42801a9 100644 --- a/apps/system/i2c/Makefile +++ b/apps/system/i2c/Makefile @@ -68,7 +68,7 @@ STACKSIZE = 2048 # Build targets all: .built -.PHONY: .context context .depend depend clean distclean +.PHONY: context .depend depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -80,11 +80,14 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) $(Q) touch .built -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif .depend: Makefile $(SRCS) $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep @@ -97,7 +100,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/install/Makefile b/apps/system/install/Makefile index 6a02d859f..aa65e60ed 100644 --- a/apps/system/install/Makefile +++ b/apps/system/install/Makefile @@ -93,11 +93,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -112,7 +115,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/poweroff/Makefile b/apps/system/poweroff/Makefile index bbceccb9e..0067a13ab 100644 --- a/apps/system/poweroff/Makefile +++ b/apps/system/poweroff/Makefile @@ -93,11 +93,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -112,7 +115,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/ramtron/Makefile b/apps/system/ramtron/Makefile index 9f5af1659..1c92398f3 100644 --- a/apps/system/ramtron/Makefile +++ b/apps/system/ramtron/Makefile @@ -93,11 +93,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -112,7 +115,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/readline/Makefile b/apps/system/readline/Makefile index 3a48d324e..040fd2e28 100644 --- a/apps/system/readline/Makefile +++ b/apps/system/readline/Makefile @@ -100,7 +100,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/sdcard/Makefile b/apps/system/sdcard/Makefile index 6d5d12960..6c580ba86 100644 --- a/apps/system/sdcard/Makefile +++ b/apps/system/sdcard/Makefile @@ -93,11 +93,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -112,7 +115,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/apps/system/sysinfo/Makefile b/apps/system/sysinfo/Makefile index fa6aebf71..d233aa3d8 100644 --- a/apps/system/sysinfo/Makefile +++ b/apps/system/sysinfo/Makefile @@ -93,11 +93,14 @@ $(COBJS): %$(OBJEXT): %.c # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies @@ -112,7 +115,6 @@ clean: $(call CLEAN) distclean: clean - $(call DELFILE, .context) $(call DELFILE, Make.dep) $(call DELFILE, .depend) diff --git a/nuttx/Documentation/NuttShell.html b/nuttx/Documentation/NuttShell.html index cc3f078dd..7ad96da79 100644 --- a/nuttx/Documentation/NuttShell.html +++ b/nuttx/Documentation/NuttShell.html @@ -3349,11 +3349,7 @@ int hello_main(int argc, char *argv[])

  • - And finally, the apps/examples/Makefilewill execute the context target in all configured examplesub-directores, getting us finally to apps/examples/Makefile (which is covered below).

    -
  • -

    - At the conclusion of the context phase, the apps/Makefile will touch a file called .context in the apps/ directory, preventing any further configurations during any subsequent context phase build attempts. -

    + And finally, the apps/examples/Makefile will execute the context target in all configured examplesub-directores, getting us finally to apps/examples/Makefile which is covered below.

    @@ -3417,9 +3413,8 @@ STACKSIZE = 2048 When the hello command is executed, it will start the task with entry point hello_main() with the default priority and with a stack size of 2K. 

      -.context:
+context:
   $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main)
-  @touch $@
    diff --git a/nuttx/configs/vsn/src/Makefile b/nuttx/configs/vsn/src/Makefile index a71c80c8a..b0eba0a20 100644 --- a/nuttx/configs/vsn/src/Makefile +++ b/nuttx/configs/vsn/src/Makefile @@ -85,11 +85,14 @@ libboard$(LIBEXT): $(OBJS) # Register application -.context: +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) - $(Q) touch $@ -context: .context +context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat +else +context: +endif # Create dependencies -- cgit v1.2.3 From 424d1af00f29a81ec98b9b91bc518b70fb8e2013 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 24 Dec 2012 13:15:57 +0000 Subject: Some fixes to apps/builtin/registry need to handle some additional cases git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5456 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 5 ++++- apps/Make.defs | 6 ++++++ apps/builtin/Makefile | 2 ++ apps/builtin/registry/Makefile | 9 ++++++++- apps/examples/adc/Makefile | 2 +- apps/examples/buttons/Makefile | 2 +- apps/examples/can/Makefile | 2 +- apps/examples/cdcacm/Makefile | 4 ++-- apps/examples/composite/Makefile | 4 ++-- apps/examples/cxxtest/Makefile | 2 +- apps/examples/dhcpd/Makefile | 2 +- apps/examples/discover/Makefile | 2 +- apps/examples/ftpc/Makefile | 2 +- apps/examples/ftpd/Makefile | 4 ++-- apps/examples/hello/Makefile | 2 +- apps/examples/helloxx/Makefile | 2 +- apps/examples/json/Makefile | 2 +- apps/examples/keypadtest/Makefile | 2 +- apps/examples/lcdrw/Makefile | 2 +- apps/examples/modbus/Makefile | 2 +- apps/examples/nettest/Makefile | 2 +- apps/examples/nx/Makefile | 2 +- apps/examples/nxhello/Makefile | 2 +- apps/examples/nximage/Makefile | 2 +- apps/examples/nxlines/Makefile | 2 +- apps/examples/nxtext/Makefile | 2 +- apps/examples/ostest/Makefile | 2 +- apps/examples/pwm/Makefile | 2 +- apps/examples/qencoder/Makefile | 2 +- apps/examples/relays/Makefile | 2 +- apps/examples/telnetd/Makefile | 2 +- apps/examples/tiff/Makefile | 2 +- apps/examples/touchscreen/Makefile | 2 +- apps/examples/usbstorage/Makefile | 4 ++-- apps/examples/usbterm/Makefile | 2 +- apps/examples/watchdog/Makefile | 2 +- apps/examples/wgetjson/Makefile | 2 +- apps/examples/xmlrpc/Makefile | 2 +- apps/system/free/Makefile | 2 +- apps/system/i2c/Makefile | 2 +- apps/system/install/Makefile | 2 +- apps/system/poweroff/Makefile | 2 +- apps/system/ramtron/Makefile | 2 +- apps/system/sdcard/Makefile | 2 +- apps/system/sysinfo/Makefile | 2 +- 45 files changed, 65 insertions(+), 47 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 8999047ef..09a4f634d 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -440,8 +440,11 @@ files. It makes sense for 'leaf' Makefiles to have this dependency, but it does not make sense for upper-level Makefiles. * namedapp/: Renamed to builtins in preparation for another change. - * .context: Removed the .context kludge. This causes lots of problems + * .context: Removed the .context kludge. This caused lots of problems when changing configurations because there is no easy way to get the system to rebuild the context. Now, the context will be rebuilt whenever there is a change in either .config or the Makefile. + * builtin/registry: Updated new built-in registration logic to handle + cases where (1) old apps/.config is used, and (2) applications ared + removed, not just added. diff --git a/apps/Make.defs b/apps/Make.defs index 217137a29..c62999804 100644 --- a/apps/Make.defs +++ b/apps/Make.defs @@ -36,6 +36,12 @@ BUILTIN_REGISTRY = $(APPDIR)$(DELIM)builtin$(DELIM)registry +ifeq ($(CONFIG_NUTTX_NEWCONFIG),y) +DEPCONFIG = $(TOPDIR)/.config +else +DEPCONFIG = $(TOPDIR)/.config $(APPDIR)/.config +endif + define REGISTER $(Q) echo "Register: $1" $(Q) echo "{ \"$1\", $2, $3, $4 }," > "$(BUILTIN_REGISTRY)$(DELIM)$4.bdat" diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index 6633146e9..2d8b0193e 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -96,6 +96,7 @@ endif $(Q) touch .built context: + $(Q) $(MAKE) -C registry context TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" .depend: Makefile $(SRCS) $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep @@ -104,6 +105,7 @@ context: depend: .depend clean: + $(Q) $(MAKE) -C registry clean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" $(call DELFILE, .built) $(call CLEAN) diff --git a/apps/builtin/registry/Makefile b/apps/builtin/registry/Makefile index 9117f53d6..4ecd5da9f 100644 --- a/apps/builtin/registry/Makefile +++ b/apps/builtin/registry/Makefile @@ -41,7 +41,14 @@ include $(APPDIR)/Make.defs all: .PHONY: context depend clean distclean -context: +.updated: $(DEPCONFIG) + $(call DELFILE, *.bdat) + $(call DELFILE, *.pdat) + $(Q) touch .updated + +# This must run before any other context target + +context: .updated depend: diff --git a/apps/examples/adc/Makefile b/apps/examples/adc/Makefile index 55bc259e4..3cbe843f6 100644 --- a/apps/examples/adc/Makefile +++ b/apps/examples/adc/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/buttons/Makefile b/apps/examples/buttons/Makefile index ac1f2f05a..a2e8679d4 100644 --- a/apps/examples/buttons/Makefile +++ b/apps/examples/buttons/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/can/Makefile b/apps/examples/can/Makefile index 5df96e1e7..548c6702c 100644 --- a/apps/examples/can/Makefile +++ b/apps/examples/can/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/cdcacm/Makefile b/apps/examples/cdcacm/Makefile index d9e19e906..2cf3a107f 100644 --- a/apps/examples/cdcacm/Makefile +++ b/apps/examples/cdcacm/Makefile @@ -88,10 +88,10 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat diff --git a/apps/examples/composite/Makefile b/apps/examples/composite/Makefile index b1fe49308..1f05d9c64 100644 --- a/apps/examples/composite/Makefile +++ b/apps/examples/composite/Makefile @@ -88,10 +88,10 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat diff --git a/apps/examples/cxxtest/Makefile b/apps/examples/cxxtest/Makefile index cba9f0a4f..97fdb6ede 100644 --- a/apps/examples/cxxtest/Makefile +++ b/apps/examples/cxxtest/Makefile @@ -101,7 +101,7 @@ $(CXXOBJS): %$(OBJEXT): %.cxx @touch .built ifeq ($(CONFIG_EXAMPLES_HELLOXX_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/dhcpd/Makefile b/apps/examples/dhcpd/Makefile index 0522d4cc4..d718d79e1 100644 --- a/apps/examples/dhcpd/Makefile +++ b/apps/examples/dhcpd/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/discover/Makefile b/apps/examples/discover/Makefile index b0285fbff..033ab1131 100644 --- a/apps/examples/discover/Makefile +++ b/apps/examples/discover/Makefile @@ -85,7 +85,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/ftpc/Makefile b/apps/examples/ftpc/Makefile index e09779abd..cc966f8d6 100644 --- a/apps/examples/ftpc/Makefile +++ b/apps/examples/ftpc/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/ftpd/Makefile b/apps/examples/ftpd/Makefile index dc53bfdea..dd18d5043 100644 --- a/apps/examples/ftpd/Makefile +++ b/apps/examples/ftpd/Makefile @@ -79,10 +79,10 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat: $(DEPCONFIG) Makefile $(call REGISTER,ftpd_start,SCHED_PRIORITY_DEFAULT,2048,ftpd_start) -$(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat: $(DEPCONFIG) Makefile $(call REGISTER,ftpd_stop,SCHED_PRIORITY_DEFAULT,2048,ftpd_stop) context: $(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat $(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat diff --git a/apps/examples/hello/Makefile b/apps/examples/hello/Makefile index c4e6f735a..fc98fa7f4 100644 --- a/apps/examples/hello/Makefile +++ b/apps/examples/hello/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_HELLO_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/helloxx/Makefile b/apps/examples/helloxx/Makefile index df1b360a5..44d880658 100644 --- a/apps/examples/helloxx/Makefile +++ b/apps/examples/helloxx/Makefile @@ -101,7 +101,7 @@ $(CXXOBJS): %$(OBJEXT): %.cxx @touch .built ifeq ($(CONFIG_EXAMPLES_HELLOXX_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/json/Makefile b/apps/examples/json/Makefile index 1e42757b8..f6a38fb1a 100644 --- a/apps/examples/json/Makefile +++ b/apps/examples/json/Makefile @@ -82,7 +82,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/keypadtest/Makefile b/apps/examples/keypadtest/Makefile index 0c40a5c6c..e38e66a82 100644 --- a/apps/examples/keypadtest/Makefile +++ b/apps/examples/keypadtest/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/lcdrw/Makefile b/apps/examples/lcdrw/Makefile index 61d6bcce6..aab04acf5 100644 --- a/apps/examples/lcdrw/Makefile +++ b/apps/examples/lcdrw/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_LCDRW_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/modbus/Makefile b/apps/examples/modbus/Makefile index da31c3b52..b2fba6764 100644 --- a/apps/examples/modbus/Makefile +++ b/apps/examples/modbus/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nettest/Makefile b/apps/examples/nettest/Makefile index e6f56e765..a0308713c 100644 --- a/apps/examples/nettest/Makefile +++ b/apps/examples/nettest/Makefile @@ -117,7 +117,7 @@ $(HOST_BIN): $(HOST_OBJS) @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nx/Makefile b/apps/examples/nx/Makefile index 4474a58c3..13a938821 100644 --- a/apps/examples/nx/Makefile +++ b/apps/examples/nx/Makefile @@ -87,7 +87,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_NX_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nxhello/Makefile b/apps/examples/nxhello/Makefile index 52ced123d..4a72eb8c7 100644 --- a/apps/examples/nxhello/Makefile +++ b/apps/examples/nxhello/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_NXHELLO_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nximage/Makefile b/apps/examples/nximage/Makefile index 98f04c2d5..7bdaa46d2 100644 --- a/apps/examples/nximage/Makefile +++ b/apps/examples/nximage/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_NXIMAGE_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nxlines/Makefile b/apps/examples/nxlines/Makefile index 9673a5520..54495b292 100644 --- a/apps/examples/nxlines/Makefile +++ b/apps/examples/nxlines/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/nxtext/Makefile b/apps/examples/nxtext/Makefile index 738209754..dfb165608 100644 --- a/apps/examples/nxtext/Makefile +++ b/apps/examples/nxtext/Makefile @@ -88,7 +88,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_NXTEXT_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile index dfb500387..3d19f6a78 100644 --- a/apps/examples/ostest/Makefile +++ b/apps/examples/ostest/Makefile @@ -128,7 +128,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_OSTEST_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/pwm/Makefile b/apps/examples/pwm/Makefile index d33d1c277..ece901a99 100644 --- a/apps/examples/pwm/Makefile +++ b/apps/examples/pwm/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/qencoder/Makefile b/apps/examples/qencoder/Makefile index 1caff2ed3..9668796e6 100644 --- a/apps/examples/qencoder/Makefile +++ b/apps/examples/qencoder/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/relays/Makefile b/apps/examples/relays/Makefile index 17bf7a6a4..1ab4c8716 100644 --- a/apps/examples/relays/Makefile +++ b/apps/examples/relays/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/telnetd/Makefile b/apps/examples/telnetd/Makefile index 63876baa0..4391870c0 100644 --- a/apps/examples/telnetd/Makefile +++ b/apps/examples/telnetd/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/tiff/Makefile b/apps/examples/tiff/Makefile index 853e904a7..17b3bb92c 100644 --- a/apps/examples/tiff/Makefile +++ b/apps/examples/tiff/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_TIFF_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/touchscreen/Makefile b/apps/examples/touchscreen/Makefile index 8761cc5b5..1a65c7282 100644 --- a/apps/examples/touchscreen/Makefile +++ b/apps/examples/touchscreen/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_TOUCHSCREEN_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/usbstorage/Makefile b/apps/examples/usbstorage/Makefile index a1eb77836..6c486bf9c 100644 --- a/apps/examples/usbstorage/Makefile +++ b/apps/examples/usbstorage/Makefile @@ -88,10 +88,10 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_USBMSC_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME1),$(PRIORITY1),$(STACKSIZE1),$(APPNAME1)_main) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME2),$(PRIORITY2),$(STACKSIZE2),$(APPNAME2)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME1)_main.bdat $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME2)_main.bdat diff --git a/apps/examples/usbterm/Makefile b/apps/examples/usbterm/Makefile index 3b3ca6cd7..91e80686e 100644 --- a/apps/examples/usbterm/Makefile +++ b/apps/examples/usbterm/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_EXAMPLES_USBTERM_BUILTIN),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/watchdog/Makefile b/apps/examples/watchdog/Makefile index cf947b011..076272fe3 100644 --- a/apps/examples/watchdog/Makefile +++ b/apps/examples/watchdog/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/wgetjson/Makefile b/apps/examples/wgetjson/Makefile index 38bd8ac04..89cb3e11e 100644 --- a/apps/examples/wgetjson/Makefile +++ b/apps/examples/wgetjson/Makefile @@ -84,7 +84,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/examples/xmlrpc/Makefile b/apps/examples/xmlrpc/Makefile index 4756bfabb..b103fd7ed 100644 --- a/apps/examples/xmlrpc/Makefile +++ b/apps/examples/xmlrpc/Makefile @@ -85,7 +85,7 @@ $(COBJS): %$(OBJEXT): %.c @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/free/Makefile b/apps/system/free/Makefile index 4f6424f50..58ca7956c 100644 --- a/apps/system/free/Makefile +++ b/apps/system/free/Makefile @@ -93,7 +93,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/i2c/Makefile b/apps/system/i2c/Makefile index 7f42801a9..1ed7a2fae 100644 --- a/apps/system/i2c/Makefile +++ b/apps/system/i2c/Makefile @@ -81,7 +81,7 @@ $(COBJS): %$(OBJEXT): %.c $(Q) touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/install/Makefile b/apps/system/install/Makefile index aa65e60ed..07d42887a 100644 --- a/apps/system/install/Makefile +++ b/apps/system/install/Makefile @@ -94,7 +94,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/poweroff/Makefile b/apps/system/poweroff/Makefile index 0067a13ab..eb7518fbc 100644 --- a/apps/system/poweroff/Makefile +++ b/apps/system/poweroff/Makefile @@ -94,7 +94,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/ramtron/Makefile b/apps/system/ramtron/Makefile index 1c92398f3..b47781095 100644 --- a/apps/system/ramtron/Makefile +++ b/apps/system/ramtron/Makefile @@ -94,7 +94,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/sdcard/Makefile b/apps/system/sdcard/Makefile index 6c580ba86..d748b2b04 100644 --- a/apps/system/sdcard/Makefile +++ b/apps/system/sdcard/Makefile @@ -94,7 +94,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat diff --git a/apps/system/sysinfo/Makefile b/apps/system/sysinfo/Makefile index d233aa3d8..eb788b01a 100644 --- a/apps/system/sysinfo/Makefile +++ b/apps/system/sysinfo/Makefile @@ -94,7 +94,7 @@ $(COBJS): %$(OBJEXT): %.c # Register application ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(TOPDIR)$(DELIM).config Makefile +$(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) context: $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat -- cgit v1.2.3 From 5859e0d35365a89d1b3001f562f89dd81d001302 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 24 Dec 2012 14:31:02 +0000 Subject: Correct round-to-ticks logic in sigtimedwait() git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5457 42af7a65-404d-4744-a932-0658087f49c3 --- apps/README.txt | 114 +++++++++++++++++++++++++++++++++++++------- nuttx/ChangeLog | 3 ++ nuttx/sched/sig_timedwait.c | 22 +++++++-- 3 files changed, 118 insertions(+), 21 deletions(-) diff --git a/apps/README.txt b/apps/README.txt index 4f043dcfa..328126905 100644 --- a/apps/README.txt +++ b/apps/README.txt @@ -17,15 +17,15 @@ Contents General ------- This folder provides various applications found in sub-directories. These -applications are not inherently a part of NuttX but are provided you help +applications are not inherently a part of NuttX but are provided to help you develop your own applications. The apps/ directory is a "break away" -part of the configuration that you may chose to use or not. +part of the configuration that you may choose to use or not. Directory Location ------------------ The default application directory used by the NuttX build should be named apps/ (or apps-x.y/ where x.y is the NuttX version number). This apps/ -directoy should appear in the directory tree at the same level as the +directory should appear in the directory tree at the same level as the NuttX directory. Like: . @@ -54,7 +54,7 @@ In this case, application entry points with their requirements are gathered together in two files: - builtin/builtin_proto.h Entry points, prototype function - - builtin/builtin_list.h Application specific information and requirements + - builtin/builtin_list.h Application specific information and requirements The build occurs in several phases as different build targets are executed: (1) context, (2) depend, and (3) default (all). Application information is @@ -96,11 +96,11 @@ after the NSH command. Application Configuration File ------------------------------ -A special configuration file is used to configure which applications -are to be included in the build. The source for this file is -configs///appconfig. The existence of the appconfig -file in the board configuration directory is sufficient to enable building -of applications. +The old-style NuttX configuration uses a special configuration file is +used to configure which applications are to be included in the build. +The source for this file is configs///appconfig. +The existence of the appconfig file in the board configuration directory\ +is sufficient to enable building of applications. The appconfig file is copied into the apps/ directory as .config when NuttX is configured. .config is included in the toplevel apps/Makefile. @@ -109,6 +109,38 @@ CONFIGURED_APPS list like: CONFIGURED_APPS += examples/hello system/poweroff +The new NuttX configuration uses kconfig-frontends tools and only the +NuttX .config file. The new configuration is indicated by the existence +of the definition CONFIG_NUTTX_NEWCONFIG=y in the NuttX .config file. +If CONFIG_NUTTX_NEWCONFIG is defined, then the Makefile will: + +- Assume that there is no apps/.config file and will instead +- Include Make.defs files from each of the subdirectories. + +When an application is enabled using the kconfig-frontends tool, then +a new definition is added to the NuttX .config file. For example, if +you want to enable apps/examples/hello then the old apps/.config would +have had: + + CONFIGURED_APPS += examples/hello + +But in the new configuration there will be no apps/.config file and, +instead, the NuttX .config will have: + + CONFIG_EXAMPLES_HELLO=y + +This will select the apps/examples/hello in the following way: + +- The top-level make will include examples/Make.defs +- examples/Make.defs will set CONFIGURED_APPS += examples/hello + like this: + + ifeq ($(CONFIG_EXAMPLES_HELLO),y) + CONFIGURED_APPS += examples/hello + endif + +Thus accomplishing the same thing with no apps/.config file. + Built-In Start-Up main() function ------------------------------ A builtin application can even be used as the main, start-up entry point @@ -130,17 +162,63 @@ An example application skeleton can be found under the examples/hello sub-directory. This example shows how a builtin application can be added to the project. One must define: - 1. create sub-directory as: appname - 2. provide entry point: appname_main() - 3. set the requirements in the file: Makefile, specially the lines: +Old configuration method: + + 1. Create sub-directory as: appname + + 2. In this directory there should be: + + - A Makefile, and + - The application source code. + + 3. The application source code should provide the entry point: + appname_main() + + 4. Set the requirements in the file: Makefile, specially the lines: + + APPNAME = appname + PRIORITY = SCHED_PRIORITY_DEFAULT + STACKSIZE = 768 + ASRCS = asm source file list as a.asm b.asm ... + CSRCS = C source file list as foo1.c foo2.c .. + + Look at some of the other Makefiles for examples. Note the + special registration logic needed for the context: target + + 5. Add the to the application to the CONFIGIURED_APPS in the + apps/.config file: + + CONFIGURED_APPS += appname + +New Configuration Method: + + 1. Create sub-directory as: appname + + 2. In this directory there should be: + + - A Make.defs file that would be included by the apps/Makefile + - A Kconfig file that would be used by the configuration tool (see + misc/tools/kconfig-language.txt). This Kconfig file should be + included by the apps/Kconfig file + - A Makefile, and + - The application source code. + + 3. The application source code should provide the entry point: + appname_main() + + 4. Set the requirements in the file: Makefile, specially the lines: + + APPNAME = appname + PRIORITY = SCHED_PRIORITY_DEFAULT + STACKSIZE = 768 + ASRCS = asm source file list as a.asm b.asm ... + CSRCS = C source file list as foo1.c foo2.c .. - APPNAME = appname - PRIORITY = SCHED_PRIORITY_DEFAULT - STACKSIZE = 768 - ASRCS = asm source file list as a.asm b.asm ... - CSRCS = C source file list as foo1.c foo2.c .. + 4b. The Make.defs file should include a line like: - 4. add application in the apps/.config + ifeq ($(CONFIG_APPNAME),y) + CONFIGURED_APPS += appname + endif Building NuttX with Board-Specific Pieces Outside the Source Tree ----------------------------------------------------------------- diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 56edf9487..6c6fd7843 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3812,4 +3812,7 @@ * include/pthread.h: In sys/prctl.h because it is needed by pthread_[set|get]name_np() * tools/kconfig.bat: Kludge to run kconfig-frontends from a DOS shell. + * sched/sig_timedwait.c: Should always move the time up to the next + largest number of system ticks. The logic was rounding. Noted by + Petteri Aimonen. diff --git a/nuttx/sched/sig_timedwait.c b/nuttx/sched/sig_timedwait.c index 1b8dfd162..d03611610 100644 --- a/nuttx/sched/sig_timedwait.c +++ b/nuttx/sched/sig_timedwait.c @@ -238,10 +238,25 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, if (timeout) { - /* Convert the timespec to milliseconds */ + /* Convert the timespec to system clock ticks, making sure that + * the resultint delay is greater than or equal to the requested + * time in nanoseconds. + */ - waitticks = MSEC2TICK(timeout->tv_sec * MSEC_PER_SEC - + timeout->tv_nsec / NSEC_PER_MSEC); +#ifdef CONFIG_HAVE_LONG_LONG + uint64_t waitticks64 = (timeout->tv_sec * NSEC_PER_SEC + + timeout->tv_nsec + NSEC_PER_TICK - 1) / + NSEC_PER_TICK; + DEBUGASSERT(waitticks64 <= UINT32_MAX); + waitticks = (uint32_t)waitticks64; +#else + uint32_t waitmsec; + + DEBUGASSERT(timeout->tv_sec < UINT32_MAX / MSEC_PER_SEC); + waitmsec = timeout->tv_sec * MSEC_PER_SEC + + (timeout->tv_nsec + NSEC_PER_MSEC - 1) / NSEC_PER_MSEC; + waitticks = (waitmsec + MSEC_PER_TICK - 1) / MSEC_PER_TICK; +#endif /* Create a watchdog */ @@ -326,6 +341,7 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, { memcpy(info, &rtcb->sigunbinfo, sizeof(struct siginfo)); } + irqrestore(saved_state); } -- cgit v1.2.3 From 7c73fe57c659ce9f9a31a247b04f7068a0b62cb1 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 24 Dec 2012 17:49:58 +0000 Subject: Fixes for l3s, USB composite, nfsmount, apps context build problems git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5458 42af7a65-404d-4744-a932-0658087f49c3 --- apps/builtin/Makefile | 16 ++++++++++++++-- apps/nshlib/nsh_mntcmds.c | 3 +++ apps/nshlib/nsh_netcmds.c | 1 + nuttx/configs/ekk-lm3s9b96/nsh/setenv.sh | 12 ++++++++---- nuttx/configs/ekk-lm3s9b96/ostest/setenv.sh | 12 ++++++++---- nuttx/configs/lm3s8962-ek/nsh/appconfig | 2 +- nuttx/configs/lm3s8962-ek/nsh/setenv.sh | 26 +++++++++++++++++++++----- nuttx/configs/lm3s8962-ek/nx/setenv.sh | 26 +++++++++++++++++++++----- nuttx/configs/lm3s8962-ek/ostest/setenv.sh | 26 +++++++++++++++++++++----- nuttx/configs/stm3210e-eval/RIDE/defconfig | 2 +- nuttx/drivers/usbdev/composite.c | 4 ++-- nuttx/include/nuttx/clock.h | 2 +- nuttx/sched/sig_timedwait.c | 5 +++-- 13 files changed, 105 insertions(+), 32 deletions(-) diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index 2d8b0193e..0efb832f8 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -77,18 +77,30 @@ $(COBJS): %$(OBJEXT): %.c builtin_list.h: registry/.updated $(call DELFILE, builtin_list.h) + $(Q) touch builtin_list.h ifeq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) for /f %%G in ('dir /b registry\*.bdat`) do ( type registry\%%G >> builtin_list.h ) else - $(Q) for file in `ls registry/*.bdat`; do cat $$file >> builtin_list.h; done + $(Q) ( \ + filelist=`ls registry/*.bdat 2>/dev/null || echo ""`; \ + for file in $$filelist; \ + do cat $$file >> builtin_list.h; \ + done; \ + ) endif builtin_proto.h: registry/.updated $(call DELFILE, builtin_proto.h) + $(Q) touch builtin_proto.h ifeq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) for /f %%G in ('dir /b registry\*.pdat`) do ( type registry\%%G >> builtin_proto.h ) else - $(Q) for file in `ls registry/*.pdat`; do cat $$file >> builtin_proto.h; done + $(Q) ( \ + filelist=`ls registry/*.pdat 2>/dev/null || echo ""`; \ + for file in $$filelist; \ + do cat $$file >> builtin_proto.h; \ + done; \ + ) endif .built: builtin_list.h builtin_proto.h $(OBJS) diff --git a/apps/nshlib/nsh_mntcmds.c b/apps/nshlib/nsh_mntcmds.c index 690d027ca..f6eb26c31 100644 --- a/apps/nshlib/nsh_mntcmds.c +++ b/apps/nshlib/nsh_mntcmds.c @@ -45,10 +45,13 @@ #include #include +#include #include #include #include +#include + #include "nsh.h" #include "nsh_console.h" diff --git a/apps/nshlib/nsh_netcmds.c b/apps/nshlib/nsh_netcmds.c index 371d30460..506950e14 100644 --- a/apps/nshlib/nsh_netcmds.c +++ b/apps/nshlib/nsh_netcmds.c @@ -67,6 +67,7 @@ #if defined(CONFIG_NET_ICMP) && defined(CONFIG_NET_ICMP_PING) && \ !defined(CONFIG_DISABLE_CLOCK) && !defined(CONFIG_DISABLE_SIGNALS) # include +# include #endif #if defined(CONFIG_NET_UDP) && CONFIG_NFILE_DESCRIPTORS > 0 diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/setenv.sh b/nuttx/configs/ekk-lm3s9b96/nsh/setenv.sh index 6e591e0dd..bba7595de 100755 --- a/nuttx/configs/ekk-lm3s9b96/nsh/setenv.sh +++ b/nuttx/configs/ekk-lm3s9b96/nsh/setenv.sh @@ -48,12 +48,16 @@ if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}" fi -# TOOLCHAIN_BIN must be defined to the full path to the location where you -# have installed the toolchain of your choice. Modify the following: +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +# This is the Cygwin path to the location where I build the buildroot +# toolchain. export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -# Andd add the toolchain path to the PATH variable - +# Add the path to the toolchain to the PATH varialble export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + echo "PATH : ${PATH}" diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/setenv.sh b/nuttx/configs/ekk-lm3s9b96/ostest/setenv.sh index d98c6cc40..60dfa3c71 100755 --- a/nuttx/configs/ekk-lm3s9b96/ostest/setenv.sh +++ b/nuttx/configs/ekk-lm3s9b96/ostest/setenv.sh @@ -48,12 +48,16 @@ if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}" fi -# TOOLCHAIN_BIN must be defined to the full path to the location where you -# have installed the toolchain of your choice. Modify the following: +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +# This is the Cygwin path to the location where I build the buildroot +# toolchain. export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -# Andd add the toolchain path to the PATH variable - +# Add the path to the toolchain to the PATH varialble export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + echo "PATH : ${PATH}" diff --git a/nuttx/configs/lm3s8962-ek/nsh/appconfig b/nuttx/configs/lm3s8962-ek/nsh/appconfig index 5eeb56607..2e2421b67 100644 --- a/nuttx/configs/lm3s8962-ek/nsh/appconfig +++ b/nuttx/configs/lm3s8962-ek/nsh/appconfig @@ -40,7 +40,7 @@ CONFIGURED_APPS += examples/nsh # NSH library CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlibO +CONFIGURED_APPS += nshlib # Networking support diff --git a/nuttx/configs/lm3s8962-ek/nsh/setenv.sh b/nuttx/configs/lm3s8962-ek/nsh/setenv.sh index 511552d94..1db7f8ee2 100755 --- a/nuttx/configs/lm3s8962-ek/nsh/setenv.sh +++ b/nuttx/configs/lm3s8962-ek/nsh/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - WD=`pwd` -export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/lm3s8962-ek/nx/setenv.sh b/nuttx/configs/lm3s8962-ek/nx/setenv.sh index a36725083..c716ddf5e 100755 --- a/nuttx/configs/lm3s8962-ek/nx/setenv.sh +++ b/nuttx/configs/lm3s8962-ek/nx/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - WD=`pwd` -export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/lm3s8962-ek/ostest/setenv.sh b/nuttx/configs/lm3s8962-ek/ostest/setenv.sh index 6bd49b6fa..91bf1095b 100755 --- a/nuttx/configs/lm3s8962-ek/ostest/setenv.sh +++ b/nuttx/configs/lm3s8962-ek/ostest/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - WD=`pwd` -export BUILDROOT_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/stm3210e-eval/RIDE/defconfig b/nuttx/configs/stm3210e-eval/RIDE/defconfig index 64665f47e..e71540c24 100755 --- a/nuttx/configs/stm3210e-eval/RIDE/defconfig +++ b/nuttx/configs/stm3210e-eval/RIDE/defconfig @@ -169,7 +169,7 @@ CONFIG_RAW_BINARY=n # # General OS setup # -#CONFIG_USER_ENTRYPOINT= +CONFIG_USER_ENTRYPOINT="null_main" CONFIG_DEBUG=n CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=n diff --git a/nuttx/drivers/usbdev/composite.c b/nuttx/drivers/usbdev/composite.c index 4cad8af86..530d64416 100644 --- a/nuttx/drivers/usbdev/composite.c +++ b/nuttx/drivers/usbdev/composite.c @@ -523,12 +523,12 @@ static int composite_setup(FAR struct usbdevclass_driver_s *driver, { /* Save the configuration and inform the constituent classes */ - ret = CLASS_SETUP(priv->dev1, dev, ctrl); + ret = CLASS_SETUP(priv->dev1, dev, ctrl, dataout, outlen); dispatched = true; if (ret >= 0) { - ret = CLASS_SETUP(priv->dev2, dev, ctrl); + ret = CLASS_SETUP(priv->dev2, dev, ctrl, dataout, outlen); if (ret >= 0) { priv->config = value; diff --git a/nuttx/include/nuttx/clock.h b/nuttx/include/nuttx/clock.h index 952e0e5ef..e640ecd2e 100644 --- a/nuttx/include/nuttx/clock.h +++ b/nuttx/include/nuttx/clock.h @@ -113,7 +113,7 @@ #define USEC2TICK(usec) (((usec)+(USEC_PER_TICK/2))/USEC_PER_TICK) /* Rounds */ #define MSEC2TICK(msec) (((msec)+(MSEC_PER_TICK/2))/MSEC_PER_TICK) /* Rounds */ #define DSEC2TICK(dsec) MSEC2TICK((dsec)*MSEC_PER_DSEC) -#define SEC2TICK(sec) MSEC2TICK((sec)*MSEC_PER_SEC) +#define SEC2TICK(sec) MSEC2TICK((sec)*MSEC_PER_SEC) /* Exact */ #define TICK2NSEC(tick) ((tick)*NSEC_PER_TICK) /* Exact */ #define TICK2USEC(tick) ((tick)*USEC_PER_TICK) /* Exact */ diff --git a/nuttx/sched/sig_timedwait.c b/nuttx/sched/sig_timedwait.c index d03611610..d7610cd49 100644 --- a/nuttx/sched/sig_timedwait.c +++ b/nuttx/sched/sig_timedwait.c @@ -38,6 +38,7 @@ ****************************************************************************/ #include +#include #include #include @@ -244,8 +245,8 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, */ #ifdef CONFIG_HAVE_LONG_LONG - uint64_t waitticks64 = (timeout->tv_sec * NSEC_PER_SEC + - timeout->tv_nsec + NSEC_PER_TICK - 1) / + uint64_t waitticks64 = ((uint64_t)timeout->tv_sec * NSEC_PER_SEC + + (uint64_t)timeout->tv_nsec + NSEC_PER_TICK - 1) / NSEC_PER_TICK; DEBUGASSERT(waitticks64 <= UINT32_MAX); waitticks = (uint32_t)waitticks64; -- cgit v1.2.3 From 6953365d30f06846a8f3877b73e01ee7d8321db0 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 24 Dec 2012 20:22:14 +0000 Subject: Fix several build issues noted by Mike Smith git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5459 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 10 ++++- apps/builtin/Makefile | 5 ++- apps/examples/nettest/Makefile | 57 +++++++++++++++-------------- nuttx/ChangeLog | 3 ++ nuttx/arch/arm/src/arm/up_head.S | 51 +++++++++++++++++++------- nuttx/configs/ntosd-dm320/nettest/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/nsh/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/ostest/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/poll/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/thttpd/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/udp/setenv.sh | 26 ++++++++++--- nuttx/configs/ntosd-dm320/uip/setenv.sh | 26 ++++++++++--- 12 files changed, 228 insertions(+), 80 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 09a4f634d..ea1b247f5 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -439,12 +439,18 @@ * Makefiles: Removed dependency of distclean on clean in most top-level files. It makes sense for 'leaf' Makefiles to have this dependency, but it does not make sense for upper-level Makefiles. - * namedapp/: Renamed to builtins in preparation for another change. + * apps/namedapp/: Renamed to builtins in preparation for another change. * .context: Removed the .context kludge. This caused lots of problems when changing configurations because there is no easy way to get the system to rebuild the context. Now, the context will be rebuilt whenever there is a change in either .config or the Makefile. - * builtin/registry: Updated new built-in registration logic to handle + * apps/builtin/registry: Updated new built-in registration logic to handle cases where (1) old apps/.config is used, and (2) applications ared removed, not just added. + * apps/examples/nettest/Makefile: Fix an error that crept in during + some of the recent, massive build system changes. + * apps/builtin/Makefile: Need to have auto-generated header files + in place early in the dependency generation phase to avoid warnings. + It is not important if they are only stubbed out header files at + this build phase. diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index 0efb832f8..ccb860c88 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -75,6 +75,9 @@ $(AOBJS): %$(OBJEXT): %.S $(COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) +registry/.updated: + $(V) $(MAKE) -C registry .updated TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" + builtin_list.h: registry/.updated $(call DELFILE, builtin_list.h) $(Q) touch builtin_list.h @@ -110,7 +113,7 @@ endif context: $(Q) $(MAKE) -C registry context TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" -.depend: Makefile $(SRCS) +.depend: Makefile $(SRCS) builtin_list.h builtin_proto.h $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep $(Q) touch $@ diff --git a/apps/examples/nettest/Makefile b/apps/examples/nettest/Makefile index a0308713c..5368bdefc 100644 --- a/apps/examples/nettest/Makefile +++ b/apps/examples/nettest/Makefile @@ -39,64 +39,64 @@ include $(APPDIR)/Make.defs # Basic TCP networking test -TARG_ASRCS = -TARG_AOBJS = $(TARG_ASRCS:.S=$(OBJEXT)) +TARG_ASRCS = +TARG_AOBJS = $(TARG_ASRCS:.S=$(OBJEXT)) -TARG_CSRCS = nettest.c +TARG_CSRCS = nettest.c ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y) -TARG_CSRCS += nettest_server.c +TARG_CSRCS += nettest_server.c else -TARG_CSRCS += nettest_client.c +TARG_CSRCS += nettest_client.c endif -TARG_COBJS = $(TARG_CSRCS:.c=$(OBJEXT)) +TARG_COBJS = $(TARG_CSRCS:.c=$(OBJEXT)) -TARG_SRCS = $(TARG_ASRCS) $(TARG_CSRCS) -TARG_OBJS = $(TARG_AOBJS) $(TARG_COBJS) +TARG_SRCS = $(TARG_ASRCS) $(TARG_CSRCS) +TARG_OBJS = $(TARG_AOBJS) $(TARG_COBJS) ifeq ($(CONFIG_WINDOWS_NATIVE),y) - TARG_BIN = ..\..\libapps$(LIBEXT) + TARG_BIN = ..\..\libapps$(LIBEXT) else ifeq ($(WINTOOL),y) - TARG_BIN = ..\\..\\libapps$(LIBEXT) + TARG_BIN = ..\\..\\libapps$(LIBEXT) else - TARG_BIN = ../../libapps$(LIBEXT) + TARG_BIN = ../../libapps$(LIBEXT) endif endif -HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_HOST=1 +HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_HOST=1 ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y) -HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_SERVER=1 \ - -DCONFIG_EXAMPLES_NETTEST_CLIENTIP="$(CONFIG_EXAMPLES_NETTEST_CLIENTIP)" +HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_SERVER=1 -DCONFIG_EXAMPLES_NETTEST_CLIENTIP="$(CONFIG_EXAMPLES_NETTEST_CLIENTIP)" endif ifeq ($(CONFIG_EXAMPLES_NETTEST_PERFORMANCE),y) -HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_PERFORMANCE=1 +HOSTCFLAGS += -DCONFIG_EXAMPLES_NETTEST_PERFORMANCE=1 endif -HOST_SRCS = host.c +HOST_SRCS = host.c ifeq ($(CONFIG_EXAMPLES_NETTEST_SERVER),y) -HOST_SRCS += nettest_client.c +HOST_SRCS += nettest_client.c else -HOST_SRCS += nettest_server.c +HOST_SRCS += nettest_server.c endif -HOST_OBJS = $(HOST_SRCS:.c=.o) -HOST_BIN = host +HOSTOBJEXT ?= .hobj +HOST_OBJS = $(HOST_SRCS:.c=$(HOSTOBJEXT)) +HOST_BIN = host -ROOTDEPPATH = --dep-path . +ROOTDEPPATH = --dep-path . # NET test built-in application info -APPNAME = nettest -PRIORITY = SCHED_PRIORITY_DEFAULT -STACKSIZE = 2048 +APPNAME = nettest +PRIORITY = SCHED_PRIORITY_DEFAULT +STACKSIZE = 2048 # Common build -VPATH = +VPATH = all: .built $(HOST_BIN) -.PHONY: clean depend distclean +.PHONY: clean depend distclean $(TARG_AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -104,7 +104,7 @@ $(TARG_AOBJS): %$(OBJEXT): %.S $(TARG_COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) -$(HOST_OBJS): %.o: %.c +$(HOST_OBJS): %$(HOSTOBJEXT): %.c @echo "CC: $<" @$(HOSTCC) -c $(HOSTCFLAGS) $< -o $@ @@ -113,7 +113,7 @@ $(HOST_BIN): $(HOST_OBJS) @$(HOSTCC) $(HOSTLDFLAGS) $(HOST_OBJS) -o $@ .built: $(TARG_OBJS) - $(call ARCHIVE, $(BIN), $(TARG_OBJS)) + $(call ARCHIVE, $(TARG_BIN), $(TARG_OBJS)) @touch .built ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) @@ -132,6 +132,7 @@ endif depend: .depend clean: + $(call DELFILE, *$(HOSTOBJEXT)) $(call DELFILE, $(HOST_BIN)) $(call DELFILE, .built) $(call CLEAN) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 6c6fd7843..c5cc9b54a 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3815,4 +3815,7 @@ * sched/sig_timedwait.c: Should always move the time up to the next largest number of system ticks. The logic was rounding. Noted by Petteri Aimonen. + * arch/arm/src/up_head.S: Fix backward conditional compilation. NOTE + there is a issue of ARM9 systems with low vectors and large memories + that will have to be addressed in the future. diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S index 91d67fd15..46efd8772 100644 --- a/nuttx/arch/arm/src/arm/up_head.S +++ b/nuttx/arch/arm/src/arm/up_head.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/arm/up_head.S + * arch/arm/src/arm/up_pghead.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -78,6 +78,10 @@ * beginning of FLASH. */ +# if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART) +# error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined" +# endif + # if CONFIG_FLASH_START == CONFIG_FLASH_VSTART # define CONFIG_IDENTITY_TEXTMAP 1 # endif @@ -102,6 +106,10 @@ * beginning of FLASH. */ +# if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART) +# error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined" +# endif + # if CONFIG_FLASH_START == CONFIG_FLASH_VSTART # define CONFIG_IDENTITY_TEXTMAP 1 # endif @@ -120,6 +128,10 @@ * beginning of RAM. */ +# if !defined(CONFIG_DRAM_START) || !defined(CONFIG_DRAM_VSTART) +# error "CONFIG_DRAM_START or CONFIG_DRAM_VSTART is not defined" +# endif + # if CONFIG_DRAM_START == CONFIG_DRAM_VSTART # define CONFIG_IDENTITY_TEXTMAP 1 # endif @@ -162,26 +174,37 @@ * Assembly Macros ****************************************************************************/ -/* The ARM9 L1 page table can be placed at the beginning or at the end of the - * RAM space. This decision is based on the placement of the vector area: - * If the vectors are place in low memory at address 0x0000 0000, then the - * page table is placed in high memory; if the vectors are placed in high - * memory at address 0xfff0 0000, then the page table is locating at the - * beginning of RAM. +/* The ARM9 L1 page table can be placed at the beginning or at the end of + * the RAM space. This decision is based on the placement of the vector + * area: If the vectors are place in low memory at address 0x0000 0000, then + * the page table is placed in high memory; if the vectors are placed in + * high memory at address 0xfff0 0000, then the page table is locating at + * the beginning of RAM. * - * For the special case where (1) the program executes out of RAM, and (2) the - * page is located at the beginning of RAM, then the following macro can - * easily find the physical address of the section that includes the first - * part of the text region: Since the page table is closely related to the - * NuttX base address in this case, we can convert the page table base address - * to the base address of the section containing both. + * For the special case where (1) the program executes out of RAM, and (2) + * the page is located at the beginning of RAM (i.e., the high vector case), + * then the following macro can easily find the physical address of the + * section that includes the first part of the text region: Since the page + * table is closely related to the NuttX base address in this case, we can + * convert the page table base address to the base address of the section + * containing both. + */ + +/* REVISIT: This works now of the low vector case only because the RAM + * sizes that we have been dealing with are less then 1MB so that both the + * page table and the vector table are in the same 1MB RAM block. But + * this will certainly break later. Hence, the annoying warning. */ #ifdef CONFIG_ARCH_LOWVECTORS +# warning "REVISIT" +#endif + +//#ifndef CONFIG_ARCH_LOWVECTORS .macro mksection, section, pgtable bic \section, \pgtable, #0x000ff000 .endm -#endif +//#endif /* This macro will modify r0, r1, r2 and r14 */ diff --git a/nuttx/configs/ntosd-dm320/nettest/setenv.sh b/nuttx/configs/ntosd-dm320/nettest/setenv.sh index 6090d4cea..cfb438ce7 100755 --- a/nuttx/configs/ntosd-dm320/nettest/setenv.sh +++ b/nuttx/configs/ntosd-dm320/nettest/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/nsh/setenv.sh b/nuttx/configs/ntosd-dm320/nsh/setenv.sh index a84e68884..005aa8153 100755 --- a/nuttx/configs/ntosd-dm320/nsh/setenv.sh +++ b/nuttx/configs/ntosd-dm320/nsh/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/ostest/setenv.sh b/nuttx/configs/ntosd-dm320/ostest/setenv.sh index a65be2677..75d6f0cd0 100755 --- a/nuttx/configs/ntosd-dm320/ostest/setenv.sh +++ b/nuttx/configs/ntosd-dm320/ostest/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/poll/setenv.sh b/nuttx/configs/ntosd-dm320/poll/setenv.sh index de3b64ea9..427ffe26a 100755 --- a/nuttx/configs/ntosd-dm320/poll/setenv.sh +++ b/nuttx/configs/ntosd-dm320/poll/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/thttpd/setenv.sh b/nuttx/configs/ntosd-dm320/thttpd/setenv.sh index 92ff91700..ea38c09a5 100755 --- a/nuttx/configs/ntosd-dm320/thttpd/setenv.sh +++ b/nuttx/configs/ntosd-dm320/thttpd/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/udp/setenv.sh b/nuttx/configs/ntosd-dm320/udp/setenv.sh index 052413b08..92995bee5 100755 --- a/nuttx/configs/ntosd-dm320/udp/setenv.sh +++ b/nuttx/configs/ntosd-dm320/udp/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" diff --git a/nuttx/configs/ntosd-dm320/uip/setenv.sh b/nuttx/configs/ntosd-dm320/uip/setenv.sh index 988e0a126..33c252e1e 100755 --- a/nuttx/configs/ntosd-dm320/uip/setenv.sh +++ b/nuttx/configs/ntosd-dm320/uip/setenv.sh @@ -32,15 +32,31 @@ # POSSIBILITY OF SUCH DAMAGE. # -if [ "$(basename $0)" = "setenv.sh" ] ; then +if [ "$_" = "$0" ] ; then echo "You must source this script, not run it!" 1>&2 exit 1 fi -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - WD=`pwd` -export BUILDROOT_BIN=${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" -- cgit v1.2.3 From 292d4db37a4080585577c43434157db335cd5158 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 25 Dec 2012 17:22:58 +0000 Subject: Add logic to serialize and marshal out-of-band keyboard commands git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5460 42af7a65-404d-4744-a932-0658087f49c3 --- apps/Make.defs | 4 +- apps/builtin/Makefile | 6 +- nuttx/ChangeLog | 4 +- nuttx/include/nuttx/input/kbd_codec.h | 292 ++++++++++++++++++++++++++++++++++ nuttx/include/nuttx/usb/hid.h | 2 +- nuttx/libc/misc/Make.defs | 2 +- nuttx/libc/misc/lib_kbddecode.c | 258 ++++++++++++++++++++++++++++++ nuttx/libc/misc/lib_kbdencode.c | 81 ++++++++++ 8 files changed, 641 insertions(+), 8 deletions(-) create mode 100644 nuttx/include/nuttx/input/kbd_codec.h create mode 100644 nuttx/libc/misc/lib_kbddecode.c create mode 100644 nuttx/libc/misc/lib_kbdencode.c diff --git a/apps/Make.defs b/apps/Make.defs index c62999804..f7e6aa08d 100644 --- a/apps/Make.defs +++ b/apps/Make.defs @@ -37,9 +37,9 @@ BUILTIN_REGISTRY = $(APPDIR)$(DELIM)builtin$(DELIM)registry ifeq ($(CONFIG_NUTTX_NEWCONFIG),y) -DEPCONFIG = $(TOPDIR)/.config +DEPCONFIG = $(TOPDIR)$(DELIM).config else -DEPCONFIG = $(TOPDIR)/.config $(APPDIR)/.config +DEPCONFIG = $(TOPDIR)$(DELIM).config $(APPDIR)$(DELIM).config endif define REGISTER diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index ccb860c88..8c8928886 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -75,10 +75,10 @@ $(AOBJS): %$(OBJEXT): %.S $(COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) -registry/.updated: +registry$(DELIM).updated: $(V) $(MAKE) -C registry .updated TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" -builtin_list.h: registry/.updated +builtin_list.h: registry$(DELIM).updated $(call DELFILE, builtin_list.h) $(Q) touch builtin_list.h ifeq ($(CONFIG_WINDOWS_NATIVE),y) @@ -92,7 +92,7 @@ else ) endif -builtin_proto.h: registry/.updated +builtin_proto.h: registry$(DELIM).updated $(call DELFILE, builtin_proto.h) $(Q) touch builtin_proto.h ifeq ($(CONFIG_WINDOWS_NATIVE),y) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c5cc9b54a..80ddb56c6 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3818,4 +3818,6 @@ * arch/arm/src/up_head.S: Fix backward conditional compilation. NOTE there is a issue of ARM9 systems with low vectors and large memories that will have to be addressed in the future. - + * libc/misc/lib_kbdencode.c and lib_kbddecode.c: Add logic to marshal + and serialized "out-of-band" keyboard commands intermixed with normal + ASCII data (not yet hooked into anything). diff --git a/nuttx/include/nuttx/input/kbd_codec.h b/nuttx/include/nuttx/input/kbd_codec.h new file mode 100644 index 000000000..b103d544e --- /dev/null +++ b/nuttx/include/nuttx/input/kbd_codec.h @@ -0,0 +1,292 @@ +/************************************************************************************ + * include/nuttx/input/kbd_codec.h + * Serialize and marshaling out-of-band keyboard data + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __INCLUDE_NUTTX_INPUT_KBD_CODEC_H +#define __INCLUDE_NUTTX_INPUT_KBD_CODEC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* These are the special, "out-of-band" keyboard commands recognized by the + * CODEC. + */ + +enum kbd_keycode_e +{ + KEYCODE_NORMAL = 0, /* Not a special keycode */ + + /* Delete and Backspace keycodes (in case they may be different than the + * ASCII BKSP and DEL values. + */ + + KEYCODE_FWDDEL, /* DELete (forward delete) */ + KEYCODE_BACKDEL, /* Backspace (backward delete) */ + + /* Cursor movement */ + + KEYCODE_HOME, /* Home */ + KEYCODE_END, /* End */ + KEYCODE_LEFT, /* Left arrow */ + KEYCODE_RIGHT, /* Right arrow */ + KEYCODE_UP, /* Up arrow */ + KEYCODE_DOWN, /* Down arrow */ + KEYCODE_PAGEUP, /* Page up */ + KEYCODE_PAGEDOWN, /* Page down */ + + /* Edit commands */ + + KEYCODE_INSERT, /* Insert */ + KEYCODE_AGAIN, /* Again */ + KEYCODE_UNDO, /* Undo */ + KEYCODE_REDO, /* Redo */ + KEYCODE_CUT, /* Cut */ + KEYCODE_COPY, /* Copy */ + KEYCODE_PASTE, /* Paste */ + KEYCODE_FIND , /* Find */ + + /* Selection codes */ + + KEYCODE_ENTER, /* Enter */ + KEYCODE_SELECT, /* Select */ + KEYCODE_EXECUTE, /* Execute */ + + /* Keyboard modes */ + + KEYCODE_CAPSLOCK, /* Caps Lock */ + KEYCODE_SCROLLLOCK, /* Scroll Lock */ + KEYCODE_NUMLOCK, /* Keypad Num Lock and Clear */ + KEYCODE_LCAPSLOCK, /* Locking Caps Lock */ + KEYCODE_LNUMLOCK, /* Locking Num Lock */ + KEYCODE_LSCROLLLOCK, /* Locking Scroll Lock */ + + /* Misc control codes */ + + KEYCODE_POWER, /* Power */ + KEYCODE_HELP, /* Help */ + KEYCODE_MENU, /* Menu */ + KEYCODE_STOP, /* Stop */ + KEYCODE_PAUSE, /* Pause */ + KEYCODE_BREAK, /* Break */ + KEYCODE_CANCEL, /* Cancel */ + KEYCODE_PRINTSCN, /* PrintScreen */ + KEYCODE_SYSREQ, /* SysReq/Attention */ + + /* Audio */ + + KEYCODE_MUTE, /* Mute */ + KEYCODE_VOLUP, /* Volume Up */ + KEYCODE_VOLDOWN, /* Volume Down */ + + /* Telephone */ + + KEYCODE_ANSWER, /* Answer (phone) */ + KEYCODE_HANGUP, /* Hang-up (phone) */ + + /* Calculator */ + + KEYCODE_CLEAR, /* Clear */ + KEYCODE_CLEARENTRY, /* Clear entry */ + + KEYCODE_MEMSET, /* Memory set */ + KEYCODE_MEMCLEAR, /* Memory clear */ + KEYCODE_MEMRECALL, /* Memory recall */ + KEYCODE_MEMADD, /* Memory add */ + KEYCODE_MEMSUBTRACT, /* Memory substract */ + KEYCODE_MEMMULTIPY, /* Memory multiply */ + KEYCODE_MEMDIVIDE, /* Memory divide */ + + KEYCODE_BINARY, /* Binary mode */ + KEYCODE_OCTAL, /* Octal mode */ + KEYCODE_DECIMAL, /* Decimal mode */ + KEYCODE_HEXADECIMAL, /* Hexadecimal mode */ + + /* Languages */ + + KEYCODE_LANG1, /* LANG1 */ + KEYCODE_LANG2, /* LANG2 */ + KEYCODE_LANG3, /* LANG3 */ + KEYCODE_LANG4, /* LANG4 */ + KEYCODE_LANG5, /* LANG5 */ + KEYCODE_LANG6, /* LANG6 */ + KEYCODE_LANG7, /* LANG7 */ + KEYCODE_LANG8, /* LANG8 */ + + /* Context-specific function keys */ + + KEYCODE_F1, /* Function key 1 */ + KEYCODE_F2, /* Function key 2 */ + KEYCODE_F3, /* Function key 3 */ + KEYCODE_F4, /* Function key 4 */ + KEYCODE_F5, /* Function key 5 */ + KEYCODE_F6, /* Function key 6 */ + KEYCODE_F7, /* Function key 7 */ + KEYCODE_F8, /* Function key 8 */ + KEYCODE_F9, /* Function key 9 */ + KEYCODE_F10, /* Function key 10 */ + KEYCODE_F11, /* Function key 11 */ + KEYCODE_F12, /* Function key 12 */ + KEYCODE_F13, /* Function key 13 */ + KEYCODE_F14, /* Function key 14 */ + KEYCODE_F15, /* Function key 15 */ + KEYCODE_F16, /* Function key 16 */ + KEYCODE_F17, /* Function key 17 */ + KEYCODE_F18, /* Function key 18 */ + KEYCODE_F19, /* Function key 19 */ + KEYCODE_F20, /* Function key 20 */ + KEYCODE_F21, /* Function key 21 */ + KEYCODE_F22, /* Function key 22 */ + KEYCODE_F23, /* Function key 23 */ + KEYCODE_F24 /* Function key 24 */ +}; + +#define FIRST_KEYCODE KEYCODE_FWDDEL +#define LAST_KEYCODE KEYCODE_F24 + +/* kbd_get return values */ + +#define KBD_NORMAL 0 +#define KBD_SPECIAL 1 +#define KBD_ERROR EOF + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct kget_getstate_s +{ + uint8_t nch; /* Number of characters in the buffer */ + uint8_t ndx; /* Index to next character in the buffer */ + uint8_t buf[4]; /* Buffer of ungotten data */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * The following functions are intended for use by "producer", keyboard + * or keypad drivers to encode information into driver buffers. + ****************************************************************************/ + +/**************************************************************************** + * Name: kbd_puttext + * + * Description: + * Put one byte of normal, "in-band" ASCII data into the output stream. + * + * Input Parameters: + * ch - The character to be into the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#define kbd_puttext(ch, stream) (stream)->put((stream), (int)(ch)) + +/**************************************************************************** + * Name: kbd_putspecial + * + * Description: + * Put one special, "out-of-band" command into the output stream. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_putspecial(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream); + +/**************************************************************************** + * The following functions are intended for use by "consumer" applications + * to remove and decode information from the driver provided buffer. + ****************************************************************************/ + +/**************************************************************************** + * Name: kbd_get + * + * Description: + * Put one byte of data or special command from the driver provided input + * buffer. + * + * Input Parameters: + * stream - An instance of lib_instream_s to do the low-level get + * operation. + * pch - The location character to save the returned value. This may be + * either a normal, "in-band" ASCII characer or a special, "out-of-band" + * command. + * state - A user provided buffer to support parsing. This structure + * should be cleared the first time that kbd_get is called. + * + * Returned Value: + * 1 - Indicates the successful receipt of a special, "out-of-band" command + * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. + * EOF - An error has getting the next character (reported by the stream). + * Normally indicates the end of file. + * + ****************************************************************************/ + +int kbd_get(FAR struct lib_instream_s *stream, + FAR struct kget_getstate_s *state, FAR uint8_t *pch); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_INPUT_KBD_CODEC_H */ + diff --git a/nuttx/include/nuttx/usb/hid.h b/nuttx/include/nuttx/usb/hid.h index 5b83f08fc..877203a9c 100644 --- a/nuttx/include/nuttx/usb/hid.h +++ b/nuttx/include/nuttx/usb/hid.h @@ -619,7 +619,7 @@ #define USBHID_KBDUSE_RCTRL 0xe4 /* Keyboard RightControl */ #define USBHID_KBDUSE_RSHIFT 0xe5 /* Keyboard RightShift */ #define USBHID_KBDUSE_RALT 0xe6 /* Keyboard RightAlt */ -#define USBHID_KBDUSE_RGUI 0xe7 /* Keyboard Right GUI*/ +#define USBHID_KBDUSE_RGUI 0xe7 /* Keyboard Right GUI */ #define USBHID_KBDUSE_MAX 0xe7 diff --git a/nuttx/libc/misc/Make.defs b/nuttx/libc/misc/Make.defs index f4284ac60..c6af5f860 100644 --- a/nuttx/libc/misc/Make.defs +++ b/nuttx/libc/misc/Make.defs @@ -35,7 +35,7 @@ # Add the internal C files to the build -CSRCS += lib_init.c lib_filesem.c +CSRCS += lib_init.c lib_filesem.c lib_kbdencode.c lib_kbddecode.c # Add C files that depend on file OR socket descriptors diff --git a/nuttx/libc/misc/lib_kbddecode.c b/nuttx/libc/misc/lib_kbddecode.c new file mode 100644 index 000000000..046d570f9 --- /dev/null +++ b/nuttx/libc/misc/lib_kbddecode.c @@ -0,0 +1,258 @@ +/******************************************************************************************** + * libc/msic/lib_kbddecode.c + * Decoding side of the Keyboard CODEC + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +#define NDX_ESC 0 +#define NDX_BRACKET 1 +#define NDX_CODE 2 +#define NCX_SEMICOLON 3 + +#define NCH_ESC 1 +#define NCH_BRACKET 2 +#define NCH_CODE 3 +#define NCH_SEMICOLON 4 + +/******************************************************************************************** + * Private Functions + ********************************************************************************************/ + +/**************************************************************************** + * Name: kbd_reget + * + * Description: + * We have unused characters from the last, unsuccessful. Return one of + * these instead of the . + * + * Input Parameters: + * stream - An instance of lib_instream_s to do the low-level get + * operation. + * pch - The location character to save the returned value. This may be + * either a normal, "in-band" ASCII characer or a special, "out-of-band" + * command. + * state - A user provided buffer to support parsing. This structure + * should be cleared the first time that kbd_get is called. + * + * Returned Value: + * 2 - Indicates the successful receipt of a special, "out-of-band" command + * 1 - Indicates the successful receipt of normal, "in-band" ASCII data. + * 0 - Indicates end-of-file or that the stream has been closed + * EOF - An error has getting the next character (reported by the stream). + * + ****************************************************************************/ + +static int kbd_reget(FAR struct kget_getstate_s *state, FAR uint8_t *pch) +{ + /* Return the next character */ + + *pch = state->buf[state->ndx]; + state->ndx++; + state->nch--; + return KBD_NORMAL; +} + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +/**************************************************************************** + * Name: kbd_get + * + * Description: + * Put one byte of data or special command from the driver provided input + * buffer. + * + * Input Parameters: + * stream - An instance of lib_instream_s to do the low-level get + * operation. + * pch - The location character to save the returned value. This may be + * either a normal, "in-band" ASCII characer or a special, "out-of-band" + * command. + * state - A user provided buffer to support parsing. This structure + * should be cleared the first time that kbd_get is called. + * + * Returned Value: + * 1 - Indicates the successful receipt of a special, "out-of-band" command + * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. + * EOF - An error has getting the next character (reported by the stream). + * Normally indicates the end of file. + * + ****************************************************************************/ + +int kbd_get(FAR struct lib_instream_s *stream, + FAR struct kget_getstate_s *state, FAR uint8_t *pch) +{ + int ch; + + DEBUGASSERT(stream && state && pch); + + /* Are their ungotten characters from the last, failed parse? */ + + if (state->nch > 0) + { + /* Yes, return the next ungotten character */ + + return kbd_reget(state, pch); + } + + state->ndx = 0; + + /* No, ungotten characters. Check for the beginning of an esc sequence. */ + + ch = stream->get(stream); + if (ch == EOF) + { + /* End of file/stream */ + + return KBD_ERROR; + } + else + { + state->buf[NDX_ESC] = (uint8_t)ch; + state->nch = NCH_ESC; + + if (ch != ASCII_ESC) + { + /* Not the beginning of an escape sequence. Return the character. */ + + return kbd_reget(state, pch); + } + } + + /* Check for ESC-[ */ + + ch = stream->get(stream); + if (ch == EOF) + { + /* End of file/stream. Return the escape character now. We will + * return the EOF indication next time. + */ + + return kbd_reget(state, pch); + } + else + { + state->buf[NDX_BRACKET] = ch; + state->nch = NCH_BRACKET; + + if (ch != '[') + { + /* Not the beginning of an escape sequence. Return the ESC now, + * return the following character later. + */ + + return kbd_reget(state, pch); + } + } + + /* Get and verify the special, "out-of-band" command code */ + + ch = stream->get(stream); + if (ch == EOF) + { + /* End of file/stream. Unget everything and return the ESC character. + */ + + return kbd_reget(state, pch); + } + else + { + state->buf[NDX_CODE] = (uint8_t)ch; + state->nch = NCH_CODE; + + /* Check for a valid special command code */ + + if (ch < FIRST_KEYCODE || ch > LAST_KEYCODE) + { + /* Not a special command code, return the ESC now and the next two + * characters later. + */ + + return kbd_reget(state, pch); + } + } + + /* Check for the final semicolon */ + + ch = stream->get(stream); + if (ch == EOF) + { + /* End of file/stream. Unget everything and return the ESC character. + */ + + return kbd_reget(state, pch); + } + else + { + state->buf[NCX_SEMICOLON] = (uint8_t)ch; + state->nch = NCH_SEMICOLON; + + /* Check for a valid special command code */ + + if (ch != ';') + { + /* Not a special command code, return the ESC now and the next two + * characters later. + */ + + return kbd_reget(state, pch); + } + } + + /* We have successfully parsed the the entire escape sequence. Return the + * special code in pch and the value 2. + */ + + *pch = state->buf[NDX_CODE]; + state->nch = 0; + return KBD_SPECIAL; +} + diff --git a/nuttx/libc/misc/lib_kbdencode.c b/nuttx/libc/misc/lib_kbdencode.c new file mode 100644 index 000000000..80bf14777 --- /dev/null +++ b/nuttx/libc/misc/lib_kbdencode.c @@ -0,0 +1,81 @@ +/******************************************************************************************** + * libc/msic/lib_kbdencode.c + * Encoding side of the Keyboard CODEC + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +/**************************************************************************** + * Name: kbd_putspecial + * + * Description: + * Put one special, "out-of-band" command into the output stream. + * + * Input Parameters: + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_putspecial(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream) +{ + DEBUGASSERT(stream && keycode >= KEYCODE_FWDDEL && keycode <= LAST_KEYCODE); + + stream->put(stream, ASCII_ESC); + stream->put(stream, '['); + stream->put(stream, (int)keycode); + stream->put(stream, ';'); +} + -- cgit v1.2.3 From 373e145e546cc34b6a0000d7b3f71538c05a3b1b Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 26 Dec 2012 18:54:59 +0000 Subject: Implement encoding the usbhost HID keyboard driver; configre olimex-lpc1766stk HID keyboard configuration to use the kconfig-frontends tool git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5461 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/hidkbd/hidkbd_main.c | 4 +- nuttx/ChangeLog | 6 + nuttx/Documentation/NuttxPortingGuide.html | 148 +++- nuttx/configs/olimex-lpc1766stk/README.txt | 20 +- nuttx/configs/olimex-lpc1766stk/hidkbd/appconfig | 39 - nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig | 914 +++++++++++++---------- nuttx/configs/olimex-lpc1766stk/hidkbd/setenv.sh | 4 +- nuttx/drivers/usbhost/Kconfig | 64 +- nuttx/drivers/usbhost/usbhost_hidkbd.c | 375 ++++++++-- nuttx/include/nuttx/input/kbd_codec.h | 26 +- nuttx/libc/misc/lib_kbddecode.c | 10 +- nuttx/libc/misc/lib_kbdencode.c | 3 + 12 files changed, 1080 insertions(+), 533 deletions(-) delete mode 100644 nuttx/configs/olimex-lpc1766stk/hidkbd/appconfig diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c index e744a495c..bc1eebed0 100644 --- a/apps/examples/hidkbd/hidkbd_main.c +++ b/apps/examples/hidkbd/hidkbd_main.c @@ -206,7 +206,7 @@ int hidkbd_main(int argc, char *argv[]) printf("Device %s opened\n", CONFIG_EXAMPLES_HIDKBD_DEVNAME); fflush(stdout); - /* Loop until there is a read failure */ + /* Loop until there is a read failure (or EOF?) */ do { @@ -220,7 +220,7 @@ int hidkbd_main(int argc, char *argv[]) (void)write(1, buffer, nbytes); } } - while (nbytes >= 0); + while (nbytes > 0); printf("Closing device %s: %d\n", CONFIG_EXAMPLES_HIDKBD_DEVNAME, (int)nbytes); fflush(stdout); diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 80ddb56c6..7e1c538d7 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3821,3 +3821,9 @@ * libc/misc/lib_kbdencode.c and lib_kbddecode.c: Add logic to marshal and serialized "out-of-band" keyboard commands intermixed with normal ASCII data (not yet hooked into anything). + * drivers/usbhost/usbhost_hidkbd.c: If CONFIG_HIDKBD_ENCODED is + defined, this driver will now use libc/misc/lib_kbdencode.c to + encode special function keys. + * configs/olimex-lpc1766stk/hidkbd: This configuration has been + converted to use the kconfig-frontends configuration tool. + diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 0408f82ac..ebb3eff4b 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -131,7 +131,8 @@ 6.3.12 PWM Drivers
    6.3.13 CAN Drivers
    6.3.14 Quadrature Encoder Drivers
    - 6.3.15 Watchdog Timer Drivers + 6.3.15 Watchdog Timer Drivers
    + 6.3.16 Keyboard/Keypad Drivers
    6.4 Power Management
      @@ -3620,6 +3621,151 @@ extern void up_ledoff(int led);
    +

    6.3.16 Keyboard/Keypad Drivers

    +

    + "Out-of-Band" Commands. + Keyboards and keypads are the same device for NuttX. + A keypad is thought of as simply a keyboard with fewer keys. + In NuttX, a keyboard/keypad driver is simply a character driver that may have an (optional) encoding/decoding layer on the data returned by the character driver. + A keyboard may return simple text data (alphabetic, numeric, and punctuaction) or control characters (enter, control-C, etc.). + We can think about this the normal "in-band" keyboard data stream. + However, in addition, most keyboards support actions that cannot be represented as text data. + Such actions include things like cursor controls (home, up arrow, page down, etc.), editing functions (insert, delete, etc.), volume controls, (mute, volume up, etc.) and other special functions. + We can think about this as special, "out-of-band" keyboard commands. + In this case, some special encoding may be required to multiplex the in-band text data and out-of-band command streams. +

    +

    + Encoding/Decoding Layer. + An optional encoding/decoding layer can be used with the basic character driver to encode the out-of-band commands into the text data stream. + The function interfaces that comprise that encoding/decoding layer are defined in the header file include/nuttx/input/kbd_code.h. + These functions provide an matched set of (a) driver encoding interfaces, and (b) application decoding interfaces. +

    +
      +
    1. +

      + Driver Encoding Interfaces. +

      +
        +
      • +

        + kbd_puttext() +

        +

        Function Prototype:

        + 
          +#include <nuttx/streams.h>
+#include <nuttx/input/kbd_codec.h>
+void kbd_puttext(int ch, FAR struct lib_outstream_s *stream);
+
        +

        Description:

        +
          + Put one byte of normal, "in-band" ASCII data into the output stream. +
        +

        Input Pameters:

        +
          +
        • + ch: The character to be added to the output stream. +
          • +
        • + stream: An instance of lib_outstream_s to perform the actual low-level put operation. +
          • +
        +

        Returned Value:

        +
          + None. +
        +
        • +
      • +

        + kbd_putspecial() +

        +

        Function Prototype:

        + 
          +#include <nuttx/streams.h>
+#include <nuttx/input/kbd_codec.h>
+void kbd_putspecial(enum kbd_keycode_e keycode, FAR struct lib_outstream_s *stream);
+
        +

        Description:

        +
          + Put one special, "out-of-band" command into the output stream. +
        +

        Input Pameters:

        +
          +
        • + keycode: The command to be added to the output stream. + The enumeration enum kbd_keycode_e keycode identifies all commands known to the system. +
          • +
        • + stream: An instance of lib_outstream_s to perform the actual low-level put operation. +
          • +
        +

        Returned Value:

        +
          + None. +
        +
        • +
      +
      2. +
    2. +

      + Application Decoding Interfaces. +

      +
        +
      • +

        + kbd_get() +

        +

        Function Prototype:

        + 
          +#include <nuttx/streams.h>
+#include <nuttx/input/kbd_codec.h>
+int kbd_get(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *state, FAR uint8_t *pch);
+
        +

        Description:

        +
          + Get one byte of data or special command from the driver provided input buffer. +
        +

        Input Pameters:

        +
          +
        • + stream: An instance of lib_instream_s to perform the actual low-level get operation. +
          • +
        • + pch: The location character to save the returned value. + This may be either a normal, "in-band" ASCII characer or a special, "out-of-band" command (i.e., a value from enum kbd_getstate_s. +
          • +
        • + state: A user provided buffer to support parsing. + This structure should be cleared the first time that kbd_get is called. +
          • +
        +

        Returned Value:

        +
          +
        • + 1: + Indicates the successful receipt of a special, "out-of-band" command. + The returned value in pch is a value from enum kbd_getstate_s. +
          • +
        • + 0: + Indicates the successful receipt of normal, "in-band" ASCII data. + The returned value in pch is a simple byte of text or control data. +
          • +
        • + EOF: + An error has getting the next character (reported by the stream). + Normally indicates the end of file. +
          • +
        +
        • +
      +
      3. +
    +

    + I/O Streams. + Notice the use of the abstract I/O streams in these interfaces. + These stream interfaces are defined in include/nuttx/streams.h. +

    +

    6.4 Power Management

    6.4.1 Overview

    diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt index ec7ddd42d..e2c940bac 100644 --- a/nuttx/configs/olimex-lpc1766stk/README.txt +++ b/nuttx/configs/olimex-lpc1766stk/README.txt @@ -899,7 +899,25 @@ Where is one of the following: This configuration directory, performs a simple test of the USB host HID keyboard class driver using the test logic in apps/examples/hidkbd. - nettest: + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: This is how the build is configured by + be default. These options can easily be re-confured, however. + + CONFIG_HOST_WINDOWS=y : Windows + CONFIG_WINDOWS_CYGWIN=y : Cygwin environment on Windows + CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + + nettest: This configuration directory may be used to enable networking using the LPC17xx's Ethernet controller. It uses apps/examples/nettest to excercise the TCP/IP network. diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/appconfig b/nuttx/configs/olimex-lpc1766stk/hidkbd/appconfig deleted file mode 100644 index 79a7c50ab..000000000 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/appconfig +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# configs/olimex-lpc1766stk/hidkbd/appconfig -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/hidkbd - diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig index 9a4c37fb4..78e411560 100755 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -1,506 +1,604 @@ -############################################################################ -# configs/olimex-lpc1766stk/hidkbd/defconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +CONFIG_ARCH_CHIP_LPC17XX=y +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lpc17xx" -CONFIG_ARCH_CHIP_LPC17XX=y -CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_BOARD="olimex-lpc1766stk" -CONFIG_ARCH_BOARD_LPC1766STK=y +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=8111 -CONFIG_DRAM_SIZE=32768 -CONFIG_DRAM_START=0x10000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # -# Identify toolchain and linker options +# LPC17xx Configuration Options # -CONFIG_LPC17_CODESOURCERYW=n -CONFIG_LPC17_CODESOURCERYL=n -CONFIG_LPC17_DEVKITARM=n -CONFIG_LPC17_BUILDROOT=y +# CONFIG_ARCH_CHIP_LPC1751 is not set +# CONFIG_ARCH_CHIP_LPC1752 is not set +# CONFIG_ARCH_CHIP_LPC1754 is not set +# CONFIG_ARCH_CHIP_LPC1756 is not set +# CONFIG_ARCH_CHIP_LPC1758 is not set +# CONFIG_ARCH_CHIP_LPC1759 is not set +# CONFIG_ARCH_CHIP_LPC1764 is not set +# CONFIG_ARCH_CHIP_LPC1765 is not set +CONFIG_ARCH_CHIP_LPC1766=y +# CONFIG_ARCH_CHIP_LPC1767 is not set +# CONFIG_ARCH_CHIP_LPC1768 is not set +# CONFIG_ARCH_CHIP_LPC1769 is not set +CONFIG_ARCH_FAMILY_LPC176X=y # -# Individual subsystems can be enabled: +# LPC17xx Peripheral Support # -CONFIG_LPC17_ETHERNET=n +CONFIG_LPC17_MAINOSC=y +CONFIG_LPC17_PLL0=y +# CONFIG_LPC17_PLL1 is not set +# CONFIG_LPC17_ETHERNET is not set CONFIG_LPC17_USBHOST=y -CONFIG_LPC17_USBOTG=n -CONFIG_LPC17_USBDEV=n +# CONFIG_LPC17_USBDEV is not set CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=n -CONFIG_LPC17_UART2=n -CONFIG_LPC17_UART3=n -CONFIG_LPC17_CAN1=n -CONFIG_LPC17_CAN2=n -CONFIG_LPC17_SPI=n -CONFIG_LPC17_SSP0=n -CONFIG_LPC17_SSP1=n -CONFIG_LPC17_I2C0=n -CONFIG_LPC17_I2C1=n -CONFIG_LPC17_I2S=n -CONFIG_LPC17_TMR0=n -CONFIG_LPC17_TMR1=n -CONFIG_LPC17_TMR2=n -CONFIG_LPC17_TMR3=n -CONFIG_LPC17_RIT=n -CONFIG_LPC17_PWM=n -CONFIG_LPC17_MCPWM=n -CONFIG_LPC17_QEI=n -CONFIG_LPC17_RTC=n -CONFIG_LPC17_WDT=n -CONFIG_LPC17_ADC=n -CONFIG_LPC17_DAC=n -CONFIG_LPC17_GPDMA=n - -# -# LPC17xx Button interrupt support -# -CONFIG_GPIO_IRQ=n -CONFIG_ARCH_IRQBUTTONS=n - -# -# LPC17xx specific serial device driver settings +# CONFIG_LPC17_UART1 is not set +# CONFIG_LPC17_UART2 is not set +# CONFIG_LPC17_UART3 is not set +# CONFIG_LPC17_CAN1 is not set +# CONFIG_LPC17_CAN2 is not set +# CONFIG_LPC17_SPI is not set +# CONFIG_LPC17_SSP0 is not set +# CONFIG_LPC17_SSP1 is not set +# CONFIG_LPC17_I2C0 is not set +# CONFIG_LPC17_I2C1 is not set +# CONFIG_LPC17_I2C2 is not set +# CONFIG_LPC17_I2S is not set +# CONFIG_LPC17_TMR0 is not set +# CONFIG_LPC17_TMR1 is not set +# CONFIG_LPC17_TMR2 is not set +# CONFIG_LPC17_TMR3 is not set +# CONFIG_LPC17_RIT is not set +# CONFIG_LPC17_PWM is not set +# CONFIG_LPC17_MCPWM is not set +# CONFIG_LPC17_QEI is not set +# CONFIG_LPC17_RTC is not set +# CONFIG_LPC17_WDT is not set +# CONFIG_LPC17_ADC is not set +# CONFIG_LPC17_DAC is not set +# CONFIG_LPC17_GPDMA is not set +# CONFIG_LPC17_FLASH is not set + # -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART3_SERIAL_CONSOLE=n +# Serial driver options +# +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_UART0_FLOWCONTROL is not set -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART3_TXBUFSIZE=256 +# +# ADC driver options +# -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART3_RXBUFSIZE=256 +# +# CAN driver options +# +# CONFIG_GPIO_IRQ is not set -CONFIG_UART0_BAUD=57600 -CONFIG_UART2_BAUD=57600 -CONFIG_UART3_BAUD=57600 -CONFIG_UART1_BAUD=57600 +# +# I2C driver options +# -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART3_BITS=8 +# +# Ethernet driver options +# -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART3_PARITY=0 +# +# USB device driver options +# -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 -CONFIG_UART3_2STOP=0 +# +# USB host driver options +# +CONFIG_USBHOST_OHCIRAM_SIZE=1536 +CONFIG_USBHOST_NEDS=2 +CONFIG_USBHOST_NTDS=3 +CONFIG_USBHOST_TDBUFFERS=3 +CONFIG_USBHOST_TDBUFSIZE=128 +CONFIG_USBHOST_IOBUFSIZE=512 +CONFIG_USBHOST_BULK_DISABLE=y +# CONFIG_USBHOST_INT_DISABLE is not set +CONFIG_USBHOST_ISOC_DISABLE=y +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# LPC17xx specific PHY/Ethernet device driver settings +# Architecture Options # -CONFIG_PHY_KS8721=y -CONFIG_PHY_AUTONEG=y -CONFIG_PHY_SPEED100=n -CONFIG_PHY_FDUPLEX=y -CONFIG_NET_EMACRAM_SIZE=8192 -CONFIG_NET_NTXDESC=7 -CONFIG_NET_NRXDESC=7 -CONFIG_NET_REGDEBUG=n +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # -# General build options +# Board Settings # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=y -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=n +CONFIG_DRAM_START=0x10000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 # -# General OS setup +# Boot options # -CONFIG_USER_ENTRYPOINT="hidkbd_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_USB=n -CONFIG_MM_REGIONS=2 -CONFIG_ARCH_LOWPUTC=y +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_LPC1766STK=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-lpc1766stk" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=11 CONFIG_START_DAY=10 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 CONFIG_SIG_SIGWORK=4 +# CONFIG_SCHED_LPWORK is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="hidkbd_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_POLL is not set + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_HAVECARDDETECT is not set +CONFIG_MMCSD_SPI=y +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_CONFIG_SERIAL_NPOLLWAITERS=2 +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=57600 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +CONFIG_USBHOST=y +CONFIG_USBHOST_NPREALLOC=0 +# CONFIG_USBHOST_MSC is not set +CONFIG_USBHOST_HIDKBD=y +CONFIG_HIDKBD_POLLUSEC=100000 +CONFIG_HIDKBD_DEFPRIO=50 +CONFIG_HIDKBD_STACKSIZE=1024 +CONFIG_HIDKBD_BUFSIZE=64 +CONFIG_HIDKBD_NPOLLWAITERS=2 +# CONFIG_HIDKBD_RAWSCANCODES is not set +# CONFIG_HIDKBD_ENCODED is not set +# CONFIG_HIDKBD_ALLSCANCODES is not set +# CONFIG_HIDKBD_NODEBOUNCE is not set +# CONFIG_WIRELESS is not set # -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. +# System Logging Device Options # -# There are certain dependency relationships in these -# features. + # -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. +# System Logging # -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n -CONFIG_DISABLE_POLL=n +# CONFIG_RAMLOG is not set # -# Misc libc settings +# Networking Support # -CONFIG_NOPRINTF_FIELDWIDTH=n +# CONFIG_NET is not set # -# Allow for architecture optimized implementations +# File Systems # -# The architecture can provide optimized versions of the -# following to improve system performance + +# +# File system configuration # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n +# CONFIG_FS_FAT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set # -# Sizes of configurable things (0 disables) +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines # -CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=4 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=4 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# Filesystem configuration +# Basic CXX Support # -CONFIG_FS_FAT=n -CONFIG_FAT_LCNAMES=n -CONFIG_FAT_LFN=n -CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set # -# Maintain legacy build behavior (revisit) +# Application Configuration # -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set # -# SPI-based MMC/SD driver +# Examples # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +CONFIG_EXAMPLES_HIDKBD=y +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set # -# Block driver buffering +# Interpreters # -CONFIG_FS_READAHEAD=n -CONFIG_FS_WRITEBUFFER=n # -# SDIO-based MMC/SD driver +# Interpreters # -CONFIG_SDIO_DMA=n -CONFIG_MMCSD_MMCSUPPORT=n -CONFIG_MMCSD_HAVECARDDETECT=n +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set # -# TCP/IP and UDP support via uIP +# Network Utilities # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=8 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=562 -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=8 -CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 -CONFIG_NET_TCPBACKLOG=n -CONFIG_NET_MAX_LISTENPORTS=8 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=8 -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n # -# UIP Network Utilities +# Networking Utilities # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set # -# USB Device Configuration +# ModBus # -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 # -# USB Host Configuration +# FreeModbus # -CONFIG_USBHOST=y -CONFIG_USBHOST_NPREALLOC=0 -CONFIG_USBHOST_BULK_DISABLE=y -CONFIG_USBHOST_INT_DISABLE=n -CONFIG_USBHOST_ISOC_DISABLE=y +# CONFIG_MODBUS is not set # -# LPC17xx USB Device Configuration +# NSH Library # -CONFIG_LPC17_USBDEV_FRAME_INTERRUPT=n -CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT=n -CONFIG_LPC17_USBDEV_DMA=n -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 -CONFIG_LPC17_USBDEV_DMAINTMASK=0 +# CONFIG_NSH_LIBRARY is not set # -# LPC17xx USB Host Configuration +# NxWidgets/NxWM # -# OHCI RAM layout: + +# +# System NSH Add-Ons # -CONFIG_USBHOST_OHCIRAM_SIZE=1536 -CONFIG_USBHOST_NEDS=2 -CONFIG_USBHOST_NTDS=3 -CONFIG_USBHOST_TDBUFFERS=3 -CONFIG_USBHOST_TDBUFSIZE=128 -CONFIG_USBHOST_IOBUFSIZE=512 # -# USB Serial Device Configuration -# -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=5 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 - -# -# USB Storage Device Configuration -# -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=2 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y - -# -# Settings for examples/uip -# -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n - -# -# Settings for examples/nettest -# -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 - -# -# Settings for examples/ostest -# -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 - -# -# Settings for examples/buttons -# -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=7 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_BUTTONS_NAME0="BUT1" -CONFIG_EXAMPLES_BUTTONS_NAME1="BUT2" -CONFIG_EXAMPLES_BUTTONS_NAME2="WAKE-UP" -CONFIG_EXAMPLES_BUTTONS_NAME3="CENTER" -CONFIG_EXAMPLES_BUTTONS_NAME4="UP" -CONFIG_EXAMPLES_BUTTONS_NAME5="DOWN" -CONFIG_EXAMPLES_BUTTONS_NAME6="LEFT" -CONFIG_EXAMPLES_BUTTONS_NAME7="RIGHT" - -# -# Settings for apps/nshlib -# -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=y -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" - -# -# Architecture-specific NSH options -# -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 - -# -# Settings for examples/usbserial -# -CONFIG_EXAMPLES_USBSERIAL_INONLY=n -CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n -CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n -CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n - -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set # -# Stack and heap information +# I2C tool # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/setenv.sh b/nuttx/configs/olimex-lpc1766stk/hidkbd/setenv.sh index af4a2589e..6b51c10de 100755 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/setenv.sh +++ b/nuttx/configs/olimex-lpc1766stk/hidkbd/setenv.sh @@ -50,7 +50,7 @@ fi # This is the Cygwin path to the location where I installed the CodeSourcery # toolchain under windows. You will also have to edit this if you install # the CodeSourcery toolchain in any other location -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" # These are the Cygwin paths to the locations where I installed the Atollic # toolchain under windows. You will also have to edit this if you install @@ -62,7 +62,7 @@ fi # This is the Cygwin path to the location where I build the buildroot # toolchain. -export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" +# export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" # The Olimex-lpc1766stk/tools directory export LPCTOOL_DIR="${WD}/configs/olimex-lpc1766stk/tools" diff --git a/nuttx/drivers/usbhost/Kconfig b/nuttx/drivers/usbhost/Kconfig index 35695d750..de8469b41 100644 --- a/nuttx/drivers/usbhost/Kconfig +++ b/nuttx/drivers/usbhost/Kconfig @@ -2,6 +2,7 @@ # For a description of the syntax of this configuration file, # see misc/tools/kconfig-language.txt. # + config USBHOST_NPREALLOC int "Number of pre-allocated class instances" default 4 @@ -29,64 +30,85 @@ config USBHOST_ISOC_DISABLE On some architectures, selecting this setting will reduce driver size by disabling isochronous endpoint support +config USBHOST_MSC + bool "Mass Storage Class Support" + default n + depends on !BULK_DISABLE + ---help--- + Enable support for the keyboard class driver. This also depends on + NFILE_DESCRIPTORS > 0 && SCHED_WORKQUEUE=y + config USBHOST_HIDKBD - bool "HID keyboad class support" + bool "HID Keyboard Class Support" default n - depends on !USBHOST_INT_DISABLE && SCHED_WORKQUEUE && !DISABLE_SIGNALS + depends on !INT_DISABLE + ---help--- + Enable support for the keyboard class driver. This also depends on + SCHED_WORKQUEUE && !DISABLE_SIGNALS if USBHOST_HIDKBD config HIDKBD_POLLUSEC - bool "" - default n + int "Keyboard Poll Rate (MSEC)" + default 100000 ---help--- - Device poll rate in microseconds. Default: 100 milliseconds. + Device poll rate in microseconds. Default: 100,000 microseconds. config HIDKBD_DEFPRIO - bool "" - default n + int "Polling Thread Priority" + default 50 ---help--- Priority of the polling thread. Default: 50. config HIDKBD_STACKSIZE - bool "" - default n + int "Polling thread stack size" + default 1024 ---help--- Stack size for polling thread. Default: 1024 config HIDKBD_BUFSIZE - bool "" - default n + int "Scancode Buffer Size" + default 64 ---help--- Scancode buffer size. Default: 64. config HIDKBD_NPOLLWAITERS - bool "" - default n + int "Max Number of Waiters for Poll Event" + default 2 + depends on !DISABLE_POLL ---help--- If the poll() method is enabled, this defines the maximum number of threads that can be waiting for keyboard events. Default: 2. config HIDKBD_RAWSCANCODES - bool "" + bool "Use Raw Scan Codes" + default n + ---help--- + If set to y no conversions will be made on the raw keyboard scan + codes. This option is useful during testing. Default: ASCII conversion. + +config HIDKBD_ENCODED + bool "Enocode Special Keys" default n + depends on !HIDKBD_RAWSCANCODES ---help--- - If set to y no conversion will be made on the raw keyboard scan - codes. Default: ASCII conversion. + Encode special key press events in the user buffer. In this case, + the use end must decode the encoded special key values using the + interfaces defined in include/nuttx/input/kbd_codec.h. These + special keys include such things as up/down arrows, home and end + keys, etc. If this not defined, only 7-bit print-able and control + ASCII characters will be provided to the user. config HIDKBD_ALLSCANCODES - bool "" + bool "Use All Scancodes" default n ---help--- If set to y all 231 possible scancodes will be converted to something. Default: 104 key US keyboard. config HIDKBD_NODEBOUNCE - bool "" + bool "Disable Debounce" default n ---help--- If set to y normal debouncing is disabled. Default: Debounce enabled (No repeat keys). - USB host mass storage class driver. Requires USBHOST=y, - config USBHOST_BULK_DISABLE=n, NFILE_DESCRIPTORS > 0, - and SCHED_WORKQUEUE=y endif diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c index e69d68e7b..e0c4680eb 100644 --- a/nuttx/drivers/usbhost/usbhost_hidkbd.c +++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/usbhost/usbhost_hidkbd.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -62,6 +62,11 @@ #include #include +#ifdef CONFIG_HIDKBD_ENCODED +# include +# include +#endif + /* Don't compile if prerequisites are not met */ #if defined(CONFIG_USBHOST) && !defined(CONFIG_USBHOST_INT_DISABLE) && CONFIG_NFILE_DESCRIPTORS > 0 @@ -126,6 +131,14 @@ # endif #endif +/* If we are using raw scancodes, then we cannot support encoding of + * special characters either. + */ + +#ifdef CONFIG_HIDKBD_RAWSCANCODES +# undef CONFIG_HIDKBD_ENCODED +#endif + /* Driver support ***********************************************************/ /* This format is used to construct the /dev/kbd[n] device driver path. It * defined here so that it will be used consistently in all places. @@ -144,6 +157,23 @@ #define USBHOST_MAX_CREFS 0x7fff +/* Debug ********************************************************************/ +/* Both CONFIG_DEBUG_INPUT and CONFIG_DEBUG_USB could apply to this file. + * We assume here that CONFIG_DEBUG_INPUT might be enabled separately, but + * CONFIG_DEBUG_USB implies both. + */ + +#ifndef CONFIG_DEBUG_INPUT +# undef idbg +# define idbg udbg +# undef illdbg +# define illdbg ulldbg +# undef ivdbg +# define ivdbg uvdbg +# undef illvdbg +# define illvdbg ullvdbg +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -209,6 +239,16 @@ struct usbhost_state_s uint8_t kbdbuffer[CONFIG_HIDKBD_BUFSIZE]; }; +/* This type is used for encoding special characters */ + +#ifdef CONFIG_HIDKBD_ENCODED +struct usbhost_outstream_s +{ + struct lib_outstream_s stream; + FAR struct usbhost_state_s *priv; +}; +#endif + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -240,7 +280,15 @@ static inline void usbhost_mkdevname(FAR struct usbhost_state_s *priv, char *dev /* Keyboard polling thread */ static void usbhost_destroy(FAR void *arg); +static void usbhost_putbuffer(FAR struct usbhost_state_s *priv, uint8_t keycode); +#ifdef CONFIG_HIDKBD_ENCODED +static void usbhost_putstream(FAR struct lib_outstream_s *this, int ch); +#endif static inline uint8_t usbhost_mapscancode(uint8_t scancode, uint8_t modifier); +#ifdef CONFIG_HIDKBD_ENCODED +static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, + uint8_t scancode, uint8_t modifier); +#endif static int usbhost_kbdpoll(int argc, char *argv[]); /* Helpers for usbhost_connect() */ @@ -346,6 +394,121 @@ static struct usbhost_state_s *g_priv; /* Data passed to thread */ */ #ifndef CONFIG_HIDKBD_RAWSCANCODES +#ifdef CONFIG_HIDKBD_ENCODED + +/* The first and last scancode values with encode-able values */ + +#define FIRST_ENCODING USBHID_KBDUSE_ENTER /* 0x28 Keyboard Return (ENTER) */ +#ifdef CONFIG_HIDKBD_ALLSCANCODES +# define LAST_ENCODING USBHID_KBDUSE_POWER /* 0x66 Keyboard Power */ +#else +#define LAST_ENCODING USBHID_KBDUSE_KPDHEXADECIMAL /* 0xdd Keypad Hexadecimal */ +#endif + +#define USBHID_NUMENCODINGS (LAST_ENCODING - FIRST_ENCODING + 1) + +static const uint8_t encoding[USBHID_NUMENCODINGS] = +{ + /* 0x28-0x2f: Enter,escape,del,back-tab,space,_,+,{ */ + + KEYCODE_ENTER, 0, KEYCODE_FWDDEL, KEYCODE_BACKDEL, 0, 0, 0, 0, + + /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */ + + 0, KEYCODE_CAPSLOCK, KEYCODE_F1, KEYCODE_F2, KEYCODE_F3, KEYCODE_F4, KEYCODE_F5, KEYCODE_F6, + + /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ + + KEYCODE_F7, KEYCODE_F8, KEYCODE_F9, KEYCODE_F10, KEYCODE_F11, KEYCODE_F12, KEYCODE_PRTSCRN, KEYCODE_SCROLLLOCK, + + /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ + + KEYCODE_PAUSE, KEYCODE_INSERT, KEYCODE_HOME, KEYCODE_PAGEUP, KEYCODE_FWDDEL, KEYCODE_END, KEYCODE_PAGEDOWN, KEYCODE_RIGHT, + + /* 0x50-0x57: LeftArrow,DownArrow,UpArrow,Num Lock,/,*,-,+ */ + + KEYCODE_LEFT, KEYCODE_DOWN, KEYCODE_UP, KEYCODE_NUMLOCK, 0, 0, 0, 0, + + /* 0x58-0x5f: Enter,1-7 */ + + KEYCODE_ENTER, 0, 0, 0, 0, 0, 0, 0, + + /* 0x60-0x66: 8-9,0,.,Non-US \,Application,Power */ + + 0, 0, 0, 0, 0, 0, KEYCODE_POWER, + +#ifdef CONFIG_HIDKBD_ALLSCANCODES + + 0, /* 0x67 = */ + + /* 0x68-0x6f: F13,F14,F15,F16,F17,F18,F19,F20 */ + + KEYCODE_F13, KEYCODE_F14, KEYCODE_F15, KEYCODE_F16, KEYCODE_F17, KEYCODE_F18, KEYCODE_F19, KEYCODE_F20, + + /* 0x70-0x77: F21,F22,F23,F24,Execute,Help,Menu,Select */ + + KEYCODE_F21, KEYCODE_F22, KEYCODE_F23, KEYCODE_F24, KEYCODE_EXECUTE, KEYCODE_HELP, KEYCODE_MENU, KEYCODE_SELECT, + + /* 0x78-0x7f: Stop,Again,Undo,Cut,Copy,Paste,Find,Mute */ + + KEYCODE_STOP, KEYCODE_AGAIN, KEYCODE_UNDO, KEYCODE_CUT, KEYCODE_COPY, KEYCODE_PASTE, KEYCODE_FIND, KEYCODE_MUTE, + + /* 0x80-0x87: VolUp,VolDown,LCapsLock,lNumLock,LScrollLock,,,=,International1 */ + + KEYCODE_VOLUP, KEYCODE_VOLDOWN, KEYCODE_LCAPSLOCK, KEYCODE_LNUMLOCK, KEYCODE_LSCROLLLOCK, 0, 0, 0, + + /* 0x88-0x8f: International 2-9 */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0x90-0x97: LAN 1-8 */ + + KEYCODE_LANG1, KEYCODE_LANG2, KEYCODE_LANG3, KEYCODE_LANG4, KEYCODE_LANG5, KEYCODE_LANG6, KEYCODE_LANG7, KEYCODE_LANG8, + + /* 0x98-0x9f: LAN 9,Erase,SysReq,Cancel,Clear,Prior,Return,Separator */ + + 0, 0, KEYCODE_SYSREQ, KEYCODE_CANCEL, KEYCODE_CLEAR, 0, KEYCODE_ENTER, 0, + + /* 0xa0-0xa7: Out,Oper,Clear,CrSel,Excel,(reserved) */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0xa8-0xaf: (reserved) */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0xb0-0xb7: 00,000,ThouSeparator,DecSeparator,CurrencyUnit,SubUnit,(,) */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0xb8-0xbf: {,},tab,backspace,A-D */ + + 0, 0, 0, KEYCODE_BACKDEL, 0, 0, 0, 0, + + /* 0xc0-0xc7: E-F,XOR,^,%,<,>,& */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0xc8-0xcf: &&,|,||,:,#, ,@,! */ + + 0, 0, 0, 0, 0, 0, 0, 0, + + /* 0xd0-0xd7: Memory Store,Recall,Clear,Add,Subtract,Muliply,Divide,+/- */ + + KEYCODE_MEMSTORE, KEYCODE_MEMRECALL, KEYCODE_MEMCLEAR, KEYCODE_MEMADD, KEYCODE_MEMSUB, KEYCODE_MEMMUL, KEYCODE_MEMDIV, KEYCODE_NEGATE, + + /* 0xd8-0xdd: Clear,ClearEntry,Binary,Octal,Decimal,Hexadecimal */ + + KEYCODE_CLEAR, KEYCODE_CLEARENTRY, KEYCODE_BINARY, KEYCODE_OCTAL, KEYCODE_DECIMAL, KEYCODE_HEXADECIMAL +#endif +}; + +#endif + static const uint8_t ucmap[USBHID_NUMSCANCODES] = { 0, 0, 0, 0, 'A', 'B', 'C', 'D', /* 0x00-0x07: Reserved, errors, A-D */ @@ -356,7 +519,7 @@ static const uint8_t ucmap[USBHID_NUMSCANCODES] = '\n', '\033', '\177', 0, ' ', '_', '+', '{', /* 0x28-0x2f: Enter,escape,del,back-tab,space,_,+,{ */ '}', '|', 0, ':', '"', 0, '<', '>', /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */ '?', 0, 0, 0, 0, 0, 0, 0, /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,sScrollLock */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ 0, 0, 0, 0, '/', '*', '-', '+', /* 0x50-0x57: LeftArrow,DownArrow,UpArrow,Num Lock,/,*,-,+ */ '\n', '1', '2', '3', '4', '4', '6', '7', /* 0x58-0x5f: Enter,1-7 */ @@ -368,7 +531,7 @@ static const uint8_t ucmap[USBHID_NUMSCANCODES] = 0, 0, 0, 0, 0, ',', 0, 0, /* 0x80-0x87: VolUp,VolDown,LCapsLock,lNumLock,LScrollLock,,,=,International1 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x88-0x8f: International 2-9 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90-0x97: LAN 1-8 */ - 0, 0, 0, 0, 0, 0, '\n', 0, /* 0x98-0x9f: LAN 9,Ease,SysReq,Cancel,Clear,Prior,Return,Separator */ + 0, 0, 0, 0, 0, 0, '\n', 0, /* 0x98-0x9f: LAN 9,Erase,SysReq,Cancel,Clear,Prior,Return,Separator */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0xa0-0xa7: Out,Oper,Clear,CrSel,Excel,(reserved) */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0xa8-0xaf: (reserved) */ 0, 0, 0, 0, 0, 0, '(', ')', /* 0xb0-0xb7: 00,000,ThouSeparator,DecSeparator,CurrencyUnit,SubUnit,(,) */ @@ -403,7 +566,7 @@ static const uint8_t lcmap[USBHID_NUMSCANCODES] = 0, 0, 0, 0, 0, ',', 0, 0, /* 0x80-0x87: VolUp,VolDown,LCapsLock,lNumLock,LScrollLock,,,=,International1 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x88-0x8f: International 2-9 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90-0x97: LAN 1-8 */ - 0, 0, 0, 0, 0, 0, '\n', 0, /* 0x98-0x9f: LAN 9,Ease,SysReq,Cancel,Clear,Prior,Return,Separator */ + 0, 0, 0, 0, 0, 0, '\n', 0, /* 0x98-0x9f: LAN 9,Erase,SysReq,Cancel,Clear,Prior,Return,Separator */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0xa0-0xa7: Out,Oper,Clear,CrSel,Excel,(reserved) */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0xa8-0xaf: (reserved) */ 0, 0, 0, 0, 0, 0, '(', ')', /* 0xb0-0xb7: 00,000,ThouSeparator,DecSeparator,CurrencyUnit,SubUnit,(,) */ @@ -637,6 +800,88 @@ static void usbhost_destroy(FAR void *arg) usbhost_freeclass(priv); } +/**************************************************************************** + * Name: usbhost_putbuffer + * + * Description: + * Add one character to the user buffer. + * + * Input Parameters: + * priv - Driver internal state + * keycode - The value to add to the user buffer + * + * Returned Values: + * None + * + ****************************************************************************/ + +static void usbhost_putbuffer(FAR struct usbhost_state_s *priv, + uint8_t keycode) +{ + register unsigned int head; + register unsigned int tail; + + /* Copy the next keyboard character into the user buffer. */ + + head = priv->headndx; + priv->kbdbuffer[head] = keycode; + + /* Increment the head index */ + + if (++head >= CONFIG_HIDKBD_BUFSIZE) + { + head = 0; + } + + /* If the buffer is full, then increment the tail index to make space. Is + * it better to lose old keystrokes or new? + */ + + tail = priv->tailndx; + if (tail == head) + { + if (++tail >= CONFIG_HIDKBD_BUFSIZE) + { + tail = 0; + } + + /* Save the updated tail index */ + + priv->tailndx = tail; + } + + /* Save the updated head index */ + + priv->headndx = head; +} + +/**************************************************************************** + * Name: usbhost_putstream + * + * Description: + * A wrapper for usbhost_putc that is compatibile with the lib_outstream_s + * putc methos. + * + * Input Parameters: + * stream - The struct lib_outstream_s reference + * ch - The character to add to the user buffer + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_HIDKBD_ENCODED +static void usbhost_putstream(FAR struct lib_outstream_s *stream, int ch) +{ + FAR struct usbhost_outstream_s *privstream = (FAR struct lib_outstream_s *)stream; + + DEBUGASSERT(privstream && privstream->priv); + usbhost_putbuffer(privstream->priv), (uint8_t)ch); + stream->nput++; +} +#endif + /**************************************************************************** * Name: usbhost_mapscancode * @@ -679,6 +924,58 @@ static inline uint8_t usbhost_mapscancode(uint8_t scancode, uint8_t modifier) #endif } +/**************************************************************************** + * Name: usbhost_encodescancode + * + * Description: + * Check if the key has a special function encoding and, if it does, add + * the encoded value to the user buffer. + * + * Input Parameters: + * priv - Driver internal state + * scancode - Scan code to be mapped. + * modifier - Ctrl,Alt,Shift,GUI modifier bits + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_HIDKBD_ENCODED +static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, + uint8_t scancode, uint8_t modifier) +{ + struct usbhost_outstream_s stream; + uint8_t encoded; + + /* Check if the raw scancode is in a valid range */ + + if (scancode >= FIRST_ENCODING && scancode <= LAST_ENCODING) + { + /* Yes the value is within range */ + + encoded = encoding(scancode - FIRST_ENCODING); + ivdbg(" scancode: %02x modifier: %02x encoded: %d\n", + scancode, modifier, encoded); + + if (encoded) + { + struct usbhost_outstream_s usbstream; + + /* And it does correspond to a special function key */ + + usbstream->stream.put = usbhost_putstream; + usbstream->stream.nput = 0; + usbstream->priv = priv; + + /* Add the special function value to the user buffer */ + + kbd_putspecial((enum kbd_keycode_e)encoded, &usbstream); + } + } +} +#endif + /**************************************************************************** * Name: usbhost_kbdpoll * @@ -704,6 +1001,8 @@ static int usbhost_kbdpoll(int argc, char *argv[]) unsigned int npolls = 0; #endif unsigned int nerrors = 0; + bool empty = true; + bool newstate; int ret; uvdbg("Started\n"); @@ -717,13 +1016,13 @@ static int usbhost_kbdpoll(int argc, char *argv[]) * running. */ - priv = g_priv; - DEBUGASSERT(priv != NULL); + priv = g_priv; + DEBUGASSERT(priv != NULL); - priv->polling = true; - priv->crefs++; - usbhost_givesem(&g_syncsem); - sleep(1); + priv->polling = true; + priv->crefs++; + usbhost_givesem(&g_syncsem); + sleep(1); /* Loop here until the device is disconnected */ @@ -784,17 +1083,12 @@ static int usbhost_kbdpoll(int argc, char *argv[]) else if (priv->open) { struct usbhid_kbdreport_s *rpt = (struct usbhid_kbdreport_s *)priv->tbuffer; - unsigned int head; - unsigned int tail; - uint8_t ascii; + uint8_t keycode; int i; /* Add the newly received keystrokes to our internal buffer */ usbhost_takesem(&priv->exclsem); - head = priv->headndx; - tail = priv->tailndx; - for (i = 0; i < 6; i++) { /* Is this key pressed? But not pressed last time? @@ -828,15 +1122,15 @@ static int usbhost_kbdpoll(int argc, char *argv[]) * or cursor controls in this version of the driver. */ - ascii = usbhost_mapscancode(rpt->key[i], rpt->modifier); - uvdbg("Key %d: %02x ASCII:%c modifier: %02x\n", - i, rpt->key[i], ascii ? ascii : ' ', rpt->modifier); + keycode = usbhost_mapscancode(rpt->key[i], rpt->modifier); + ivdbg("Key %d: %02x keycode:%c modifier: %02x\n", + i, rpt->key[i], keycode ? keycode : ' ', rpt->modifier); /* Zero at this point means that the key does not map to a * printable character. */ - if (ascii != 0) + if (keycode != 0) { /* Handle control characters. Zero after this means * a valid, NUL character. @@ -844,36 +1138,28 @@ static int usbhost_kbdpoll(int argc, char *argv[]) if ((rpt->modifier & (USBHID_MODIFER_LCTRL|USBHID_MODIFER_RCTRL)) != 0) { - ascii &= 0x1f; + keycode &= 0x1f; } /* Copy the next keyboard character into the user * buffer. */ - priv->kbdbuffer[head] = ascii; - - /* Increment the head index */ - - if (++head >= CONFIG_HIDKBD_BUFSIZE) - { - head = 0; - } + usbhost_putbuffer(priv, keycode); + } - /* If the buffer is full, then increment the tail - * index to make space. Is it better to lose old - * keystrokes or new? - */ + /* The zero might, however, map to a special keyboard action (such as a + * cursor movement or function key). Attempt to encode the special key. + */ - if (tail == head) - { - if (++tail >= CONFIG_HIDKBD_BUFSIZE) - { - tail = 0; - } - } +#ifdef CONFIG_HIDKBD_ENCODED + else + { + usbhost_encodescancode(priv, rpt->key[i], rpt->modifier)); } +#endif } + /* Save the scancode (or lack thereof) for key debouncing on * next keyboard report. */ @@ -885,7 +1171,8 @@ static int usbhost_kbdpoll(int argc, char *argv[]) /* Did we just transition from no data available to data available? */ - if (head != tail && priv->headndx == priv->tailndx) + newstate = (priv->headndx == priv->tailndx); + if (empty && !newstate) { /* Yes.. Is there a thread waiting for keyboard data now? */ @@ -902,10 +1189,7 @@ static int usbhost_kbdpoll(int argc, char *argv[]) usbhost_pollnotify(priv); } - /* Update the head/tail indices */ - - priv->headndx = head; - priv->tailndx = tail; + empty = newstate; usbhost_givesem(&priv->exclsem); } @@ -958,6 +1242,7 @@ static int usbhost_kbdpoll(int argc, char *argv[]) usbhost_givesem(&priv->exclsem); } + return 0; } diff --git a/nuttx/include/nuttx/input/kbd_codec.h b/nuttx/include/nuttx/input/kbd_codec.h index b103d544e..d374ed8d3 100644 --- a/nuttx/include/nuttx/input/kbd_codec.h +++ b/nuttx/include/nuttx/input/kbd_codec.h @@ -113,7 +113,7 @@ enum kbd_keycode_e KEYCODE_PAUSE, /* Pause */ KEYCODE_BREAK, /* Break */ KEYCODE_CANCEL, /* Cancel */ - KEYCODE_PRINTSCN, /* PrintScreen */ + KEYCODE_PRTSCRN, /* PrintScreen */ KEYCODE_SYSREQ, /* SysReq/Attention */ /* Audio */ @@ -131,14 +131,15 @@ enum kbd_keycode_e KEYCODE_CLEAR, /* Clear */ KEYCODE_CLEARENTRY, /* Clear entry */ + KEYCODE_NEGATE, /* +/- */ - KEYCODE_MEMSET, /* Memory set */ + KEYCODE_MEMSTORE, /* Memory store */ KEYCODE_MEMCLEAR, /* Memory clear */ KEYCODE_MEMRECALL, /* Memory recall */ KEYCODE_MEMADD, /* Memory add */ - KEYCODE_MEMSUBTRACT, /* Memory substract */ - KEYCODE_MEMMULTIPY, /* Memory multiply */ - KEYCODE_MEMDIVIDE, /* Memory divide */ + KEYCODE_MEMSUB, /* Memory substract */ + KEYCODE_MEMMUL, /* Memory multiply */ + KEYCODE_MEMDIV, /* Memory divide */ KEYCODE_BINARY, /* Binary mode */ KEYCODE_OCTAL, /* Octal mode */ @@ -197,7 +198,7 @@ enum kbd_keycode_e * Public Types ****************************************************************************/ -struct kget_getstate_s +struct kbd_getstate_s { uint8_t nch; /* Number of characters in the buffer */ uint8_t ndx; /* Index to next character in the buffer */ @@ -225,7 +226,7 @@ extern "C" * Put one byte of normal, "in-band" ASCII data into the output stream. * * Input Parameters: - * ch - The character to be into the output stream. + * ch - The character to be added to the output stream. * stream - An instance of lib_outstream_s to do the low-level put * operation. * @@ -243,6 +244,9 @@ extern "C" * Put one special, "out-of-band" command into the output stream. * * Input Parameters: + * keycode - The command to be added to the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. * * Returned Value: * None @@ -261,7 +265,7 @@ void kbd_putspecial(enum kbd_keycode_e keycode, * Name: kbd_get * * Description: - * Put one byte of data or special command from the driver provided input + * Get one byte of data or special command from the driver provided input * buffer. * * Input Parameters: @@ -274,15 +278,17 @@ void kbd_putspecial(enum kbd_keycode_e keycode, * should be cleared the first time that kbd_get is called. * * Returned Value: - * 1 - Indicates the successful receipt of a special, "out-of-band" command + * 1 - Indicates the successful receipt of a special, "out-of-band" command. + * The returned value in pch is a value from enum kbd_getstate_s. * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. + * The returned value in pch is a simple byte of text or control data. * EOF - An error has getting the next character (reported by the stream). * Normally indicates the end of file. * ****************************************************************************/ int kbd_get(FAR struct lib_instream_s *stream, - FAR struct kget_getstate_s *state, FAR uint8_t *pch); + FAR struct kbd_getstate_s *state, FAR uint8_t *pch); #ifdef __cplusplus } diff --git a/nuttx/libc/misc/lib_kbddecode.c b/nuttx/libc/misc/lib_kbddecode.c index 046d570f9..cb57b5215 100644 --- a/nuttx/libc/misc/lib_kbddecode.c +++ b/nuttx/libc/misc/lib_kbddecode.c @@ -89,7 +89,7 @@ * ****************************************************************************/ -static int kbd_reget(FAR struct kget_getstate_s *state, FAR uint8_t *pch) +static int kbd_reget(FAR struct kbd_getstate_s *state, FAR uint8_t *pch) { /* Return the next character */ @@ -107,7 +107,7 @@ static int kbd_reget(FAR struct kget_getstate_s *state, FAR uint8_t *pch) * Name: kbd_get * * Description: - * Put one byte of data or special command from the driver provided input + * Get one byte of data or special command from the driver provided input * buffer. * * Input Parameters: @@ -120,15 +120,17 @@ static int kbd_reget(FAR struct kget_getstate_s *state, FAR uint8_t *pch) * should be cleared the first time that kbd_get is called. * * Returned Value: - * 1 - Indicates the successful receipt of a special, "out-of-band" command + * 1 - Indicates the successful receipt of a special, "out-of-band" command. + * The returned value in pch is a value from enum kbd_getstate_s. * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. + * The returned value in pch is a simple byte of text or control data. * EOF - An error has getting the next character (reported by the stream). * Normally indicates the end of file. * ****************************************************************************/ int kbd_get(FAR struct lib_instream_s *stream, - FAR struct kget_getstate_s *state, FAR uint8_t *pch) + FAR struct kbd_getstate_s *state, FAR uint8_t *pch) { int ch; diff --git a/nuttx/libc/misc/lib_kbdencode.c b/nuttx/libc/misc/lib_kbdencode.c index 80bf14777..40a8805b1 100644 --- a/nuttx/libc/misc/lib_kbdencode.c +++ b/nuttx/libc/misc/lib_kbdencode.c @@ -62,6 +62,9 @@ * Put one special, "out-of-band" command into the output stream. * * Input Parameters: + * keycode - The command to be added to the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. * * Returned Value: * None -- cgit v1.2.3 From 8ed19bb07d00a15e2f2c9893d57b1ef1261b2d23 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 26 Dec 2012 20:04:57 +0000 Subject: Add UG_2965SWEG01 driver from Darcy Gong; fix logic error in how waiters are reawakened in the USB HID keyboard driver git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5462 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/hidkbd/hidkbd_main.c | 1 + nuttx/ChangeLog | 6 + nuttx/configs/stm32f4discovery/README.txt | 2 +- nuttx/configs/stm32f4discovery/src/Makefile | 4 + .../src/stm32f4discovery-internal.h | 4 +- .../stm32f4discovery/src/up_ug2864hsweg01.c | 161 +++ nuttx/drivers/lcd/Make.defs | 4 + nuttx/drivers/lcd/ug-2864hsweg01.c | 1177 ++++++++++++++++++++ nuttx/drivers/usbhost/usbhost_hidkbd.c | 16 +- nuttx/include/nuttx/lcd/ug-2864hsweg01.h | 245 ++++ 10 files changed, 1613 insertions(+), 7 deletions(-) create mode 100644 nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c create mode 100644 nuttx/drivers/lcd/ug-2864hsweg01.c create mode 100644 nuttx/include/nuttx/lcd/ug-2864hsweg01.h diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c index bc1eebed0..8c9f6fa95 100644 --- a/apps/examples/hidkbd/hidkbd_main.c +++ b/apps/examples/hidkbd/hidkbd_main.c @@ -227,5 +227,6 @@ int hidkbd_main(int argc, char *argv[]) close(fd); } } + return 0; } diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7e1c538d7..a7087656a 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3826,4 +3826,10 @@ encode special function keys. * configs/olimex-lpc1766stk/hidkbd: This configuration has been converted to use the kconfig-frontends configuration tool. + * drivers/lcd/ug-2864hsweg01.c and include/nuttx/lcd/ug-2864hsweg01.h: + Driver for UG-2864HSWEG01 OLED contributed by Darcy Gong. + * configs/stm32f4discovery/src/up_ug2864hsweg01.c: Support for the + UG-2864HSWEG01 OLED for the STM32F4Discovery board. + * drivers/usbhost/usbhost_hidkbd.c: Correct a logic error in how + tasks waiting for read data are awakened. diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index d824668ce..37dae7b9e 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -711,7 +711,7 @@ pinout for the UG-2864AMBAG01 is specific to the theO.net display board that I am using: --------------------------+---------------------------------------------- - Connector CON10 J1: | STM32F4Discovery + Connector CON10 J1: | STM32F4Discovery --------------+-----------+---------------------------------------------- CON10 J1: | CON20 J2: | P1/P2: --------------+-----------+---------------------------------------------- diff --git a/nuttx/configs/stm32f4discovery/src/Makefile b/nuttx/configs/stm32f4discovery/src/Makefile index 68419e5d0..7ac27a7d0 100644 --- a/nuttx/configs/stm32f4discovery/src/Makefile +++ b/nuttx/configs/stm32f4discovery/src/Makefile @@ -100,6 +100,10 @@ ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) CSRCS += up_ug2864ambag01.c endif +ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) +CSRCS += up_ug2864hsweg01.c +endif + COBJS = $(CSRCS:.c=$(OBJEXT)) SRCS = $(ASRCS) $(CSRCS) diff --git a/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h b/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h index 00f17b58e..eae09594c 100644 --- a/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h +++ b/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h @@ -113,7 +113,7 @@ # define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) #endif -/* UG-2864AMBAG01 OLED Display: +/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display: * * --------------------------+---------------------------------------------- * Connector CON10 J1: | STM32F4Discovery @@ -135,7 +135,7 @@ * ------------------------------------------------------------------------- */ -#ifdef CONFIG_LCD_UG2864AMBAG01 +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) # define GPIO_OLED_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6) # define GPIO_OLED_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ diff --git a/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c b/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c new file mode 100644 index 000000000..4eee077a1 --- /dev/null +++ b/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * config/stm32f4discovery/src/up_ug2864hsweg01.c + * arch/arm/src/board/up_ug2864hsweg01.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f4discovery-internal.h" + +#ifdef CONFIG_LCD_UG2864HSWEG01 + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* The pin configurations here require that SPI1 is selected */ + +#ifndef CONFIG_STM32_SPI1 +# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" +#endif + +#ifndef CONFIG_SPI_CMDDATA +# error "The OLED driver requires CONFIG_SPI_CMDDATA in the configuration" +#endif + +/* Pin Configuration ********************************************************/ +/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display: + * + * --------------------------+---------------------------------------------- + * Connector CON10 J1: | STM32F4Discovery + * --------------+-----------+---------------------------------------------- + * CON10 J1: | CON20 J2: | P1/P2: + * --------------+-----------+---------------------------------------------- + * 1 3v3 | 3,4 3v3 | P2 3V + * 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection) + * 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection)(2) + * 7 A0 | 9 A0 | P2 PB8 (Arbitrary selection)(2) + * 9 LED+ (N/C) | ----- | ----- + * 2 5V Vcc | 1,2 Vcc | P2 5V + * 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1)) + * 6 SCLK | 19 D0/SCL | P1 PA5 (GPIO_SPI1_SCK == GPIO_SPI1_SCK_1 (2)) + * 8 LED- (N/C) | ----- | ------ + * 10 GND | 20 GND | P2 GND + * --------------+-----------+---------------------------------------------- + * (1) Required because of on-board MEMS + * (2) Note that the OLED CS and A0 are managed in the up_spi.c file. + * ------------------------------------------------------------------------- + */ + +/* Definitions in stm32f4discovery-internal.h */ + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_LCD +# define lcddbg(format, arg...) dbg(format, ##arg) +# define lcdvdbg(format, arg...) vdbg(format, ##arg) +#else +# define lcddbg(x...) +# define lcdvdbg(x...) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_nxdrvinit + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) +{ + FAR struct spi_dev_s *spi; + FAR struct lcd_dev_s *dev; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + (void)stm32_configgpio(GPIO_OLED_RESET); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_OLED_RESET, true); + + /* Get the SPI1 port interface */ + + spi = up_spiinitialize(1); + if (!spi) + { + lcddbg("Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ug2864hsweg01_initialize(spi, devno); + if (!dev) + { + lcddbg("Failed to bind SPI port 1 to OLED %d: %d\n", devno); + } + else + { + lcdvdbg("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + (void)dev->setpower(dev, CONFIG_LCD_MAXPOWER); + return dev; + } + } + + return NULL; +} +#endif /* CONFIG_LCD_UG2864AMBAG01 */ diff --git a/nuttx/drivers/lcd/Make.defs b/nuttx/drivers/lcd/Make.defs index 1b445b6a7..067f76f4e 100644 --- a/nuttx/drivers/lcd/Make.defs +++ b/nuttx/drivers/lcd/Make.defs @@ -51,6 +51,10 @@ ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) CSRCS += ug-2864ambag01.c endif +ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) + CSRCS += ug-2864hsweg01.c +endif + ifeq ($(CONFIG_LCD_UG9664HSWAG01),y) CSRCS += ug-9664hswag01.c endif diff --git a/nuttx/drivers/lcd/ug-2864hsweg01.c b/nuttx/drivers/lcd/ug-2864hsweg01.c new file mode 100644 index 000000000..9f9f99906 --- /dev/null +++ b/nuttx/drivers/lcd/ug-2864hsweg01.c @@ -0,0 +1,1177 @@ +/************************************************************************************** + * drivers/lcd/ug-2864hsweg01.c + * Driver for Univision UG-2864HSWEG01 OLED display (wih SSD1306 controller) in SPI + * mode + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * 1. Product Specification (Preliminary), Part Name: OEL Display Module, Part ID: + * UG-2864HSWEG01, Doc No: SAS1-9046-B, Univision Technology Inc. + * 2. SSD1306, 128 X 64 Dot Matrix OLED/PLED, Preliminary Segment/Common Driver with + * Controller, Solomon Systech + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************/ +/************************************************************************************** + * Device memory organization: + * + * +----------------------------+ + * | Column | + * --------+----+---+---+---+-...-+-----+ + * Page | 0 | 1 | 2 | 3 | ... | 127 | + * --------+----+---+---+---+-...-+-----+ + * Page 0 | D0 | X | | | | | + * | D1 | X | | | | | + * | D2 | X | | | | | + * | D3 | X | | | | | + * | D4 | X | | | | | + * | D5 | X | | | | | + * | D6 | X | | | | | + * | D7 | X | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 1 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 2 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 3 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 4 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 5 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 6 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * Page 7 | | | | | | | + * --------+----+---+---+---+-...-+-----+ + * + * -----------------------------------+--------------------------------------- + * Landscape Display: | Reverse Landscape Display: + * --------+-----------------------+ | --------+---------------------------+ + * | Column | | | Column | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 0 | 0 | 1 | 2 | | 127 | | Page 7 | 127 | 126 | 125 | | 0 | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 1 | V | | Page 6 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 2 | V | | Page 5 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 3 | V | | Page 4 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 4 | V | | Page 3 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 5 | V | | Page 2 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 6 | V | | Page 1 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * Page 7 | V | | Page 0 | ^ | + * --------+---+---+---+-...-+-----+ | --------+-----+-----+-----+-...-+---+ + * -----------------------------------+--------------------------------------- + * + * -----------------------------------+--------------------------------------- + * Portrait Display: | Reverse Portrait Display: + * -----------+---------------------+ | -----------+---------------------+ + * | Page | | | Page | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * Column 0 | 0 | 1 | 2 | | 7 | | Column 127 | 7 | 6 | 5 | | 0 | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * Column 1 | > > > > > | | Column 126 | | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * Column 2 | | | Column 125 | | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * ... | | | ... | | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * Column 127 | | | Column 0 | < < < < < | + * -----------+---+---+---+-...-+---+ | -----------+---+---+---+-...-+---+ + * -----------------------------------+---------------------------------------- + **************************************************************************************/ + +/************************************************************************************** + * Included Files + **************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_LCD_UG2864HSWEG01 + +/************************************************************************************** + * Pre-processor Definitions + **************************************************************************************/ +/* Configuration **********************************************************************/ +/* Limitations of the current configuration that I hope to fix someday */ + +#if CONFIG_UG2864HSWEG01_NINTERFACES != 1 +# warning "This implementation supports only a single OLED device" +# undef CONFIG_UG2864HSWEG01_NINTERFACES +# define CONFIG_UG2864HSWEG01_NINTERFACES 1 +#endif + +#if defined(CONFIG_LCD_PORTRAIT) || defined(CONFIG_LCD_RPORTRAIT) +# warning "No support yet for portrait modes" +# define CONFIG_LCD_LANDSCAPE 1 +# undef CONFIG_LCD_PORTRAIT +# undef CONFIG_LCD_RLANDSCAPE +# undef CONFIG_LCD_RPORTRAIT +#elif defined(CONFIG_LCD_RLANDSCAPE) +# warning "Reverse landscape mode is untested and, hence, probably buggy" +#endif + +/* SSD1306 Commands *******************************************************************/ + +#define SSD1306_SETCOLL(ad) (0x00 | ((ad) & 0x0f)) /* Set Lower Column Address: (00h - 0fh) */ +#define SSD1306_SETCOLH(ad) (0x10 | ((ad) & 0x0f)) /* Set Higher Column Address: (10h - 1fh) */ +#define SSD1306_STARTLINE(ln) (0x40 | ((ln) & 0x3f)) /* Set Display Start Line: (40h - 7fh) */ +#define SSD1306_CONTRAST_MODE (0x81) /* Set Contrast Control Register: (Double Bytes Command) */ +# define SSD1306_CONTRAST(c) (c) +#define SSD1306_SEGREMAP(m) (0xa0 | ((m) & 0x01)) /* Set Segment Re-map: (a0h - a1h) */ +# define SSD1306_REMAPRIGHT SSD1306_SEGREMAP(0) /* Right rotation */ +# define SSD1306_REMAPPLEFT SSD1306_SEGREMAP(1) /* Left rotation */ +#define SSD1306_EDISPOFFON(s) (0xa4 | ((s) & 0x01)) /* Set Entire Display OFF/ON: (a4h - a5h) */ +# define SSD1306_EDISPOFF SSD1306_EDISPOFFON(0) /* Display off */ +# define SSD1306_EDISPON SSD1306_EDISPOFFON(1) /* Display on */ +#define SSD1306_NORMREV(s) (0xa6 | ((s) & 0x01)) /* Set Normal/Reverse Display: (a6h -a7h) */ +# define SSD1306_NORMAL SSD1306_NORMREV(0) /* Normal display */ +# define SSD1306_REVERSE SSD1306_NORMREV(1) /* Reverse display */ +#define SSD1306_MRATIO_MODE (0xa8) /* Set Multiplex Ration: (Double Bytes Command) */ +# define SSD1306_MRATIO(d) ((d) & 0x3f) +#define SSD1306_DCDC_MODE (0xad) /* Set DC-DC OFF/ON: (Double Bytes Command) */ +# define SSD1306_DCDC_OFF (0x8a) +# define SSD1306_DCDC_ON (0x8b) + +#define SSD1306_DISPOFFON(s) (0xae | ((s) & 0x01)) /* Display OFF/ON: (aeh - afh) */ +# define SSD1306_DISPOFF SSD1306_DISPOFFON(0) /* Display off */ +# define SSD1306_DISPON SSD1306_DISPOFFON(1) /* Display on */ +#define SSD1306_PAGEADDR(a) (0xb0 | ((a) & 0x0f)) /* Set Page Address: (b0h - b7h) */ +#define SSD1306_SCANDIR(d) (0xc0 | ((d) & 0x08)) /* Set Common Output Scan Direction: (c0h - c8h) */ +# define SSD1306_SCANFROMCOM0 SSD1306_SCANDIR(0x00) /* Scan from COM[0] to COM[n-1]*/ +# define SSD1306_SCANTOCOM0 SSD1306_SCANDIR(0x08) /* Scan from COM[n-1] to COM[0] */ +#define SSD1306_DISPOFFS_MODE (0xd3) /* Set Display Offset: (Double Bytes Command) */ +# define SSD1306_DISPOFFS(o) ((o) & 0x3f) +#define SSD1306_CLKDIV_SET (0xd5) /* Set Display Clock Divide Ratio/Oscillator Frequency: (Double Bytes Command) */ +# define SSD1306_CLKDIV(f,d) ((((f) & 0x0f) << 4) | ((d) & 0x0f)) +#define SSD1306_CHRGPER_SET (0xd9) /* Set Dis-charge/Pre-charge Period: (Double Bytes Command) */ +# define SSD1306_CHRGPER(d,p) ((((d) & 0x0f) << 4) | ((p) & 0x0f)) +#define SSD1306_CMNPAD_CONFIG (0xda) /* Set Common pads hardware configuration: (Double Bytes Command) */ +# define SSD1306_CMNPAD(c) ((0x02) | ((c) & 0x10)) +#define SSD1306_VCOM_SET (0xdb) /* Set VCOM Deselect Level: (Double Bytes Command) */ +# define SSD1306_VCOM(v) (v) + +#define SSD1306_CHRPUMP_SET (0x8d) /* Charge Pump Setting */ +# define SSD1306_CHRPUMP_ON (0x14) +# define SSD1306_CHRPUMP_OFF (0x10) + +#define SSD1306_RMWSTART (0xe0) /* Read-Modify-Write: (e0h) */ +#define SSD1306_NOP (0xe3) /* NOP: (e3h) */ +#define SSD1306_END (0xee) /* End: (eeh) */ + +#define SSD1306_WRDATA(d) (d) /* Write Display Data */ +#define SSD1306_STATUS_BUSY (0x80) /* Read Status */ +#define SSD1306_STATUS_ONOFF (0x40) +#define SSD1306_RDDATA(d) (d) /* Read Display Data */ + +/* Color Properties *******************************************************************/ +/* Display Resolution + * + * The SSD1306 display controller can handle a resolution of 132x64. The UG-2864HSWEG01 + * on the base board is 128x64. + */ + +#define UG2864HSWEG01_DEV_XRES 128 /* Only 128 of 131 columns used */ +#define UG2864HSWEG01_DEV_YRES 64 /* 8 pages each 8 rows */ +#define UG2864HSWEG01_DEV_XOFFSET 2 /* Offset to logical column 0 */ +#define UG2864HSWEG01_DEV_PAGES 8 /* 8 pages */ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# define UG2864HSWEG01_XRES UG2864HSWEG01_DEV_XRES +# define UG2864HSWEG01_YRES UG2864HSWEG01_DEV_YRES +#else +# define UG2864HSWEG01_XRES UG2864HSWEG01_DEV_YRES +# define UG2864HSWEG01_YRES UG2864HSWEG01_DEV_XRES +#endif + +/* Color depth and format */ + +#define UG2864HSWEG01_BPP 1 +#define UG2864HSWEG01_COLORFMT FB_FMT_Y1 + +/* Bytes per logical row and actual device row */ + +#define UG2864HSWEG01_XSTRIDE (UG2864HSWEG01_XRES >> 3) +#define UG2864HSWEG01_YSTRIDE (UG2864HSWEG01_YRES >> 3) + +/* Default contrast */ + +#define UG2864HSWEG01_CONTRAST (128) + +/* The size of the shadow frame buffer or one row buffer. + * + * Frame buffer size: 128 columns x 64 rows / 8 bits-per-pixel + * Row size: 128 columns x 8 rows-per-page / 8 bits-per-pixel + */ + +#define UG2864HSWEG01_FBSIZE (UG2864HSWEG01_XSTRIDE * UG2864HSWEG01_YRES) +#define UG2864HSWEG01_ROWSIZE (UG2864HSWEG01_XSTRIDE) + +/* Bit helpers */ + +#define LS_BIT (1 << 0) +#define MS_BIT (1 << 7) + +/* Debug ******************************************************************************/ + +#ifdef CONFIG_DEBUG_LCD +# define lcddbg(format, arg...) dbg(format, ##arg) +# define lcdvdbg(format, arg...) vdbg(format, ##arg) +#else +# define lcddbg(x...) +# define lcdvdbg(x...) +#endif + +/************************************************************************************** + * Private Type Definition + **************************************************************************************/ + +/* This structure describes the state of this driver */ + +struct ug2864hsweg01_dev_s +{ + struct lcd_dev_s dev; /* Publically visible device structure */ + + /* Private LCD-specific information follows */ + + FAR struct spi_dev_s *spi; /* Cached SPI device reference */ + uint8_t contrast; /* Current contrast setting */ + bool on; /* true: display is on */ + + + /* The SSD1306 does not support reading from the display memory in SPI mode. + * Since there is 1 BPP and access is byte-by-byte, it is necessary to keep + * a shadow copy of the framebuffer memory. At 128x64, this amounts to 1KB. + */ + + uint8_t fb[UG2864HSWEG01_FBSIZE]; +}; + +/************************************************************************************** + * Private Function Protototypes + **************************************************************************************/ + +/* Low-level SPI helpers */ + +#ifdef CONFIG_SPI_OWNBUS +static inline void ug2864hsweg01_configspi(FAR struct spi_dev_s *spi); +# define ug2864hsweg01_lock(spi) +# define ug2864hsweg01_unlock(spi) +#else +# define ug2864hsweg01_configspi(spi) +static void ug2864hsweg01_lock(FAR struct spi_dev_s *spi); +static void ug2864hsweg01_unlock(FAR struct spi_dev_s *spi); +#endif + +/* LCD Data Transfer Methods */ + +static int ug2864hsweg01_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int ug2864hsweg01_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, + size_t npixels); + +/* LCD Configuration */ + +static int ug2864hsweg01_getvideoinfo(FAR struct lcd_dev_s *dev, + FAR struct fb_videoinfo_s *vinfo); +static int ug2864hsweg01_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int ug2864hsweg01_getpower(struct lcd_dev_s *dev); +static int ug2864hsweg01_setpower(struct lcd_dev_s *dev, int power); +static int ug2864hsweg01_getcontrast(struct lcd_dev_s *dev); +static int ug2864hsweg01_setcontrast(struct lcd_dev_s *dev, unsigned int contrast); + +/************************************************************************************** + * Private Data + **************************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint8_t g_runbuffer[UG2864HSWEG01_ROWSIZE]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = UG2864HSWEG01_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = UG2864HSWEG01_XRES, /* Horizontal resolution in pixel columns */ + .yres = UG2864HSWEG01_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = ug2864hsweg01_putrun, /* Put a run into LCD memory */ + .getrun = ug2864hsweg01_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ + .bpp = UG2864HSWEG01_BPP, /* Bits-per-pixel */ +}; + +/* This is the OLED driver instance (only a single device is supported for now) */ + +static struct ug2864hsweg01_dev_s g_oleddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = ug2864hsweg01_getvideoinfo, + .getplaneinfo = ug2864hsweg01_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = ug2864hsweg01_getpower, + .setpower = ug2864hsweg01_setpower, + .getcontrast = ug2864hsweg01_getcontrast, + .setcontrast = ug2864hsweg01_setcontrast, + }, +}; + +/************************************************************************************** + * Private Functions + **************************************************************************************/ + +/************************************************************************************** + * Name: ug2864hsweg01_configspi + * + * Description: + * Configure the SPI for use with the UG-2864HSWEG01 + * + * Input Parameters: + * spi - Reference to the SPI driver structure + * + * Returned Value: + * None + * + * Assumptions: + * + **************************************************************************************/ + +#ifdef CONFIG_SPI_OWNBUS +static inline void ug2864hsweg01_configspi(FAR struct spi_dev_s *spi) +{ + lcdvdbg("Mode: %d Bits: 8 Frequency: %d\n", + CONFIG_UG2864HSWEG01_SPIMODE, CONFIG_UG2864HSWEG01_FREQUENCY); + + /* Configure SPI for the UG-2864HSWEG01. But only if we own the SPI bus. Otherwise, + * don't bother because it might change. + */ + + SPI_SETMODE(spi, CONFIG_UG2864HSWEG01_SPIMODE); + SPI_SETBITS(spi, 8); + SPI_SETFREQUENCY(spi, CONFIG_UG2864HSWEG01_FREQUENCY) +} +#endif + +/************************************************************************************** + * Name: ug2864hsweg01_lock + * + * Description: + * Select the SPI, locking and re-configuring if necessary + * + * Input Parameters: + * spi - Reference to the SPI driver structure + * + * Returned Value: + * None + * + * Assumptions: + * + **************************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static inline void ug2864hsweg01_lock(FAR struct spi_dev_s *spi) +{ + /* Lock the SPI bus if there are multiple devices competing for the SPI bus. */ + + SPI_LOCK(spi, true); + + /* Now make sure that the SPI bus is configured for the UG-2864HSWEG01 (it + * might have gotten configured for a different device while unlocked) + */ + + SPI_SETMODE(spi, CONFIG_UG2864HSWEG01_SPIMODE); + SPI_SETBITS(spi, 8); + SPI_SETFREQUENCY(spi, CONFIG_UG2864HSWEG01_FREQUENCY); +} +#endif + +/************************************************************************************** + * Name: ug2864hsweg01_unlock + * + * Description: + * De-select the SPI + * + * Input Parameters: + * spi - Reference to the SPI driver structure + * + * Returned Value: + * None + * + * Assumptions: + * + **************************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static inline void ug2864hsweg01_unlock(FAR struct spi_dev_s *spi) +{ + /* De-select UG-2864HSWEG01 chip and relinquish the SPI bus. */ + + SPI_LOCK(spi, false); +} +#endif + +/************************************************************************************** + * Name: ug2864hsweg01_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD. + * + * Input Parameters: + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + **************************************************************************************/ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +static int ug2864hsweg01_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, + size_t npixels) +{ + /* Because of this line of code, we will only be able to support a single UG device */ + + FAR struct ug2864hsweg01_dev_s *priv = (FAR struct ug2864hsweg01_dev_s *)&g_oleddev; + FAR uint8_t *fbptr; + FAR uint8_t *ptr; + uint8_t devcol; + uint8_t fbmask; + uint8_t page; + uint8_t usrmask; + int pixlen; + uint8_t i; + + lcdvdbg("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer); + + /* Clip the run to the display */ + + pixlen = npixels; + if ((unsigned int)col + (unsigned int)pixlen > (unsigned int)UG2864HSWEG01_XRES) + { + pixlen = (int)UG2864HSWEG01_XRES - (int)col; + } + + /* Verify that some portion of the run remains on the display */ + + if (pixlen <= 0 || row > UG2864HSWEG01_YRES) + { + return OK; + } + + /* Perform coordinate conversion for reverse landscape mode */ + +#ifdef CONFIG_LCD_RLANDSCAPE + row = (UG2864HSWEG01_YRES-1) - row; + col = (UG2864HSWEG01_XRES-1) - col; +#endif + + /* Get the page number. The range of 64 lines is divided up into eight + * pages of 8 lines each. + */ + + page = row >> 3; + + /* Update the shadow frame buffer memory. First determine the pixel + * position in the frame buffer memory. Pixels are organized like + * this: + * + * --------+---+---+---+---+-...-+-----+ + * Segment | 0 | 1 | 2 | 3 | ... | 131 | + * --------+---+---+---+---+-...-+-----+ + * D0 | | X | | | | | + * D1 | | X | | | | | + * D2 | | X | | | | | + * D3 | | X | | | | | + * D4 | | X | | | | | + * D5 | | X | | | | | + * D6 | | X | | | | | + * D7 | | X | | | | | + * --------+---+---+---+---+-...-+-----+ + * + * So, in order to draw a white, horizontal line, at row 45. we + * would have to modify all of the bytes in page 45/8 = 5. We + * would have to set bit 45%8 = 5 in every byte in the page. + */ + + fbmask = 1 << (row & 7); + fbptr = &priv->fb[page * UG2864HSWEG01_XRES + col]; +#ifdef CONFIG_LCD_RLANDSCAPE + ptr = fbptr + pixlen - 1; +#else + ptr = fbptr; +#endif +#ifdef CONFIG_NX_PACKEDMSFIRST + usrmask = MS_BIT; +#else + usrmask = LS_BIT; +#endif + + for (i = 0; i < pixlen; i++) + { + /* Set or clear the corresponding bit */ + +#ifdef CONFIG_LCD_RLANDSCAPE + if ((*buffer & usrmask) != 0) + { + *ptr-- |= fbmask; + } + else + { + *ptr-- &= ~fbmask; + } +#else + if ((*buffer & usrmask) != 0) + { + *ptr++ |= fbmask; + } + else + { + *ptr++ &= ~fbmask; + } +#endif + + /* Inc/Decrement to the next source pixel */ + +#ifdef CONFIG_NX_PACKEDMSFIRST + if (usrmask == LS_BIT) + { + buffer++; + usrmask = MS_BIT; + } + else + { + usrmask >>= 1; + } +#else + if (usrmask == MS_BIT) + { + buffer++; + usrmask = LS_BIT; + } + else + { + usrmask <<= 1; + } +#endif + } + + /* Offset the column position to account for smaller horizontal + * display range. + */ + + devcol = col + UG2864HSWEG01_DEV_XOFFSET; + + /* Lock and select device */ + + ug2864hsweg01_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, true); + + /* Select command transfer */ + + SPI_CMDDATA(priv->spi, SPIDEV_DISPLAY, true); + + /* Set the starting position for the run */ + /* Set the column address to the XOFFSET value */ + + SPI_SEND(priv->spi, SSD1306_SETCOLL(devcol & 0x0f)); + SPI_SEND(priv->spi, SSD1306_SETCOLH(devcol >> 4)); + + /* Set the page address */ + + SPI_SEND(priv->spi, SSD1306_PAGEADDR(page)); + + /* Select data transfer */ + + SPI_CMDDATA(priv->spi, SPIDEV_DISPLAY, false); + + /* Then transfer all of the data */ + + (void)SPI_SNDBLOCK(priv->spi, fbptr, pixlen); + + /* De-select and unlock the device */ + + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, false); + ug2864hsweg01_unlock(priv->spi); + return OK; +} +#else +# error "Configuration not implemented" +#endif + +/************************************************************************************** + * Name: ug2864hsweg01_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * Description: + * This method can be used to write a partial raster line to the LCD. + * + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + **************************************************************************************/ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +static int ug2864hsweg01_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, + size_t npixels) +{ + /* Because of this line of code, we will only be able to support a single UG device */ + + FAR struct ug2864hsweg01_dev_s *priv = &g_oleddev; + FAR uint8_t *fbptr; + uint8_t page; + uint8_t fbmask; + uint8_t usrmask; + int pixlen; + uint8_t i; + + lcdvdbg("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer); + + /* Clip the run to the display */ + + pixlen = npixels; + if ((unsigned int)col + (unsigned int)pixlen > (unsigned int)UG2864HSWEG01_XRES) + { + pixlen = (int)UG2864HSWEG01_XRES - (int)col; + } + + /* Verify that some portion of the run is actually the display */ + + if (pixlen <= 0 || row > UG2864HSWEG01_YRES) + { + return -EINVAL; + } + + /* Perform coordinate conversion for reverse landscape mode */ + +#ifdef CONFIG_LCD_RLANDSCAPE + row = (UG2864HSWEG01_YRES-1) - row; + col = (UG2864HSWEG01_XRES-1) - col; +#endif + + /* Then transfer the display data from the shadow frame buffer memory */ + /* Get the page number. The range of 64 lines is divided up into eight + * pages of 8 lines each. + */ + + page = row >> 3; + + /* Update the shadow frame buffer memory. First determine the pixel + * position in the frame buffer memory. Pixels are organized like + * this: + * + * --------+---+---+---+---+-...-+-----+ + * Segment | 0 | 1 | 2 | 3 | ... | 131 | + * --------+---+---+---+---+-...-+-----+ + * D0 | | X | | | | | + * D1 | | X | | | | | + * D2 | | X | | | | | + * D3 | | X | | | | | + * D4 | | X | | | | | + * D5 | | X | | | | | + * D6 | | X | | | | | + * D7 | | X | | | | | + * --------+---+---+---+---+-...-+-----+ + * + * So, in order to draw a white, horizontal line, at row 45. we + * would have to modify all of the bytes in page 45/8 = 5. We + * would have to set bit 45%8 = 5 in every byte in the page. + */ + + fbmask = 1 << (row & 7); +#ifdef CONFIG_LCD_RLANDSCAPE + fbptr = &priv->fb[page * (UG2864HSWEG01_XRES-1) + col + pixlen]; +#else + fbptr = &priv->fb[page * UG2864HSWEG01_XRES + col]; +#endif +#ifdef CONFIG_NX_PACKEDMSFIRST + usrmask = MS_BIT; +#else + usrmask = LS_BIT; +#endif + + *buffer = 0; + for (i = 0; i < pixlen; i++) + { + /* Set or clear the corresponding bit */ + +#ifdef CONFIG_LCD_RLANDSCAPE + uint8_t byte = *fbptr--; +#else + uint8_t byte = *fbptr++; +#endif + if ((byte & fbmask) != 0) + { + *buffer |= usrmask; + } + + /* Inc/Decrement to the next destination pixel. Hmmmm. It looks like + * this logic could write past the end of the user buffer. Revisit + * this! + */ + +#ifdef CONFIG_NX_PACKEDMSFIRST + if (usrmask == LS_BIT) + { + buffer++; + *buffer = 0; + usrmask = MS_BIT; + } + else + { + usrmask >>= 1; + } +#else + if (usrmask == MS_BIT) + { + buffer++; + *buffer = 0; + usrmask = LS_BIT; + } + else + { + usrmask <<= 1; + } +#endif + } + + return OK; +} +#else +# error "Configuration not implemented" +#endif + +/************************************************************************************** + * Name: ug2864hsweg01_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + **************************************************************************************/ + +static int ug2864hsweg01_getvideoinfo(FAR struct lcd_dev_s *dev, + FAR struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + lcdvdbg("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/************************************************************************************** + * Name: ug2864hsweg01_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + **************************************************************************************/ + +static int ug2864hsweg01_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(pinfo && planeno == 0); + lcdvdbg("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + return OK; +} + +/************************************************************************************** + * Name: ug2864hsweg01_getpower + * + * Description: + * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on. On + * backlit LCDs, this setting may correspond to the backlight setting. + * + **************************************************************************************/ + +static int ug2864hsweg01_getpower(FAR struct lcd_dev_s *dev) +{ + FAR struct ug2864hsweg01_dev_s *priv = (FAR struct ug2864hsweg01_dev_s *)dev; + DEBUGASSERT(priv); + + lcdvdbg("power: %s\n", priv->on ? "ON" : "OFF"); + return priv->on ? CONFIG_LCD_MAXPOWER : 0; +} + +/************************************************************************************** + * Name: ug2864hsweg01_setpower + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On + * backlit LCDs, this setting may correspond to the backlight setting. + * + **************************************************************************************/ + +static int ug2864hsweg01_setpower(struct lcd_dev_s *dev, int power) +{ + struct ug2864hsweg01_dev_s *priv = (struct ug2864hsweg01_dev_s *)dev; + DEBUGASSERT(priv && (unsigned)power <= CONFIG_LCD_MAXPOWER && priv->spi); + + lcdvdbg("power: %d [%d]\n", power, priv->on ? CONFIG_LCD_MAXPOWER : 0); + + /* Lock and select device */ + + ug2864hsweg01_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, true); + + if (power <= 0) + { + /* Turn the display off */ + + (void)SPI_SEND(priv->spi, SSD1306_DISPOFF); + priv->on = false; + } + else + { + /* Turn the display on */ + + (void)SPI_SEND(priv->spi, SSD1306_DISPON); /* Display on, dim mode */ + priv->on = true; + } + + /* De-select and unlock the device */ + + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, false); + ug2864hsweg01_unlock(priv->spi); + return OK; +} + +/************************************************************************************** + * Name: ug2864hsweg01_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + **************************************************************************************/ + +static int ug2864hsweg01_getcontrast(struct lcd_dev_s *dev) +{ + struct ug2864hsweg01_dev_s *priv = (struct ug2864hsweg01_dev_s *)dev; + DEBUGASSERT(priv); + + lcdvdbg("contrast: %d\n", priv->contrast); + return priv->contrast; +} + +/************************************************************************************** + * Name: ug2864hsweg01_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + **************************************************************************************/ + +static int ug2864hsweg01_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + struct ug2864hsweg01_dev_s *priv = (struct ug2864hsweg01_dev_s *)dev; + unsigned int scaled; + + lcdvdbg("contrast: %d\n", contrast); + DEBUGASSERT(priv); + + /* Verify the contrast value */ + +#ifdef CONFIG_DEBUG + if (contrast > CONFIG_LCD_MAXCONTRAST) + { + return -EINVAL; + } +#endif + + /* Scale contrast: newcontrast = 255 * contrast / CONFIG_LCD_MAXCONTRAST + * Where contrast is in the range {1,255} + */ + +#if CONFIG_LCD_MAXCONTRAST != 255 + scaled = ((contrast << 8) - 1) / CONFIG_LCD_MAXCONTRAST; +#else + scaled = contrast; +#endif + + /* Lock and select device */ + + ug2864hsweg01_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, true); + + /* Select command transfer */ + + SPI_CMDDATA(priv->spi, SPIDEV_DISPLAY, true); + + /* Set the contrast */ + + (void)SPI_SEND(priv->spi, SSD1306_CONTRAST_MODE); /* Set contrast control register */ + (void)SPI_SEND(priv->spi, SSD1306_CONTRAST(scaled)); /* Data 1: Set 1 of 256 contrast steps */ + priv->contrast = contrast; + + /* De-select and unlock the device */ + + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, false); + ug2864hsweg01_unlock(priv->spi); + return OK; +} + +/************************************************************************************** + * Public Functions + **************************************************************************************/ + +/************************************************************************************** + * Name: ug2864hsweg01_initialize + * + * Description: + * Initialize the UG-2864HSWEG01 video hardware. The initial state of the + * OLED is fully initialized, display memory cleared, and the OLED ready + * to use, but with the power setting at 0 (full off == sleep mode). + * + * Input Parameters: + * + * spi - A reference to the SPI driver instance. + * devno - A value in the range of 0 through CONFIG_UG2864HSWEG01_NINTERFACES-1. + * This allows support for multiple OLED devices. + * + * Returned Value: + * + * On success, this function returns a reference to the LCD object for + * the specified OLED. NULL is returned on any failure. + * + **************************************************************************************/ + +FAR struct lcd_dev_s *ug2864hsweg01_initialize(FAR struct spi_dev_s *spi, unsigned int devno) +{ + FAR struct ug2864hsweg01_dev_s *priv = &g_oleddev; + + lcdvdbg("Initializing\n"); + DEBUGASSERT(spi && devno == 0); + + /* Save the reference to the SPI device */ + + priv->spi = spi; + + /* Configure the SPI */ + + ug2864hsweg01_configspi(spi) + + /* Lock and select device */ + + ug2864hsweg01_lock(priv->spi); + SPI_SELECT(spi, SPIDEV_DISPLAY, true); + + /* Select command transfer */ + + SPI_CMDDATA(spi, SPIDEV_DISPLAY, true); + + /* Configure the device */ + + SPI_SEND(spi, SSD1306_DISPOFF); /* Display off 0xAE*/ + SPI_SEND(spi, SSD1306_SETCOLL(0)); /* Set lower column address 0x00 */ + SPI_SEND(spi, SSD1306_SETCOLH(0)); /* Set higher column address 0x10 */ + SPI_SEND(spi, SSD1306_STARTLINE(0)); /* Set display start line 0x40*/ + SPI_SEND(spi, SSD1306_PAGEADDR(0)); /* Set page address [¿ÉºöÂÔ] */ + SPI_SEND(spi, SSD1306_CONTRAST_MODE); /* Contrast control 0x81*/ + SPI_SEND(spi ,SSD1306_CONTRAST(UG2864HSWEG01_CONTRAST)); /* Default contrast 0xCF */ + SPI_SEND(spi, SSD1306_REMAPPLEFT); /* Set segment remap left 95 to 0 | 0xA1*/ + SPI_SEND(spi, SSD1306_EDISPOFF); /* Normal display :off 0xA4 [¶à³öµÄÒ»ÐÐ] */ + SPI_SEND(spi, SSD1306_NORMAL); /* Normal (un-reversed) display mode 0xA6 */ + SPI_SEND(spi, SSD1306_MRATIO_MODE); /* Multiplex ratio 0xA8*/ + SPI_SEND(spi, SSD1306_MRATIO(0x3f)); /* Duty = 1/64 */ + SPI_SEND(spi, SSD1306_SCANTOCOM0); /* Com scan direction: Scan from COM[n-1] to COM[0] [¿ÉºöÂÔ] */ + SPI_SEND(spi, SSD1306_DISPOFFS_MODE); /* Set display offset 0xD3 */ + SPI_SEND(spi, SSD1306_DISPOFFS(0)); + SPI_SEND(spi, SSD1306_CLKDIV_SET); /* Set clock divider 0xD5*/ + SPI_SEND(spi, SSD1306_CLKDIV(8,0)); /* 0x80 ? ¼ì²é ĬÈÏ0,0*/ + + SPI_SEND(spi, SSD1306_CHRGPER_SET); /* ++Set pre-charge period 0xD9*/ + SPI_SEND(spi, SSD1306_CHRGPER(0x0f,1)); /* 0xf1 or 0x22£¨Ôöǿģʽ£¿£© */ + + SPI_SEND(spi, SSD1306_CMNPAD_CONFIG); /* Set common pads / set com pins hardware configuration 0xDA*/ + SPI_SEND(spi, SSD1306_CMNPAD(0x12)); /* 0x12 ? ¼ì²é ĬÈÏ 0x10 */ + + SPI_SEND(spi, SSD1306_VCOM_SET); /* set vcomh 0xDB*/ + SPI_SEND(spi, SSD1306_VCOM(0x40)); + + SPI_SEND(spi, SSD1306_CHRPUMP_SET); /* ++Set Charge Pump enable/disable 0x8D Ôö¼ÓµÄ*/ + SPI_SEND(spi, SSD1306_CHRPUMP_ON); /* 0x14 */ + + //SPI_SEND(spi, SSD1306_DCDC_MODE); /* DC/DC control mode: on */ + //SPI_SEND(spi, SSD1306_DCDC_ON); + + SPI_SEND(spi, SSD1306_DISPON); /* display ON 0xAF */ + + /* De-select and unlock the device */ + + SPI_SELECT(spi, SPIDEV_DISPLAY, false); + ug2864hsweg01_unlock(priv->spi); + + /* Clear the display */ + + up_mdelay(100); + ug2864hsweg01_fill(&priv->dev, UG_Y1_BLACK); + return &priv->dev; +} + +/************************************************************************************** + * Name: ug2864hsweg01_fill + * + * Description: + * This non-standard method can be used to clear the entire display by writing one + * color to the display. This is much faster than writing a series of runs. + * + * Input Parameters: + * priv - Reference to private driver structure + * + * Assumptions: + * Caller has selected the OLED section. + * + **************************************************************************************/ + +void ug2864hsweg01_fill(FAR struct lcd_dev_s *dev, uint8_t color) +{ + FAR struct ug2864hsweg01_dev_s *priv = &g_oleddev; + unsigned int page; + + /* Make an 8-bit version of the selected color */ + + if (color & 1) + { + color = 0xff; + } + else + { + color = 0; + } + + /* Initialize the framebuffer */ + + memset(priv->fb, color, UG2864HSWEG01_FBSIZE); + + /* Lock and select device */ + + ug2864hsweg01_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, true); + + /* Visit each page */ + + for (page = 0; page < UG2864HSWEG01_DEV_PAGES; page++) + { + /* Select command transfer */ + + SPI_CMDDATA(priv->spi, SPIDEV_DISPLAY, true); + + /* Set the column address to the XOFFSET value */ + + SPI_SEND(priv->spi, SSD1306_SETCOLL(UG2864HSWEG01_DEV_XOFFSET)); + SPI_SEND(priv->spi, SSD1306_SETCOLH(0)); + + /* Set the page address */ + + SPI_SEND(priv->spi, SSD1306_PAGEADDR(page)); + + /* Select data transfer */ + + SPI_CMDDATA(priv->spi, SPIDEV_DISPLAY, false); + + /* Transfer one page of the selected color */ + + (void)SPI_SNDBLOCK(priv->spi, &priv->fb[page * UG2864HSWEG01_XRES], + UG2864HSWEG01_XRES); + } + + /* De-select and unlock the device */ + + SPI_SELECT(priv->spi, SPIDEV_DISPLAY, false); + ug2864hsweg01_unlock(priv->spi); +} + +#endif /* CONFIG_LCD_UG2864HSWEG01 */ diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c index e0c4680eb..5022793ca 100644 --- a/nuttx/drivers/usbhost/usbhost_hidkbd.c +++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c @@ -1027,6 +1027,7 @@ static int usbhost_kbdpoll(int argc, char *argv[]) /* Loop here until the device is disconnected */ uvdbg("Entering poll loop\n"); + while (!priv->disconnected) { /* Make sure that we have exclusive access to the private data @@ -1169,10 +1170,10 @@ static int usbhost_kbdpoll(int argc, char *argv[]) #endif } - /* Did we just transition from no data available to data available? */ + /* Is there data available? */ newstate = (priv->headndx == priv->tailndx); - if (empty && !newstate) + if (!newstate) { /* Yes.. Is there a thread waiting for keyboard data now? */ @@ -1184,9 +1185,15 @@ static int usbhost_kbdpoll(int argc, char *argv[]) priv->waiting = false; } - /* And wake up any threads waiting for the POLLIN event */ + /* Did we just transition from no data available to data + * available? If so, wake up any threads waiting for the + * POLLIN event. + */ - usbhost_pollnotify(priv); + if (empty) + { + usbhost_pollnotify(priv); + } } empty = newstate; @@ -2146,6 +2153,7 @@ static ssize_t usbhost_read(FAR struct file *filep, FAR char *buffer, size_t len /* Wait for data to be available */ uvdbg("Waiting...\n"); + priv->waiting = true; usbhost_givesem(&priv->exclsem); usbhost_takesem(&priv->waitsem); diff --git a/nuttx/include/nuttx/lcd/ug-2864hsweg01.h b/nuttx/include/nuttx/lcd/ug-2864hsweg01.h new file mode 100644 index 000000000..bbefd39be --- /dev/null +++ b/nuttx/include/nuttx/lcd/ug-2864hsweg01.h @@ -0,0 +1,245 @@ +/************************************************************************************** + * include/nuttx/lcd/ug-2864hsweg01.h + * Driver for Univision UG-2864HSWEG01 OLED display (wih SSD1306 controller) in SPI + * mode + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * 1. Product Specification (Preliminary), Part Name: OEL Display Module, Part ID: + * UG-2864HSWEG01, Doc No: SAS1-9046-B, Univision Technology Inc. + * 2. SSD1306, 128 X 64 Dot Matrix OLED/PLED, Preliminary Segment/Common Driver with + * Controller, Solomon Systech + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************/ + +#ifndef __INCLUDE_NUTTX_UG_8264HSWEG01_H +#define __INCLUDE_NUTTX_UG_8264HSWEG01_H + +/************************************************************************************** + * Included Files + **************************************************************************************/ + +#include + +#include + +#include + +#ifdef CONFIG_LCD_UG2864HSWEG01 + +/************************************************************************************** + * Pre-processor Definitions + **************************************************************************************/ +/* Configuration **********************************************************************/ +/* UG-2864HSWEG01 Configuration Settings: + * + * CONFIG_UG2864HSWEG01_SPIMODE - Controls the SPI mode + * CONFIG_UG2864HSWEG01_FREQUENCY - Define to use a different bus frequency + * CONFIG_UG2864HSWEG01_NINTERFACES - Specifies the number of physical UG-2864HSWEG01 + * devices that will be supported. + * + * Required LCD driver settings: + * + * CONFIG_LCD_UG28HSWEG01 - Enable UG-2864HSWEG01 support + * CONFIG_LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + * CONFIG_LCD_MAXPOWER must be 1 + * + * Option LCD driver settings: + * CONFIG_LCD_LANDSCAPE, CONFIG_LCD_PORTRAIT, CONFIG_LCD_RLANDSCAPE, and + * CONFIG_LCD_RPORTRAIT - Display orientation. + * + * Required SPI driver settings: + * CONFIG_SPI_CMDDATA - Include support for cmd/data selection. + */ + +/* SPI Interface + * + * "The serial interface consists of serial clock SCL, serial data SI, A0 and + * CS . SI is shifted into an 8-bit shift register on every rising edge of + * SCL in the order of D7, D6, … and D0. A0 is sampled on every eighth clock + * and the data byte in the shift register is written to the display data RAM + * or command register in the same clock." + * + * MODE 3: + * Clock polarity: High (CPOL=1) + * Clock phase: Sample on trailing (rising edge) (CPHA 1) + */ + +#ifndef CONFIG_UG2864HSWEG01_SPIMODE +# define CONFIG_UG2864HSWEG01_SPIMODE SPIDEV_MODE3 +#endif + +/* "This module determines whether the input data is interpreted as data or + * command. When A0 = “H”, the inputs at D7 - D0 are interpreted as data and be + * written to display RAM. When A0 = “L”, the inputs at D7 - D0 are interpreted + * as command, they will be decoded and be written to the corresponding command + * registers. + */ + +#ifndef CONFIG_SPI_CMDDATA +# error "CONFIG_SPI_CMDDATA must be defined in your NuttX configuration" +#endif + +/* CONFIG_UG2864HSWEG01_NINTERFACES determines the number of physical interfaces + * that will be supported. + */ + +#ifndef CONFIG_UG2864HSWEG01_NINTERFACES +# define CONFIG_UG2864HSWEG01_NINTERFACES 1 +#endif + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 255 +#endif + +#if CONFIG_LCD_MAXCONTRAST <= 0|| CONFIG_LCD_MAXCONTRAST > 255 +# error "CONFIG_LCD_MAXCONTRAST exceeds supported maximum" +#endif + +#if CONFIG_LCD_MAXCONTRAST < 255 +# warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255" +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) +# define CONFIG_LCD_MAXPOWER 1 +#endif + +#if CONFIG_LCD_MAXPOWER != 1 +# warning "CONFIG_LCD_MAXPOWER exceeds supported maximum" +# undef CONFIG_LCD_MAXPOWER +# define CONFIG_LCD_MAXPOWER 1 +#endif + +/* Color is 1bpp monochrome with leftmost column contained in bits 0 */ + +#ifdef CONFIG_NX_DISABLE_1BPP +# warning "1 bit-per-pixel support needed" +#endif + +/* Orientation */ + +#if defined(CONFIG_LCD_LANDSCAPE) +# undef CONFIG_LCD_PORTRAIT +# undef CONFIG_LCD_RLANDSCAPE +# undef CONFIG_LCD_RPORTRAIT +#elif defined(CONFIG_LCD_PORTRAIT) +# undef CONFIG_LCD_LANDSCAPE +# undef CONFIG_LCD_RLANDSCAPE +# undef CONFIG_LCD_RPORTRAIT +#elif defined(CONFIG_LCD_RLANDSCAPE) +# undef CONFIG_LCD_LANDSCAPE +# undef CONFIG_LCD_PORTRAIT +# undef CONFIG_LCD_RPORTRAIT +#elif defined(CONFIG_LCD_RPORTRAIT) +# undef CONFIG_LCD_LANDSCAPE +# undef CONFIG_LCD_PORTRAIT +# undef CONFIG_LCD_RLANDSCAPE +#else +# define CONFIG_LCD_LANDSCAPE 1 +# warning "Assuming landscape orientation" +#endif + +/* Some important "colors" */ + +#define UG_Y1_BLACK 0 +#define UG_Y1_WHITE 1 + +/************************************************************************************** + * Public Types + **************************************************************************************/ + +/************************************************************************************** + * Public Data + **************************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************** + * Public Function Prototypes + **************************************************************************************/ + +/************************************************************************************** + * Name: ug2864hsweg01_initialize + * + * Description: + * Initialize the UG-2864HSWEG01 video hardware. The initial state of the + * OLED is fully initialized, display memory cleared, and the OLED ready + * to use, but with the power setting at 0 (full off == sleep mode). + * + * Input Parameters: + * + * spi - A reference to the SPI driver instance. + * devno - A value in the range of 0 through CONFIG_UG2864HSWEG01_NINTERFACES-1. + * This allows support for multiple OLED devices. + * + * Returned Value: + * + * On success, this function returns a reference to the LCD object for + * the specified OLED. NULL is returned on any failure. + * + **************************************************************************************/ + +struct lcd_dev_s; /* See include/nuttx/lcd/lcd.h */ +struct spi_dev_s; /* See include/nuttx/spi.h */ +FAR struct lcd_dev_s *ug2864hsweg01_initialize(FAR struct spi_dev_s *spi, + unsigned int devno); + +/************************************************************************************************ + * Name: ug2864hsweg01_fill + * + * Description: + * This non-standard method can be used to clear the entire display by writing one + * color to the display. This is much faster than writing a series of runs. + * + * Input Parameters: + * priv - Reference to private driver structure + * + * Assumptions: + * Caller has selected the OLED section. + * + **************************************************************************************/ + +void ug2864hsweg01_fill(FAR struct lcd_dev_s *dev, uint8_t color); + +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_LCD_UG2864HSWEG01 */ +#endif /* __INCLUDE_NUTTX_UG_8264HSWEG01_H */ -- cgit v1.2.3 From 88bccb641eccf8ca1a91ab0583976a211deb1ed5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 26 Dec 2012 21:37:50 +0000 Subject: Verified USB HID KBD driver encoding of special characters; apps/examples/hidkbd now decodes encoded keyboar characters. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5463 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/examples/README.txt | 18 +++- apps/examples/hidkbd/Kconfig | 31 +++++++ apps/examples/hidkbd/hidkbd_main.c | 106 ++++++++++++++++++++++- nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig | 20 ++++- nuttx/drivers/usbhost/Kconfig | 4 +- nuttx/drivers/usbhost/usbhost_hidkbd.c | 34 +++++--- nuttx/include/nuttx/input/kbd_codec.h | 5 +- nuttx/libc/Kconfig | 28 ++++++ nuttx/libc/math/Kconfig | 2 +- nuttx/libc/misc/Make.defs | 8 +- 11 files changed, 234 insertions(+), 24 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index ea1b247f5..d156b1065 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -453,4 +453,6 @@ in place early in the dependency generation phase to avoid warnings. It is not important if they are only stubbed out header files at this build phase. + * apps/examples/hidbkd: Now supports decoding of encoded special keys + if CONFIG_EXAMPLES_HIDKBD_ENCODED is defined. diff --git a/apps/examples/README.txt b/apps/examples/README.txt index e40a63be9..7bfba721a 100644 --- a/apps/examples/README.txt +++ b/apps/examples/README.txt @@ -540,9 +540,21 @@ examples/hidkbd This is a simple test to debug/verify the USB host HID keyboard class driver. - CONFIG_EXAMPLES_HIDKBD_DEFPRIO - Priority of "waiter" thread. - CONFIG_EXAMPLES_HIDKBD_STACKSIZE - Stacksize of "waiter" thread. - + CONFIG_EXAMPLES_HIDKBD_DEFPRIO - Priority of "waiter" thread. Default: + 50 + CONFIG_EXAMPLES_HIDKBD_STACKSIZE - Stacksize of "waiter" thread. Default + 1024 + CONFIG_EXAMPLES_HIDKBD_DEVNAME - Name of keyboard device to be used. + Default: "/dev/kbda" + CONFIG_EXAMPLES_HIDKBD_ENCODED - Decode special key press events in the + user buffer. In this case, the example coded will use the interfaces + defined in include/nuttx/input/kbd_codec.h to decode the returned + keyboard data. These special keys include such things as up/down + arrows, home and end keys, etc. If this not defined, only 7-bit print- + able and control ASCII characters will be provided to the user. + Requires CONFIG_HIDKBD_ENCODED && CONFIG_LIB_KBDCODEC + +endif examples/igmp ^^^^^^^^^^^^^ diff --git a/apps/examples/hidkbd/Kconfig b/apps/examples/hidkbd/Kconfig index 503d9d9d9..81f817ef9 100644 --- a/apps/examples/hidkbd/Kconfig +++ b/apps/examples/hidkbd/Kconfig @@ -10,4 +10,35 @@ config EXAMPLES_HIDKBD Enable the USB HID keyboard example if EXAMPLES_HIDKBD + +config EXAMPLES_HIDKBD_DEFPRIO + int "Waiter Thread Priority" + default 50 + ---help--- + Priority of "waiter" thread. Default: 50 + +config EXAMPLES_HIDKBD_STACKSIZE + int "Waiter Thread Stack Size" + default 1024 + ---help--- + Stacksize of "waiter" thread. Default 1024 + +config EXAMPLES_HIDKBD_DEVNAME + string "Keyboard Device Name" + default "/dev/kbda" + ---help--- + Name of keyboard device to be used. Default: "/dev/kbda" + +config EXAMPLES_HIDKBD_ENCODED + bool "Encode Special Keys" + default y + depends on HIDKBD_ENCODED && LIB_KBDCODEC + ---help--- + Decode special key press events in the user buffer. In this case, + the example coded will use the interfaces defined in + include/nuttx/input/kbd_codec.h to decode the returned keyboard + data. These special keys include such things as up/down arrows, + home and end keys, etc. If this not defined, only 7-bit print-able + and control ASCII characters will be provided to the user. + endif diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c index 8c9f6fa95..8a632bab7 100644 --- a/apps/examples/hidkbd/hidkbd_main.c +++ b/apps/examples/hidkbd/hidkbd_main.c @@ -46,10 +46,18 @@ #include #include #include +#include +#include +#include #include #include +#ifdef CONFIG_EXAMPLES_HIDKBD_ENCODED +# include +# include +#endif + /**************************************************************************** * Definitions ****************************************************************************/ @@ -83,10 +91,23 @@ # define CONFIG_EXAMPLES_HIDKBD_DEVNAME "/dev/kbda" #endif +#if !defined(CONFIG_HIDKBD_ENCODED) || !defined(CONFIG_LIB_KBDCODEC) +# undef CONFIG_EXAMPLES_HIDKBD_ENCODED +#endif + /**************************************************************************** * Private Types ****************************************************************************/ +#ifdef CONFIG_EXAMPLES_HIDKBD_ENCODED +struct hidbkd_instream_s +{ + struct lib_instream_s stream; + FAR char *buffer; + ssize_t nbytes; +}; +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -98,9 +119,84 @@ static struct usbhost_driver_s *g_drvr; ****************************************************************************/ /**************************************************************************** - * Public Functions + * Name: hidkbd_getstream + * + * Description: + * Get one character from the keyboard. + * ****************************************************************************/ +#ifdef CONFIG_EXAMPLES_HIDKBD_ENCODED +static int hidkbd_getstream(FAR struct lib_instream_s *this) +{ + FAR struct hidbkd_instream_s *kbdstream = (FAR struct hidbkd_instream_s *)this; + + DEBUGASSERT(kbdstream && kbdstream->buffer); + if (kbdstream->nbytes > 0) + { + kbdstream->nbytes--; + kbdstream->stream.nget++; + return (int)*kbdstream->buffer++; + } + + return EOF; +} +#endif + +/**************************************************************************** + * Name: hidkbd_decode + * + * Description: + * Decode encoded keyboard input + * + ****************************************************************************/ + +#ifdef CONFIG_EXAMPLES_HIDKBD_ENCODED +static void hidkbd_decode(FAR char *buffer, ssize_t nbytes) +{ + struct hidbkd_instream_s kbdstream; + struct kbd_getstate_s state; + uint8_t ch; + int ret; + + /* Initialize */ + + memset(&state, 0, sizeof(struct kbd_getstate_s)); + kbdstream.stream.get = hidkbd_getstream; + kbdstream.stream.nget = 0; + kbdstream.buffer = buffer; + kbdstream.nbytes = nbytes; + + /* Loop until all of the bytes have been consumed. We implicitly assume + * that the the escaped sequences do not cross buffer boundaries. That + * might be true if the read buffer were small or the data rates high. + */ + + for (;;) + { + /* Decode the next thing from the buffer */ + + ret = kbd_get((FAR struct lib_instream_s *)&kbdstream, &state, &ch); + if (ret == KBD_ERROR) + { + break; + } + + /* Normal data? Or special key? */ + + if (ret == KBD_NORMAL) + { + printf("Data: %c [%02x]\n", isprint(ch) ? ch : '.', ch); + } + else + { + DEBUGASSERT(ret == KBD_SPECIAL); + printf("Special: %d\n", ch); + } + } +} +#endif + /**************************************************************************** * Name: hidkbd_waiter * @@ -140,6 +236,10 @@ static int hidkbd_waiter(int argc, char *argv[]) return 0; } +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: hidkbd_main ****************************************************************************/ @@ -217,7 +317,11 @@ int hidkbd_main(int argc, char *argv[]) { /* On success, echo the buffer to stdout */ +#ifdef CONFIG_EXAMPLES_HIDKBD_ENCODED + hidkbd_decode(buffer, nbytes); +#else (void)write(1, buffer, nbytes); +#endif } } while (nbytes > 0); diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig index 78e411560..35a7bfc3d 100755 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -316,7 +316,10 @@ CONFIG_DEV_NULL=y # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set # CONFIG_BCH is not set -# CONFIG_INPUT is not set +CONFIG_INPUT=y +# CONFIG_INPUT_TSC2007 is not set +# CONFIG_INPUT_ADS7843E is not set +# CONFIG_INPUT_STMPE811 is not set # CONFIG_LCD is not set CONFIG_MMCSD=y CONFIG_MMCSD_NSLOTS=1 @@ -364,7 +367,7 @@ CONFIG_HIDKBD_STACKSIZE=1024 CONFIG_HIDKBD_BUFSIZE=64 CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_HIDKBD_RAWSCANCODES is not set -# CONFIG_HIDKBD_ENCODED is not set +CONFIG_HIDKBD_ENCODED=y # CONFIG_HIDKBD_ALLSCANCODES is not set # CONFIG_HIDKBD_NODEBOUNCE is not set # CONFIG_WIRELESS is not set @@ -425,6 +428,10 @@ CONFIG_MM_REGIONS=2 # # Library Routines # + +# +# Standard C Library Options +# CONFIG_STDIO_BUFFER_SIZE=256 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 @@ -443,6 +450,11 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + # # Basic CXX Support # @@ -473,6 +485,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_HELLOXX is not set # CONFIG_EXAMPLES_JSON is not set CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 +CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 +CONFIG_EXAMPLES_HIDKBD_DEVNAME="/dev/kbda" +CONFIG_EXAMPLES_HIDKBD_ENCODED=y # CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set # CONFIG_EXAMPLES_LCDRW is not set diff --git a/nuttx/drivers/usbhost/Kconfig b/nuttx/drivers/usbhost/Kconfig index de8469b41..531e94442 100644 --- a/nuttx/drivers/usbhost/Kconfig +++ b/nuttx/drivers/usbhost/Kconfig @@ -89,10 +89,10 @@ config HIDKBD_RAWSCANCODES config HIDKBD_ENCODED bool "Enocode Special Keys" default n - depends on !HIDKBD_RAWSCANCODES + depends on !HIDKBD_RAWSCANCODES && LIB_KBDCODEC ---help--- Encode special key press events in the user buffer. In this case, - the use end must decode the encoded special key values using the + the user end must decode the encoded special key values using the interfaces defined in include/nuttx/input/kbd_codec.h. These special keys include such things as up/down arrows, home and end keys, etc. If this not defined, only 7-bit print-able and control diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c index 5022793ca..917ebfa3f 100644 --- a/nuttx/drivers/usbhost/usbhost_hidkbd.c +++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c @@ -131,6 +131,14 @@ # endif #endif +/* We cant support encoding of special characters of unless the Keyboard + * CODEC is enabled. + */ + +#ifndef CONFIG_LIB_KBDCODEC +# undef CONFIG_HIDKBD_ENCODED +#endif + /* If we are using raw scancodes, then we cannot support encoding of * special characters either. */ @@ -398,11 +406,11 @@ static struct usbhost_state_s *g_priv; /* Data passed to thread */ /* The first and last scancode values with encode-able values */ -#define FIRST_ENCODING USBHID_KBDUSE_ENTER /* 0x28 Keyboard Return (ENTER) */ -#ifdef CONFIG_HIDKBD_ALLSCANCODES -# define LAST_ENCODING USBHID_KBDUSE_POWER /* 0x66 Keyboard Power */ +#define FIRST_ENCODING USBHID_KBDUSE_ENTER /* 0x28 Keyboard Return (ENTER) */ +#ifndef CONFIG_HIDKBD_ALLSCANCODES +# define LAST_ENCODING USBHID_KBDUSE_POWER /* 0x66 Keyboard Power */ #else -#define LAST_ENCODING USBHID_KBDUSE_KPDHEXADECIMAL /* 0xdd Keypad Hexadecimal */ +# define LAST_ENCODING USBHID_KBDUSE_KPDHEXADECIMAL /* 0xdd Keypad Hexadecimal */ #endif #define USBHID_NUMENCODINGS (LAST_ENCODING - FIRST_ENCODING + 1) @@ -874,10 +882,10 @@ static void usbhost_putbuffer(FAR struct usbhost_state_s *priv, #ifdef CONFIG_HIDKBD_ENCODED static void usbhost_putstream(FAR struct lib_outstream_s *stream, int ch) { - FAR struct usbhost_outstream_s *privstream = (FAR struct lib_outstream_s *)stream; + FAR struct usbhost_outstream_s *privstream = (FAR struct usbhost_outstream_s *)stream; DEBUGASSERT(privstream && privstream->priv); - usbhost_putbuffer(privstream->priv), (uint8_t)ch); + usbhost_putbuffer(privstream->priv, (uint8_t)ch); stream->nput++; } #endif @@ -945,7 +953,6 @@ static inline uint8_t usbhost_mapscancode(uint8_t scancode, uint8_t modifier) static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, uint8_t scancode, uint8_t modifier) { - struct usbhost_outstream_s stream; uint8_t encoded; /* Check if the raw scancode is in a valid range */ @@ -954,7 +961,7 @@ static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, { /* Yes the value is within range */ - encoded = encoding(scancode - FIRST_ENCODING); + encoded = encoding[scancode - FIRST_ENCODING]; ivdbg(" scancode: %02x modifier: %02x encoded: %d\n", scancode, modifier, encoded); @@ -964,13 +971,14 @@ static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, /* And it does correspond to a special function key */ - usbstream->stream.put = usbhost_putstream; - usbstream->stream.nput = 0; - usbstream->priv = priv; + usbstream.stream.put = usbhost_putstream; + usbstream.stream.nput = 0; + usbstream.priv = priv; /* Add the special function value to the user buffer */ - kbd_putspecial((enum kbd_keycode_e)encoded, &usbstream); + kbd_putspecial((enum kbd_keycode_e)encoded, + (FAR struct lib_outstream_s *)&usbstream); } } } @@ -1156,7 +1164,7 @@ static int usbhost_kbdpoll(int argc, char *argv[]) #ifdef CONFIG_HIDKBD_ENCODED else { - usbhost_encodescancode(priv, rpt->key[i], rpt->modifier)); + usbhost_encodescancode(priv, rpt->key[i], rpt->modifier); } #endif } diff --git a/nuttx/include/nuttx/input/kbd_codec.h b/nuttx/include/nuttx/input/kbd_codec.h index d374ed8d3..0a3a54d2d 100644 --- a/nuttx/include/nuttx/input/kbd_codec.h +++ b/nuttx/include/nuttx/input/kbd_codec.h @@ -44,6 +44,8 @@ #include #include +#ifdef CONFIG_LIB_KBDCODEC + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -87,7 +89,7 @@ enum kbd_keycode_e KEYCODE_CUT, /* Cut */ KEYCODE_COPY, /* Copy */ KEYCODE_PASTE, /* Paste */ - KEYCODE_FIND , /* Find */ + KEYCODE_FIND, /* Find */ /* Selection codes */ @@ -294,5 +296,6 @@ int kbd_get(FAR struct lib_instream_s *stream, } #endif +#endif /* CONFIG_LIB_KBDCODEC */ #endif /* __INCLUDE_NUTTX_INPUT_KBD_CODEC_H */ diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index bd470be7f..a5ff7fd43 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -3,6 +3,8 @@ # see misc/tools/kconfig-language.txt. # +comment "Standard C Library Options" + config STDIO_BUFFER_SIZE int "C STDIO buffer size" default 64 @@ -273,3 +275,29 @@ config ARCH_BZERO of bzero(). endif + +comment "Non-standard Helper Functions" + +config LIB_KBDCODEC + bool "Keyboard CODEC" + default y + ---help--- + In NuttX, a keyboard/keypad driver is simply a character driver that + may have an (optional) encoding/decoding layer on the data returned + by the character driver. A keyboard may return simple text data + (alphabetic, numeric, and punctuaction) or control characters + (enter, control-C, etc.). We can think about this the normal + "in-band" keyboard data stream. However, in addition, most + keyboards support actions that cannot be represented as text data. + Such actions include things like cursor controls (home, up arrow, + page down, etc.), editing functions (insert, delete, etc.), volume + controls, (mute, volume up, etc.) and other special functions. We + can think about this as special, "out-of-band" keyboard commands. + In this case, some special encoding may be required to multiplex + the in-band text data and out-of-band command streams. + + This option enables the functions that implement the encoding and + decoding of keyboard data. These are the interfaces prototyped in + include/nuttx/input/kbd_codec.h. While not correctly a part of + the C library, it is included here because the decoding side of this + interface must be accessible by end user programs. diff --git a/nuttx/libc/math/Kconfig b/nuttx/libc/math/Kconfig index c24bfd53f..db9dfae63 100644 --- a/nuttx/libc/math/Kconfig +++ b/nuttx/libc/math/Kconfig @@ -4,7 +4,7 @@ # config LIBM - bool "Math library" + bool "Standard Math library" default n depends on !ARCH_MATH_H ---help--- diff --git a/nuttx/libc/misc/Make.defs b/nuttx/libc/misc/Make.defs index c6af5f860..ad0313346 100644 --- a/nuttx/libc/misc/Make.defs +++ b/nuttx/libc/misc/Make.defs @@ -35,7 +35,7 @@ # Add the internal C files to the build -CSRCS += lib_init.c lib_filesem.c lib_kbdencode.c lib_kbddecode.c +CSRCS += lib_init.c lib_filesem.c # Add C files that depend on file OR socket descriptors @@ -63,6 +63,12 @@ CSRCS += lib_match.c CSRCS += lib_crc32.c CSRCS += lib_dbg.c lib_dumpbuffer.c +# Keyboard driver encoder/decoder + +ifneq ($(CONFIG_LIB_KBDCODEC),0) +CSRCS += lib_kbdencode.c lib_kbddecode.c +endif + # Add the misc directory to the build DEPPATH += --dep-path misc -- cgit v1.2.3 From 954529e8c571cd7c2cc5963259d7eef46f6f5429 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 27 Dec 2012 14:01:59 +0000 Subject: Add support for key release events git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5464 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 5 +- apps/examples/hidkbd/hidkbd_main.c | 33 +++++-- nuttx/ChangeLog | 4 + nuttx/Documentation/NuttxPortingGuide.html | 138 +++++++++++++++++++++++------ nuttx/drivers/usbhost/usbhost_hidkbd.c | 8 +- nuttx/include/nuttx/input/kbd_codec.h | 100 +++++++++++++++------ nuttx/libc/misc/lib_kbddecode.c | 99 +++++++++++---------- nuttx/libc/misc/lib_kbdencode.c | 101 +++++++++++++++++---- 8 files changed, 356 insertions(+), 132 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index d156b1065..d6a2f9d90 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -455,4 +455,7 @@ this build phase. * apps/examples/hidbkd: Now supports decoding of encoded special keys if CONFIG_EXAMPLES_HIDKBD_ENCODED is defined. - + * apps/examples/hidbkd: Add support for decoding key release events + as well. However, the USB HID keyboard drier has not yet been + updated to detect key release events. That is kind of tricky in + the USB HID keyboard report data. diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c index 8a632bab7..d7e79b121 100644 --- a/apps/examples/hidkbd/hidkbd_main.c +++ b/apps/examples/hidkbd/hidkbd_main.c @@ -176,7 +176,7 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes) { /* Decode the next thing from the buffer */ - ret = kbd_get((FAR struct lib_instream_s *)&kbdstream, &state, &ch); + ret = kbd_decode((FAR struct lib_instream_s *)&kbdstream, &state, &ch); if (ret == KBD_ERROR) { break; @@ -184,14 +184,31 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes) /* Normal data? Or special key? */ - if (ret == KBD_NORMAL) + switch (ret) { - printf("Data: %c [%02x]\n", isprint(ch) ? ch : '.', ch); - } - else - { - DEBUGASSERT(ret == KBD_SPECIAL); - printf("Special: %d\n", ch); + case KBD_PRESS: /* Key press event */ + printf("Normal Press: %c [%02x]\n", isprint(ch) ? ch : '.', ch); + break; + + case KBD_RELEASE: /* Key release event */ + printf("Normal Release: %c [%02x]\n", isprint(ch) ? ch : '.', ch); + break; + + case KBD_SPECPRESS: /* Special key press event */ + printf("Special Press: %d\n", ch); + break; + + case KBD_SPECREL: /* Special key release event */ + printf("Special Release: %d\n", ch); + break; + + case KBD_ERROR: /* Error or end-of-file */ + printf("EOF: %d\n", ret); + break; + + default: + printf("Unexpected: %d\n", ret); + break; } } } diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index a7087656a..2e114af8c 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3832,4 +3832,8 @@ UG-2864HSWEG01 OLED for the STM32F4Discovery board. * drivers/usbhost/usbhost_hidkbd.c: Correct a logic error in how tasks waiting for read data are awakened. + * libc/misc/lib_kbdencode.c and lib_kbddecode.c: Now handles keypress + events too. However, the USB HID keyboard drier has not yet been + updated to detect key release events. That is kind of tricky in + the USB HID keyboard report data. diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index ebb3eff4b..e626bf7a5 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -3623,20 +3623,27 @@ extern void up_ledoff(int led);

    6.3.16 Keyboard/Keypad Drivers

    - "Out-of-Band" Commands. - Keyboards and keypads are the same device for NuttX. + Keypads vs. Keyboards + Keyboards and keypads are really the same devices for NuttX. A keypad is thought of as simply a keyboard with fewer keys. +

    +

    + Special Commands. In NuttX, a keyboard/keypad driver is simply a character driver that may have an (optional) encoding/decoding layer on the data returned by the character driver. - A keyboard may return simple text data (alphabetic, numeric, and punctuaction) or control characters (enter, control-C, etc.). - We can think about this the normal "in-band" keyboard data stream. - However, in addition, most keyboards support actions that cannot be represented as text data. + A keyboard may return simple text data (alphabetic, numeric, and punctuaction) or control characters (enter, control-C, etc.) when a key is pressed. + We can think about this the "normal" keyboard data stream. + However, in addition, most keyboards support actions that cannot be represented as text or control data. Such actions include things like cursor controls (home, up arrow, page down, etc.), editing functions (insert, delete, etc.), volume controls, (mute, volume up, etc.) and other special functions. - We can think about this as special, "out-of-band" keyboard commands. - In this case, some special encoding may be required to multiplex the in-band text data and out-of-band command streams. + In this case, some special encoding may be required to multiplex the normal text data and special command key press data streams. +

    +

    + Key Press and Release Events + Sometimes the time that a key is released is needed by applications as well. + Thus, in addition to normal and special key press events, it may also be necessary to encode normal and special key release events.

    Encoding/Decoding Layer. - An optional encoding/decoding layer can be used with the basic character driver to encode the out-of-band commands into the text data stream. + An optional encoding/decoding layer can be used with the basic character driver to encode the keyboard events into the text data stream. The function interfaces that comprise that encoding/decoding layer are defined in the header file include/nuttx/input/kbd_code.h. These functions provide an matched set of (a) driver encoding interfaces, and (b) application decoding interfaces.

    @@ -3644,21 +3651,23 @@ extern void up_ledoff(int led);

  • Driver Encoding Interfaces. + These are interfaces used by the keyboard/keypad driver to encode keyboard events and data.

    • - kbd_puttext() + kbd_press()

      Function Prototype:

         #include <nuttx/streams.h>
 #include <nuttx/input/kbd_codec.h>
-void kbd_puttext(int ch, FAR struct lib_outstream_s *stream);
+void kbd_press(int ch, FAR struct lib_outstream_s *stream);

      Description:

        - Put one byte of normal, "in-band" ASCII data into the output stream. + Indicates a normal key press event. + Put one byte of normal keyboard data into the output stream.

      Input Pameters:

        @@ -3676,18 +3685,77 @@ void kbd_puttext(int ch, FAR struct lib_outstream_s *stream);

      • - kbd_putspecial() + kbd_release() +

        +

        Function Prototype:

        + 
          +#include <nuttx/streams.h>
+#include <nuttx/input/kbd_codec.h>
+void kbd_release(uint8_t ch, FAR struct lib_outstream_s *stream);
+
        +

        Description:

        +
          + Encode the release of a normal key. +
        +

        Input Pameters:

        +
          +
        • + ch: The character associated with the key that was releared. +
          • +
        • + stream: An instance of lib_outstream_s to perform the actual low-level put operation. +
          • +
        +

        Returned Value:

        +
          + None. +
        +
        • +
      • +

        + kbd_specpress()

        Function Prototype:

           #include <nuttx/streams.h>
 #include <nuttx/input/kbd_codec.h>
-void kbd_putspecial(enum kbd_keycode_e keycode, FAR struct lib_outstream_s *stream);
+void kbd_specpress(enum kbd_keycode_e keycode, FAR struct lib_outstream_s *stream);

        Description:

          - Put one special, "out-of-band" command into the output stream. + Denotes a special key press event. + Put one special keyboard command into the output stream. +
        +

        Input Pameters:

        +
          +
        • + keycode: The command to be added to the output stream. + The enumeration enum kbd_keycode_e keycode identifies all commands known to the system. +
          • +
        • + stream: An instance of lib_outstream_s to perform the actual low-level put operation. +
        +

        Returned Value:

        +
          + None. +
        +
        • +
      • +

        + kbd_specrel() +

        +

        Function Prototype:

        + 
          +#include <nuttx/streams.h>
+#include <nuttx/input/kbd_codec.h>
+void kbd_specrel(enum kbd_keycode_e keycode, FAR struct lib_outstream_s *stream);
+
        +

        Description:

        +
          + Denotes a special key release event. + Put one special keyboard command into the output stream. +

        Input Pameters:

        • @@ -3708,17 +3776,18 @@ void kbd_putspecial(enum kbd_keycode_e keycode, FAR struct lib_outstream_s *stre

        • Application Decoding Interfaces. -

          + These are user interfaces to decode the values returned by the keyboard/keypad driver. +

          • - kbd_get() + kbd_decode()

            Function Prototype:

               #include <nuttx/streams.h>
 #include <nuttx/input/kbd_codec.h>
-int kbd_get(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *state, FAR uint8_t *pch);
+int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *state, FAR uint8_t *pch);

            Description:

              @@ -3730,30 +3799,41 @@ int kbd_get(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *state, stream: An instance of lib_instream_s to perform the actual low-level get operation.
            • - pch: The location character to save the returned value. - This may be either a normal, "in-band" ASCII characer or a special, "out-of-band" command (i.e., a value from enum kbd_getstate_s. + pch: The location to save the returned value. + This may be either a normal, character code or a special command (i.e., a value from enum kbd_getstate_s.
            • state: A user provided buffer to support parsing. - This structure should be cleared the first time that kbd_get is called. + This structure should be cleared the first time that kbd_decode() is called.

            Returned Value:

            • - 1: - Indicates the successful receipt of a special, "out-of-band" command. - The returned value in pch is a value from enum kbd_getstate_s. + KBD_PRESS (0): + Indicates the successful receipt of normal, keyboard data. + This corresponds to a keypress event. + The returned value in pch is a simple byte of text or control data.
            • - 0: - Indicates the successful receipt of normal, "in-band" ASCII data. - The returned value in pch is a simple byte of text or control data. + KBD_RELEASE (1): + Indicates a key release event. + The returned value in pch is the byte of text or control data corresponding to the released key. +
              • +
            • + KBD_SPECPRESS (2): + Indicates the successful receipt of a special keyboard command. + The returned value in pch is a value from enum kbd_getstate_s. +
              • +
            • + KBD_SPECREL (3): + Indicates a special command key release event. + The returned value in pch is a value from enum kbd_getstate_s.
            • - EOF: - An error has getting the next character (reported by the stream). - Normally indicates the end of file. + KBD_ERROR (EOF): + An error has getting the next character (reported by the stream). + Normally indicates the end of file.
            • diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c index 917ebfa3f..0bab89c28 100644 --- a/nuttx/drivers/usbhost/usbhost_hidkbd.c +++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c @@ -530,7 +530,7 @@ static const uint8_t ucmap[USBHID_NUMSCANCODES] = 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ 0, 0, 0, 0, '/', '*', '-', '+', /* 0x50-0x57: LeftArrow,DownArrow,UpArrow,Num Lock,/,*,-,+ */ - '\n', '1', '2', '3', '4', '4', '6', '7', /* 0x58-0x5f: Enter,1-7 */ + '\n', '1', '2', '3', '4', '5', '6', '7', /* 0x58-0x5f: Enter,1-7 */ '8', '9', '0', '.', 0, 0, 0, '=', /* 0x60-0x67: 8-9,0,.,Non-US \,Application,Power,= */ #ifdef CONFIG_HIDKBD_ALLSCANCODES 0, 0, 0, 0, 0, 0, 0, 0, /* 0x68-0x6f: F13,F14,F15,F16,F17,F18,F19,F20 */ @@ -565,7 +565,7 @@ static const uint8_t lcmap[USBHID_NUMSCANCODES] = 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ 0, 0, 0, 0, '/', '*', '-', '+', /* 0x50-0x57: LeftArrow,DownArrow,UpArrow,Num Lock,/,*,-,+ */ - '\n', '1', '2', '3', '4', '4', '6', '7', /* 0x58-0x5f: Enter,1-7 */ + '\n', '1', '2', '3', '4', '5', '6', '7', /* 0x58-0x5f: Enter,1-7 */ '8', '9', '0', '.', 0, 0, 0, '=', /* 0x60-0x67: 8-9,0,.,Non-US \,Application,Power,= */ #ifdef CONFIG_HIDKBD_ALLSCANCODES 0, 0, 0, 0, 0, 0, 0, 0, /* 0x68-0x6f: F13,F14,F15,F16,F17,F18,F19,F20 */ @@ -977,8 +977,8 @@ static inline void usbhost_encodescancode(FAR struct usbhost_state_s *priv, /* Add the special function value to the user buffer */ - kbd_putspecial((enum kbd_keycode_e)encoded, - (FAR struct lib_outstream_s *)&usbstream); + kbd_specpress((enum kbd_keycode_e)encoded, + (FAR struct lib_outstream_s *)&usbstream); } } } diff --git a/nuttx/include/nuttx/input/kbd_codec.h b/nuttx/include/nuttx/input/kbd_codec.h index 0a3a54d2d..9a7c7c8e6 100644 --- a/nuttx/include/nuttx/input/kbd_codec.h +++ b/nuttx/include/nuttx/input/kbd_codec.h @@ -1,6 +1,6 @@ /************************************************************************************ * include/nuttx/input/kbd_codec.h - * Serialize and marshaling out-of-band keyboard data + * Serialize and marshaling keyboard data and events * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -54,9 +54,7 @@ * Public Types ****************************************************************************/ -/* These are the special, "out-of-band" keyboard commands recognized by the - * CODEC. - */ +/* These are the special keyboard commands recognized by the CODEC. */ enum kbd_keycode_e { @@ -190,11 +188,13 @@ enum kbd_keycode_e #define FIRST_KEYCODE KEYCODE_FWDDEL #define LAST_KEYCODE KEYCODE_F24 -/* kbd_get return values */ +/* kbd_decode() return values */ -#define KBD_NORMAL 0 -#define KBD_SPECIAL 1 -#define KBD_ERROR EOF +#define KBD_PRESS 0 /* Key press event */ +#define KBD_RELEASE 1 /* Key release event */ +#define KBD_SPECPRESS 2 /* Special key press event */ +#define KBD_SPECREL 3 /* Special key release event */ +#define KBD_ERROR EOF /* Error or end-of-file */ /**************************************************************************** * Public Types @@ -222,10 +222,11 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: kbd_puttext + * Name: kbd_press * * Description: - * Put one byte of normal, "in-band" ASCII data into the output stream. + * Indicates a normal key press event. Put one byte of normal keyboard + * data into the output stream. * * Input Parameters: * ch - The character to be added to the output stream. @@ -237,13 +238,52 @@ extern "C" * ****************************************************************************/ -#define kbd_puttext(ch, stream) (stream)->put((stream), (int)(ch)) +#define kbd_press(ch, stream) (stream)->put((stream), (int)(ch)) /**************************************************************************** - * Name: kbd_putspecial + * Name: kbd_release * * Description: - * Put one special, "out-of-band" command into the output stream. + * Encode the release of a normal key. + * + * Input Parameters: + * ch - The character associated with the key that was releared. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_release(uint8_t ch, FAR struct lib_outstream_s *stream); + +/**************************************************************************** + * Name: kbd_specpress + * + * Description: + * Denotes a special key press event. Put one special keyboard command + * into the output stream. + * + * Input Parameters: + * keycode - The command to be added to the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_specpress(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream); + +/**************************************************************************** + * Name: kbd_specrel + * + * Description: + * Denotes a special key release event. Put one special keyboard + * command into the output stream. * * Input Parameters: * keycode - The command to be added to the output stream. @@ -255,8 +295,8 @@ extern "C" * ****************************************************************************/ -void kbd_putspecial(enum kbd_keycode_e keycode, - FAR struct lib_outstream_s *stream); +void kbd_specrel(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream); /**************************************************************************** * The following functions are intended for use by "consumer" applications @@ -264,7 +304,7 @@ void kbd_putspecial(enum kbd_keycode_e keycode, ****************************************************************************/ /**************************************************************************** - * Name: kbd_get + * Name: kbd_decode * * Description: * Get one byte of data or special command from the driver provided input @@ -273,24 +313,30 @@ void kbd_putspecial(enum kbd_keycode_e keycode, * Input Parameters: * stream - An instance of lib_instream_s to do the low-level get * operation. - * pch - The location character to save the returned value. This may be - * either a normal, "in-band" ASCII characer or a special, "out-of-band" - * command. + * pch - The location to save the returned value. This may be + * either a normal, character code or a special command from enum + * kbd_keycode_e * state - A user provided buffer to support parsing. This structure - * should be cleared the first time that kbd_get is called. + * should be cleared the first time that kbd_decode is called. * * Returned Value: - * 1 - Indicates the successful receipt of a special, "out-of-band" command. - * The returned value in pch is a value from enum kbd_getstate_s. - * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. - * The returned value in pch is a simple byte of text or control data. + * + * KBD_PRESS - Indicates the successful receipt of normal, keyboard data. + * This corresponds to a keypress event. The returned value in pch is a + * simple byte of text or control data corresponding to the pressed key. + * KBD_RELEASE - Indicates a key release event. The returned value in pch + * is the byte of text or control data corresponding to the released key. + * KBD_SPECPRESS - Indicates the successful receipt of a special keyboard + * command. The returned value in pch is a value from enum kbd_getstate_s. + * KBD_SPECREL - Indicates a special key release event. The returned value + * in pch is a value from enum kbd_getstate_s. * EOF - An error has getting the next character (reported by the stream). - * Normally indicates the end of file. + * Normally indicates the end of file. * ****************************************************************************/ -int kbd_get(FAR struct lib_instream_s *stream, - FAR struct kbd_getstate_s *state, FAR uint8_t *pch); +int kbd_decode(FAR struct lib_instream_s *stream, + FAR struct kbd_getstate_s *state, FAR uint8_t *pch); #ifdef __cplusplus } diff --git a/nuttx/libc/misc/lib_kbddecode.c b/nuttx/libc/misc/lib_kbddecode.c index cb57b5215..62554902c 100644 --- a/nuttx/libc/misc/lib_kbddecode.c +++ b/nuttx/libc/misc/lib_kbddecode.c @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * libc/msic/lib_kbddecode.c * Decoding side of the Keyboard CODEC * @@ -32,38 +32,43 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include #include +#include #include #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-Processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -#define NDX_ESC 0 -#define NDX_BRACKET 1 -#define NDX_CODE 2 -#define NCX_SEMICOLON 3 +#define NDX_ESC 0 +#define NDX_BRACKET 1 +#define NDX_CODE 2 +#define NDX_TERMINATOR 3 -#define NCH_ESC 1 -#define NCH_BRACKET 2 -#define NCH_CODE 3 -#define NCH_SEMICOLON 4 +#define NCH_ESC 1 +#define NCH_BRACKET 2 +#define NCH_CODE 3 +#define NCH_TERMINATOR 4 -/******************************************************************************************** +#define TERM_MIN ('a' + KBD_RELEASE) +#define TERM_MAX ('a' + KBD_SPECREL) +#define TERM_RETURN(a) ((a) - 'a') + +/**************************************************************************** * Private Functions - ********************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: kbd_reget @@ -76,16 +81,11 @@ * stream - An instance of lib_instream_s to do the low-level get * operation. * pch - The location character to save the returned value. This may be - * either a normal, "in-band" ASCII characer or a special, "out-of-band" - * command. - * state - A user provided buffer to support parsing. This structure - * should be cleared the first time that kbd_get is called. + * either a normal, character code or a special command from enum + * kbd_keycode_e * * Returned Value: - * 2 - Indicates the successful receipt of a special, "out-of-band" command - * 1 - Indicates the successful receipt of normal, "in-band" ASCII data. - * 0 - Indicates end-of-file or that the stream has been closed - * EOF - An error has getting the next character (reported by the stream). + * KBD_PRESS - Indicates the successful receipt of norma keyboard data. * ****************************************************************************/ @@ -96,15 +96,15 @@ static int kbd_reget(FAR struct kbd_getstate_s *state, FAR uint8_t *pch) *pch = state->buf[state->ndx]; state->ndx++; state->nch--; - return KBD_NORMAL; + return KBD_PRESS; } -/******************************************************************************************** +/**************************************************************************** * Public Functions - ********************************************************************************************/ + ****************************************************************************/ /**************************************************************************** - * Name: kbd_get + * Name: kbd_decode * * Description: * Get one byte of data or special command from the driver provided input @@ -113,24 +113,30 @@ static int kbd_reget(FAR struct kbd_getstate_s *state, FAR uint8_t *pch) * Input Parameters: * stream - An instance of lib_instream_s to do the low-level get * operation. - * pch - The location character to save the returned value. This may be - * either a normal, "in-band" ASCII characer or a special, "out-of-band" - * command. + * pch - The location to save the returned value. This may be + * either a normal, character code or a special command from enum + * kbd_keycode_e * state - A user provided buffer to support parsing. This structure - * should be cleared the first time that kbd_get is called. + * should be cleared the first time that kbd_decode is called. * * Returned Value: - * 1 - Indicates the successful receipt of a special, "out-of-band" command. - * The returned value in pch is a value from enum kbd_getstate_s. - * 0 - Indicates the successful receipt of normal, "in-band" ASCII data. - * The returned value in pch is a simple byte of text or control data. + * + * KBD_PRESS - Indicates the successful receipt of normal, keyboard data. + * This corresponds to a keypress event. The returned value in pch is a + * simple byte of text or control data corresponding to the pressed key. + * KBD_RELEASE - Indicates a key release event. The returned value in pch + * is the byte of text or control data corresponding to the released key. + * KBD_SPECPRESS - Indicates the successful receipt of a special keyboard + * command. The returned value in pch is a value from enum kbd_getstate_s. + * KBD_SPECREL - Indicates a special key release event. The returned value + * in pch is a value from enum kbd_getstate_s. * EOF - An error has getting the next character (reported by the stream). - * Normally indicates the end of file. + * Normally indicates the end of file. * ****************************************************************************/ -int kbd_get(FAR struct lib_instream_s *stream, - FAR struct kbd_getstate_s *state, FAR uint8_t *pch) +int kbd_decode(FAR struct lib_instream_s *stream, + FAR struct kbd_getstate_s *state, FAR uint8_t *pch) { int ch; @@ -147,7 +153,7 @@ int kbd_get(FAR struct lib_instream_s *stream, state->ndx = 0; - /* No, ungotten characters. Check for the beginning of an esc sequence. */ + /* No, ungotten characters. Check for the beginning of an ESC sequence. */ ch = stream->get(stream); if (ch == EOF) @@ -195,7 +201,7 @@ int kbd_get(FAR struct lib_instream_s *stream, } } - /* Get and verify the special, "out-of-band" command code */ + /* Get and verify the special keyboard data to decode */ ch = stream->get(stream); if (ch == EOF) @@ -234,12 +240,12 @@ int kbd_get(FAR struct lib_instream_s *stream, } else { - state->buf[NCX_SEMICOLON] = (uint8_t)ch; - state->nch = NCH_SEMICOLON; + state->buf[NDX_TERMINATOR] = (uint8_t)ch; + state->nch = NCH_TERMINATOR; /* Check for a valid special command code */ - if (ch != ';') + if (ch < TERM_MIN || ch > TERM_MAX) { /* Not a special command code, return the ESC now and the next two * characters later. @@ -250,11 +256,12 @@ int kbd_get(FAR struct lib_instream_s *stream, } /* We have successfully parsed the the entire escape sequence. Return the - * special code in pch and the value 2. + * keyboard value in pch and the value an indication determined by the + * terminating character. */ *pch = state->buf[NDX_CODE]; state->nch = 0; - return KBD_SPECIAL; + return TERM_RETURN(state->buf[NDX_TERMINATOR]); } diff --git a/nuttx/libc/misc/lib_kbdencode.c b/nuttx/libc/misc/lib_kbdencode.c index 40a8805b1..80138ca80 100644 --- a/nuttx/libc/misc/lib_kbdencode.c +++ b/nuttx/libc/misc/lib_kbdencode.c @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * libc/msic/lib_kbdencode.c * Encoding side of the Keyboard CODEC * @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -47,38 +47,105 @@ #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-Processor Definitions - ********************************************************************************************/ - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ + ****************************************************************************/ /**************************************************************************** - * Name: kbd_putspecial + * Name: kbd_encode * * Description: - * Put one special, "out-of-band" command into the output stream. + * Encode one special special sequence command into the output stream. * * Input Parameters: * keycode - The command to be added to the output stream. * stream - An instance of lib_outstream_s to do the low-level put * operation. + * terminator - Escape sequence terminating character. * * Returned Value: * None * ****************************************************************************/ -void kbd_putspecial(enum kbd_keycode_e keycode, - FAR struct lib_outstream_s *stream) +static void kbd_encode(uint8_t keycode, FAR struct lib_outstream_s *stream, + uint8_t terminator) { - DEBUGASSERT(stream && keycode >= KEYCODE_FWDDEL && keycode <= LAST_KEYCODE); - stream->put(stream, ASCII_ESC); stream->put(stream, '['); stream->put(stream, (int)keycode); - stream->put(stream, ';'); + stream->put(stream, terminator); } +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kbd_release + * + * Description: + * Encode the release of a normal key. + * + * Input Parameters: + * ch - The character associated with the key that was releared. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_release(uint8_t ch, FAR struct lib_outstream_s *stream) +{ + kbd_encode(ch, stream, ('a' + KBD_RELEASE)); +} + +/**************************************************************************** + * Name: kbd_specpress + * + * Description: + * Denotes a special key press event. Put one special keyboard command + * into the output stream. + * + * Input Parameters: + * keycode - The command to be added to the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_specpress(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream) +{ + DEBUGASSERT(stream && keycode >= KEYCODE_FWDDEL && keycode <= LAST_KEYCODE); + kbd_encode((uint8_t)keycode, stream, ('a' + KBD_SPECPRESS)); +} + +/**************************************************************************** + * Name: kbd_specrel + * + * Description: + * Denotes a special key release event. Put one special keyboard + * command into the output stream. + * + * Input Parameters: + * keycode - The command to be added to the output stream. + * stream - An instance of lib_outstream_s to do the low-level put + * operation. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kbd_specrel(enum kbd_keycode_e keycode, + FAR struct lib_outstream_s *stream) +{ + DEBUGASSERT(stream && keycode >= KEYCODE_FWDDEL && keycode <= LAST_KEYCODE); + kbd_encode((uint8_t)keycode, stream, ('a' + KBD_SPECREL)); +} -- cgit v1.2.3 From e0be95b9a02ebd38cc370b81586371bd93e6ac76 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 28 Dec 2012 23:40:54 +0000 Subject: Add board support at configs/zp214xpa for the The0.net ZP213X/4XPA board with the LPC2148; Add configurations sim/nxlines. convert mcu123-lpc214x/nsh to use the kconfig-frontends. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5465 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/hidkbd/hidkbd_main.c | 11 +- nuttx/ChangeLog | 6 + nuttx/Documentation/NuttX.html | 5 +- nuttx/arch/arm/src/lpc214x/Kconfig | 134 +++++ nuttx/configs/Kconfig | 14 +- nuttx/configs/README.txt | 5 + nuttx/configs/mcu123-lpc214x/README.txt | 18 +- nuttx/configs/mcu123-lpc214x/nsh/appconfig | 44 -- nuttx/configs/mcu123-lpc214x/nsh/defconfig | 760 ++++++++++++++++--------- nuttx/configs/mcu123-lpc214x/scripts/ld.script | 6 +- nuttx/configs/sim/nxlines/Make.defs | 107 ++++ nuttx/configs/sim/nxlines/defconfig | 591 +++++++++++++++++++ nuttx/configs/sim/nxlines/setenv.sh | 53 ++ nuttx/configs/zp214xpa/Kconfig | 7 + nuttx/configs/zp214xpa/README.txt | 136 +++++ nuttx/configs/zp214xpa/include/board.h | 68 +++ nuttx/configs/zp214xpa/nsh/Make.defs | 128 +++++ nuttx/configs/zp214xpa/nsh/defconfig | 574 +++++++++++++++++++ nuttx/configs/zp214xpa/nsh/setenv.sh | 65 +++ nuttx/configs/zp214xpa/scripts/ld.script | 120 ++++ nuttx/configs/zp214xpa/src/Makefile | 84 +++ nuttx/drivers/mmcsd/Kconfig | 1 + nuttx/drivers/usbhost/usbhost_hidkbd.c | 6 +- 23 files changed, 2626 insertions(+), 317 deletions(-) delete mode 100644 nuttx/configs/mcu123-lpc214x/nsh/appconfig create mode 100644 nuttx/configs/sim/nxlines/Make.defs create mode 100644 nuttx/configs/sim/nxlines/defconfig create mode 100755 nuttx/configs/sim/nxlines/setenv.sh create mode 100644 nuttx/configs/zp214xpa/Kconfig create mode 100644 nuttx/configs/zp214xpa/README.txt create mode 100644 nuttx/configs/zp214xpa/include/board.h create mode 100644 nuttx/configs/zp214xpa/nsh/Make.defs create mode 100644 nuttx/configs/zp214xpa/nsh/defconfig create mode 100755 nuttx/configs/zp214xpa/nsh/setenv.sh create mode 100644 nuttx/configs/zp214xpa/scripts/ld.script create mode 100644 nuttx/configs/zp214xpa/src/Makefile diff --git a/apps/examples/hidkbd/hidkbd_main.c b/apps/examples/hidkbd/hidkbd_main.c index d7e79b121..abc942a44 100644 --- a/apps/examples/hidkbd/hidkbd_main.c +++ b/apps/examples/hidkbd/hidkbd_main.c @@ -177,12 +177,14 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes) /* Decode the next thing from the buffer */ ret = kbd_decode((FAR struct lib_instream_s *)&kbdstream, &state, &ch); - if (ret == KBD_ERROR) + if (ret == KBD_ERROR) /* Error or end-of-file */ { + /* Break out when all of the data has been processed */ + break; } - /* Normal data? Or special key? */ + /* Normal data? Or special key? Press? Or release? */ switch (ret) { @@ -202,10 +204,7 @@ static void hidkbd_decode(FAR char *buffer, ssize_t nbytes) printf("Special Release: %d\n", ch); break; - case KBD_ERROR: /* Error or end-of-file */ - printf("EOF: %d\n", ret); - break; - + case KBD_ERROR: /* Error or end-of-file, already handled */ default: printf("Unexpected: %d\n", ret); break; diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2e114af8c..dcabb6c07 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3836,4 +3836,10 @@ events too. However, the USB HID keyboard drier has not yet been updated to detect key release events. That is kind of tricky in the USB HID keyboard report data. + * configs/mcu123-214x/nsh: Converted to use the kconfig-frontends + configuration tool. + * configs/zp214xpa: Add basic support for the The0.net ZP213x/4xPA + board (with the LPC2148 and the UG_2864AMBAG01). + * configs/sim/nxlines: Add an nxlines configuration for the + simulator. diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 84f298d3a..dc454c0b6 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@

            NuttX RTOS

            -

            Last Updated: December 20, 2012

            +

            Last Updated: December 28, 2012

            @@ -1505,7 +1505,8 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code

            NXP LPC214x. Support is provided for the NXP LPC214x family of processors. In particular, - support is provided for the mcu123.com lpc214x evaluation board (LPC2148). + support is provided for (1) the mcu123.com lpc214x evaluation board (LPC2148) + and (1) the The0.net ZPA213X/4XPA development board (with the The0.net UG-2864AMBAG01 OLED) This port also used the GNU arm-nuttx-elf toolchain* under Linux or Cygwin.

              diff --git a/nuttx/arch/arm/src/lpc214x/Kconfig b/nuttx/arch/arm/src/lpc214x/Kconfig index a26483ed9..5d52eb000 100644 --- a/nuttx/arch/arm/src/lpc214x/Kconfig +++ b/nuttx/arch/arm/src/lpc214x/Kconfig @@ -4,3 +4,137 @@ # comment "LPC214x Configuration Options" + +# Fragments of LPC214x chip selection logic. The LPC2148 is the only chip +# supported for now. + +config ARCH_CHIP_LPC2148 + bool + default y + +comment "LPC214x Initialization Options" + +choice + prompt "Memory Execution Mode" + default DEFAULT_MODE + +config EXTMEM_MODE + bool "External Memory Mode" + ---help--- + Code executes from external memory starting at address 0x8000:0000. + +config RAM_MODE + bool "RAM Memory Mode" + ---help--- + Code executes from on-chip RAM at address 0x4000:0000. + +config DEFAULT_MODE + bool "Default Memory Mode" + ---help--- + Executes from 0x0000:0000. In non-default modes, the MEMAP register + is set override the settings of the CPU configuration pins. + +endchoice + +config CODE_BASE + hex "Execuation Base Address" + default 0x00000000 + ---help--- + This must match the expected address for the selected "Memory + Execution Address": + + EXTMEM_MODE: 0x8000:0000 + RAM_MODE: 0x4000:0000 + DEFAULT)MODE: 0x0000:0000 + +config PLL_SETUP + bool "Configure the PLL" + default y + +config MAM_SETUP + bool "Configure the Memory Accelerator Module (MAM)" + default y + +config APBDIV_SETUP + bool "Configure the APB Divider" + default y + +config APBDIV_VALUE + int "APB Divisor" + default 1 + +config EMC_SETUP + bool "Configure EMC" + default n + +config BCFG0_SETUP + bool "Configure BCFG0" + default n + +config BCFG1_SETUP + bool "Configure BCFG1" + default n + +config BCFG2_SETUP + bool "Configure BCFG2" + default n + +config BCFG3_SETUP + bool "Configure BCFG3" + default n + +config ADC_SETUP + bool "Configure ADC" + default y + +menu "LPC214x Peripheral Support" + +config LPC214X_UART0 + bool + default y + select ARCH_HAVE_UART0 + +config LPC214X_UART1 + bool + default y + select ARCH_HAVE_UART1 + +config LPC214X_USBDEV + bool "USB Device" + default y + depends on USBDEV + +endmenu + +config LPC214x_FIO + bool "Fast GPIO" + default n + +if LPC214X_USBDEV +menu "LPC214x USB Device Configuration" + +config LPC214X_USBDEV_DMA + bool "USB Device DMA Support" + default n + +config CONFIG_LPC214X_USBDEV_NDMADESCRIPTORS + int "Number of USB DMA Descriptors" + default 8 + depends on LPC214X_USBDEV_DMA + +config LPC214X_USBDEV_EPFAST_INTERRUPT + bool "USB Device Fast Endpoint Interrupts" + default n + +config LPC214X_USBDEV_FRAME_INTERRUPT + bool "USB Device Frame Interrupts" + default n + +config LPC214X_USBDEV_REGDEBUG + bool "USB Device Register-Level Debug Output" + default n + depends on DEBUG + +endmenu +endif + diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index bba1444c4..cda5aa7bc 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -619,6 +619,14 @@ config ARCH_BOARD_Z8F64200100KIT development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line tools. The development environment is Cygwin under WinXP. +config ARCH_BOARD_ZP214XPA + bool "The0.net LPC2148 Development Board" + depends on ARCH_CHIP_LPC2148 + ---help--- + This port is for the NXP LPC2148 as provided on the The0.net + ZPA213X/4XPA development board. Includes support for the + UG-2864AMBAG01 OLED also from The0.net + config ARCH_BOARD_SIM bool "User mode simulation" depends on ARCH_SIM @@ -700,6 +708,7 @@ config ARCH_BOARD default "z80sim" if ARCH_BOARD_Z80SIM default "z8encore000zco" if ARCH_BOARD_Z8ENCORE000ZCO default "z8f64200100kit" if ARCH_BOARD_Z8F64200100KIT + default "zp214xpa" if ARCH_BOARD_ZP214XPA default "sim" if ARCH_BOARD_SIM default "" if ARCH_BOARD_CUSTOM @@ -709,7 +718,7 @@ config ARCH_HAVE_LEDS bool config ARCH_LEDS - bool "Board LEDs support" + bool "Board LED support" default y depends on ARCH_HAVE_LEDS ---help--- @@ -935,6 +944,9 @@ endif if ARCH_BOARD_Z8F64200100KIT source "configs/z8f64200100kit/Kconfig" endif +if ARCH_BOARD_ZP214XPA +source "configs/zp214xpa/Kconfig" +endif if ARCH_BOARD_SIM source "configs/sim/Kconfig" endif diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 21aace2af..4e9bcca14 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1936,6 +1936,11 @@ configs/z8f64200100kit development kit, Z8F6423 part, and the Zilog ZDS-II Windows command line tools. The development environment is Cygwin under WinXP. +configs/zp214xpa + This port is for the NXP LPC2148 as provided on the The0.net + ZPA213X/4XPA development board. Includes support for the + UG-2864AMBAG01 OLED also from The0.net + Configuring NuttX ^^^^^^^^^^^^^^^^^ diff --git a/nuttx/configs/mcu123-lpc214x/README.txt b/nuttx/configs/mcu123-lpc214x/README.txt index 435f8647d..4c7c608b7 100644 --- a/nuttx/configs/mcu123-lpc214x/README.txt +++ b/nuttx/configs/mcu123-lpc214x/README.txt @@ -349,8 +349,22 @@ nsh: Configures the NuttShell (nsh) located at examples/nsh. The Configuration enables only the serial NSH interfaces. - Default toolchain: Buildroot - Output format: ELF and binary + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Windows + CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary ostest: ------- diff --git a/nuttx/configs/mcu123-lpc214x/nsh/appconfig b/nuttx/configs/mcu123-lpc214x/nsh/appconfig deleted file mode 100644 index f8e2d5165..000000000 --- a/nuttx/configs/mcu123-lpc214x/nsh/appconfig +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# configs/mcu123-lpc214x/nsh/appconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nsh - -# The NSH library - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - diff --git a/nuttx/configs/mcu123-lpc214x/nsh/defconfig b/nuttx/configs/mcu123-lpc214x/nsh/defconfig index a8a53a340..6ae163386 100644 --- a/nuttx/configs/mcu123-lpc214x/nsh/defconfig +++ b/nuttx/configs/mcu123-lpc214x/nsh/defconfig @@ -1,169 +1,207 @@ -############################################################################ -# configs/mcu123-lpc214x/nsh/defconfig -# -# Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +CONFIG_ARCH_CHIP_LPC214X=y +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_ARM7TDMI=y +CONFIG_ARCH_FAMILY="arm" CONFIG_ARCH_CHIP="lpc214x" -CONFIG_ARCH_CHIP_LPC2148=y -CONFIG_ARCH_BOARD="mcu123-lpc214x" -CONFIG_ARCH_BOARD_MCU123=y +CONFIG_ARCH_HAVE_LOWVECTORS=y +# CONFIG_ARCH_LOWVECTORS is not set CONFIG_BOARD_LOOPSPERMSEC=3270 -CONFIG_ARCH_LEDS=y -CONFIG_DRAM_SIZE=32768 -CONFIG_DRAM_START=0x40000000 -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_CALIBRATION is not set # -# LPC2148 specific chip initialization +# ARM Configuration Options +# +# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARM_TOOLCHAIN_GNU_EABI=y + +# +# LPC214x Configuration Options +# +CONFIG_ARCH_CHIP_LPC2148=y + # -CONFIG_EXTMEM_MODE=n -CONFIG_RAM_MODE=n +# LPC214x Initialization Options +# +# CONFIG_EXTMEM_MODE is not set +# CONFIG_RAM_MODE is not set +CONFIG_DEFAULT_MODE=y CONFIG_CODE_BASE=0x00000000 CONFIG_PLL_SETUP=y CONFIG_MAM_SETUP=y CONFIG_APBDIV_SETUP=y -CONFIG_EMC_SETUP=n -CONFIG_BCFG0_SETUP=n -CONFIG_BCFG1_SETUP=n -CONFIG_BCFG2_SETUP=n -CONFIG_BCFG3_SETUP=n +CONFIG_APBDIV_VALUE=1 +# CONFIG_EMC_SETUP is not set +# CONFIG_BCFG0_SETUP is not set +# CONFIG_BCFG1_SETUP is not set +# CONFIG_BCFG2_SETUP is not set +# CONFIG_BCFG3_SETUP is not set CONFIG_ADC_SETUP=y # -# LPC214X specific device driver settings +# LPC214x Peripheral Support # -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART0_BAUD=38400 -CONFIG_UART1_BAUD=38400 -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 +CONFIG_LPC214X_UART0=y +CONFIG_LPC214X_UART1=y +# CONFIG_LPC214x_FIO is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# General build options +# Architecture Options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # -# General OS setup +# Board Settings # -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y +CONFIG_DRAM_START=0x40000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_MCU123=y +# CONFIG_ARCH_BOARD_ZP214XPA is not set +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="mcu123-lpc214x" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=0 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=10 CONFIG_START_DAY=1 -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set CONFIG_DISABLE_POLL=y -# -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - # # Sizes of configurable things (0 disables) # @@ -173,8 +211,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -182,168 +218,380 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Filesystem configuration +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +# CONFIG_SPI_EXCHANGE is not set +# CONFIG_SPI_CMDDATA is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVECARDDETECT=y +CONFIG_MMCSD_SPI=y +CONFIG_MMCSD_SPICLOCK=20000000 +# CONFIG_MMCSD_SDIO is not set +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_UART1_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=38400 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=38400 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration # CONFIG_FS_FAT=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set # -# Maintain legacy build behavior (revisit) +# System Logging # +# CONFIG_SYSLOG is not set -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +# +# Graphics Support +# +# CONFIG_NX is not set # -# SPI-based MMC/SD driver +# Memory Management # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -#CONFIG_MMCSD_SPICLOCK=20000000 +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set # -# SPI-based MMC/SD driver +# Binary Formats # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set # -# TCP/IP and UDP support via uIP +# Library Routines # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n # -# UIP Network Utilities +# Standard C Library Options # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# USB Device Configuration +# Non-standard Helper Functions # -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 +CONFIG_LIB_KBDCODEC=y # -# LPC214X USB Configuration +# Basic CXX Support # -CONFIG_LPC214X_USBDEV_FRAME_INTERRUPT=n -CONFIG_LPC214X_USBDEV_EPFAST_INTERRUPT=n -CONFIG_LPC214X_USBDEV_DMA=n -CONFIG_LPC214X_USBDEV_NDMADESCRIPTORS=0 -CONFIG_LPC214X_USBDEV_DMAINTMASK=0 +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set # -# USB Serial Device Configuration +# Application Configuration # -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=5 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 # -# USB Storage Device Configuration +# Built-In Applications +# +# CONFIG_BUILTIN is not set + # -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=2 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set # -# Settings for examples/ostest -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=4096 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +# Interpreters +# # -# Settings for apps/nshlib +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + # +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n +# CONFIG_NSH_CONDEV is not set CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" - -# -# Architecture-specific NSH options -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 # -# Stack and heap information +# NxWidgets/NxWM # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/mcu123-lpc214x/scripts/ld.script b/nuttx/configs/mcu123-lpc214x/scripts/ld.script index 8ce83748f..bc025dfb7 100644 --- a/nuttx/configs/mcu123-lpc214x/scripts/ld.script +++ b/nuttx/configs/mcu123-lpc214x/scripts/ld.script @@ -35,12 +35,12 @@ /* FLASH: * The lpc2148 has 512Kb of non-volatile memory beginning at address - * 0x00000000. The OS entry point is via the reset vector at address - * 0x00000000 (default MEMMAP mode assumed) + * 0x0000:0000. The OS entry point is via the reset vector at address + * 0x0000:0000 (default MEMMAP mode assumed) * * SRAM: * The lpc2148 has 32Kb of on-chip static RAM beginning at address - * 0x40000000. The .data section will be relocated from _eronly + * 0x4000:0000. The .data section will be relocated from _eronly * to _sdata at boot time. */ diff --git a/nuttx/configs/sim/nxlines/Make.defs b/nuttx/configs/sim/nxlines/Make.defs new file mode 100644 index 000000000..18c8bf537 --- /dev/null +++ b/nuttx/configs/sim/nxlines/Make.defs @@ -0,0 +1,107 @@ +############################################################################ +# configs/sim/nxlines/Make.defs +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +HOSTOS = ${shell uname -o 2>/dev/null || echo "Other"} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = -O2 +endif + +ARCHCPUFLAGS = -fno-builtin +ARCHCPUFLAGSXX = -fno-builtin -fno-exceptions -fno-rtti +ARCHPICFLAGS = -fpic +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHINCLUDES = -I. -isystem $(TOPDIR)/include +ARCHINCLUDESXX = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx +ARCHSCRIPT = + +ifeq ($(CONFIG_SIM_M32),y) + ARCHCPUFLAGS += -m32 + ARCHCPUFLAGSXX += -m32 +endif + +CROSSDEV = +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXFLAGS = $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGSXX) $(ARCHINCLUDESXX) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +OBJEXT = .o +LIBEXT = .a + +ifeq ($(HOSTOS),Cygwin) + EXEEXT = .exe +else + EXEEXT = +endif + +LDLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(LD) +CCLINKFLAGS = $(ARCHSCRIPT) # Link flags used with $(CC) +LDFLAGS = $(ARCHSCRIPT) # For backward compatibility, same as CCLINKFLAGS + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDLINKFLAGS += -g + CCLINKFLAGS += -g + LDFLAGS += -g +endif + +ifeq ($(CONFIG_SIM_M32),y) + LDLINKFLAGS += -melf_i386 + CCLINKFLAGS += -m32 + LDFLAGS += -m32 +endif + +MKDEP = $(TOPDIR)/tools/mkdeps.sh + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +HOSTLDFLAGS = diff --git a/nuttx/configs/sim/nxlines/defconfig b/nuttx/configs/sim/nxlines/defconfig new file mode 100644 index 000000000..c023af674 --- /dev/null +++ b/nuttx/configs/sim/nxlines/defconfig @@ -0,0 +1,591 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +CONFIG_DEBUG_SYMBOLS=y + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +CONFIG_ARCH_SIM=y +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="sim" +CONFIG_BOARD_LOOPSPERMSEC= + +# +# Simulation Configuration Options +# +# CONFIG_SIM_M32 is not set +# CONFIG_SIM_WALLTIME is not set +CONFIG_SIM_FRAMEBUFFER=y +CONFIG_SIM_X11FB=y +# CONFIG_SIM_X11NOSHM is not set +CONFIG_SIM_FBHEIGHT=240 +CONFIG_SIM_FBWIDTH=480 +CONFIG_SIM_FBBPP=32 + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +# CONFIG_ARCH_STACKDUMP is not set +# CONFIG_ENDIAN_BIG is not set + +# +# Board Settings +# +CONFIG_DRAM_START= +CONFIG_DRAM_SIZE= + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SIM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sim" + +# +# Common Board Options +# +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=32 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=5 +CONFIG_START_DAY=1 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_ATEXIT is not set +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_ONEXIT_MAX=1 +CONFIG_USER_ENTRYPOINT="nxlines_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +CONFIG_DISABLE_POSIX_TIMERS=y +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=16 +CONFIG_NFILE_STREAMS=16 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MAX_WDOGPARMS=4 +CONFIG_PREALLOC_WDOGS=32 +CONFIG_PREALLOC_TIMERS=8 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_USERMAIN_STACKSIZE=16384 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=8192 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +CONFIG_FS_ROMFS=y + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +CONFIG_NX=y +CONFIG_NX_NPLANES=1 +# CONFIG_NX_WRITEONLY is not set + +# +# Supported Pixel Depths +# +CONFIG_NX_DISABLE_1BPP=y +CONFIG_NX_DISABLE_2BPP=y +CONFIG_NX_DISABLE_4BPP=y +CONFIG_NX_DISABLE_8BPP=y +CONFIG_NX_DISABLE_16BPP=y +CONFIG_NX_DISABLE_24BPP=y +# CONFIG_NX_DISABLE_32BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set + +# +# Input Devices +# +CONFIG_NX_MOUSE=y +CONFIG_NX_KBD=y + +# +# Framed Window Borders +# +CONFIG_NXTK_BORDERWIDTH=4 +CONFIG_NXTK_BORDERCOLOR1=0x005a96bd +CONFIG_NXTK_BORDERCOLOR2=0x00233a49 +CONFIG_NXTK_BORDERCOLOR3=0x00f8f8f8 +# CONFIG_NXTK_AUTORAISE is not set + +# +# Font Selections +# +CONFIG_NXFONTS_CHARBITS=7 +# CONFIG_NXFONT_SANS17X22 is not set +# CONFIG_NXFONT_SANS20X26 is not set +CONFIG_NXFONT_SANS23X27=y +# CONFIG_NXFONT_SANS22X29 is not set +# CONFIG_NXFONT_SANS28X37 is not set +# CONFIG_NXFONT_SANS39X48 is not set +# CONFIG_NXFONT_SANS17X23B is not set +# CONFIG_NXFONT_SANS20X27B is not set +# CONFIG_NXFONT_SANS22X29B is not set +CONFIG_NXFONT_SANS28X37B=y +# CONFIG_NXFONT_SANS40X49B is not set +# CONFIG_NXFONT_SERIF22X29 is not set +# CONFIG_NXFONT_SERIF29X37 is not set +# CONFIG_NXFONT_SERIF38X48 is not set +# CONFIG_NXFONT_SERIF22X28B is not set +# CONFIG_NXFONT_SERIF27X38B is not set +# CONFIG_NXFONT_SERIF38X49B is not set +# CONFIG_NXCONSOLE is not set + +# +# NX Multi-user only options +# +# CONFIG_NX_MULTIUSER is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +# CONFIG_HAVE_CXXINITIALIZE is not set +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_VPLANE=0 +CONFIG_EXAMPLES_NXLINES_DEVNO=0 +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00006400 +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x00ffff00 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=16 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x00ffff00 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x00f5f5dc +CONFIG_EXAMPLES_NXLINES_BPP=32 +# CONFIG_EXAMPLES_NXLINES_EXTERNINIT is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_ROMFSETC=y +CONFIG_NSH_ROMFSMOUNTPT="/etc" +CONFIG_NSH_INITSCRIPT="init.d/rcS" +CONFIG_NSH_ROMFSDEVNO=1 +CONFIG_NSH_ROMFSSECTSIZE=64 +CONFIG_NSH_FATDEVNO=2 +CONFIG_NSH_FATSECTSIZE=512 +CONFIG_NSH_FATNSECTORS=1024 +CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# +# CONFIG_NXWIDGETS is not set + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/sim/nxlines/setenv.sh b/nuttx/configs/sim/nxlines/setenv.sh new file mode 100755 index 000000000..0722cbc2e --- /dev/null +++ b/nuttx/configs/sim/nxlines/setenv.sh @@ -0,0 +1,53 @@ +#!/bin/bash +# sim/nxlines/setenv.sh +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +#export NUTTX_BIN= +#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/zp214xpa/Kconfig b/nuttx/configs/zp214xpa/Kconfig new file mode 100644 index 000000000..d8d04ca5c --- /dev/null +++ b/nuttx/configs/zp214xpa/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_ZP214XPA +endif diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt new file mode 100644 index 000000000..6fd7bfba9 --- /dev/null +++ b/nuttx/configs/zp214xpa/README.txt @@ -0,0 +1,136 @@ +zp214xpa README FILE +==================== + +The ZP213X/4XPA board from the0.net with LPC2148 installed. +Includes support for the UG-2864AMBAG01 OLED from The0.net. + +Contents +======== + + o MCU Connections + o Serial Console + o Configurations + +MCU Connections: +================ + +Module Socket: +-------------- +PIN NAME PIN NAME + 1 VBAT 56 VCC + 2 3V3 55 Vusb + 3 VREF 54 3V3 + 4 P0.0 53 RESET + 5 P0.1 52 P1.31 + 6 P0.2 51 P1.30 + 7 P0.3 50 P1.29 + 8 P0.4 49 P1.28 + 9 P0.5 48 P1.27 +10 P0.6 47 P1.26 +11 P0.7 46 P1.25 +12 P0.8 45 P1.24 +13 P0.9 44 P1.23 +14 P0.10 43 P1.22 +15 P0.11 42 P1.21 +16 P0.12 41 P1.20 +17 P0.13 40 P1.19 +18 P0.14 39 P1.18 +19 P0.15 38 P1.17 +20 P0.16 37 P1.16 +21 P0.17 36 P0.31 +22 P0.18 35 P0.30 +23 P0.19 34 P0.29 +24 P0.20 33 P0.28 +25 P0.21 32 P0.27 +26 P0.22 31 P0.26 +27 P0.23 30 P0.25 +28 GND 29 GND + +JTAG Debug: +----------- +PIN NAME PIN NAME + 1 VCC1 2 3V3 + 3 P1.31 NTRST 4 GND + 5 P1.28 TDI 6 GND + 7 P1.30 TMS 8 GND + 9 P1.29 TCK 10 GND +11 P1.26 RTCK 12 GND +13 P1.27 TDO 14 GND +15 RESET NRTS 16 GND +17 N/C NC0 18 GND +19 N/C NC1 20 GND + +Z28160 Net Module: +------------------ +PIN NAME PIN NAME + 1 P0.7 /CS 10 3V3 VCC + 2 P0.4 SCK 9 P1.24 RST + 3 P0.6 SI 8 N/C CLKOUT + 4 P0.5 SO 7 INT P1.25 + 5 GND 6 N/C WOL + +SPI LCD: +-------- +PIN NAME + 1 3V3 3V3 + 2 VCC 5V + 3 P0.18 RESET(DO) + 4 P0.19 DI + 5 P0.20 CS + 6 P0.17 SCK + 7 P0.23 A0(RESET) + 8 N/C LED- + 9 N/C LED+(BL) +10 GND GND + +USB Interface: +-------------- +Vusb, P0.26, P0.27 + +Serial Console: +=============== + +Both UART0 and UART1 are always enabled. UART0 is configured to be the +serial console in these configurations. + +P0.0/TXD0/PWM1 Module Socket, Pin 4 +P0.1/RxD0/PWM3/EINT0 Module Socket, Pin 5 + +P0.8/TXD1/PWM4/AD1.1 Module Socket, Pin 12 +P0.9/RxD1/PWM6/EINT3 Module Socket, Pin 13 + +Configurations: +=============== + +Each NXP LPC214x configuration is maintained in a sudirectory and +can be selected as follow: + + cd tools + ./configure.sh zp214xpa/ + cd - + . ./setenv.sh + +Where is one of the following: + +nsh: +---- + + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables only the serial NSH interfaces. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Windows + CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary diff --git a/nuttx/configs/zp214xpa/include/board.h b/nuttx/configs/zp214xpa/include/board.h new file mode 100644 index 000000000..111d8ad55 --- /dev/null +++ b/nuttx/configs/zp214xpa/include/board.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * configs/zp214xpa/include/board.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_ZP214XPA_INCLUDE_BOARD_H +#define __CONFIGS_ZP214XPA_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Oscillator frequency */ + +#define LPC214X_FOSC 12000000 + +/* PLL0 settings CCLK = PLL_M * FOSC PCLK = CCLK/APBDIV */ + +#define LPC214X_PLL_M 5 +#define LPC214X_PLL_P 2 +#define LPC214X_APB_DIV 1 + +/* USB Pll settings -- 48 MHz needed. FUSB = PLL_M FOSC */ + +#define LPC214X_USBPLL_M 4 +#define LPC214X_USBPLL_P 2 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#endif /* __CONFIGS_ZP214XPA_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/zp214xpa/nsh/Make.defs b/nuttx/configs/zp214xpa/nsh/Make.defs new file mode 100644 index 000000000..f55e766d3 --- /dev/null +++ b/nuttx/configs/zp214xpa/nsh/Make.defs @@ -0,0 +1,128 @@ +############################################################################## +# configs/zp214xpa/nsh/Make.defs +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +# The default value for CROSSDEV can be overridden from the make command line: +# make -- Will build for the NuttX buildroot toolchain +# make CROSSDEV=arm-eabi- -- Will build for the devkitARM toolchain +# make CROSSDEV=arm-none-eabi- -- Will build for the CodeSourcery toolchain +# make CROSSDEV=arm-nuttx-elf- -- Will build for the NuttX buildroot toolchain + +CROSSDEV = arm-nuttx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +HOSTOS = ${shell uname -o 2>/dev/null || echo "Other"} + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(ARCHCCMAJOR),4) +ifneq ($(HOSTOS),Cygwin) +OBJCOPYARGS = -R .note -R .note.gnu.build-id -R .comment +endif +endif + +ifeq ($(CROSSDEV),arm-nuttx-elf-) + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script + MAXOPTIMIZATION = -Os +else + WINTOOL = y + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(ARCHCCMAJOR),4) + ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft +else + ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = diff --git a/nuttx/configs/zp214xpa/nsh/defconfig b/nuttx/configs/zp214xpa/nsh/defconfig new file mode 100644 index 000000000..7c7d9d06c --- /dev/null +++ b/nuttx/configs/zp214xpa/nsh/defconfig @@ -0,0 +1,574 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +CONFIG_ARCH_CHIP_LPC214X=y +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_ARM7TDMI=y +CONFIG_ARCH_FAMILY="arm" +CONFIG_ARCH_CHIP="lpc214x" +CONFIG_ARCH_HAVE_LOWVECTORS=y +# CONFIG_ARCH_LOWVECTORS is not set +CONFIG_BOARD_LOOPSPERMSEC=3270 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARM Configuration Options +# +# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARM_TOOLCHAIN_GNU_EABI=y + +# +# LPC214x Configuration Options +# +CONFIG_ARCH_CHIP_LPC2148=y + +# +# LPC214x Initialization Options +# +# CONFIG_EXTMEM_MODE is not set +# CONFIG_RAM_MODE is not set +CONFIG_DEFAULT_MODE=y +CONFIG_CODE_BASE=0x00000000 +CONFIG_PLL_SETUP=y +CONFIG_MAM_SETUP=y +CONFIG_APBDIV_SETUP=y +CONFIG_APBDIV_VALUE=1 +# CONFIG_EMC_SETUP is not set +# CONFIG_BCFG0_SETUP is not set +# CONFIG_BCFG1_SETUP is not set +# CONFIG_BCFG2_SETUP is not set +# CONFIG_BCFG3_SETUP is not set +CONFIG_ADC_SETUP=y + +# +# LPC214x Peripheral Support +# +CONFIG_LPC214X_UART0=y +CONFIG_LPC214X_UART1=y +# CONFIG_LPC214x_FIO is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x40000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_MCU123 is not set +CONFIG_ARCH_BOARD_ZP214XPA=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="zp214xpa" + +# +# Common Board Options +# +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2008 +CONFIG_START_MONTH=10 +CONFIG_START_DAY=1 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_UART1_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=38400 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=38400 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_FS_FAT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/zp214xpa/nsh/setenv.sh b/nuttx/configs/zp214xpa/nsh/setenv.sh new file mode 100755 index 000000000..724dab706 --- /dev/null +++ b/nuttx/configs/zp214xpa/nsh/setenv.sh @@ -0,0 +1,65 @@ +#!/bin/bash +# configs/zp214xpa/nsh/setenv.sh +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# The zp214xpa/tools directory +export LPCTOOL_DIR="${WD}/configs/zp214xpa/tools" + +# Add the path to the toolchain and tools directory to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/zp214xpa/scripts/ld.script b/nuttx/configs/zp214xpa/scripts/ld.script new file mode 100644 index 000000000..ba6ff8f2c --- /dev/null +++ b/nuttx/configs/zp214xpa/scripts/ld.script @@ -0,0 +1,120 @@ +/**************************************************************************** + * configs/zp214xpa/scripts/ld.script + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* FLASH: + * The lpc2148 has 512Kb of non-volatile memory beginning at address + * 0x0000:0000. The OS entry point is via the reset vector at address + * 0x0000:0000 (default MEMMAP mode assumed) + * + * SRAM: + * The lpc2148 has 32Kb of on-chip static RAM beginning at address + * 0x4000:0000. The .data section will be relocated from _eronly + * to _sdata at boot time. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K + sram (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32 +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/nuttx/configs/zp214xpa/src/Makefile b/nuttx/configs/zp214xpa/src/Makefile new file mode 100644 index 000000000..8f1e1c05d --- /dev/null +++ b/nuttx/configs/zp214xpa/src/Makefile @@ -0,0 +1,84 @@ +############################################################################ +# configs/zp214xpa/src/Makefile +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/arm}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/sched}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/arm -I$(TOPDIR)/sched +endif + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) +CSRCS = + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I $(TOPDIR)/arch/$(CONFIG_ARCH)/src + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig index c224f220a..f3a64be6c 100644 --- a/nuttx/drivers/mmcsd/Kconfig +++ b/nuttx/drivers/mmcsd/Kconfig @@ -2,6 +2,7 @@ # For a description of the syntax of this configuration file, # see misc/tools/kconfig-language.txt. # + config MMCSD_NSLOTS int "Number of MMC/SD slots" default 1 diff --git a/nuttx/drivers/usbhost/usbhost_hidkbd.c b/nuttx/drivers/usbhost/usbhost_hidkbd.c index 0bab89c28..d6a9ceda3 100644 --- a/nuttx/drivers/usbhost/usbhost_hidkbd.c +++ b/nuttx/drivers/usbhost/usbhost_hidkbd.c @@ -421,7 +421,7 @@ static const uint8_t encoding[USBHID_NUMENCODINGS] = KEYCODE_ENTER, 0, KEYCODE_FWDDEL, KEYCODE_BACKDEL, 0, 0, 0, 0, - /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */ + /* 0x30-0x37: },|,Non-US tilde,:,",grave tilde,<,> */ 0, 0, 0, 0, 0, 0, 0, 0, @@ -525,7 +525,7 @@ static const uint8_t ucmap[USBHID_NUMSCANCODES] = 'U', 'V', 'W', 'X', 'Y', 'Z', '!', '@', /* 0x18-0x1f: U-Z,!,@ */ '#', '$', '%', '^', '&', '*', '(', ')', /* 0x20-0x27: #,$,%,^,&,*,(,) */ '\n', '\033', '\177', 0, ' ', '_', '+', '{', /* 0x28-0x2f: Enter,escape,del,back-tab,space,_,+,{ */ - '}', '|', 0, ':', '"', 0, '<', '>', /* 0x30-0x37: },|,Non-US tilde,:,",grave tidle,<,> */ + '}', '|', 0, ':', '"', '~', '<', '>', /* 0x30-0x37: },|,Non-US tilde,:,",grave tilde,<,> */ '?', 0, 0, 0, 0, 0, 0, 0, /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ @@ -560,7 +560,7 @@ static const uint8_t lcmap[USBHID_NUMSCANCODES] = 'u', 'v', 'w', 'x', 'y', 'z', '1', '2', /* 0x18-0x1f: u-z,1-2 */ '3', '4', '5', '6', '7', '8', '9', '0', /* 0x20-0x27: 3-9,0 */ '\n', '\033', '\177', '\t', ' ', '-', '=', '[', /* 0x28-0x2f: Enter,escape,del,tab,space,-,=,[ */ - ']', '\\', '\234', ';', '\'', 0, ',', '.', /* 0x30-0x37: ],\,Non-US pound,;,',grave accent,,,. */ + ']', '\\', '\234', ';', '\'', '`', ',', '.', /* 0x30-0x37: ],\,Non-US pound,;,',grave accent,,,. */ '/', 0, 0, 0, 0, 0, 0, 0, /* 0x38-0x3f: /,CapsLock,F1,F2,F3,F4,F5,F6 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x40-0x47: F7,F8,F9,F10,F11,F12,PrtScn,ScrollLock */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x48-0x4f: Pause,Insert,Home,PageUp,DeleteForward,End,PageDown,RightArrow */ -- cgit v1.2.3 From e1eacb2254652f35e0eacc8b9a733bbad7976111 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 30 Dec 2012 16:39:25 +0000 Subject: Add ZP213X/4XPA nxlines configuration (needs a little more work) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5466 42af7a65-404d-4744-a932-0658087f49c3 --- misc/buildroot/configs/arm7tdmi-defconfig-4.3.3 | 7 + nuttx/ChangeLog | 5 +- nuttx/configs/mcu123-lpc214x/src/Makefile | 2 +- nuttx/configs/mcu123-lpc214x/src/up_spi.c | 602 ---------------------- nuttx/configs/mcu123-lpc214x/src/up_spi1.c | 602 ++++++++++++++++++++++ nuttx/configs/olimex-lpc1766stk/README.txt | 10 +- nuttx/configs/sim/README.txt | 15 + nuttx/configs/zp214xpa/README.txt | 376 ++++++++++---- nuttx/configs/zp214xpa/nxlines/Make.defs | 128 +++++ nuttx/configs/zp214xpa/nxlines/defconfig | 606 ++++++++++++++++++++++ nuttx/configs/zp214xpa/nxlines/setenv.sh | 65 +++ nuttx/configs/zp214xpa/src/Makefile | 4 + nuttx/configs/zp214xpa/src/up_spi1.c | 644 ++++++++++++++++++++++++ nuttx/configs/zp214xpa/src/up_ug2864ambag01.c | 177 +++++++ nuttx/configs/zp214xpa/tools/olimex.cfg | 62 +++ nuttx/configs/zp214xpa/tools/oocd.sh | 52 ++ nuttx/configs/zp214xpa/tools/usb-repair.txt | 25 + nuttx/graphics/Kconfig | 6 + nuttx/include/nuttx/nx/nxfonts.h | 5 + 19 files changed, 2698 insertions(+), 695 deletions(-) delete mode 100644 nuttx/configs/mcu123-lpc214x/src/up_spi.c create mode 100644 nuttx/configs/mcu123-lpc214x/src/up_spi1.c create mode 100644 nuttx/configs/zp214xpa/nxlines/Make.defs create mode 100644 nuttx/configs/zp214xpa/nxlines/defconfig create mode 100755 nuttx/configs/zp214xpa/nxlines/setenv.sh create mode 100644 nuttx/configs/zp214xpa/src/up_spi1.c create mode 100644 nuttx/configs/zp214xpa/src/up_ug2864ambag01.c create mode 100755 nuttx/configs/zp214xpa/tools/olimex.cfg create mode 100755 nuttx/configs/zp214xpa/tools/oocd.sh create mode 100644 nuttx/configs/zp214xpa/tools/usb-repair.txt diff --git a/misc/buildroot/configs/arm7tdmi-defconfig-4.3.3 b/misc/buildroot/configs/arm7tdmi-defconfig-4.3.3 index 7e97a77d6..c027c8a8c 100644 --- a/misc/buildroot/configs/arm7tdmi-defconfig-4.3.3 +++ b/misc/buildroot/configs/arm7tdmi-defconfig-4.3.3 @@ -14,6 +14,7 @@ BR2_arm=y # BR2_m68k is not set # BR2_m68hc11 is not set # BR2_m68hc12 is not set +# BR2_m9s12x is not set # BR2_mips is not set # BR2_mipsel is not set # BR2_nios2 is not set @@ -71,8 +72,11 @@ BR2_GNU_TARGET_SUFFIX="nuttx-elf" # Binutils Options # # BR2_BINUTILS_VERSION_2_17 is not set +# BR2_BINUTILS_VERSION_2_18 is not set # BR2_BINUTILS_VERSION_2_19 is not set BR2_BINUTILS_VERSION_2_19_1=y +# BR2_BINUTILS_VERSION_2_21_1 is not set +# BR2_BINUTILS_VERSION_2_22 is not set BR2_BINUTILS_VERSION="2.19.1" BR2_EXTRA_BINUTILS_CONFIG_OPTIONS="" @@ -80,9 +84,12 @@ BR2_EXTRA_BINUTILS_CONFIG_OPTIONS="" # GCC Options # BR2_PACKAGE_GCC=y +# BR2_GCC_VERSION_3_3_6 is not set # BR2_GCC_VERSION_3_4_6 is not set # BR2_GCC_VERSION_4_2_4 is not set BR2_GCC_VERSION_4_3_3=y +# BR2_GCC_VERSION_4_5_2 is not set +# BR2_GCC_VERSION_4_6_3 is not set BR2_GCC_SUPPORTS_SYSROOT=y BR2_GCC_VERSION="4.3.3" # BR2_GCC_USE_SJLJ_EXCEPTIONS is not set diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index dcabb6c07..56cc5515d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3842,4 +3842,7 @@ board (with the LPC2148 and the UG_2864AMBAG01). * configs/sim/nxlines: Add an nxlines configuration for the simulator. - + * configs/zp214xpa/nxlines: Add an nxlines configuration for the + ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). As of this + writing (2012-12-30), I see only garbage on the display each time + the display is updated. diff --git a/nuttx/configs/mcu123-lpc214x/src/Makefile b/nuttx/configs/mcu123-lpc214x/src/Makefile index 5ddcebe42..79f767fff 100644 --- a/nuttx/configs/mcu123-lpc214x/src/Makefile +++ b/nuttx/configs/mcu123-lpc214x/src/Makefile @@ -47,7 +47,7 @@ endif ASRCS = AOBJS = $(ASRCS:.S=$(OBJEXT)) -CSRCS = up_spi.c up_leds.c +CSRCS = up_spi1.c up_leds.c ifeq ($(CONFIG_NSH_ARCHINIT),y) CSRCS += up_nsh.c diff --git a/nuttx/configs/mcu123-lpc214x/src/up_spi.c b/nuttx/configs/mcu123-lpc214x/src/up_spi.c deleted file mode 100644 index b58c8d667..000000000 --- a/nuttx/configs/mcu123-lpc214x/src/up_spi.c +++ /dev/null @@ -1,602 +0,0 @@ -/**************************************************************************** - * config/mcu123-lpc214x/src/up_spi.c - * arch/arm/src/board/up_spi.c - * - * Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * One the mcu123.com lpc214x board, the MMC slot is connect via SPI with the - * following SPI mode pinout: - * - * 1 CS: Chip select (low) - SSEL1 5 SCLK: Clock - SCK1 - * 2 DI: Data input - MOSI1 6 Vss2: Supply Voltage- GRND - * 3 Vss: Supply Voltage - GRND 7 DO: Data Output - MISO1 - * 4 Vdd: Power Supply - Vcc 8 - N/C - * - * The LPC214x supports one SPI port (SPI0) and one SSP port (SPI1). SPI1 - * is used to interface with the MMC connect - * - * SCK1 - pin 47, P0.17/CAP1.2/SCK1/MAT1.2 - * MISO1 - pin 53, P0.18/CAP1.3/MISO1/MAT1.3 - * MOSI1 - pin 54, P0.19/MAT1.2/MOSI1/CAP1.2 - * SSEL1 - pin 55, P0.20/MAT1.3/SSEL1/EINT3 - * - * SPI0 is available on the mcu123.com board (pins 27, 29, 30, and 31). - * Pin 27 is dedicated to a chip select, pins 30 and 31 connect to keys, nd - * pin 29 is unconnected. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "lpc214x_power.h" -#include "lpc214x_pinsel.h" -#include "lpc214x_spi.h" - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SPI_DEBUG /* Define to enable debug */ -#undef SPI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SPI_DEBUG -# define spidbg lldbg -# ifdef SPI_VERBOSE -# define spivdbg lldbg -# else -# define spivdbg(x...) -# endif -#else -# undef SPI_VERBOSE -# define spidbg(x...) -# define spivdbg(x...) -#endif - -/* Clocking */ - -#define LPC214X_CCLKFREQ (LPC214X_FOSC*LPC214X_PLL_M) -#define LPC214X_PCLKFREQ (LPC214X_CCLKFREQ/LPC214X_APB_DIV) - -/* Use either FIO or legacy GPIO */ - -#ifdef CONFIG_LPC214x_FIO -# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) -#else -# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifndef CONFIG_SPI_OWNBUS -static int spi_lock(FAR struct spi_dev_s *dev, bool lock); -#endif -static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); -static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct spi_ops_s g_spiops = -{ -#ifndef CONFIG_SPI_OWNBUS - .lock = spi_lock, -#endif - .select = spi_select, - .setfrequency = spi_setfrequency, - .status = spi_status, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = spi_cmddata, -#endif - .send = spi_send, - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, - .registercallback = 0, /* Not implemented */ -}; - -static struct spi_dev_s g_spidev = { &g_spiops }; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: spi_lock - * - * Description: - * On SPI busses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the busses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_OWNBUS -static int spi_lock(FAR struct spi_dev_s *dev, bool lock) -{ - /* Not implemented */ - - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: spi_select - * - * Description: - * Enable/disable the SPI slave select. The implementation of this method - * must include handshaking: If a device is selected, it must hold off - * all other attempts to select the device until the device is deselecte. - * - * Input Parameters: - * dev - Device-specific state data - * devid - Identifies the device to select - * selected - true: slave selected, false: slave de-selected - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - uint32_t bit = 1 << 20; - - if (selected) - { - /* Enable slave select (low enables) */ - - spidbg("CD asserted\n"); - putreg32(bit, CS_CLR_REGISTER); - } - else - { - /* Disable slave select (low enables) */ - - spidbg("CD de-asserted\n"); - putreg32(bit, CS_SET_REGISTER); - - /* Wait for the TX FIFO not full indication */ - - while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); - putreg16(0xff, LPC214X_SPI1_DR); - - /* Wait until TX FIFO and TX shift buffer are empty */ - - while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY); - - /* Wait until RX FIFO is not empty */ - - while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); - - /* Then read and discard bytes until the RX FIFO is empty */ - - do - { - (void)getreg16(LPC214X_SPI1_DR); - } - while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE); - } -} - -/**************************************************************************** - * Name: spi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - ****************************************************************************/ - -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) -{ - uint32_t divisor = LPC214X_PCLKFREQ / frequency; - - if (divisor < 2) - { - divisor = 2; - } - else if (divisor > 254) - { - divisor = 254; - } - - divisor = (divisor + 1) & ~1; - putreg8(divisor, LPC214X_SPI1_CPSR); - - spidbg("Frequency %d->%d\n", frequency, LPC214X_PCLKFREQ / divisor); - return LPC214X_PCLKFREQ / divisor; -} - -/**************************************************************************** - * Name: spi_status - * - * Description: - * Get SPI/MMC status - * - * Input Parameters: - * dev - Device-specific state data - * devid - Identifies the device to report status on - * - * Returned Value: - * Returns a bitset of status values (see SPI_STATUS_* defines - * - ****************************************************************************/ - -static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - /* I don't think there is anyway to determine these things on the mcu123.com - * board. - */ - - spidbg("Return SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} - -/**************************************************************************** - * Name: spi_cmddata - * - * Description: - * Some devices require and additional out-of-band bit to specify if the - * next word sent to the device is a command or data. This is typical, for - * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. - * This function provides selection of command or data. - * - * This "latches" the CMD/DATA state. It does not have to be called before - * every word is transferred; only when the CMD/DATA state changes. This - * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX - * configuration - * - * Input Parameters: - * dev - Device-specific state data - * cmd - TRUE: The following word is a command; FALSE: the following words - * are data. - * - * Returned Value: - * OK unless an error occurs. Then a negated errno value is returned - * - ****************************************************************************/ - - #ifdef CONFIG_SPI_CMDDATA -static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) -{ -# error "spi_cmddata not implemented" - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: spi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - register uint16_t regval; - - /* Wait while the TX FIFO is full */ - - while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); - - /* Write the byte to the TX FIFO */ - - putreg16((uint8_t)wd, LPC214X_SPI1_DR); - - /* Wait for the RX FIFO not empty */ - - while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); - - /* Get the value from the RX FIFO and return it */ - - regval = getreg16(LPC214X_SPI1_DR); - spidbg("%04x->%04x\n", wd, regval); - return regval; -} - -/************************************************************************* - * Name: spi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) -{ - FAR const uint8_t *ptr = (FAR const uint8_t *)buffer; - uint8_t sr; - - /* Loop while thre are bytes remaining to be sent */ - - spidbg("nwords: %d\n", nwords); - while (nwords > 0) - { - /* While the TX FIFO is not full and there are bytes left to send */ - - while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && nwords) - { - /* Send the data */ - - putreg16((uint16_t)*ptr, LPC214X_SPI1_DR); - ptr++; - nwords--; - } - } - - /* Then discard all card responses until the RX & TX FIFOs are emptied. */ - - spidbg("discarding\n"); - do - { - /* Is there anything in the RX fifo? */ - - sr = getreg8(LPC214X_SPI1_SR); - if ((sr & LPC214X_SPI1SR_RNE) != 0) - { - /* Yes.. Read and discard */ - - (void)getreg16(LPC214X_SPI1_DR); - } - - /* There is a race condition where TFE may go true just before - * RNE goes true and this loop terminates prematurely. The nasty little - * delay in the following solves that (it could probably be tuned - * to improve performance). - */ - - else if ((sr & LPC214X_SPI1SR_TFE) != 0) - { - up_udelay(100); - sr = getreg8(LPC214X_SPI1_SR); - } - } - while ((sr & LPC214X_SPI1SR_RNE) != 0 || (sr & LPC214X_SPI1SR_TFE) == 0); -} - -/**************************************************************************** - * Name: spi_recvblock - * - * Description: - * Revice a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) -{ - FAR uint8_t *ptr = (FAR uint8_t*)buffer; - uint32_t rxpending = 0; - - /* While there is remaining to be sent (and no synchronization error has occurred) */ - - spidbg("nwords: %d\n", nwords); - while (nwords || rxpending) - { - /* Fill the transmit FIFO with 0xff... - * Write 0xff to the data register while (1) the TX FIFO is - * not full, (2) we have not exceeded the depth of the TX FIFO, - * and (3) there are more bytes to be sent. - */ - - spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords); - while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && - (rxpending < LPC214X_SPI1_FIFOSZ) && nwords) - { - putreg16(0xff, LPC214X_SPI1_DR); - nwords--; - rxpending++; - } - - /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ - - spivdbg("RX: rxpending: %d\n", rxpending); - while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE) - { - *ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR); - rxpending--; - } - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_spiinitialize - * - * Description: - * Initialize the selected SPI port - * - * Input Parameter: - * Port number (for hardware that has mutiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structre reference on succcess; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *up_spiinitialize(int port) -{ - uint32_t regval32; - uint8_t regval8; - int i; - - /* Only the SPI1 interface is supported */ - -#ifdef CONFIG_DEBUG - if (port != 1) - { - return NULL; - } -#endif - - /* Configure multiplexed pins as connected on the mcu123.com board: - * - * PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1 - * PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1 - * PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1 - * PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=10 for P0.20 (we'll control it via GPIO or FIO) - */ - - regval32 = getreg32(LPC214X_PINSEL1); - regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P018_MASK| - LPC214X_PINSEL1_P019_MASK|LPC214X_PINSEL1_P020_MASK); - regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P018_MISO1| - LPC214X_PINSEL1_P019_MOSI1|LPC214X_PINSEL1_P020_GPIO); - putreg32(regval32, LPC214X_PINSEL1); - - /* Disable chip select using P0.20 (SSEL1) (low enables) */ - - regval32 = 1 << 20; - putreg32(regval32, CS_SET_REGISTER); - regval32 |= getreg32(CS_DIR_REGISTER); - putreg32(regval32, CS_DIR_REGISTER); - - /* Enable peripheral clocking to SPI1 */ - - regval32 = getreg32(LPC214X_PCON_PCONP); - regval32 |= LPC214X_PCONP_PCSPI1; - putreg32(regval32, LPC214X_PCON_PCONP); - - /* Configure 8-bit SPI mode */ - - putreg16(LPC214X_SPI1CR0_DSS8BIT|LPC214X_SPI1CR0_FRFSPI, LPC214X_SPI1_CR0); - - /* Disable the SSP and all interrupts (we'll poll for all data) */ - - putreg8(0, LPC214X_SPI1_CR1); - putreg8(0, LPC214X_SPI1_IMSC); - - /* Set the initial clock frequency for indentification mode < 400kHz */ - - spi_setfrequency(NULL, 400000); - - /* Enable the SPI */ - - regval8 = getreg8(LPC214X_SPI1_CR1); - putreg8(regval8 | LPC214X_SPI1CR1_SSE, LPC214X_SPI1_CR1); - - for (i = 0; i < 8; i++) - { - (void)getreg16(LPC214X_SPI1_DR); - } - - return &g_spidev; -} diff --git a/nuttx/configs/mcu123-lpc214x/src/up_spi1.c b/nuttx/configs/mcu123-lpc214x/src/up_spi1.c new file mode 100644 index 000000000..61abee20a --- /dev/null +++ b/nuttx/configs/mcu123-lpc214x/src/up_spi1.c @@ -0,0 +1,602 @@ +/**************************************************************************** + * config/mcu123-lpc214x/src/up_spi1.c + * arch/arm/src/board/up_spi1.c + * + * Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * One the mcu123.com lpc214x board, the MMC slot is connect via SPI with the + * following SPI mode pinout: + * + * 1 CS: Chip select (low) - SSEL1 5 SCLK: Clock - SCK1 + * 2 DI: Data input - MOSI1 6 Vss2: Supply Voltage- GRND + * 3 Vss: Supply Voltage - GRND 7 DO: Data Output - MISO1 + * 4 Vdd: Power Supply - Vcc 8 - N/C + * + * The LPC214x supports one SPI port (SPI0) and one SSP port (SPI1). SPI1 + * is used to interface with the MMC connect + * + * SCK1 - pin 47, P0.17/CAP1.2/SCK1/MAT1.2 + * MISO1 - pin 53, P0.18/CAP1.3/MISO1/MAT1.3 + * MOSI1 - pin 54, P0.19/MAT1.2/MOSI1/CAP1.2 + * SSEL1 - pin 55, P0.20/MAT1.3/SSEL1/EINT3 + * + * SPI0 is available on the mcu123.com board (pins 27, 29, 30, and 31). + * Pin 27 is dedicated to a chip select, pins 30 and 31 connect to keys, nd + * pin 29 is unconnected. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "lpc214x_power.h" +#include "lpc214x_pinsel.h" +#include "lpc214x_spi.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SPI_DEBUG /* Define to enable debug */ +#undef SPI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SPI_DEBUG +# define spidbg lldbg +# ifdef SPI_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# undef SPI_VERBOSE +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/* Clocking */ + +#define LPC214X_CCLKFREQ (LPC214X_FOSC*LPC214X_PLL_M) +#define LPC214X_PCLKFREQ (LPC214X_CCLKFREQ/LPC214X_APB_DIV) + +/* Use either FIO or legacy GPIO */ + +#ifdef CONFIG_LPC214x_FIO +# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) +#else +# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = spi_select, + .setfrequency = spi_setfrequency, + .status = spi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = spi_cmddata, +#endif + .send = spi_send, + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, + .registercallback = 0, /* Not implemented */ +}; + +static struct spi_dev_s g_spidev = { &g_spiops }; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + /* Not implemented */ + + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: spi_select + * + * Description: + * Enable/disable the SPI slave select. The implementation of this method + * must include handshaking: If a device is selected, it must hold off + * all other attempts to select the device until the device is deselecte. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + uint32_t bit = 1 << 20; + + if (selected) + { + /* Enable slave select (low enables) */ + + spidbg("CD asserted\n"); + putreg32(bit, CS_CLR_REGISTER); + } + else + { + /* Disable slave select (low enables) */ + + spidbg("CD de-asserted\n"); + putreg32(bit, CS_SET_REGISTER); + + /* Wait for the TX FIFO not full indication */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); + putreg16(0xff, LPC214X_SPI1_DR); + + /* Wait until TX FIFO and TX shift buffer are empty */ + + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY); + + /* Wait until RX FIFO is not empty */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); + + /* Then read and discard bytes until the RX FIFO is empty */ + + do + { + (void)getreg16(LPC214X_SPI1_DR); + } + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE); + } +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + uint32_t divisor = LPC214X_PCLKFREQ / frequency; + + if (divisor < 2) + { + divisor = 2; + } + else if (divisor > 254) + { + divisor = 254; + } + + divisor = (divisor + 1) & ~1; + putreg8(divisor, LPC214X_SPI1_CPSR); + + spidbg("Frequency %d->%d\n", frequency, LPC214X_PCLKFREQ / divisor); + return LPC214X_PCLKFREQ / divisor; +} + +/**************************************************************************** + * Name: spi_status + * + * Description: + * Get SPI/MMC status + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines + * + ****************************************************************************/ + +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + /* I don't think there is anyway to determine these things on the mcu123.com + * board. + */ + + spidbg("Return SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} + +/**************************************************************************** + * Name: spi_cmddata + * + * Description: + * Some devices require and additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This is typical, for + * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. + * This function provides selection of command or data. + * + * This "latches" the CMD/DATA state. It does not have to be called before + * every word is transferred; only when the CMD/DATA state changes. This + * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX + * configuration + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + + #ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ +# error "spi_cmddata not implemented" + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + register uint16_t regval; + + /* Wait while the TX FIFO is full */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); + + /* Write the byte to the TX FIFO */ + + putreg16((uint8_t)wd, LPC214X_SPI1_DR); + + /* Wait for the RX FIFO not empty */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); + + /* Get the value from the RX FIFO and return it */ + + regval = getreg16(LPC214X_SPI1_DR); + spidbg("%04x->%04x\n", wd, regval); + return regval; +} + +/************************************************************************* + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + FAR const uint8_t *ptr = (FAR const uint8_t *)buffer; + uint8_t sr; + + /* Loop while thre are bytes remaining to be sent */ + + spidbg("nwords: %d\n", nwords); + while (nwords > 0) + { + /* While the TX FIFO is not full and there are bytes left to send */ + + while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && nwords) + { + /* Send the data */ + + putreg16((uint16_t)*ptr, LPC214X_SPI1_DR); + ptr++; + nwords--; + } + } + + /* Then discard all card responses until the RX & TX FIFOs are emptied. */ + + spidbg("discarding\n"); + do + { + /* Is there anything in the RX fifo? */ + + sr = getreg8(LPC214X_SPI1_SR); + if ((sr & LPC214X_SPI1SR_RNE) != 0) + { + /* Yes.. Read and discard */ + + (void)getreg16(LPC214X_SPI1_DR); + } + + /* There is a race condition where TFE may go true just before + * RNE goes true and this loop terminates prematurely. The nasty little + * delay in the following solves that (it could probably be tuned + * to improve performance). + */ + + else if ((sr & LPC214X_SPI1SR_TFE) != 0) + { + up_udelay(100); + sr = getreg8(LPC214X_SPI1_SR); + } + } + while ((sr & LPC214X_SPI1SR_RNE) != 0 || (sr & LPC214X_SPI1SR_TFE) == 0); +} + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + FAR uint8_t *ptr = (FAR uint8_t*)buffer; + uint32_t rxpending = 0; + + /* While there is remaining to be sent (and no synchronization error has occurred) */ + + spidbg("nwords: %d\n", nwords); + while (nwords || rxpending) + { + /* Fill the transmit FIFO with 0xff... + * Write 0xff to the data register while (1) the TX FIFO is + * not full, (2) we have not exceeded the depth of the TX FIFO, + * and (3) there are more bytes to be sent. + */ + + spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords); + while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && + (rxpending < LPC214X_SPI1_FIFOSZ) && nwords) + { + putreg16(0xff, LPC214X_SPI1_DR); + nwords--; + rxpending++; + } + + /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ + + spivdbg("RX: rxpending: %d\n", rxpending); + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE) + { + *ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR); + rxpending--; + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize the selected SPI port + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structre reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + uint32_t regval32; + uint8_t regval8; + int i; + + /* Only the SPI1 interface is supported */ + +#ifdef CONFIG_DEBUG + if (port != 1) + { + return NULL; + } +#endif + + /* Configure multiplexed pins as connected on the mcu123.com board: + * + * PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1 + * PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1 + * PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1 + * PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=10 for P0.20 (we'll control it via GPIO or FIO) + */ + + regval32 = getreg32(LPC214X_PINSEL1); + regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P018_MASK| + LPC214X_PINSEL1_P019_MASK|LPC214X_PINSEL1_P020_MASK); + regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P018_MISO1| + LPC214X_PINSEL1_P019_MOSI1|LPC214X_PINSEL1_P020_GPIO); + putreg32(regval32, LPC214X_PINSEL1); + + /* Disable chip select using P0.20 (SSEL1) (low enables) */ + + regval32 = 1 << 20; + putreg32(regval32, CS_SET_REGISTER); + regval32 |= getreg32(CS_DIR_REGISTER); + putreg32(regval32, CS_DIR_REGISTER); + + /* Enable peripheral clocking to SPI1 */ + + regval32 = getreg32(LPC214X_PCON_PCONP); + regval32 |= LPC214X_PCONP_PCSPI1; + putreg32(regval32, LPC214X_PCON_PCONP); + + /* Configure 8-bit SPI mode */ + + putreg16(LPC214X_SPI1CR0_DSS8BIT|LPC214X_SPI1CR0_FRFSPI, LPC214X_SPI1_CR0); + + /* Disable the SSP and all interrupts (we'll poll for all data) */ + + putreg8(0, LPC214X_SPI1_CR1); + putreg8(0, LPC214X_SPI1_IMSC); + + /* Set the initial clock frequency for indentification mode < 400kHz */ + + spi_setfrequency(NULL, 400000); + + /* Enable the SPI */ + + regval8 = getreg8(LPC214X_SPI1_CR1); + putreg8(regval8 | LPC214X_SPI1CR1_SSE, LPC214X_SPI1_CR1); + + for (i = 0; i < 8; i++) + { + (void)getreg16(LPC214X_SPI1_DR); + } + + return &g_spidev; +} diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt index e2c940bac..35f00e9f2 100644 --- a/nuttx/configs/olimex-lpc1766stk/README.txt +++ b/nuttx/configs/olimex-lpc1766stk/README.txt @@ -439,12 +439,12 @@ LEDs that interrupt). So a brighter LED1 means that the processor is spending less time sleeping. - When my STM32 sits IDLE -- doing absolutely nothing but processing timer interrupts -- + When my LPC1766 sits IDLE -- doing absolutely nothing but processing timer interrupts -- I see the following: 1. LED1 glows dimly due to the timer interrupts. 2. But LED2 is even more dim! The LED ON time excludes the time processing the - interrupt that re-awakens the processing. So this tells me that the STM32 is + interrupt that re-awakens the processing. So this tells me that the LPC1766 is spending more time processing timer interrupts than doing any other kind of processing. That, of course, makes sense if the system is truly idle and only processing timer interrupts. @@ -913,9 +913,9 @@ Where is one of the following: 2. Default platform/toolchain: This is how the build is configured by be default. These options can easily be re-confured, however. - CONFIG_HOST_WINDOWS=y : Windows - CONFIG_WINDOWS_CYGWIN=y : Cygwin environment on Windows - CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_HOST_WINDOWS=y : Windows + CONFIG_WINDOWS_CYGWIN=y : Cygwin environment on Windows + CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows nettest: This configuration directory may be used to enable networking using the diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 03f163ea5..ff756fb4b 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -446,6 +446,21 @@ nx11 See apps/examples/README.txt for further details. +nxlines + + This is the apps/examples/nxlines test. + + NOTES: + ------ + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + nxwm This is a special configuration setup for the NxWM window manager diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt index 6fd7bfba9..9f577b98d 100644 --- a/nuttx/configs/zp214xpa/README.txt +++ b/nuttx/configs/zp214xpa/README.txt @@ -9,114 +9,294 @@ Contents o MCU Connections o Serial Console + o Using OpenOCD and GDB with an FT2232 JTAG emulator o Configurations MCU Connections: ================ -Module Socket: --------------- -PIN NAME PIN NAME - 1 VBAT 56 VCC - 2 3V3 55 Vusb - 3 VREF 54 3V3 - 4 P0.0 53 RESET - 5 P0.1 52 P1.31 - 6 P0.2 51 P1.30 - 7 P0.3 50 P1.29 - 8 P0.4 49 P1.28 - 9 P0.5 48 P1.27 -10 P0.6 47 P1.26 -11 P0.7 46 P1.25 -12 P0.8 45 P1.24 -13 P0.9 44 P1.23 -14 P0.10 43 P1.22 -15 P0.11 42 P1.21 -16 P0.12 41 P1.20 -17 P0.13 40 P1.19 -18 P0.14 39 P1.18 -19 P0.15 38 P1.17 -20 P0.16 37 P1.16 -21 P0.17 36 P0.31 -22 P0.18 35 P0.30 -23 P0.19 34 P0.29 -24 P0.20 33 P0.28 -25 P0.21 32 P0.27 -26 P0.22 31 P0.26 -27 P0.23 30 P0.25 -28 GND 29 GND - -JTAG Debug: ------------ -PIN NAME PIN NAME - 1 VCC1 2 3V3 - 3 P1.31 NTRST 4 GND - 5 P1.28 TDI 6 GND - 7 P1.30 TMS 8 GND - 9 P1.29 TCK 10 GND -11 P1.26 RTCK 12 GND -13 P1.27 TDO 14 GND -15 RESET NRTS 16 GND -17 N/C NC0 18 GND -19 N/C NC1 20 GND - -Z28160 Net Module: ------------------- -PIN NAME PIN NAME - 1 P0.7 /CS 10 3V3 VCC - 2 P0.4 SCK 9 P1.24 RST - 3 P0.6 SI 8 N/C CLKOUT - 4 P0.5 SO 7 INT P1.25 - 5 GND 6 N/C WOL - -SPI LCD: --------- -PIN NAME - 1 3V3 3V3 - 2 VCC 5V - 3 P0.18 RESET(DO) - 4 P0.19 DI - 5 P0.20 CS - 6 P0.17 SCK - 7 P0.23 A0(RESET) - 8 N/C LED- - 9 N/C LED+(BL) -10 GND GND - -USB Interface: --------------- -Vusb, P0.26, P0.27 +The ZP213X/4XPA board is no more than an LPC2148, crystals, +USB device and several connectors. + + Module Socket: + -------------- + PIN NAME PIN NAME + 1 VBAT 56 VCC + 2 3V3 55 Vusb + 3 VREF 54 3V3 + 4 P0.0 53 RESET + 5 P0.1 52 P1.31 + 6 P0.2 51 P1.30 + 7 P0.3 50 P1.29 + 8 P0.4 49 P1.28 + 9 P0.5 48 P1.27 + 10 P0.6 47 P1.26 + 11 P0.7 46 P1.25 + 12 P0.8 45 P1.24 + 13 P0.9 44 P1.23 + 14 P0.10 43 P1.22 + 15 P0.11 42 P1.21 + 16 P0.12 41 P1.20 + 17 P0.13 40 P1.19 + 18 P0.14 39 P1.18 + 19 P0.15 38 P1.17 + 20 P0.16 37 P1.16 + 21 P0.17 36 P0.31 + 22 P0.18 35 P0.30 + 23 P0.19 34 P0.29 + 24 P0.20 33 P0.28 + 25 P0.21 32 P0.27 + 26 P0.22 31 P0.26 + 27 P0.23 30 P0.25 + 28 GND 29 GND + + JTAG Debug: + ----------- + PIN NAME PIN NAME + 1 VCC1 2 3V3 + 3 P1.31 NTRST 4 GND + 5 P1.28 TDI 6 GND + 7 P1.30 TMS 8 GND + 9 P1.29 TCK 10 GND + 11 P1.26 RTCK 12 GND + 13 P1.27 TDO 14 GND + 15 RESET NRTS 16 GND + 17 N/C NC0 18 GND + 19 N/C NC1 20 GND + + Z28160 Net Module: + ------------------ + PIN NAME PIN NAME + 1 P0.7 /CS 10 3V3 VCC + 2 P0.4 SCK 9 P1.24 RST + 3 P0.6 SI 8 N/C CLKOUT + 4 P0.5 SO 7 INT P1.25 + 5 GND 6 N/C WOL + + SPI LCD: + -------- + PIN NAME + 1 3V3 3V3 + 2 VCC 5V + 3 P0.18 RESET(DO) + 4 P0.19 DI + 5 P0.20 CS + 6 P0.17 SCK + 7 P0.23 A0(RESET) + 8 N/C LED- + 9 N/C LED+(BL) + 10 GND GND + + USB Interface: + -------------- + Vusb, P0.26, P0.27 Serial Console: =============== -Both UART0 and UART1 are always enabled. UART0 is configured to be the -serial console in these configurations. + Both UART0 and UART1 are always enabled. UART0 is configured to be the + serial console in these configurations. + + P0.0/TXD0/PWM1 Module Socket, Pin 4 + P0.1/RxD0/PWM3/EINT0 Module Socket, Pin 5 + + P0.8/TXD1/PWM4/AD1.1 Module Socket, Pin 12 + P0.9/RxD1/PWM6/EINT3 Module Socket, Pin 13 + +LCD Interface +============= + + PIN NAME PIN CONFIGURATION + 3 RESET P0.18/CAP1.3/MISO1/MAT1.3P0.18 RESET - General purpose output + 4 DI P0.19/MAT1.2/MOSI1/CAP1.2P0.19 DI - Alternate function 2 + 5 CS P0.20/MAT1.3/SSEL1/EINT3 - General purpose output + 6 SCK P0.17/CAP1.2/SCK1/MAT1.2 - Alternate function 2 + 7 A0 P0.23/VBUS - General purpose output + +ENC29J60 Interface +================== + + PIN NAME PIN CONFIGURATION + 1 /CS P0.7/SSEL0/PWM2/EINT2 - General purpose output + 2 SCK P0.4/SCK0/CAP0.1/AD0.6 - Alternate function 1 + 3 SI P0.6/MOSI0/CAP0.2/AD1.0 - Alternate function 1 + 4 SO P0.5/MISO0/MAT0.1/AD0.7 - Alternate function 1 + 7 INT P1.25/EXTIN0 - Alternal function 1 + 9 RST P1.24/TRACECLK - General purpose output + +Using OpenOCD and GDB with an FT2232 JTAG emulator +================================================== + + Downloading OpenOCD + + You can get information about OpenOCD here: http://openocd.berlios.de/web/ + and you can download it from here. http://sourceforge.net/projects/openocd/files/. + To get the latest OpenOCD with more mature lpc214x, you have to download + from the GIT archive. + + git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd + + At present, there is only the older, frozen 0.4.0 version. These, of course, + may have changed since I wrote this. + + Building OpenOCD under Cygwin: + + You can build OpenOCD for Windows using the Cygwin tools. Below are a + few notes that worked as of November 7, 2010. Things may have changed + by the time you read this, but perhaps the following will be helpful to + you: + + 1. Install Cygwin (http://www.cygwin.com/). My recommendation is to install + everything. There are many tools you will need and it is best just to + waste a little disk space and have everthing you need. Everything will + require a couple of gigbytes of disk space. + + 2. Create a directory /home/OpenOCD. + + 3. Get the FT2232 drivr from http://www.ftdichip.com/Drivers/D2XX.htm and + extract it into /home/OpenOCD/ftd2xx + + $ pwd + /home/OpenOCD + $ ls + CDM20802 WHQL Certified.zip + $ mkdir ftd2xx + $ cd ftd2xx + $ unzip ..CDM20802\ WHQL\ Certified.zip + Archive: CDM20802 WHQL Certified.zip + ... + + 3. Get the latest OpenOCD source + + $ pwd + /home/OpenOCD + $ git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd + + You will then have the source code in /home/OpenOCD/openocd + + 4. Build OpenOCD for the FT22322 interface + + $ pwd + /home/OpenOCD/openocd + $ ./bootstrap + + Jim is a tiny version of the Tcl scripting language. It is needed + by more recent versions of OpenOCD. Build libjim.a using the following + instructions: + + $ git submodule init + $ git submodule update + $ cd jimtcl + $ ./configure --with-jim-ext=nvp + $ make + $ make install + + Configure OpenOCD: + + $ ./configure --enable-maintainer-mode --disable-werror --disable-shared \ + --enable-ft2232_ftd2xx --with-ftd2xx-win32-zipdir=/home/OpenOCD/ftd2xx \ + LDFLAGS="-L/home/OpenOCD/openocd/jimtcl" + + Then build OpenOCD and its HTML documentation: + + $ make + $ make html + + The result of the first make will be the "openocd.exe" will be + created in the folder /home/openocd/src. The following command + will install OpenOCD to a standard location (/usr/local/bin) + using using this command: + + $ make install + + Helper Scripts. + + I have been using the Olimex ARM-USB-OCD JTAG debugger with the + ZP213X/4XPA. OpenOCD requires a configuration file. I keep the + one I used last here: + + configs/zpa214xpa/tools/olimex.cfg + + However, the "correct" configuration script to use with OpenOCD may + change as the features of OpenOCD evolve. So you should at least + compare that olimex.cfg file with configuration files in + /usr/local/share/openocd/scripts/target (or /home/OpenOCD/openocd/tcl/target). + + There is also a script on the tools/ directory that I use to start + the OpenOCD daemon on my system called oocd.sh. That script will + probably require some modifications to work in another environment: + + - Possibly the value of OPENOCD_PATH and TARGET_PATH + - It assumes that the correct script to use is the one at + configs/zp214xpa/tools/olimex.cfg -P0.0/TXD0/PWM1 Module Socket, Pin 4 -P0.1/RxD0/PWM3/EINT0 Module Socket, Pin 5 + Starting OpenOCD -P0.8/TXD1/PWM4/AD1.1 Module Socket, Pin 12 -P0.9/RxD1/PWM6/EINT3 Module Socket, Pin 13 + Then you should be able to start the OpenOCD daemon like: + + configs/zp214xpa/tools/oocd.sh $PWD + + If you use the setenv.sh file, that the path to oocd.sh will be added + to your PATH environment variabl. So, in that case, the command simplifies + to just: + + oocd.sh $PWD + + Where it is assumed that you are executing oocd.sh from the top-level + directory where NuttX is installed. $PWD will be the path to the + top-level NuttX directory. + + Connecting GDB + + Once the OpenOCD daemon has been started, you can connect to it via + GDB using the following GDB command: + + arm-nuttx-elf-gdb + (gdb) target remote localhost:3333 + + NOTE: The name of your GDB program may differ. For example, with the + CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb. + + After starting GDB, you can load the NuttX ELF file: + + (gdb) symbol-file nuttx + (gdb) load nuttx + + NOTES: + 1. Loading the symbol-file is only useful if you have built NuttX to + include debug symbols (by setting CONFIG_DEBUG_SYMBOLS=y in the + .config file). + + OpenOCD will support several special 'monitor' commands. These + GDB commands will send comments to the OpenOCD monitor. Here + are a couple that you will need to use: + + (gdb) monitor reset + (gdb) monitor halt + + NOTES: + 1. The MCU must be halted using 'mon halt' prior to loading code. + 2. Reset will restart the processor after loading code. + 3. The 'monitor' command can be abbreviated as just 'mon'. Configurations: =============== -Each NXP LPC214x configuration is maintained in a sudirectory and -can be selected as follow: + Each NXP LPC214x configuration is maintained in a sudirectory and + can be selected as follow: cd tools ./configure.sh zp214xpa/ cd - . ./setenv.sh -Where is one of the following: + Where is one of the following: -nsh: ----- + nsh: + ---- - Configures the NuttShell (nsh) located at examples/nsh. The - Configuration enables only the serial NSH interfaces. + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables only the serial NSH interfaces. NOTES: @@ -131,6 +311,30 @@ nsh: 2. Default platform/toolchain: - CONFIG_HOST_LINUX=y : Windows + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + nxlines: + -------- + + This is the apps/examples/nxlines test using the UG_2864AMBAG01 board + from The0.net that plugs into the "SPI LCD" connector on the ZP3X4XPA + board. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary diff --git a/nuttx/configs/zp214xpa/nxlines/Make.defs b/nuttx/configs/zp214xpa/nxlines/Make.defs new file mode 100644 index 000000000..274eb8d72 --- /dev/null +++ b/nuttx/configs/zp214xpa/nxlines/Make.defs @@ -0,0 +1,128 @@ +############################################################################## +# configs/zp214xpa/nxlines/Make.defs +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +# The default value for CROSSDEV can be overridden from the make command line: +# make -- Will build for the NuttX buildroot toolchain +# make CROSSDEV=arm-eabi- -- Will build for the devkitARM toolchain +# make CROSSDEV=arm-none-eabi- -- Will build for the CodeSourcery toolchain +# make CROSSDEV=arm-nuttx-elf- -- Will build for the NuttX buildroot toolchain + +CROSSDEV = arm-nuttx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +HOSTOS = ${shell uname -o 2>/dev/null || echo "Other"} + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(ARCHCCMAJOR),4) +ifneq ($(HOSTOS),Cygwin) +OBJCOPYARGS = -R .note -R .note.gnu.build-id -R .comment +endif +endif + +ifeq ($(CROSSDEV),arm-nuttx-elf-) + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script + MAXOPTIMIZATION = -Os +else + WINTOOL = y + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(ARCHCCMAJOR),4) + ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft +else + ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = diff --git a/nuttx/configs/zp214xpa/nxlines/defconfig b/nuttx/configs/zp214xpa/nxlines/defconfig new file mode 100644 index 000000000..03a6bf72c --- /dev/null +++ b/nuttx/configs/zp214xpa/nxlines/defconfig @@ -0,0 +1,606 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM3S is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +CONFIG_ARCH_CHIP_LPC214X=y +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_ARM7TDMI=y +CONFIG_ARCH_FAMILY="arm" +CONFIG_ARCH_CHIP="lpc214x" +CONFIG_ARCH_HAVE_LOWVECTORS=y +# CONFIG_ARCH_LOWVECTORS is not set +CONFIG_BOARD_LOOPSPERMSEC=3270 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARM Configuration Options +# +# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARM_TOOLCHAIN_GNU_EABI=y + +# +# LPC214x Configuration Options +# +CONFIG_ARCH_CHIP_LPC2148=y + +# +# LPC214x Initialization Options +# +# CONFIG_EXTMEM_MODE is not set +# CONFIG_RAM_MODE is not set +CONFIG_DEFAULT_MODE=y +CONFIG_CODE_BASE=0x00000000 +CONFIG_PLL_SETUP=y +CONFIG_MAM_SETUP=y +CONFIG_APBDIV_SETUP=y +CONFIG_APBDIV_VALUE=1 +# CONFIG_EMC_SETUP is not set +# CONFIG_BCFG0_SETUP is not set +# CONFIG_BCFG1_SETUP is not set +# CONFIG_BCFG2_SETUP is not set +# CONFIG_BCFG3_SETUP is not set +CONFIG_ADC_SETUP=y + +# +# LPC214x Peripheral Support +# +CONFIG_LPC214X_UART0=y +CONFIG_LPC214X_UART1=y +# CONFIG_LPC214x_FIO is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x40000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_MCU123 is not set +CONFIG_ARCH_BOARD_ZP214XPA=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="zp214xpa" + +# +# Common Board Options +# + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2008 +CONFIG_START_MONTH=10 +CONFIG_START_DAY=1 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nxlines_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_SPI_CMDDATA=y +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +CONFIG_LCD=y +# CONFIG_LCD_NOGETRUN is not set +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_MAXPOWER=1 +# CONFIG_LCD_P14201 is not set +# CONFIG_LCD_NOKIA6100 is not set +# CONFIG_LCD_UG9664HSWAG01 is not set +CONFIG_LCD_UG2864AMBAG01=y +CONFIG_UG2864AMBAG01_SPIMODE=3 +CONFIG_UG2864AMBAG01_FREQUENCY=3500000 +CONFIG_UG2864AMBAG01_NINTERFACES=1 +# CONFIG_LCD_SSD1289 is not set +CONFIG_LCD_LANDSCAPE=y +# CONFIG_LCD_PORTRAIT is not set +# CONFIG_LCD_RPORTRAIT is not set +# CONFIG_LCD_RLANDSCAPE is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_UART1_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=38400 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=38400 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_FS_FAT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +CONFIG_NX=y +CONFIG_NX_LCDDRIVER=y +CONFIG_NX_NPLANES=1 +CONFIG_NX_WRITEONLY=y + +# +# Supported Pixel Depths +# +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_NX_DISABLE_2BPP=y +CONFIG_NX_DISABLE_4BPP=y +CONFIG_NX_DISABLE_8BPP=y +CONFIG_NX_DISABLE_16BPP=y +CONFIG_NX_DISABLE_24BPP=y +CONFIG_NX_DISABLE_32BPP=y +CONFIG_NX_PACKEDMSFIRST=y + +# +# Input Devices +# +# CONFIG_NX_MOUSE is not set +# CONFIG_NX_KBD is not set + +# +# Framed Window Borders +# +CONFIG_NXTK_BORDERWIDTH=2 +CONFIG_NXTK_BORDERCOLOR1=0x01 +CONFIG_NXTK_BORDERCOLOR2=0x01 +CONFIG_NXTK_BORDERCOLOR3=0x01 +# CONFIG_NXTK_AUTORAISE is not set + +# +# Font Selections +# +CONFIG_NXFONTS_CHARBITS=7 +CONFIG_NXFONT_MONO5X8=y +# CONFIG_NXFONT_SANS17X22 is not set +# CONFIG_NXFONT_SANS20X26 is not set +# CONFIG_NXFONT_SANS23X27 is not set +# CONFIG_NXFONT_SANS22X29 is not set +# CONFIG_NXFONT_SANS28X37 is not set +# CONFIG_NXFONT_SANS39X48 is not set +# CONFIG_NXFONT_SANS17X23B is not set +# CONFIG_NXFONT_SANS20X27B is not set +# CONFIG_NXFONT_SANS22X29B is not set +# CONFIG_NXFONT_SANS28X37B is not set +# CONFIG_NXFONT_SANS40X49B is not set +# CONFIG_NXFONT_SERIF22X29 is not set +# CONFIG_NXFONT_SERIF29X37 is not set +# CONFIG_NXFONT_SERIF38X48 is not set +# CONFIG_NXFONT_SERIF22X28B is not set +# CONFIG_NXFONT_SERIF27X38B is not set +# CONFIG_NXFONT_SERIF38X49B is not set +# CONFIG_NXCONSOLE is not set + +# +# NX Multi-user only options +# +# CONFIG_NX_MULTIUSER is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_VPLANE=0 +CONFIG_EXAMPLES_NXLINES_DEVNO=0 +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00 +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x01 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x01 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x00 +CONFIG_EXAMPLES_NXLINES_BPP=1 +CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WLAN is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/zp214xpa/nxlines/setenv.sh b/nuttx/configs/zp214xpa/nxlines/setenv.sh new file mode 100755 index 000000000..77f1425e5 --- /dev/null +++ b/nuttx/configs/zp214xpa/nxlines/setenv.sh @@ -0,0 +1,65 @@ +#!/bin/bash +# configs/zp214xpa/nxlines/setenv.sh +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# The zp214xpa/tools directory +export LPCTOOL_DIR="${WD}/configs/zp214xpa/tools" + +# Add the path to the toolchain and tools directory to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/zp214xpa/src/Makefile b/nuttx/configs/zp214xpa/src/Makefile index 8f1e1c05d..571b43b07 100644 --- a/nuttx/configs/zp214xpa/src/Makefile +++ b/nuttx/configs/zp214xpa/src/Makefile @@ -49,6 +49,10 @@ ASRCS = AOBJS = $(ASRCS:.S=$(OBJEXT)) CSRCS = +ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) +CSRCS += up_ug2864ambag01.c up_spi1.c +endif + COBJS = $(CSRCS:.c=$(OBJEXT)) SRCS = $(ASRCS) $(CSRCS) diff --git a/nuttx/configs/zp214xpa/src/up_spi1.c b/nuttx/configs/zp214xpa/src/up_spi1.c new file mode 100644 index 000000000..563d63589 --- /dev/null +++ b/nuttx/configs/zp214xpa/src/up_spi1.c @@ -0,0 +1,644 @@ +/**************************************************************************** + * config/zp214xpa/src/up_spi1.c + * arch/arm/src/board/up_spi1.c + * + * Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * LCD Interface + * + * PIN NAME PIN CONFIGURATION + * 3 RESET P0.18/CAP1.3/MISO1/MAT1.3P0.18 - General purpose output + * 4 DI P0.19/MAT1.2/MOSI1/CAP1.2P0.19 - Alternate function 2 + * 5 CS P0.20/MAT1.3/SSEL1/EINT3 - General purpose output + * 6 SCK P0.17/CAP1.2/SCK1/MAT1.2 - Alternate function 2 + * 7 A0 P0.23/VBUS - General purpose output + * + * ENC29J60 Interface + * + * PIN NAME PIN CONFIGURATION + * 1 /CS P0.7/SSEL0/PWM2/EINT2 - General purpose output + * 2 SCK P0.4/SCK0/CAP0.1/AD0.6 - Alternate function 1 + * 3 SI P0.6/MOSI0/CAP0.2/AD1.0 - Alternate function 1 + * 4 SO P0.5/MISO0/MAT0.1/AD0.7 - Alternate function 1 + * 7 INT P1.25/EXTIN0 - Alternal function 1 + * 9 RST P1.24/TRACECLK + * + * This file provides support only for the LCD interface on SPI1. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "lpc214x_power.h" +#include "lpc214x_pinsel.h" +#include "lpc214x_spi.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SPI_DEBUG /* Define to enable debug */ +#undef SPI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SPI_DEBUG +# define spidbg lldbg +# ifdef SPI_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# undef SPI_VERBOSE +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/* Clocking */ + +#define LPC214X_CCLKFREQ (LPC214X_FOSC*LPC214X_PLL_M) +#define LPC214X_PCLKFREQ (LPC214X_CCLKFREQ/LPC214X_APB_DIV) + +/* Use either FIO or legacy GPIO */ + +#ifdef CONFIG_LPC214x_FIO +# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) +#else +# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = spi_select, + .setfrequency = spi_setfrequency, + .status = spi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = spi_cmddata, +#endif + .send = spi_send, + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, + .registercallback = 0, /* Not implemented */ +}; + +static struct spi_dev_s g_spidev = { &g_spiops }; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + /* Not implemented */ + + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: spi_select + * + * Description: + * Enable/disable the SPI slave select. The implementation of this method + * must include handshaking: If a device is selected, it must hold off + * all other attempts to select the device until the device is deselecte. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + uint32_t bit = 1 << 20; + + /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the + * only thing on the bus. + */ + + if (selected) + { + /* Enable slave select (low enables) */ + + spidbg("CD asserted\n"); + putreg32(bit, CS_CLR_REGISTER); + } + else + { + /* Disable slave select (low enables) */ + + spidbg("CD de-asserted\n"); + putreg32(bit, CS_SET_REGISTER); + + /* Wait for the TX FIFO not full indication */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); + putreg16(0xff, LPC214X_SPI1_DR); + + /* Wait until TX FIFO and TX shift buffer are empty */ + + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_BSY); + + /* Wait until RX FIFO is not empty */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); + + /* Then read and discard bytes until the RX FIFO is empty */ + + do + { + (void)getreg16(LPC214X_SPI1_DR); + } + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE); + } +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + uint32_t divisor = LPC214X_PCLKFREQ / frequency; + + if (divisor < 2) + { + divisor = 2; + } + else if (divisor > 254) + { + divisor = 254; + } + + divisor = (divisor + 1) & ~1; + putreg8(divisor, LPC214X_SPI1_CPSR); + + spidbg("Frequency %d->%d\n", frequency, LPC214X_PCLKFREQ / divisor); + return LPC214X_PCLKFREQ / divisor; +} + +/**************************************************************************** + * Name: spi_status + * + * Description: + * Get SPI/MMC status + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines + * + ****************************************************************************/ + +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + spidbg("Return 0\n"); + return 0; +} + +/**************************************************************************** + * Name: spi_cmddata + * + * Description: + * Some devices require and additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This is typical, for + * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. + * This function provides selection of command or data. + * + * This "latches" the CMD/DATA state. It does not have to be called before + * every word is transferred; only when the CMD/DATA state changes. This + * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX + * configuration + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ + uint32_t bit = 1 << 23; + + /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the + * only thing on the bus. + */ + + /* "This is the Data/Command control pad which determines whether the + * data bits are data or a command. + * + * A0 = H: the inputs at D0 to D7 are treated as display data. + * A0 = L: the inputs at D0 to D7 are transferred to the command registers." + */ + + if (cmd) + { + /* L: the inputs at D0 to D7 are transferred to the command registers */ + + spidbg("Command\n"); + putreg32(bit, CS_CLR_REGISTER); + } + else + { + /* H: the inputs at D0 to D7 are treated as display data. */ + + spidbg("CD de-asserted\n"); + putreg32(bit, CS_SET_REGISTER); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + register uint16_t regval; + + /* Wait while the TX FIFO is full */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF)); + + /* Write the byte to the TX FIFO */ + + putreg16((uint8_t)wd, LPC214X_SPI1_DR); + + /* Wait for the RX FIFO not empty */ + + while (!(getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE)); + + /* Get the value from the RX FIFO and return it */ + + regval = getreg16(LPC214X_SPI1_DR); + spidbg("%04x->%04x\n", wd, regval); + return regval; +} + +/************************************************************************* + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + FAR const uint8_t *ptr = (FAR const uint8_t *)buffer; + uint8_t sr; + + /* Loop while thre are bytes remaining to be sent */ + + spidbg("nwords: %d\n", nwords); + while (nwords > 0) + { + /* While the TX FIFO is not full and there are bytes left to send */ + + while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && nwords) + { + /* Send the data */ + + putreg16((uint16_t)*ptr, LPC214X_SPI1_DR); + ptr++; + nwords--; + } + } + + /* Then discard all card responses until the RX & TX FIFOs are emptied. */ + + spidbg("discarding\n"); + do + { + /* Is there anything in the RX fifo? */ + + sr = getreg8(LPC214X_SPI1_SR); + if ((sr & LPC214X_SPI1SR_RNE) != 0) + { + /* Yes.. Read and discard */ + + (void)getreg16(LPC214X_SPI1_DR); + } + + /* There is a race condition where TFE may go true just before + * RNE goes true and this loop terminates prematurely. The nasty little + * delay in the following solves that (it could probably be tuned + * to improve performance). + */ + + else if ((sr & LPC214X_SPI1SR_TFE) != 0) + { + up_udelay(100); + sr = getreg8(LPC214X_SPI1_SR); + } + } + while ((sr & LPC214X_SPI1SR_RNE) != 0 || (sr & LPC214X_SPI1SR_TFE) == 0); +} + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + FAR uint8_t *ptr = (FAR uint8_t*)buffer; + uint32_t rxpending = 0; + + /* While there is remaining to be sent (and no synchronization error has occurred) */ + + spidbg("nwords: %d\n", nwords); + while (nwords || rxpending) + { + /* Fill the transmit FIFO with 0xff... + * Write 0xff to the data register while (1) the TX FIFO is + * not full, (2) we have not exceeded the depth of the TX FIFO, + * and (3) there are more bytes to be sent. + */ + + spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords); + while ((getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_TNF) && + (rxpending < LPC214X_SPI1_FIFOSZ) && nwords) + { + putreg16(0xff, LPC214X_SPI1_DR); + nwords--; + rxpending++; + } + + /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ + + spivdbg("RX: rxpending: %d\n", rxpending); + while (getreg8(LPC214X_SPI1_SR) & LPC214X_SPI1SR_RNE) + { + *ptr++ = (uint8_t)getreg16(LPC214X_SPI1_DR); + rxpending--; + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize the selected SPI port + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structre reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + uint32_t regval32; + uint8_t regval8; + int i; + + /* Only the SPI1 interface is supported */ + +#ifdef CONFIG_DEBUG + if (port != 1) + { + return NULL; + } +#endif + + /* Configure multiplexed pins as connected on the ZP213X/4XPA board: + * + * PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1 + * PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1 + * (This is the RESET line for the UG_2864AMBAG01, + * although it is okay to configure it as an input too) + * PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1 + * PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=00 for P0.20 (we'll control it via GPIO or FIO) + * PINSEL1 P0.23/VBUS Bits 12-13=00 for P0.21 (we'll control it via GPIO or FIO) + */ + + regval32 = getreg32(LPC214X_PINSEL1); +#ifdef CONFIG_LCD_UG2864AMBAG01 + regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P019_MASK| + LPC214X_PINSEL1_P020_MASK|LPC214X_PINSEL1_P023_MASK); + regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P019_MOSI1| + LPC214X_PINSEL1_P020_GPIO|LPC214X_PINSEL1_P023_GPIO); +#else + regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P018_MASK + LPC214X_PINSEL1_P019_MASK|LPC214X_PINSEL1_P020_MASK| + LPC214X_PINSEL1_P023_MASK); + regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P018_MISO1| + LPC214X_PINSEL1_P019_MOSI1|LPC214X_PINSEL1_P020_GPIO| + LPC214X_PINSEL1_P023_GPIO); +#endif + putreg32(regval32, LPC214X_PINSEL1); + + /* De-select chip select using P0.20 (SSEL1) (low enables) and select A0 + * for commands (also low) + */ + + regval32 = (1 << 20) || (1 << 23); + putreg32(regval32, CS_SET_REGISTER); + regval32 |= getreg32(CS_DIR_REGISTER); + putreg32(regval32, CS_DIR_REGISTER); + + /* Enable peripheral clocking to SPI1 */ + + regval32 = getreg32(LPC214X_PCON_PCONP); + regval32 |= LPC214X_PCONP_PCSPI1; + putreg32(regval32, LPC214X_PCON_PCONP); + + /* Configure 8-bit SPI mode */ + + putreg16(LPC214X_SPI1CR0_DSS8BIT|LPC214X_SPI1CR0_FRFSPI, LPC214X_SPI1_CR0); + + /* Disable the SSP and all interrupts (we'll poll for all data) */ + + putreg8(0, LPC214X_SPI1_CR1); + putreg8(0, LPC214X_SPI1_IMSC); + + /* Set the initial clock frequency for indentification mode < 400kHz */ + + spi_setfrequency(NULL, 400000); + + /* Enable the SPI */ + + regval8 = getreg8(LPC214X_SPI1_CR1); + putreg8(regval8 | LPC214X_SPI1CR1_SSE, LPC214X_SPI1_CR1); + + for (i = 0; i < 8; i++) + { + (void)getreg16(LPC214X_SPI1_DR); + } + + return &g_spidev; +} diff --git a/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c new file mode 100644 index 000000000..164518db3 --- /dev/null +++ b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * config/zp214xpa/src/up_ug2864ambag01.c + * arch/arm/src/board/up_ug2864ambag01.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc214x_pinsel.h" + +#ifdef CONFIG_LCD_UG2864AMBAG01 + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* The pin configurations here requires that SPI1 is avaialable */ + +/* SPI should be configured with CMD/DATA support (and no transfer methods) */ + +#ifndef CONFIG_SPI_CMDDATA +# error "The OLED driver requires CONFIG_SPI_CMDDATA in the configuration" +#endif + +/* Pin Configuration ********************************************************/ +/* UG-2864AMBAG01 OLED Display: + * + * PIN NAME PIN CONFIGURATION + * 1 3V3 + * 2 5V + * 3 RESET P0.18/CAP1.3/MISO1/MAT1.3P0.18 RESET - General purpose output + * 4 DI P0.19/MAT1.2/MOSI1/CAP1.2P0.19 DI - Alternate function 2 + * 5 CS P0.20/MAT1.3/SSEL1/EINT3 - General purpose output + * 6 SCK P0.17/CAP1.2/SCK1/MAT1.2 - Alternate function 2 + * 7 A0 P0.23/VBUS - General purpose output + * 8 N/C LED- + * 9 N/C LED+ (BL) + * 10 GND + * + * Definitions and configuration for DO, DI, CS, in up_spi1.c + */ + +/* Use either FIO or legacy GPIO */ + +#ifdef CONFIG_LPC214x_FIO +# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) +#else +# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) +# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) +# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_LCD +# define lcddbg(format, arg...) dbg(format, ##arg) +# define lcdvdbg(format, arg...) vdbg(format, ##arg) +#else +# define lcddbg(x...) +# define lcdvdbg(x...) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_nxdrvinit + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) +{ + FAR struct spi_dev_s *spi; + FAR struct lcd_dev_s *dev; + uint32_t regval32; + uint32_t bits32; + + /* Configure multiplexed pins as connected on the ZP213X/4XPA board: + * + * PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=00 for P0.18 + */ + + regval32 = getreg32(LPC214X_PINSEL1); + regval32 &= ~LPC214X_PINSEL1_P018_MASK; + regval32 |= LPC214X_PINSEL1_P018_GPIO; + putreg32(regval32, LPC214X_PINSEL1); + + /* Set the RESET line low, putting the OLED into the reset state. */ + + bits32 = (1 << 18); + putreg32(bits32, CS_CLR_REGISTER); + regval32 = getreg32(CS_DIR_REGISTER); + putreg32(regval32 | bits32, CS_DIR_REGISTER); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + putreg32(bits32, CS_SET_REGISTER); + + /* Get the SPI1 port interface */ + + spi = up_spiinitialize(1); + if (!spi) + { + lcddbg("Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ug2864ambag01_initialize(spi, devno); + if (!dev) + { + lcddbg("Failed to bind SPI port 1 to OLED %d: %d\n", devno); + } + else + { + lcdvdbg("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + (void)dev->setpower(dev, CONFIG_LCD_MAXPOWER); + return dev; + } + } + + return NULL; +} +#endif /* CONFIG_LCD_UG2864AMBAG01 */ diff --git a/nuttx/configs/zp214xpa/tools/olimex.cfg b/nuttx/configs/zp214xpa/tools/olimex.cfg new file mode 100755 index 000000000..09f373993 --- /dev/null +++ b/nuttx/configs/zp214xpa/tools/olimex.cfg @@ -0,0 +1,62 @@ +# NXP LPC2148 ARM7TDMI + +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG A" +ft2232_layout "olimex-jtag" +ft2232_vid_pid 0x15BA 0x0003 + +# Use RCLK. If RCLK is not available fall back to 500kHz. +# +# Depending on cabling you might be able to eek this up to 2000kHz. +jtag_rclk 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2148 +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4f1f0f0f +} + +adapter_nsrst_delay 200 +jtag_ntrst_delay 200 + +# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate +# JTAG, power-on reset is not enough, i.e. you need to perform a +# reset before being able to talk to the LPC2148, attach is not possible. + +reset_config trst_and_srst + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { + # Force target into ARM state + arm core_state arm + + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See section 7.1 on page 32 ("Memory Mapping control register") in + # "UM10139: Volume 1: LPC214x User Manual", Rev. 02 -- 25 July 2006. + # http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2141.lpc2142.lpc2144.lpc2146.lpc2148.pdf + mwb 0xE01FC040 0x01 +} + +# flash bank lpc2000 0 0 [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum diff --git a/nuttx/configs/zp214xpa/tools/oocd.sh b/nuttx/configs/zp214xpa/tools/oocd.sh new file mode 100755 index 000000000..f1e49344d --- /dev/null +++ b/nuttx/configs/zp214xpa/tools/oocd.sh @@ -0,0 +1,52 @@ +#!/bin/sh +# +# See configs/zp214xpa/README.txt for information about +# this file. + +TOPDIR=$1 +USAGE="$0 [-d]" +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment +# the following to run directly from the build directory +#OPENOCD_PATH="/home/OpenOCD/openocd/src" +#TARGET_PATH="/home/OpenOCD/openocd/tcl" +OPENOCD_PATH="/usr/local/bin" +TARGET_PATH="/usr/local/share/openocd/scripts" + +OPENOCD_EXE=openocd.exe +OPENOCD_CFG="${TOPDIR}/configs/zp214xpa/tools/olimex.cfg" +OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}" + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +if [ ! -d ${OPENOCD_PATH} ]; then + echo "OpenOCD path does not exist: ${OPENOCD_PATH}" + exit 1 +fi +if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then + echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f ${OPENOCD_CFG} ]; then + echo "OpenOCD config file does not exist: ${OPENOCD_CFG}" + exit 1 +fi + +echo "Starting OpenOCD" +cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; } +${OPENOCD_EXE} ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" + + + + diff --git a/nuttx/configs/zp214xpa/tools/usb-repair.txt b/nuttx/configs/zp214xpa/tools/usb-repair.txt new file mode 100644 index 000000000..83d7598a5 --- /dev/null +++ b/nuttx/configs/zp214xpa/tools/usb-repair.txt @@ -0,0 +1,25 @@ +https://www.olimex.com/dev/pdf/ARM/JTAG/Repair%20Procedure%20for%20OpenOcd-Rev.%20G%20drivers.pdf + +Repair procedure for ARM-USB-OCD drivers + +1. Uninstalling ARM-USB-OCD drivers +------------------------------------- +1.1. Connect your programmer/debugger to your computer, open Device Manager + and uninstall the drivers for ARM-USB-OCD. +1.2. After you have uninstalled ARM-USB-TINY driver from Device Manager, + disconnect the programmer from your computer. +1.3. Now you should download FTClean.exe from here: + http://www.ftdichip.com/Support/Utilities/FTClean.zip. +1.4. After download is complete extract the "*.zip" file, open folder FTClean, + and run FTClean.exe +1.5. Ror VID (Hex) select "Other". And after that fill the first box with 15ba + and "PID (Hex)" with 0004. +1.6. Press "Clean System" button. Make sure that all FTDI devices are + disconnected. (My require administrator privileges). + +2. Re-installing the ARM-USB-OCD driver +--------------------------------------- +2.1 Connect the programmer/debugger to the computer. +2.2 When prompted, browse to the C:\gccfd\DRIVERS\ARM-USB-OCD-DRIVER + directory and install. (A different driver is required for OpenOCD + 0.4.0. That driver is available from the olimex.com web site). diff --git a/nuttx/graphics/Kconfig b/nuttx/graphics/Kconfig index 18b1e1ab9..b56a6cb5c 100644 --- a/nuttx/graphics/Kconfig +++ b/nuttx/graphics/Kconfig @@ -178,6 +178,12 @@ config NXFONTS_CHARBITS The number of bits in the character set. Current options are only 7 and 8. The default is 7. +config NXFONT_MONO5X8 + bool "Mono 5x8" + default n + ---help--- + Tiny mono-spaced 5x8 font (font ID FONTID_MONO5X8 = 18) + config NXFONT_SANS17X22 bool "Sans 17x22" default n diff --git a/nuttx/include/nuttx/nx/nxfonts.h b/nuttx/include/nuttx/nx/nxfonts.h index 8e7289b2a..91bce0036 100644 --- a/nuttx/include/nuttx/nx/nxfonts.h +++ b/nuttx/include/nuttx/nx/nxfonts.h @@ -113,6 +113,11 @@ #elif defined(CONFIG_NXFONT_SERIF38X49B) # define NXFONT_DEFAULT FONTID_SERIF38X49B +/* Mono-space fonts */ + +#elif defined(CONFIG_NXFONT_MONO5X8) +# define NXFONT_DEFAULT FONTID_MONO5X8 + #endif /**************************************************************************** -- cgit v1.2.3 From e88ff3cdfaf26f8dec8f2d634cb3bc4390c6c464 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 30 Dec 2012 21:12:43 +0000 Subject: Fix the nxlines configuration for the zp214xpa board git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5467 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/nxlines/nxlines_main.c | 1 + nuttx/ChangeLog | 6 ++-- nuttx/configs/mcu123-lpc214x/src/up_spi1.c | 26 +++++++--------- nuttx/configs/zp214xpa/README.txt | 2 ++ nuttx/configs/zp214xpa/src/up_spi1.c | 44 ++++++++++++++++++--------- nuttx/configs/zp214xpa/src/up_ug2864ambag01.c | 29 ++++++++++++------ nuttx/drivers/lcd/ug-2864ambag01.c | 4 +-- 7 files changed, 68 insertions(+), 44 deletions(-) diff --git a/apps/examples/nxlines/nxlines_main.c b/apps/examples/nxlines/nxlines_main.c index 331fab631..e4632bb21 100644 --- a/apps/examples/nxlines/nxlines_main.c +++ b/apps/examples/nxlines/nxlines_main.c @@ -191,6 +191,7 @@ static inline int nxlines_initialize(void) g_nxlines.code = NXEXIT_NXOPEN; return ERROR; } + return OK; } diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 56cc5515d..daa1e068c 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3843,6 +3843,6 @@ * configs/sim/nxlines: Add an nxlines configuration for the simulator. * configs/zp214xpa/nxlines: Add an nxlines configuration for the - ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). As of this - writing (2012-12-30), I see only garbage on the display each time - the display is updated. + ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). Working + as of 2012-12-30. + diff --git a/nuttx/configs/mcu123-lpc214x/src/up_spi1.c b/nuttx/configs/mcu123-lpc214x/src/up_spi1.c index 61abee20a..c10144d88 100644 --- a/nuttx/configs/mcu123-lpc214x/src/up_spi1.c +++ b/nuttx/configs/mcu123-lpc214x/src/up_spi1.c @@ -85,20 +85,16 @@ * Definitions ****************************************************************************/ -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ +/* Enables debug output from this file */ -#undef SPI_DEBUG /* Define to enable debug */ -#undef SPI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SPI_DEBUG +#ifdef CONFIG_DEBUG_SPI # define spidbg lldbg -# ifdef SPI_VERBOSE +# ifdef CONFIG_DEBUG_VERBOSE # define spivdbg lldbg # else # define spivdbg(x...) # endif #else -# undef SPI_VERBOSE # define spidbg(x...) # define spivdbg(x...) #endif @@ -125,17 +121,17 @@ ****************************************************************************/ #ifndef CONFIG_SPI_OWNBUS -static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); #endif -static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); -static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA -static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); /**************************************************************************** * Private Data @@ -224,14 +220,14 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel { /* Enable slave select (low enables) */ - spidbg("CD asserted\n"); + spidbg("CS asserted\n"); putreg32(bit, CS_CLR_REGISTER); } else { /* Disable slave select (low enables) */ - spidbg("CD de-asserted\n"); + spidbg("CS de-asserted\n"); putreg32(bit, CS_SET_REGISTER); /* Wait for the TX FIFO not full indication */ diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt index 9f577b98d..58a2242d0 100644 --- a/nuttx/configs/zp214xpa/README.txt +++ b/nuttx/configs/zp214xpa/README.txt @@ -338,3 +338,5 @@ Configurations: CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc) CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + 3. Verified as of this writing (2012-12-30). diff --git a/nuttx/configs/zp214xpa/src/up_spi1.c b/nuttx/configs/zp214xpa/src/up_spi1.c index 563d63589..1ee1cac32 100644 --- a/nuttx/configs/zp214xpa/src/up_spi1.c +++ b/nuttx/configs/zp214xpa/src/up_spi1.c @@ -86,20 +86,16 @@ * Definitions ****************************************************************************/ -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ +/* Enables debug output from this file */ -#undef SPI_DEBUG /* Define to enable debug */ -#undef SPI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SPI_DEBUG +#ifdef CONFIG_DEBUG_SPI # define spidbg lldbg -# ifdef SPI_VERBOSE +# ifdef CONFIG_DEBUG_VERBOSE # define spivdbg lldbg # else # define spivdbg(x...) # endif #else -# undef SPI_VERBOSE # define spidbg(x...) # define spivdbg(x...) #endif @@ -112,10 +108,12 @@ /* Use either FIO or legacy GPIO */ #ifdef CONFIG_LPC214x_FIO +# define CS_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET) # define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) # define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) # define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) #else +# define CS_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET) # define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) # define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) # define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) @@ -130,7 +128,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock); #endif static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); -static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif @@ -193,7 +191,7 @@ static struct spi_dev_s g_spidev = { &g_spiops }; #ifndef CONFIG_SPI_OWNBUS static int spi_lock(FAR struct spi_dev_s *dev, bool lock) { - /* Not implemented */ + /* Not implemented -- the UG_2864AMBAG01 is the only device on SPI1 */ return -ENOSYS; } @@ -219,25 +217,32 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { +#ifdef CONFIG_DEBUG_SPI + uint32_t regval; +#endif uint32_t bit = 1 << 20; /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the * only thing on the bus. */ +#ifdef CONFIG_DEBUG_SPI + regval = getreg32(CS_PIN_REGISTER); +#endif + if (selected) { /* Enable slave select (low enables) */ - spidbg("CD asserted\n"); putreg32(bit, CS_CLR_REGISTER); + spidbg("CS asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } else { /* Disable slave select (low enables) */ - spidbg("CD de-asserted\n"); putreg32(bit, CS_SET_REGISTER); + spidbg("CS de-asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); /* Wait for the TX FIFO not full indication */ @@ -345,6 +350,9 @@ static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_SPI_CMDDATA static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) { +#ifdef CONFIG_DEBUG_SPI + uint32_t regval; +#endif uint32_t bit = 1 << 23; /* We do not bother to check if devid == SPIDEV_DISPLAY because that is the @@ -358,19 +366,23 @@ static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd * A0 = L: the inputs at D0 to D7 are transferred to the command registers." */ +#ifdef CONFIG_DEBUG_SPI + regval = getreg32(CS_PIN_REGISTER); +#endif + if (cmd) { /* L: the inputs at D0 to D7 are transferred to the command registers */ - spidbg("Command\n"); putreg32(bit, CS_CLR_REGISTER); + spidbg("Command: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } else { /* H: the inputs at D0 to D7 are treated as display data. */ - spidbg("CD de-asserted\n"); putreg32(bit, CS_SET_REGISTER); + spidbg("Data: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER)); } return OK; @@ -606,11 +618,15 @@ FAR struct spi_dev_s *up_spiinitialize(int port) * for commands (also low) */ - regval32 = (1 << 20) || (1 << 23); + regval32 = (1 << 20) | (1 << 23); putreg32(regval32, CS_SET_REGISTER); regval32 |= getreg32(CS_DIR_REGISTER); putreg32(regval32, CS_DIR_REGISTER); + spidbg("CS Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n", + getreg32(LPC214X_PINSEL1), getreg32(CS_PIN_REGISTER), + getreg32(CS_DIR_REGISTER)); + /* Enable peripheral clocking to SPI1 */ regval32 = getreg32(LPC214X_PCON_PCONP); diff --git a/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c index 164518db3..236f9fa41 100644 --- a/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c +++ b/nuttx/configs/zp214xpa/src/up_ug2864ambag01.c @@ -85,13 +85,15 @@ /* Use either FIO or legacy GPIO */ #ifdef CONFIG_LPC214x_FIO -# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) +# define RESET_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET) +# define RESET_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET) +# define RESET_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET) +# define RESET_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET) #else -# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) -# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) -# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) +# define RESET_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET) +# define RESET_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET) +# define RESET_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET) +# define RESET_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET) #endif /* Debug ********************************************************************/ @@ -136,14 +138,21 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) /* Set the RESET line low, putting the OLED into the reset state. */ bits32 = (1 << 18); - putreg32(bits32, CS_CLR_REGISTER); - regval32 = getreg32(CS_DIR_REGISTER); - putreg32(regval32 | bits32, CS_DIR_REGISTER); + putreg32(bits32, RESET_CLR_REGISTER); + regval32 = getreg32(RESET_DIR_REGISTER); + putreg32(regval32 | bits32, RESET_DIR_REGISTER); + + lcdvdbg("RESET Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n", + getreg32(LPC214X_PINSEL1), getreg32(RESET_PIN_REGISTER), + getreg32(RESET_DIR_REGISTER)); /* Wait a bit then release the OLED from the reset state */ up_mdelay(20); - putreg32(bits32, CS_SET_REGISTER); + putreg32(bits32, RESET_SET_REGISTER); + + lcdvdbg("RESET release: PIN: %08x DIR: %08x\n", + getreg32(RESET_PIN_REGISTER), getreg32(RESET_DIR_REGISTER)); /* Get the SPI1 port interface */ diff --git a/nuttx/drivers/lcd/ug-2864ambag01.c b/nuttx/drivers/lcd/ug-2864ambag01.c index 2a47b38eb..ca1d4c123 100644 --- a/nuttx/drivers/lcd/ug-2864ambag01.c +++ b/nuttx/drivers/lcd/ug-2864ambag01.c @@ -1148,8 +1148,8 @@ void ug2864ambag01_fill(FAR struct lcd_dev_s *dev, uint8_t color) /* Transfer one page of the selected color */ - (void)SPI_SNDBLOCK(priv->spi, &priv->fb[page * UG2864AMBAG01_XRES], - UG2864AMBAG01_XRES); + (void)SPI_SNDBLOCK(priv->spi, &priv->fb[page * UG2864AMBAG01_XRES], + UG2864AMBAG01_XRES); } /* De-select and unlock the device */ -- cgit v1.2.3 From 167854a980facb6f611e2610a1754903dfc12ce4 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 31 Dec 2012 13:44:36 +0000 Subject: Remove non-functional WLAN examples, configurations git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5468 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/examples/Kconfig | 1 - apps/examples/Make.defs | 4 - apps/examples/Makefile | 2 +- apps/examples/wlan/Kconfig | 13 - apps/examples/wlan/Makefile | 98 ----- apps/examples/wlan/wlan_main.c | 306 --------------- nuttx/ChangeLog | 6 +- nuttx/configs/olimex-lpc1766stk/wlan/Make.defs | 109 ------ nuttx/configs/olimex-lpc1766stk/wlan/appconfig | 42 --- nuttx/configs/olimex-lpc1766stk/wlan/defconfig | 498 ------------------------- nuttx/configs/olimex-lpc1766stk/wlan/setenv.sh | 73 ---- 12 files changed, 7 insertions(+), 1147 deletions(-) delete mode 100644 apps/examples/wlan/Kconfig delete mode 100644 apps/examples/wlan/Makefile delete mode 100644 apps/examples/wlan/wlan_main.c delete mode 100644 nuttx/configs/olimex-lpc1766stk/wlan/Make.defs delete mode 100644 nuttx/configs/olimex-lpc1766stk/wlan/appconfig delete mode 100755 nuttx/configs/olimex-lpc1766stk/wlan/defconfig delete mode 100755 nuttx/configs/olimex-lpc1766stk/wlan/setenv.sh diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index d6a2f9d90..0464c6198 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -459,3 +459,5 @@ as well. However, the USB HID keyboard drier has not yet been updated to detect key release events. That is kind of tricky in the USB HID keyboard report data. + * apps/examples/wlan: Remove non-functional example. + diff --git a/apps/examples/Kconfig b/apps/examples/Kconfig index ae5f0a61a..b0cbd7088 100644 --- a/apps/examples/Kconfig +++ b/apps/examples/Kconfig @@ -58,5 +58,4 @@ source "$APPSDIR/examples/usbterm/Kconfig" source "$APPSDIR/examples/watchdog/Kconfig" source "$APPSDIR/examples/wget/Kconfig" source "$APPSDIR/examples/wgetjson/Kconfig" -source "$APPSDIR/examples/wlan/Kconfig" source "$APPSDIR/examples/xmlrpc/Kconfig" diff --git a/apps/examples/Make.defs b/apps/examples/Make.defs index 91f1331df..de2b8939f 100644 --- a/apps/examples/Make.defs +++ b/apps/examples/Make.defs @@ -254,10 +254,6 @@ ifeq ($(CONFIG_EXAMPLES_WGETJSON),y) CONFIGURED_APPS += examples/wgetjson endif -ifeq ($(CONFIG_EXAMPLES_WLAN),y) -CONFIGURED_APPS += examples/wlan -endif - ifeq ($(CONFIG_EXAMPLES_XMLRPC),y) CONFIGURED_APPS += examples/xmlrpc endif diff --git a/apps/examples/Makefile b/apps/examples/Makefile index 50e9596d7..99312af7a 100644 --- a/apps/examples/Makefile +++ b/apps/examples/Makefile @@ -42,7 +42,7 @@ SUBDIRS += ftpd hello helloxx hidkbd igmp json keypadtest lcdrw mm modbus mount SUBDIRS += nettest nsh null nx nxconsole nxffs nxflat nxhello nximage SUBDIRS += nxlines nxtext ostest pashello pipe poll pwm qencoder relays SUBDIRS += rgmp romfs serloop telnetd thttpd tiff touchscreen udp uip -SUBDIRS += usbserial sendmail usbstorage usbterm watchdog wget wgetjson wlan +SUBDIRS += usbserial sendmail usbstorage usbterm watchdog wget wgetjson # Sub-directories that might need context setup. Directories may need # context setup for a variety of reasons, but the most common is because diff --git a/apps/examples/wlan/Kconfig b/apps/examples/wlan/Kconfig deleted file mode 100644 index 7f8fb526a..000000000 --- a/apps/examples/wlan/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see misc/tools/kconfig-language.txt. -# - -config EXAMPLES_WLAN - bool "WLAN example" - default n - ---help--- - Enable the WLAN example - -if EXAMPLES_WLAN -endif diff --git a/apps/examples/wlan/Makefile b/apps/examples/wlan/Makefile deleted file mode 100644 index 1da79736f..000000000 --- a/apps/examples/wlan/Makefile +++ /dev/null @@ -1,98 +0,0 @@ -############################################################################ -# apps/examples/wlan/Makefile -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Authors: Gregory Nutt -# Rafael Noronha -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/.config --include $(TOPDIR)/Make.defs -include $(APPDIR)/Make.defs - -# WLAN Test - -ASRCS = -CSRCS = wlan_main.c - -AOBJS = $(ASRCS:.S=$(OBJEXT)) -COBJS = $(CSRCS:.c=$(OBJEXT)) - -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) - -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - BIN = ..\..\libapps$(LIBEXT) -else -ifeq ($(WINTOOL),y) - BIN = ..\\..\\libapps$(LIBEXT) -else - BIN = ../../libapps$(LIBEXT) -endif -endif - -ROOTDEPPATH = --dep-path . - -# Common build - -VPATH = - -all: .built -.PHONY: clean depend distclean - -$(AOBJS): %$(OBJEXT): %.S - $(call ASSEMBLE, $<, $@) - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -.built: $(OBJS) - $(call ARCHIVE, $(BIN), $(OBJS)) - @touch .built - -context: - -.depend: Makefile $(SRCS) - @$(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep - @touch $@ - -depend: .depend - -clean: - $(call DELFILE, .built) - $(call CLEAN) - -distclean: clean - $(call DELFILE, Make.dep) - $(call DELFILE, .depend) - --include Make.dep - diff --git a/apps/examples/wlan/wlan_main.c b/apps/examples/wlan/wlan_main.c deleted file mode 100644 index aa48a0238..000000000 --- a/apps/examples/wlan/wlan_main.c +++ /dev/null @@ -1,306 +0,0 @@ -/**************************************************************************** - * examples/wlan/wlan_main.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * Rafael Noronha - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name Gregory Nutt nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -/* DHCPC may be used in conjunction with any other feature (or not) */ - -#ifdef CONFIG_EXAMPLES_WLAN_DHCPC -# include -# include -# include -#endif - -/**************************************************************************** - * Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/* Sanity checking */ - -#ifndef CONFIG_USBHOST -# error "CONFIG_USBHOST is not defined" -#endif - -#ifdef CONFIG_USBHOST_BULK_DISABLE -# error "Bulk endpoints are disabled (CONFIG_USBHOST_BULK_DISABLE)" -#endif - -#ifndef CONFIG_NFILE_DESCRIPTORS -# error "CONFIG_NFILE_DESCRIPTORS > 0 needed" -#endif - -/* Provide some default values for other configuration settings */ - -#ifndef CONFIG_EXAMPLES_WLAN_DEFPRIO -# define CONFIG_EXAMPLES_WLAN_DEFPRIO 50 -#endif - -#ifndef CONFIG_EXAMPLES_WLAN_STACKSIZE -# define CONFIG_EXAMPLES_WLAN_STACKSIZE 1024 -#endif - -#ifndef CONFIG_EXAMPLES_WLAN_DEVNAME -# define CONFIG_EXAMPLES_WLAN_DEVNAME "wlan0" -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct usbhost_driver_s *g_drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: wlan_bringup - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -static inline void wlan_bringup(void) -{ -#if defined(CONFIG_EXAMPLES_WLAN_DHCPC) || defined(CONFIG_EXAMPLES_WLAN_NOMAC) - uint8_t mac[IFHWADDRLEN]; -#endif - struct in_addr addr; -#ifdef CONFIG_EXAMPLES_WLAN_DHCPC - void *handle; -#endif - - /* Many embedded network interfaces must have a software assigned - * MAC - */ - -#ifdef CONFIG_EXAMPLES_WLAN_NOMAC - mac[0] = 0x00; - mac[1] = 0xe0; - mac[2] = 0xde; - mac[3] = 0xad; - mac[4] = 0xbe; - mac[5] = 0xef; - uip_setmacaddr("eth0", mac); -#endif - - /* Set up the default router address */ - - addr.s_addr = HTONL(CONFIG_EXAMPLES_WLAN_DRIPADDR); - uip_setdraddr("eth0", &addr); - - /* Setup the subnet mask */ - - addr.s_addr = HTONL(CONFIG_EXAMPLES_WLAN_NETMASK); - uip_setnetmask("eth0", &addr); - - /* Set up our host address */ - -#ifdef CONFIG_EXAMPLES_WLAN_DHCPC - addr.s_addr = 0; -#else - addr.s_addr = HTONL(CONFIG_EXAMPLES_WLAN_IPADDR); -#endif - uip_sethostaddr("eth0", &addr); - -#ifdef CONFIG_EXAMPLES_WLAN_DHCPC - /* Set up the resolver */ - - resolv_init(); - - /* Get the MAC address of the NIC */ - - uip_getmacaddr("eth0", mac); - - /* Set up the DHCPC modules */ - - handle = dhcpc_open(&mac, IFHWADDRLEN); - - /* Get an IP address. Note: there is no logic here for renewing - * the address in this example. The address should be renewed in - * ds.lease_time/2 seconds. - */ - - printf("Getting IP address\n"); - if (handle) - { - struct dhcpc_state ds; - (void)dhcpc_request(handle, &ds); - uip_sethostaddr("eth1", &ds.ipaddr); - if (ds.netmask.s_addr != 0) - { - uip_setnetmask("eth0", &ds.netmask); - } - if (ds.default_router.s_addr != 0) - { - uip_setdraddr("eth0", &ds.default_router); - } - if (ds.dnsaddr.s_addr != 0) - { - resolv_conf(&ds.dnsaddr); - } - dhcpc_close(handle); - printf("IP: %s\n", inet_ntoa(ds.ipaddr)); - } -#endif -} - -/**************************************************************************** - * Name: wlan_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -static int wlan_waiter(int argc, char *argv[]) -{ - bool connected = false; - int ret; - - printf("wlan_waiter: Running\n"); - for (;;) - { - /* Wait for the device to change state */ - - ret = DRVR_WAIT(g_drvr, connected); - DEBUGASSERT(ret == OK); - - connected = !connected; - printf("wlan_waiter: %s\n", connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (connected) - { - /* Yes.. enumerate the newly connected device */ - - ret = DRVR_ENUMERATE(g_drvr); - - /* If the enumeration was successful, then bring up the interface */ - - wlan_bringup(); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} - -/**************************************************************************** - * Name: wlan_main - ****************************************************************************/ - -int wlan_main(int argc, char *argv[]) -{ - pid_t pid; - int ret; - - /* First, register all of the USB host Wireless LAN drivers */ - - printf("wlan_main: Register drivers\n"); - ret = usbhost_wlaninit(); - if (ret != OK) - { - printf("wlan_main: Failed to register the WLAN driver\n"); - } - - /* Then get an instance of the USB host interface */ - - printf("wlan_main: Initialize USB host WLAN driver\n"); - g_drvr = usbhost_initialize(0); - if (g_drvr) - { - /* Start a thread to handle device connection. */ - - printf("wlan_main: Start wlan_waiter\n"); - -#ifndef CONFIG_CUSTOM_STACK - pid = task_create("usbhost", CONFIG_EXAMPLES_WLAN_DEFPRIO, - CONFIG_EXAMPLES_WLAN_STACKSIZE, - (main_t)wlan_waiter, (const char **)NULL); -#else - pid = task_create("usbhost", CONFIG_EXAMPLES_WLAN_DEFPRIO, - (main_t)wlan_waiter, (const char **)NULL); -#endif - - /* Now just sleep. Eventually logic here will perform the device test. */ - - for (;;) - { - sleep(5); - printf("usert_start: Still alive\n"); - } - } - return 0; -} diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index daa1e068c..80b4bde1d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -1452,7 +1452,7 @@ complex: 'uname -o 2>/dev/null || echo "Other"' * drivers/usbhost/usbhost_enumerate.c: Add logic to get the VID and PID. This is necessary in order to support vendor-specific USB devices. - * examplex/wlan, configs/olimex-lpc1766stk/wlan, drivers/usbhost/usbhost_rtl8187.c, + * examples/wlan, configs/olimex-lpc1766stk/wlan, drivers/usbhost/usbhost_rtl8187.c, Add infrastructure to support RTL18187 wireless USB. * configs/nucleus2g: backed out USB host changes... wrong board. * Renamed arc/hc/include/mc9s12ne64 and src/mc9s12ne64 to m9s12. That name is @@ -1920,7 +1920,7 @@ CONFIG_FAT_LCNAMES is not selected, all filenames are strictly upper case. * configs/stm3210e-eval/nsh2: Console is back on UART1; Added - examplex/nx as an NSH "built-in" command as a demonstration. + examples/nx as an NSH "built-in" command as a demonstration. * fs/fat/fs_fat32dirent.c: Fix an important bug in the directory allocation (fat_allocatedirentry()). I looks like it could be initializing the wrong sectors! NOTE: This function was in @@ -3845,4 +3845,6 @@ * configs/zp214xpa/nxlines: Add an nxlines configuration for the ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). Working as of 2012-12-30. + * config/olimex-lpc1766stk/wlan: Remove non-functional + configuration. diff --git a/nuttx/configs/olimex-lpc1766stk/wlan/Make.defs b/nuttx/configs/olimex-lpc1766stk/wlan/Make.defs deleted file mode 100644 index f99c88f53..000000000 --- a/nuttx/configs/olimex-lpc1766stk/wlan/Make.defs +++ /dev/null @@ -1,109 +0,0 @@ -############################################################################ -# configs/olimex-lpc1766stk/wlan/Make.defs -# -# Copyright (C) 2011, 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mknulldeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" - MAXOPTIMIZATION = -O2 -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps.sh - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -else - ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -ARCHWARNINGSXX = -Wall -Wshadow -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe -HOSTLDFLAGS = - diff --git a/nuttx/configs/olimex-lpc1766stk/wlan/appconfig b/nuttx/configs/olimex-lpc1766stk/wlan/appconfig deleted file mode 100644 index 7fb2871aa..000000000 --- a/nuttx/configs/olimex-lpc1766stk/wlan/appconfig +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# configs/olimex-lpc1766stk/wlan/appconfig -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/wlan - -# Networking support - -CONFIGURED_APPS += netutils/uiplib diff --git a/nuttx/configs/olimex-lpc1766stk/wlan/defconfig b/nuttx/configs/olimex-lpc1766stk/wlan/defconfig deleted file mode 100755 index 009191f65..000000000 --- a/nuttx/configs/olimex-lpc1766stk/wlan/defconfig +++ /dev/null @@ -1,498 +0,0 @@ -############################################################################ -# configs/olimex-lpc1766stk/wlan/defconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection -# -CONFIG_ARCH="arm" -CONFIG_ARCH_ARM=y -CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lpc17xx" -CONFIG_ARCH_CHIP_LPC17XX=y -CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_BOARD="olimex-lpc1766stk" -CONFIG_ARCH_BOARD_LPC1766STK=y -CONFIG_BOARD_LOOPSPERMSEC=8111 -CONFIG_DRAM_SIZE=32768 -CONFIG_DRAM_START=0x10000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n - -# -# Identify toolchain and linker options -# -CONFIG_LPC17_CODESOURCERYW=n -CONFIG_LPC17_CODESOURCERYL=n -CONFIG_LPC17_DEVKITARM=n -CONFIG_LPC17_BUILDROOT=y - -# -# Individual subsystems can be enabled: -# -CONFIG_LPC17_ETHERNET=n -CONFIG_LPC17_USBHOST=y -CONFIG_LPC17_USBOTG=n -CONFIG_LPC17_USBDEV=n -CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=n -CONFIG_LPC17_UART2=n -CONFIG_LPC17_UART3=n -CONFIG_LPC17_CAN1=n -CONFIG_LPC17_CAN2=n -CONFIG_LPC17_SPI=n -CONFIG_LPC17_SSP0=n -CONFIG_LPC17_SSP1=n -CONFIG_LPC17_I2C0=n -CONFIG_LPC17_I2C1=n -CONFIG_LPC17_I2S=n -CONFIG_LPC17_TMR0=n -CONFIG_LPC17_TMR1=n -CONFIG_LPC17_TMR2=n -CONFIG_LPC17_TMR3=n -CONFIG_LPC17_RIT=n -CONFIG_LPC17_PWM=n -CONFIG_LPC17_MCPWM=n -CONFIG_LPC17_QEI=n -CONFIG_LPC17_RTC=n -CONFIG_LPC17_WDT=n -CONFIG_LPC17_ADC=n -CONFIG_LPC17_DAC=n -CONFIG_LPC17_GPDMA=n - -# -# LPC17xx specific serial device driver settings -# -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART3_SERIAL_CONSOLE=n - -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART3_TXBUFSIZE=256 - -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART3_RXBUFSIZE=256 - -CONFIG_UART0_BAUD=57600 -CONFIG_UART2_BAUD=57600 -CONFIG_UART3_BAUD=57600 -CONFIG_UART1_BAUD=57600 - -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART3_BITS=8 - -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART3_PARITY=0 - -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 -CONFIG_UART3_2STOP=0 - -# -# LPC17xx specific PHY/Ethernet device driver settings -# -CONFIG_PHY_KS8721=y -CONFIG_PHY_AUTONEG=y -CONFIG_PHY_SPEED100=n -CONFIG_PHY_FDUPLEX=y -CONFIG_NET_REGDEBUG=n - -# -# General build options -# -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=y -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=n - -# -# General OS setup -# -CONFIG_USER_ENTRYPOINT="wlan_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_NET=n -CONFIG_DEBUG_USB=n -CONFIG_MM_REGIONS=2 -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=0 -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=3 -CONFIG_START_DAY=8 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n -CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n -CONFIG_SCHED_WORKQUEUE=y -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n -CONFIG_DISABLE_POLL=n - -# -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=16 -CONFIG_MAX_TASK_ARGS=4 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_NUNGET_CHARS=2 -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PREALLOC_TIMERS=4 - -# -# Filesystem configuration -# -CONFIG_FS_FAT=n -CONFIG_FAT_LCNAMES=n -CONFIG_FAT_LFN=n -CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y - -# -# SPI-based MMC/SD driver -# -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 - -# -# Block driver buffering -# -CONFIG_FS_READAHEAD=n -CONFIG_FS_WRITEBUFFER=n - -# -# SDIO-based MMC/SD driver -# -CONFIG_SDIO_DMA=n -CONFIG_MMCSD_MMCSUPPORT=n -CONFIG_MMCSD_HAVECARDDETECT=n - -# -# TCP/IP and UDP support via uIP -# -CONFIG_NET=y -CONFIG_NET_NOINTS=y -CONFIG_NET_MULTIBUFFER=y -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=2 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n -CONFIG_NET_WLAN=y - -# -# UIP Network Utilities -# -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 - -# -# USB Device Configuration -# -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 - -# -# USB Host Configuration -# -CONFIG_USBHOST=y -CONFIG_USBHOST_NPREALLOC=0 -CONFIG_USBHOST_BULK_DISABLE=n -CONFIG_USBHOST_INT_DISABLE=y -CONFIG_USBHOST_ISOC_DISABLE=y - -# -# LPC17xx USB Device Configuration -# -CONFIG_LPC17_USBDEV_FRAME_INTERRUPT=n -CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT=n -CONFIG_LPC17_USBDEV_DMA=n -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 -CONFIG_LPC17_USBDEV_DMAINTMASK=0 - -# -# LPC17xx USB Host Configuration -# -# OHCI RAM layout: -# -CONFIG_USBHOST_OHCIRAM_SIZE=2048 -CONFIG_USBHOST_NEDS=3 -CONFIG_USBHOST_NTDS=2 -CONFIG_USBHOST_TDBUFFERS=4 -CONFIG_USBHOST_TDBUFSIZE=128 -CONFIG_USBHOST_IOBUFSIZE=448 - -# -# USB Serial Device Configuration -# -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=5 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 - -# -# USB Storage Device Configuration -# -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=2 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y - -# -# Settings for examples/uip -# -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n - -# -# Settings for examples/nettest -# -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 - -# -# Settings for apps/examples/wlan -# -CONFIG_EXAMPLES_WLAN_DHCPC=n -CONFIG_EXAMPLES_WLAN_NOMAC=n -CONFIG_EXAMPLES_WLAN_IPADDR=0xc0a800c9 -CONFIG_EXAMPLES_WLAN_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_WLAN_NETMASK=0xffffff00 - -# -# Settings for examples/ostest -# -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 - -# -# Settings for apps/nshlib -# -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_ARCHINIT=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" - -# -# Architecture-specific NSH options -# -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 - -# -# Settings for examples/usbserial -# -CONFIG_EXAMPLES_USBSERIAL_INONLY=n -CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n -CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n -CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n - -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n - -# -# Stack and heap information -# -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= - -# -# USB WLAN device identification -# -CONFIG_USB_WLAN_VID=0x0bda -CONFIG_USB_WLAN_PID=0x8189 diff --git a/nuttx/configs/olimex-lpc1766stk/wlan/setenv.sh b/nuttx/configs/olimex-lpc1766stk/wlan/setenv.sh deleted file mode 100755 index 767614612..000000000 --- a/nuttx/configs/olimex-lpc1766stk/wlan/setenv.sh +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/bash -# configs/olimex-lpc1766stk/wlan/setenv.sh -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" - -# The Olimex-lpc1766stk/tools directory -export LPCTOOL_DIR="${WD}/configs/olimex-lpc1766stk/tools" - -# Add the path to the toolchain and tools directory to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" -- cgit v1.2.3 From 29da58a677ffc192c61b29f8c1d53216b1c68ebe Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 1 Jan 2013 14:55:01 +0000 Subject: Updates from Darcy Gong for UG-2864SWEG01 OLED git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5469 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 4 +- nuttx/configs/stm32f4discovery/README.txt | 21 ++++--- .../src/stm32f4discovery-internal.h | 5 +- nuttx/configs/stm32f4discovery/src/up_spi.c | 28 ++++++--- .../stm32f4discovery/src/up_ug2864ambag01.c | 2 +- .../stm32f4discovery/src/up_ug2864hsweg01.c | 6 +- nuttx/drivers/lcd/ug-2864ambag01.c | 4 +- nuttx/drivers/lcd/ug-2864hsweg01.c | 73 +++++++++++++++++----- 8 files changed, 101 insertions(+), 42 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 80b4bde1d..9fd5619fd 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3845,6 +3845,8 @@ * configs/zp214xpa/nxlines: Add an nxlines configuration for the ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). Working as of 2012-12-30. - * config/olimex-lpc1766stk/wlan: Remove non-functional + * configs/olimex-lpc1766stk/wlan: Remove non-functional configuration. + * configs/stm32f4discovery/src and nuttx/drivers/lcd/ug-2864hsweg01.c: + Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong. diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index 37dae7b9e..571385abb 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -20,7 +20,7 @@ Contents - FPU - FSMC SRAM - SSD1289 - - UG-2864AMBAG01 + - UG-2864AMBAG01 / UG-2964SWEG01 - STM32F4Discovery-specific Configuration Options - Configurations @@ -696,10 +696,10 @@ The following summarize the bit banging oprations: WriteData(data); } -UG-2864AMBAG01 -============== +UG-2864AMBAG01 / UG-2964SWEG01 +============================== -I purchased an OLED display on eBay. The OLDE is 128x64 monochrome and +I purchased an OLED display on eBay. The OLED is 128x64 monochrome and is based on an UG-2864AMBAG01 OLED controller. The OLED can run in either parallel or SPI mode. I am using SPI mode. In SPI mode, the OLED is write only so the driver keeps a 128*64/8 = 1KB framebuffer to remember @@ -729,6 +729,10 @@ that I am using: (1) Required because of on-board MEMS ------------------------------------------------------------------------- +Darcy Gong recently added support for the UG-2964SWEG01 OLED which is also +an option with this configuratin. I have little technical information about +the UG-2964SWEG01 interface (see configs/stm32f4discovery/src/up_ug2864sweg01.c). + STM32F4Discovery-specific Configuration Options =============================================== @@ -1347,9 +1351,10 @@ Where is one of the following: b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. - 3. This configured can be re-configured to use the UG-2864AMBAG01 - 0.96 inch OLED by adding or changing the following items int - the configuration (using 'make menuconfig'): + 3. This configured can be re-configured to use either the + UG-2864AMBAG01 or UG-2864SWEG01 0.96 inch OLEDs by adding + or changing the following items in the configuration (using + 'make menuconfig'): +CONFIG_SPI_CMDDATA=y @@ -1360,7 +1365,7 @@ Where is one of the following: -CONFIG_LCD_SSD1289=y -CONFIG_SSD1289_PROFILE1=y - +CONFIG_LCD_UG2864AMBAG01=y + +CONFIG_LCD_UG2864AMBAG01=y : For the UG-2964AMBAG01 +CONFIG_UG2864AMBAG01_SPIMODE=3 +CONFIG_UG2864AMBAG01_FREQUENCY=3500000 +CONFIG_UG2864AMBAG01_NINTERFACES=1 diff --git a/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h b/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h index eae09594c..7027b639b 100644 --- a/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h +++ b/nuttx/configs/stm32f4discovery/src/stm32f4discovery-internal.h @@ -113,7 +113,7 @@ # define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) #endif -/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display: +/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display (SPI 4-wire): * * --------------------------+---------------------------------------------- * Connector CON10 J1: | STM32F4Discovery @@ -123,7 +123,7 @@ * 1 3v3 | 3,4 3v3 | P2 3V * 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection) * 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection) - * 7 A0 | 9 A0 | P2 PB8 (Arbitrary selection) + * 7 A0|D/C | 9 A0|D/C | P2 PB8 (Arbitrary selection) * 9 LED+ (N/C) | ----- | ----- * 2 5V Vcc | 1,2 Vcc | P2 5V * 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1)) @@ -142,6 +142,7 @@ GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7) # define GPIO_OLED_A0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_OLED_DC GPIO_OLED_A0 #endif /**************************************************************************************************** diff --git a/nuttx/configs/stm32f4discovery/src/up_spi.c b/nuttx/configs/stm32f4discovery/src/up_spi.c index 7ef3138fd..5b812d50c 100644 --- a/nuttx/configs/stm32f4discovery/src/up_spi.c +++ b/nuttx/configs/stm32f4discovery/src/up_spi.c @@ -96,11 +96,16 @@ void weak_function stm32_spiinitialize(void) { #ifdef CONFIG_STM32_SPI1 - (void)stm32_configgpio(GPIO_CS_MEMS); + (void)stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ #endif -#ifdef CONFIG_LCD_UG2864AMBAG01 +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) (void)stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ +# if defined(CONFIG_LCD_UG2864AMBAG01) (void)stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) + (void)stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +# endif #endif } @@ -134,7 +139,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sele { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); -#ifdef CONFIG_LCD_UG2864AMBAG01 +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) if (devid == SPIDEV_DISPLAY) { stm32_gpiowrite(GPIO_OLED_CS, !selected); @@ -180,9 +185,9 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) * Name: stm32_spi1cmddata * * Description: - * Set or clear the SD1329 D/Cn bit to select data (true) or command - * (false). This function must be provided by platform-specific logic. - * This is an implementation of the cmddata method of the SPI + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi.h). * * Input Parameters: @@ -203,18 +208,23 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) { -#ifdef CONFIG_LCD_UG2864AMBAG01 +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) if (devid == SPIDEV_DISPLAY) { /* "This is the Data/Command control pad which determines whether the * data bits are data or a command. * - * A0 = “H”: the inputs at D0 to D7 are treated as display data. - * A0 = “L”: the inputs at D0 to D7 are transferred to the command + * A0 = "H": the inputs at D0 to D7 are treated as display data. + * A0 = "L": the inputs at D0 to D7 are transferred to the command * registers." */ +# if defined(CONFIG_LCD_UG2864AMBAG01) (void)stm32_gpiowrite(GPIO_OLED_A0, !cmd); +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) + (void)stm32_gpiowrite(GPIO_OLED_DC, !cmd); +# endif return OK; } #endif diff --git a/nuttx/configs/stm32f4discovery/src/up_ug2864ambag01.c b/nuttx/configs/stm32f4discovery/src/up_ug2864ambag01.c index 2f2133116..42ad0c2a5 100644 --- a/nuttx/configs/stm32f4discovery/src/up_ug2864ambag01.c +++ b/nuttx/configs/stm32f4discovery/src/up_ug2864ambag01.c @@ -66,7 +66,7 @@ #endif /* Pin Configuration ********************************************************/ -/* UG-2864AMBAG01 OLED Display: +/* UG-2864AMBAG01 OLED Display (SPI 4-wire): * * --------------------------+---------------------------------------------- * Connector CON10 J1: | STM32F4Discovery diff --git a/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c b/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c index 4eee077a1..b6fe354d3 100644 --- a/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c +++ b/nuttx/configs/stm32f4discovery/src/up_ug2864hsweg01.c @@ -66,7 +66,7 @@ #endif /* Pin Configuration ********************************************************/ -/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display: +/* UG-2864HSWEG01 OLED Display (SPI 4-wire): * * --------------------------+---------------------------------------------- * Connector CON10 J1: | STM32F4Discovery @@ -76,7 +76,7 @@ * 1 3v3 | 3,4 3v3 | P2 3V * 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection) * 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection)(2) - * 7 A0 | 9 A0 | P2 PB8 (Arbitrary selection)(2) + * 7 D/C | 9 D/C | P2 PB8 (Arbitrary selection)(2) * 9 LED+ (N/C) | ----- | ----- * 2 5V Vcc | 1,2 Vcc | P2 5V * 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1)) @@ -85,7 +85,7 @@ * 10 GND | 20 GND | P2 GND * --------------+-----------+---------------------------------------------- * (1) Required because of on-board MEMS - * (2) Note that the OLED CS and A0 are managed in the up_spi.c file. + * (2) Note that the OLED CS and D/C are managed in the up_spi.c file. * ------------------------------------------------------------------------- */ diff --git a/nuttx/drivers/lcd/ug-2864ambag01.c b/nuttx/drivers/lcd/ug-2864ambag01.c index ca1d4c123..6b3d6d5a8 100644 --- a/nuttx/drivers/lcd/ug-2864ambag01.c +++ b/nuttx/drivers/lcd/ug-2864ambag01.c @@ -428,7 +428,7 @@ static inline void ug2864ambag01_configspi(FAR struct spi_dev_s *spi) SPI_SETMODE(spi, CONFIG_UG2864AMBAG01_SPIMODE); SPI_SETBITS(spi, 8); - SPI_SETFREQUENCY(spi, CONFIG_UG2864AMBAG01_FREQUENCY) + SPI_SETFREQUENCY(spi, CONFIG_UG2864AMBAG01_FREQUENCY); } #endif @@ -1035,7 +1035,7 @@ FAR struct lcd_dev_s *ug2864ambag01_initialize(FAR struct spi_dev_s *spi, unsign /* Configure the SPI */ - ug2864ambag01_configspi(spi) + ug2864ambag01_configspi(spi); /* Lock and select device */ diff --git a/nuttx/drivers/lcd/ug-2864hsweg01.c b/nuttx/drivers/lcd/ug-2864hsweg01.c index 9f9f99906..02a59b104 100644 --- a/nuttx/drivers/lcd/ug-2864hsweg01.c +++ b/nuttx/drivers/lcd/ug-2864hsweg01.c @@ -434,7 +434,7 @@ static inline void ug2864hsweg01_configspi(FAR struct spi_dev_s *spi) SPI_SETMODE(spi, CONFIG_UG2864HSWEG01_SPIMODE); SPI_SETBITS(spi, 8); - SPI_SETFREQUENCY(spi, CONFIG_UG2864HSWEG01_FREQUENCY) + SPI_SETFREQUENCY(spi, CONFIG_UG2864HSWEG01_FREQUENCY); } #endif @@ -1041,7 +1041,7 @@ FAR struct lcd_dev_s *ug2864hsweg01_initialize(FAR struct spi_dev_s *spi, unsign /* Configure the SPI */ - ug2864hsweg01_configspi(spi) + ug2864hsweg01_configspi(spi); /* Lock and select device */ @@ -1052,40 +1052,81 @@ FAR struct lcd_dev_s *ug2864hsweg01_initialize(FAR struct spi_dev_s *spi, unsign SPI_CMDDATA(spi, SPIDEV_DISPLAY, true); + /* Configure OLED SPI or I/O, must be delayed 1-10ms */ + + up_mdelay(5); + /* Configure the device */ +//#define OLED_WriteCmd(v) SPI_SEND(spi,v) +// +// /* Module manufacturers to provide initialization code Ä£¿é³§¼ÒÌṩ³õʼ»¯´úÂë */ +// +// OLED_WriteCmd(0xAE); /* ¹Ø±ÕOLEDÃæ°åÏÔʾ(ÐÝÃß) */ +// OLED_WriteCmd(0x00); /* ÉèÖÃÁеØÖ·µÍ4bit */ +// OLED_WriteCmd(0x10); /* ÉèÖÃÁеØÖ·¸ß4bit */ +// OLED_WriteCmd(0x40); /* ÉèÖÃÆðʼÐеØÖ·£¨µÍ5bit 0-63£©£¬ Ó²¼þÏà¹Ø*/ +// +// OLED_WriteCmd(0x81); /* ÉèÖöԱȶÈÃüÁî(Ë«×Ö½ÚÃüÁ£¬µÚ1¸ö×Ö½ÚÊÇÃüÁµÚ2¸ö×Ö½ÚÊǶԱȶȲÎÊý0-255 */ +// OLED_WriteCmd(0xCF); /* ÉèÖöԱȶȲÎÊý */ +// +// OLED_WriteCmd(0xA1); /* A0 £ºÁеØÖ·0Ó³Éäµ½SEG0; A1 £ºÁеØÖ·127Ó³Éäµ½SEG0 */ +// OLED_WriteCmd(0xA6); /* A6 : ÉèÖÃÕý³£ÏÔʾģʽ; A7 : ÉèÖÃΪ·´ÏÔģʽ */ +// +// OLED_WriteCmd(0xA8); /* ÉèÖÃCOM·Êý */ +// OLED_WriteCmd(0x3F); /* 1 ->£¨63+1£©Â· */ +// +// OLED_WriteCmd(0xD3); /* ÉèÖÃÏÔʾƫÒÆ£¨Ë«×Ö½ÚÃüÁ*/ +// OLED_WriteCmd(0x00); /* ÎÞÆ«ÒÆ */ +// +// OLED_WriteCmd(0xD5); /* ÉèÖÃÏÔʾʱÖÓ·ÖƵϵÊý/Õñµ´ÆµÂÊ */ +// OLED_WriteCmd(0x80); /* ÉèÖ÷ÖƵϵÊý,¸ß4bitÊÇ·ÖƵϵÊý£¬µÍ4bitÊÇÕñµ´ÆµÂÊ */ +// +// OLED_WriteCmd(0xD9); /* ÉèÖÃÔ¤³äµçÖÜÆÚ */ +// OLED_WriteCmd(0xF1); /* [3:0],PHASE 1; [7:4],PHASE 2; */ +// +// OLED_WriteCmd(0xDA); /* ÉèÖÃCOM½ÅÓ²¼þ½ÓÏß·½Ê½ */ +// OLED_WriteCmd(0x12); +// +// OLED_WriteCmd(0xDB); /* ÉèÖà vcomh µçѹ±¶ÂÊ */ +// OLED_WriteCmd(0x40); /* [6:4] 000 = 0.65 x VCC; 0.77 x VCC (RESET); 0.83 x VCC */ +// +// OLED_WriteCmd(0x8D); /* ÉèÖóäµç±Ã£¨ºÍϸöÃüÁî½áºÏʹÓã© */ +// OLED_WriteCmd(0x14); /* 0x14 ʹÄܳäµç±Ã£¬ 0x10 ÊÇ¹Ø±Õ */ +// OLED_WriteCmd(0xAF); /* ´ò¿ªOLEDÃæ°å */ + SPI_SEND(spi, SSD1306_DISPOFF); /* Display off 0xAE*/ SPI_SEND(spi, SSD1306_SETCOLL(0)); /* Set lower column address 0x00 */ SPI_SEND(spi, SSD1306_SETCOLH(0)); /* Set higher column address 0x10 */ SPI_SEND(spi, SSD1306_STARTLINE(0)); /* Set display start line 0x40*/ - SPI_SEND(spi, SSD1306_PAGEADDR(0)); /* Set page address [¿ÉºöÂÔ] */ + /* SPI_SEND(spi, SSD1306_PAGEADDR(0));*//* Set page address (Can ignore)*/ SPI_SEND(spi, SSD1306_CONTRAST_MODE); /* Contrast control 0x81*/ SPI_SEND(spi ,SSD1306_CONTRAST(UG2864HSWEG01_CONTRAST)); /* Default contrast 0xCF */ SPI_SEND(spi, SSD1306_REMAPPLEFT); /* Set segment remap left 95 to 0 | 0xA1*/ - SPI_SEND(spi, SSD1306_EDISPOFF); /* Normal display :off 0xA4 [¶à³öµÄÒ»ÐÐ] */ + /* SPI_SEND(spi, SSD1306_EDISPOFF); */ /* Normal display :off 0xA4 (Can ignore)*/ SPI_SEND(spi, SSD1306_NORMAL); /* Normal (un-reversed) display mode 0xA6 */ SPI_SEND(spi, SSD1306_MRATIO_MODE); /* Multiplex ratio 0xA8*/ SPI_SEND(spi, SSD1306_MRATIO(0x3f)); /* Duty = 1/64 */ - SPI_SEND(spi, SSD1306_SCANTOCOM0); /* Com scan direction: Scan from COM[n-1] to COM[0] [¿ÉºöÂÔ] */ + /* SPI_SEND(spi, SSD1306_SCANTOCOM0);*/ /* Com scan direction: Scan from COM[n-1] to COM[0] (Can ignore)*/ SPI_SEND(spi, SSD1306_DISPOFFS_MODE); /* Set display offset 0xD3 */ SPI_SEND(spi, SSD1306_DISPOFFS(0)); SPI_SEND(spi, SSD1306_CLKDIV_SET); /* Set clock divider 0xD5*/ - SPI_SEND(spi, SSD1306_CLKDIV(8,0)); /* 0x80 ? ¼ì²é ĬÈÏ0,0*/ - + SPI_SEND(spi, SSD1306_CLKDIV(8,0)); /* 0x80*/ + SPI_SEND(spi, SSD1306_CHRGPER_SET); /* ++Set pre-charge period 0xD9*/ - SPI_SEND(spi, SSD1306_CHRGPER(0x0f,1)); /* 0xf1 or 0x22£¨Ôöǿģʽ£¿£© */ - + SPI_SEND(spi, SSD1306_CHRGPER(0x0f,1)); /* 0xf1 or 0x22£¨Enhanced mode?£© */ + SPI_SEND(spi, SSD1306_CMNPAD_CONFIG); /* Set common pads / set com pins hardware configuration 0xDA*/ - SPI_SEND(spi, SSD1306_CMNPAD(0x12)); /* 0x12 ? ¼ì²é ĬÈÏ 0x10 */ - - SPI_SEND(spi, SSD1306_VCOM_SET); /* set vcomh 0xDB*/ + SPI_SEND(spi, SSD1306_CMNPAD(0x12)); /* 0x12 */ + + SPI_SEND(spi, SSD1306_VCOM_SET); /* set vcomh 0xDB*/ SPI_SEND(spi, SSD1306_VCOM(0x40)); - SPI_SEND(spi, SSD1306_CHRPUMP_SET); /* ++Set Charge Pump enable/disable 0x8D Ôö¼ÓµÄ*/ - SPI_SEND(spi, SSD1306_CHRPUMP_ON); /* 0x14 */ + SPI_SEND(spi, SSD1306_CHRPUMP_SET); /* ++Set Charge Pump enable/disable 0x8D ssd1306*/ + SPI_SEND(spi, SSD1306_CHRPUMP_ON); /* 0x14 close 0x10 */ - //SPI_SEND(spi, SSD1306_DCDC_MODE); /* DC/DC control mode: on */ - //SPI_SEND(spi, SSD1306_DCDC_ON); + /*SPI_SEND(spi, SSD1306_DCDC_MODE); */ /* DC/DC control mode: on (SSD1306 Not supported) */ + /*SPI_SEND(spi, SSD1306_DCDC_ON); */ SPI_SEND(spi, SSD1306_DISPON); /* display ON 0xAF */ -- cgit v1.2.3 From 41731a71efe2bca6fdc3490eff7af1e6fbcb6a3c Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 1 Jan 2013 16:33:47 +0000 Subject: All lm3s6965-ek configurations converted to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5470 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 + nuttx/arch/arm/src/lm3s/Kconfig | 140 +++++ nuttx/configs/lm3s6965-ek/README.txt | 59 ++- nuttx/configs/lm3s6965-ek/nsh/appconfig | 58 --- nuttx/configs/lm3s6965-ek/nsh/defconfig | 800 ++++++++++++++++++++--------- nuttx/configs/lm3s6965-ek/nx/appconfig | 39 -- nuttx/configs/lm3s6965-ek/nx/defconfig | 788 +++++++++++++++++----------- nuttx/configs/lm3s6965-ek/ostest/appconfig | 39 -- nuttx/configs/lm3s6965-ek/ostest/defconfig | 705 +++++++++++++++---------- 9 files changed, 1678 insertions(+), 952 deletions(-) delete mode 100644 nuttx/configs/lm3s6965-ek/nsh/appconfig delete mode 100644 nuttx/configs/lm3s6965-ek/nx/appconfig delete mode 100644 nuttx/configs/lm3s6965-ek/ostest/appconfig diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 9fd5619fd..7f2bda457 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3849,4 +3849,6 @@ configuration. * configs/stm32f4discovery/src and nuttx/drivers/lcd/ug-2864hsweg01.c: Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong. + * configs/lm326965-ek: All configurations converted to use the + kconfig-frontends configuration tool. diff --git a/nuttx/arch/arm/src/lm3s/Kconfig b/nuttx/arch/arm/src/lm3s/Kconfig index 469ff1fc9..aaf8342fa 100644 --- a/nuttx/arch/arm/src/lm3s/Kconfig +++ b/nuttx/arch/arm/src/lm3s/Kconfig @@ -12,6 +12,7 @@ choice config ARCH_CHIP_LM3S6918 bool "LM3S6918" + select LM3S_HAVE_SSI1 config ARCH_CHIP_LM3S9B96 bool "LM3S9B96" @@ -27,33 +28,172 @@ config ARCH_CHIP_LM3S8962 endchoice +config LM3S_HAVE_SSI1 + bool + +config LM3S_REVA2 + bool "Rev A2" + default n + ---help--- + Some early silicon returned an increase LDO voltage or 2.75V to work + around a PLL bug + config LM3S_DFU bool "DFU" default y +menu "Select LM3S Peripheral Support" + +config LM3S_UART0 + bool "UART0" + select ARCH_HAVE_UART0 + default n + +config LM3S_UART1 + bool "UART1" + select ARCH_HAVE_UART1 + default n + +config SSI0_DISABLE + bool "Disable SSI0" + default y + +config SSI1_DISABLE + bool "Disable SSI1" + default y + +config LM3S_UART2 + bool "UART2" + select ARCH_HAVE_UART2 + default n + +config LM3S_ETHERNET + bool "LM3S Ethernet" + default n + ---help--- + This must be set (along with NET) to build the LM3S Ethernet driver. + +endmenu + +menu "Disable GPIO Interrupts" + config LM3S_DISABLE_GPIOA_IRQS bool "Disable GPIOA IRQs" + default n config LM3S_DISABLE_GPIOB_IRQS bool "Disable GPIOB IRQs" + default n config LM3S_DISABLE_GPIOC_IRQS bool "Disable GPIOC IRQs" + default n config LM3S_DISABLE_GPIOD_IRQS bool "Disable GPIOD IRQs" + default n config LM3S_DISABLE_GPIOE_IRQS bool "Disable GPIOE IRQs" + default n config LM3S_DISABLE_GPIOF_IRQS bool "Disable GPIOF IRQs" + default n config LM3S_DISABLE_GPIOG_IRQS bool "Disable GPIOG IRQs" + default n config LM3S_DISABLE_GPIOH_IRQS bool "Disable GPIOH IRQs" + default n config LM3S_DISABLE_GPIOJ_IRQS bool "Disable GPIOJ IRQs" + default n + +endmenu + +if LM3S_ETHERNET +menu "LM3S Ethernet Configuration" + +config LM3S_ETHLEDS + bool "Ethernet LEDs" + default n + ---help--- + Enable to use Ethernet LEDs on the board. + +config LM3S_BOARDMAC + bool "Board MAC" + default n + ---help--- + If the board-specific logic can provide a MAC address (via + lm3s_ethernetmac()), then this should be selected. + +config LM3S_ETHHDUPLEX + bool "Force Half Duplex" + default n + ---help--- + Set to force half duplex operation + +config LM3S_ETHNOAUTOCRC + bool "Disable auto-CRC" + default n + ---help--- + Set to suppress auto-CRC generation + +config LM3S_ETHNOPAD + bool "Disable Tx Padding" + default n + ---help--- + Set to suppress Tx padding + +config LM3S_MULTICAST + bool "Enable Multicast" + default n + ---help--- + Set to enable multicast frames + +config LM3S_PROMISCUOUS + bool "Enable Promiscuous Mode" + default n + ---help--- + Set to enable promiscuous mode + +config LM3S_TIMESTAMP + bool "Enable Timestamping" + default n + +config LM3S_BADCRC + bool "Enable Bad CRC Rejection" + default n + ---help--- + Set to enable bad CRC rejection. + +config M3S_DUMPPACKET + bool "Dump Packets" + default n + ---help--- + Dump each packet received/sent to the console. + +endmenu +endif + +if !SSI0_DISABLE || !SSI1_DISABLE +menu "LM3S SSI Configuration" + +config SSI_POLLWAIT + bool "Poll Wait (No-Interrupt) Mode" + default y + +config SSI_TXLIMIT + int "Tx Limit" + default 4 + ---help--- + Default of 4 assumes half of the 8 entry FIFO + +endmenu +endif + + diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index 1e3aed2d9..09a07ec68 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -478,21 +478,68 @@ Where is one of the following: Configures the NuttShell (nsh) located at examples/nsh. The Configuration enables both the serial and telnetd NSH interfaces. - NOTE: As it is configured now, you MUST have a network connected. - Otherwise, the NSH prompt will not come up because the Ethernet - driver is waiting for the network to come up. That is probably - a bug in the Ethernet driver behavior! + NOTES: + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: - Network File System (NFS) support can be added by setting the - following in your configuration file: + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + 3. As it is configured now, you MUST have a network connected. + Otherwise, the NSH prompt will not come up because the Ethernet + driver is waiting for the network to come up. That is probably + a bug in the Ethernet driver behavior! + + 4. Network File System (NFS) support can be added by setting the + following in your configuration file: CONFIG_NFS=y + nx: And example using the NuttX graphics system (NX). This example uses the P14201 OLED driver. + NOTES: + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + ostest: This configuration directory, performs a simple OS test using examples/ostest. + NOTES: + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the mconf tool. See nuttx/README.txt and + misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary diff --git a/nuttx/configs/lm3s6965-ek/nsh/appconfig b/nuttx/configs/lm3s6965-ek/nsh/appconfig deleted file mode 100644 index 6277056d0..000000000 --- a/nuttx/configs/lm3s6965-ek/nsh/appconfig +++ /dev/null @@ -1,58 +0,0 @@ -############################################################################ -# configs/lm3s6965-ek/nsh/appconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nsh - -# NSH library - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - -# Networking support - -ifeq ($(CONFIG_NET),y) -CONFIGURED_APPS += netutils/uiplib -CONFIGURED_APPS += netutils/dhcpc -CONFIGURED_APPS += netutils/resolv -CONFIGURED_APPS += netutils/tftpc -CONFIGURED_APPS += netutils/webclient -ifeq ($(CONFIG_NSH_TELNET),y) -CONFIGURED_APPS += netutils/telnetd -endif -endif - - diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 7b75178ea..84651012d 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -1,213 +1,231 @@ -############################################################################ -# configs/lm3s6965-ek/nsh/defconfig -# -# Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM3S=y +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lm3s" -CONFIG_ARCH_CHIP_LM3S=y -CONFIG_ARCH_CHIP_LM3S6965=y -CONFIG_ARCH_BOARD="lm3s6965-ek" -CONFIG_ARCH_BOARD_LM3S6965EK=y +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 -CONFIG_DRAM_SIZE=65536 -CONFIG_DRAM_START=0x20000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_CALIBRATION=n +# CONFIG_ARCH_CALIBRATION is not set # -# Identify toolchain and linker options +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set + # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y +# LM3S Configuration Options +# +# CONFIG_ARCH_CHIP_LM3S6918 is not set +# CONFIG_ARCH_CHIP_LM3S9B96 is not set +# CONFIG_ARCH_CHIP_LM3S6432 is not set +CONFIG_ARCH_CHIP_LM3S6965=y +# CONFIG_ARCH_CHIP_LM3S8962 is not set +# CONFIG_LM3S_REVA2 is not set CONFIG_LM3S_DFU=y # -# Disable support for interrupts on GPIOH and GPIOJ which do not -# exist on the LM3S6B96. Additional interrupt support can be -# disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n +# Select LM3S Peripheral Support +# +CONFIG_LM3S_UART0=y +# CONFIG_LM3S_UART1 is not set +# CONFIG_SSI0_DISABLE is not set +CONFIG_SSI1_DISABLE=y +# CONFIG_LM3S_UART2 is not set +CONFIG_LM3S_ETHERNET=y + +# +# Disable GPIO Interrupts +# +# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set CONFIG_LM3S_DISABLE_GPIOH_IRQS=y CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y # -# LM3S6965 specific serial device driver settings -# -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART1_BAUD=115200 -CONFIG_UART2_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 +# LM3S Ethernet Configuration +# +# CONFIG_LM3S_ETHLEDS is not set +# CONFIG_LM3S_BOARDMAC is not set +# CONFIG_LM3S_ETHHDUPLEX is not set +# CONFIG_LM3S_ETHNOAUTOCRC is not set +# CONFIG_LM3S_ETHNOPAD is not set +# CONFIG_LM3S_MULTICAST is not set +# CONFIG_LM3S_PROMISCUOUS is not set +# CONFIG_LM3S_TIMESTAMP is not set +# CONFIG_LM3S_BADCRC is not set +# CONFIG_M3S_DUMPPACKET is not set # -# LM3S6965 specific SSI device driver settings +# LM3S SSI Configuration # -CONFIG_SSI0_DISABLE=n -CONFIG_SSI1_DISABLE=y CONFIG_SSI_POLLWAIT=y -#CONFIG_SSI_TXLIMIT=4 +CONFIG_SSI_TXLIMIT=4 +# CONFIG_NET_MULTICAST is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# LM3S6965 specific serial device driver settings +# Architecture Options # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=n -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n - -# -# General build options -# -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # -# General OS setup +# Board Settings # -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_NET=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=65536 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_LM3S6965EK=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="lm3s6965-ek" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 CONFIG_START_DAY=8 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set CONFIG_DISABLE_POLL=y -# -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - # # Sizes of configurable things (0 disables) # @@ -217,8 +235,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -226,126 +242,414 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Filesystem configuration +# Stack and heap information # -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=n -CONFIG_NFS=n +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # -# Maintain legacy build behavior (revisit) -# - +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y +CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MTD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_NET_SLIP is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set # -# SPI-based MMC/SD driver +# UART0 Configuration # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set # -# TCP/IP and UDP support via uIP +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support # CONFIG_NET=y -CONFIG_NET_IPv6=n +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_MULTIBUFFER is not set +# CONFIG_NET_IPv6 is not set CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 CONFIG_NET_SOCKOPTS=y CONFIG_NET_BUFSIZE=562 +# CONFIG_NET_TCPURGDATA is not set CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=8 -CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 -CONFIG_NET_TCPBACKLOG=n CONFIG_NET_MAX_LISTENPORTS=8 +CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 +CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 +CONFIG_NET_TCP_RECVDELAY=0 +# CONFIG_NET_TCPBACKLOG is not set CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_UDP_CONNS=8 +# CONFIG_NET_BROADCAST is not set CONFIG_NET_ICMP=y CONFIG_NET_ICMP_PING=y -#CONFIG_NET_PINGADDRCONF=0 +# CONFIG_NET_PINGADDRCONF is not set +# CONFIG_NET_IGMP is not set CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +CONFIG_NET_RECEIVE_WINDOW=562 +CONFIG_NET_ARPTAB_SIZE=16 +# CONFIG_NET_ARP_IPIN is not set # -# UIP Network Utilities +# File Systems +# + +# +# File system configuration +# +CONFIG_FS_FAT=y +# CONFIG_FAT_LCNAMES is not set +# CONFIG_FAT_LFN is not set +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 # -# Settings for examples/uip +# Built-In Applications # -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n +# CONFIG_BUILTIN is not set # -# Settings for examples/nettest -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WGET is not set # -# Settings for examples/ostest +# Interpreters # -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # -# Settings for apps/nshlib +# Interpreters # +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_RESOLV=y +CONFIG_NET_RESOLV_ENTRIES=4 +CONFIG_NET_RESOLV_MAXRESPONSE=96 +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +# CONFIG_NETUTILS_THTTPD is not set +CONFIG_NETUTILS_UIPLIB=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_DISCOVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=y +# CONFIG_NSH_CONDEV is not set CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_TELNET=y +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=y +# CONFIG_NSH_TELNET_LOGIN is not set CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_NOMAC=y +CONFIG_NSH_MAX_ROUNDTRIP=20 # -# Architecture-specific NSH options +# NxWidgets/NxWM # -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 # -# Stack and heap information +# System NSH Add-Ons # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/lm3s6965-ek/nx/appconfig b/nuttx/configs/lm3s6965-ek/nx/appconfig deleted file mode 100644 index 69f92ce3a..000000000 --- a/nuttx/configs/lm3s6965-ek/nx/appconfig +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# configs/lm3s6965-ek/nx/appconfig -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nx - diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index bca864013..5fb666e65 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -1,219 +1,212 @@ -############################################################################ -# configs/lm3s6965-ek/nx/defconfig -# -# Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM3S=y +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lm3s" -CONFIG_ARCH_CHIP_LM3S=y -CONFIG_ARCH_CHIP_LM3S6965=y -CONFIG_ARCH_BOARD="lm3s6965-ek" -CONFIG_ARCH_BOARD_LM3S6965EK=y +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 -CONFIG_DRAM_SIZE=65536 -CONFIG_DRAM_START=0x20000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_CALIBRATION=n +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set # -# Identify toolchain and linker options +# LM3S Configuration Options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y +# CONFIG_ARCH_CHIP_LM3S6918 is not set +# CONFIG_ARCH_CHIP_LM3S9B96 is not set +# CONFIG_ARCH_CHIP_LM3S6432 is not set +CONFIG_ARCH_CHIP_LM3S6965=y +# CONFIG_ARCH_CHIP_LM3S8962 is not set +# CONFIG_LM3S_REVA2 is not set CONFIG_LM3S_DFU=y # -# Disable support for interrupts on GPIOH and GPIOJ which do not -# exist on the LM3S6B96. Additional interrupt support can be -# disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n +# Select LM3S Peripheral Support +# +CONFIG_LM3S_UART0=y +# CONFIG_LM3S_UART1 is not set +# CONFIG_SSI0_DISABLE is not set +CONFIG_SSI1_DISABLE=y +# CONFIG_LM3S_UART2 is not set +# CONFIG_LM3S_ETHERNET is not set + +# +# Disable GPIO Interrupts +# +# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set CONFIG_LM3S_DISABLE_GPIOH_IRQS=y CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y # -# LM3S6965 specific serial device driver settings +# LM3S SSI Configuration # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART1_BAUD=115200 -CONFIG_UART2_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 +CONFIG_SSI_POLLWAIT=y +CONFIG_SSI_TXLIMIT=4 # -# LM3S6965 specific SSI device driver settings +# Architecture Options # -CONFIG_SSI0_DISABLE=n -CONFIG_SSI1_DISABLE=y -CONFIG_SSI_POLLWAIT=y -#CONFIG_SSI_TXLIMIT=4 +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # -# LM3S6965 specific serial device driver settings +# Board Settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=65536 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 # -# General build options +# Boot options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set # -# General SPI interface configuration +# Board Selection # -CONFIG_SPI_CMDDATA=y +CONFIG_ARCH_BOARD_LM3S6965EK=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="lm3s6965-ek" # -# General OS setup +# Common Board Options # -CONFIG_USER_ENTRYPOINT="nx_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_GRAPHICS=n -CONFIG_LCD_RITDEBUG=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 CONFIG_START_DAY=12 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nx_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_POLL=y -# -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance -# -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n - # # Sizes of configurable things (0 disables) # @@ -223,8 +216,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=12 CONFIG_NFILE_STREAMS=12 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -232,187 +223,382 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Framebuffer driver options -CONFIG_FB_CMAP=n -CONFIG_FB_HWCURSOR=n -CONFIG_FB_HWCURSORIMAGE=n -#CONFIG_FB_HWCURSORSIZE -#CONFIG_FB_TRANSPARENCY +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # -# Filesystem configuration +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +CONFIG_SPI_EXCHANGE=y +CONFIG_SPI_CMDDATA=y +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +CONFIG_LCD=y +# CONFIG_LCD_NOGETRUN is not set +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_MAXPOWER=1 +CONFIG_LCD_P14201=y +CONFIG_P14201_NINTERFACES=1 +CONFIG_P14201_SPIMODE=2 +CONFIG_P14201_FREQUENCY=3500000 +CONFIG_P14201_FRAMEBUFFER=y +# CONFIG_LCD_NOKIA6100 is not set +# CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_UG2864AMBAG01 is not set +# CONFIG_LCD_SSD1289 is not set +CONFIG_LCD_LANDSCAPE=y +# CONFIG_LCD_PORTRAIT is not set +# CONFIG_LCD_RPORTRAIT is not set +# CONFIG_LCD_RLANDSCAPE is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options # -CONFIG_FS_FAT=n -CONFIG_FS_ROMFS=n # -# Maintain legacy build behavior (revisit) +# System Logging # +# CONFIG_RAMLOG is not set -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +# +# Networking Support +# +# CONFIG_NET is not set # -# SPI-based MMC/SD driver +# File Systems # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 # -# TCP/IP and UDP support via uIP +# File system configuration # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_FS_RAMMAP is not set # -# UIP Network Utilities +# System Logging # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +# CONFIG_SYSLOG is not set # -# Graphics related configuration settings +# Graphics Support # CONFIG_NX=y -CONFIG_NX_MULTIUSER=n +CONFIG_NX_LCDDRIVER=y CONFIG_NX_NPLANES=1 +# CONFIG_NX_WRITEONLY is not set + +# +# Supported Pixel Depths +# CONFIG_NX_DISABLE_1BPP=y CONFIG_NX_DISABLE_2BPP=y -CONFIG_NX_DISABLE_4BPP=n +# CONFIG_NX_DISABLE_4BPP is not set CONFIG_NX_DISABLE_8BPP=y CONFIG_NX_DISABLE_16BPP=y CONFIG_NX_DISABLE_24BPP=y CONFIG_NX_DISABLE_32BPP=y CONFIG_NX_PACKEDMSFIRST=y -CONFIG_NX_LCDDRIVER=y -CONFIG_LCD_MAXPOWER=1 -CONFIG_LCD_MAXCONTRAST=255 + +# +# Input Devices +# CONFIG_NX_MOUSE=y CONFIG_NX_KBD=y -#CONFIG_NXTK_BORDERWIDTH=4 -CONFIG_NXTK_BORDERCOLOR1=8 -CONFIG_NXTK_BORDERCOLOR2=4 -CONFIG_NXTK_AUTORAISE=n -CONFIG_NXFONT_SANS23X27=y + +# +# Framed Window Borders +# +CONFIG_NXTK_BORDERWIDTH=4 +CONFIG_NXTK_BORDERCOLOR1=0x08 +CONFIG_NXTK_BORDERCOLOR2=0x04 +CONFIG_NXTK_BORDERCOLOR3=0 +# CONFIG_NXTK_AUTORAISE is not set + +# +# Font Selections +# CONFIG_NXFONTS_CHARBITS=7 -CONFIG_NX_BLOCKING=y -CONFIG_NX_MXSERVERMSGS=32 -CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXFONT_MONO5X8 is not set +# CONFIG_NXFONT_SANS17X22 is not set +# CONFIG_NXFONT_SANS20X26 is not set +CONFIG_NXFONT_SANS23X27=y +# CONFIG_NXFONT_SANS22X29 is not set +# CONFIG_NXFONT_SANS28X37 is not set +# CONFIG_NXFONT_SANS39X48 is not set +# CONFIG_NXFONT_SANS17X23B is not set +# CONFIG_NXFONT_SANS20X27B is not set +# CONFIG_NXFONT_SANS22X29B is not set +# CONFIG_NXFONT_SANS28X37B is not set +# CONFIG_NXFONT_SANS40X49B is not set +# CONFIG_NXFONT_SERIF22X29 is not set +# CONFIG_NXFONT_SERIF29X37 is not set +# CONFIG_NXFONT_SERIF38X48 is not set +# CONFIG_NXFONT_SERIF22X28B is not set +# CONFIG_NXFONT_SERIF27X38B is not set +# CONFIG_NXFONT_SERIF38X49B is not set +# CONFIG_NXCONSOLE is not set # -# RiT P14201 OLED Driver Configuration +# NX Multi-user only options # -CONFIG_LCD_P14201=y -CONFIG_P14201_SPIMODE=2 -CONFIG_P14201_FREQUENCY=3500000 -CONFIG_P14201_NINTERFACES=1 -CONFIG_P14201_FRAMEBUFFER=y +# CONFIG_NX_MULTIUSER is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set # -# Settings for examples/uip +# Binary Formats # -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set # -# Settings for examples/nettest -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 +# Library Routines +# # -# Settings for examples/ostest +# Standard C Library Options # -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# Settings for apps/nshlib +# Non-standard Helper Functions # -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_ARCHINIT=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_LIB_KBDCODEC=y # -# Architecture-specific NSH options +# Basic CXX Support # -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set # -# Settings for examples/nx +# Application Configuration # + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX_VPLANE=0 CONFIG_EXAMPLES_NX_DEVNO=0 -CONFIG_EXAMPLES_NX_BGCOLOR=2 -CONFIG_EXAMPLES_NX_COLOR1=10 -CONFIG_EXAMPLES_NX_COLOR2=12 -CONFIG_EXAMPLES_NX_TBCOLOR=8 -CONFIG_EXAMPLES_NX_FONTCOLOR=0 +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +CONFIG_EXAMPLES_NX_BGCOLOR=0x02 +CONFIG_EXAMPLES_NX_COLOR1=0x0a +CONFIG_EXAMPLES_NX_COLOR2=0x0c +CONFIG_EXAMPLES_NX_TBCOLOR=0x08 +CONFIG_EXAMPLES_NX_FONTCOLOR=0x00 +CONFIG_EXAMPLES_NX_DEFAULT_FONT=y CONFIG_EXAMPLES_NX_BPP=4 -CONFIG_EXAMPLES_NX_RAWWINDOWS=n -CONFIG_EXAMPLES_NX_STACKSIZE=2048 -CONFIG_EXAMPLES_NX_CLIENTPRIO=80 -CONFIG_EXAMPLES_NX_SERVERPRIO=120 -CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 +# CONFIG_EXAMPLES_NX_RAWWINDOWS is not set CONFIG_EXAMPLES_NX_EXTERNINIT=y +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set # -# Stack and heap information +# Interpreters # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/lm3s6965-ek/ostest/appconfig b/nuttx/configs/lm3s6965-ek/ostest/appconfig deleted file mode 100644 index dabf1f2b4..000000000 --- a/nuttx/configs/lm3s6965-ek/ostest/appconfig +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# configs/lm3s6965-ek/ostest/appconfig -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/ostest - diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index fcee44433..d1168ad45 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -1,211 +1,213 @@ -############################################################################ -# configs/lm3s6965-ek/ostest/defconfig -# -# Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM3S=y +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lm3s" -CONFIG_ARCH_CHIP_LM3S=y -CONFIG_ARCH_CHIP_LM3S6965=y -CONFIG_ARCH_BOARD="lm3s6965-ek" -CONFIG_ARCH_BOARD_LM3S6965EK=y +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 -CONFIG_DRAM_SIZE=65536 -CONFIG_DRAM_START=0x20000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_CALIBRATION=n +# CONFIG_ARCH_CALIBRATION is not set # -# Identify toolchain and linker options +# ARMV7M Configuration Options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set # -# Disable support for interrupts on GPIOH and GPIOJ which do not -# exist on the LM3S6B96. Additional interrupt support can be -# disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +# LM3S Configuration Options +# +# CONFIG_ARCH_CHIP_LM3S6918 is not set +# CONFIG_ARCH_CHIP_LM3S9B96 is not set +# CONFIG_ARCH_CHIP_LM3S6432 is not set +CONFIG_ARCH_CHIP_LM3S6965=y +# CONFIG_ARCH_CHIP_LM3S8962 is not set +# CONFIG_LM3S_REVA2 is not set +CONFIG_LM3S_DFU=y # -# LM3S6965 specific serial device driver settings +# Select LM3S Peripheral Support # CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART1_BAUD=115200 -CONFIG_UART2_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 +# CONFIG_LM3S_UART1 is not set +# CONFIG_SSI0_DISABLE is not set +CONFIG_SSI1_DISABLE=y +# CONFIG_LM3S_UART2 is not set +# CONFIG_LM3S_ETHERNET is not set # -# LM3S6965 specific SSI device driver settings +# Disable GPIO Interrupts # -CONFIG_SSI0_DISABLE=n -CONFIG_SSI1_DISABLE=y -CONFIG_SSI_POLLWAIT=y -#CONFIG_SSI_TXLIMIT=4 +# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set +CONFIG_LM3S_DISABLE_GPIOH_IRQS=y +CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y # -# LM3S6965 specific serial device driver settings +# LM3S SSI Configuration # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_SSI_POLLWAIT=y +CONFIG_SSI_TXLIMIT=4 +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # -# General build options +# Architecture Options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=y +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set # -# General OS setup +# Board Settings # -CONFIG_USER_ENTRYPOINT="ostest_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=0 -CONFIG_START_YEAR=2010 -CONFIG_START_MONTH=5 -CONFIG_START_DAY=6 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=y -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n -CONFIG_SDCLONE_DISABLE=y -CONFIG_NXFLAT=n +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=65536 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 # -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. +# Boot options # -# There are certain dependency relationships in these -# features. +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + # -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. +# Board Selection # -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_POLL=y +CONFIG_ARCH_BOARD_LM3S6965EK=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="lm3s6965-ek" # -# Misc libc settings +# Common Board Options # -CONFIG_NOPRINTF_FIELDWIDTH=n +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y # -# Allow for architecture optimized implementations +# Board-Specific Options # -# The architecture can provide optimized versions of the -# following to improve system performance + +# +# RTOS Features # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2010 +CONFIG_START_MONTH=5 +CONFIG_START_DAY=6 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_POLL=y # # Sizes of configurable things (0 disables) @@ -216,8 +218,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -225,123 +225,306 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Filesystem configuration +# Stack and heap information # -CONFIG_FS_FAT=n -CONFIG_FS_ROMFS=n +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # -# Maintain legacy build behavior (revisit) -# - +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y +CONFIG_MMCSD_SPICLOCK=12500000 CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set # -# SPI-based MMC/SD driver +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 # -# TCP/IP and UDP support via uIP +# File system configuration # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_FS_RAMMAP is not set # -# UIP Network Utilities +# System Logging # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +# CONFIG_SYSLOG is not set # -# Settings for examples/uip +# Graphics Support # -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n +# CONFIG_NX is not set # -# Settings for examples/nettest -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set # -# Settings for examples/ostest +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +CONFIG_LIB_KBDCODEC=y + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + # +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set # -# Settings for apps/nshlib -# -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_ARCHINIT=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" - -# -# Architecture-specific NSH options -# -CONFIG_NSH_MMCSDSPIPORTNO=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 +# Interpreters +# # -# Stack and heap information +# Interpreters # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set -- cgit v1.2.3 From 5d6b2017a05d31b6e7bdeab8defa3717fc72be3a Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 1 Jan 2013 16:34:12 +0000 Subject: All lm3s6965-ek configurations converted to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5471 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/nx/Kconfig | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/apps/examples/nx/Kconfig b/apps/examples/nx/Kconfig index 2081b12dc..f636daf84 100644 --- a/apps/examples/nx/Kconfig +++ b/apps/examples/nx/Kconfig @@ -10,4 +10,132 @@ config EXAMPLES_NX Enable the NX graphics example if EXAMPLES_NX + +config EXAMPLES_NX_BUILTIN + bool "NSH Built-IN" + depends on NSH_BUILTIN_APPS + ---help--- + Build the NX example as a "built-in" that can be executed from the + NSH command line + +config EXAMPLES_NX_VPLANE + int "Video Plane" + default 0 + ---help--- + The plane to select from the framebuffer driver for use in the test. + Default: 0 + +config EXAMPLES_NX_DEVNO + int "Video Device Number" + default 0 + ---help--- + The LCD device to select from the LCD driver for use in the test: + Default: 0 + +config EXAMPLES_NX_DEFAULT_COLORS + bool "Use Default Colors" + default y + +if !EXAMPLES_NX_DEFAULT_COLORS + +config EXAMPLES_NX_BGCOLOR + hex "Background Color" + ---help--- + The color of the background. Default depends on config EXAMPLES_NX_BPP. + +config EXAMPLES_NX_COLOR1 + hex "Color of Window 1" + ---help--- + The color of window 1. Default depends on config EXAMPLES_NX_BPP. + +config EXAMPLES_NX_COLOR2 + hex "Color of Window 2" + ---help--- + The color of window 2. Default depends on config EXAMPLES_NX_BPP. + +config EXAMPLES_NX_TBCOLOR + hex "Toolbar Color" + ---help--- + The color of the toolbar. Default depends on config EXAMPLES_NX_BPP. + +config EXAMPLES_NX_FONTCOLOR + hex "Font Color" + ---help--- + The color of the fonts. Default depends on config EXAMPLES_NX_BPP. + +endif + +config EXAMPLES_NX_DEFAULT_FONT + bool "Use Default Font" + default y + +config EXAMPLES_NX_FONTID + bool "Font ID" + depends on !EXAMPLES_NX_DEFAULT_FONT + ---help--- + Selects the font (see font ID numbers in include/nuttx/nx/nxfonts.h) + +config EXAMPLES_NX_BPP + int "Bits-Per-Pixel" + default 32 + ---help--- + Pixels per pixel to use. Valid options include 2, 4, 8, 16, 24, + and 32. Default is 32. + +config EXAMPLES_NX_RAWWINDOWS + bool "Use Raw Windows" + default n + ---help--- + Use raw windows; Default is to use pretty, framed NXTK windows with + toolbars. + +config EXAMPLES_NX_EXTERNINIT + bool "External Device Initialization" + default n + ---help--- + The driver for the graphics device on this platform requires some + unusual initialization. This is the for, for example, SPI LCD/OLED + devices. If this configuration is selected, then the platform code + must provide an LCD initialization function with a prototype like: + + #ifdef CONFIG_NX_LCDDRIVER + FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno); + #else + FAR struct fb_vtable_s *up_nxdrvinit(unsigned int devno); + #endif + +if NX_MULTIUSER +comment "Multi-User Configuration Options" + +config EXAMPLES_NX_STACKSIZE + int "NX Server Stack Size" + default 2048 + ---help--- + The stacksize to use when creating the NX server. Default 2048 + +config EXAMPLES_NX_CLIENTPRIO + int "Client Priority" + default 100 + ---help--- + The client priority. Default: 100 + +config EXAMPLES_NX_SERVERPRIO + int "Server Priority" + default 120 + ---help--- + The server priority. Default: 120 + +config EXAMPLES_NX_LISTENERPRIO + int "Listener Priority" + default 80 + ---help--- + The priority of the event listener thread. Default 80. + +config EXAMPLES_NX_NOTIFYSIGNO + int "Notify Signal Number" + default 4 + ---help--- + The signal number to use with nx_eventnotify(). Default: 4 + +endif endif -- cgit v1.2.3 From d0d3328d9cec65a161330c29aa318d1a3ded63e3 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 2 Jan 2013 14:02:07 +0000 Subject: Misc fixes for LM3S kconfig-frontends build git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5472 42af7a65-404d-4744-a932-0658087f49c3 --- misc/buildroot/configs/cortexm3-defconfig-4.3.3 | 7 +++++++ nuttx/ChangeLog | 5 ++++- nuttx/arch/arm/src/arm/Kconfig | 7 +++++++ nuttx/arch/arm/src/arm/Toolchain.defs | 5 +++++ nuttx/arch/arm/src/armv7-m/Kconfig | 8 ++++++++ nuttx/arch/arm/src/armv7-m/Toolchain.defs | 11 ++++++----- nuttx/configs/Kconfig | 2 +- nuttx/configs/lm3s6965-ek/nsh/defconfig | 7 ++++++- nuttx/configs/lm3s6965-ek/nx/defconfig | 1 + nuttx/configs/lm3s6965-ek/ostest/defconfig | 1 + nuttx/drivers/Kconfig | 3 ++- nuttx/drivers/mmcsd/Kconfig | 3 ++- 12 files changed, 50 insertions(+), 10 deletions(-) diff --git a/misc/buildroot/configs/cortexm3-defconfig-4.3.3 b/misc/buildroot/configs/cortexm3-defconfig-4.3.3 index 664000a16..a3371531b 100644 --- a/misc/buildroot/configs/cortexm3-defconfig-4.3.3 +++ b/misc/buildroot/configs/cortexm3-defconfig-4.3.3 @@ -14,6 +14,7 @@ BR2_arm=y # BR2_m68k is not set # BR2_m68hc11 is not set # BR2_m68hc12 is not set +# BR2_m9s12x is not set # BR2_mips is not set # BR2_mipsel is not set # BR2_nios2 is not set @@ -71,8 +72,11 @@ BR2_GNU_TARGET_SUFFIX="nuttx-elf" # Binutils Options # # BR2_BINUTILS_VERSION_2_17 is not set +# BR2_BINUTILS_VERSION_2_18 is not set # BR2_BINUTILS_VERSION_2_19 is not set BR2_BINUTILS_VERSION_2_19_1=y +# BR2_BINUTILS_VERSION_2_21_1 is not set +# BR2_BINUTILS_VERSION_2_22 is not set BR2_BINUTILS_VERSION="2.19.1" BR2_EXTRA_BINUTILS_CONFIG_OPTIONS="" @@ -80,9 +84,12 @@ BR2_EXTRA_BINUTILS_CONFIG_OPTIONS="" # GCC Options # BR2_PACKAGE_GCC=y +# BR2_GCC_VERSION_3_3_6 is not set # BR2_GCC_VERSION_3_4_6 is not set # BR2_GCC_VERSION_4_2_4 is not set BR2_GCC_VERSION_4_3_3=y +# BR2_GCC_VERSION_4_5_2 is not set +# BR2_GCC_VERSION_4_6_3 is not set BR2_GCC_SUPPORTS_SYSROOT=y BR2_GCC_VERSION="4.3.3" # BR2_GCC_USE_SJLJ_EXCEPTIONS is not set diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7f2bda457..ee43a897e 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3851,4 +3851,7 @@ Updates and correctinos for the UG-2864HSWEG01 from Darcy Gong. * configs/lm326965-ek: All configurations converted to use the kconfig-frontends configuration tool. - + * configs/Kconfig: NSH_MMCSDSPIPORTNO should depend on MMCSD_SPI, + not just SPI (from Jose Pablo Carballo). + * arch/arm/src/arm/Kconfig and armv7m/Kconfig: Add an option for + buildroot toolchains: They may be EABI or OABI. diff --git a/nuttx/arch/arm/src/arm/Kconfig b/nuttx/arch/arm/src/arm/Kconfig index 0d08d89a8..665fab575 100644 --- a/nuttx/arch/arm/src/arm/Kconfig +++ b/nuttx/arch/arm/src/arm/Kconfig @@ -33,3 +33,10 @@ config ARM_TOOLCHAIN_GNU_EABI configured for arm-none-eabi. endchoice + +config ARM_OABI_TOOLCHAIN + bool "OABI (vs EABI)" + default y + depends on ARM_TOOLCHAIN_BUILDROOT + ---help--- + Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi- diff --git a/nuttx/arch/arm/src/arm/Toolchain.defs b/nuttx/arch/arm/src/arm/Toolchain.defs index defe30b51..ea11c4dc9 100644 --- a/nuttx/arch/arm/src/arm/Toolchain.defs +++ b/nuttx/arch/arm/src/arm/Toolchain.defs @@ -102,8 +102,13 @@ endif # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT) +ifeq ($(CONFIG_ARMV_OABI_TOOLCHAIN),y) CROSSDEV = arm-nuttx-elf- ARCROSSDEV = arm-nuttx-elf- +else + CROSSDEV = arm-nuttx-eabi- + ARCROSSDEV = arm-nuttx-eabi- +endif MAXOPTIMIZATION = -Os endif diff --git a/nuttx/arch/arm/src/armv7-m/Kconfig b/nuttx/arch/arm/src/armv7-m/Kconfig index dc5aa3915..a154a4c5c 100644 --- a/nuttx/arch/arm/src/armv7-m/Kconfig +++ b/nuttx/arch/arm/src/armv7-m/Kconfig @@ -49,3 +49,11 @@ config ARMV7M_TOOLCHAIN_RAISONANCE depends on HOST_WINDOWS endchoice + +config ARMV7M_OABI_TOOLCHAIN + bool "OABI (vs EABI)" + default y + depends on ARMV7M_TOOLCHAIN_BUILDROOT + ---help--- + Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi- + diff --git a/nuttx/arch/arm/src/armv7-m/Toolchain.defs b/nuttx/arch/arm/src/armv7-m/Toolchain.defs index e214ce8bd..d7f2ed77f 100644 --- a/nuttx/arch/arm/src/armv7-m/Toolchain.defs +++ b/nuttx/arch/arm/src/armv7-m/Toolchain.defs @@ -160,14 +160,15 @@ endif # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT) - # OABI - # CROSSDEV = arm-nuttx-elf- - # ARCROSSDEV = arm-nuttx-elf- - # ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - # EABI +ifeq ($(CONFIG_ARMV7M_OABI_TOOLCHAIN),y) + CROSSDEV = arm-nuttx-elf- + ARCROSSDEV = arm-nuttx-elf- + ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft +else CROSSDEV = arm-nuttx-eabi- ARCROSSDEV = arm-nuttx-eabi- ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft +endif MAXOPTIMIZATION = -Os endif diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index cda5aa7bc..d851eeccb 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -761,7 +761,7 @@ config NSH_MMCSDSLOTNO config NSH_MMCSDSPIPORTNO int "MMC/SD SPI device number" default 0 - depends on NSH_LIBRARY && MMCSD && SPI + depends on NSH_LIBRARY && MMCSD && MMCSD_SPI ---help--- If board-specif NSH start-up logic will mount an SPI-based MMC/SD volume, then this setting may be needed to tell the board logic which SPI bus to use. Default: 0 (meaning is board-specific). diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 84651012d..1213797a7 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y # # LM3S Configuration Options @@ -189,6 +190,7 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_NSH_MMCSDMINOR=0 CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options @@ -259,7 +261,10 @@ CONFIG_DEV_NULL=y # CONFIG_CAN is not set # CONFIG_PWM is not set # CONFIG_I2C is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index 5fb666e65..7fca4d735 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y # # LM3S Configuration Options diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index d1168ad45..abfdcc251 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -89,6 +89,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y # # LM3S Configuration Options diff --git a/nuttx/drivers/Kconfig b/nuttx/drivers/Kconfig index 8302d21b7..3ced01b58 100644 --- a/nuttx/drivers/Kconfig +++ b/nuttx/drivers/Kconfig @@ -140,7 +140,8 @@ menuconfig SPI bool "SPI Driver Support" default n ---help--- - This selection enables building of the "upper-half" SPI driver. + This selection enables selection of common SPI options. This option + should be enabled by all platforms that support SPI interfaces. See include/nuttx/spi.h for further SPI driver information. if SPI diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig index f3a64be6c..5cdc23bcf 100644 --- a/nuttx/drivers/mmcsd/Kconfig +++ b/nuttx/drivers/mmcsd/Kconfig @@ -39,8 +39,9 @@ config MMCSD_HAVECARDDETECT 100% accurate config MMCSD_SPI - bool "MMC/SD spi transfer support" + bool "MMC/SD SPI transfer support" default y + depends on SPI config MMCSD_SPICLOCK int "MMC/SD maximum SPI clock" -- cgit v1.2.3 From 8d75785fad6f77f796655167bb9087266df2a117 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 3 Jan 2013 13:39:16 +0000 Subject: STM32 FLASH changes from Freddie Chopin git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5473 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 3 + nuttx/README.txt | 110 +++++++++++++++++++++++++++++++++ nuttx/arch/arm/src/stm32/stm32_flash.c | 37 ++++++----- nuttx/include/nuttx/progmem.h | 4 +- 4 files changed, 138 insertions(+), 16 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index ee43a897e..0c7a4dcbf 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3855,3 +3855,6 @@ not just SPI (from Jose Pablo Carballo). * arch/arm/src/arm/Kconfig and armv7m/Kconfig: Add an option for buildroot toolchains: They may be EABI or OABI. + * include/nuttx/progmem and arch/arm/src/stm32/stm32_flash.c: + Fix a counting bug plus change interface to use either relative + or absolut FLASH addressing (from Freddie Chopin). diff --git a/nuttx/README.txt b/nuttx/README.txt index dc3c9fb67..c00f086a1 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -10,6 +10,8 @@ README o Configuring NuttX - Instantiating "Canned" Configurations - NuttX Configuration Tool + - Incompatibilities with Older Configurations + - Converting Older Configurations to use the Configuration Tool - NuttX Configuration Tool under DOS o Toolchains - Cross-Development Toolchains @@ -292,6 +294,114 @@ NuttX Configuration Tool install 'mconf', make certain that your PATH variable includes a path to that installation directory. + The basic configuration order is "bottom-up": + + - Select the build environment, + - Select the processor, + - Select the board, + - Select the supported peripherals + - Configure the device drivers, + - Configure the application options on top of this. + + This is pretty straight forward for creating new configurations + but may be less intuitive for modifying existing configurations. + +Incompatibilities with Older Configurations +------------------------------------------- + + ***** WARNING ***** + + The old legacy, manual configurations and the new kconfig-frontends + configurations are not 100% compatible. Old legacy configurations + can *not* be used with the kconfig-frontends tool: If you run + 'make menuconfig' with a legacy configuration the resulting + configuration will probably not be functional. + + Q: How can I tell if a configuration is a new kconfig-frontends + configuration or an older, manual configuration? + + A: a) New kcondfig-frontends configurations will have this setting + within the defconfig/.config file": + + CONFIG_NUTTX_NEWCONFIG=y + + b) Only old, manual configurations will have an appconfig file + +Converting Older Configurations to use the Configuration Tool +------------------------------------------------------------- + + Q: How can I convert a older, manual configuration into a new, + kconfig-frontends toolchain. + + A: 1) Look at the appconfig file: Each application path there + will now have to have an enabling setting. For example, + if the old appconfig file had: + + CONFIGURED_APPS = examples/ostest + + Then the new configuration will need: + + CONFIG_EXAMPLES_OSTEST=y + + The appconfig file can then be deleted because it will not + be needed after the conversion. + + 2) Build the cmpconfig utility at tools: + + cd tools + make -f Makefile.host cmpconfig + + 3) Perform these steps repeatedly until you are convinced that + the configurations are the same: + + a) Repeat the following until you have account for all of the differences: + + cp configs///defconfig .config + make menuconfig (Just exit and save the new .config file) + tools/cmpconfig configs///defconfig .config | grep file1 + + The final grep will show settings in the old defconfig file that + do not appear in the new .config file (or have a different value + in the new .config file). In the new configuration, you will + probably have to enable certain groups of features. Such + hierarachical enabling options were not part of the older + configuration. + + b) Then make sure these all make sense: + + tools/cmpconfig configs///defconfig .config | grep file2 + + The final grep will show settings in the new .config file that + do not appear in the older defconfig file (or have a different value + in the new .config file). Here you should see only the new + hierarachical enabling options (such as CONFIG_SPI or CONFIG_MMCSD) + plus some other internal configuration settings (like CONFIG_ARCH_HAVE_UART0). + You will have to convince yourself that these new settings all make sense. + + 4) Finally, update the configuration: + + cp .config configs///defconfig + rm configs///appconfig + + NOTE: You should comment out the line containing the CONFIG_APPS_DIR + in the new defconfig file. Why? Because the application directory + may reside at a different location when the configuration is installed + at some later time. + + # CONFIG_APPS_DIR="../apps" + + 5) The updated configuration can then be instantiated in the normal + fashion: + + cd tools + ./configure.sh / + + NOTE: If CONFIG_APPS_DIR is not defined in the defconfig file, + the configure.sh script will find and add the new, correct path to + the application directory (CONFIG_APPS_DIR) when it copies the + defconfig file to the .config file. This is the setting that was + commented out in step 4. + NuttX Configuration Tool under DOS ---------------------------------- diff --git a/nuttx/arch/arm/src/stm32/stm32_flash.c b/nuttx/arch/arm/src/stm32/stm32_flash.c index 83fcc6172..20b0cfe10 100644 --- a/nuttx/arch/arm/src/stm32/stm32_flash.c +++ b/nuttx/arch/arm/src/stm32/stm32_flash.c @@ -35,7 +35,7 @@ /* Provides standard flash access functions, to be used by the flash mtd driver. * The interface is defined in the include/nuttx/progmem.h - * + * * Requirements during write/erase operations on FLASH: * - HSI must be ON. * - Low Power Modes are not permitted during write/erase @@ -80,7 +80,7 @@ void stm32_flash_unlock(void) if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } @@ -112,6 +112,11 @@ uint16_t up_progmem_pagesize(uint16_t page) int up_progmem_getpage(uint32_t addr) { + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; @@ -131,14 +136,14 @@ int up_progmem_erasepage(uint16_t page) } /* Get flash ready and begin erasing single page */ - + if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION)) { return -EPERM; } - + stm32_flash_unlock(); - + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER); putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR); modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); @@ -146,10 +151,10 @@ int up_progmem_erasepage(uint16_t page) while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste(); modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0); - + /* Verify */ - - for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; count; count-=4, addr += 4) { if (getreg32(addr) != 0xffffffff) @@ -173,8 +178,8 @@ int up_progmem_ispageerased(uint16_t page) } /* Verify */ - - for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; count; count--, addr++) { if (getreg8(addr) != 0xff) @@ -200,6 +205,11 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) /* Check for valid address range */ + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + if ((addr+count) >= STM32_FLASH_SIZE) { return -EFAULT; @@ -213,10 +223,10 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) } stm32_flash_unlock(); - + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); - - for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) + + for (addr += STM32_FLASH_BASE; count; count-=2, hword++, addr+=2) { /* Write half-word and wait to complete */ @@ -237,7 +247,6 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); return -EIO; } - } modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); diff --git a/nuttx/include/nuttx/progmem.h b/nuttx/include/nuttx/progmem.h index ac5a65940..2da59eab1 100644 --- a/nuttx/include/nuttx/progmem.h +++ b/nuttx/include/nuttx/progmem.h @@ -99,7 +99,7 @@ uint16_t up_progmem_pagesize(uint16_t page); * Address to page conversion * * Input Parameters: - * addr - Address without flash offet (aligned to page0) + * addr - Address with of without flash offset (absolute or aligned to page0) * * Returned Value: * Page or negative value on error. The following errors are reported @@ -165,7 +165,7 @@ int up_progmem_ispageerased(uint16_t page); * the address be aligned inside the page boundaries. * * Input Parameters: - * addr - Address without flash offet (aligned to page0) + * addr - Address with or without flash offset (absolute or aligned to page0) * buf - Pointer to buffer * count - Number of bytes to write * * -- cgit v1.2.3 From 60bd93728b779608fb0733822b7de55308ab738b Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 3 Jan 2013 15:45:57 +0000 Subject: Fix bad conditional in nuttx/libc/misc/Make.defs git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5474 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 ++ nuttx/libc/misc/Make.defs | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 0c7a4dcbf..bc698f6ad 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3858,3 +3858,5 @@ * include/nuttx/progmem and arch/arm/src/stm32/stm32_flash.c: Fix a counting bug plus change interface to use either relative or absolut FLASH addressing (from Freddie Chopin). + * libc/misc/Make.defs: Fix error in conditional for KBD CODEC. + diff --git a/nuttx/libc/misc/Make.defs b/nuttx/libc/misc/Make.defs index ad0313346..0d3c87d9d 100644 --- a/nuttx/libc/misc/Make.defs +++ b/nuttx/libc/misc/Make.defs @@ -65,7 +65,7 @@ CSRCS += lib_dbg.c lib_dumpbuffer.c # Keyboard driver encoder/decoder -ifneq ($(CONFIG_LIB_KBDCODEC),0) +ifeq ($(CONFIG_LIB_KBDCODEC),y) CSRCS += lib_kbdencode.c lib_kbddecode.c endif -- cgit v1.2.3 From 19752b4453e78c844b9ca348992100b594c3eaa1 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 3 Jan 2013 16:18:44 +0000 Subject: The default should be CONFIG_LIB_KBDCODEC=n git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5475 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 ++ nuttx/configs/lm3s6965-ek/nsh/defconfig | 2 +- nuttx/configs/lm3s6965-ek/nx/defconfig | 2 +- nuttx/configs/lm3s6965-ek/ostest/defconfig | 2 +- nuttx/configs/mcu123-lpc214x/nsh/defconfig | 2 +- nuttx/configs/sim/nxlines/defconfig | 2 +- nuttx/configs/zp214xpa/nsh/defconfig | 2 +- nuttx/configs/zp214xpa/nxlines/defconfig | 2 +- nuttx/libc/Kconfig | 2 +- 9 files changed, 10 insertions(+), 8 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index bc698f6ad..2762faf66 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3859,4 +3859,6 @@ Fix a counting bug plus change interface to use either relative or absolut FLASH addressing (from Freddie Chopin). * libc/misc/Make.defs: Fix error in conditional for KBD CODEC. + * libc/Kconfig and configs/*/defconfig (several): The default + setting should be CONFIG_LIB_KBDCODEC=n diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 1213797a7..64f4397cb 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -424,7 +424,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index 7fca4d735..be75c2875 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -431,7 +431,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index abfdcc251..83e89a6ae 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -363,7 +363,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/mcu123-lpc214x/nsh/defconfig b/nuttx/configs/mcu123-lpc214x/nsh/defconfig index 6ae163386..e065ef3fb 100644 --- a/nuttx/configs/mcu123-lpc214x/nsh/defconfig +++ b/nuttx/configs/mcu123-lpc214x/nsh/defconfig @@ -381,7 +381,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/sim/nxlines/defconfig b/nuttx/configs/sim/nxlines/defconfig index c023af674..c798b175f 100644 --- a/nuttx/configs/sim/nxlines/defconfig +++ b/nuttx/configs/sim/nxlines/defconfig @@ -347,7 +347,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/zp214xpa/nsh/defconfig b/nuttx/configs/zp214xpa/nsh/defconfig index 7c7d9d06c..7f8ddc19b 100644 --- a/nuttx/configs/zp214xpa/nsh/defconfig +++ b/nuttx/configs/zp214xpa/nsh/defconfig @@ -358,7 +358,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/configs/zp214xpa/nxlines/defconfig b/nuttx/configs/zp214xpa/nxlines/defconfig index 03a6bf72c..209b4a5e4 100644 --- a/nuttx/configs/zp214xpa/nxlines/defconfig +++ b/nuttx/configs/zp214xpa/nxlines/defconfig @@ -433,7 +433,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Non-standard Helper Functions # -CONFIG_LIB_KBDCODEC=y +# CONFIG_LIB_KBDCODEC is not set # # Basic CXX Support diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index a5ff7fd43..0ae56ac57 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -280,7 +280,7 @@ comment "Non-standard Helper Functions" config LIB_KBDCODEC bool "Keyboard CODEC" - default y + default n ---help--- In NuttX, a keyboard/keypad driver is simply a character driver that may have an (optional) encoding/decoding layer on the data returned -- cgit v1.2.3 From c504d9e32ec45736356b68afd878705a46d8791e Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 4 Jan 2013 16:00:38 +0000 Subject: Renaming some files in tools/ git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5476 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/README.txt | 9 +- nuttx/TODO | 84 +++++++----- nuttx/tools/Makefile.host | 22 +++- nuttx/tools/README.txt | 4 +- nuttx/tools/cfgdefine.c | 322 ++++++++++++++++++++++++++++++++++++++++++++++ nuttx/tools/cfgdefine.h | 64 +++++++++ nuttx/tools/mkconfig.c | 4 +- nuttx/tools/mkversion.c | 4 +- 8 files changed, 469 insertions(+), 44 deletions(-) create mode 100644 nuttx/tools/cfgdefine.c create mode 100644 nuttx/tools/cfgdefine.h diff --git a/nuttx/README.txt b/nuttx/README.txt index c00f086a1..bfd057351 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -41,6 +41,10 @@ Installing Cygwin tiny setup.exe program and it does the real, internet installation for you. + NOTE: NuttX can also be installed and built on a native Windows + system, but with some loss of tool functionality (see the + discussion "Native Windows Build" below). + Some Cygwin installation tips: 1. Install at C:\cygwin @@ -61,8 +65,9 @@ Installing Cygwin After installing Cygwin, you will get lots of links for installed tools and shells. I use the RXVT native shell. It is fast and reliable and does not require you to run the Cygwin X server (which is neither - fast nor reliable). The rest of these instructions assume that you - are at a bash command line prompt in either Linux or in Cygwin shell. + fast nor reliable). Unless otherwise noted, the rest of these + instructions assume that you are at a bash command line prompt in + either Linux or in Cygwin shell. Download and Unpack ------------------- diff --git a/nuttx/TODO b/nuttx/TODO index 6162431dc..d37231e1d 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,8 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (6) Task/Scheduler (sched/) - (1) On-demand paging (sched/) + (10) Task/Scheduler (sched/) (1) Memory Managment (mm/) (2) Signals (sched/, arch/) (2) pthreads (sched/) @@ -56,14 +55,9 @@ o Task/Scheduler (sched/) Title: CHILD PTHREAD TERMINATION Description: When a tasks exits, shouldn't all of its child pthreads also be terminated? - Status: Open + Status: Closed. No, this behavior will not be implemented. Priority: Medium, required for good emulation of process/pthread model. - Title: MMAN.H - Description: Implement sys/mman.h and functions - Status: Open - Priority: Low - Title: WAIT.H Description: Implement sys/wait.h and functions. Consider implementing wait, waitpid, waitid. At present, a parent has no information about @@ -72,14 +66,16 @@ o Task/Scheduler (sched/) Update: A simple but usable version of waitpid() has been included. This version is not compliant with all specifications and can be enabled with CONFIG_SCHED_WAITPID. - Status: Open + Status: Open, however no further work is planned. Priority: Low Title: MISSING ERRNO SETTINGS Description: Several APIs do not set errno. Need to review all APIs. Update: These are being fixed as they are encountered. There is no accounting of how many interfaces have this problem. - Status: Open + Status: Open? There has been an effort over the past few years to assure + that all errno settings are in place. What is the current state? + Unknown. Priority: Medium, required for standard compliance (but makes the code bigger) @@ -107,18 +103,29 @@ o Task/Scheduler (sched/) 3) sched_process_timeslice(). Then there is round-robin time-slicing. - Status: Open + The primary advantage of a tickless OS is that is would allow for + reduce power consumptions. That is because timer interrupts will + usually awaken CPUs from reduced power consumption states. + Status: Open. There will probably be no tickless OS implementation unless + someone gets motivated and drives the change. Priority: Low Title: posix_spawn() Description: This would be a good interface to add to NuttX. It is really just a re-packaging of the existing, non-standard NuttX exec() function. - Status: Open + Status: Open. There are no plans to implement this capabilitiey now. Priority: Medium low. -o On-demand paging (sched/) - ^^^^^^^^^^^^^^^^^^^^^^^^^ + Title: pause() NON-COMPLIANCE + Description: In the POSIX description of this function is the pause() function + will suspend the calling thread until delivery of a signal whose + action is either to execute a signal-catching function or to + terminate the process. The current implementation only waits for + any non-blocked signal to be received. It should only wake up if + the signal is delivered to a handler. + Status: Open. + Priority: Medium Low. Title: ON-DEMAND PAGE INCOMPLETE Description: On-demand paging has recently been incorporated into the RTOS. @@ -130,19 +137,16 @@ o On-demand paging (sched/) configs/ea3131/pgnsh and locked directories). There are some limitations of this testing so I still cannot say that the feature is fully functional. - Status: Open + Status: Open. This has been put on the shelf for some time. Priority: Medium-Low -o Other core OS logic - ^^^^^^^^^^^^^^^^^^^ - Title: GET_ENVIRON_PTR() Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented. The representation of the the environment strings selected for NutX is not compatible with the operation. Some significant re-design would be required to implement this funcion and that effort is thought to be not worth the result. - Status: Open + Status: Open. No change is planned. Priority: Low -- There is no plan to implement this. Title: TIMER_GETOVERRUN() @@ -150,6 +154,23 @@ o Other core OS logic Status: Open Priority: Low -- There is no plan to implement this. + Title: USER-SPACE WORK QUEUES + Description: There has been some use of work queues that has crept into some + user code. I am thinking of NxWidgets::CNxTimer. That timer + logic was originally implemented (correctly) using POSIX timers, + but was re-implemented using timed work. + + The issue is that NxWidgets::CNxTimer is a user-space application + but the work queues are an OS internal feature. This will be a + problem for KERNEL builds. Hooks and definitions have been added + in include/nuttx/wqueue.h to support a user-space work queue, but + the corresponding logic has not been implemented. + + The work queue logic will need to be moved from sched/ to libc/wqueue/ + Status: Open. No work will probably be done until a functional KERNEL build + that includes NxWisges::CNxTimer is needed. + Priority: Medium Low for now + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ @@ -212,7 +233,7 @@ o Memory Managment (mm/) be required to keep this memory on the correct list (or on no list at all). - Status: Open + Status: Open. No changes are planned. Priority: Medium/Low, a good feature to prevent memory leaks but would have negative impact on memory usage and code size. @@ -222,7 +243,7 @@ o Signals (sched/, arch/) Title: STANDARD SIGNALS Description: 'Standard' signals and signal actions are not supported. (e.g., SIGINT, SIGCHLD, SIGSEGV, etc). - Status: Open + Status: Open. No changes are planned. Priority: Low, required by standards but not so critical for an embedded system. @@ -240,11 +261,11 @@ o pthreads (sched/) Title: CANCELLATION POINTS Description: pthread_cancel(): Should implement cancellation points and pthread_testcancel() - Status: Open + Status: Open. No changes are planned. Priority: Low, probably not that useful Title: PTHREAD_PRIO_PROTECT - Description: Extended pthread_mutexattr_setprotocol() suport PTHREAD_PRIO_PROTECT: + Description: Extended pthread_mutexattr_setprotocol() suport PTHREAD_PRIO_PROTECT: "When a thread owns one or more mutexes initialized with the PTHREAD_PRIO_PROTECT protocol, it shall execute at the higher of its priority or the highest of the priority ceilings of all the mutexes @@ -260,7 +281,7 @@ o pthreads (sched/) PTHREAD_PRIO_PROTECT protocol attributes, it shall not be subject to being moved to the tail of the scheduling queue at its priority in the event that its original priority is changed." - Status: Open + Status: Open. No changes planned. Priority: Low -- about zero, probably not that useful. Priority inheritance is already supported and is a much better solution. And it turns out that priority protection is just about as complex as priority inheritance. @@ -442,21 +463,25 @@ o Network (net/, drivers/net) Title: SOCK_RAW/SOCK_PACKET Description: Should implement SOCK_RAW, SOCK_PACKET - Status: Open + Status: Open. No changes are planned. Priority: Low Tile: MULTIPLE NETWORK INTERFACE SUPPORT Description: uIP polling issues / Multiple network interface support: + (1) Current logic will not support multiple ethernet drivers. Each driver should poll on TCP connections connect on the network supported by the driver; UDP polling should respond with TX data only if the UDP packet is intended for the the network supported by the driver. + (2) If there were multiple drivers, polling would occur at double the rate. Fix by using bound IP address in TCP connection (lipaddr) and verifying that it is in the subnet served by the driver. - Status: Open + + Status: Open. Nothing will probably be done until I have a platform + with two network interfaces that I need to support. Priority: Medium, The feature is not important, but it is important for NuttX to resolve the architectural issues. @@ -464,7 +489,7 @@ o Network (net/, drivers/net) Description: sendto() and multiple network interface support: When polled, would have to assure that the destination IP is on the subnet served by the polling driver. - Status: Open + Status: Open. This is really part of the above issue. Priority: Medium, The feature is not important, but it is important for NuttX to resolve the architectural issues. @@ -472,7 +497,8 @@ o Network (net/, drivers/net) Description: IPv6 support is incomplete. Adam Dunkels has recently announced IPv6 support for uIP (currently only as part of Contiki). Those changes need to be ported to NuttX. - Status: Open + Status: Open. No work will probably be done until there is a specific + requirement for IPv6. Priority: Medium Title: LISTENING FOR UDP BROADCASTS @@ -488,7 +514,7 @@ o Network (net/, drivers/net) driver should be throttled. Perhaps the driver should disable RX interrupts when throttled and re-anable on each poll time. recvfrom would, of course, have to un-throttle. - Status: Open + Status: Open. This is just a thought experiment. No changes are planned. Priority: Medium Title: STANDARDIZE ETHERNET DRIVER STATISTICS diff --git a/nuttx/tools/Makefile.host b/nuttx/tools/Makefile.host index 4a46901e6..663ff29c7 100644 --- a/nuttx/tools/Makefile.host +++ b/nuttx/tools/Makefile.host @@ -45,13 +45,12 @@ ifneq ($(CONFIG_WINDOWS_NATIVE),y) endif all: b16$(HOSTEXEEXT) bdf-converter$(HOSTEXEEXT) cmpconfig$(HOSTEXEEXT) \ - mkconfig$(HOSTEXEEXT) mkdeps$(HOSTEXEEXT) mksymtab$(HOSTEXEEXT) \ + configure$(HOSTEXEEXT) mkconfig$(HOSTEXEEXT) mkdeps$(HOSTEXEEXT) mksymtab$(HOSTEXEEXT) \ mksyscall$(HOSTEXEEXT) mkversion$(HOSTEXEEXT) default: mkconfig$(HOSTEXEEXT) mksyscall$(HOSTEXEEXT) mkdeps$(HOSTEXEEXT) ifdef HOSTEXEEXT -.PHONY: b16 bdf-converter cmpconfig clean mkconfig mkdeps mksymtab \ - mksyscall mkversion +.PHONY: b16 bdf-converter cmpconfig clean configure mkconfig mkdeps mksymtab mksyscall mkversion else .PHONY: clean endif @@ -70,10 +69,19 @@ ifdef HOSTEXEEXT b16: b16$(HOSTEXEEXT) endif +# configure - Instantiate a canned NuttX configuration + +configure$(HOSTEXEEXT): configure.c cfgparser.c + $(Q) $(HOSTCC) $(HOSTCFLAGS) -o configure$(HOSTEXEEXT) configure.c cfgparser.c + +ifdef HOSTEXEEXT +configure: configure$(HOSTEXEEXT) +endif + # mkconfig - Convert a .config file into a C config.h file -mkconfig$(HOSTEXEEXT): mkconfig.c cfgparser.c - $(Q) $(HOSTCC) $(HOSTCFLAGS) -o mkconfig$(HOSTEXEEXT) mkconfig.c cfgparser.c +mkconfig$(HOSTEXEEXT): mkconfig.c cfgdefine.c + $(Q) $(HOSTCC) $(HOSTCFLAGS) -o mkconfig$(HOSTEXEEXT) mkconfig.c cfgdefine.c ifdef HOSTEXEEXT mkconfig: mkconfig$(HOSTEXEEXT) @@ -90,8 +98,8 @@ endif # mkversion - Convert a .version file into a C version.h file -mkversion$(HOSTEXEEXT): mkconfig.c cfgparser.c - $(Q) $(HOSTCC) $(HOSTCFLAGS) -o mkversion$(HOSTEXEEXT) mkversion.c cfgparser.c +mkversion$(HOSTEXEEXT): mkconfig.c cfgdefine.c + $(Q) $(HOSTCC) $(HOSTCFLAGS) -o mkversion$(HOSTEXEEXT) mkversion.c cfgdefine.c ifdef HOSTEXEEXT mkversion: mkversion$(HOSTEXEEXT) diff --git a/nuttx/tools/README.txt b/nuttx/tools/README.txt index fc0332212..f9e2d1099 100644 --- a/nuttx/tools/README.txt +++ b/nuttx/tools/README.txt @@ -38,7 +38,7 @@ discover.py Example script for discovering devices in the local network. It is the counter part to apps/netutils/discover -mkconfig.c, cfgparser.c, and cfgparser.h +mkconfig.c, cfgdefine.c, and cfgdefine.h ---------------------------------------- These are Cs file that are used to build mkconfig program. The mkconfig @@ -79,7 +79,7 @@ mkfsdata.pl NOTE: This perl script comes from uIP and was (probably) written by Adam Dunkels. uIP has a license that is compatible with NuttX. -mkversion.c, cfgparser.c, and cfgparser.h +mkversion.c, cfgdefine.c, and cfgdefine.h ----------------------------------------- This is C file that is used to build mkversion program. The mkversion diff --git a/nuttx/tools/cfgdefine.c b/nuttx/tools/cfgdefine.c new file mode 100644 index 000000000..00dd11c20 --- /dev/null +++ b/nuttx/tools/cfgdefine.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * tools/cfgdefine.c + * + * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "cfgdefine.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +char line[LINESIZE+1]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* These are configuration variable name that are quoted by configuration tool + * but which must be unquoted when used in C code. + */ + +static const char *dequote_list[] = +{ + /* NuttX */ + + "CONFIG_USER_ENTRYPOINT", /* Name of entry point function */ + + /* NxWidgets/NxWM */ + + "CONFIG_NXWM_BACKGROUND_IMAGE", /* Name of bitmap image class */ + "CONFIG_NXWM_STARTWINDOW_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_NXCONSOLE_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_CALIBRATION_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_HEXCALCULATOR_ICON", /* Name of bitmap image class */ + + NULL /* Marks the end of the list */ +}; + + /**************************************************************************** + * Private Functions + ****************************************************************************/ + + /* Skip over any spaces */ + +static char *skip_space(char *ptr) +{ + while (*ptr && isspace((int)*ptr)) ptr++; + return ptr; +} + +/* Find the end of a variable string */ + +static char *find_name_end(char *ptr) +{ + while (*ptr && (isalnum((int)*ptr) || *ptr == '_')) ptr++; + return ptr; +} + +/* Find the end of a value string */ + +static char *find_value_end(char *ptr) +{ + while (*ptr && !isspace((int)*ptr)) + { + if (*ptr == '"') + { + do ptr++; while (*ptr && *ptr != '"'); + if (*ptr) ptr++; + } + else + { + do ptr++; while (*ptr && !isspace((int)*ptr) && *ptr != '"'); + } + } + return ptr; +} + +/* Read the next line from the configuration file */ + +static char *read_line(FILE *stream) +{ + char *ptr; + + for (;;) + { + line[LINESIZE] = '\0'; + if (!fgets(line, LINESIZE, stream)) + { + return NULL; + } + else + { + ptr = skip_space(line); + if (*ptr && *ptr != '#' && *ptr != '\n') + { + return ptr; + } + } + } +} + +/* Parse the line from the configuration file into a variable name + * string and a value string. + */ + +static void parse_line(char *ptr, char **varname, char **varval) +{ + /* Skip over any leading spaces */ + + ptr = skip_space(ptr); + + /* The first no-space is the beginning of the variable name */ + + *varname = skip_space(ptr); + *varval = NULL; + + /* Parse to the end of the variable name */ + + ptr = find_name_end(ptr); + + /* An equal sign is expected next, perhaps after some white space */ + + if (*ptr && *ptr != '=') + { + /* Some else follows the variable name. Terminate the variable + * name and skip over any spaces. + */ + + *ptr = '\0'; + ptr = skip_space(ptr + 1); + } + + /* Verify that the equal sign is present */ + + if (*ptr == '=') + { + /* Make sure that the variable name is terminated (this was already + * done if the name was followed by white space. + */ + + *ptr = '\0'; + + /* The variable value should follow =, perhaps separated by some + * white space. + */ + + ptr = skip_space(ptr + 1); + if (*ptr) + { + /* Yes.. a variable follows. Save the pointer to the start + * of the variable string. + */ + + *varval = ptr; + + /* Find the end of the variable string and make sure that it + * is terminated. + */ + + ptr = find_value_end(ptr); + *ptr = '\0'; + } + } +} + +static char *dequote_value(const char *varname, char *varval) +{ + const char **dqnam; + char *dqval = varval; + int len; + + if (dqval) + { + /* Check if the variable name is in the list of strings to be dequoated */ + + for (dqnam = dequote_list; *dqnam; dqnam++) + { + if (strcmp(*dqnam, varname) == 0) + { + break; + } + } + + /* Did we find the variable name in the list of configuration variables + * to be dequoated? + */ + + if (*dqnam) + { + /* Yes... Check if there is a traiing quote */ + + len = strlen(dqval); + if (dqval[len-1] == '"') + { + /* Yes... replace it with a terminator */ + + dqval[len-1] = '\0'; + len--; + } + + /* Is there a leading quote? */ + + if (dqval[0] == '"') + { + /* Yes.. skip over the leading quote */ + + dqval++; + len--; + } + + /* Handle the case where nothing is left after dequoting */ + + if (len <= 0) + { + dqval = NULL; + } + } + } + + return dqval; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void generate_definitions(FILE *stream) +{ + char *varname; + char *varval; + char *ptr; + + /* Loop until the entire file has been parsed. */ + + do + { + /* Read the next line from the file */ + + ptr = read_line(stream); + if (ptr) + { + /* Parse the line into a variable and a value field */ + + parse_line(ptr, &varname, &varval); + + /* Was a variable name found? */ + + if (varname) + { + /* Yes.. dequote the value if necessary */ + + varval = dequote_value(varname, varval); + + /* If no value was provided or if the special value 'n' was provided, + * then undefine the configuration variable. + */ + + if (!varval || strcmp(varval, "n") == 0) + { + printf("#undef %s\n", varname); + } + + /* Simply define the configuration variable if it has the special + * value "y" + */ + + else if (strcmp(varval, "y") == 0) + { + printf("#define %s 1\n", varname); + } + + /* Otherwise, use the value as provided */ + + else + { + printf("#define %s %s\n", varname, varval); + } + } + } + } + while (ptr); +} diff --git a/nuttx/tools/cfgdefine.h b/nuttx/tools/cfgdefine.h new file mode 100644 index 000000000..04817b719 --- /dev/null +++ b/nuttx/tools/cfgdefine.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * tools/cfgdefine.h + * + * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __TOOLS_CFGDEFINE_H +#define __TOOLS_CFGDEFINE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +#define LINESIZE ( PATH_MAX > 256 ? PATH_MAX : 256 ) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern char line[LINESIZE+1]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +extern void generate_definitions(FILE *stream); + +#endif /* __TOOLS_CFGDEFINE_H */ diff --git a/nuttx/tools/mkconfig.c b/nuttx/tools/mkconfig.c index 3e55f5097..f4a1168c5 100644 --- a/nuttx/tools/mkconfig.c +++ b/nuttx/tools/mkconfig.c @@ -41,7 +41,7 @@ #include #include -#include "cfgparser.h" +#include "cfgdefine.h" /**************************************************************************** * Pre-processor Definitions @@ -99,7 +99,7 @@ int main(int argc, char **argv, char **envp) printf("#ifndef __INCLUDE_NUTTX_CONFIG_H\n"); printf("#define __INCLUDE_NUTTX_CONFIG_H\n\n"); printf("/* Architecture-specific options *************************/\n\n"); - parse_file(stream); + generate_definitions(stream); printf("\n/* Sanity Checks *****************************************/\n\n"); printf("/* If this is an NXFLAT, external build, then make sure that\n"); printf(" * NXFLAT support is enabled in the base code.\n"); diff --git a/nuttx/tools/mkversion.c b/nuttx/tools/mkversion.c index 32068df38..c6b00c5e5 100644 --- a/nuttx/tools/mkversion.c +++ b/nuttx/tools/mkversion.c @@ -41,7 +41,7 @@ #include #include -#include "cfgparser.h" +#include "cfgdefine.h" /**************************************************************************** * Definitions @@ -98,7 +98,7 @@ int main(int argc, char **argv, char **envp) printf("/* version.h -- Autogenerated! Do not edit. */\n\n"); printf("#ifndef __INCLUDE_NUTTX_VERSION_H\n"); printf("#define __INCLUDE_NUTTX_VERSION_H\n\n"); - parse_file(stream); + generate_definitions(stream); printf("\n#define CONFIG_VERSION ((CONFIG_VERSION_MAJOR << 8) | (CONFIG_VERSION_MINOR))\n\n"); printf("#endif /* __INCLUDE_NUTTX_VERSION_H */\n"); fclose(stream); -- cgit v1.2.3 From b66a46decca8ba8bc3570ca5d91d908f2e339c0d Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 4 Jan 2013 16:50:15 +0000 Subject: Working on configure.c git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5477 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/tools/Makefile.host | 4 +- nuttx/tools/cfgdefine.c | 2 +- nuttx/tools/cfgdefine.h | 2 +- nuttx/tools/cfgparser.c | 165 ++++++++++++++++++++-------------------------- nuttx/tools/cfgparser.h | 15 ++++- nuttx/tools/cmpconfig.c | 154 +------------------------------------------ 6 files changed, 91 insertions(+), 251 deletions(-) diff --git a/nuttx/tools/Makefile.host b/nuttx/tools/Makefile.host index 663ff29c7..73352aae3 100644 --- a/nuttx/tools/Makefile.host +++ b/nuttx/tools/Makefile.host @@ -89,8 +89,8 @@ endif # cmpconfig - Compare the contents of two configuration files -cmpconfig$(HOSTEXEEXT): cmpconfig.c - $(Q) $(HOSTCC) $(HOSTCFLAGS) -o cmpconfig$(HOSTEXEEXT) cmpconfig.c +cmpconfig$(HOSTEXEEXT): cmpconfig.c cfgparser.c + $(Q) $(HOSTCC) $(HOSTCFLAGS) -o cmpconfig$(HOSTEXEEXT) cmpconfig.c cfgparser.c ifdef HOSTEXEEXT cmpconfig: cmpconfig$(HOSTEXEEXT) diff --git a/nuttx/tools/cfgdefine.c b/nuttx/tools/cfgdefine.c index 00dd11c20..ee1dd4003 100644 --- a/nuttx/tools/cfgdefine.c +++ b/nuttx/tools/cfgdefine.c @@ -76,7 +76,7 @@ static const char *dequote_list[] = NULL /* Marks the end of the list */ }; - /**************************************************************************** +/**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/nuttx/tools/cfgdefine.h b/nuttx/tools/cfgdefine.h index 04817b719..f76ba73fb 100644 --- a/nuttx/tools/cfgdefine.h +++ b/nuttx/tools/cfgdefine.h @@ -59,6 +59,6 @@ extern char line[LINESIZE+1]; * Public Functions ****************************************************************************/ -extern void generate_definitions(FILE *stream); +void generate_definitions(FILE *stream); #endif /* __TOOLS_CFGDEFINE_H */ diff --git a/nuttx/tools/cfgparser.c b/nuttx/tools/cfgparser.c index 1a35f7857..cb4ab4c52 100644 --- a/nuttx/tools/cfgparser.c +++ b/nuttx/tools/cfgparser.c @@ -38,7 +38,9 @@ ****************************************************************************/ #include +#include #include + #include "cfgparser.h" /**************************************************************************** @@ -55,28 +57,7 @@ char line[LINESIZE+1]; * Private Data ****************************************************************************/ -/* These are configuration variable name that are quoted by configuration tool - * but which must be unquoted when used in C code. - */ - -static const char *dequote_list[] = -{ - /* NuttX */ - - "CONFIG_USER_ENTRYPOINT", /* Name of entry point function */ - - /* NxWidgets/NxWM */ - - "CONFIG_NXWM_BACKGROUND_IMAGE", /* Name of bitmap image class */ - "CONFIG_NXWM_STARTWINDOW_ICON", /* Name of bitmap image class */ - "CONFIG_NXWM_NXCONSOLE_ICON", /* Name of bitmap image class */ - "CONFIG_NXWM_CALIBRATION_ICON", /* Name of bitmap image class */ - "CONFIG_NXWM_HEXCALCULATOR_ICON", /* Name of bitmap image class */ - - NULL /* Marks the end of the list */ -}; - - /**************************************************************************** +/**************************************************************************** * Private Functions ****************************************************************************/ @@ -203,69 +184,15 @@ static void parse_line(char *ptr, char **varname, char **varval) } } -static char *dequote_value(const char *varname, char *varval) -{ - const char **dqnam; - char *dqval = varval; - int len; - - if (dqval) - { - /* Check if the variable name is in the list of strings to be dequoated */ - - for (dqnam = dequote_list; *dqnam; dqnam++) - { - if (strcmp(*dqnam, varname) == 0) - { - break; - } - } - - /* Did we find the variable name in the list of configuration variables - * to be dequoated? - */ - - if (*dqnam) - { - /* Yes... Check if there is a traiing quote */ - - len = strlen(dqval); - if (dqval[len-1] == '"') - { - /* Yes... replace it with a terminator */ - - dqval[len-1] = '\0'; - len--; - } - - /* Is there a leading quote? */ - - if (dqval[0] == '"') - { - /* Yes.. skip over the leading quote */ - - dqval++; - len--; - } - - /* Handle the case where nothing is left after dequoting */ - - if (len <= 0) - { - dqval = NULL; - } - } - } - - return dqval; -} - /**************************************************************************** * Public Functions ****************************************************************************/ -void parse_file(FILE *stream) +void parse_file(FILE *stream, struct variable_s **list) { + struct variable_s *curr; + struct variable_s *prev; + struct variable_s *next; char *varname; char *varval; char *ptr; @@ -283,40 +210,90 @@ void parse_file(FILE *stream) parse_line(ptr, &varname, &varval); - /* Was a variable name found? */ + /* If the variable has not value (or the special value 'n'), then + * ignore it. + */ - if (varname) + if (!varval || strcmp(varval, "n") == 0) { - /* Yes.. dequote the value if necessary */ + continue; + } + + /* Make sure that a variable name was found. */ - varval = dequote_value(varname, varval); + if (varname) + { + int varlen = strlen(varname) + 1; + int vallen = 0; - /* If no value was provided or if the special value 'n' was provided, - * then undefine the configuration variable. + /* Get the size of the value, including the NUL terminating + * character. */ - if (!varval || strcmp(varval, "n") == 0) + if (varval) { - printf("#undef %s\n", varname); + vallen = strlen(varval) + 1; } - /* Simply define the configuration variable if it has the special - * value "y" + /* Allocate memory to hold the struct variable_s with the + * variable name and the value. */ - else if (strcmp(varval, "y") == 0) + curr = (struct variable_s *)malloc(sizeof(struct variable_s) + varlen + vallen - 1); + if (curr) { - printf("#define %s 1\n", varname); + /* Add the variable to the list */ + + curr->var = &curr->storage[0]; + strcpy(curr->var, varname); + + curr->val = NULL; + if (varval) + { + curr->val = &curr->storage[varlen]; + strcpy(curr->val, varval); + } } - /* Otherwise, use the value as provided */ + prev = 0; + next = *list; + while (next && strcmp(next->var, curr->var) <= 0) + { + prev = next; + next = next->flink; + } + if (prev) + { + prev->flink = curr; + } else { - printf("#define %s %s\n", varname, varval); + *list = curr; } + + curr->flink = next; } } } while (ptr); } + +struct variable_s *find_variable(const char *varname, struct variable_s *list) +{ + char *varval1; + char *varval2; + + while (list) + { + if (strcmp(varname, list->var) == 0) + { + return list; + } + + list = list->flink; + } + + return NULL; +} + diff --git a/nuttx/tools/cfgparser.h b/nuttx/tools/cfgparser.h index b1c4bae76..b1f421a68 100644 --- a/nuttx/tools/cfgparser.h +++ b/nuttx/tools/cfgparser.h @@ -49,6 +49,18 @@ #define LINESIZE ( PATH_MAX > 256 ? PATH_MAX : 256 ) +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct variable_s +{ + struct variable_s *flink; + char *var; + char *val; + char storage[1]; +}; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -59,6 +71,7 @@ extern char line[LINESIZE+1]; * Public Functions ****************************************************************************/ -extern void parse_file(FILE *stream); +void parse_file(FILE *stream, struct variable_s **list); +struct variable_s *find_variable(const char *varname, struct variable_s *list); #endif /* __TOOLS_CFGPARSER_H */ diff --git a/nuttx/tools/cmpconfig.c b/nuttx/tools/cmpconfig.c index 2958acdc7..08b7dab3f 100644 --- a/nuttx/tools/cmpconfig.c +++ b/nuttx/tools/cmpconfig.c @@ -43,6 +43,8 @@ #include #include +#include "cfgparser.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -51,14 +53,6 @@ * Private Types ****************************************************************************/ -struct variable_s -{ - struct variable_s *flink; - char *var; - char *val; - char storage[1]; -}; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -69,150 +63,6 @@ static void show_usage(const char *progname) exit(EXIT_FAILURE); } -static char *skip_space(char *ptr) -{ - while (*ptr && isspace((int)*ptr)) ptr++; - return ptr; -} - -static char *read_line(FILE *stream, char *line, int len) -{ - char *ptr; - - for (;;) - { - line[len-1] = '\0'; - if (!fgets(line, len, stream)) - { - return NULL; - } - else - { - ptr = skip_space(line); - if (*ptr && *ptr != '#' && *ptr != '\n') - { - return ptr; - } - } - } -} - -static char *find_name_end(char *ptr) -{ - while (*ptr && (isalnum((int)*ptr) || *ptr == '_')) ptr++; - return ptr; -} - -static char *find_value_end(char *ptr) -{ - while (*ptr && !isspace((int)*ptr)) - { - if (*ptr == '"') - { - do ptr++; while (*ptr && *ptr != '"'); - if (*ptr) ptr++; - } - else - { - do ptr++; while (*ptr && !isspace((int)*ptr) && *ptr != '"'); - } - } - return ptr; -} - -static void parse_line(char *ptr, char **varname, char **varval) -{ - *varname = ptr; - *varval = NULL; - - ptr = find_name_end(ptr); - if (*ptr && *ptr != '=') - { - *ptr = '\0'; - ptr = skip_space(ptr + 1); - } - - if (*ptr == '=') - { - *ptr = '\0'; - ptr = skip_space(ptr + 1); - if (*ptr) - { - *varval = ptr; - ptr = find_value_end(ptr); - *ptr = '\0'; - } - } -} - -static void parse_file(FILE *stream, struct variable_s **list) -{ - char line[10242]; - struct variable_s *curr; - struct variable_s *prev; - struct variable_s *next; - char *varname; - char *varval; - char *ptr; - - do - { - ptr = read_line(stream, line, 1024); - if (ptr) - { - parse_line(ptr, &varname, &varval); - if (!varval || strcmp(varval, "n") == 0) - { - continue; - } - - if (varname) - { - int varlen = strlen(varname) + 1; - int vallen = 0; - - if (varval) - { - vallen = strlen(varval) + 1; - } - - curr = (struct variable_s *)malloc(sizeof(struct variable_s) + varlen + vallen - 1); - if (curr) - { - curr->var = &curr->storage[0]; - strcpy(curr->var, varname); - - curr->val = NULL; - if (varval) - { - curr->val = &curr->storage[varlen]; - strcpy(curr->val, varval); - } - } - - prev = 0; - next = *list; - while (next && strcmp(next->var, curr->var) <= 0) - { - prev = next; - next = next->flink; - } - - if (prev) - { - prev->flink = curr; - } - else - { - *list = curr; - } - curr->flink = next; - } - } - } - while (ptr); -} - static void compare_variables(struct variable_s *list1, struct variable_s *list2) { char *varval1; -- cgit v1.2.3 From 5c572a3cb50e6e52a641ee652d9e151b4c70661c Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 4 Jan 2013 21:37:31 +0000 Subject: Add tools/configure.c and configure.bat git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5478 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 11 +- nuttx/Documentation/NuttxPortingGuide.html | 31 +- nuttx/Makefile.win | 2 +- nuttx/README.txt | 21 +- nuttx/TODO | 16 +- nuttx/configs/README.txt | 24 +- nuttx/configs/stm32f4discovery/README.txt | 5 + nuttx/configs/xtrs/README.txt | 15 + nuttx/tools/README.txt | 27 +- nuttx/tools/cfgparser.c | 3 - nuttx/tools/configure.bat | 128 +++++ nuttx/tools/configure.c | 763 +++++++++++++++++++++++++++++ 12 files changed, 1003 insertions(+), 43 deletions(-) create mode 100644 nuttx/tools/configure.bat create mode 100644 nuttx/tools/configure.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2762faf66..710ffdceb 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3861,4 +3861,13 @@ * libc/misc/Make.defs: Fix error in conditional for KBD CODEC. * libc/Kconfig and configs/*/defconfig (several): The default setting should be CONFIG_LIB_KBDCODEC=n - + * tools/configure.c: configure.c can be used to build a work-alike + program as a replacement for configure.sh. This work-alike + program would be used in environments that do not support Bash + scripting (such as the Windows native environment). + * tools/configure.bat: configure.bat is a small Windows batch + file that can be used as a replacement for configure.sh in a + Windows native environment. configure.bat is actually just a + thin layer that execuates configure.exe if it is available. If + configure.exe is not available, then configure.bat will attempt + to build it first. diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index e626bf7a5..559253d45 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -1263,23 +1263,23 @@ tools/ |-- Makefile.host |-- Makefile.export |-- README.txt -|-- configure.sh +|-- configure.sh / configure.bat |-- cfgparser.c |-- cfgparser.h -|-- copydir.sh -|-- define.sh -|-- incdir.sh +|-- copydir.sh / copydir.bat +|-- define.sh / define.bat +|-- incdir.sh / indir.bat |-- indent.sh -|-- link.sh +|-- link.sh / link.bat |-- mkconfig.c -|-- mkdeps.sh +|-- mkdeps.sh / mkdeps.bat |-- mkexport.sh |-- mkimage.sh |-- mknulldeps.sh |-- mkromfsimg.sh |-- mksyscall.c |-- mkversion.c -|-- unlink.sh +|-- unlink.sh / unlink.bat |-- version.sh `-- zipme.sh
            @@ -1416,17 +1416,28 @@ netutils/ 

                 cd tools
-  ./configure.sh <board-name>[/<config-dir>]
+  ./configure.sh <board-name>[/<config-dir>]

            - And if configs/<board-name>/[<config-dir>/appconfig + There is an alternative Windows batch file, configure.bat, that can be used insteach of configure.sh in the windows native enironment like: +

            +
              +  cd tools
+  configure.bat <board-name>[\<config-dir>]
+
            +

            + See tools/README.txt for more information about these scripts. +

            + +

            + If configs/<board-name>/[<config-dir>]/appconfig exists and your application directory is not in the standard loction (../apps), then you should also specify the location of the application directory on the command line like: 

                 cd tools
-  ./configure.sh -a <app-dir> <board-name>[/<config-dir>]
+  ./configure.sh -a <app-dir> <board-name>[/<config-dir>]

            diff --git a/nuttx/Makefile.win b/nuttx/Makefile.win index fcf971d32..803d073b2 100644 --- a/nuttx/Makefile.win +++ b/nuttx/Makefile.win @@ -452,7 +452,7 @@ clean_context: # check_context # # This target checks if NuttX has been configured. NuttX is configured using -# the script tools\configure.sh. That script will install certain files in +# the script tools\configure.bat. That script will install certain files in # the top-level NuttX build directory. This target verifies that those # configuration files have been installed and that NuttX is ready to be built. diff --git a/nuttx/README.txt b/nuttx/README.txt index bfd057351..717c129b0 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -257,6 +257,14 @@ easier. It is used as follows: cd ${TOPDIR}/tools ./configure.sh / +There is an alternative Windows batch file that can be used in the +windows native enironment like: + + cd ${TOPDIR}\tools + configure.bat \ + +See tools/README.txt for more information about these scripts. + NuttX Configuration Tool ------------------------ @@ -401,6 +409,8 @@ Converting Older Configurations to use the Configuration Tool cd tools ./configure.sh / + (or configure.bat for the case of the Windows native build). + NOTE: If CONFIG_APPS_DIR is not defined in the defconfig file, the configure.sh script will find and add the new, correct path to the application directory (CONFIG_APPS_DIR) when it copies the @@ -682,10 +692,15 @@ Native Windows Build the you not install the optional MSYS components as there may be conflicts. This capability should still be considered a work in progress because: + (1) It has not been verfied on all targets and tools, and - (2) itstill lacks some of the creature-comforts of the more mature environments - (like a functional configure.sh script and 'make menuconfig' support. - See the section "NuttX Configuration Tool under DOS" above). + (2) it still lacks some of the creature-comforts of the more mature environments + (like 'make menuconfig' support. See the section "NuttX Configuration Tool + under DOS" above). + + There is an alternative to the setenv.sh script available for the Windows + native environment: tools/configure.bat. See tools/README.txt for additional + information. Installing GNUWin32 ------------------- diff --git a/nuttx/TODO b/nuttx/TODO index d37231e1d..4a70e577f 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -19,7 +19,7 @@ nuttx/ (5) Graphics subystem (graphics/) (1) Pascal add-on (pcode/) (1) Documentation (Documentation/) - (8) Build system / Toolchains + (7) Build system / Toolchains (5) Linux/Cywgin simulation (arch/sim) (6) ARM (arch/arm/) (1) ARM/C5471 (arch/arm/src/c5471/) @@ -1037,20 +1037,6 @@ o Build system Status: Open, there are some workarounds, but none are good. Priority: High - Title: configure.sh NOT AVAILABLE IN NATIVE WINDOWS BUILD - Description: configure.sh is a Bash script and cannot be used from a Windows - CMD.exe window. I started a configure.bat script, but I do - not have the batch file programming skills to duplicate some - of the more complex operations. - - I also considered adding a configure.c file that could be - compiled and then executed by configure.bat (and configure.sh?). - But I have not gone down that path yet. - - The current work-around is to configure under Cygwin. - Status: Open - Priority: High - o Linux/Cywgin simulation (arch/sim) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 4e9bcca14..6e7526ed0 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1960,16 +1960,24 @@ tools/configure.sh There is a script that automates these steps. The following steps will accomplish the same configuration: - cd tools - ./configure.sh / + cd tools + ./configure.sh / -And if configs///appconfig exists and your -application directory is not in the standard loction (../apps), then -you should also specify the location of the application directory on the -command line like: + There is an alternative Windows batch file that can be used in the + windows native enironment like: - cd tools - ./configure.sh -a / + cd ${TOPDIR}\tools + configure.bat \ + + See tools/README.txt for more information about these scripts. + + And if configs///appconfig exists and your + application directory is not in the standard loction (../apps), then + you should also specify the location of the application directory on the + command line like: + + cd tools + ./configure.sh -a / Building Symbol Tables ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index 571385abb..28072f44b 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -1011,6 +1011,11 @@ can be selected as follow: cd - . ./setenv.sh +If this is a Windows native build, then configure.bat should be used +instead of configure.sh: + + configure.bat STM32F4Discovery\ + Where is one of the following: cxxtest: diff --git a/nuttx/configs/xtrs/README.txt b/nuttx/configs/xtrs/README.txt index 1a63d3a90..d462dcab1 100644 --- a/nuttx/configs/xtrs/README.txt +++ b/nuttx/configs/xtrs/README.txt @@ -59,6 +59,11 @@ Configuring NuttX setenv.bat make + If this is a Windows native build, then configure.bat should be used + in step 1) instead of configure.sh: + + configure.bat xtrs\ostest + The setenv.bat will need to be updated to include the PATH to the XTRS hex2cmd program. @@ -90,6 +95,11 @@ Configuring NuttX setenv.bat make + If this is a Windows native build, then configure.bat should be used + in step 1) instead of configure.sh: + + configure.bat xtrs\nsh + The setenv.bat will need to be updated to include the PATH to the XTRS hex2cmd program. @@ -128,6 +138,11 @@ Configuring NuttX setenv.bat make + If this is a Windows native build, then configure.bat should be used + in step 1) instead of configure.sh: + + configure.bat xtrs\pashello + The setenv.bat will need to be updated to include the PATH to the XTRS hex2cmd program. diff --git a/nuttx/tools/README.txt b/nuttx/tools/README.txt index f9e2d1099..5651ff2f0 100644 --- a/nuttx/tools/README.txt +++ b/nuttx/tools/README.txt @@ -26,12 +26,35 @@ Config.mk override these default definitions as necessary. configure.sh +configure.bat +configure.c, cfgparser.c, and cfgparser.h ------------ - This is a bash script that is used to configure NuttX for a given - target board. See configs/README.txt or Documentation/NuttxPortingGuide.html + configure.sh is a bash script that is used to configure NuttX for a given + target board in a environment that supports POSIX paths (Linux, Cygwin, + OSX, or similar). See configs/README.txt or Documentation/NuttxPortingGuide.html for a description of how to configure NuttX with this script. + configure.c, cfgparser.c, and cfgparser.h can be used to build a work-alike + program as a replacement for configure.sh. This work-alike program would be + used in environments that do not support Bash scripting (such as the Windows + native environment). + + configure.bat is a small Windows batch file that can be used as a replacement + for configure.sh in a Windows native environment. configure.bat is actually + just a thin layer that execuates configure.exe if it is available. If + configure.exe is not available, then configure.bat will attempt to build it + first. + + In order two build configure.exe from configure.c in the Windows native + environment, two assumptions are made: + + 1) You have installed the MinGW GCC toolchain. This toolchain can be + downloaded from http://www.mingw.org/. Tt is recommended the you not + install the optional MSYS components as there may be conflicts. + 2) That path to bin bin/ directory containing mingw-gcc.exe must be + included in the PATH variable. + discover.py ----------- diff --git a/nuttx/tools/cfgparser.c b/nuttx/tools/cfgparser.c index cb4ab4c52..ac25bd26b 100644 --- a/nuttx/tools/cfgparser.c +++ b/nuttx/tools/cfgparser.c @@ -281,9 +281,6 @@ void parse_file(FILE *stream, struct variable_s **list) struct variable_s *find_variable(const char *varname, struct variable_s *list) { - char *varval1; - char *varval2; - while (list) { if (strcmp(varname, list->var) == 0) diff --git a/nuttx/tools/configure.bat b/nuttx/tools/configure.bat new file mode 100644 index 000000000..c28558fbb --- /dev/null +++ b/nuttx/tools/configure.bat @@ -0,0 +1,128 @@ +@echo off + +rem tools/configure.bat +rem +rem Copyright (C) 2012 Gregory Nutt. All rights reserved. +rem Author: Gregory Nutt +rem +rem Redistribution and use in source and binary forms, with or without +rem modification, are permitted provided that the following conditions +rem are met: +rem +rem 1. Redistributions of source code must retain the above copyright +rem notice, this list of conditions and the following disclaimer. +rem 2. Redistributions in binary form must reproduce the above copyright +rem notice, this list of conditions and the following disclaimer in +rem the documentation and/or other materials provided with the +rem distribution. +rem 3. Neither the name NuttX nor the names of its contributors may be +rem used to endorse or promote products derived from this software +rem without specific prior written permission. +rem +rem THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +rem "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +rem LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +rem FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +rem COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +rem INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +rem BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +rem OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +rem AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +rem LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +rem ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +rem POSSIBILITY OF SUCH DAMAGE. +rem + +rem Parse command line arguments + +set debug= +set fmt=-w +set posix= +set help= +set appdir= +set config= + +:ArgLoop +if "%1"=="" goto :NoConfig +if "%1"=="-h" goto :ShowUsage +if "%1"=="-d" goto :SetDebug +if "%1"=="-w" goto :SetWindows +if "%1"=="-l" goto :SetPosix +if "%1"=="-a" goto :SetAppDir + +set config=%1 +goto EndOfLoop + +:SetDebug +set debug=-d +goto :NextArg + +:SetWindows +set fmt=-w +goto :NextArg + +:SetWindows +set fmt=-l +goto :NextArg + +:SetAppDir +shift +set appdir=-a %1 + +:NextArg +shift +goto :ArgLoop + +:EndOfLoop + +rem Check if we have to build configure.exe + +if exist configure.exe goto :HaveConfigureExe + +set cc=mingw32-gcc.exe +set cflags=-Wall -Wstrict-prototypes -Wshadow -g -pipe -I. -DCONFIG_WINDOWS_NATIVE=y +%cc% %cflags% -o configure.exe configure.c cfgparser.c +if errorlevel 1 ( + echo ERROR: %cc% failed + echo Is ming32-gcc.exe installed? Is it in the PATH variable? + goto End +) + +:HaveConfigureExe +configure.exe %debug% %fmt% %appdir% %config% +if errorlevel 1 echo configure.exe failed +goto End + + +:NoConfig +echo Missing ^/^ argument + +:ShowUsage +echo USAGE: %0 [-d] [-w] [-l] [-h] [-a ^] ^\^ +echo\nWhere: +echo ^: +echo Identifies the board. This must correspond to a board directory +echo under nuttx/configs/. +echo ^: +echo Identifies the specific configuratin for the selected ^. +echo This must correspond to a sub-directory under the board directory at +echo under nuttx/configs/^/. +echo ^<-d^>: +echo Enables debug output +echo ^<-w^>: +echo Informs the tool that it should use Windows style paths like C:\\Program Files +echo instead of POSIX style paths are used like /usr/local/bin. Windows +echo style paths are used by default. +echo ^<-l^>: +echo Informs the tool that it should use POSIX style paths like /usr/local/bin. +echo By default, Windows style paths like C:\\Program Files are used. +echo -a ^: +echo Informs the configuration tool where the application build +echo directory. This is a relative path from the top-level NuttX +echo build directory. But default, this tool will look in the usual +echo places to try to locate the application directory: ../apps or +echo ../apps-xx.yy where xx.yy is the NuttX version number. +echo ^<-h^>: +echo Prints this message and exits. + +:End diff --git a/nuttx/tools/configure.c b/nuttx/tools/configure.c new file mode 100644 index 000000000..f189f5b98 --- /dev/null +++ b/nuttx/tools/configure.c @@ -0,0 +1,763 @@ +/**************************************************************************** + * tools/configure.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cfgparser.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BUFFER_SIZE 1024 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_WINDOWS_NATIVE +static char g_delim = '\\'; /* Delimiter to use when forming paths */ +static bool g_winpaths = true; /* True: Windows style paths */ +#else +static char g_delim = '/'; /* Delimiter to use when forming paths */ +static bool g_winpaths = false; /* False: POSIX style paths */ +#endif +static bool g_debug = false; /* Enable debug output */ + +static const char *g_appdir = NULL; /* Relative path to the applicatin directory */ +static const char *g_boarddir = NULL; /* Name of board subdirectory */ +static char *g_configdir = NULL; /* Name of configuration subdirectory */ + +static char *g_topdir = NULL; /* Full path to top-level NuttX build directory */ +static char *g_apppath = NULL; /* Full path to the applicatino directory */ +static char *g_configpath = NULL; /* Full path to the configuration directory */ +static char *g_verstring = "0.0"; /* Version String */ + +static char *g_srcdefconfig = NULL; /* Source defconfig file */ +static char *g_srcmakedefs = NULL; /* Source Make.defs file */ +static char *g_srcappconfig = NULL ; /* Source appconfig file (optional) */ +static char *g_srcsetenvsh = NULL; /* Source setenv.sh file (optional) */ +static char *g_srcsetenvbat = NULL; /* Source setenv.bat file (optional) */ + +static bool g_newconfig = false; /* True: New style configuration */ +static bool g_winnative = false; /* True: Windows native configuration */ +static bool g_needapppath = true; /* Need to add app path to the .config file */ + +static char g_buffer[BUFFER_SIZE]; /* Scratch buffer for forming full paths */ + +static struct variable_s *g_configvars = NULL; +static struct variable_s *g_versionvars = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void show_usage(const char *progname, int exitcode) +{ + fprintf(stderr, "\nUSAGE: %s [-d] [-w] [-l] [-h] [-a ] %c\n", progname, g_delim); + fprintf(stderr, "\nWhere:\n"); + fprintf(stderr, " :\n"); + fprintf(stderr, " Identifies the board. This must correspond to a board directory\n"); + fprintf(stderr, " under nuttx%cconfigs%c.\n", g_delim, g_delim); + fprintf(stderr, " :\n"); + fprintf(stderr, " Identifies the specific configuratin for the selected .\n"); + fprintf(stderr, " This must correspond to a sub-directory under the board directory at\n"); + fprintf(stderr, " under nuttx%cconfigs%c%c.\n", g_delim, g_delim, g_delim); + fprintf(stderr, " <-d>:\n"); + fprintf(stderr, " Enables debug output\n"); + fprintf(stderr, " <-w>:\n"); +#ifdef CONFIG_WINDOWS_NATIVE + fprintf(stderr, " Informs the tool that it should use Windows style paths like C:\\Program Files\n"); + fprintf(stderr, " instead of POSIX style paths are used like /usr/local/bin. Windows\n"); + fprintf(stderr, " style paths are used by default.\n"); +#else + fprintf(stderr, " Informs the tool that it should use Windows style paths like C:\\Program Files.\n"); + fprintf(stderr, " By default, POSIX style paths like /usr/local/bin are used.\n"); +#endif + fprintf(stderr, " <-l>:\n"); +#ifdef CONFIG_WINDOWS_NATIVE + fprintf(stderr, " Informs the tool that it should use POSIX style paths like /usr/local/bin.\n"); + fprintf(stderr, " By default, Windows style paths like C:\\Program Files are used.\n"); +#else + fprintf(stderr, " Informs the tool that it should use POSIX style paths like /usr/local/bin\n"); + fprintf(stderr, " instead of Windows style paths like C:\\Program Files are used. POSIX\n"); + fprintf(stderr, " style paths are used by default.\n"); +#endif + fprintf(stderr, " -a :\n"); + fprintf(stderr, " Informs the configuration tool where the application build\n"); + fprintf(stderr, " directory. This is a relative path from the top-level NuttX\n"); + fprintf(stderr, " build directory. But default, this tool will look in the usual\n"); + fprintf(stderr, " places to try to locate the application directory: ..%capps or\n", g_delim); + fprintf(stderr, " ..%capps-xx.yy where xx.yy is the NuttX version number.\n", g_delim); + fprintf(stderr, " <-h>:\n"); + fprintf(stderr, " Prints this message and exits.\n"); + exit(exitcode); +} + +static void debug(const char *fmt, ...) +{ + va_list ap; + + if (g_debug) + { + va_start(ap, fmt); + (void)vprintf(fmt, ap); + va_end(ap); + } +} + +static void parse_args(int argc, char **argv) +{ + char *ptr; + int ch; + + /* Parse command line options */ + + g_debug = false; + + while ((ch = getopt(argc, argv, ":a:dwlh")) > 0) + { + switch (ch) + { + case 'a' : + g_appdir = optarg; + break; + + case 'd' : + g_debug = true; + break; + + case 'w' : + g_delim = '/'; + g_winpaths = true; + break; + + case 'l' : + g_delim = '\\'; + g_winpaths = false; + break; + + case 'h' : + show_usage(argv[0], EXIT_SUCCESS); + + case '?' : + fprintf(stderr, "ERROR: Unrecognized option: %c\n", optopt); + show_usage(argv[0], EXIT_FAILURE); + + case ':' : + fprintf(stderr, "ERROR: Missing option argument, option: %c\n", optopt); + show_usage(argv[0], EXIT_FAILURE); + + break; + fprintf(stderr, "ERROR: Unexpected option: %c\n", ch); + show_usage(argv[0], EXIT_FAILURE); + } + } + + /* There should be exactly one argument following the options */ + + if (optind >= argc) + { + fprintf(stderr, "ERROR: Missing %c\n", g_delim); + show_usage(argv[0], EXIT_FAILURE); + } + + /* The required option should be the board directory name and the + * configuration directory name separated by '/' or '\'. Either is + * acceptable in this context. + */ + + g_boarddir = argv[optind]; + optind++; + + ptr = strchr(g_boarddir, '/'); + if (!ptr) + { + ptr = strchr(g_boarddir, '\\'); + } + + if (!ptr) + { + fprintf(stderr, "ERROR: Invalid %c\n", g_delim); + show_usage(argv[0], EXIT_FAILURE); + } + + *ptr++ = '\0'; + g_configdir = ptr; + + if (optind < argc) + { + fprintf(stderr, "Unexpected garbage at the end of the line\n"); + show_usage(argv[0], EXIT_FAILURE); + } +} + +static void verify_directory(const char *directory) +{ + struct stat buf; + + if (stat(directory, &buf) < 0) + { + fprintf(stderr, "ERROR: stat of %s failed: %s\n", directory, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (!S_ISDIR(buf.st_mode)) + { + fprintf(stderr, "ERROR: %s exists but is not a directory\n", directory); + exit(EXIT_FAILURE); + } +} + +static bool verify_optiondir(const char *directory) +{ + struct stat buf; + + if (stat(directory, &buf) < 0) + { + /* It may be okay if the dirctory does not exist */ + + debug("verify_optiondir: stat of %s failed: %s\n", directory, strerror(errno)); + return false; + } + + if (!S_ISDIR(buf.st_mode)) + { + fprintf(stderr, "ERROR: %s exists but is not a directory\n", directory); + exit(EXIT_FAILURE); + } + + return true; +} + +static void verify_file(const char *path) +{ + struct stat buf; + + if (stat(path, &buf) < 0) + { + fprintf(stderr, "ERROR: stat of %s failed: %s\n", path, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (!S_ISREG(buf.st_mode)) + { + fprintf(stderr, "ERROR: %s exists but is not a regular file\n", path); + exit(EXIT_FAILURE); + } +} + +static bool verify_optionfile(const char *path) +{ + struct stat buf; + + if (stat(path, &buf) < 0) + { + /* It may be okay if the file does not exist */ + + debug("verify_optionfile: stat of %s failed: %s\n", path, strerror(errno)); + return false; + } + + if (!S_ISREG(buf.st_mode)) + { + fprintf(stderr, "ERROR: %s exists but is not a regular file\n", path); + exit(EXIT_FAILURE); + } + + return true; +} + +static void get_topdir(void) +{ + /* Get and verify the top-level NuttX directory */ + + if (getcwd(g_buffer, BUFFER_SIZE) == NULL) + { + fprintf(stderr, "ERROR: getcwd failed: %s\n", strerror(errno)); + exit(EXIT_FAILURE); + } + + g_topdir = strdup(dirname(g_buffer)); + debug("get_topdir: Checking topdir=%s\n", g_topdir); + verify_directory(g_topdir); +} + +static void check_configdir(void) +{ + /* Get and verify the path to the selected configuration */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%cconfigs%c%s%c%s", + g_topdir, g_delim, g_delim, g_boarddir, g_delim, g_configdir); + g_configpath = strdup(g_buffer); + debug("check_configdir: Checking configpath=%s\n", g_configpath); + verify_directory(g_configpath); +} + +static void read_configfile(void) +{ + FILE *stream; + + snprintf(g_buffer, BUFFER_SIZE, "%s%cdefconfig", g_configpath, g_delim); + stream = fopen(g_buffer, "r"); + if (!stream) + { + fprintf(stderr, "ERROR: failed to open %s for reading: %s\n", + g_buffer, strerror(errno)); + exit(EXIT_FAILURE); + } + + parse_file(stream, &g_configvars); + fclose(stream); +} + +static void read_versionfile(void) +{ + FILE *stream; + + snprintf(g_buffer, BUFFER_SIZE, "%s%c.version", g_topdir, g_delim); + stream = fopen(g_buffer, "r"); + if (!stream) + { + /* It may not be an error if there is no .version file */ + + debug("Failed to open %s for reading: %s\n", + g_buffer, strerror(errno)); + } + else + { + parse_file(stream, &g_versionvars); + fclose(stream); + } +} + +static void get_verstring(void) +{ + struct variable_s *var; + + if (g_versionvars) + { + var = find_variable("CONFIG_VERSION_STRING", g_versionvars); + if (var && var->val) + { + g_verstring = strdup(var->val); + } + } + + debug("get_verstring: Version string=%s\n", g_verstring); +} + +static bool verify_appdir(const char *appdir) +{ + /* Does this directory exist? */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%c%s", g_topdir, g_delim, appdir); + debug("verify_appdir: Checking apppath=%s\n", g_buffer); + if (verify_optiondir(g_buffer)) + { + /* Yes.. Use this application directory path */ + + g_appdir = strdup(appdir); + g_apppath = strdup(g_buffer); + return true; + } + + debug("verify_appdir: apppath=%s does not exist\n", g_buffer); + return false; +} + +static void check_appdir(void) +{ + char tmp[16]; + + /* Get and verify the full path to the application directory */ + /* Was the appdir provided on the command line? */ + + debug("check_appdir: Command line appdir=%s\n", + g_appdir ? g_appdir : ""); + + if (!g_appdir) + { + /* No, was the path provided in the configuration? */ + + struct variable_s *var = find_variable("CONFIG_APP_DIR", g_configvars); + if (var) + { + debug("check_appdir: Config file appdir=%s\n", + var->val ? var->val : ""); + + /* Yes.. does this directory exist? */ + + if (var->val && verify_appdir(var->val)) + { + /* We are using the CONFIG_APP_DIR setting already + * in the defconfig file. + */ + + g_needapppath = false; + return; + } + } + + /* Now try some canned locations */ + + /* Try ../apps-xx.yy where xx.yy is the version string */ + + snprintf(tmp, 16, ".%capps-%s", g_delim, g_verstring); + debug("check_appdir: Try appdir=%s\n", tmp); + if (verify_appdir(tmp)) + { + return; + } + + /* Try ../apps with no version */ + + snprintf(tmp, 16, "..%capps", g_delim); + debug("check_appdir: Try appdir=%s\n", tmp); + if (verify_appdir(tmp)) + { + return; + } + + /* Try ../apps-xx.yy where xx.yy are the NuttX version number */ + + fprintf(stderr, "ERROR: Could not find the path to the application directory\n"); + exit(EXIT_FAILURE); + } + else + { + snprintf(g_buffer, BUFFER_SIZE, "%s%c%s", g_topdir, g_delim, g_appdir); + if (!verify_appdir(g_buffer)) + { + fprintf(stderr, "ERROR: Command line path to application directory does not exist\n"); + exit(EXIT_FAILURE); + } + } +} + +static void check_configuration(void) +{ + struct variable_s *var; + + /* Check if this the new style configuration based on kconfig-fontends */ + + var = find_variable("CONFIG_NUTTX_NEWCONFIG", g_configvars); + if (var && var->val && strcmp("y", var->val) == 0) + { + debug("check_configuration: New style configuration\n"); + g_newconfig = true; + } + + /* Check if this is a Windows native configuration */ + + var = find_variable("CONFIG_WINDOWS_NATIVE", g_configvars); + if (var && var->val && strcmp("y", var->val) == 0) + { + debug("check_configuration: Windows native configuration\n"); + g_winnative = true; + } + + /* All configurations must provide a defconfig and Make.defs file */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%cdefconfig", g_configpath, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + verify_file(g_buffer); + g_srcdefconfig = strdup(g_buffer); + + snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_configpath, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + verify_file(g_buffer); + g_srcmakedefs = strdup(g_buffer); + + /* Windows native configurations may provide setenv.bat; POSIX + * configurations may provide a setenv.sh. + */ + + if (g_winnative) + { + snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.bat", g_configpath, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + if (verify_optionfile(g_buffer)) + { + g_srcsetenvbat = strdup(g_buffer); + } + } + else + { + snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.sh", g_configpath, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + if (verify_optionfile(g_buffer)) + { + g_srcsetenvsh = strdup(g_buffer); + } + } + + /* Old style configurations MUST provide an appconfig file */ + + if (!g_newconfig) + { + snprintf(g_buffer, BUFFER_SIZE, "%s%cappconfig", g_configpath, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + verify_file(g_buffer); + g_srcappconfig = strdup(g_buffer); + } +} + +static void copy_file(const char *srcpath, const char *destpath) +{ + int nbytesread; + int nbyteswritten; + int rdfd; + int wrfd; + + /* Open the source file for reading */ + + rdfd = open(srcpath, O_RDONLY); + if (rdfd < 0) + { + fprintf(stderr, "ERROR: Failed to open %s for reading: %s\n", srcpath, strerror(errno)); + exit(EXIT_FAILURE); + } + + /* Now open the destination for writing*/ + + wrfd = open(destpath, O_WRONLY|O_CREAT|O_TRUNC, 0666); + if (wrfd < 0) + { + fprintf(stderr, "ERROR: Failed to open %s for writing: %s\n", destpath, strerror(errno)); + exit(EXIT_FAILURE); + } + + /* Now copy the file */ + + for (;;) + { + do + { + nbytesread = read(rdfd, g_buffer, BUFFER_SIZE); + if (nbytesread == 0) + { + /* End of file */ + + close(rdfd); + close(wrfd); + return; + } + else if (nbytesread < 0) + { + /* EINTR is not an error (but will still stop the copy) */ + + fprintf(stderr, "ERROR: Read failure: %s\n", strerror(errno)); + exit(EXIT_FAILURE); + } + } + while (nbytesread <= 0); + + do + { + nbyteswritten = write(wrfd, g_buffer, nbytesread); + if (nbyteswritten >= 0) + { + nbytesread -= nbyteswritten; + } + else + { + /* EINTR is not an error (but will still stop the copy) */ + + fprintf(stderr, "ERROR: Write failure: %s\n", strerror(errno)); + exit(EXIT_FAILURE); + } + } + while (nbytesread > 0); + } +} + +static void substitute(char *str, int ch1, int ch2) +{ + for (; *str; str++) + { + if (*str == ch1) + { + *str = ch2; + } + } +} + +static void configure(void) +{ + char *destconfig; + + /* Copy the defconfig file as .config */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_topdir, g_delim); + destconfig = strdup(g_buffer); + debug("configure: Copying from %s to %s\n", g_srcdefconfig, destconfig); + copy_file(g_srcdefconfig, destconfig); + + /* Copy the Make.defs file as Make.defs */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_topdir, g_delim); + debug("configure: Copying from %s to %s\n", g_srcmakedefs, g_buffer); + copy_file(g_srcmakedefs, g_buffer); + + /* Copy the setenv.sh file if have one and need one */ + + if (g_srcsetenvsh) + { + snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.sh", g_topdir, g_delim); + debug("configure: Copying from %s to %s\n", g_srcsetenvsh, g_buffer); + copy_file(g_srcsetenvsh, g_buffer); + + /* Mark the file executable */ + + if (chmod(g_buffer, 0777) != 0) + { + fprintf(stderr, "ERROR: Failed to make setenv.sh executable: %s\n", strerror(errno)); + exit(EXIT_FAILURE); + } + } + + /* Copy the setenv.bat file if have one and need one */ + + if (g_srcsetenvbat) + { + snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.bat", g_topdir, g_delim); + debug("configure: Copying from %s to %s\n", g_srcsetenvbat, g_buffer); + copy_file(g_srcsetenvbat, g_buffer); + } + + /* Copy the appconfig file to ../apps/.config if have one and need one */ + + if (g_srcappconfig) + { + snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_apppath, g_delim); + debug("configure: Copying from %s to %s\n", g_srcappconfig, g_buffer); + copy_file(g_srcappconfig, g_buffer); + } + + /* If we did not use the CONFIG_APPS_DIR that was in the defconfig config file, + * then append the correct application information to the tail of the .config + * file + */ + + if (g_needapppath) + { + FILE *stream; + char *appdir = strdup(g_appdir); + + /* One complexity is if we are using Windows paths, but the configuration + * needs POSIX paths (or vice versa). + */ + + if (g_winpaths != g_winnative) + { + /* Not the same */ + + if (g_winpaths) + { + /* Using Windows paths, but the configuration wants POSIX paths */ + + substitute(appdir, '\\', '/'); + } + else + { + /* Using POSIX paths, but the configuration wants Windows paths */ + + substitute(appdir, '/', '\\'); + } + } + + /* Open the file for appending */ + + stream = fopen(destconfig, "a"); + if (!stream) + { + fprintf(stderr, "ERROR: Failed to open %s for append mode mode: %s\n", + destconfig, strerror(errno)); + exit(EXIT_FAILURE); + } + + fprintf(stream, "\n# Application configuration\n\n"); + fprintf(stream, "CONFIG_APPS_DIR=\"%s\"\n", appdir); + fclose(stream); + free(appdir); + } + + free(destconfig); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int main(int argc, char **argv, char **envp) +{ + debug("main: Checking arguments\n"); + parse_args(argc, argv); + + debug("main: Checking Nuttx Directories\n"); + get_topdir(); + check_configdir(); + + debug("main: Reading the configuration/version files\n"); + read_configfile(); + read_versionfile(); + get_verstring(); + + debug("main: Checking Configuration Directory\n"); + check_configuration(); + + debug("main: Checking Application Directories\n"); + check_appdir(); + debug("main: Using apppath=%s\n", g_apppath ? g_apppath : ""); + + debug("main: Configuring\n"); + configure(); + return EXIT_SUCCESS; +} -- cgit v1.2.3 From 470c2e71df47a3ad527afe4b20dbe8988c3f8575 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 5 Jan 2013 13:19:53 +0000 Subject: Correct some errors in the LPC17xx SYSCON register bit definitions (from Rommel Marcello) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5479 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 ++ nuttx/Documentation/NuttX.html | 2 +- nuttx/Documentation/NuttxPortingGuide.html | 2 +- nuttx/README.txt | 2 +- nuttx/TODO | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h | 16 ++++++++-------- nuttx/tools/configure.c | 22 +++++++--------------- nuttx/tools/configure.sh | 21 +++++++-------------- 8 files changed, 28 insertions(+), 41 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 710ffdceb..cce091587 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3871,3 +3871,5 @@ thin layer that execuates configure.exe if it is available. If configure.exe is not available, then configure.bat will attempt to build it first. + * arch/arm/src/lpc17xx/lpc17_syscon.h: Correct some typos in bit + definitions (from Rommel Marcelo). diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index dc454c0b6..876aa2a0a 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@

            NuttX RTOS

            -

            Last Updated: December 28, 2012

            +

            Last Updated: January 4, 2012

            diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 559253d45..24b4852e0 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

            NuttX RTOS Porting Guide

            -

            Last Updated: December 18, 2012

            +

            Last Updated: January 4, 2012

            diff --git a/nuttx/README.txt b/nuttx/README.txt index 717c129b0..0348f7f30 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -687,7 +687,7 @@ Native Windows Build Build Tools. The build still relies on some Unix-like commands. I use the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/. - Host Compiler: I use the MingGW compiler which can be downloaded from + Host Compiler: I use the MingGW GCC compiler which can be downloaded from http://www.mingw.org/. If you are using GNUWin32, then it is recommended the you not install the optional MSYS components as there may be conflicts. diff --git a/nuttx/TODO b/nuttx/TODO index 4a70e577f..02100e97e 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated December 20, 2012) +NuttX TODO List (Last updated January 4, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h index ce8654645..3b9c32526 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h @@ -242,29 +242,29 @@ #define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ #define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) - /* Bit 15: Reserved */ + /* Bit 15: Reserved */ #define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ #define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) #define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ #define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ #define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ - /* Bits 27-31: Reserved */ + /* Bits 27-31: Reserved */ /* PLL1 Status register */ -#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL01Multiplier value readback */ +#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ #define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) #define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ #define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) /* Bit 7: Reserved */ -#define SYSCON_PLL1STAT_PLLE (1 << 24) /* Bit 8: PLL1 enable readback */ -#define SYSCON_PLL1STAT_PLLC (1 << 25) /* Bit 9: PLL1 connect readback */ -#define SYSCON_PLL1STAT_PLOCK (1 << 26) /* Bit 10: PLL1 lock status */ - /* Bits 11-31: Reserved */ +#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ +#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ +#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ + /* Bits 11-31: Reserved */ /* PLL0/1 Feed register */ #define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ #define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) - /* Bits 8-31: Reserved */ + /* Bits 8-31: Reserved */ /* Clocking and power control -- Clock dividers */ /* CPU Clock Configuration register */ diff --git a/nuttx/tools/configure.c b/nuttx/tools/configure.c index f189f5b98..eb8268f19 100644 --- a/nuttx/tools/configure.c +++ b/nuttx/tools/configure.c @@ -549,7 +549,7 @@ static void check_configuration(void) } } -static void copy_file(const char *srcpath, const char *destpath) +static void copy_file(const char *srcpath, const char *destpath, mode_t mode) { int nbytesread; int nbyteswritten; @@ -567,7 +567,7 @@ static void copy_file(const char *srcpath, const char *destpath) /* Now open the destination for writing*/ - wrfd = open(destpath, O_WRONLY|O_CREAT|O_TRUNC, 0666); + wrfd = open(destpath, O_WRONLY|O_CREAT|O_TRUNC, mode); if (wrfd < 0) { fprintf(stderr, "ERROR: Failed to open %s for writing: %s\n", destpath, strerror(errno)); @@ -638,13 +638,13 @@ static void configure(void) snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_topdir, g_delim); destconfig = strdup(g_buffer); debug("configure: Copying from %s to %s\n", g_srcdefconfig, destconfig); - copy_file(g_srcdefconfig, destconfig); + copy_file(g_srcdefconfig, destconfig, 0644); /* Copy the Make.defs file as Make.defs */ snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_topdir, g_delim); debug("configure: Copying from %s to %s\n", g_srcmakedefs, g_buffer); - copy_file(g_srcmakedefs, g_buffer); + copy_file(g_srcmakedefs, g_buffer, 0644); /* Copy the setenv.sh file if have one and need one */ @@ -652,15 +652,7 @@ static void configure(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.sh", g_topdir, g_delim); debug("configure: Copying from %s to %s\n", g_srcsetenvsh, g_buffer); - copy_file(g_srcsetenvsh, g_buffer); - - /* Mark the file executable */ - - if (chmod(g_buffer, 0777) != 0) - { - fprintf(stderr, "ERROR: Failed to make setenv.sh executable: %s\n", strerror(errno)); - exit(EXIT_FAILURE); - } + copy_file(g_srcsetenvsh, g_buffer, 0755); } /* Copy the setenv.bat file if have one and need one */ @@ -669,7 +661,7 @@ static void configure(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.bat", g_topdir, g_delim); debug("configure: Copying from %s to %s\n", g_srcsetenvbat, g_buffer); - copy_file(g_srcsetenvbat, g_buffer); + copy_file(g_srcsetenvbat, g_buffer, 0644); } /* Copy the appconfig file to ../apps/.config if have one and need one */ @@ -678,7 +670,7 @@ static void configure(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_apppath, g_delim); debug("configure: Copying from %s to %s\n", g_srcappconfig, g_buffer); - copy_file(g_srcappconfig, g_buffer); + copy_file(g_srcappconfig, g_buffer, 0644); } /* If we did not use the CONFIG_APPS_DIR that was in the defconfig config file, diff --git a/nuttx/tools/configure.sh b/nuttx/tools/configure.sh index ffa997178..89f2e2fbc 100755 --- a/nuttx/tools/configure.sh +++ b/nuttx/tools/configure.sh @@ -125,7 +125,6 @@ else fi src_config="${configpath}/defconfig" -tmp_config="${TOPDIR}/.configX" dest_config="${TOPDIR}/.config" if [ ! -r "${src_config}" ]; then @@ -201,7 +200,7 @@ if [ "X${have_setenv}" = "Xy" ]; then { echo "Failed to copy ${src_setenv}" ; exit 8 ; } chmod 755 "${dest_setenv}" fi -install "${src_config}" "${tmp_config}" || \ +install "${src_config}" "${dest_config}" || \ { echo "Failed to copy \"${src_config}\"" ; exit 9 ; } # If we did not use the CONFIG_APPS_DIR that was in the defconfig config file, @@ -209,14 +208,14 @@ install "${src_config}" "${tmp_config}" || \ # file if [ "X${defappdir}" = "Xy" ]; then - sed -i -e "/^CONFIG_APPS_DIR/d" "${tmp_config}" - echo "" >> "${tmp_config}" - echo "# Application configuration" >> "${tmp_config}" - echo "" >> "${tmp_config}" + sed -i -e "/^CONFIG_APPS_DIR/d" "${dest_config}" + echo "" >> "${dest_config}" + echo "# Application configuration" >> "${dest_config}" + echo "" >> "${dest_config}" if [ "X${winnative}" = "Xy" ]; then - echo "CONFIG_APPS_DIR=\"$winappdir\"" >> "${tmp_config}" + echo "CONFIG_APPS_DIR=\"$winappdir\"" >> "${dest_config}" else - echo "CONFIG_APPS_DIR=\"$posappdir\"" >> "${tmp_config}" + echo "CONFIG_APPS_DIR=\"$posappdir\"" >> "${dest_config}" fi fi @@ -232,9 +231,3 @@ if [ ! -z "${appdir}" -a "X${newconfig}" != "Xy" ]; then { echo "Failed to copy ${configpath}/appconfig" ; exit 10 ; } fi fi - -# install the final .configX only if it differs from any existing -# .config file. - -install "${tmp_config}" "${dest_config}" -rm -f "${tmp_config}" -- cgit v1.2.3 From 3e91a8a290fddb2b7755ac32fd1b8b318fc013a5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 5 Jan 2013 14:57:43 +0000 Subject: Clean up a few tools/ build issues git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5480 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/tools/Makefile.host | 27 +++++++++++++++++++-------- nuttx/tools/cmpconfig.c | 7 ++++--- nuttx/tools/configure.bat | 1 - nuttx/tools/mksyscall.c | 6 ++++-- 4 files changed, 27 insertions(+), 14 deletions(-) diff --git a/nuttx/tools/Makefile.host b/nuttx/tools/Makefile.host index 73352aae3..998d38916 100644 --- a/nuttx/tools/Makefile.host +++ b/nuttx/tools/Makefile.host @@ -37,13 +37,29 @@ TOPDIR ?= ${shell pwd}/.. -include $(TOPDIR)/Make.defs include ${TOPDIR}/tools/Config.mk +# Define HOSTCC on the make command line if it differs from these defaults +# Define HOSTCFLAGS with -g on the make command line to build debug versions + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + +# In the Windows native environment, the MinGW GCC compiler is assumed + +HOSTCC ?= mingw-gcc.exe +HOSTCFLAGS ?= -O2 -Wall -Wstrict-prototypes -Wshadow -I. -DCONFIG_WINDOWS_NATIVE=y + +else + +# GCC is assumed in the POSIX environment. # strtok_r is used in some tools, but does not seem to be available in # the MinGW environment. -ifneq ($(CONFIG_WINDOWS_NATIVE),y) - HOSTCFLAGS += -D HAVE_STRTOK_C +HOSTCC ?= gcc +HOSTCFLAGS ?= -O2 -Wall -Wstrict-prototypes -Wshadow -I. -DHAVE_STRTOK_C + endif +# Targets + all: b16$(HOSTEXEEXT) bdf-converter$(HOSTEXEEXT) cmpconfig$(HOSTEXEEXT) \ configure$(HOSTEXEEXT) mkconfig$(HOSTEXEEXT) mkdeps$(HOSTEXEEXT) mksymtab$(HOSTEXEEXT) \ mksyscall$(HOSTEXEEXT) mkversion$(HOSTEXEEXT) @@ -55,12 +71,7 @@ else .PHONY: clean endif -# Add HOSTCFLAGS=-g on the make command line build debug versions - -HOSTCFLAGS ?= -O2 -Wall -I. -HOSTCC ?= gcc - -# b16 - Fixed precision math converstion tool +# b16 - Fixed precision math conversion tool b16$(HOSTEXEEXT): b16.c $(Q) $(HOSTCC) $(HOSTCFLAGS) -o b16$(HOSTEXEEXT) b16.c diff --git a/nuttx/tools/cmpconfig.c b/nuttx/tools/cmpconfig.c index 08b7dab3f..a5a539401 100644 --- a/nuttx/tools/cmpconfig.c +++ b/nuttx/tools/cmpconfig.c @@ -67,6 +67,7 @@ static void compare_variables(struct variable_s *list1, struct variable_s *list2 { char *varval1; char *varval2; + int result; while (list1 || list2) { @@ -102,7 +103,7 @@ static void compare_variables(struct variable_s *list1, struct variable_s *list2 } else { - int result = strcmp(list1->var, list2->var); + result = strcmp(list1->var, list2->var); if (result < 0) { printf("file1: %s=%s\n", list1->var, varval1); @@ -115,9 +116,9 @@ static void compare_variables(struct variable_s *list1, struct variable_s *list2 printf("file2: %s=%s\n\n", list2->var, varval2); list2 = list2->flink; } - else + else /* if (result == 0) */ { - int result = strcmp(varval1, varval2); + result = strcmp(varval1, varval2); if (result != 0) { printf("file1: %s=%s\n", list1->var, varval1); diff --git a/nuttx/tools/configure.bat b/nuttx/tools/configure.bat index c28558fbb..7dc9ca116 100644 --- a/nuttx/tools/configure.bat +++ b/nuttx/tools/configure.bat @@ -93,7 +93,6 @@ configure.exe %debug% %fmt% %appdir% %config% if errorlevel 1 echo configure.exe failed goto End - :NoConfig echo Missing ^/^ argument diff --git a/nuttx/tools/mksyscall.c b/nuttx/tools/mksyscall.c index a75e82d28..1d172a2a1 100644 --- a/nuttx/tools/mksyscall.c +++ b/nuttx/tools/mksyscall.c @@ -61,11 +61,11 @@ static FILE *g_stubstream; * Private Functions ****************************************************************************/ -static bool is_vararg(const char *type, int index, int nparms) +static bool is_vararg(const char *type, int ndx, int nparms) { if (strcmp(type,"...") == 0) { - if (index != (nparms-1)) + if (ndx != (nparms-1)) { fprintf(stderr, "%d: ... is not the last in the argument list\n", g_lineno); exit(11); @@ -75,8 +75,10 @@ static bool is_vararg(const char *type, int index, int nparms) fprintf(stderr, "%d: Need one parameter before ...\n", g_lineno); exit(14); } + return true; } + return false; } -- cgit v1.2.3 From 362d3bb5d2257092e30c5ff9c27cd713403a87df Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 5 Jan 2013 16:07:37 +0000 Subject: Extend tools/configure.c for better compatibility with configure.sh git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5481 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 + nuttx/libc/string/lib_strndup.c | 11 +-- nuttx/tools/configure.c | 199 +++++++++++++++++++++++++++++++++------- 3 files changed, 173 insertions(+), 39 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index cce091587..b27800419 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3873,3 +3873,5 @@ to build it first. * arch/arm/src/lpc17xx/lpc17_syscon.h: Correct some typos in bit definitions (from Rommel Marcelo). + * libc/string/lib_strndup.c: strndup() should use strnlen(), not + strlen(), to determine the size of the string. diff --git a/nuttx/libc/string/lib_strndup.c b/nuttx/libc/string/lib_strndup.c index 524e09754..5a78e2dcf 100644 --- a/nuttx/libc/string/lib_strndup.c +++ b/nuttx/libc/string/lib_strndup.c @@ -1,7 +1,7 @@ /************************************************************************ * libc/string//lib_strndup.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -68,13 +68,9 @@ FAR char *strndup(FAR const char *s, size_t size) FAR char *news = NULL; if (s) { - /* Get the size of the new string = MIN(strlen(s), size) */ + /* Get the size of the new string (limited to size) */ - size_t allocsize = strlen(s); - if (allocsize > size) - { - allocsize = size; - } + size_t allocsize = strnlen(s, size); /* Allocate the new string, adding 1 for the NUL terminator */ @@ -89,5 +85,6 @@ FAR char *strndup(FAR const char *s, size_t size) news[allocsize] = '\0'; } } + return news; } diff --git a/nuttx/tools/configure.c b/nuttx/tools/configure.c index eb8268f19..9e82c3657 100644 --- a/nuttx/tools/configure.c +++ b/nuttx/tools/configure.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include @@ -76,7 +77,8 @@ static char *g_configdir = NULL; /* Name of configuration subdirector static char *g_topdir = NULL; /* Full path to top-level NuttX build directory */ static char *g_apppath = NULL; /* Full path to the applicatino directory */ -static char *g_configpath = NULL; /* Full path to the configuration directory */ +static char *g_configtop = NULL; /* Full path to the top-level configuration directory */ +static char *g_configpath = NULL; /* Full path to the configuration sub-directory */ static char *g_verstring = "0.0"; /* Version String */ static char *g_srcdefconfig = NULL; /* Source defconfig file */ @@ -100,13 +102,13 @@ static struct variable_s *g_versionvars = NULL; static void show_usage(const char *progname, int exitcode) { - fprintf(stderr, "\nUSAGE: %s [-d] [-w] [-l] [-h] [-a ] %c\n", progname, g_delim); + fprintf(stderr, "\nUSAGE: %s [-d] [-w] [-l] [-h] [-a ] [%c]\n", progname, g_delim); fprintf(stderr, "\nWhere:\n"); fprintf(stderr, " :\n"); fprintf(stderr, " Identifies the board. This must correspond to a board directory\n"); fprintf(stderr, " under nuttx%cconfigs%c.\n", g_delim, g_delim); fprintf(stderr, " :\n"); - fprintf(stderr, " Identifies the specific configuratin for the selected .\n"); + fprintf(stderr, " Identifies the specific configuration for the selected .\n"); fprintf(stderr, " This must correspond to a sub-directory under the board directory at\n"); fprintf(stderr, " under nuttx%cconfigs%c%c.\n", g_delim, g_delim, g_delim); fprintf(stderr, " <-d>:\n"); @@ -263,8 +265,19 @@ static bool verify_optiondir(const char *directory) { /* It may be okay if the dirctory does not exist */ - debug("verify_optiondir: stat of %s failed: %s\n", directory, strerror(errno)); - return false; + /* It may be okay if the file does not exist */ + + int errcode = errno; + if (errcode == ENOENT) + { + debug("verify_optiondir: stat of %s failed: %s\n", directory, strerror(errno)); + return false; + } + else + { + fprintf(stderr, "ERROR: stat of %s failed: %s\n", directory, strerror(errno)); + exit(EXIT_FAILURE); + } } if (!S_ISDIR(buf.st_mode)) @@ -276,24 +289,7 @@ static bool verify_optiondir(const char *directory) return true; } -static void verify_file(const char *path) -{ - struct stat buf; - - if (stat(path, &buf) < 0) - { - fprintf(stderr, "ERROR: stat of %s failed: %s\n", path, strerror(errno)); - exit(EXIT_FAILURE); - } - - if (!S_ISREG(buf.st_mode)) - { - fprintf(stderr, "ERROR: %s exists but is not a regular file\n", path); - exit(EXIT_FAILURE); - } -} - -static bool verify_optionfile(const char *path) +static bool verify_file(const char *path) { struct stat buf; @@ -301,8 +297,17 @@ static bool verify_optionfile(const char *path) { /* It may be okay if the file does not exist */ - debug("verify_optionfile: stat of %s failed: %s\n", path, strerror(errno)); - return false; + int errcode = errno; + if (errcode == ENOENT) + { + debug("verify_file: stat of %s failed: %s\n", path, strerror(errno)); + return false; + } + else + { + fprintf(stderr, "ERROR: stat of %s failed: %s\n", path, strerror(errno)); + exit(EXIT_FAILURE); + } } if (!S_ISREG(buf.st_mode)) @@ -329,15 +334,124 @@ static void get_topdir(void) verify_directory(g_topdir); } +static void config_search(const char *boarddir) +{ + DIR *dir; + struct dirent *dp; + struct stat buf; + char *parent; + char *child; + + /* Skip over any leading '/' or '\\'. This happens on the first second + * call because the starting boarddir is "" + */ + + if (boarddir[0] == g_delim) + { + boarddir++; + } + + /* Get the full directory path and open it */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%c%s", g_configtop, g_delim, boarddir); + dir = opendir(g_buffer); + if (!dir) + { + fprintf(stderr, "ERROR: Could not open %s: %s\n", + g_buffer, strerror(errno)); + return; + } + + /* Make a copy of the path to the directory */ + + parent = strdup(g_buffer); + + /* Vist each entry in the directory */ + + while ((dp = readdir (dir)) != NULL) + { + /* Ignore directory entries that start with '.' */ + + if (dp->d_name[0] == '.') + { + continue; + } + + /* Get a properly terminated copy of d_name (if d_name is long it may + * not include a NUL terminator.\ */ + + child = strndup(dp->d_name, NAME_MAX); + + /* Get the full path to d_name and stat the file/directory */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%c%s", parent, g_delim, child); + if (stat(g_buffer, &buf) < 0) + { + fprintf(stderr, "ERROR: stat of %s failed: %s\n", + g_buffer, strerror(errno)); + free(child); + continue; + } + + /* If it is a directory, the recurse */ + + if (S_ISDIR(buf.st_mode)) + { + char *tmppath; + snprintf(g_buffer, BUFFER_SIZE, "%s%c%s", boarddir, g_delim, child); + tmppath = strdup(g_buffer); + config_search(tmppath); + free(tmppath); + } + + /* If it is a regular file named 'defconfig' then we have found a + * configuration directory. We could terminate the serach in this case + * because we do not expect sub-directories within configuration + * directories. + */ + + else if (S_ISREG(buf.st_mode) && strcmp("defconfig", child) == 0) + { + fprintf(stderr, " %s\n", boarddir); + } + + free(child); + } + + free(parent); + closedir(dir); +} + +static void enumerate_configs(void) +{ + fprintf(stderr, "Options for [%c] include:\n\n", g_delim); + config_search(""); +} + static void check_configdir(void) { + /* Get the path to the top level configuration directory */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%cconfigs", g_topdir, g_delim); + debug("check_configdir: Checking configtop=%s\n", g_buffer); + + verify_directory(g_buffer); + g_configtop = strdup(g_buffer); + /* Get and verify the path to the selected configuration */ snprintf(g_buffer, BUFFER_SIZE, "%s%cconfigs%c%s%c%s", g_topdir, g_delim, g_delim, g_boarddir, g_delim, g_configdir); + debug("check_configdir: Checking configpath=%s\n", g_buffer); + + if (!verify_optiondir(g_buffer)) + { + fprintf(stderr, "ERROR: No configuration at %s\n", g_buffer); + enumerate_configs(); + exit(EXIT_FAILURE); + } + g_configpath = strdup(g_buffer); - debug("check_configdir: Checking configpath=%s\n", g_configpath); - verify_directory(g_configpath); } static void read_configfile(void) @@ -507,12 +621,26 @@ static void check_configuration(void) snprintf(g_buffer, BUFFER_SIZE, "%s%cdefconfig", g_configpath, g_delim); debug("check_configuration: Checking %s\n", g_buffer); - verify_file(g_buffer); + if (!verify_file(g_buffer)) + { + fprintf(stderr, "ERROR: No configuration in %s\n", g_configpath); + fprintf(stderr, " No defconfig file found.\n"); + enumerate_configs(); + exit(EXIT_FAILURE); + } + g_srcdefconfig = strdup(g_buffer); snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_configpath, g_delim); debug("check_configuration: Checking %s\n", g_buffer); - verify_file(g_buffer); + if (!verify_file(g_buffer)) + { + fprintf(stderr, "ERROR: Configuration corrupted in %s\n", g_configpath); + fprintf(stderr, " No Make.defs file found.\n"); + enumerate_configs(); + exit(EXIT_FAILURE); + } + g_srcmakedefs = strdup(g_buffer); /* Windows native configurations may provide setenv.bat; POSIX @@ -523,7 +651,7 @@ static void check_configuration(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.bat", g_configpath, g_delim); debug("check_configuration: Checking %s\n", g_buffer); - if (verify_optionfile(g_buffer)) + if (verify_file(g_buffer)) { g_srcsetenvbat = strdup(g_buffer); } @@ -532,7 +660,7 @@ static void check_configuration(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%csetenv.sh", g_configpath, g_delim); debug("check_configuration: Checking %s\n", g_buffer); - if (verify_optionfile(g_buffer)) + if (verify_file(g_buffer)) { g_srcsetenvsh = strdup(g_buffer); } @@ -544,7 +672,14 @@ static void check_configuration(void) { snprintf(g_buffer, BUFFER_SIZE, "%s%cappconfig", g_configpath, g_delim); debug("check_configuration: Checking %s\n", g_buffer); - verify_file(g_buffer); + if (!verify_file(g_buffer)) + { + fprintf(stderr, "ERROR: Configuration corrupted in %s\n", g_configpath); + fprintf(stderr, " Required appconfig file not found.\n"); + enumerate_configs(); + exit(EXIT_FAILURE); + } + g_srcappconfig = strdup(g_buffer); } } -- cgit v1.2.3 From 0d86268de677a844efa345638650dcaa6bf12764 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 6 Jan 2013 17:00:08 +0000 Subject: Remove CONFIG_BUILTIN_APPS_START git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5482 42af7a65-404d-4744-a932-0658087f49c3 --- apps/README.txt | 15 --------------- nuttx/ChangeLog | 5 +++++ nuttx/Documentation/NuttShell.html | 25 +++---------------------- nuttx/sched/os_bringup.c | 22 ++-------------------- 4 files changed, 10 insertions(+), 57 deletions(-) diff --git a/apps/README.txt b/apps/README.txt index 328126905..4a336abdb 100644 --- a/apps/README.txt +++ b/apps/README.txt @@ -141,21 +141,6 @@ This will select the apps/examples/hello in the following way: Thus accomplishing the same thing with no apps/.config file. -Built-In Start-Up main() function ------------------------------- -A builtin application can even be used as the main, start-up entry point -into your embedded software. When the user defines this option in -the NuttX configuration file: - - CONFIG_BUILTIN_APP_START= - -that application shall be invoked immediately after system starts -*instead* of the default "user_start" entry point. -Note that must be provided as: "hello", -will call: - - int hello_main(int argc, char *argv[]) - Example Built-In Application ---------------------------- An example application skeleton can be found under the examples/hello diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index b27800419..f4f697563 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3875,3 +3875,8 @@ definitions (from Rommel Marcelo). * libc/string/lib_strndup.c: strndup() should use strnlen(), not strlen(), to determine the size of the string. + * sched/os_bringup.c: Remove support for CONFIG_BUILTIN_APP_START. + This is not really a useful feature and creates a violation of the + OS layered architecture. + + diff --git a/nuttx/Documentation/NuttShell.html b/nuttx/Documentation/NuttShell.html index 7ad96da79..95a75b22c 100644 --- a/nuttx/Documentation/NuttShell.html +++ b/nuttx/Documentation/NuttShell.html @@ -3421,29 +3421,10 @@ context:

            Other Uses of Built-In Application. The primary purpose of builtin applications is to support command line execution of applications from NSH. - However, there are two other uses of builtin applications that should be mentioned. + However, there is one other use of builtin applications that should be mentioned.

              -
            1. -

              - Built-In Application Start-Up main() function. - A builtin application can even be used as the main, start-up entry point into your embedded software. - When the user defines this option in the NuttX configuration file: -

              -
                -CONFIG_BUILTIN_APP_START=<application name>
-
              -

              - that application will be invoked immediately after system starts instead of the default CONFIG_USER_ENTRYPOINT() entry point. - Note that <application name> must be provided just as it would have been on the NSH command line. - For example, hello would result in hello_main() being started at power-up. -

              -

              - This option might be useful in some develop environments where you use NSH only during the debug phase, but want to eliminate NSH in the final product. - Setting CONFIG_BUILTIN_APP_START in this way will bypass NSH and execute your application just as if it were entered from the NSH command line. -

              -

            2. binfs. binfs is a tiny file system located at apps/builtin/binfs.c. @@ -3452,7 +3433,8 @@ CONFIG_BUILTIN_APP_START=<application name> binfs will create a tiny pseudo-file system mounted at /bin. Using binfs, you can see the available builtin applications by listing the contents of /bin directory. This gives some superficial Unix compatibility, but does not really add any new functionality. -

              +

              +

            4.3.2 Synchronous Built-In Applications

            @@ -3770,7 +3752,6 @@ mount -t vfat /dev/ram1 /tmp
          • Command summaries
          • Command table
          • Conditional command execution
            • -
          • CONFIG_BUILTIN_APP_START
          • CONFIG_DISABLE_MOUNTPOINT
          • CONFIG_FS_ROMFS
          • CONFIG_NFILE_DESCRIPTORS
            • diff --git a/nuttx/sched/os_bringup.c b/nuttx/sched/os_bringup.c index 4b5adcae1..610d8515a 100644 --- a/nuttx/sched/os_bringup.c +++ b/nuttx/sched/os_bringup.c @@ -57,9 +57,6 @@ #ifdef CONFIG_SCHED_WORKQUEUE # include "work_internal.h" #endif -#ifdef CONFIG_BUILTIN_APP_START -# include "apps/apps.h" -#endif #ifdef CONFIG_NUTTX_KERNEL # include "arch/board/user_map.h" #endif @@ -112,22 +109,15 @@ * function is to serve as the "bottom half" of device * drivers. * - * And the main application entry point. This may be one of two different + * And the main application entry point: * symbols: * - * - USER_ENTRYPOINT: This is the default entry point used for all of the - * example code in apps/examples. - * - CONFIG_BUILTIN_APP_START: The system can also be configured to start - * custom applications at however CONFIG_BUILTIN_APP_START - * is defined in the NuttX start-up file. + * - USER_ENTRYPOINT: This is the default user application entry point. * ****************************************************************************/ int os_bringup(void) { -#ifdef CONFIG_BUILTIN_APP_START - static const char *argv[3] = {NULL, "init", NULL}; -#endif int init_taskid; /* Setup up the initial environment for the idle task. At present, this @@ -188,19 +178,11 @@ int os_bringup(void) svdbg("Starting init thread\n"); -#ifdef CONFIG_BUILTIN_APP_START - /* Start the built-in application, passing an "init" argument, so that - * application can distinguish different run-levels - */ - - init_taskid = exec_builtin(CONFIG_BUILTIN_APP_START, argv); -#else /* Start the default application at CONFIG_USER_ENTRYPOINT() */ init_taskid = TASK_CREATE("init", SCHED_PRIORITY_DEFAULT, CONFIG_USERMAIN_STACKSIZE, (main_t)CONFIG_USER_ENTRYPOINT, (const char **)NULL); -#endif ASSERT(init_taskid != ERROR); /* We an save a few bytes by discarding the IDLE thread's environment. */ -- cgit v1.2.3 From fe4b34bdedf8004ce14843f9d3dd16bff1d8693a Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 6 Jan 2013 17:34:03 +0000 Subject: Fix SEM_INITIALIZER git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5483 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/include/semaphore.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/nuttx/include/semaphore.h b/nuttx/include/semaphore.h index 257a5826f..203118bd6 100644 --- a/nuttx/include/semaphore.h +++ b/nuttx/include/semaphore.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/semaphore.h * - * Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -103,9 +103,13 @@ typedef struct sem_s sem_t; /* Initializers */ #ifdef CONFIG_PRIORITY_INHERITANCE -# define SEM_INITIALIZER(c) {(c), SEMHOLDER_INITIALIZER} +# if CONFIG_SEM_PREALLOCHOLDERS > 0 +# define SEM_INITIALIZER(c) {(c), NULL} /* semcount, hhead */ +# else +# define SEM_INITIALIZER(c) {(c), SEMHOLDER_INITIALIZER} /* semcount, holder */ +# endif #else -# define SEM_INITIALIZER(c) {(c)} +# define SEM_INITIALIZER(c) {(c)} /* semcount */ #endif /**************************************************************************** -- cgit v1.2.3 From f6c0ca1513bf82552a6d5fab92eedceee96515c0 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 6 Jan 2013 19:29:01 +0000 Subject: Update kconfig-frontends to 3.7.0 git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5484 42af7a65-404d-4744-a932-0658087f49c3 --- misc/tools/kconfig-frontends/configure | 22 +-- misc/tools/kconfig-frontends/configure.ac | 1 + misc/tools/kconfig-frontends/frontends/conf/conf.c | 25 +-- .../kconfig-frontends/frontends/mconf/mconf.c | 123 +++++++++++---- .../kconfig-frontends/frontends/nconf/nconf.c | 2 +- .../tools/kconfig-frontends/libs/lxdialog/dialog.h | 9 +- .../kconfig-frontends/libs/lxdialog/textbox.c | 171 +++++++++++---------- misc/tools/kconfig-frontends/libs/lxdialog/util.c | 7 + .../kconfig-frontends/libs/parser/Makefile.am | 2 +- .../kconfig-frontends/libs/parser/Makefile.in | 2 +- misc/tools/kconfig-frontends/libs/parser/expr.h | 10 ++ misc/tools/kconfig-frontends/libs/parser/list.h | 91 +++++++++++ .../kconfig-frontends/libs/parser/lkc_proto.h | 6 +- misc/tools/kconfig-frontends/libs/parser/menu.c | 55 +++++-- misc/tools/kconfig-frontends/scripts/ksync.list | 1 + misc/tools/kconfig-frontends/scripts/version.sh | 2 +- 16 files changed, 388 insertions(+), 141 deletions(-) create mode 100644 misc/tools/kconfig-frontends/libs/parser/list.h diff --git a/misc/tools/kconfig-frontends/configure b/misc/tools/kconfig-frontends/configure index ad26f3f9d..069ec071f 100755 --- a/misc/tools/kconfig-frontends/configure +++ b/misc/tools/kconfig-frontends/configure @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.67 for kconfig-frontends 3.6.0-0. +# Generated by GNU Autoconf 2.67 for kconfig-frontends 3.7.0.0. # # Report bugs to . # @@ -701,8 +701,8 @@ MAKEFLAGS= # Identity of this package. PACKAGE_NAME='kconfig-frontends' PACKAGE_TARNAME='kconfig-frontends' -PACKAGE_VERSION='3.6.0-0' -PACKAGE_STRING='kconfig-frontends 3.6.0-0' +PACKAGE_VERSION='3.7.0.0' +PACKAGE_STRING='kconfig-frontends 3.7.0.0' PACKAGE_BUGREPORT='yann.morin.1998@free.fr' PACKAGE_URL='' @@ -1516,7 +1516,7 @@ if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures kconfig-frontends 3.6.0-0 to adapt to many kinds of systems. +\`configure' configures kconfig-frontends 3.7.0.0 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1587,7 +1587,7 @@ fi if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of kconfig-frontends 3.6.0-0:";; + short | recursive ) echo "Configuration of kconfig-frontends 3.7.0.0:";; esac cat <<\_ACEOF @@ -1735,7 +1735,7 @@ fi test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -kconfig-frontends configure 3.6.0-0 +kconfig-frontends configure 3.7.0.0 generated by GNU Autoconf 2.67 Copyright (C) 2010 Free Software Foundation, Inc. @@ -2325,7 +2325,7 @@ cat >config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by kconfig-frontends $as_me 3.6.0-0, which was +It was created by kconfig-frontends $as_me 3.7.0.0, which was generated by GNU Autoconf 2.67. Invocation command line was $ $0 $@ @@ -3157,7 +3157,7 @@ fi # Define the identity of the package. PACKAGE='kconfig-frontends' - VERSION='3.6.0-0' + VERSION='3.7.0.0' cat >>confdefs.h <<_ACEOF @@ -17335,7 +17335,7 @@ fi #---------------------------------------- # Get the version to apply to the parser shared library -KCONFIGPARSER_LIB_VERSION=3.6.0 +KCONFIGPARSER_LIB_VERSION=3.7.0 #---------------------------------------- @@ -17912,7 +17912,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by kconfig-frontends $as_me 3.6.0-0, which was +This file was extended by kconfig-frontends $as_me 3.7.0.0, which was generated by GNU Autoconf 2.67. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -17978,7 +17978,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ -kconfig-frontends config.status 3.6.0-0 +kconfig-frontends config.status 3.7.0.0 configured by $0, generated by GNU Autoconf 2.67, with options \\"\$ac_cs_config\\" diff --git a/misc/tools/kconfig-frontends/configure.ac b/misc/tools/kconfig-frontends/configure.ac index 895cd58cf..6ecf47b4f 100644 --- a/misc/tools/kconfig-frontends/configure.ac +++ b/misc/tools/kconfig-frontends/configure.ac @@ -43,6 +43,7 @@ AC_SUBST([SILENT_MAKEFLAGS]) #---------------------------------------- # Prepare libtool +m4_ifdef([AM_PROG_AR], [AM_PROG_AR]) dnl Automake, we have a problem... LT_PREREQ([2.2.6]) LT_INIT([disable-static]) diff --git a/misc/tools/kconfig-frontends/frontends/conf/conf.c b/misc/tools/kconfig-frontends/frontends/conf/conf.c index 0dc4a2c77..4da3b4adf 100644 --- a/misc/tools/kconfig-frontends/frontends/conf/conf.c +++ b/misc/tools/kconfig-frontends/frontends/conf/conf.c @@ -32,7 +32,7 @@ enum input_mode { defconfig, savedefconfig, listnewconfig, - oldnoconfig, + olddefconfig, } input_mode = oldaskconfig; static int indent = 1; @@ -365,7 +365,7 @@ static void conf(struct menu *menu) case P_MENU: if ((input_mode == silentoldconfig || input_mode == listnewconfig || - input_mode == oldnoconfig) && + input_mode == olddefconfig) && rootEntry != menu) { check_conf(menu); return; @@ -429,7 +429,7 @@ static void check_conf(struct menu *menu) if (sym->name && !sym_is_choice_value(sym)) { printf("%s%s\n", CONFIG_, sym->name); } - } else if (input_mode != oldnoconfig) { + } else if (input_mode != olddefconfig) { if (!conf_cnt++) printf(_("*\n* Restart config...\n*\n")); rootEntry = menu_get_parent_menu(menu); @@ -454,7 +454,13 @@ static struct option long_opts[] = { {"alldefconfig", no_argument, NULL, alldefconfig}, {"randconfig", no_argument, NULL, randconfig}, {"listnewconfig", no_argument, NULL, listnewconfig}, - {"oldnoconfig", no_argument, NULL, oldnoconfig}, + {"olddefconfig", no_argument, NULL, olddefconfig}, + /* + * oldnoconfig is an alias of olddefconfig, because people already + * are dependent on its behavior(sets new symbols to their default + * value but not 'n') with the counter-intuitive name. + */ + {"oldnoconfig", no_argument, NULL, olddefconfig}, {NULL, 0, NULL, 0} }; @@ -467,7 +473,8 @@ static void conf_usage(const char *progname) printf(" --oldaskconfig Start a new configuration using a line-oriented program\n"); printf(" --oldconfig Update a configuration using a provided .config as base\n"); printf(" --silentoldconfig Same as oldconfig, but quietly, additionally update deps\n"); - printf(" --oldnoconfig Same as silentoldconfig but set new symbols to no\n"); + printf(" --olddefconfig Same as silentoldconfig but sets new symbols to their default value\n"); + printf(" --oldnoconfig An alias of olddefconfig\n"); printf(" --defconfig New config with default defined in \n"); printf(" --savedefconfig Save the minimal current configuration to \n"); printf(" --allnoconfig New config where all options are answered with no\n"); @@ -520,7 +527,7 @@ int main(int ac, char **av) case allmodconfig: case alldefconfig: case listnewconfig: - case oldnoconfig: + case olddefconfig: break; case '?': conf_usage(progname); @@ -565,7 +572,7 @@ int main(int ac, char **av) case oldaskconfig: case oldconfig: case listnewconfig: - case oldnoconfig: + case olddefconfig: conf_read(NULL); break; case allnoconfig: @@ -645,7 +652,7 @@ int main(int ac, char **av) /* fall through */ case oldconfig: case listnewconfig: - case oldnoconfig: + case olddefconfig: case silentoldconfig: /* Update until a loop caused no more changes */ do { @@ -653,7 +660,7 @@ int main(int ac, char **av) check_conf(&rootmenu); } while (conf_cnt && (input_mode != listnewconfig && - input_mode != oldnoconfig)); + input_mode != olddefconfig)); break; } diff --git a/misc/tools/kconfig-frontends/frontends/mconf/mconf.c b/misc/tools/kconfig-frontends/frontends/mconf/mconf.c index f584a281b..53975cf87 100644 --- a/misc/tools/kconfig-frontends/frontends/mconf/mconf.c +++ b/misc/tools/kconfig-frontends/frontends/mconf/mconf.c @@ -236,16 +236,19 @@ search_help[] = N_( "Result:\n" "-----------------------------------------------------------------\n" "Symbol: FOO [=m]\n" + "Type : tristate\n" "Prompt: Foo bus is used to drive the bar HW\n" - "Defined at drivers/pci/Kconfig:47\n" - "Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" - "Location:\n" - " -> Bus options (PCI, PCMCIA, EISA, ISA)\n" - " -> PCI support (PCI [=y])\n" - " -> PCI access mode ( [=y])\n" - "Selects: LIBCRC32\n" - "Selected by: BAR\n" + " Defined at drivers/pci/Kconfig:47\n" + " Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n" + " Location:\n" + " -> Bus options (PCI, PCMCIA, EISA, ISA)\n" + " -> PCI support (PCI [=y])\n" + "(1) -> PCI access mode ( [=y])\n" + " Selects: LIBCRC32\n" + " Selected by: BAR\n" "-----------------------------------------------------------------\n" + "o The line 'Type:' shows the type of the configuration option for\n" + " this symbol (boolean, tristate, string, ...)\n" "o The line 'Prompt:' shows the text used in the menu structure for\n" " this symbol\n" "o The 'Defined at' line tell at what file / line number the symbol\n" @@ -254,8 +257,12 @@ search_help[] = N_( " this symbol to be visible in the menu (selectable)\n" "o The 'Location:' lines tell where in the menu structure this symbol\n" " is located\n" - " A location followed by a [=y] indicate that this is a selectable\n" - " menu item - and current value is displayed inside brackets.\n" + " A location followed by a [=y] indicates that this is a\n" + " selectable menu item - and the current value is displayed inside\n" + " brackets.\n" + " Press the key in the (#) prefix to jump directly to that\n" + " location. You will be returned to the current search results\n" + " after exiting this new menu.\n" "o The 'Selects:' line tell what symbol will be automatically\n" " selected if this symbol is selected (y or m)\n" "o The 'Selected by' line tell what symbol has selected this symbol\n" @@ -273,13 +280,15 @@ static struct menu *current_menu; static int child_count; static int single_menu_mode; static int show_all_options; -static int saved_x, saved_y; -static void conf(struct menu *menu); +static void conf(struct menu *menu, struct menu *active_menu); static void conf_choice(struct menu *menu); static void conf_string(struct menu *menu); static void conf_load(void); static void conf_save(void); +static int show_textbox_ext(const char *title, char *text, int r, int c, + int *keys, int *vscroll, int *hscroll, + update_text_fn update_text, void *data); static void show_textbox(const char *title, const char *text, int r, int c); static void show_helptext(const char *title, const char *text); static void show_help(struct menu *menu); @@ -302,12 +311,47 @@ static void set_config_filename(const char *config_filename) } +struct search_data { + struct list_head *head; + struct menu **targets; + int *keys; +}; + +static void update_text(char *buf, size_t start, size_t end, void *_data) +{ + struct search_data *data = _data; + struct jump_key *pos; + int k = 0; + + list_for_each_entry(pos, data->head, entries) { + if (pos->offset >= start && pos->offset < end) { + char header[4]; + + if (k < JUMP_NB) { + int key = '0' + (pos->index % JUMP_NB) + 1; + + sprintf(header, "(%c)", key); + data->keys[k] = key; + data->targets[k] = pos->target; + k++; + } else { + sprintf(header, " "); + } + + memcpy(buf + pos->offset, header, sizeof(header) - 1); + } + } + data->keys[k] = 0; +} + static void search_conf(void) { struct symbol **sym_arr; struct gstr res; char *dialog_input; - int dres; + int dres, vscroll = 0, hscroll = 0; + bool again; + again: dialog_clear(); dres = dialog_inputbox(_("Search Configuration Parameter"), @@ -330,10 +374,30 @@ again: dialog_input += strlen(CONFIG_); sym_arr = sym_re_search(dialog_input); - res = get_relations_str(sym_arr); + do { + LIST_HEAD(head); + struct menu *targets[JUMP_NB]; + int keys[JUMP_NB + 1], i; + struct search_data data = { + .head = &head, + .targets = targets, + .keys = keys, + }; + + res = get_relations_str(sym_arr, &head); + dres = show_textbox_ext(_("Search Results"), (char *) + str_get(&res), 0, 0, keys, &vscroll, + &hscroll, &update_text, (void *) + &data); + again = false; + for (i = 0; i < JUMP_NB && keys[i]; i++) + if (dres == keys[i]) { + conf(targets[i]->parent, targets[i]); + again = true; + } + str_free(&res); + } while (again); free(sym_arr); - show_textbox(_("Search Results"), str_get(&res), 0, 0); - str_free(&res); } static void build_conf(struct menu *menu) @@ -514,12 +578,11 @@ conf_childs: indent -= doint; } -static void conf(struct menu *menu) +static void conf(struct menu *menu, struct menu *active_menu) { struct menu *submenu; const char *prompt = menu_get_prompt(menu); struct symbol *sym; - struct menu *active_menu = NULL; int res; int s_scroll = 0; @@ -562,13 +625,13 @@ static void conf(struct menu *menu) if (single_menu_mode) submenu->data = (void *) (long) !submenu->data; else - conf(submenu); + conf(submenu, NULL); break; case 't': if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes) conf_choice(submenu); else if (submenu->prompt->type == P_MENU) - conf(submenu); + conf(submenu, NULL); break; case 's': conf_string(submenu); @@ -607,7 +670,7 @@ static void conf(struct menu *menu) if (item_is_tag('t')) sym_toggle_tristate_value(sym); else if (item_is_tag('m')) - conf(submenu); + conf(submenu, NULL); break; case 7: search_conf(); @@ -619,10 +682,19 @@ static void conf(struct menu *menu) } } -static void show_textbox(const char *title, const char *text, int r, int c) +static int show_textbox_ext(const char *title, char *text, int r, int c, int + *keys, int *vscroll, int *hscroll, update_text_fn + update_text, void *data) { dialog_clear(); - dialog_textbox(title, text, r, c); + return dialog_textbox(title, text, r, c, keys, vscroll, hscroll, + update_text, data); +} + +static void show_textbox(const char *title, const char *text, int r, int c) +{ + show_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL, + NULL, NULL); } static void show_helptext(const char *title, const char *text) @@ -862,9 +934,6 @@ int main(int ac, char **av) single_menu_mode = 1; } - initscr(); - - getyx(stdscr, saved_y, saved_x); if (init_dialog(NULL)) { fprintf(stderr, N_("Your display is too small to run Menuconfig!\n")); fprintf(stderr, N_("It must be at least 19 lines by 80 columns.\n")); @@ -873,7 +942,7 @@ int main(int ac, char **av) set_config_filename(conf_get_configname()); do { - conf(&rootmenu); + conf(&rootmenu, NULL); res = handle_exit(); } while (res == KEY_ESC); diff --git a/misc/tools/kconfig-frontends/frontends/nconf/nconf.c b/misc/tools/kconfig-frontends/frontends/nconf/nconf.c index 1704a8562..87d4b15da 100644 --- a/misc/tools/kconfig-frontends/frontends/nconf/nconf.c +++ b/misc/tools/kconfig-frontends/frontends/nconf/nconf.c @@ -721,7 +721,7 @@ again: dialog_input += strlen(CONFIG_); sym_arr = sym_re_search(dialog_input); - res = get_relations_str(sym_arr); + res = get_relations_str(sym_arr, NULL); free(sym_arr); show_scroll_win(main_window, _("Search Results"), str_get(&res)); diff --git a/misc/tools/kconfig-frontends/libs/lxdialog/dialog.h b/misc/tools/kconfig-frontends/libs/lxdialog/dialog.h index b5211fce0..ee17a5264 100644 --- a/misc/tools/kconfig-frontends/libs/lxdialog/dialog.h +++ b/misc/tools/kconfig-frontends/libs/lxdialog/dialog.h @@ -144,6 +144,7 @@ struct dialog_info { */ extern struct dialog_info dlg; extern char dialog_input_result[]; +extern int saved_x, saved_y; /* Needed in signal handler in mconf.c */ /* * Function prototypes @@ -209,7 +210,13 @@ int first_alpha(const char *string, const char *exempt); int dialog_yesno(const char *title, const char *prompt, int height, int width); int dialog_msgbox(const char *title, const char *prompt, int height, int width, int pause); -int dialog_textbox(const char *title, const char *file, int height, int width); + + +typedef void (*update_text_fn)(char *buf, size_t start, size_t end, void + *_data); +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data); int dialog_menu(const char *title, const char *prompt, const void *selected, int *s_scroll); int dialog_checklist(const char *title, const char *prompt, int height, diff --git a/misc/tools/kconfig-frontends/libs/lxdialog/textbox.c b/misc/tools/kconfig-frontends/libs/lxdialog/textbox.c index 4e5de60a0..a48bb93e0 100644 --- a/misc/tools/kconfig-frontends/libs/lxdialog/textbox.c +++ b/misc/tools/kconfig-frontends/libs/lxdialog/textbox.c @@ -22,23 +22,25 @@ #include "dialog.h" static void back_lines(int n); -static void print_page(WINDOW * win, int height, int width); -static void print_line(WINDOW * win, int row, int width); +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data); +static void print_line(WINDOW *win, int row, int width); static char *get_line(void); static void print_position(WINDOW * win); static int hscroll; static int begin_reached, end_reached, page_length; -static const char *buf; -static const char *page; +static char *buf; +static char *page; /* * refresh window content */ static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw, - int cur_y, int cur_x) + int cur_y, int cur_x, update_text_fn update_text, + void *data) { - print_page(box, boxh, boxw); + print_page(box, boxh, boxw, update_text, data); print_position(dialog); wmove(dialog, cur_y, cur_x); /* Restore cursor position */ wrefresh(dialog); @@ -47,14 +49,18 @@ static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw, /* * Display text from a file in a dialog box. + * + * keys is a null-terminated array + * update_text() may not add or remove any '\n' or '\0' in tbuf */ -int dialog_textbox(const char *title, const char *tbuf, - int initial_height, int initial_width) +int dialog_textbox(const char *title, char *tbuf, int initial_height, + int initial_width, int *keys, int *_vscroll, int *_hscroll, + update_text_fn update_text, void *data) { int i, x, y, cur_x, cur_y, key = 0; int height, width, boxh, boxw; - int passed_end; WINDOW *dialog, *box; + bool done = false; begin_reached = 1; end_reached = 0; @@ -63,6 +69,15 @@ int dialog_textbox(const char *title, const char *tbuf, buf = tbuf; page = buf; /* page is pointer to start of page to be displayed */ + if (_vscroll && *_vscroll) { + begin_reached = 0; + + for (i = 0; i < *_vscroll; i++) + get_line(); + } + if (_hscroll) + hscroll = *_hscroll; + do_resize: getmaxyx(stdscr, height, width); if (height < 8 || width < 8) @@ -120,9 +135,10 @@ do_resize: /* Print first page of text */ attr_clear(box, boxh, boxw, dlg.dialog.atr); - refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text, + data); - while ((key != KEY_ESC) && (key != '\n')) { + while (!done) { key = wgetch(dialog); switch (key) { case 'E': /* Exit */ @@ -130,16 +146,17 @@ do_resize: case 'X': case 'x': case 'q': - delwin(box); - delwin(dialog); - return 0; + case '\n': + done = true; + break; case 'g': /* First page */ case KEY_HOME: if (!begin_reached) { begin_reached = 1; page = buf; refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + cur_y, cur_x, update_text, + data); } break; case 'G': /* Last page */ @@ -149,45 +166,18 @@ do_resize: /* point to last char in buf */ page = buf + strlen(buf); back_lines(boxh); - refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case 'K': /* Previous line */ case 'k': case KEY_UP: - if (!begin_reached) { - back_lines(page_length + 1); - - /* We don't call print_page() here but use - * scrolling to ensure faster screen update. - * However, 'end_reached' and 'page_length' - * should still be updated, and 'page' should - * point to start of next page. This is done - * by calling get_line() in the following - * 'for' loop. */ - scrollok(box, TRUE); - wscrl(box, -1); /* Scroll box region down one line */ - scrollok(box, FALSE); - page_length = 0; - passed_end = 0; - for (i = 0; i < boxh; i++) { - if (!i) { - /* print first line of page */ - print_line(box, 0, boxw); - wnoutrefresh(box); - } else - /* Called to update 'end_reached' and 'page' */ - get_line(); - if (!passed_end) - page_length++; - if (end_reached && !passed_end) - passed_end = 1; - } + if (begin_reached) + break; - print_position(dialog); - wmove(dialog, cur_y, cur_x); /* Restore cursor position */ - wrefresh(dialog); - } + back_lines(page_length + 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case 'B': /* Previous page */ case 'b': @@ -196,23 +186,18 @@ do_resize: if (begin_reached) break; back_lines(page_length + boxh); - refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case 'J': /* Next line */ case 'j': case KEY_DOWN: - if (!end_reached) { - begin_reached = 0; - scrollok(box, TRUE); - scroll(box); /* Scroll box region up one line */ - scrollok(box, FALSE); - print_line(box, boxh - 1, boxw); - wnoutrefresh(box); - print_position(dialog); - wmove(dialog, cur_y, cur_x); /* Restore cursor position */ - wrefresh(dialog); - } + if (end_reached) + break; + + back_lines(page_length - 1); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case KEY_NPAGE: /* Next page */ case ' ': @@ -221,8 +206,8 @@ do_resize: break; begin_reached = 0; - refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case '0': /* Beginning of line */ case 'H': /* Scroll left */ @@ -237,8 +222,8 @@ do_resize: hscroll--; /* Reprint current page to scroll horizontally */ back_lines(page_length); - refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case 'L': /* Scroll right */ case 'l': @@ -248,11 +233,12 @@ do_resize: hscroll++; /* Reprint current page to scroll horizontally */ back_lines(page_length); - refresh_text_box(dialog, box, boxh, boxw, - cur_y, cur_x); + refresh_text_box(dialog, box, boxh, boxw, cur_y, + cur_x, update_text, data); break; case KEY_ESC: - key = on_key_esc(dialog); + if (on_key_esc(dialog) == KEY_ESC) + done = true; break; case KEY_RESIZE: back_lines(height); @@ -260,11 +246,31 @@ do_resize: delwin(dialog); on_key_resize(); goto do_resize; + default: + for (i = 0; keys[i]; i++) { + if (key == keys[i]) { + done = true; + break; + } + } } } delwin(box); delwin(dialog); - return key; /* ESC pressed */ + if (_vscroll) { + const char *s; + + s = buf; + *_vscroll = 0; + back_lines(page_length); + while (s < page && (s = strchr(s, '\n'))) { + (*_vscroll)++; + s++; + } + } + if (_hscroll) + *_hscroll = hscroll; + return key; } /* @@ -301,12 +307,23 @@ static void back_lines(int n) } /* - * Print a new page of text. Called by dialog_textbox(). + * Print a new page of text. */ -static void print_page(WINDOW * win, int height, int width) +static void print_page(WINDOW *win, int height, int width, update_text_fn + update_text, void *data) { int i, passed_end = 0; + if (update_text) { + char *end; + + for (i = 0; i < height; i++) + get_line(); + end = page; + back_lines(height); + update_text(buf, page - buf, end - buf, data); + } + page_length = 0; for (i = 0; i < height; i++) { print_line(win, i, width); @@ -319,7 +336,7 @@ static void print_page(WINDOW * win, int height, int width) } /* - * Print a new line of text. Called by dialog_textbox() and print_page(). + * Print a new line of text. */ static void print_line(WINDOW * win, int row, int width) { @@ -357,10 +374,8 @@ static char *get_line(void) end_reached = 0; while (*page != '\n') { if (*page == '\0') { - if (!end_reached) { - end_reached = 1; - break; - } + end_reached = 1; + break; } else if (i < MAX_LEN) line[i++] = *(page++); else { @@ -373,7 +388,7 @@ static char *get_line(void) if (i <= MAX_LEN) line[i] = '\0'; if (!end_reached) - page++; /* move pass '\n' */ + page++; /* move past '\n' */ return line; } diff --git a/misc/tools/kconfig-frontends/libs/lxdialog/util.c b/misc/tools/kconfig-frontends/libs/lxdialog/util.c index f2375ad7e..109d53117 100644 --- a/misc/tools/kconfig-frontends/libs/lxdialog/util.c +++ b/misc/tools/kconfig-frontends/libs/lxdialog/util.c @@ -23,6 +23,9 @@ #include "dialog.h" +/* Needed in signal handler in mconf.c */ +int saved_x, saved_y; + struct dialog_info dlg; static void set_mono_theme(void) @@ -273,6 +276,10 @@ int init_dialog(const char *backtitle) int height, width; initscr(); /* Init curses */ + + /* Get current cursor position for signal handler in mconf.c */ + getyx(stdscr, saved_y, saved_x); + getmaxyx(stdscr, height, width); if (height < 19 || width < 80) { endwin(); diff --git a/misc/tools/kconfig-frontends/libs/parser/Makefile.am b/misc/tools/kconfig-frontends/libs/parser/Makefile.am index ad6e5aa8b..567b1e888 100644 --- a/misc/tools/kconfig-frontends/libs/parser/Makefile.am +++ b/misc/tools/kconfig-frontends/libs/parser/Makefile.am @@ -14,7 +14,7 @@ libkconfig_parser_la_LDFLAGS = -release $(KCONFIGPARSER_LIB_VERSION) -no-undefin libkconfig_parser_la_LIBADD = $(intl_LIBS) kconfig_includedir = $(includedir)/kconfig -kconfig_include_HEADERS = lkc.h expr.h lkc_proto.h +kconfig_include_HEADERS = list.h lkc.h expr.h lkc_proto.h BUILT_SOURCES = hconf.c lconf.c CLEANFILES = hconf.c lconf.c yconf.c diff --git a/misc/tools/kconfig-frontends/libs/parser/Makefile.in b/misc/tools/kconfig-frontends/libs/parser/Makefile.in index 97793927c..7fa4e8507 100644 --- a/misc/tools/kconfig-frontends/libs/parser/Makefile.in +++ b/misc/tools/kconfig-frontends/libs/parser/Makefile.in @@ -304,7 +304,7 @@ libkconfig_parser_la_CFLAGS = $(AM_CFLAGS) $(kf_CFLAGS) libkconfig_parser_la_LDFLAGS = -release $(KCONFIGPARSER_LIB_VERSION) -no-undefined libkconfig_parser_la_LIBADD = $(intl_LIBS) kconfig_includedir = $(includedir)/kconfig -kconfig_include_HEADERS = lkc.h expr.h lkc_proto.h +kconfig_include_HEADERS = list.h lkc.h expr.h lkc_proto.h BUILT_SOURCES = hconf.c lconf.c CLEANFILES = hconf.c lconf.c yconf.c EXTRA_DIST = yconf.y.patch diff --git a/misc/tools/kconfig-frontends/libs/parser/expr.h b/misc/tools/kconfig-frontends/libs/parser/expr.h index d4ecce8bc..cdd48600e 100644 --- a/misc/tools/kconfig-frontends/libs/parser/expr.h +++ b/misc/tools/kconfig-frontends/libs/parser/expr.h @@ -12,6 +12,7 @@ extern "C" { #include #include +#include "list.h" #ifndef __cplusplus #include #endif @@ -173,6 +174,15 @@ struct menu { #define MENU_CHANGED 0x0001 #define MENU_ROOT 0x0002 +struct jump_key { + struct list_head entries; + size_t offset; + struct menu *target; + int index; +}; + +#define JUMP_NB 9 + extern struct file *file_list; extern struct file *current_file; struct file *lookup_file(const char *name); diff --git a/misc/tools/kconfig-frontends/libs/parser/list.h b/misc/tools/kconfig-frontends/libs/parser/list.h new file mode 100644 index 000000000..0ae730be5 --- /dev/null +++ b/misc/tools/kconfig-frontends/libs/parser/list.h @@ -0,0 +1,91 @@ +#ifndef LIST_H +#define LIST_H + +/* + * Copied from include/linux/... + */ + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + + +struct list_head { + struct list_head *next, *prev; +}; + + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *_new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = _new; + _new->next = next; + _new->prev = prev; + prev->next = _new; +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *_new, struct list_head *head) +{ + __list_add(_new, head->prev, head); +} + +#endif diff --git a/misc/tools/kconfig-frontends/libs/parser/lkc_proto.h b/misc/tools/kconfig-frontends/libs/parser/lkc_proto.h index 47fe9c340..ef1a7381f 100644 --- a/misc/tools/kconfig-frontends/libs/parser/lkc_proto.h +++ b/misc/tools/kconfig-frontends/libs/parser/lkc_proto.h @@ -21,8 +21,10 @@ P(menu_get_root_menu,struct menu *,(struct menu *menu)); P(menu_get_parent_menu,struct menu *,(struct menu *menu)); P(menu_has_help,bool,(struct menu *menu)); P(menu_get_help,const char *,(struct menu *menu)); -P(get_symbol_str, void, (struct gstr *r, struct symbol *sym)); -P(get_relations_str, struct gstr, (struct symbol **sym_arr)); +P(get_symbol_str, void, (struct gstr *r, struct symbol *sym, struct list_head + *head)); +P(get_relations_str, struct gstr, (struct symbol **sym_arr, struct list_head + *head)); P(menu_get_ext_help,void,(struct menu *menu, struct gstr *help)); /* symbol.c */ diff --git a/misc/tools/kconfig-frontends/libs/parser/menu.c b/misc/tools/kconfig-frontends/libs/parser/menu.c index 8c2a97e60..e98a05c8e 100644 --- a/misc/tools/kconfig-frontends/libs/parser/menu.c +++ b/misc/tools/kconfig-frontends/libs/parser/menu.c @@ -507,10 +507,12 @@ const char *menu_get_help(struct menu *menu) return ""; } -static void get_prompt_str(struct gstr *r, struct property *prop) +static void get_prompt_str(struct gstr *r, struct property *prop, + struct list_head *head) { int i, j; - struct menu *submenu[8], *menu; + struct menu *submenu[8], *menu, *location = NULL; + struct jump_key *jump; str_printf(r, _("Prompt: %s\n"), _(prop->text)); str_printf(r, _(" Defined at %s:%d\n"), prop->menu->file->name, @@ -521,13 +523,44 @@ static void get_prompt_str(struct gstr *r, struct property *prop) str_append(r, "\n"); } menu = prop->menu->parent; - for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) + for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) { + bool accessible = menu_is_visible(menu); + submenu[i++] = menu; + if (location == NULL && accessible) + location = menu; + } + if (head && location) { + jump = malloc(sizeof(struct jump_key)); + + if (menu_is_visible(prop->menu)) { + /* + * There is not enough room to put the hint at the + * beginning of the "Prompt" line. Put the hint on the + * last "Location" line even when it would belong on + * the former. + */ + jump->target = prop->menu; + } else + jump->target = location; + + if (list_empty(head)) + jump->index = 0; + else + jump->index = list_entry(head->prev, struct jump_key, + entries)->index + 1; + + list_add_tail(&jump->entries, head); + } + if (i > 0) { str_printf(r, _(" Location:\n")); for (j = 4; --i >= 0; j += 2) { menu = submenu[i]; - str_printf(r, "%*c-> %s", j, ' ', _(menu_get_prompt(menu))); + if (head && location && menu == location) + jump->offset = r->len - 1; + str_printf(r, "%*c-> %s", j, ' ', + _(menu_get_prompt(menu))); if (menu->sym) { str_printf(r, " (%s [=%s])", menu->sym->name ? menu->sym->name : _(""), @@ -538,7 +571,11 @@ static void get_prompt_str(struct gstr *r, struct property *prop) } } -void get_symbol_str(struct gstr *r, struct symbol *sym) +/* + * head is optional and may be NULL + */ +void get_symbol_str(struct gstr *r, struct symbol *sym, + struct list_head *head) { bool hit; struct property *prop; @@ -557,7 +594,7 @@ void get_symbol_str(struct gstr *r, struct symbol *sym) } } for_all_prompts(sym, prop) - get_prompt_str(r, prop); + get_prompt_str(r, prop, head); hit = false; for_all_properties(sym, prop, P_SELECT) { if (!hit) { @@ -577,14 +614,14 @@ void get_symbol_str(struct gstr *r, struct symbol *sym) str_append(r, "\n\n"); } -struct gstr get_relations_str(struct symbol **sym_arr) +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head) { struct symbol *sym; struct gstr res = str_new(); int i; for (i = 0; sym_arr && (sym = sym_arr[i]); i++) - get_symbol_str(&res, sym); + get_symbol_str(&res, sym, head); if (!i) str_append(&res, _("No matches found.\n")); return res; @@ -603,5 +640,5 @@ void menu_get_ext_help(struct menu *menu, struct gstr *help) } str_printf(help, "%s\n", _(help_text)); if (sym) - get_symbol_str(help, sym); + get_symbol_str(help, sym, NULL); } diff --git a/misc/tools/kconfig-frontends/scripts/ksync.list b/misc/tools/kconfig-frontends/scripts/ksync.list index 9766b7a05..aa8b9b6fa 100644 --- a/misc/tools/kconfig-frontends/scripts/ksync.list +++ b/misc/tools/kconfig-frontends/scripts/ksync.list @@ -21,6 +21,7 @@ scripts/kconfig/expr.c --> libs/parser/expr.c scripts/kconfig/expr.h --> libs/parser/expr.h scripts/kconfig/zconf.gperf --> libs/parser/hconf.gperf scripts/kconfig/zconf.l --> libs/parser/lconf.l +scripts/kconfig/list.h --> libs/parser/list.h scripts/kconfig/lkc.h --> libs/parser/lkc.h scripts/kconfig/lkc_proto.h --> libs/parser/lkc_proto.h scripts/kconfig/menu.c --> libs/parser/menu.c diff --git a/misc/tools/kconfig-frontends/scripts/version.sh b/misc/tools/kconfig-frontends/scripts/version.sh index 57f699c6a..b3d0c6ebe 100755 --- a/misc/tools/kconfig-frontends/scripts/version.sh +++ b/misc/tools/kconfig-frontends/scripts/version.sh @@ -38,6 +38,6 @@ esac if [ "${plain}" -eq 1 ]; then echo "${k_ver_plain}" else - echo "${k_ver}${k_ver_extra}-${kf_ver}" + echo "${k_ver}${k_ver_extra}.${kf_ver}" fi -- cgit v1.2.3 From a4a2b830b9958cd5aff6fc13bed75f001ae79ddb Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 6 Jan 2013 19:33:10 +0000 Subject: Missed a file in the kconfig-frontends 3.7.0 update git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5485 42af7a65-404d-4744-a932-0658087f49c3 --- misc/tools/kconfig-frontends/.version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misc/tools/kconfig-frontends/.version b/misc/tools/kconfig-frontends/.version index a512a0944..585c66f03 100644 --- a/misc/tools/kconfig-frontends/.version +++ b/misc/tools/kconfig-frontends/.version @@ -1,2 +1,2 @@ -3.6.0 a0d271cbfed1dd50278c6b06bead3d00ba0a88f9 Terrified Chipmunk +3.7.0 29594404d7fe73cd80eaa4ee8c43dcc53970c60e Terrified Chipmunk 0 -- cgit v1.2.3 From 876062fe3a2b6273855b77c0ed1c9d0cbcfc43c6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 7 Jan 2013 15:20:21 +0000 Subject: Implement a simple vfork(). ARM only for now git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5486 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 3 +- nuttx/arch/arm/src/arm/up_vfork.S | 92 +++++++++++++++++++++++ nuttx/arch/arm/src/armv7-m/up_vfork.S | 96 ++++++++++++++++++++++++ nuttx/arch/arm/src/c5471/Make.defs | 6 +- nuttx/arch/arm/src/calypso/Make.defs | 6 +- nuttx/arch/arm/src/common/up__vfork.c | 134 ++++++++++++++++++++++++++++++++++ nuttx/arch/arm/src/dm320/Make.defs | 6 +- nuttx/arch/arm/src/imx/Make.defs | 6 +- nuttx/arch/arm/src/kinetis/Make.defs | 8 +- nuttx/arch/arm/src/lm3s/Make.defs | 8 +- nuttx/arch/arm/src/lpc17xx/Make.defs | 7 +- nuttx/arch/arm/src/lpc214x/Make.defs | 7 +- nuttx/arch/arm/src/lpc2378/Make.defs | 15 ++-- nuttx/arch/arm/src/lpc31xx/Make.defs | 4 +- nuttx/arch/arm/src/lpc43xx/Make.defs | 10 ++- nuttx/arch/arm/src/sam3u/Make.defs | 7 +- nuttx/arch/arm/src/stm32/Make.defs | 8 +- nuttx/arch/arm/src/str71x/Make.defs | 15 ++-- nuttx/include/unistd.h | 3 +- 19 files changed, 389 insertions(+), 52 deletions(-) create mode 100644 nuttx/arch/arm/src/arm/up_vfork.S create mode 100644 nuttx/arch/arm/src/armv7-m/up_vfork.S create mode 100644 nuttx/arch/arm/src/common/up__vfork.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index f4f697563..e2d8a586b 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3878,5 +3878,6 @@ * sched/os_bringup.c: Remove support for CONFIG_BUILTIN_APP_START. This is not really a useful feature and creates a violation of the OS layered architecture. - + * include/unistd.h, arch/arch/src/*: Implement a simple vfork(). + On initial checkin, this API is available only for ARM platforms. diff --git a/nuttx/arch/arm/src/arm/up_vfork.S b/nuttx/arch/arm/src/arm/up_vfork.S new file mode 100644 index 000000000..23e975c30 --- /dev/null +++ b/nuttx/arch/arm/src/arm/up_vfork.S @@ -0,0 +1,92 @@ +/************************************************************************************ + * arch/arm/src/arm/up_vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .file "up_vfork.S" + .globl __vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling __vfork() with the vfork() + * return address as an argument. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .globl vfork + .type vfork, function +vfork: + + /* I know, I could have used the GCC's return address builtin and done this all + * in C. But this works even if there is no builtin. + */ + + mov r0, lr + b __vfork + .size vfork, .-vfork + .end diff --git a/nuttx/arch/arm/src/armv7-m/up_vfork.S b/nuttx/arch/arm/src/armv7-m/up_vfork.S new file mode 100644 index 000000000..65ccc4535 --- /dev/null +++ b/nuttx/arch/arm/src/armv7-m/up_vfork.S @@ -0,0 +1,96 @@ +/************************************************************************************ + * arch/arm/src/armv7-m/up_vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .syntax unified + .thumb + .file "up_vfork.S" + .globl __vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling __vfork() with the vfork() + * return address as an argument. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .thumb_func + .globl vfork + .type vfork, function +vfork: + + /* I know, I could have used the GCC's return address builtin and done this all + * in C. But this works even if there is no builtin. + */ + + mov r0, lr + b __vfork + .size vfork, .-vfork + .end + diff --git a/nuttx/arch/arm/src/c5471/Make.defs b/nuttx/arch/arm/src/c5471/Make.defs index 2bc396fd3..89c3aaf0b 100644 --- a/nuttx/arch/arm/src/c5471/Make.defs +++ b/nuttx/arch/arm/src/c5471/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # c5471/Make.defs # -# Copyright (C) 2007 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,14 +35,14 @@ HEAD_ASRC = up_nommuhead.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c + up_undefinedinsn.c up_usestack.c up__vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs index 4b53c3b7c..957d4e677 100644 --- a/nuttx/arch/arm/src/calypso/Make.defs +++ b/nuttx/arch/arm/src/calypso/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # calypso/Make.defs # -# Copyright (C) 2007 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Copyright (C) 2011 Stefan Richter. All rights reserved. @@ -39,14 +39,14 @@ HEAD_ASRC = calypso_head.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ - up_nommuhead.S + up_nommuhead.S up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \ up_exit.c up_idle.c up_initialstate.c up_initialize.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c calypso_power.c + up_undefinedinsn.c up_usestack.c calypso_power.c up__vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/common/up__vfork.c b/nuttx/arch/arm/src/common/up__vfork.c new file mode 100644 index 000000000..a1081faa8 --- /dev/null +++ b/nuttx/arch/arm/src/common/up__vfork.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * arch/arm/src/common/up__vfork + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ARM requires at least a 4-byte stack alignment. For use with EABI and + * floating point, the stack must be aligned to 8-byte addresses. + */ + +#ifndef CONFIG_STACK_ALIGNMENT + +/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you + * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly! + */ + +# ifdef __ARM_EABI__ +# define CONFIG_STACK_ALIGNMENT 8 +# else +# define CONFIG_STACK_ALIGNMENT 4 +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * This thin layer starts the vfork child by simply spawning a new thread + * that begins at the return address of vfork(). + * + * Input Paremeters: + * retaddr - The return address of vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +pid_t __vfork(uint32_t retaddr) +{ + FAR _TCB *parent = (FAR _TCB *)g_readytorun.head; + size_t stacksize; + int priority; + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Get the current priority of the parent task */ + +#ifdef CONFIG_PRIORITY_INHERITANCE + priority = parent->base_priority; /* "Normal," unboosted priority */ +#else + priority = parent->sched_priority; /* Current priority */ +#endif + + /* Start the child thread at the vfork return address. TASK_CREATE will + * return the PID of the new thread. Otherwise a negative value will be + * returned and the errno will be set appropriately. + * + * When the registers are initialized, the return value in R0 should be + * cleared to zero, providing the indication to the newly started child + * thread. + */ + + return TASK_CREATE("init", priority, stacksize, (main_t)retaddr, + (const char **)NULL); +} diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs index 9087708ef..52e65c0e8 100644 --- a/nuttx/arch/arm/src/dm320/Make.defs +++ b/nuttx/arch/arm/src/dm320/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # dm320/Make.defs # -# Copyright (C) 2007, 2010 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2010, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -36,14 +36,14 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c + up_undefinedinsn.c up_usestack.c up__vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs index a1c2e72e6..a7c0ceebd 100644 --- a/nuttx/arch/arm/src/imx/Make.defs +++ b/nuttx/arch/arm/src/imx/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/imx/Make.defs # -# Copyright (C) 2009 Gregory Nutt. All rights reserved. +# Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -36,14 +36,14 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c + up_undefinedinsn.c up_usestack.c up__vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs index 65bc7b465..bad2946e2 100644 --- a/nuttx/arch/arm/src/kinetis/Make.defs +++ b/nuttx/arch/arm/src/kinetis/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/kinetis/Make.defs # -# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,14 +39,16 @@ HEAD_ASRC = kinetis_vectors.S # Common ARM and Cortex-M3 files -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_initialize.c \ up_memfault.c up_initialstate.c up_interruptcontext.c \ up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_releasepending.c up_sigdeliver.c up_unblocktask.c up_usestack.c \ - up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c + up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c \ + up__vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs index 8d2918027..c745e1953 100644 --- a/nuttx/arch/arm/src/lm3s/Make.defs +++ b/nuttx/arch/arm/src/lm3s/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/lm3s/Make.defs # -# Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,14 +35,16 @@ HEAD_ASRC = lm3s_vectors.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \ up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \ - up_usestack.c up_doirq.c up_hardfault.c up_svcall.c + up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ + up__vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs index c7ef4a147..1ea0183a1 100644 --- a/nuttx/arch/arm/src/lpc17xx/Make.defs +++ b/nuttx/arch/arm/src/lpc17xx/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/lpc17xx/Make.defs # -# Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,14 +39,15 @@ HEAD_ASRC = lpc17_vectors.S # Common ARM and Cortex-M3 files -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c \ up_initialstate.c up_interruptcontext.c up_modifyreg8.c \ up_modifyreg16.c up_modifyreg32.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \ - up_hardfault.c up_svcall.c up_checkstack.c + up_hardfault.c up_svcall.c up_checkstack.c up__vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lpc214x/Make.defs b/nuttx/arch/arm/src/lpc214x/Make.defs index ae5ed15fb..6821d512b 100644 --- a/nuttx/arch/arm/src/lpc214x/Make.defs +++ b/nuttx/arch/arm/src/lpc214x/Make.defs @@ -1,7 +1,7 @@ ############################################################################## # lpc214x/Make.defs # -# Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,13 +35,14 @@ HEAD_ASRC = lpc214x_head.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ + up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c + up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs index 4fe75d924..3d3c15926 100644 --- a/nuttx/arch/arm/src/lpc2378/Make.defs +++ b/nuttx/arch/arm/src/lpc2378/Make.defs @@ -1,7 +1,7 @@ ############################################################################## # lpc23xx/Make.defs # -# Copyright (C) 2010 Rommel Marcelo. All rights reserved. +# Copyright (C) 2010, 2013 Rommel Marcelo. All rights reserved. # Author: Rommel Marcelo # # This file is part of the NuttX RTOS and based on the lpc2148 port: @@ -40,13 +40,14 @@ HEAD_ASRC = lpc23xx_head.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ + up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ - up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ - up_exit.c up_idle.c up_initialize.c up_initialstate.c \ - up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ - up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c + up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ + up_exit.c up_idle.c up_initialize.c up_initialstate.c \ + up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ + up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ + up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/arch/arm/src/lpc31xx/Make.defs b/nuttx/arch/arm/src/lpc31xx/Make.defs index db63563ef..b3a9746b4 100644 --- a/nuttx/arch/arm/src/lpc31xx/Make.defs +++ b/nuttx/arch/arm/src/lpc31xx/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ @@ -44,7 +44,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c + up_undefinedinsn.c up_usestack.c up__vfork.c ifeq ($(CONFIG_PAGING),y) CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs index cd78ddd5b..211f9bee3 100644 --- a/nuttx/arch/arm/src/lpc43xx/Make.defs +++ b/nuttx/arch/arm/src/lpc43xx/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/lpc43xx/Make.defs # -# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -33,16 +33,18 @@ # ############################################################################ -HEAD_ASRC = +HEAD_ASRC = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c +CMN_ASRCS += up_vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c -CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c +CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up__vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs index daa129169..4682ea83d 100644 --- a/nuttx/arch/arm/src/sam3u/Make.defs +++ b/nuttx/arch/arm/src/sam3u/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/sam3u/Make.defs # -# Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,14 +39,15 @@ HEAD_ASRC = sam3u_vectors.S # Common ARM and Cortex-M3 files -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \ up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c \ up_modifyreg16.c up_modifyreg32.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \ - up_hardfault.c up_svcall.c + up_hardfault.c up_svcall.c up__vfork.c # Configuration-dependent common files diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index 1e6c0c401..89c291791 100644 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/stm32/Make.defs # -# Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,14 +39,16 @@ else HEAD_ASRC = stm32_vectors.S endif -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + up_vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \ - up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c + up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c \ + up_svcall.c up__vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs index 32eaddcdb..3612950a6 100644 --- a/nuttx/arch/arm/src/str71x/Make.defs +++ b/nuttx/arch/arm/src/str71x/Make.defs @@ -1,7 +1,7 @@ ############################################################################## # arch/arm/src/str71x/Make.defs # -# Copyright (C) 2008 Gregory Nutt. All rights reserved. +# Copyright (C) 2008, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,13 +35,14 @@ HEAD_ASRC = str71x_head.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ + up_vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ - up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ - up_exit.c up_idle.c up_initialize.c up_initialstate.c \ - up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ - up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c + up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ + up_exit.c up_idle.c up_initialize.c up_initialstate.c \ + up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ + up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ + up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h index 681ce9e63..ddb6880f4 100644 --- a/nuttx/include/unistd.h +++ b/nuttx/include/unistd.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/unistd.h * - * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -129,6 +129,7 @@ EXTERN int optopt; /* unrecognized option character */ /* Task Control Interfaces */ +EXTERN pid_t vfork(void); EXTERN pid_t getpid(void); EXTERN void _exit(int status) noreturn_function; EXTERN unsigned int sleep(unsigned int seconds); -- cgit v1.2.3 From a5f001189e1a056be275e1d736e38893f96cd395 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 7 Jan 2013 19:35:47 +0000 Subject: This initial vfork() check-in was a little pollyanna-ish git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5487 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/arm/up_vfork.S | 92 ------------ nuttx/arch/arm/src/arm/vfork.S | 134 +++++++++++++++++ nuttx/arch/arm/src/armv7-m/up_vfork.S | 96 ------------ nuttx/arch/arm/src/armv7-m/vfork.S | 138 ++++++++++++++++++ nuttx/arch/arm/src/c5471/Make.defs | 4 +- nuttx/arch/arm/src/calypso/Make.defs | 4 +- nuttx/arch/arm/src/common/up__vfork.c | 134 ----------------- nuttx/arch/arm/src/common/up_vfork.c | 196 +++++++++++++++++++++++++ nuttx/arch/arm/src/common/up_vfork.h | 82 +++++++++++ nuttx/arch/arm/src/dm320/Make.defs | 4 +- nuttx/arch/arm/src/imx/Make.defs | 4 +- nuttx/arch/arm/src/kinetis/Make.defs | 4 +- nuttx/arch/arm/src/lm3s/Make.defs | 4 +- nuttx/arch/arm/src/lpc17xx/Make.defs | 4 +- nuttx/arch/arm/src/lpc214x/Make.defs | 4 +- nuttx/arch/arm/src/lpc2378/Make.defs | 4 +- nuttx/arch/arm/src/lpc31xx/Make.defs | 4 +- nuttx/arch/arm/src/lpc43xx/Make.defs | 4 +- nuttx/arch/arm/src/sam3u/Make.defs | 4 +- nuttx/arch/arm/src/stm32/Make.defs | 4 +- nuttx/arch/arm/src/str71x/Make.defs | 4 +- nuttx/include/nuttx/arch.h | 2 +- nuttx/include/nuttx/sched.h | 26 ++++ nuttx/sched/Makefile | 2 +- nuttx/sched/sched_setuptaskfiles.c | 3 +- nuttx/sched/task_create.c | 2 + nuttx/sched/task_vfork.c | 266 ++++++++++++++++++++++++++++++++++ 27 files changed, 876 insertions(+), 353 deletions(-) delete mode 100644 nuttx/arch/arm/src/arm/up_vfork.S create mode 100644 nuttx/arch/arm/src/arm/vfork.S delete mode 100644 nuttx/arch/arm/src/armv7-m/up_vfork.S create mode 100644 nuttx/arch/arm/src/armv7-m/vfork.S delete mode 100644 nuttx/arch/arm/src/common/up__vfork.c create mode 100644 nuttx/arch/arm/src/common/up_vfork.c create mode 100644 nuttx/arch/arm/src/common/up_vfork.h create mode 100644 nuttx/sched/task_vfork.c diff --git a/nuttx/arch/arm/src/arm/up_vfork.S b/nuttx/arch/arm/src/arm/up_vfork.S deleted file mode 100644 index 23e975c30..000000000 --- a/nuttx/arch/arm/src/arm/up_vfork.S +++ /dev/null @@ -1,92 +0,0 @@ -/************************************************************************************ - * arch/arm/src/arm/up_vfork.S - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Global Symbols - ************************************************************************************/ - - .file "up_vfork.S" - .globl __vfork - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: vfork - * - * Description: - * The vfork() function has the same effect as fork(), except that the behavior is - * undefined if the process created by vfork() either modifies any data other than - * a variable of type pid_t used to store the return value from vfork(), or returns - * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. - * - * This thin layer implements vfork by simply calling __vfork() with the vfork() - * return address as an argument. - * - * Input Paremeters: - * None - * - * Return: - * Upon successful completion, vfork() returns 0 to the child process and returns - * the process ID of the child process to the parent process. Otherwise, -1 is - * returned to the parent, no child process is created, and errno is set to - * indicate the error. - * - ************************************************************************************/ - - .globl vfork - .type vfork, function -vfork: - - /* I know, I could have used the GCC's return address builtin and done this all - * in C. But this works even if there is no builtin. - */ - - mov r0, lr - b __vfork - .size vfork, .-vfork - .end diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S new file mode 100644 index 000000000..f0fe17f73 --- /dev/null +++ b/nuttx/arch/arm/src/arm/vfork.S @@ -0,0 +1,134 @@ +/************************************************************************************ + * arch/arm/src/arm/vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "up_vfork.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .file "vfork.S" + .globl task_vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling task_vfork() with the vfork() + * context as an argument. The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .globl vfork + .type vfork, function +vfork: + /* Create a stack frame */ + + mov r0, sp /* Save the value of the stack frame on entry */ + sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + + /* Save the volatile registers */ + + str r4, [sp, #VFORK_R4_OFFSET] + str r5, [sp, #VFORK_R5_OFFSET] + str r6, [sp, #VFORK_R6_OFFSET] + str r7, [sp, #VFORK_R7_OFFSET] + str r8, [sp, #VFORK_R8_OFFSET] + str r9, [sp, #VFORK_R9_OFFSET] + str r10, [sp, #VFORK_R10_OFFSET] + + /* Save the frame pointer, stack pointer, and return address */ + + str fp, [sp, #VFORK_FP_OFFSET] + str r0, [sp, #VFORK_SP_OFFSET] + str lr, [sp, #VFORK_LR_OFFSET] + + /* Then, call task_vfork(), passing it a pointer to the stack structure */ + + mov r0, sp + bl task_vfork + + /* Release the stack data and return the value returned by task_vfork */ + + add sp, sp, #VFORK_SIZEOF + mov pc, lr + .size vfork, .-vfork + .end diff --git a/nuttx/arch/arm/src/armv7-m/up_vfork.S b/nuttx/arch/arm/src/armv7-m/up_vfork.S deleted file mode 100644 index 65ccc4535..000000000 --- a/nuttx/arch/arm/src/armv7-m/up_vfork.S +++ /dev/null @@ -1,96 +0,0 @@ -/************************************************************************************ - * arch/arm/src/armv7-m/up_vfork.S - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Global Symbols - ************************************************************************************/ - - .syntax unified - .thumb - .file "up_vfork.S" - .globl __vfork - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: vfork - * - * Description: - * The vfork() function has the same effect as fork(), except that the behavior is - * undefined if the process created by vfork() either modifies any data other than - * a variable of type pid_t used to store the return value from vfork(), or returns - * from the function in which vfork() was called, or calls any other function before - * successfully calling _exit() or one of the exec family of functions. - * - * This thin layer implements vfork by simply calling __vfork() with the vfork() - * return address as an argument. - * - * Input Paremeters: - * None - * - * Return: - * Upon successful completion, vfork() returns 0 to the child process and returns - * the process ID of the child process to the parent process. Otherwise, -1 is - * returned to the parent, no child process is created, and errno is set to - * indicate the error. - * - ************************************************************************************/ - - .thumb_func - .globl vfork - .type vfork, function -vfork: - - /* I know, I could have used the GCC's return address builtin and done this all - * in C. But this works even if there is no builtin. - */ - - mov r0, lr - b __vfork - .size vfork, .-vfork - .end - diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S new file mode 100644 index 000000000..aceded400 --- /dev/null +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -0,0 +1,138 @@ +/************************************************************************************ + * arch/arm/src/armv7-m/vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "up_vfork.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .syntax unified + .thumb + .file "vfork.S" + .globl task_vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling task_vfork() with the vfork() + * context as an argument. The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .thumb_func + .globl vfork + .type vfork, function +vfork: + /* Create a stack frame */ + + mov r0, sp /* Save the value of the stack frame on entry */ + sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + + /* Save the volatile registers */ + + str r4, [sp, #VFORK_R4_OFFSET] + str r5, [sp, #VFORK_R5_OFFSET] + str r6, [sp, #VFORK_R6_OFFSET] + str r7, [sp, #VFORK_R7_OFFSET] + str r8, [sp, #VFORK_R8_OFFSET] + str r9, [sp, #VFORK_R9_OFFSET] + str r10, [sp, #VFORK_R10_OFFSET] + + /* Save the frame pointer, stack pointer, and return address */ + + str fp, [sp, #VFORK_FP_OFFSET] + str r0, [sp, #VFORK_SP_OFFSET] + str lr, [sp, #VFORK_LR_OFFSET] + + /* Then, call task_vfork(), passing it a pointer to the stack structure */ + + mov r0, sp + bl task_vfork + + /* Release the stack data and return the value returned by task_vfork */ + + add sp, sp, #VFORK_SIZEOF + bx lr + .size vfork, .-vfork + .end + diff --git a/nuttx/arch/arm/src/c5471/Make.defs b/nuttx/arch/arm/src/c5471/Make.defs index 89c3aaf0b..afa73cf6c 100644 --- a/nuttx/arch/arm/src/c5471/Make.defs +++ b/nuttx/arch/arm/src/c5471/Make.defs @@ -35,14 +35,14 @@ HEAD_ASRC = up_nommuhead.S -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vfork.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs index 957d4e677..1a1d14869 100644 --- a/nuttx/arch/arm/src/calypso/Make.defs +++ b/nuttx/arch/arm/src/calypso/Make.defs @@ -39,14 +39,14 @@ HEAD_ASRC = calypso_head.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ - up_nommuhead.S up_vfork.S + up_nommuhead.S vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \ up_exit.c up_idle.c up_initialstate.c up_initialize.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c calypso_power.c up__vfork.c + up_undefinedinsn.c up_usestack.c calypso_power.c up_vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/common/up__vfork.c b/nuttx/arch/arm/src/common/up__vfork.c deleted file mode 100644 index a1081faa8..000000000 --- a/nuttx/arch/arm/src/common/up__vfork.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/up__vfork - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "os_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ARM requires at least a 4-byte stack alignment. For use with EABI and - * floating point, the stack must be aligned to 8-byte addresses. - */ - -#ifndef CONFIG_STACK_ALIGNMENT - -/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you - * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly! - */ - -# ifdef __ARM_EABI__ -# define CONFIG_STACK_ALIGNMENT 8 -# else -# define CONFIG_STACK_ALIGNMENT 4 -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: __vfork - * - * Description: - * The vfork() function has the same effect as fork(), except that the - * behavior is undefined if the process created by vfork() either modifies - * any data other than a variable of type pid_t used to store the return - * value from vfork(), or returns from the function in which vfork() was - * called, or calls any other function before successfully calling _exit() - * or one of the exec family of functions. - * - * This thin layer starts the vfork child by simply spawning a new thread - * that begins at the return address of vfork(). - * - * Input Paremeters: - * retaddr - The return address of vfork() - * - * Return: - * Upon successful completion, vfork() returns 0 to the child process and - * returns the process ID of the child process to the parent process. - * Otherwise, -1 is returned to the parent, no child process is created, - * and errno is set to indicate the error. - * - ****************************************************************************/ - -pid_t __vfork(uint32_t retaddr) -{ - FAR _TCB *parent = (FAR _TCB *)g_readytorun.head; - size_t stacksize; - int priority; - - /* Get the size of the parent task's stack. Due to alignment operations, - * the adjusted stack size may be smaller than the stack size originally - * requrested. - */ - - stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; - - /* Get the current priority of the parent task */ - -#ifdef CONFIG_PRIORITY_INHERITANCE - priority = parent->base_priority; /* "Normal," unboosted priority */ -#else - priority = parent->sched_priority; /* Current priority */ -#endif - - /* Start the child thread at the vfork return address. TASK_CREATE will - * return the PID of the new thread. Otherwise a negative value will be - * returned and the errno will be set appropriately. - * - * When the registers are initialized, the return value in R0 should be - * cleared to zero, providing the indication to the newly started child - * thread. - */ - - return TASK_CREATE("init", priority, stacksize, (main_t)retaddr, - (const char **)NULL); -} diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c new file mode 100644 index 000000000..404abd1f8 --- /dev/null +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -0,0 +1,196 @@ +/**************************************************************************** + * arch/arm/src/common/up_vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_vfork.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ARM requires at least a 4-byte stack alignment. For use with EABI and + * floating point, the stack must be aligned to 8-byte addresses. + */ + +#ifndef CONFIG_STACK_ALIGNMENT + +/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you + * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly! + */ + +# ifdef __ARM_EABI__ +# define CONFIG_STACK_ALIGNMENT 8 +# else +# define CONFIG_STACK_ALIGNMENT 4 +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + * + * Input Paremeters: + * context - Caller context information saved by vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +pid_t up_vfork(struct vfork_s *context) +{ + _TCB *parent = (FAR _TCB *)g_readytorun.head; + _TCB *child; + size_t stacksize; + uint32_t newsp; + uint32_t stackutil; + int ret; + + /* Allocate and initialize a TCB for the child task. */ + + child = task_vforksetup((start_t)context->lr); + if (!child) + { + return (pid_t)ERROR; + } + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Allocate the stack for the TCB */ + + ret = up_create_stack(child, stacksize); + if (ret != OK) + { + task_vforkabort(child, -ret); + return (pid_t)ERROR; + } + + /* How much of the parent's stack was utilized? */ + + DEBUGASSERT(parent->adj_stack_ptr > context->sp); + stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + + /* Make some feeble effort to perserve the stack contents. This is + * feeble because the stack surely contains invalid pointer and other + * content that will not work in the child context. However, if the + * user follows all of the caveats of vfor() usage, even this feeble + * effort is overkill. + */ + + newsp = (uint32_t)child->adj_stack_ptr - stackutil; + memcpy((void *)newsp, (const void *)context->sp, stackutil); + + /* Update the stack pointer, frame pointer, and voltile registers. When + * the child TCB was initialized, all of the values were set to zero. + * up_initial_state() altered a few values, but the return value in R0 + * should be cleared to zero, providing the indication to the newly started + * child thread. + */ + + child->xcp.regs[REG_R4] = context->r4; /* Volatile register r4 */ + child->xcp.regs[REG_R5] = context->r5; /* Volatile register r5 */ + child->xcp.regs[REG_R6] = context->r6; /* Volatile register r6 */ + child->xcp.regs[REG_R7] = context->r7; /* Volatile register r7 */ + child->xcp.regs[REG_R8] = context->r8; /* Volatile register r8 */ + child->xcp.regs[REG_R9] = context->r9; /* Volatile register r9 */ + child->xcp.regs[REG_R10] = context->r10; /* Volatile register r10 */ + child->xcp.regs[REG_FP] = context->fp; /* Frame pointer */ + child->xcp.regs[REG_SP] = context->sp; /* Stack pointer */ + + /* And, finally, start the child task. On a failure, task_vforkstart() + * will discard the TCB by calling task_vforkabort(). + */ + + return task_vforkstart(child); +} diff --git a/nuttx/arch/arm/src/common/up_vfork.h b/nuttx/arch/arm/src/common/up_vfork.h new file mode 100644 index 000000000..a4505474a --- /dev/null +++ b/nuttx/arch/arm/src/common/up_vfork.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/src/common/arm-vfork.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARM_VFORK_H +#define __ARCH_ARM_SRC_ARM_VFORK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define VFORK_R4_OFFSET (0*4) /* Volatile register r4 */ +#define VFORK_R5_OFFSET (1*4) /* Volatile register r5 */ +#define VFORK_R6_OFFSET (2*4) /* Volatile register r6 */ +#define VFORK_R7_OFFSET (3*4) /* Volatile register r7 */ +#define VFORK_R8_OFFSET (4*4) /* Volatile register r8 */ +#define VFORK_R9_OFFSET (5*4) /* Volatile register r9 */ +#define VFORK_R10_OFFSET (6*4) /* Volatile register r10 */ +#define VFORK_FP_OFFSET (7*4) /* Frame pointer */ +#define VFORK_SP_OFFSET (8*4) /* Stack pointer*/ +#define VFORK_LR_OFFSET (9*4) /* Return address*/ + +#define VFORK_SIZEOF (10*4) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct vfork_s +{ + uint32_t r4; /* Volatile register r4 */ + uint32_t r5; /* Volatile register r5 */ + uint32_t r6; /* Volatile register r6 */ + uint32_t r7; /* Volatile register r7 */ + uint32_t r8; /* Volatile register r8 */ + uint32_t r9; /* Volatile register r9 */ + uint32_t r10; /* Volatile register r10 */ + uint32_t fp; /* Frame pointer */ + uint32_t sp; /* Stack pointer*/ + uint32_t lr; /* Return address*/ +}; +#endif + +#endif /* __ARCH_ARM_SRC_ARM_VFORK_H */ diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs index 52e65c0e8..651d9fea9 100644 --- a/nuttx/arch/arm/src/dm320/Make.defs +++ b/nuttx/arch/arm/src/dm320/Make.defs @@ -36,14 +36,14 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs index a7c0ceebd..3cea29b9b 100644 --- a/nuttx/arch/arm/src/imx/Make.defs +++ b/nuttx/arch/arm/src/imx/Make.defs @@ -36,14 +36,14 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_vfork.c ifeq ($(CONFIG_ELF),y) CMN_CSRCS += up_elf.c diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs index bad2946e2..e41746547 100644 --- a/nuttx/arch/arm/src/kinetis/Make.defs +++ b/nuttx/arch/arm/src/kinetis/Make.defs @@ -40,7 +40,7 @@ HEAD_ASRC = kinetis_vectors.S # Common ARM and Cortex-M3 files CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_initialize.c \ up_memfault.c up_initialstate.c up_interruptcontext.c \ @@ -48,7 +48,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_releasepending.c up_sigdeliver.c up_unblocktask.c up_usestack.c \ up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c \ - up__vfork.c + up_vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs index c745e1953..66b8f5658 100644 --- a/nuttx/arch/arm/src/lm3s/Make.defs +++ b/nuttx/arch/arm/src/lm3s/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = lm3s_vectors.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \ @@ -44,7 +44,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \ up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ - up__vfork.c + up_vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs index 1ea0183a1..ed05fff95 100644 --- a/nuttx/arch/arm/src/lpc17xx/Make.defs +++ b/nuttx/arch/arm/src/lpc17xx/Make.defs @@ -40,14 +40,14 @@ HEAD_ASRC = lpc17_vectors.S # Common ARM and Cortex-M3 files CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c \ up_initialstate.c up_interruptcontext.c up_modifyreg8.c \ up_modifyreg16.c up_modifyreg32.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \ - up_hardfault.c up_svcall.c up_checkstack.c up__vfork.c + up_hardfault.c up_svcall.c up_checkstack.c up_vfork.c ifeq ($(CONFIG_ARCH_MEMCPY),y) CMN_ASRCS += up_memcpy.S diff --git a/nuttx/arch/arm/src/lpc214x/Make.defs b/nuttx/arch/arm/src/lpc214x/Make.defs index 6821d512b..34713b008 100644 --- a/nuttx/arch/arm/src/lpc214x/Make.defs +++ b/nuttx/arch/arm/src/lpc214x/Make.defs @@ -36,13 +36,13 @@ HEAD_ASRC = lpc214x_head.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs index 3d3c15926..cfd9dc79f 100644 --- a/nuttx/arch/arm/src/lpc2378/Make.defs +++ b/nuttx/arch/arm/src/lpc2378/Make.defs @@ -41,13 +41,13 @@ HEAD_ASRC = lpc23xx_head.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/arch/arm/src/lpc31xx/Make.defs b/nuttx/arch/arm/src/lpc31xx/Make.defs index b3a9746b4..4e6f69299 100644 --- a/nuttx/arch/arm/src/lpc31xx/Make.defs +++ b/nuttx/arch/arm/src/lpc31xx/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = up_head.S CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \ - up_vectors.S up_vectoraddrexcptn.S up_vectortab.S up_vfork.S + up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ @@ -44,7 +44,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_prefetchabort.c up_releasepending.c up_releasestack.c \ up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_vfork.c ifeq ($(CONFIG_PAGING),y) CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs index 211f9bee3..9674196c5 100644 --- a/nuttx/arch/arm/src/lpc43xx/Make.defs +++ b/nuttx/arch/arm/src/lpc43xx/Make.defs @@ -36,7 +36,7 @@ HEAD_ASRC = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S -CMN_ASRCS += up_vfork.S +CMN_ASRCS += vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c @@ -44,7 +44,7 @@ CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c -CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up__vfork.c +CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c up_vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs index 4682ea83d..58047af21 100644 --- a/nuttx/arch/arm/src/sam3u/Make.defs +++ b/nuttx/arch/arm/src/sam3u/Make.defs @@ -40,14 +40,14 @@ HEAD_ASRC = sam3u_vectors.S # Common ARM and Cortex-M3 files CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \ up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \ up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c \ up_modifyreg16.c up_modifyreg32.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \ - up_hardfault.c up_svcall.c up__vfork.c + up_hardfault.c up_svcall.c up_vfork.c # Configuration-dependent common files diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index 89c291791..fd19e3bf6 100644 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -40,7 +40,7 @@ HEAD_ASRC = stm32_vectors.S endif CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ @@ -48,7 +48,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \ up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \ up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c \ - up_svcall.c up__vfork.c + up_svcall.c up_vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs index 3612950a6..bde5ca003 100644 --- a/nuttx/arch/arm/src/str71x/Make.defs +++ b/nuttx/arch/arm/src/str71x/Make.defs @@ -36,13 +36,13 @@ HEAD_ASRC = str71x_head.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ - up_vfork.S + vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \ up_exit.c up_idle.c up_initialize.c up_initialstate.c \ up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \ - up_undefinedinsn.c up_usestack.c up_lowputs.c up__vfork.c + up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c diff --git a/nuttx/include/nuttx/arch.h b/nuttx/include/nuttx/arch.h index 8b4b10ade..958986472 100644 --- a/nuttx/include/nuttx/arch.h +++ b/nuttx/include/nuttx/arch.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/arch.h * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h index 6eaba6e9c..940bf1f1b 100644 --- a/nuttx/include/nuttx/sched.h +++ b/nuttx/include/nuttx/sched.h @@ -382,6 +382,32 @@ EXTERN FAR struct streamlist *sched_getstreams(void); EXTERN FAR struct socketlist *sched_getsockets(void); #endif /* CONFIG_NSOCKET_DESCRIPTORS */ +/* Internal vfork support.The overall sequence is: + * + * 1) User code calls vfork(). vfork() is provided in architecture-specific + * code. + * 2) vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) vfork() provides any additional operating context. vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + */ + +FAR _TCB *task_vforksetup(start_t retaddr); +pid_t task_vforkstart(FAR _TCB *child); +void task_vforkabort(FAR _TCB *child, int errcode); + /* sched_foreach will enumerate over each task and provide the * TCB of each task to a user callback functions. Interrupts * will be disabled throughout this enumeration! diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile index 82f74fc3c..23d1e9938 100644 --- a/nuttx/sched/Makefile +++ b/nuttx/sched/Makefile @@ -45,7 +45,7 @@ MISC_SRCS = os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c \ TSK_SRCS = prctl.c task_create.c task_init.c task_setup.c task_activate.c \ task_start.c task_delete.c task_deletecurrent.c task_exithook.c \ - task_restart.c exit.c getpid.c sched_addreadytorun.c \ + task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c \ sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c \ sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c \ sched_verifytcb.c sched_releasetcb.c diff --git a/nuttx/sched/sched_setuptaskfiles.c b/nuttx/sched/sched_setuptaskfiles.c index fe0b14143..d01b8d4cd 100644 --- a/nuttx/sched/sched_setuptaskfiles.c +++ b/nuttx/sched/sched_setuptaskfiles.c @@ -200,7 +200,8 @@ static inline void sched_dupsockets(FAR _TCB *tcb) * tcb - tcb of the new task. * * Return Value: - * None + * Zero (OK) is returned on success; A negated errno value is returned on + * failure. * * Assumptions: * diff --git a/nuttx/sched/task_create.c b/nuttx/sched/task_create.c index 4d92c9bb0..801706cbf 100644 --- a/nuttx/sched/task_create.c +++ b/nuttx/sched/task_create.c @@ -169,6 +169,8 @@ static int thread_create(const char *name, uint8_t type, int priority, ret = task_activate(tcb); if (ret != OK) { + /* The TCB was added to the active task list by task_schedsetup() */ + dq_rem((FAR dq_entry_t*)tcb, (dq_queue_t*)&g_inactivetasks); goto errout_with_tcb; } diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c new file mode 100644 index 000000000..93fcb46da --- /dev/null +++ b/nuttx/sched/task_vfork.c @@ -0,0 +1,266 @@ +/**************************************************************************** + * sched/task_vfork + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "os_internal.h" +#include "env_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: task_vforksetup + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * This functin provides one step in the overall vfork() sequence: It + * Allocates and initializes the child task's TCB. The overall sequence is: + * + * 1) User code calls vfork(). vfork() is provided in architecture-specific + * code. + * 2) vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * retaddr - The return address from vfork() where the child task + * will be started. + * + * Returned Value: + * Upon successful completion, task_vforksetup() returns a pointer to + * newly allocated and initalized child task's TCB. NULL is returned + * on any failure and the errno is set appropriately. + * + ****************************************************************************/ + +FAR _TCB *task_vforksetup(start_t retaddr) +{ + _TCB *parent = (FAR _TCB *)g_readytorun.head; + _TCB *child; + int priority; + int ret; + + DEBUGASSERT(retaddr); + + /* Allocate a TCB for the child task. */ + + child = (FAR _TCB*)kzalloc(sizeof(_TCB)); + if (!child) + { + set_errno(ENOMEM); + return NULL; + } + + /* Associate file descriptors with the new task */ + +#if CONFIG_NFILE_DESCRIPTORS > 0 || CONFIG_NSOCKET_DESCRIPTORS > 0 + ret = sched_setuptaskfiles(child); + if (ret != OK) + { + goto errout_with_tcb; + } +#endif + + /* Clone the parent's task environment */ + + (void)env_dup(child); + + /* Mark the type of this thread (this setting will be needed in + * task_schedsetup() when up_initial_state() is called. + */ + + child->flags |= TCB_FLAG_TTYPE_TASK; + + /* Get the priority of the parent task */ + +#ifdef CONFIG_PRIORITY_INHERITANCE + priority = parent->base_priority; /* "Normal," unboosted priority */ +#else + priority = parent->sched_priority; /* Current priority */ +#endif + + /* Initialize the task control block. This calls up_initial_state() */ + + ret = task_schedsetup(child, priority, retaddr, parent->entry.main); + if (ret != OK) + { + goto errout_with_tcb; + } + + return child; + +errout_with_tcb: + sched_releasetcb(child); + set_errno(-ret); + return NULL; +} + +/**************************************************************************** + * Name: task_vforkstart + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * This functin provides one step in the overall vfork() sequence: It + * starts execution of the previously initialized TCB. The overall + * sequence is: + * + * 1) User code calls vfork() + * 2) Architecture-specific code provides vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) vfork() provides any additional operating context. vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * retaddr - The return address from vfork() where the child task + * will be started. + * + * Returned Value: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +pid_t task_vforkstart(FAR _TCB *child) +{ + FAR const char *name; + pid_t pid; + int ret; + + DEBUGASSERT(child); + + /* Setup to pass parameters to the new task */ + +#if CONFIG_TASK_NAME_SIZE > 0 + name = parent->name; +#else + name = ""; +#endif + + (void)task_argsetup(child, name, (const char **)NULL); + + /* Get the assigned pid before we start the task */ + + pid = (int)child->pid; + + /* Activate the task */ + + ret = task_activate(child); + if (ret != OK) + { + task_vforkabort(child, -ret); + return ERROR; + } + + return pid; +} + +/**************************************************************************** + * Name: task_vforkabort + * + * Description: + * Recover from any errors after task_vforksetup() was called. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void task_vforkabort(FAR _TCB *child, int errcode) +{ + /* The TCB was added to the active task list by task_schedsetup() */ + + dq_rem((FAR dq_entry_t*)child, (dq_queue_t*)&g_inactivetasks); + + /* Release the TCB */ + + sched_releasetcb(child); + set_errno(errcode); +} \ No newline at end of file -- cgit v1.2.3 From 66cdd288ab6a4d19c67300a73a26e9ee5a958187 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 7 Jan 2013 21:41:20 +0000 Subject: Add ostest vfork test (does not work yet) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5488 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/ostest/Makefile | 4 ++ apps/examples/ostest/ostest.h | 6 +++ apps/examples/ostest/ostest_main.c | 6 +++ apps/examples/ostest/vfork.c | 99 ++++++++++++++++++++++++++++++++++++ nuttx/arch/Kconfig | 5 ++ nuttx/arch/arm/src/arm/vfork.S | 10 ++-- nuttx/arch/arm/src/armv7-m/vfork.S | 10 ++-- nuttx/arch/arm/src/common/up_vfork.c | 45 +++++++++++++--- nuttx/sched/sched_addprioritized.c | 2 +- nuttx/sched/sched_addreadytorun.c | 8 +-- nuttx/sched/task_vfork.c | 9 +++- 11 files changed, 182 insertions(+), 22 deletions(-) create mode 100644 apps/examples/ostest/vfork.c diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile index 3d19f6a78..b7ba9a9a8 100644 --- a/apps/examples/ostest/Makefile +++ b/apps/examples/ostest/Makefile @@ -84,6 +84,10 @@ ifneq ($(CONFIG_DISABLE_POSIX_TIMERS),y) CSRCS += posixtimer.c endif +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CSRCS += vfork.c +endif + ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_PTHREAD),y) ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) diff --git a/apps/examples/ostest/ostest.h b/apps/examples/ostest/ostest.h index a4af37f05..bc46a3860 100644 --- a/apps/examples/ostest/ostest.h +++ b/apps/examples/ostest/ostest.h @@ -163,6 +163,12 @@ extern void barrier_test(void); extern void priority_inheritance(void); +/* vfork.c ******************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_VFORK +extern int vfork_test(void); +#endif + /* APIs exported (conditionally) by the OS specifically for testing of * priority inheritance */ diff --git a/apps/examples/ostest/ostest_main.c b/apps/examples/ostest/ostest_main.c index 46726d515..ca44353c3 100644 --- a/apps/examples/ostest/ostest_main.c +++ b/apps/examples/ostest/ostest_main.c @@ -409,6 +409,11 @@ static int user_main(int argc, char *argv[]) check_test_memory_usage(); #endif /* CONFIG_PRIORITY_INHERITANCE && !CONFIG_DISABLE_SIGNALS && !CONFIG_DISABLE_PTHREAD */ +#ifdef CONFIG_ARCH_HAVE_VFORK + printf("\nuser_main: vfork() test\n"); + vfork_test(); +#endif + /* Compare memory usage at time ostest_main started until * user_main exits. These should not be identical, but should * be similar enough that we can detect any serious OS memory @@ -428,6 +433,7 @@ static int user_main(int argc, char *argv[]) show_memory_usage(&g_mmbefore, &g_mmafter); #endif } + printf("user_main: Exitting\n"); return 0; } diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c new file mode 100644 index 000000000..6c83047e3 --- /dev/null +++ b/apps/examples/ostest/vfork.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * examples/ostest/vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "ostest.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_ARCH_HAVE_VFORK) && !defined(CONFIG_DISABLE_SIGNALS) +static volatile bool g_vforkchild; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int vfork_test(void) +{ +#if defined(CONFIG_ARCH_HAVE_VFORK) && !defined(CONFIG_DISABLE_SIGNALS) + pid_t pid; + + g_vforkchild = false; + pid = vfork(); + if (pid == 0) + { + /* There is not very much that the child is permitted to do. Perhaps + * it can just set g_vforkchild. + */ + + g_vforkchild = true; + exit(0); + } + else if (pid < 0) + { + printf("vfork_test: vfork() failed: %d\n", errno); + return -1; + } + else + { + sleep(1); + if (g_vforkchild) + { + printf("vfork_test: Child %d ran successfully\n", pid); + } + else + { + printf("vfork_test: ERROR Child %d did not run\n", pid); + return -1; + } + } +#endif + + return 0; +} diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig index f19228143..7d34b56f4 100644 --- a/nuttx/arch/Kconfig +++ b/nuttx/arch/Kconfig @@ -16,6 +16,7 @@ config ARCH_8051 config ARCH_ARM bool "ARM" select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_VFORK ---help--- The ARM architectures @@ -124,6 +125,10 @@ config ADDRENV bool default n +config ARCH_HAVE_VFORK + bool + default n + config ARCH_STACKDUMP bool "Dump stack on assertions" default n diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S index f0fe17f73..b498fd7f7 100644 --- a/nuttx/arch/arm/src/arm/vfork.S +++ b/nuttx/arch/arm/src/arm/vfork.S @@ -50,7 +50,7 @@ ************************************************************************************/ .file "vfork.S" - .globl task_vfork + .globl up_vfork /************************************************************************************ * Public Functions @@ -66,7 +66,7 @@ * from the function in which vfork() was called, or calls any other function before * successfully calling _exit() or one of the exec family of functions. * - * This thin layer implements vfork by simply calling task_vfork() with the vfork() + * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: * * 1) User code calls vfork(). vfork() collects context information and @@ -121,12 +121,12 @@ vfork: str r0, [sp, #VFORK_SP_OFFSET] str lr, [sp, #VFORK_LR_OFFSET] - /* Then, call task_vfork(), passing it a pointer to the stack structure */ + /* Then, call up_vfork(), passing it a pointer to the stack structure */ mov r0, sp - bl task_vfork + bl up_vfork - /* Release the stack data and return the value returned by task_vfork */ + /* Release the stack data and return the value returned by up_vfork */ add sp, sp, #VFORK_SIZEOF mov pc, lr diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S index aceded400..0d9e144cd 100644 --- a/nuttx/arch/arm/src/armv7-m/vfork.S +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -52,7 +52,7 @@ .syntax unified .thumb .file "vfork.S" - .globl task_vfork + .globl up_vfork /************************************************************************************ * Public Functions @@ -68,7 +68,7 @@ * from the function in which vfork() was called, or calls any other function before * successfully calling _exit() or one of the exec family of functions. * - * This thin layer implements vfork by simply calling task_vfork() with the vfork() + * This thin layer implements vfork by simply calling up_vfork() with the vfork() * context as an argument. The overall sequence is: * * 1) User code calls vfork(). vfork() collects context information and @@ -124,12 +124,12 @@ vfork: str r0, [sp, #VFORK_SP_OFFSET] str lr, [sp, #VFORK_LR_OFFSET] - /* Then, call task_vfork(), passing it a pointer to the stack structure */ + /* Then, call up_vfork(), passing it a pointer to the stack structure */ mov r0, sp - bl task_vfork + bl up_vfork - /* Release the stack data and return the value returned by task_vfork */ + /* Release the stack data and return the value returned by up_vfork */ add sp, sp, #VFORK_SIZEOF bx lr diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c index 404abd1f8..2e3c2d4a1 100644 --- a/nuttx/arch/arm/src/common/up_vfork.c +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include @@ -129,17 +130,28 @@ pid_t up_vfork(struct vfork_s *context) _TCB *child; size_t stacksize; uint32_t newsp; + uint32_t newfp; uint32_t stackutil; int ret; + svdbg("r4:%08x r5:%08x r6:%08x r7:%08x\n", + context->r4, context->r5, context->r6, context->r7); + svdbg("r8:%08x r9:%08x r10:%08x\n", + context->r8, context->r9, context->r10); + svdbg("fp:%08x sp:%08x lr:%08x\n", + context->fp, context->sp, context->lr); + /* Allocate and initialize a TCB for the child task. */ - child = task_vforksetup((start_t)context->lr); + child = task_vforksetup((start_t)(context->lr & ~1)); if (!child) { + sdbg("task_vforksetup failed\n"); return (pid_t)ERROR; } + svdbg("Parent=%p Child=%p\n", parent, child); + /* Get the size of the parent task's stack. Due to alignment operations, * the adjusted stack size may be smaller than the stack size originally * requrested. @@ -152,15 +164,18 @@ pid_t up_vfork(struct vfork_s *context) ret = up_create_stack(child, stacksize); if (ret != OK) { + sdbg("up_create_stack failed: %d\n", ret); task_vforkabort(child, -ret); return (pid_t)ERROR; } /* How much of the parent's stack was utilized? */ - DEBUGASSERT(parent->adj_stack_ptr > context->sp); + DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); + /* Make some feeble effort to perserve the stack contents. This is * feeble because the stack surely contains invalid pointer and other * content that will not work in the child context. However, if the @@ -170,8 +185,26 @@ pid_t up_vfork(struct vfork_s *context) newsp = (uint32_t)child->adj_stack_ptr - stackutil; memcpy((void *)newsp, (const void *)context->sp, stackutil); - - /* Update the stack pointer, frame pointer, and voltile registers. When + + /* Was there a frame pointer in place before? */ + + if (context->fp <= (uint32_t)parent->adj_stack_ptr && + context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize) + { + uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp; + newfp = (uint32_t)child->adj_stack_ptr - frameutil; + } + else + { + newfp = context->fp; + } + + svdbg("Old stack base:%08x SP:%08x FP:%08x\n", + parent->adj_stack_ptr, context->sp, context->fp); + svdbg("New stack base:%08x SP:%08x FP:%08x\n", + child->adj_stack_ptr, newsp, newfp); + + /* Update the stack pointer, frame pointer, and voltile registers. When * the child TCB was initialized, all of the values were set to zero. * up_initial_state() altered a few values, but the return value in R0 * should be cleared to zero, providing the indication to the newly started @@ -185,8 +218,8 @@ pid_t up_vfork(struct vfork_s *context) child->xcp.regs[REG_R8] = context->r8; /* Volatile register r8 */ child->xcp.regs[REG_R9] = context->r9; /* Volatile register r9 */ child->xcp.regs[REG_R10] = context->r10; /* Volatile register r10 */ - child->xcp.regs[REG_FP] = context->fp; /* Frame pointer */ - child->xcp.regs[REG_SP] = context->sp; /* Stack pointer */ + child->xcp.regs[REG_FP] = newfp; /* Frame pointer */ + child->xcp.regs[REG_SP] = newsp; /* Stack pointer */ /* And, finally, start the child task. On a failure, task_vforkstart() * will discard the TCB by calling task_vforkabort(). diff --git a/nuttx/sched/sched_addprioritized.c b/nuttx/sched/sched_addprioritized.c index 8f19a4731..20178fb9c 100644 --- a/nuttx/sched/sched_addprioritized.c +++ b/nuttx/sched/sched_addprioritized.c @@ -114,7 +114,7 @@ bool sched_addprioritized(FAR _TCB *tcb, DSEG dq_queue_t *list) (next && sched_priority <= next->sched_priority); next = next->flink); - /* Add the tcb to the spot found in the list. Check if the tcb + /* Add the tcb to the spot found in the list. Check if the tcb * goes at the end of the list. NOTE: This could only happen if list * is the g_pendingtasks list! */ diff --git a/nuttx/sched/sched_addreadytorun.c b/nuttx/sched/sched_addreadytorun.c index f6117b6ff..1e1829343 100644 --- a/nuttx/sched/sched_addreadytorun.c +++ b/nuttx/sched/sched_addreadytorun.c @@ -84,8 +84,8 @@ * btcb - Points to the blocked TCB that is ready-to-run * * Return Value: - * true if the currently active task (the head of the - * g_readytorun list) has changed. + * true if the currently active task (the head of the g_readytorun list) + * has changed. * * Assumptions: * - The caller has established a critical section before @@ -104,7 +104,7 @@ bool sched_addreadytorun(FAR _TCB *btcb) bool ret; /* Check if pre-emption is disabled for the current running task and if - * the new ready-to-run task would cause the current running task to be + * the new ready-to-run task would cause the current running task to be * preempted. */ @@ -123,7 +123,7 @@ bool sched_addreadytorun(FAR _TCB *btcb) else if (sched_addprioritized(btcb, (FAR dq_queue_t*)&g_readytorun)) { - /* Information the instrumentation logic that we are switching tasks */ + /* Inform the instrumentation logic that we are switching tasks */ sched_note_switch(rtcb, btcb); diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c index 93fcb46da..64f6f0636 100644 --- a/nuttx/sched/task_vfork.c +++ b/nuttx/sched/task_vfork.c @@ -43,6 +43,7 @@ #include #include #include +#include #include @@ -151,12 +152,14 @@ FAR _TCB *task_vforksetup(start_t retaddr) /* Initialize the task control block. This calls up_initial_state() */ + svdbg("Child priority=%d start=%p\n", priority, retaddr); ret = task_schedsetup(child, priority, retaddr, parent->entry.main); if (ret != OK) { goto errout_with_tcb; } + svdbg("parent=%p, returning child=%p\n", parent, child); return child; errout_with_tcb: @@ -210,10 +213,14 @@ errout_with_tcb: pid_t task_vforkstart(FAR _TCB *child) { +#if CONFIG_TASK_NAME_SIZE > 0 + _TCB *parent = (FAR _TCB *)g_readytorun.head; +#endif FAR const char *name; pid_t pid; int ret; + svdbg("Starting Child TCB=%p, parent=%p\n", child, g_readytorun.head); DEBUGASSERT(child); /* Setup to pass parameters to the new task */ @@ -221,7 +228,7 @@ pid_t task_vforkstart(FAR _TCB *child) #if CONFIG_TASK_NAME_SIZE > 0 name = parent->name; #else - name = ""; + name = NULL; #endif (void)task_argsetup(child, name, (const char **)NULL); -- cgit v1.2.3 From 5a9162f017e457a5415eb0af7c41a7ef49d355c6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 7 Jan 2013 23:09:09 +0000 Subject: Disable the vfork() OS test... it fails git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5489 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/ostest/vfork.c | 10 ++++++++++ nuttx/arch/arm/src/common/up_vfork.c | 10 +++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c index 6c83047e3..8657f0ceb 100644 --- a/apps/examples/ostest/vfork.c +++ b/apps/examples/ostest/vfork.c @@ -47,6 +47,16 @@ #include "ostest.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Disabled this test for now. There are some issues with the vfork + * implementation. +*/ + +#undef CONFIG_ARCH_HAVE_VFORK + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c index 2e3c2d4a1..3da602679 100644 --- a/nuttx/arch/arm/src/common/up_vfork.c +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -169,7 +169,11 @@ pid_t up_vfork(struct vfork_s *context) return (pid_t)ERROR; } - /* How much of the parent's stack was utilized? */ + /* How much of the parent's stack was utilized? The ARM uses + * a push-down stack so that the current stack pointer should + * be lower than the initial, adjusted stack pointer. The + * stack usage should be the difference between those two. + */ DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; @@ -177,7 +181,7 @@ pid_t up_vfork(struct vfork_s *context) svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); /* Make some feeble effort to perserve the stack contents. This is - * feeble because the stack surely contains invalid pointer and other + * feeble because the stack surely contains invalid pointers and other * content that will not work in the child context. However, if the * user follows all of the caveats of vfor() usage, even this feeble * effort is overkill. @@ -204,7 +208,7 @@ pid_t up_vfork(struct vfork_s *context) svdbg("New stack base:%08x SP:%08x FP:%08x\n", child->adj_stack_ptr, newsp, newfp); - /* Update the stack pointer, frame pointer, and voltile registers. When + /* Update the stack pointer, frame pointer, and voltile registers. When * the child TCB was initialized, all of the values were set to zero. * up_initial_state() altered a few values, but the return value in R0 * should be cleared to zero, providing the indication to the newly started -- cgit v1.2.3 From a9f2c6fa8ae6936da9489e4acf2a2d2cd6c0f664 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 7 Jan 2013 23:50:25 +0000 Subject: Fixed ARM vfork; re-enabled vfork OS test git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5490 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/ostest/vfork.c | 6 ------ nuttx/arch/arm/src/arm/vfork.S | 3 ++- nuttx/arch/arm/src/armv7-m/vfork.S | 3 ++- nuttx/arch/arm/src/common/up_vfork.c | 2 +- 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/apps/examples/ostest/vfork.c b/apps/examples/ostest/vfork.c index 8657f0ceb..4e1b8c892 100644 --- a/apps/examples/ostest/vfork.c +++ b/apps/examples/ostest/vfork.c @@ -51,12 +51,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Disabled this test for now. There are some issues with the vfork - * implementation. -*/ - -#undef CONFIG_ARCH_HAVE_VFORK - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S index b498fd7f7..226d9f7de 100644 --- a/nuttx/arch/arm/src/arm/vfork.S +++ b/nuttx/arch/arm/src/arm/vfork.S @@ -102,7 +102,7 @@ vfork: /* Create a stack frame */ - mov r0, sp /* Save the value of the stack frame on entry */ + mov r0, sp /* Save the value of the stack on entry */ sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ /* Save the volatile registers */ @@ -128,6 +128,7 @@ vfork: /* Release the stack data and return the value returned by up_vfork */ + ldr lr, [sp, #VFORK_LR_OFFSET] add sp, sp, #VFORK_SIZEOF mov pc, lr .size vfork, .-vfork diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S index 0d9e144cd..386fca33c 100644 --- a/nuttx/arch/arm/src/armv7-m/vfork.S +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -105,7 +105,7 @@ vfork: /* Create a stack frame */ - mov r0, sp /* Save the value of the stack frame on entry */ + mov r0, sp /* Save the value of the stack on entry */ sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ /* Save the volatile registers */ @@ -131,6 +131,7 @@ vfork: /* Release the stack data and return the value returned by up_vfork */ + ldr lr, [sp, #VFORK_LR_OFFSET] add sp, sp, #VFORK_SIZEOF bx lr .size vfork, .-vfork diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c index 3da602679..5349378bc 100644 --- a/nuttx/arch/arm/src/common/up_vfork.c +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -124,7 +124,7 @@ * ****************************************************************************/ -pid_t up_vfork(struct vfork_s *context) +pid_t up_vfork(const struct vfork_s *context) { _TCB *parent = (FAR _TCB *)g_readytorun.head; _TCB *child; -- cgit v1.2.3 From 3d160e45b64485aa5f231179bf61cdea8fc5c141 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 8 Jan 2013 00:04:12 +0000 Subject: Documentation update git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5491 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 1 + nuttx/Documentation/NuttX.html | 2 +- nuttx/Documentation/NuttxPortingGuide.html | 2 +- nuttx/Documentation/NuttxUserGuide.html | 39 +++++++++++++++++++++++++++++- 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 0464c6198..cd15b430d 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -460,4 +460,5 @@ updated to detect key release events. That is kind of tricky in the USB HID keyboard report data. * apps/examples/wlan: Remove non-functional example. + * apps/examples/ostest/vfork.c: Added a test of vfork(). diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 876aa2a0a..21f732c97 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -8,7 +8,7 @@

            NuttX RTOS

            -

            Last Updated: January 4, 2012

            +

            Last Updated: January 4, 2013

            diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 24b4852e0..48fafb89f 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

            NuttX RTOS Porting Guide

            -

            Last Updated: January 4, 2012

            +

            Last Updated: January 4, 2013

            diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index d9dddf9be..5c76737e5 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

            NuttX Operating System

            User's Manual

            by

            Gregory Nutt

            -

            Last Updated: November 20, 2012

            +

            Last Updated: January 7, 2013

            @@ -201,6 +201,7 @@ paragraphs.
          • 2.1.5 exit
          • 2.1.6 task_restart
          • 2.1.7 getpid
            • +
          • 2.1.8 vfork

          2.1.1 task_create

          @@ -613,6 +614,40 @@ level. Compatible with the POSIX interface of the same name.

          +

          2.1.8 vfork

          +

          + Function Prototype: +

          + 
            +#include <unistd.h>
+pid_t vfork(void);
+
          +

          + Description: + The vfork() function has the same effect as fork(), except that the behavior is undefined if the process created by vfork() either modifies any data other than a variable of type pid_t used to store the return value from vfork(), or returns from the function in which vfork() was called, or calls any other function before successfully calling _exit() or one of the exec family of functions. +

          +

          + NOTE: + vfork() is not an independent NuttX feature, but is implemented in architecture-specific logic (using only helper functions from the NuttX core logic). + As a result, vfork() may not be available on all architectures. +
          +

          + Input Parameters: + None. +

          +

          + Returned Value: + Upon successful completion, vfork() returns 0 to the child process and returns + the process ID of the child process to the parent process. + Otherwise, -1 is returned to the parent, no child process is created, and errno is set to indicate the error. +

          + Assumptions/Limitations: +

          +

          + POSIX Compatibility: + Compatible with the Unix interface of the same name. +

          + @@ -536,7 +536,7 @@ @@ -1009,7 +1009,7 @@ This configuration file contains a long list of settings that control what is built into NuttX and what is not. There are hundreds of such settings - (see the NuttX Porting Guide + (see the NuttX Porting Guide for a partial list that excludes platform specific settings). These many, many configuration options allow NuttX to be highly tuned to meet size requirements. @@ -3837,7 +3837,7 @@ pascal-3.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org> - + diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 0b67eddb7..fec7106b0 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

          NuttX RTOS Porting Guide

          -

          Last Updated: January 12, 2013

          +

          Last Updated: January 13, 2013

          @@ -6741,6 +6776,7 @@ int telldir(FAR DIR *dirp); 
             #include <unistd.h>
 
+pid_t   vfork(void);
 pid_t   getpid(void);
 void    _exit(int status) noreturn_function;
 unsigned int sleep(unsigned int seconds);
@@ -8363,6 +8399,7 @@ notify a task when a message is available on a queue.
   
          • unistd.h,
       unistd.h
            • 
   
          • unlink
            • 
+  
          • vfork
            • 
   
          • vfprintf
            • 
   
          • vprintf
            • 
   
          • vsprintf
            • 
-- 
cgit v1.2.3


From 14f72f7a210648fe6eaaac3359ec76cab62c7278 Mon Sep 17 00:00:00 2001
From: patacongo 
Date: Tue, 8 Jan 2013 16:25:30 +0000
Subject: Add execv() and execl(); Move lm3s header files for compatibility

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5492 42af7a65-404d-4744-a932-0658087f49c3
---
 nuttx/ChangeLog                                |  12 +
 nuttx/Documentation/NuttxUserGuide.html        |  15 +-
 nuttx/arch/arm/include/lm3s/chip.h             | 123 ++++++
 nuttx/arch/arm/src/lm3s/chip.h                 |  79 +---
 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h        | 113 ++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h   | 203 ++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h      | 128 +++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h       | 395 ++++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h        | 247 ++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h  | 360 ++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h        | 235 ++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h | 495 +++++++++++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h      | 125 +++++++
 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h       | 347 +++++++++++++++++
 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h    |  69 ++++
 nuttx/arch/arm/src/lm3s/lm3s_epi.h             | 113 ------
 nuttx/arch/arm/src/lm3s/lm3s_ethernet.h        | 203 ----------
 nuttx/arch/arm/src/lm3s/lm3s_flash.h           | 128 -------
 nuttx/arch/arm/src/lm3s/lm3s_gpio.h            | 395 --------------------
 nuttx/arch/arm/src/lm3s/lm3s_i2c.h             | 247 ------------
 nuttx/arch/arm/src/lm3s/lm3s_memorymap.h       | 360 ------------------
 nuttx/arch/arm/src/lm3s/lm3s_ssi.h             | 235 ------------
 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h      | 495 -------------------------
 nuttx/arch/arm/src/lm3s/lm3s_timer.h           | 125 -------
 nuttx/arch/arm/src/lm3s/lm3s_uart.h            | 347 -----------------
 nuttx/binfmt/binfmt_exec.c                     |  21 +-
 nuttx/include/nuttx/binfmt/binfmt.h            |   3 +-
 nuttx/include/unistd.h                         |   7 +
 nuttx/libc/Kconfig                             |  48 +++
 nuttx/libc/unistd/Make.defs                    |   4 +
 nuttx/libc/unistd/lib_execl.c                  | 146 ++++++++
 nuttx/libc/unistd/lib_execv.c                  | 168 +++++++++
 nuttx/tools/cfgdefine.c                        |   1 +
 33 files changed, 3269 insertions(+), 2723 deletions(-)
 create mode 100644 nuttx/arch/arm/include/lm3s/chip.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h
 create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_epi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ethernet.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_flash.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpio.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_i2c.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ssi.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_timer.h
 delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_uart.h
 create mode 100644 nuttx/libc/unistd/lib_execl.c
 create mode 100644 nuttx/libc/unistd/lib_execv.c

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index e2d8a586b..ee6b088cf 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -3880,4 +3880,16 @@
 	  OS layered architecture.
 	* include/unistd.h, arch/arch/src/*:  Implement a simple vfork().
 	  On initial checkin, this API is available only for ARM platforms.
+	* binfmt/binfmt_exec.c: exec() now sets the priority of the new task
+	  to the same priority as the current task (instead of the arbirtrary
+	  value of 50).
+	* libc/unisted/lib_execv.c and lib_execl.c:  New, somewhat flawed,
+	  implementations of execv() and execl().
+	* tools/cfgdefine.c:  Strips quotes from CONFIG_EXECFUNCS_SYMTAB
+	  value.
+	* arch/arm/include/lm3s/chip.h:  Move chip definitions into
+	  public include area for compatibility with other architectures.
+	* arch/arm/src/lm3s/chip:  Move register definition header files
+	  into a new chip/ sub-directory.
+
 
diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html
index 5c76737e5..918b69d0f 100644
--- a/nuttx/Documentation/NuttxUserGuide.html
+++ b/nuttx/Documentation/NuttxUserGuide.html
@@ -202,6 +202,8 @@ paragraphs.
   
          • 2.1.6 task_restart
            • 
   
          • 2.1.7 getpid
            • 
   
          • 2.1.8 vfork
            • 
+  
          • 2.1.9 execv
            • 
+  
          • 2.1.10 execl
            •

          2.1.1 task_create

          @@ -648,6 +650,9 @@ pid_t vfork(void); Compatible with the Unix interface of the same name.

          +

          2.1.9 execv

          +

          2.1.10 execl

          +
          @@ -6798,6 +6803,12 @@ FAR char *getcwd(FAR char *buf, size_t size); int unlink(FAR const char *pathname); int rmdir(FAR const char *pathname); + +#ifdef CONFIG_LIBC_EXECFUNCS +int execl(FAR const char *path, ...); +int execv(FAR const char *path, FAR char *const argv[]); +#endif + int getopt(int argc, FAR char *const argv[], FAR const char *optstring); @@ -8198,7 +8209,9 @@ notify a task when a message is available on a queue.
        • Driver operations
        • dup
        • dup2
          • +
        • execl
        • eXecute In Place (XIP)
          • +
        • execv
        • exit
        • FAT File System Support
        • fclose
          • @@ -8333,9 +8346,9 @@ notify a task when a message is available on a queue.
        • ROMFS
        • sched_getparam
        • sched_get_priority_max
          • +
        • sched_get_priority_min
          		•  -
        • sched_get_priority_min
        • sched_get_rr_interval
        • sched_lockcount
        • sched_lock
          • diff --git a/nuttx/arch/arm/include/lm3s/chip.h b/nuttx/arch/arm/include/lm3s/chip.h new file mode 100644 index 000000000..d7e98a461 --- /dev/null +++ b/nuttx/arch/arm/include/lm3s/chip.h @@ -0,0 +1,123 @@ +/************************************************************************************ + * arch/arm/include/lm3s/chip.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LM3S_CHIP_H +#define __ARCH_ARM_INCLUDE_LM3S_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 2 /* Two SSI modules */ +# define LM3S_NUARTS 2 /* Two UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 0 /* No PWM generator modules */ +# define LM3S_NQEI 0 /* No quadrature encoders */ +# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define LM3S_NTIMERS 3 /* Three general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 2 /* Two UART modules */ +# define LM3S_NI2C 1 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 1 /* One PWM generator module */ +# define LM3S_NQEI 0 /* No quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 3 /* Three UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 3 /* Three PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 2 /* Two SSI modules */ +# define LM3S_NUARTS 3 /* Three UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 2 /* Two ADC module */ +# define LM3S_CAN 2 /* Two CAN module */ +# define LM3S_NPWM 4 /* Four PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 3 /* Two UART modules */ +# define LM3S_NI2C 2 /* One I2C module */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 3 /* Three PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ +# define LC3S_CANCONTROLLER 1 /* One CAN controller */ +#else +# error "Capabilities not specified for this LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LM3S_CHIP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h index 1e22f6221..1e96b5222 100644 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ b/nuttx/arch/arm/src/lm3s/chip.h @@ -41,83 +41,22 @@ ************************************************************************************/ #include +#include /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 0 /* No PWM generator modules */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM3S_NTIMERS 3 /* Three general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 1 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 1 /* One PWM generator module */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 2 /* Two ADC module */ -# define LM3S_CAN 2 /* Two CAN module */ -# define LM3S_NPWM 4 /* Four PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Two UART modules */ -# define LM3S_NI2C 2 /* One I2C module */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ -# define LC3S_CANCONTROLLER 1 /* One CAN controller */ -#else -# error "Capabilities not specified for this LM3S chip" -#endif - /* Then get all of the register definitions */ -#include "lm3s_memorymap.h" /* Memory map */ -#include "lm3s_syscontrol.h" /* System control module */ -#include "lm3s_gpio.h" /* GPIO modules */ -#include "lm3s_uart.h" /* UART modules */ -#include "lm3s_i2c.h" /* I2C modules */ -#include "lm3s_ssi.h" /* SSI modules */ -#include "lm3s_ethernet.h" /* Ethernet MAC and PHY */ -#include "lm3s_flash.h" /* FLASH */ +#include "chip/lm_memorymap.h" /* Memory map */ +#include "chip/lm3s_syscontrol.h" /* System control module */ +#include "chip/lm3s_gpio.h" /* GPIO modules */ +#include "chip/lm3s_uart.h" /* UART modules */ +#include "chip/lm3s_i2c.h" /* I2C modules */ +#include "chip/lm3s_ssi.h" /* SSI modules */ +#include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ +#include "chip/lm3s_flash.h" /* FLASH */ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h new file mode 100644 index 000000000..5b54d44ac --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_epi.h + * + * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. + * Author: Max Neklyudov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* External Peripheral Interface Register Offsets ***********************************/ + +#define LM3S_EPI_CFG_OFFSET 0x000 +#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 +#define LM3S_EPI_ADDRMAP_OFFSET 0x01C +#define LM3S_EPI_STAT_OFFSET 0x060 +#define LM3S_EPI_BAUD_OFFSET 0x004 + +/* External Peripheral Interface Register Addresses *********************************/ + +#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) +#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) +#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) +#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) +#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) + +/* External Peripheral Interface Register Bit Definitions ***************************/ + +/* EPI Configuration (EPICFG), offset 0x000 */ + +#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ +#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) +# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ + +/* EPI Address Map (EPIADDRMAP), offset 0x01C */ + +#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ +#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) +#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ +#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) + +/* EPI Status (EPISTAT), offset 0x060 */ + +#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ +#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) + +/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ + +#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ +#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) +#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ +#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) +# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) +#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ +#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) + +/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ + +#define EPI_BAUD_COUNT0_SHIFT 0 +#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) +# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h new file mode 100644 index 000000000..940686e7d --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_ethernet.h + * + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Ethernet Controller Register Offsets *********************************************/ + +/* Ethernet MAC Register Offsets */ + +#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ +#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ +#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ +#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ +#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ +#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ +#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ +#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ +#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ +#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ +#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ +#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ +#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ +#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ +#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ +#endif + +/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ + +/* Ethernet Controller Register Addresses *******************************************/ + +#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) +#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) +#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) +#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) +#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) +#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) +#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) +#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) +#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) +#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) +#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) +#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) +#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) +#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) +#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) +#endif + +/* Memory Mapped MII Management Registers */ + +#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) +#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) +#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) +#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) +#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) +#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) +#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) +#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) +#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) +#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) +#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) +#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) +#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) + +/* Ethernet Controller Register Bit Definitions *************************************/ + +/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ + +#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ +#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ +#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ +#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ +#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ +#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ +#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ + +#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ +#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ +#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ +#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ +#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ +#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ +#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ + +/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ + +#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ +#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ +#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ +#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ +#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ +#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ +#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ +#define MAC_IM_ALLINTS 0x7f + +/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ + +#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ +#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ +#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ +#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ +#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ + +/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ + +#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ +#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ +#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ +#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ + +/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ + +#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ + +/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ + +#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ +#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ +#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ +#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) + +/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ + +#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ + +/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ + +#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ + +/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ + +#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ + +/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ + +#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ + +/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ + +#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h new file mode 100644 index 000000000..2bd8956b0 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_flash.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* FLASH register offsets ***********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ +#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ +#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ +#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ +#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ +#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ +#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ +#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ +#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ +#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ +#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ +#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ +#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ +#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ +#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ +#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ +#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ +#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ +#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ + +/* FLASH register addresses *********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) +#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) +#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) +#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) +#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) +#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) +#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) +#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) +#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) +#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) +#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) +#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) +#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) +#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) +#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) +#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) +#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) +#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) +#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) + +/* FLASH register bit defitiions ****************************************************/ +/* To be provided */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h new file mode 100644 index 000000000..7253c1e7a --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h @@ -0,0 +1,395 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ +#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ +#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ +#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ +#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ +#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ +#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ +#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ +#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ +#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ +#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ +#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ +#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ +#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ +#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ +#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ +#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ +#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ +#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ +#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ +#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ +#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ +#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ +#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ +#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ +#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ +#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ +#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ +#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ +#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ +#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ +#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ + +/* GPIO Register Addresses **********************************************************/ + +#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h new file mode 100644 index 000000000..71ebe8fcf --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h @@ -0,0 +1,247 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_i2c.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +/* I2C Master */ + +#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ +#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ +#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ +#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ +#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ +#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ +#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ +#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ +#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ + +/* I2C Slave */ + +#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ +#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ +#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ +#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ +#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ +#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ +#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ + +/* I2C Register Addresses ***********************************************************/ + +#if LM3S_NI2C > 0 + +/* I2C Master */ + +#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) +#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) + +/* I2C Slave */ + +#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) +#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) + +/* I2C0 Master */ + +#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C0 Slave */ + +#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) + +#if LM3S_NI2C > 1 + +/* I2C1 Master */ + +#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C1 Slave */ + +#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) + +#endif +#endif + +/* I2C_Register Bit Definitions *****************************************************/ + +/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ + +#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ +#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ +#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) + +/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ + +#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ +#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ +#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ +#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ +#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ +#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ +#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ + +#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ +#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ +#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ +#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ + +/* I2C Master Data (I2CM_DR), offset 0x008 */ + +#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ + +/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ + +#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ + +/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ + +#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ + +/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ + +#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ + +#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ + +#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Configuration (I2CM_CR), offset 0x020 */ + +#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ +#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ +#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ + +/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ + +#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ + +/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ + +#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ +#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ +#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ + +#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ + +/* I2C Slave Data (I2CS_DR), offset 0x008 */ + +#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ + +/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ + +#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ + +/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ + +#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ + +/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ + +#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ + +/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ + +#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h new file mode 100644 index 000000000..31dc2b249 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h @@ -0,0 +1,360 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_memorymap.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory map ***********************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ + defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0xdfffffff: Reserved */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0x5fffffff: Reserved */ +# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#else +# error "Memory map not specified for this LM3S chip" +#endif + +/* Peripheral base addresses ********************************************************/ +/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt + * peripheral modules. They could probably be combined into one peripheral memory + * map. However, keeping them separate does also provide so early, compile-time + * error detection that makes the duplication worthwhile. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x3fffff: Reserved */ +# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ +# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ +# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ + /* -0x3ffff: Reserved */ +# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ +# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0x49fff: Reserved */ +# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ + /* -0x53fff: Reserved */ +# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ + /* -0x57fff: Reserved */ +# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ +# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ +# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ +# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ +# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ +# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ +# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ +# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ +# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ + /* -0xcffff: Reserved */ +# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ + /* -0xfcfff: Reserved */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ +# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ + /* -0x1ffffff: Reserved */ +#else +# error "Peripheral base addresses not specified for this LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h new file mode 100644 index 000000000..b56ca77cb --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h @@ -0,0 +1,235 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_ssi.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if LM3S_NSSI > 0 + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* SSI register offsets *************************************************************/ + +#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ +#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ +#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ +#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ +#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ +#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ +#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ +#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ +#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ +#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ +#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ +#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ +#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ +#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ +#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ +#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ +#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ +#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ +#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ +#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ +#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ + +/* SSI register addresses ***********************************************************/ + +#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#if LM3S_NSSI > 1 +#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) + +#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) +#endif /* LM3S_NSSI > 1 */ + +/* SSI register bit defitiions ******************************************************/ + +/* SSI Control 0 (SSICR0), offset 0x000 */ + +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ +#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) +#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ +#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ +#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ +#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ +#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ +#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ +#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) + +/* SSI Control 1 (SSICR1), offset 0x004 */ + +#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ +#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ +#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ +#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ + +/* SSI Data (SSIDR), offset 0x008 */ + +#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ + +/* SSI Status (SSISR), offset 0x00c */ + +#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ +#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ +#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ +#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ +#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ + +/* SSI Clock Prescale (SSICPSR), offset 0x010 */ + +#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ + +/* SSI Interrupt Mask (SSIIM), offset 0x014 */ + +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ + +/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ + +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ + +/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ + +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ + +/* SSI Interrupt Clear (SSIICR), offset 0x020 */ + +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ + +/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ + +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ + +/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ + +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* LM3S_NSSI > 0 */ +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h new file mode 100644 index 000000000..d66cfeb47 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h @@ -0,0 +1,495 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System Control Register Offsets **************************************************/ + +#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ +#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ +#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ +#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ +#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ +#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ +#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ +#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ +#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ +#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ +#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ +#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ +#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ +#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ +#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ +#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ +#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ +#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ +#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ +#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ + +/* System Control Register Addresses ************************************************/ + +#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) +#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) +#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) +#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) +#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) +#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) +#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) +#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) +#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) +#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) +#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) +#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) +#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) +#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) +#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) +#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) +#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) +#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) +#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) +#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) +#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) +#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) +#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) +#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) +#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) +#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) +#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) +#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) +#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) + +/* System Control Register Bit Definitions ******************************************/ + +/* Device Identification 0 (DID0), offset 0x000 */ + +#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ +#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) +#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ +#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) +#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ +#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) +#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ +#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) + +/* Device Identification 1 (DID1), offset 0x004 */ + +#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ +#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) +#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) +#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ +#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) +#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ +#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) +#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ +#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) +#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ +#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) +#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ +#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) + +/* Device Capabilities 0 (DC0), offset 0x008 */ + +#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ +#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) +#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ +#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) + +/* Device Capabilities 1 (DC1), offset 0x010 */ + +#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ +#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ +#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ +#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ +#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ +#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ +#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ +#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ +#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ +#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) +#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ +#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ +#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) + +/* Device Capabilities 2 (DC2), offset 0x014 */ + +#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ +#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ +#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ +#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ +#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ +#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ +#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ +#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ +#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ +#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ +#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ +#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ + +/* Device Capabilities 3 (DC3), offset 0x018 */ + +#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ +#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ +#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ +#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ +#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ +#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ +#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ +#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ +#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ +#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ +#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ +#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ +#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ +#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ +#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ +#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ +#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ +#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ +#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ +#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ + +/* Device Capabilities 4 (DC4), offset 0x01c */ + +#define SYSCON_DC4_GPIO(n) (1 << (n)) +#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ +#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ +#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ +#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ +#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ +#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ +#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ +#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ +#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ +#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ + +/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ + +#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ + +/* LDO Power Control (LDOPCTL), offset 0x034 */ + +#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ +#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) +# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ +# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ +# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ +# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ +# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ +# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ +# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ +# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ +# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ +# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ +# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ + +/* Software Reset Control 0 (SRCR0), offset 0x040 */ + +#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ +#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ +#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ + +/* Software Reset Control 1 (SRCR1), offset 0x044 */ + +#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ +#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ +#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ +#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ +#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ +#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ +#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ +#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ +#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ +#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ +#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ +#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ + +/* Software Reset Control 2 (SRCR2), offset 0x048 */ + +#define SYSCON_SRCR2_GPIO(n) (1 << (n)) +#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ +#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ +#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ +#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ +#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ +#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ +#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ +#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ +#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ +#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ + +/* Raw Interrupt Status (RIS), offset 0x050 */ + +#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ +#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ + +/* Interrupt Mask Control (IMC), offset 0x054 */ + +#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ +#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ + +/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ + +#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ +#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ + +/* Reset Cause (RESC), offset 0x05C */ + +#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ +#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ +#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ +#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ +#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ + +/* Run-Mode Clock Configuration (RCC), offset 0x060 */ + +#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ +#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ +#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ +#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) +# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ +# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ +#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ +#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) +# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ +# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ +# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ +# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ +# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ +# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ +# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ +# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ +# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ +# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ +# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ +# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ +# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B96 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif +#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ +#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ +#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ +#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ +#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) +# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) +#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ + +/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ + +#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ +#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) +#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ +#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) + +/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ + +#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ +#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) +# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ +# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ +# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ +#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ +#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ +#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ +#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) +# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) +#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ + +/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ + +#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) +#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ + +#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ + +#define SYSCON_RCGC2_GPIO(n) (1 << (n)) +#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ + +#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) +#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ + +#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ + +#define SYSCON_SCGC2_GPIO(n) (1 << (n)) +#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ + +#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) +#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ + +#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ + +#define SYSCON_DCGC2_GPIO(n) (1 << (n)) +#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ + +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) +#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ +#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h new file mode 100644 index 000000000..649737f13 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_timer.h + * + * Copyright (C) 2012 Max Nekludov. All rights reserved. + * Author: Max Nekludov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Timer register offsets ***********************************************************/ + +#define TIMER_GPTMCFG_OFFSET 0x000 +#define TIMER_GPTMTAMR_OFFSET 0x004 +#define TIMER_GPTMCTL_OFFSET 0x00C +#define TIMER_GPTMIMR_OFFSET 0x018 +#define TIMER_GPTMRIS_OFFSET 0x01C +#define TIMER_GPTMICR_OFFSET 0x024 +#define TIMER_GPTMTAILR_OFFSET 0x028 +#define TIMER_GPTMTAR_OFFSET 0x048 + +/* SSI register addresses ***********************************************************/ + +#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) + +#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) +#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) +#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) +#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) +#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) +#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) +#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) +#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) + +/* SSI register bit defitiions ******************************************************/ + +/* GPTM Configuration (GPTMCFG), offset 0x000 */ + +#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ +#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) +#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ +#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ +#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ + +/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ + +#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ +#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) +#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ +#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ +#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ +#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ +#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) +#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ +#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ +#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ +#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) +#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ +#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ +#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ +#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) +#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ +#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ +#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ +#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) + +/* GPTM Control (GPTMCTL), offset 0x00C */ + +#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ +#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) +#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ +#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) + +/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ + +#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ +#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) + +/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ + +#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ +#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) + +/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ + +#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ +#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h new file mode 100644 index 000000000..0fef5ccf7 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h @@ -0,0 +1,347 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_uart.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* UART register offsets ************************************************************/ + +#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ +#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ +#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ +#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ +#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ +#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ +#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ +#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ +#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ +#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ +#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ +#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ +#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ +#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ +#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ +#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ +#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ +#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ +#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ +#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ +#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ +#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ +#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ +#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ +#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ +#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ + +/* UART register addresses **********************************************************/ + +#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) + +#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) +#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) +#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) +#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) +#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) +#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) +#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) +#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) +#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) +#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) +#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) +#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) + +/* UART register bit settings *******************************************************/ + +/* UART Data (DR), offset 0x000 */ + +#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ +#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) +#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ +#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ +#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ +#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ + +/* UART Receive Status (RSR), offset 0x004 */ + +#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ +#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ +#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ +#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ + +/* UART Error Clear (ECR), offset 0x004 */ +/* Writing any value to this register clears pending error indications */ + +/* UART Flag (FR), offset 0x018 */ + +#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ +#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ +#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ +#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ +#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ + +/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ + +#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ + +/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ + +#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ + +/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ + +#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ + +/* Register 7: UART Line Control (LCRH), offset 0x02C */ + +#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ +#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ +#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ +#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ +#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ +#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ +#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) +# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ +# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ +# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ +# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ +#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ + +/* UART Control (CTL), offset 0x030 */ + +#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ +#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ +#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ +#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ +#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ +#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ + +/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ + +#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ +#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) +# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ +#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ +#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) +# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ + +/* UART Interrupt Mask (IM), offset 0x038 */ + +#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ +#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ +#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ +#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ +#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ +#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ +#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ + + +/* UART Raw Interrupt Status (RIS), offset 0x03c */ + +#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ +#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ +#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ +#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ +#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ +#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ +#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ + +/* UART Masked Interrupt Status (MIS), offset 0x040 */ + +#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ +#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ +#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ +#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ +#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ +#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ +#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ + +/* UART Interrupt Clear (ICR), offset 0x044 */ + +#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ +#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ +#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ +#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ +#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ +#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ +#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear + */ + +/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ + +#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ + +#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ + +#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ + +#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ + +#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ + +#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ + +#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ + +#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ + +#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ + +/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ + +#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ + +/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ + +#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ + +/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ + +#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h new file mode 100644 index 000000000..c52857847 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_memorymap.h" +#else +# error "Unsupported Stellaris memory map" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/lm3s_epi.h deleted file mode 100644 index 90c9bfb7f..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_epi.h +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_epi.h - * - * Copyright (C) 2009-2012 Max Neklyudov. All rights reserved. - * Author: Max Neklyudov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_EPI_H -#define __ARCH_ARM_SRC_LM3S_LM3S_EPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* External Peripheral Interface Register Offsets ***********************************/ - -#define LM3S_EPI_CFG_OFFSET 0x000 -#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 -#define LM3S_EPI_ADDRMAP_OFFSET 0x01C -#define LM3S_EPI_STAT_OFFSET 0x060 -#define LM3S_EPI_BAUD_OFFSET 0x004 - -/* External Peripheral Interface Register Addresses *********************************/ - -#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) -#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) -#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) -#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) -#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) - -/* External Peripheral Interface Register Bit Definitions ***************************/ - -/* EPI Configuration (EPICFG), offset 0x000 */ - -#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ -#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) -# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ - -/* EPI Address Map (EPIADDRMAP), offset 0x01C */ - -#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ -#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) -#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ -#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) - -/* EPI Status (EPISTAT), offset 0x060 */ - -#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ -#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) - -/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ - -#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ -#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) -#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ -#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) -# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) -#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ -#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) - -/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ - -#define EPI_BAUD_COUNT0_SHIFT 0 -#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) -# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h deleted file mode 100644 index 71833b271..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_ethernet.h - * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H -#define __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Ethernet Controller Register Offsets *********************************************/ - -/* Ethernet MAC Register Offsets */ - -#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ -#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ -#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ -#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ -#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ -#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ -#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ -#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ -#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ -#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ -#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ -#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ -#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ -#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ -#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ -#endif - -/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ - -/* Ethernet Controller Register Addresses *******************************************/ - -#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) -#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) -#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) -#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) -#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) -#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) -#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) -#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) -#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) -#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) -#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) -#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) -#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) -#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) -#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) -#endif - -/* Memory Mapped MII Management Registers */ - -#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) -#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) -#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) -#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) -#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) -#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) -#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) -#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) -#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) -#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) -#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) -#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) -#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) - -/* Ethernet Controller Register Bit Definitions *************************************/ - -/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ - -#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ -#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ -#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ -#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ -#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ -#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ -#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ - -#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ -#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ -#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ -#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ -#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ -#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ -#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ - -/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ - -#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ -#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ -#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ -#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ -#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ -#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ -#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ -#define MAC_IM_ALLINTS 0x7f - -/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ - -#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ -#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ -#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ -#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ -#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ - -/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ - -#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ -#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ -#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ -#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ - -/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ - -#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ - -/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ - -#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ -#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ -#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ -#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) - -/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ - -#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ - -/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ - -#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ - -/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ - -#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ - -/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ - -#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ - -/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ - -#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/lm3s_flash.h deleted file mode 100644 index 83e388921..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_flash.h +++ /dev/null @@ -1,128 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_flash.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H -#define __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* FLASH register offsets ***********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ -#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ -#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ -#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ -#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ -#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ -#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ -#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ -#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ -#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ -#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ -#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ -#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ -#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ -#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ -#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ -#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ -#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ -#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ - -/* FLASH register addresses *********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) -#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) -#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) -#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) -#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) -#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) -#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) -#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) -#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) -#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) -#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) -#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) -#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) -#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) -#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) -#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) -#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) -#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) -#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) - -/* FLASH register bit defitiions ****************************************************/ -/* To be provided */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h deleted file mode 100644 index 066666432..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h +++ /dev/null @@ -1,395 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_gpio.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H -#define __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* GPIO Register Offsets ************************************************************/ - -#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ -#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ -#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ -#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ -#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ -#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ -#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ -#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ -#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ -#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ -#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ -#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ -#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ -#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ -#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ -#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ -#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ -#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ -#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ -#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ -#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ -#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ -#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ -#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ -#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ -#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ -#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ -#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ -#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ -#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ -#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ -#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ - -/* GPIO Register Addresses **********************************************************/ - -#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/lm3s_i2c.h deleted file mode 100644 index a5f0567b9..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h +++ /dev/null @@ -1,247 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_i2c.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_I2C_H -#define __ARCH_ARM_SRC_LM3S_LM3S_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* I2C Register Offsets *************************************************************/ - -/* I2C Master */ - -#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ -#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ -#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ -#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ -#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ -#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ -#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ -#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ -#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ - -/* I2C Slave */ - -#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ -#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ -#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ -#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ -#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ -#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ -#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ - -/* I2C Register Addresses ***********************************************************/ - -#if LM3S_NI2C > 0 - -/* I2C Master */ - -#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) -#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) - -/* I2C Slave */ - -#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) -#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) - -/* I2C0 Master */ - -#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C0 Slave */ - -#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) - -#if LM3S_NI2C > 1 - -/* I2C1 Master */ - -#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C1 Slave */ - -#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) - -#endif -#endif - -/* I2C_Register Bit Definitions *****************************************************/ - -/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ - -#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ -#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ -#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) - -/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ - -#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ -#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ -#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ -#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ -#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ -#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ -#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ - -#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ -#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ -#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ -#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ - -/* I2C Master Data (I2CM_DR), offset 0x008 */ - -#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ - -/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ - -#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ - -/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ - -#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ - -/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ - -#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ - -#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ - -#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Configuration (I2CM_CR), offset 0x020 */ - -#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ -#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ -#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ - -/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ - -#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ - -/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ - -#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ -#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ -#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ - -#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ - -/* I2C Slave Data (I2CS_DR), offset 0x008 */ - -#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ - -/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ - -#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ - -/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ - -#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ - -/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ - -#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ - -/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ - -#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h deleted file mode 100644 index be0d8b58d..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h +++ /dev/null @@ -1,360 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_memorymap.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory map ***********************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ - defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0xdfffffff: Reserved */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0x5fffffff: Reserved */ -# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#else -# error "Memory map not specified for this LM3S chip" -#endif - -/* Peripheral base addresses ********************************************************/ -/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt - * peripheral modules. They could probably be combined into one peripheral memory - * map. However, keeping them separate does also provide so early, compile-time - * error detection that makes the duplication worthwhile. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ - -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x3fffff: Reserved */ -# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ -# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ -# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ - /* -0x3ffff: Reserved */ -# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ -# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0x49fff: Reserved */ -# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ - /* -0x53fff: Reserved */ -# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ - /* -0x57fff: Reserved */ -# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ -# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ -# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ -# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ -# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ -# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ -# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ -# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ -# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ - /* -0xcffff: Reserved */ -# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ - /* -0xfcfff: Reserved */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ -# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ - /* -0x1ffffff: Reserved */ -#else -# error "Peripheral base addresses not specified for this LM3S chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h deleted file mode 100644 index 482dab326..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h +++ /dev/null @@ -1,235 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_ssi.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_SSI_H -#define __ARCH_ARM_SRC_LM3S_LM3S_SSI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#if LM3S_NSSI > 0 - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* SSI register offsets *************************************************************/ - -#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ -#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ -#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ -#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ -#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ -#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ -#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ -#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ -#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ -#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ -#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ -#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ -#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ -#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ -#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ -#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ -#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ -#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ -#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ -#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ -#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ - -/* SSI register addresses ***********************************************************/ - -#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#if LM3S_NSSI > 1 -#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) - -#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) -#endif /* LM3S_NSSI > 1 */ - -/* SSI register bit defitiions ******************************************************/ - -/* SSI Control 0 (SSICR0), offset 0x000 */ - -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ -#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) -#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ -#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ -#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ -#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ -#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ -#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ -#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ -#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) - -/* SSI Control 1 (SSICR1), offset 0x004 */ - -#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ -#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ -#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ -#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ - -/* SSI Data (SSIDR), offset 0x008 */ - -#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ - -/* SSI Status (SSISR), offset 0x00c */ - -#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ -#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ -#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ -#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ -#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ - -/* SSI Clock Prescale (SSICPSR), offset 0x010 */ - -#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ - -/* SSI Interrupt Mask (SSIIM), offset 0x014 */ - -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ - -/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ - -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ - -/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ - -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ - -/* SSI Interrupt Clear (SSIICR), offset 0x020 */ - -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ - -/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ - -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ - -/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ - -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* LM3S_NSSI > 0 */ -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h deleted file mode 100644 index c59b921c4..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h +++ /dev/null @@ -1,495 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_syscontrol.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System Control Register Offsets **************************************************/ - -#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ -#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ -#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ -#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ - -/* System Control Register Addresses ************************************************/ - -#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) -#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) -#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) -#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) -#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) -#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) -#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) -#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) -#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) -#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) -#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) -#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) -#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) -#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) -#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) -#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) -#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) -#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) -#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) -#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) -#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) -#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) -#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) -#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) -#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) -#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) -#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) -#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) -#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) - -/* System Control Register Bit Definitions ******************************************/ - -/* Device Identification 0 (DID0), offset 0x000 */ - -#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ -#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) -#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ -#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) -#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ -#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ -#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) - -/* Device Identification 1 (DID1), offset 0x004 */ - -#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ -#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) -#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ -#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) -#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ -#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) -#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ -#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) -#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ -#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) -#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ -#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) -#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ -#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) - -/* Device Capabilities 0 (DC0), offset 0x008 */ - -#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ -#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) -#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ -#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) - -/* Device Capabilities 1 (DC1), offset 0x010 */ - -#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ -#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ -#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ -#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ -#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ -#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ -#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ -#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ -#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ -#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) -#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ -#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ -#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) - -/* Device Capabilities 2 (DC2), offset 0x014 */ - -#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ -#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ -#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ -#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ -#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ -#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ -#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ -#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ -#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ -#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ -#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ -#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ - -/* Device Capabilities 3 (DC3), offset 0x018 */ - -#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ -#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ -#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ -#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ -#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ -#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ -#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ -#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ -#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ -#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ -#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ -#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ -#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ -#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ -#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ -#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ -#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ -#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ -#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ -#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ - -/* Device Capabilities 4 (DC4), offset 0x01c */ - -#define SYSCON_DC4_GPIO(n) (1 << (n)) -#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ -#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ -#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ -#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ -#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ -#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ -#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ -#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ -#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ -#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ - -/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ - -#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ - -/* LDO Power Control (LDOPCTL), offset 0x034 */ - -#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ -#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) -# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ -# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ -# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ -# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ -# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ -# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ -# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ -# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ -# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ -# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ -# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ - -/* Software Reset Control 0 (SRCR0), offset 0x040 */ - -#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ -#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ -#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ - -/* Software Reset Control 1 (SRCR1), offset 0x044 */ - -#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ -#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ -#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ -#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ -#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ -#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ -#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ -#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ -#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ -#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ -#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ -#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ - -/* Software Reset Control 2 (SRCR2), offset 0x048 */ - -#define SYSCON_SRCR2_GPIO(n) (1 << (n)) -#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ -#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ -#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ -#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ -#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ -#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ -#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ -#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ -#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ -#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ - -/* Raw Interrupt Status (RIS), offset 0x050 */ - -#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ -#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ - -/* Interrupt Mask Control (IMC), offset 0x054 */ - -#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ -#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ - -/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ - -#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ -#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ - -/* Reset Cause (RESC), offset 0x05C */ - -#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ -#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ -#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ -#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ -#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ - -/* Run-Mode Clock Configuration (RCC), offset 0x060 */ - -#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ -#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ -#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ -#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) -# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) -# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ -# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ -# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ -# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ -# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ -# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ -# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ -# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ -# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ -# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ -# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ -# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ -# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ -#ifdef CONFIG_ARCH_CHIP_LM3S9B96 -# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ -# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ -# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ -# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ -# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ -#endif -#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ -#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ -#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ -#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) -# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) -#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ - -/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ - -#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ -#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) -#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ -#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) - -/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ - -#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ -#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) -# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ -# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ -# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ -#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ -#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ -#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) -#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ - -/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ - -#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) -#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ - -#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ - -#define SYSCON_RCGC2_GPIO(n) (1 << (n)) -#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ - -#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) -#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ - -#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ - -#define SYSCON_SCGC2_GPIO(n) (1 << (n)) -#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ - -#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) -#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ - -#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ - -#define SYSCON_DCGC2_GPIO(n) (1 << (n)) -#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ - -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/lm3s_timer.h deleted file mode 100644 index 7c4166293..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_timer.h +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_timer.h - * - * Copyright (C) 2012 Max Nekludov. All rights reserved. - * Author: Max Nekludov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H -#define __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Timer register offsets ***********************************************************/ - -#define TIMER_GPTMCFG_OFFSET 0x000 -#define TIMER_GPTMTAMR_OFFSET 0x004 -#define TIMER_GPTMCTL_OFFSET 0x00C -#define TIMER_GPTMIMR_OFFSET 0x018 -#define TIMER_GPTMRIS_OFFSET 0x01C -#define TIMER_GPTMICR_OFFSET 0x024 -#define TIMER_GPTMTAILR_OFFSET 0x028 -#define TIMER_GPTMTAR_OFFSET 0x048 - -/* SSI register addresses ***********************************************************/ - -#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) - -#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) -#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) -#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) -#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) -#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) -#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) -#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) -#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) - -/* SSI register bit defitiions ******************************************************/ - -/* GPTM Configuration (GPTMCFG), offset 0x000 */ - -#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ -#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) -#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ -#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ -#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ - -/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ - -#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ -#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) -#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ -#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ -#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ -#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ -#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) -#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ -#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ -#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ -#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) -#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ -#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ -#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ -#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) -#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ -#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ -#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ -#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) - -/* GPTM Control (GPTMCTL), offset 0x00C */ - -#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ -#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) -#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ -#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) - -/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ - -#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ -#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) - -/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ - -#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ -#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) - -/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ - -#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ -#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/lm3s_uart.h deleted file mode 100644 index 91bfb2266..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_uart.h +++ /dev/null @@ -1,347 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_uart.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_UART_H -#define __ARCH_ARM_SRC_LM3S_LM3S_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* UART register offsets ************************************************************/ - -#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ -#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ -#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ -#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ -#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ -#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ -#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ -#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ -#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ -#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ -#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ -#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ -#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ -#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ -#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ -#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ -#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ -#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ -#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ -#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ -#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ -#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ -#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ -#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ -#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ -#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ - -/* UART register addresses **********************************************************/ - -#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) - -#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) -#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) -#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) -#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) -#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) -#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) -#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) -#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) -#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) -#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) -#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) -#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) - -/* UART register bit settings *******************************************************/ - -/* UART Data (DR), offset 0x000 */ - -#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ -#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) -#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ -#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ -#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ -#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ - -/* UART Receive Status (RSR), offset 0x004 */ - -#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ -#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ -#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ -#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ - -/* UART Error Clear (ECR), offset 0x004 */ -/* Writing any value to this register clears pending error indications */ - -/* UART Flag (FR), offset 0x018 */ - -#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ -#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ -#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ -#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ -#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ - -/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ - -#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ - -/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ - -#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ - -/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ - -#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ - -/* Register 7: UART Line Control (LCRH), offset 0x02C */ - -#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ -#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ -#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ -#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ -#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ -#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ -#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) -# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ -# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ -# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ -# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ -#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ - -/* UART Control (CTL), offset 0x030 */ - -#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ -#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ -#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ -#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ -#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ -#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ - -/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ - -#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ -#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) -# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ -#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ -#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) -# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ - -/* UART Interrupt Mask (IM), offset 0x038 */ - -#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ -#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ -#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ -#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ -#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ -#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ -#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ - - -/* UART Raw Interrupt Status (RIS), offset 0x03c */ - -#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ -#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ -#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ -#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ -#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ -#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ -#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ - -/* UART Masked Interrupt Status (MIS), offset 0x040 */ - -#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ -#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ -#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ -#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ -#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ -#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ -#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ - -/* UART Interrupt Clear (ICR), offset 0x044 */ - -#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ -#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ -#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ -#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ -#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ -#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ -#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear - */ - -/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ - -#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ - -#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ - -#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ - -#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ - -#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ - -#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ - -#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ - -#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ - -#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ - -/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ - -#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ - -/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ - -#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ - -/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ - -#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_UART_H */ diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c index 60e8d8efd..d5e274710 100644 --- a/nuttx/binfmt/binfmt_exec.c +++ b/nuttx/binfmt/binfmt_exec.c @@ -1,7 +1,7 @@ /**************************************************************************** * binfmt/binfmt_exec.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -75,7 +75,8 @@ * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. + * one call. The priority of the executed program is set to be the + * same as the priority of the calling thread. * * Input Parameter: * filename - Fulll path to the binary to be loaded @@ -94,8 +95,20 @@ int exec(FAR const char *filename, FAR const char **argv, FAR const struct symtab_s *exports, int nexports) { struct binary_s bin; + struct sched_param param; int ret; + /* Get the priority of this thread */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + bdbg("ERROR: sched_getparam failed: %d\n", errno); + return ERROR; + } + + /* Load the module into memory */ + memset(&bin, 0, sizeof(struct binary_s)); bin.filename = filename; bin.exports = exports; @@ -108,7 +121,9 @@ int exec(FAR const char *filename, FAR const char **argv, return ERROR; } - ret = exec_module(&bin, 50); + /* Then start the module at the priority of this thread */ + + ret = exec_module(&bin, param.sched_priority); if (ret < 0) { bdbg("ERROR: Failed to execute program '%s'\n", filename); diff --git a/nuttx/include/nuttx/binfmt/binfmt.h b/nuttx/include/nuttx/binfmt/binfmt.h index 6df5190d2..480e82c09 100644 --- a/nuttx/include/nuttx/binfmt/binfmt.h +++ b/nuttx/include/nuttx/binfmt/binfmt.h @@ -228,7 +228,8 @@ int exec_module(FAR const struct binary_s *bin, int priority); * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. + * one call. The priority of the executed program is set to be the + * same as the priority of the calling thread. * * Input Parameter: * filename - Fulll path to the binary to be loaded diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h index ddb6880f4..d2ace79fa 100644 --- a/nuttx/include/unistd.h +++ b/nuttx/include/unistd.h @@ -160,6 +160,13 @@ EXTERN FAR char *getcwd(FAR char *buf, size_t size); EXTERN int unlink(FAR const char *pathname); EXTERN int rmdir(FAR const char *pathname); +/* Execution of programs from files */ + +#ifdef CONFIG_LIBC_EXECFUNCS +EXTERN int execl(FAR const char *path, ...); +EXTERN int execv(FAR const char *path, FAR char *const argv[]); +#endif + /* Other */ EXTERN int getopt(int argc, FAR char *const argv[], FAR const char *optstring); diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index 0ae56ac57..699b3ebb2 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -71,6 +71,54 @@ config EOL_IS_EITHER_CRLF endchoice +config LIBC_EXECFUNCS + bool "Enable exec[l|v] Support" + default n + depends on !BINFMT_DISABLE + ---help--- + Enable support for the exec[l|v] family of functions that can be + used to start other programs, terminating the current program. + Typical usage is (1) first call vfork() to create a new thread, then + (2) call exec[l|v] to replace the new thread with a program from the + file system. + + NOTE 1: This two step process start is completely unnecessary in + NuttX and is provided only for compatibily with Unix systems. These + functions are essentially just wrapper functions that (1) call the + non-standard binfmt function 'exec', and then (2) exit(0). Since + the new thread will be terminated by the exec[l|v] call, it really + served no purpose other than to suport Unix compatility. + + NOTE 2: Support for exec[l|v] is conditional because is requires + additional support for symbol tables that will not be available in + the typical system. + +if LIBC_EXECFUNCS + +config EXECFUNCS_SYMTAB + string "Symbol table used by exec[l|v]" + default "g_symtab" + ---help--- + The exec[l|v] functions are wrapper functions that (1) call the non- + standard binfmt function 'exec', and then (2) exit(0). The binfmt + function 'exec' needs to have (1) a symbol table that provides the + list of symbols exported by the base code, and (2) the number of + symbols in that table. This selection provides the name of that + symbol table. + +config EXECFUNCS_NSYMBOLS + int "Number of Symbols in the Table" + default 0 + ---help--- + The exec[l|v] functions are wrapper functions that (1) call the non- + standard binfmt function 'exec', and then (2) exit(0). The binfmt + function 'exec' needs to have (1) a symbol table that provides the + list of symbols exported by the base code, and (2) the number of + symbols in that table. This selection provides the number of + symbols in the symbol table. + +endif + config LIBC_STRERROR bool "Enable strerror" default n diff --git a/nuttx/libc/unistd/Make.defs b/nuttx/libc/unistd/Make.defs index 67fce9b1d..3811673bf 100644 --- a/nuttx/libc/unistd/Make.defs +++ b/nuttx/libc/unistd/Make.defs @@ -41,6 +41,10 @@ ifneq ($(CONFIG_NFILE_DESCRIPTORS),0) ifneq ($(CONFIG_DISABLE_ENVIRON),y) CSRCS += lib_chdir.c lib_getcwd.c endif + +ifeq ($(CONFIG_LIBC_EXECFUNCS),y) +CSRCS += lib_execl.c lib_execv.c +endif endif # Add the unistd directory to the build diff --git a/nuttx/libc/unistd/lib_execl.c b/nuttx/libc/unistd/lib_execl.c new file mode 100644 index 000000000..ac3147343 --- /dev/null +++ b/nuttx/libc/unistd/lib_execl.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * libc/unistd/lib_execl.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_LIBC_EXECFUNCS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: execl + * + * Description: + * The standard 'exec' family of functions will replace the current process + * image with a new process image. The new image will be constructed from a + * regular, executable file called the new process image file. There will + * be no return from a successful exec, because the calling process image + * is overlaid by the new process image. + * + * Simplified 'execl()' and 'execv()' functions are provided by NuttX for + * compatibility. NuttX is a tiny embedded RTOS that does not support + * processes and hence the concept of overlaying a tasks process image with + * a new process image does not make any sense. In NuttX, these functions + * are wrapper functions that: + * + * 1. Call the non-standard binfmt function 'exec', and then + * 2. exit(0). + * + * Note the inefficiency when 'exec[l|v]()' is called in the normal, two- + * step process: (1) first call vfork() to create a new thread, then (2) + * call 'exec[l|v]()' to replace the new thread with a program from the + * file system. Since the new thread will be terminated by the + * 'exec[l|v]()' call, it really served no purpose other than to suport + * Unix compatility. + * + * The non-standard binfmt function 'exec()' needs to have (1) a symbol + * table that provides the list of symbols exported by the base code, and + * (2) the number of symbols in that table. This information is currently + * provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings: + * + * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] Support + * CONFIG_EXECFUNCS_SYMTAB : Symbol table used by exec[l|v] + * CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table + * + * As a result of the above, the current implementations of 'execl()' and + * 'execv()' suffer from some incompatibilities that may or may not be + * addressed in a future version of NuttX. Other than just being an + * inefficient use of MCU resource, the most serious of these is that + * the exec'ed task will not have the same task ID as the vfork'ed + * function. So the parent function cannot know the ID of the exec'ed + * task. + * + * Input Parameters: + * path - The path to the program to be executed. If CONFIG_BINFMT_EXEPATH + * is defined in the configuration, then this may be a relative path + * from the current working directory. Otherwise, path must be the + * absolute path to the program. + * arg0,... - A list of the string arguments to be recevied by the + * program. Zero indicates the end of the list. + * + * Returned Value: + * This function does not return on success. On failure, it will return + * -1 (ERROR) and will set the 'errno' value appropriately. + * + ****************************************************************************/ + +int execl(FAR const char *path, ...) +{ + FAR char *argv[CONFIG_MAX_TASK_ARGS+1]; + va_list ap; + int argc; + + /* Collect the arguments into the argv[] array */ + + va_start(ap, path); + for (argc = 0; argc < CONFIG_MAX_TASK_ARGS; argc++) + { + argv[argc] = va_arg(ap, FAR char *); + if (argv[argc] == NULL) + { + break; + } + } + + argv[CONFIG_MAX_TASK_ARGS] = NULL; + va_end(ap); + + /* Then let execv() do the real work */ + + return execv(path, (char * const *)&argv); +} + +#endif /* CONFIG_LIBC_EXECFUNCS */ \ No newline at end of file diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c new file mode 100644 index 000000000..cad8ee307 --- /dev/null +++ b/nuttx/libc/unistd/lib_execv.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * libc/unistd/lib_execv.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_LIBC_EXECFUNCS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* If CONFIG_LIBC_EXECFUNCS is defined in the configuration, then the + * following must also be defined: + */ + +/* Symbol table used by exec[l|v] */ + +#ifndef CONFIG_EXECFUNCS_SYMTAB +# error "CONFIG_EXECFUNCS_SYMTAB must be defined" +#endif + +/* Number of Symbols in the Table */ + +#ifndef CONFIG_EXECFUNCS_NSYMBOLS +# error "CONFIG_EXECFUNCS_NSYMBOLS must be defined" +#endif + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: execv + * + * Description: + * The standard 'exec' family of functions will replace the current process + * image with a new process image. The new image will be constructed from a + * regular, executable file called the new process image file. There will + * be no return from a successful exec, because the calling process image + * is overlaid by the new process image. + * + * Simplified 'execl()' and 'execv()' functions are provided by NuttX for + * compatibility. NuttX is a tiny embedded RTOS that does not support + * processes and hence the concept of overlaying a tasks process image with + * a new process image does not make any sense. In NuttX, these functions + * are wrapper functions that: + * + * 1. Call the non-standard binfmt function 'exec', and then + * 2. exit(0). + * + * Note the inefficiency when 'exec[l|v]()' is called in the normal, two- + * step process: (1) first call vfork() to create a new thread, then (2) + * call 'exec[l|v]()' to replace the new thread with a program from the + * file system. Since the new thread will be terminated by the + * 'exec[l|v]()' call, it really served no purpose other than to suport + * Unix compatility. + * + * The non-standard binfmt function 'exec()' needs to have (1) a symbol + * table that provides the list of symbols exported by the base code, and + * (2) the number of symbols in that table. This information is currently + * provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings: + * + * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] Support + * CONFIG_EXECFUNCS_SYMTAB : Symbol table used by exec[l|v] + * CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table + * + * As a result of the above, the current implementations of 'execl()' and + * 'execv()' suffer from some incompatibilities that may or may not be + * addressed in a future version of NuttX. Other than just being an + * inefficient use of MCU resource, the most serious of these is that + * the exec'ed task will not have the same task ID as the vfork'ed + * function. So the parent function cannot know the ID of the exec'ed + * task. + * + * Input Parameters: + * path - The path to the program to be executed. If CONFIG_BINFMT_EXEPATH + * is defined in the configuration, then this may be a relative path + * from the current working directory. Otherwise, path must be the + * absolute path to the program. + * argv - A pointer to an array of string arguments. The end of the + * array is indicated with a NULL entry. + * + * Returned Value: + * This function does not return on success. On failure, it will return + * -1 (ERROR) and will set the 'errno' value appropriately. + * + ****************************************************************************/ + +int execv(FAR const char *path, FAR char *const argv[]) +{ + int ret; + + /* Start the task */ + + ret = exec(path, (FAR const char **)argv, + &CONFIG_EXECFUNCS_SYMTAB, CONFIG_EXECFUNCS_NSYMBOLS); + + if (ret < 0) + { + sdbg("exec failed: %d\n", errno); + return ERROR; + } + + /* Then exit */ + + exit(0); + + /* We should not get here, but might be needed by some compilers. Other, + * smarter compilers might complain that this code is unreachable. You just + * can't win. + */ + + return ERROR; +} + +#endif /* CONFIG_LIBC_EXECFUNCS */ \ No newline at end of file diff --git a/nuttx/tools/cfgdefine.c b/nuttx/tools/cfgdefine.c index ee1dd4003..f026a186f 100644 --- a/nuttx/tools/cfgdefine.c +++ b/nuttx/tools/cfgdefine.c @@ -64,6 +64,7 @@ static const char *dequote_list[] = /* NuttX */ "CONFIG_USER_ENTRYPOINT", /* Name of entry point function */ + "CONFIG_EXECFUNCS_SYMTAB", /* Symbol table used by exec[l|v] */ /* NxWidgets/NxWM */ -- cgit v1.2.3 From fd45b36c041c0bbb1f9066592482d40790405812 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 8 Jan 2013 16:51:22 +0000 Subject: Documentation update git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5493 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/Documentation/NuttxUserGuide.html | 129 +++++++++++++++++++++++++++++++- nuttx/libc/unistd/lib_execl.c | 8 +- nuttx/libc/unistd/lib_execv.c | 6 +- 3 files changed, 135 insertions(+), 8 deletions(-) diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index 918b69d0f..89bc08942 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

          NuttX Operating System

          User's Manual

          by

          Gregory Nutt

          -

          Last Updated: January 7, 2013

          +

          Last Updated: January 8, 2013
          @@ -651,7 +651,134 @@ pid_t vfork(void);

          2.1.9 execv

          +

          + Function Prototype: +

          + 
            +#include <unistd.h>
+#ifdef CONFIG_LIBC_EXECFUNCS
+int execv(FAR const char *path, FAR char *const argv[]);
+#endif
+
          +

          + Description: + The standard exec family of functions will replace the current process image with a new process image. + The new image will be constructed from a regular, executable file called the new process image file. + There will be no return from a successful exec, because the calling process image is overlaid by the new process image. +

          +

          + Simplified execl() and execv() functions are provided by NuttX for compatibility. + NuttX is a tiny embedded RTOS that does not support processes and hence the concept of overlaying a tasks process image with a new process image does not make any sense. + In NuttX, these functions are wrapper functions that: +

          +
            +
          1. + Call the non-standard binfmt function exec(), and then +
            2. +
          2. + exit(0). +
            3. +
          +

          + Note the inefficiency when execv() or execl() is called in the normal, two-step process: + (1) first call vfork() to create a new thread, then (2) call execv() or execl() to replace the new thread with a program from the file system. + Since the new thread will be terminated by the execv() or execl() call, it really served no purpose other than to support Unix compatility. +

          +

          + The non-standard binfmt function exec() needs to have (1) a symbol table that provides the list of symbols exported by the base code, and (2) the number of symbols in that table. + This information is currently provided to exec() from execv() or execl() via NuttX configuration settings: +

          +
            +
          • + CONFIG_LIBC_EXECFUNCS: + Enable execv() and execl() support +
            • +
          • + CONFIG_EXECFUNCS_SYMTAB: + Symbol table used by execv() or execl(). +
            • +
          • + CONFIG_EXECFUNCS_NSYMBOLS: + Number of symbols in the symbol table +
            • +
          +

          + As a result of the above, the current implementations of execl() and execv() suffer from some incompatibilities that may or may not be addressed in a future version of NuttX. + Other than just being an inefficient use of MCU resource, the most serious of these is that + the exec'ed task will not have the same task ID as the vfork'ed function. + So the parent function cannot know the ID of the exec'ed task.

          +

          + Input Parameters: +

          +
            +
          • + path: + The path to the program to be executed. + If CONFIG_BINFMT_EXEPATH is defined in the configuration, then this may be a relative path from the current working directory. + Otherwise, path must be the absolute path to the program. +
          • +
            • + argv: + A pointer to an array of string arguments. + The end of the array is indicated with a NULL entry. + +
          +

          + Returned Value: + This function does not return on success. + On failure, it will return -1 (ERROR) and will set the errno value appropriately. +

          + Assumptions/Limitations: +

          +

          + POSIX Compatibility: + Similar with the Unix interface of the same name. + There are, however, several compatibility issues as detailed in the description above. +

          +

          2.1.10 execl

          +

          + Function Prototype: +

          + 
            +#include <unistd.h>
+#ifdef CONFIG_LIBC_EXECFUNCS
+int execl(FAR const char *path, ...);
+#endif
+
          +

          + Description: + execl() is functionally equivalent to execv(), differing only in the form of its input parameters. + See the decription of execv() for additional information. +

          +

          + Input Parameters: +

          +
            +
          • + path: + The path to the program to be executed. + If CONFIG_BINFMT_EXEPATH is defined in the configuration, then this may be a relative path from the current working directory. + Otherwise, path must be the absolute path to the program. +
          • +
            • + ...: + A list of the string arguments to be recevied by the program. + Zero indicates the end of the list. + +
          +

          + Returned Value: + This function does not return on success. + On failure, it will return -1 (ERROR) and will set the errno value appropriately. +

          + Assumptions/Limitations: +

          +

          + POSIX Compatibility: + Similar with the Unix interface of the same name. + There are, however, several compatibility issues as detailed in the description of execv(). +

          diff --git a/nuttx/libc/unistd/lib_execl.c b/nuttx/libc/unistd/lib_execl.c index ac3147343..fa50c1429 100644 --- a/nuttx/libc/unistd/lib_execl.c +++ b/nuttx/libc/unistd/lib_execl.c @@ -83,7 +83,7 @@ * step process: (1) first call vfork() to create a new thread, then (2) * call 'exec[l|v]()' to replace the new thread with a program from the * file system. Since the new thread will be terminated by the - * 'exec[l|v]()' call, it really served no purpose other than to suport + * 'exec[l|v]()' call, it really served no purpose other than to support * Unix compatility. * * The non-standard binfmt function 'exec()' needs to have (1) a symbol @@ -91,9 +91,9 @@ * (2) the number of symbols in that table. This information is currently * provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings: * - * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] Support + * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] support * CONFIG_EXECFUNCS_SYMTAB : Symbol table used by exec[l|v] - * CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table + * CONFIG_EXECFUNCS_NSYMBOLS : Number of symbols in the table * * As a result of the above, the current implementations of 'execl()' and * 'execv()' suffer from some incompatibilities that may or may not be @@ -108,7 +108,7 @@ * is defined in the configuration, then this may be a relative path * from the current working directory. Otherwise, path must be the * absolute path to the program. - * arg0,... - A list of the string arguments to be recevied by the + * ... - A list of the string arguments to be recevied by the * program. Zero indicates the end of the list. * * Returned Value: diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c index cad8ee307..b0f4136f1 100644 --- a/nuttx/libc/unistd/lib_execv.c +++ b/nuttx/libc/unistd/lib_execv.c @@ -104,7 +104,7 @@ extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; * step process: (1) first call vfork() to create a new thread, then (2) * call 'exec[l|v]()' to replace the new thread with a program from the * file system. Since the new thread will be terminated by the - * 'exec[l|v]()' call, it really served no purpose other than to suport + * 'exec[l|v]()' call, it really served no purpose other than to support * Unix compatility. * * The non-standard binfmt function 'exec()' needs to have (1) a symbol @@ -112,9 +112,9 @@ extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; * (2) the number of symbols in that table. This information is currently * provided to 'exec()' from 'exec[l|v]()' via NuttX configuration settings: * - * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] Support + * CONFIG_LIBC_EXECFUNCS : Enable exec[l|v] support * CONFIG_EXECFUNCS_SYMTAB : Symbol table used by exec[l|v] - * CONFIG_EXECFUNCS_NSYMBOLS : Number of Symbols in the Table + * CONFIG_EXECFUNCS_NSYMBOLS : Number of symbols in the table * * As a result of the above, the current implementations of 'execl()' and * 'execv()' suffer from some incompatibilities that may or may not be -- cgit v1.2.3 From 23cc9f459cba8e90faf59922616f1c0975b389f3 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 8 Jan 2013 19:27:38 +0000 Subject: Eliminate arch/arc/src/lm3s/lm3s_internal.h; replace with several header files git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5494 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 3 +- nuttx/TODO | 29 +- nuttx/arch/arm/src/arm/Toolchain.defs | 2 +- nuttx/arch/arm/src/lm3s/chip.h | 10 + nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h | 281 +++++++++++ nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h | 69 +++ nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c | 2 +- nuttx/arch/arm/src/lm3s/lm3s_ethernet.c | 4 +- nuttx/arch/arm/src/lm3s/lm3s_gpio.c | 2 +- nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c | 3 +- nuttx/arch/arm/src/lm3s/lm3s_internal.h | 546 --------------------- nuttx/arch/arm/src/lm3s/lm3s_irq.c | 4 +- nuttx/arch/arm/src/lm3s/lm3s_lowputc.c | 5 +- nuttx/arch/arm/src/lm3s/lm3s_ssi.c | 4 +- nuttx/arch/arm/src/lm3s/lm3s_start.c | 4 +- nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c | 3 +- nuttx/arch/arm/src/lm3s/lm3s_timerisr.c | 1 - nuttx/arch/arm/src/lm3s/lm_ethernet.h | 103 ++++ nuttx/arch/arm/src/lm3s/lm_gpio.h | 223 +++++++++ nuttx/arch/arm/src/lm3s/lm_lowputc.h | 87 ++++ nuttx/arch/arm/src/lm3s/lm_ssi.h | 114 +++++ nuttx/arch/arm/src/lm3s/lm_syscontrol.h | 100 ++++ nuttx/configs/eagle100/httpd/defconfig | 1 + nuttx/configs/eagle100/nettest/defconfig | 1 + nuttx/configs/eagle100/nsh/defconfig | 1 + nuttx/configs/eagle100/nxflat/defconfig | 1 + nuttx/configs/eagle100/ostest/defconfig | 1 + nuttx/configs/eagle100/src/eagle100_internal.h | 1 + nuttx/configs/eagle100/src/up_leds.c | 2 +- nuttx/configs/eagle100/src/up_ssi.c | 2 +- nuttx/configs/eagle100/thttpd/defconfig | 1 + nuttx/configs/ekk-lm3s9b96/nsh/defconfig | 1 + nuttx/configs/ekk-lm3s9b96/ostest/defconfig | 1 + .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h | 1 + nuttx/configs/ekk-lm3s9b96/src/up_leds.c | 2 +- nuttx/configs/ekk-lm3s9b96/src/up_ssi.c | 2 +- nuttx/configs/lm3s6432-s2e/nsh/defconfig | 1 + nuttx/configs/lm3s6432-s2e/ostest/defconfig | 1 + .../lm3s6432-s2e/src/lm3s6432s2e_internal.h | 1 + nuttx/configs/lm3s6432-s2e/src/up_boot.c | 2 +- nuttx/configs/lm3s6432-s2e/src/up_leds.c | 2 +- nuttx/configs/lm3s6432-s2e/src/up_ssi.c | 2 +- .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h | 1 + nuttx/configs/lm3s6965-ek/src/up_leds.c | 2 +- nuttx/configs/lm3s6965-ek/src/up_oled.c | 2 +- nuttx/configs/lm3s6965-ek/src/up_ssi.c | 2 +- nuttx/configs/lm3s8962-ek/nsh/defconfig | 1 + nuttx/configs/lm3s8962-ek/nx/defconfig | 1 + nuttx/configs/lm3s8962-ek/ostest/defconfig | 1 + .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h | 1 + nuttx/configs/lm3s8962-ek/src/up_leds.c | 2 +- nuttx/configs/lm3s8962-ek/src/up_oled.c | 2 +- nuttx/configs/lm3s8962-ek/src/up_ssi.c | 2 +- 53 files changed, 1069 insertions(+), 574 deletions(-) create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h create mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_internal.h create mode 100644 nuttx/arch/arm/src/lm3s/lm_ethernet.h create mode 100644 nuttx/arch/arm/src/lm3s/lm_gpio.h create mode 100644 nuttx/arch/arm/src/lm3s/lm_lowputc.h create mode 100644 nuttx/arch/arm/src/lm3s/lm_ssi.h create mode 100644 nuttx/arch/arm/src/lm3s/lm_syscontrol.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index ee6b088cf..edf500df6 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3891,5 +3891,6 @@ public include area for compatibility with other architectures. * arch/arm/src/lm3s/chip: Move register definition header files into a new chip/ sub-directory. - + * arch/arm/src/lm3s/lm3s_internal.h: Broke up into several + smaller header files. diff --git a/nuttx/TODO b/nuttx/TODO index 02100e97e..c0b00d497 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 4, 2013) +NuttX TODO List (Last updated January 8, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (10) Task/Scheduler (sched/) + (11) Task/Scheduler (sched/) (1) Memory Managment (mm/) (2) Signals (sched/, arch/) (2) pthreads (sched/) @@ -31,7 +31,7 @@ nuttx/ (0) ARM/LPC43x (arch/arm/src/lpc43xx/) (3) ARM/STR71x (arch/arm/src/str71x/) (3) ARM/LM3S6918 (arch/arm/src/lm3s/) - (4) ARM/STM32 (arch/arm/src/stm32/) + (5) ARM/STM32 (arch/arm/src/stm32/) (3) AVR (arch/avr) (0) Intel x86 (arch/x86) (5) 8051 / MCS51 (arch/8051/) @@ -171,6 +171,24 @@ o Task/Scheduler (sched/) that includes NxWisges::CNxTimer is needed. Priority: Medium Low for now + Title: INCOMPATIBILITES WITH execv() AND execl() + Description: Simplified 'execl()' and 'execv()' functions are provided by + NuttX. NuttX does not support processes and hence the concept + of overlaying a tasks process image with a new process image + does not make any sense. In NuttX, these functions are + wrapper functions that: + + 1. Call the non-standard binfmt function 'exec', and then + 2. exit(0). + + As a result, the current implementations of 'execl()' and + 'execv()' suffer from some incompatibilities, the most + serious of these is that the exec'ed task will not have + the same task ID as the vfork'ed function. So the parent + function cannot know the ID of the exec'ed task. + Status: Open + Priority: Medium Low for now + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ @@ -1481,6 +1499,11 @@ o ARM/STM32 (arch/arm/src/stm32/) Status: Open Priority: Low + Title: STM32 F4 USB OTG FS DEVICE-SIDE DRIVER + Description: This driver is reported to be buggy and to need some TLC. + Status: Open + Priority: High + o AVR (arch/avr) ^^^^^^^^^^^^^^ diff --git a/nuttx/arch/arm/src/arm/Toolchain.defs b/nuttx/arch/arm/src/arm/Toolchain.defs index ea11c4dc9..daa825842 100644 --- a/nuttx/arch/arm/src/arm/Toolchain.defs +++ b/nuttx/arch/arm/src/arm/Toolchain.defs @@ -102,7 +102,7 @@ endif # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT) -ifeq ($(CONFIG_ARMV_OABI_TOOLCHAIN),y) +ifeq ($(CONFIG_ARM_OABI_TOOLCHAIN),y) CROSSDEV = arm-nuttx-elf- ARCROSSDEV = arm-nuttx-elf- else diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h index 1e96b5222..481a9be15 100644 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ b/nuttx/arch/arm/src/lm3s/chip.h @@ -58,6 +58,16 @@ #include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ #include "chip/lm3s_flash.h" /* FLASH */ +/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism + * will only look at the upper N bits of the 8-bit priority level (where N is 3 for + * the Stellaris family), so any prioritization must be performed in those bits. + * The default priority level is set to the middle value + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h new file mode 100644 index 000000000..62a4a03fd --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h @@ -0,0 +1,281 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm3s_pinmap.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The following lists the input value to lm3s_configgpio to setup the alternate, + * hardware function for each pin. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ +# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ +# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ +#else +# error "Unknown LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h new file mode 100644 index 000000000..b00a6e794 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm3s/chip/lm_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H +#define __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_pinmap.h" +#else +# error "Unsupported Stellaris PIN mapping" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c index 334a3930f..9d205b763 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c @@ -48,7 +48,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c index f7bbedb20..f44b6654f 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c @@ -58,7 +58,9 @@ #include "chip.h" #include "up_arch.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" +#include "lm_ethernet.h" +#include "chip/lm_pinmap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c index c345d113c..dd005fdd1 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "os_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c index 7cc5fea40..511195f2d 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c @@ -50,7 +50,8 @@ #include "up_arch.h" #include "os_internal.h" #include "irq_internal.h" -#include "lm3s_internal.h" + +#include "lm_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h deleted file mode 100644 index 9bfd67a5e..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h +++ /dev/null @@ -1,546 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_internal.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H -#define __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include -#include - -#include "up_internal.h" -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism - * will only look at the upper N bits of the 8-bit priority level (where N is 3 for - * the Stellaris family), so any prioritization must be performed in those bits. - * The default priority level is set to the middle value - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - -/* Bit-encoded input to lm3s_configgpio() *******************************************/ - -/* Encoding: - * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB - * - * These bits set the primary function of the pin: - * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */ -#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */ -#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */ -#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */ -#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */ -#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */ -#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */ -#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */ -#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */ -#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */ -#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */ -#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */ -#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT - -/* That primary may be modified by the following options - * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */ -#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT) -#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */ -#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */ -#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */ -#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */ -#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC - -#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */ -#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) -#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */ -#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */ -#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */ -#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */ -#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */ -#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */ -#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */ - -/* If the pin is an interrupt, then the following options apply - * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */ -#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT) -#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */ -#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */ -#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */ -#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ -#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ - -/* If the pin is an GPIO digital output, then this identifies the initial output value: - * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn - */ - -#define GPIO_VALUE_SHIFT 7 /* Bit 7: If output, inital value of output */ -#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) -#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ -#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ - -/* This identifies the GPIO port - * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn - */ - -#define GPIO_PORT_SHIFT 3 /* Bit 3-6: Port number */ -#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ -#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ -#define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */ - -/* This identifies the bit in the port: - * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB - */ - -#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */ -#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT) - -/* The following lists the input value to lm3s_configgpio to setup the alternate, - * hardware function for each pin. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ - - -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ -# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ -# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ -#else -# error "Unknown LM3S chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: up_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level initialization. - * - ****************************************************************************/ - -EXTERN void up_lowsetup(void); - -/**************************************************************************** - * Name: lm3s_clockconfig - * - * Description: - * Called to change to new clock based on desired rcc and rcc2 settings. - * This is use to set up the initial clocking but can be used later to - * support slow clocked, low power consumption modes. - * - ****************************************************************************/ - -EXTERN void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); - -/**************************************************************************** - * Name: up_clockconfig - * - * Description: - * Called early in the bootsequence (before .data and .bss are available) - * in order to configure initial clocking. - * - ****************************************************************************/ - -EXTERN void up_clockconfig(void); - -/**************************************************************************** - * Name: lm3s_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -EXTERN int lm3s_configgpio(uint32_t cfgset); - -/**************************************************************************** - * Name: lm3s_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -EXTERN void lm3s_gpiowrite(uint32_t pinset, bool value); - -/**************************************************************************** - * Name: lm3s_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -EXTERN bool lm3s_gpioread(uint32_t pinset, bool value); - -/**************************************************************************** - * Function: lm3s_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -EXTERN int lm3s_dumpgpio(uint32_t pinset, const char *msg); - -/**************************************************************************** - * Name: gpio_irqinitialize - * - * Description: - * Initialize all vectors to the unexpected interrupt handler - * - ****************************************************************************/ - -EXTERN int weak_function gpio_irqinitialize(void); - -/**************************************************************************** - * Function: lm3s_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface. If the LM3S chip - * supports multiple Ethernet controllers, then bould specific logic - * must implement up_netinitialize() and call this function to initialize - * the desiresed interfaces. - * - * Parameters: - * None - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -EXTERN int lm3s_ethinitialize(int intf); -#endif - -/**************************************************************************** - * The external functions, lm3s_spiselect, lm3s_spistatus, and - * lm3s_spicmddata must be provided by board-specific logic. These are - * implementations of the select, status, and cmddata methods of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi.h). - * All other methods (including up_spiinitialize()) are provided by common - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide - * the lm3s_spicmddata() function in your board-specific logic. This - * functions will perform cmd/data selection operations using GPIOs in - * the way your board is configured. - * 4. Add a call to up_spiinitialize() in your low level application - * initialization logic - * 5. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -struct spi_dev_s; -enum spi_dev_e; -EXTERN void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -EXTERN uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -EXTERN int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LM3S_LM3S_INTERNAL_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c index aa0ed6c87..2f0b9fa72 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c @@ -51,7 +51,9 @@ #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" -#include "lm3s_internal.h" + +#include "chip.h" +#include "lm_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c index b1cb21b2c..bdbd5a906 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c @@ -46,7 +46,10 @@ #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" +#include "chip/lm_pinmap.h" + +#include "lm_lowputc.h" /************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c index 8d1987992..8cd1cee07 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c @@ -56,7 +56,9 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" +#include "lm_ssi.h" +#include "chip/lm_pinmap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c index f3f762b52..341b82e50 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_start.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_start.c @@ -49,7 +49,9 @@ #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" + +#include "lm_lowputc.h" +#include "lm_syscontrol.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c index e26789d32..3ad0cacb5 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c @@ -49,7 +49,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "chip.h" +#include "lm_syscontrol.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c index 4d42af597..9cd912249 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c @@ -51,7 +51,6 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lm3s/lm_ethernet.h b/nuttx/arch/arm/src/lm3s/lm_ethernet.h new file mode 100644 index 000000000..600955b95 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm_ethernet.h @@ -0,0 +1,103 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm_ethernet.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H +#define __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#if LM3S_NETHCONTROLLERS > 1 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface. If the LM3S chip + * supports multiple Ethernet controllers, then bould specific logic + * must implement up_netinitialize() and call this function to initialize + * the desiresed interfaces. + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int lm3s_ethinitialize(int intf); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* LM3S_NETHCONTROLLERS > 1 */ +#endif /* __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_gpio.h b/nuttx/arch/arm/src/lm3s/lm_gpio.h new file mode 100644 index 000000000..1bfb79fc9 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm_gpio.h @@ -0,0 +1,223 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM_GPIO_H +#define __ARCH_ARM_SRC_LM3S_LM_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit-encoded input to lm3s_configgpio() *******************************************/ + +/* Encoding: + * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB + * + * These bits set the primary function of the pin: + * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */ +#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */ +#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */ +#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */ +#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */ +#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */ +#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */ +#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */ +#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */ +#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */ +#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */ +#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT + +/* That primary may be modified by the following options + * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */ +#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT) +#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */ +#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */ +#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */ +#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */ +#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC + +#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) +#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */ +#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */ +#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */ +#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */ +#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */ +#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */ +#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */ + +/* If the pin is an interrupt, then the following options apply + * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */ +#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT) +#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */ +#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */ +#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */ +#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ +#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ + +/* If the pin is an GPIO digital output, then this identifies the initial output value: + * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn + */ + +#define GPIO_VALUE_SHIFT 7 /* Bit 7: If output, inital value of output */ +#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) +#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ +#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ + +/* This identifies the GPIO port + * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn + */ + +#define GPIO_PORT_SHIFT 3 /* Bit 3-6: Port number */ +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ +#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ +#define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */ + +/* This identifies the bit in the port: + * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB + */ + +#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */ +#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm3s_configgpio(uint32_t cfgset); + +/**************************************************************************** + * Name: lm3s_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lm3s_gpiowrite(uint32_t pinset, bool value); + +/**************************************************************************** + * Name: lm3s_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm3s_gpioread(uint32_t pinset, bool value); + +/**************************************************************************** + * Function: lm3s_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm3s_dumpgpio(uint32_t pinset, const char *msg); + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int weak_function gpio_irqinitialize(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM3S_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_lowputc.h b/nuttx/arch/arm/src/lm3s/lm_lowputc.h new file mode 100644 index 000000000..8e2858ebf --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm_lowputc.h @@ -0,0 +1,87 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm3s_lowputc.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H +#define __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization. + * + ****************************************************************************/ + +void up_lowsetup(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_ssi.h b/nuttx/arch/arm/src/lm3s/lm_ssi.h new file mode 100644 index 000000000..dd1e30817 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm_ssi.h @@ -0,0 +1,114 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm_ssi.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM_SSI_H +#define __ARCH_ARM_SRC_LM3S_LM_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * The external functions, lm3s_spiselect, lm3s_spistatus, and + * lm3s_spicmddata must be provided by board-specific logic. These are + * implementations of the select, status, and cmddata methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All other methods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. These functions will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide + * the lm3s_spicmddata() function in your board-specific logic. This + * functions will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 4. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 5. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM3S_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h new file mode 100644 index 000000000..7c49da565 --- /dev/null +++ b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/src/lm3s/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H */ diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig index 2d8f82180..c2ea86bed 100644 --- a/nuttx/configs/eagle100/httpd/defconfig +++ b/nuttx/configs/eagle100/httpd/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig index fa0740208..2dab94846 100644 --- a/nuttx/configs/eagle100/nettest/defconfig +++ b/nuttx/configs/eagle100/nettest/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig index d8041c299..fd141bc80 100644 --- a/nuttx/configs/eagle100/nsh/defconfig +++ b/nuttx/configs/eagle100/nsh/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig index 756902bb0..20cd50432 100644 --- a/nuttx/configs/eagle100/nxflat/defconfig +++ b/nuttx/configs/eagle100/nxflat/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig index 43c77fe07..01f3be334 100644 --- a/nuttx/configs/eagle100/ostest/defconfig +++ b/nuttx/configs/eagle100/ostest/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h index 88d2bf3b0..d8bcd6a81 100644 --- a/nuttx/configs/eagle100/src/eagle100_internal.h +++ b/nuttx/configs/eagle100/src/eagle100_internal.h @@ -45,6 +45,7 @@ #include #include "chip.h" +#include "lm_gpio.h" /************************************************************************************ * Definitions diff --git a/nuttx/configs/eagle100/src/up_leds.c b/nuttx/configs/eagle100/src/up_leds.c index 59b489c11..0124b964b 100644 --- a/nuttx/configs/eagle100/src/up_leds.c +++ b/nuttx/configs/eagle100/src/up_leds.c @@ -48,7 +48,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "eagle100_internal.h" /**************************************************************************** diff --git a/nuttx/configs/eagle100/src/up_ssi.c b/nuttx/configs/eagle100/src/up_ssi.c index fb5f99df3..b78a0d67c 100644 --- a/nuttx/configs/eagle100/src/up_ssi.c +++ b/nuttx/configs/eagle100/src/up_ssi.c @@ -49,7 +49,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "eagle100_internal.h" /* The Eagle100 microSD CS is on SSI0 */ diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig index dceac0990..460bd64b3 100644 --- a/nuttx/configs/eagle100/thttpd/defconfig +++ b/nuttx/configs/eagle100/thttpd/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" CONFIG_ARCH_BOARD_EAGLE100=y diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig index 82ad3ce5d..d8ae63cff 100644 --- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig @@ -40,6 +40,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S9B96=y CONFIG_ARCH_BOARD="ekk-lm3s9b96" CONFIG_ARCH_BOARD_EKKLM3S9B96=y diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig index bcf2a9426..62a092d1f 100644 --- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig @@ -40,6 +40,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S9B96=y CONFIG_ARCH_BOARD="ekk-lm3s9b96" CONFIG_ARCH_BOARD_EKKLM3S9B96=y diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h index fd8ff3adb..bb3315f5b 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h +++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h @@ -46,6 +46,7 @@ #include #include "chip.h" +#include "lm_gpio.h" /************************************************************************************ * Definitions diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c index 5ed84c2d2..7628fcfe0 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c @@ -49,7 +49,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "ekklm3s9b96_internal.h" /**************************************************************************** diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c index 2fe3b81c8..8f297e7a7 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "ekklm3s9b96_internal.h" #if !defined(CONFIG_SSI0_DISABLE) || !defined(CONFIG_SSI1_DISABLE) diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig index 704d8ad91..7d1657cda 100644 --- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig +++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6432=y CONFIG_ARCH_BOARD="lm3s6432-s2e" CONFIG_ARCH_BOARD_LM3S6432S2E=y diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig index 0be2cfd4c..90357ce7f 100644 --- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig +++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6432=y CONFIG_ARCH_BOARD="lm3s6432-s2e" CONFIG_ARCH_BOARD_LM3S6432S2E=y diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h index bd4cff77f..f54403c7a 100644 --- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h +++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h @@ -44,6 +44,7 @@ #include #include "chip.h" +#include "lm_gpio.h" /************************************************************************************ * Definitions diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c index 5bb7b670f..184529638 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c @@ -47,7 +47,7 @@ #include "up_arch.h" #include "chip.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6432s2e_internal.h" /************************************************************************************ diff --git a/nuttx/configs/lm3s6432-s2e/src/up_leds.c b/nuttx/configs/lm3s6432-s2e/src/up_leds.c index 80fea934f..81610db34 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_leds.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_leds.c @@ -48,7 +48,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6432s2e_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c index d20e1d978..a7844a979 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c @@ -49,7 +49,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6432s2e_internal.h" #if !defined(CONFIG_SSI0_DISABLE) diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h index 621f00148..8ebd4cf65 100644 --- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h +++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h @@ -45,6 +45,7 @@ #include #include "chip.h" +#include "lm_gpio.h" /************************************************************************************ * Definitions diff --git a/nuttx/configs/lm3s6965-ek/src/up_leds.c b/nuttx/configs/lm3s6965-ek/src/up_leds.c index 933c11446..efa1eb738 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_leds.c +++ b/nuttx/configs/lm3s6965-ek/src/up_leds.c @@ -48,7 +48,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6965ek_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lm3s6965-ek/src/up_oled.c b/nuttx/configs/lm3s6965-ek/src/up_oled.c index 586927d53..23ce7e036 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_oled.c +++ b/nuttx/configs/lm3s6965-ek/src/up_oled.c @@ -48,7 +48,7 @@ #include #include -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6965ek_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lm3s6965-ek/src/up_ssi.c b/nuttx/configs/lm3s6965-ek/src/up_ssi.c index 16111fcda..b52116f14 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_ssi.c +++ b/nuttx/configs/lm3s6965-ek/src/up_ssi.c @@ -49,7 +49,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s6965ek_internal.h" /* The LM3S6965 Eval Kit microSD CS is on SSI0 */ diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig index 573ea582e..79f90d5f9 100755 --- a/nuttx/configs/lm3s8962-ek/nsh/defconfig +++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" CONFIG_ARCH_BOARD_LM3S8962EK=y diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig index 30c3b8952..8424b6623 100755 --- a/nuttx/configs/lm3s8962-ek/nx/defconfig +++ b/nuttx/configs/lm3s8962-ek/nx/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" CONFIG_ARCH_BOARD_LM3S8962EK=y diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig index e19cab1cc..73fbff29f 100755 --- a/nuttx/configs/lm3s8962-ek/ostest/defconfig +++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" CONFIG_ARCH_BOARD_LM3S8962EK=y diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h index 3b6175661..689472f15 100644 --- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h +++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h @@ -45,6 +45,7 @@ #include #include "chip.h" +#include "lm_gpio.h" /************************************************************************************ * Definitions diff --git a/nuttx/configs/lm3s8962-ek/src/up_leds.c b/nuttx/configs/lm3s8962-ek/src/up_leds.c index bff920434..d5000d037 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_leds.c +++ b/nuttx/configs/lm3s8962-ek/src/up_leds.c @@ -48,7 +48,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s8962ek_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lm3s8962-ek/src/up_oled.c b/nuttx/configs/lm3s8962-ek/src/up_oled.c index 761187279..3324b3897 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_oled.c +++ b/nuttx/configs/lm3s8962-ek/src/up_oled.c @@ -48,7 +48,7 @@ #include #include -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s8962ek_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lm3s8962-ek/src/up_ssi.c b/nuttx/configs/lm3s8962-ek/src/up_ssi.c index 00e07c85d..7f78b3477 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_ssi.c +++ b/nuttx/configs/lm3s8962-ek/src/up_ssi.c @@ -49,7 +49,7 @@ #include "up_arch.h" #include "chip.h" -#include "lm3s_internal.h" +#include "lm_gpio.h" #include "lm3s8962ek_internal.h" /* The LM3S8962 Eval Kit microSD CS is on SSI0 */ -- cgit v1.2.3 From 3f4d20628887f3d76705262fcbf18315bc31ea18 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 8 Jan 2013 20:56:40 +0000 Subject: Rename arch/arm/src/lm3s to arch/arm/src/lm to allow a namespace that will include the lm4f git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5495 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 3 + nuttx/TODO | 4 +- nuttx/arch/README.txt | 12 +- nuttx/arch/arm/Kconfig | 9 +- nuttx/arch/arm/include/lm/chip.h | 123 ++ nuttx/arch/arm/include/lm/irq.h | 497 ++++++ nuttx/arch/arm/include/lm3s/chip.h | 123 -- nuttx/arch/arm/include/lm3s/irq.h | 497 ------ nuttx/arch/arm/src/lm/Kconfig | 217 +++ nuttx/arch/arm/src/lm/Make.defs | 64 + nuttx/arch/arm/src/lm/chip.h | 83 + nuttx/arch/arm/src/lm/chip/lm3s_epi.h | 113 ++ nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h | 203 +++ nuttx/arch/arm/src/lm/chip/lm3s_flash.h | 128 ++ nuttx/arch/arm/src/lm/chip/lm3s_gpio.h | 395 +++++ nuttx/arch/arm/src/lm/chip/lm3s_i2c.h | 247 +++ nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h | 360 +++++ nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h | 281 ++++ nuttx/arch/arm/src/lm/chip/lm3s_ssi.h | 235 +++ nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h | 495 ++++++ nuttx/arch/arm/src/lm/chip/lm3s_timer.h | 125 ++ nuttx/arch/arm/src/lm/chip/lm3s_uart.h | 347 +++++ nuttx/arch/arm/src/lm/chip/lm_memorymap.h | 69 + nuttx/arch/arm/src/lm/chip/lm_pinmap.h | 69 + nuttx/arch/arm/src/lm/lm3s_dumpgpio.c | 167 +++ nuttx/arch/arm/src/lm/lm3s_ethernet.c | 1472 ++++++++++++++++++ nuttx/arch/arm/src/lm/lm3s_gpio.c | 854 +++++++++++ nuttx/arch/arm/src/lm/lm3s_gpioirq.c | 434 ++++++ nuttx/arch/arm/src/lm/lm3s_irq.c | 458 ++++++ nuttx/arch/arm/src/lm/lm3s_lowputc.c | 309 ++++ nuttx/arch/arm/src/lm/lm3s_serial.c | 1064 +++++++++++++ nuttx/arch/arm/src/lm/lm3s_ssi.c | 1580 ++++++++++++++++++++ nuttx/arch/arm/src/lm/lm3s_start.c | 154 ++ nuttx/arch/arm/src/lm/lm3s_syscontrol.c | 315 ++++ nuttx/arch/arm/src/lm/lm3s_timerisr.c | 142 ++ nuttx/arch/arm/src/lm/lm3s_vectors.S | 805 ++++++++++ nuttx/arch/arm/src/lm/lm_ethernet.h | 103 ++ nuttx/arch/arm/src/lm/lm_gpio.h | 223 +++ nuttx/arch/arm/src/lm/lm_lowputc.h | 87 ++ nuttx/arch/arm/src/lm/lm_ssi.h | 114 ++ nuttx/arch/arm/src/lm/lm_syscontrol.h | 100 ++ nuttx/arch/arm/src/lm3s/Kconfig | 199 --- nuttx/arch/arm/src/lm3s/Make.defs | 64 - nuttx/arch/arm/src/lm3s/chip.h | 83 - nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h | 113 -- nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h | 203 --- nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h | 128 -- nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h | 395 ----- nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h | 247 --- nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h | 360 ----- nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h | 281 ---- nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h | 235 --- nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h | 495 ------ nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h | 125 -- nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h | 347 ----- nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h | 69 - nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h | 69 - nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c | 167 --- nuttx/arch/arm/src/lm3s/lm3s_ethernet.c | 1472 ------------------ nuttx/arch/arm/src/lm3s/lm3s_gpio.c | 854 ----------- nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c | 434 ------ nuttx/arch/arm/src/lm3s/lm3s_irq.c | 458 ------ nuttx/arch/arm/src/lm3s/lm3s_lowputc.c | 309 ---- nuttx/arch/arm/src/lm3s/lm3s_serial.c | 1064 ------------- nuttx/arch/arm/src/lm3s/lm3s_ssi.c | 1580 -------------------- nuttx/arch/arm/src/lm3s/lm3s_start.c | 154 -- nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c | 315 ---- nuttx/arch/arm/src/lm3s/lm3s_timerisr.c | 142 -- nuttx/arch/arm/src/lm3s/lm3s_vectors.S | 805 ---------- nuttx/arch/arm/src/lm3s/lm_ethernet.h | 103 -- nuttx/arch/arm/src/lm3s/lm_gpio.h | 223 --- nuttx/arch/arm/src/lm3s/lm_lowputc.h | 87 -- nuttx/arch/arm/src/lm3s/lm_ssi.h | 114 -- nuttx/arch/arm/src/lm3s/lm_syscontrol.h | 100 -- nuttx/configs/eagle100/README.txt | 4 +- nuttx/configs/eagle100/httpd/defconfig | 3 +- nuttx/configs/eagle100/nettest/defconfig | 3 +- nuttx/configs/eagle100/nsh/defconfig | 3 +- nuttx/configs/eagle100/nxflat/defconfig | 3 +- nuttx/configs/eagle100/ostest/defconfig | 3 +- nuttx/configs/eagle100/thttpd/defconfig | 3 +- nuttx/configs/ekk-lm3s9b96/README.txt | 8 +- nuttx/configs/ekk-lm3s9b96/nsh/defconfig | 3 +- nuttx/configs/ekk-lm3s9b96/ostest/defconfig | 3 +- .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h | 2 +- nuttx/configs/lm3s6432-s2e/README.txt | 6 +- nuttx/configs/lm3s6432-s2e/nsh/defconfig | 3 +- nuttx/configs/lm3s6432-s2e/ostest/defconfig | 3 +- nuttx/configs/lm3s6965-ek/README.txt | 8 +- nuttx/configs/lm3s6965-ek/nsh/defconfig | 3 +- nuttx/configs/lm3s6965-ek/nx/defconfig | 3 +- nuttx/configs/lm3s6965-ek/ostest/defconfig | 3 +- .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h | 2 +- nuttx/configs/lm3s8962-ek/README.txt | 8 +- nuttx/configs/lm3s8962-ek/nsh/defconfig | 3 +- nuttx/configs/lm3s8962-ek/nx/defconfig | 3 +- nuttx/configs/lm3s8962-ek/ostest/defconfig | 3 +- 97 files changed, 12498 insertions(+), 12462 deletions(-) create mode 100644 nuttx/arch/arm/include/lm/chip.h create mode 100644 nuttx/arch/arm/include/lm/irq.h delete mode 100644 nuttx/arch/arm/include/lm3s/chip.h delete mode 100644 nuttx/arch/arm/include/lm3s/irq.h create mode 100644 nuttx/arch/arm/src/lm/Kconfig create mode 100644 nuttx/arch/arm/src/lm/Make.defs create mode 100644 nuttx/arch/arm/src/lm/chip.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_epi.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_flash.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_timer.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_uart.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_memorymap.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_pinmap.h create mode 100644 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_ethernet.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_gpio.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_gpioirq.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_irq.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_lowputc.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_serial.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_ssi.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_start.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_syscontrol.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_timerisr.c create mode 100644 nuttx/arch/arm/src/lm/lm3s_vectors.S create mode 100644 nuttx/arch/arm/src/lm/lm_ethernet.h create mode 100644 nuttx/arch/arm/src/lm/lm_gpio.h create mode 100644 nuttx/arch/arm/src/lm/lm_lowputc.h create mode 100644 nuttx/arch/arm/src/lm/lm_ssi.h create mode 100644 nuttx/arch/arm/src/lm/lm_syscontrol.h delete mode 100644 nuttx/arch/arm/src/lm3s/Kconfig delete mode 100644 nuttx/arch/arm/src/lm3s/Make.defs delete mode 100644 nuttx/arch/arm/src/lm3s/chip.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h delete mode 100644 nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ethernet.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpio.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_irq.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_lowputc.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_serial.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_ssi.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_start.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_timerisr.c delete mode 100644 nuttx/arch/arm/src/lm3s/lm3s_vectors.S delete mode 100644 nuttx/arch/arm/src/lm3s/lm_ethernet.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm_gpio.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm_lowputc.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm_ssi.h delete mode 100644 nuttx/arch/arm/src/lm3s/lm_syscontrol.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index edf500df6..35bf42253 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3893,4 +3893,7 @@ into a new chip/ sub-directory. * arch/arm/src/lm3s/lm3s_internal.h: Broke up into several smaller header files. + * arch/arm/src/lm: Rename the arch/arm/src/lm3s directory to + arch/arm/src/lm so that is can support other members of the + Stellaris family. diff --git a/nuttx/TODO b/nuttx/TODO index c0b00d497..72eb845bc 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -30,7 +30,7 @@ nuttx/ (2) ARM/LPC313x (arch/arm/src/lpc313x/) (0) ARM/LPC43x (arch/arm/src/lpc43xx/) (3) ARM/STR71x (arch/arm/src/str71x/) - (3) ARM/LM3S6918 (arch/arm/src/lm3s/) + (3) ARM/LM3S6918 (arch/arm/src/lm/) (5) ARM/STM32 (arch/arm/src/stm32/) (3) AVR (arch/avr) (0) Intel x86 (arch/x86) @@ -1409,7 +1409,7 @@ o ARM/STR71x (arch/arm/src/str71x/) Status: Open Priority: Medium -- Will be very high if you do SPI access from multiple threads. -o ARM/LM3S6918 (arch/arm/src/lm3s/) +o ARM/LM3S6918 (arch/arm/src/lm/) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Title: I2C DRIVER diff --git a/nuttx/arch/README.txt b/nuttx/arch/README.txt index 67b99b255..14704aa76 100644 --- a/nuttx/arch/README.txt +++ b/nuttx/arch/README.txt @@ -170,12 +170,12 @@ arch/arm - ARM-based micro-controllers STATUS: This port has stalled because of development tool issues. Coding is complete on the basic port (timer, serial console, SPI). - arch/arm/include/lm3s and arch/arm/src/lm3s - These directories contain support for the Luminary LMS family, particularly - for the LM3S6918. The initial, release of this port was included in NuttX version - 0.4.6. The current port includes timer, serial console, Ethernet, SSI, and microSD - support. There are working configurations the NuttX OS test, to run the NuttShell - (NSH), the NuttX networking test, and the uIP web server. + arch/arm/include/lm and arch/arm/src/lm + These directories contain support for the Luminary LM3S/4F family. The + initial, release of this port was included in NuttX version 0.4.6. The + current port includes timer, serial console, Ethernet, SSI, and microSD + support. There are working configurations the NuttX OS test, to run the + NuttShell (NSH), the NuttX networking test, and the uIP web server. arch/arm/include/lpc214x and arch/arm/src/lpc214x These directories provide support for NXP LPC214x family of diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 4fce8efbf..bc7634695 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -50,9 +50,8 @@ config ARCH_CHIP_KINETIS ---help--- Freescale Kinetis Architectures (ARM Cortex-M4) -config ARCH_CHIP_LM3S +config ARCH_CHIP_LM bool "TI Stellaris" - select ARCH_CORTEXM3 select ARCH_HAVE_MPU select ARCH_IRQPRIO ---help--- @@ -151,7 +150,7 @@ config ARCH_CHIP default "dm320" if ARCH_CHIP_DM320 default "imx" if ARCH_CHIP_IMX default "kinetis" if ARCH_CHIP_KINETIS - default "lm3s" if ARCH_CHIP_LM3S + default "lm" if ARCH_CHIP_LM default "lpc17xx" if ARCH_CHIP_LPC17XX default "lpc214x" if ARCH_CHIP_LPC214X default "lpc2378" if ARCH_CHIP_LPC2378 @@ -274,8 +273,8 @@ endif if ARCH_CHIP_KINETIS source arch/arm/src/kinetis/Kconfig endif -if ARCH_CHIP_LM3S -source arch/arm/src/lm3s/Kconfig +if ARCH_CHIP_LM +source arch/arm/src/lm/Kconfig endif if ARCH_CHIP_LPC17XX source arch/arm/src/lpc17xx/Kconfig diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h new file mode 100644 index 000000000..9eee51922 --- /dev/null +++ b/nuttx/arch/arm/include/lm/chip.h @@ -0,0 +1,123 @@ +/************************************************************************************ + * arch/arm/include/lm/chip.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LM_CHIP_H +#define __ARCH_ARM_INCLUDE_LM_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 2 /* Two SSI modules */ +# define LM3S_NUARTS 2 /* Two UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 0 /* No PWM generator modules */ +# define LM3S_NQEI 0 /* No quadrature encoders */ +# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define LM3S_NTIMERS 3 /* Three general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 2 /* Two UART modules */ +# define LM3S_NI2C 1 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 1 /* One PWM generator module */ +# define LM3S_NQEI 0 /* No quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 3 /* Three UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 3 /* Three PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 2 /* Two SSI modules */ +# define LM3S_NUARTS 3 /* Three UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 2 /* Two ADC module */ +# define LM3S_CAN 2 /* Two CAN module */ +# define LM3S_NPWM 4 /* Four PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LM3S_NSSI 1 /* One SSI module */ +# define LM3S_NUARTS 3 /* Two UART modules */ +# define LM3S_NI2C 2 /* One I2C module */ +# define LM3S_NADC 1 /* One ADC module */ +# define LM2S_NPWM 3 /* Three PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ +# define LC3S_CANCONTROLLER 1 /* One CAN controller */ +#else +# error "Capabilities not specified for this LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LM_CHIP_H */ diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h new file mode 100644 index 000000000..a80517e40 --- /dev/null +++ b/nuttx/arch/arm/include/lm/irq.h @@ -0,0 +1,497 @@ +/************************************************************************************ + * arch/arm/include/lm/irq.h + * + * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H +#define __ARCH_ARM_INCLUDE_LM_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define LM3S_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LM3S_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LM3S_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LM3S_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define LM3S_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + +# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ + /* Vector 25-29: Reserved */ +# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ + /* Vector 49: Reserved */ +# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ + /* Vectors 54-57: Reserved */ +# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ + /* Vector 25: Reserved */ +# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ + /* Vectors 27-29: Reserved */ +# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vectors 48-57: Reserved */ +# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ + /* Vectors 59-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vector 48: Reserved */ +# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ + /* Vector 50: Reserved */ +# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ + /* Vectors 55-57: Reserved */ +# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ +# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ +# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ +# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ +# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM3S_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ +# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ +# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ +# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM3S_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ +# define LM3S_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ + /* Vector 57: Reserved */ +# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ + /* Vector 59: Reserved */ +# define LM3S_IRQ_USB (60) /* Vector 60: USB */ +# define LM3S_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ +# define LM3S_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ +# define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ +# define LM3S_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ +# define LM3S_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ +# define LM3S_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ +# define LM3S_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ +# define LM3S_IRQ_I2S0 (68) /* Vector 68: I2S0 */ +# define LM3S_IRQ_EPI (69) /* Vector 69: EPI */ +# define LM3S_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ + /* Vector 71: Reserved */ +# define NR_IRQS (71) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ + /* Vector 42: Reserved */ + /* Vector 43: Reserved */ +# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vector 48: Reserved */ + /* Vector 49: Reserved */ + /* Vector 50: Reserved */ +# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM3S_IRQ_CAN0 (54) /* Vector 55: CAN0 */ + /* Vectors 56-57: Reserved */ +# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#else +# error "IRQ Numbers not specified for this LM3S chip" +#endif + +/* GPIO IRQs -- Note that support for individual GPIO ports can + * be disabled in order to reduce the size of the implemenation. + */ + +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS +# define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0) +# define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1) +# define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2) +# define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3) +# define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4) +# define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5) +# define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6) +# define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7) +# define _NGPIOAIRQS (NR_IRQS + 8) +#else +# define _NGPIOAIRQS NR_IRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS +# define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0) +# define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1) +# define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2) +# define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3) +# define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4) +# define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5) +# define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6) +# define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7) +# define _NGPIOBIRQS (_NGPIOAIRQS + 8) +#else +# define _NGPIOBIRQS _NGPIOAIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS +# define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0) +# define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1) +# define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2) +# define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3) +# define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4) +# define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5) +# define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6) +# define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7) +# define _NGPIOCIRQS (_NGPIOBIRQS + 8) +#else +# define _NGPIOCIRQS _NGPIOBIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS +# define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0) +# define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1) +# define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2) +# define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3) +# define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4) +# define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5) +# define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6) +# define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7) +# define _NGPIODIRQS (_NGPIOCIRQS + 8) +#else +# define _NGPIODIRQS _NGPIOCIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS +# define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0) +# define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1) +# define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2) +# define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3) +# define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4) +# define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5) +# define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6) +# define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7) +# define _NGPIOEIRQS (_NGPIODIRQS + 8) +#else +# define _NGPIOEIRQS _NGPIODIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS +# define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0) +# define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1) +# define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2) +# define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3) +# define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4) +# define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5) +# define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6) +# define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7) +# define _NGPIOFIRQS (_NGPIOEIRQS + 8) +#else +# define _NGPIOFIRQS _NGPIOEIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS +# define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0) +# define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1) +# define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2) +# define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3) +# define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4) +# define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5) +# define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6) +# define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7) +# define _NGPIOGIRQS (_NGPIOFIRQS + 8) +#else +# define _NGPIOGIRQS _NGPIOFIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS +# define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0) +# define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1) +# define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2) +# define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3) +# define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4) +# define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5) +# define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6) +# define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7) +# define _NGPIOHIRQS (_NGPIOGIRQS + 8) +#else +# define _NGPIOHIRQS _NGPIOGIRQS +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS +# define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0) +# define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1) +# define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2) +# define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3) +# define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4) +# define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5) +# define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6) +# define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7) +# define _NGPIOJIRQS (_NGPIOHIRQS + 8) +#else +# define _NGPIOJIRQS _NGPIOHIRQS +#endif + +#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: gpio_irqattach + * + * Description: + * Attach the interrupt handler 'isr' to the GPIO IRQ 'irq' + * + ****************************************************************************/ + +EXTERN int gpio_irqattach(int irq, xcpt_t isr); +#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL) + +/**************************************************************************** + * Name: gpio_irqenable + * + * Description: + * Enable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +EXTERN void gpio_irqenable(int irq); + +/**************************************************************************** + * Name: gpio_irqdisable + * + * Description: + * Disable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +EXTERN void gpio_irqdisable(int irq); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */ + diff --git a/nuttx/arch/arm/include/lm3s/chip.h b/nuttx/arch/arm/include/lm3s/chip.h deleted file mode 100644 index d7e98a461..000000000 --- a/nuttx/arch/arm/include/lm3s/chip.h +++ /dev/null @@ -1,123 +0,0 @@ -/************************************************************************************ - * arch/arm/include/lm3s/chip.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_LM3S_CHIP_H -#define __ARCH_ARM_INCLUDE_LM3S_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 0 /* No PWM generator modules */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM3S_NTIMERS 3 /* Three general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 1 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 1 /* One PWM generator module */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 2 /* Two ADC module */ -# define LM3S_CAN 2 /* Two CAN module */ -# define LM3S_NPWM 4 /* Four PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Two UART modules */ -# define LM3S_NI2C 2 /* One I2C module */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ -# define LC3S_CANCONTROLLER 1 /* One CAN controller */ -#else -# error "Capabilities not specified for this LM3S chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_LM3S_CHIP_H */ diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h deleted file mode 100644 index 6ffc7dec0..000000000 --- a/nuttx/arch/arm/include/lm3s/irq.h +++ /dev/null @@ -1,497 +0,0 @@ -/************************************************************************************ - * arch/arm/include/lm3s/irq.h - * - * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_LM3S_IRQ_H -#define __ARCH_ARM_INCLUDE_LM3S_IRQ_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in the IRQ - * to handle mapping tables. - */ - -/* Processor Exceptions (vectors 0-15) */ - -#define LM3S_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LM3S_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LM3S_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LM3S_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define LM3S_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25-29: Reserved */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ - /* Vector 49: Reserved */ -# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ - /* Vectors 54-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25: Reserved */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ - /* Vectors 27-29: Reserved */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vectors 48-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vectors 59-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ -# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ - /* Vector 50: Reserved */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ - /* Vectors 55-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ -# define LM3S_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ -# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ -# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM3S_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ -# define LM3S_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ - /* Vector 57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vector 59: Reserved */ -# define LM3S_IRQ_USB (60) /* Vector 60: USB */ -# define LM3S_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ -# define LM3S_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ -# define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ -# define LM3S_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ -# define LM3S_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ -# define LM3S_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ -# define LM3S_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ -# define LM3S_IRQ_I2S0 (68) /* Vector 68: I2S0 */ -# define LM3S_IRQ_EPI (69) /* Vector 69: EPI */ -# define LM3S_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ - /* Vector 71: Reserved */ -# define NR_IRQS (71) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ - /* Vector 42: Reserved */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ - /* Vector 49: Reserved */ - /* Vector 50: Reserved */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM3S_IRQ_CAN0 (54) /* Vector 55: CAN0 */ - /* Vectors 56-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#else -# error "IRQ Numbers not specified for this LM3S chip" -#endif - -/* GPIO IRQs -- Note that support for individual GPIO ports can - * be disabled in order to reduce the size of the implemenation. - */ - -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS -# define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0) -# define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1) -# define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2) -# define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3) -# define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4) -# define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5) -# define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6) -# define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7) -# define _NGPIOAIRQS (NR_IRQS + 8) -#else -# define _NGPIOAIRQS NR_IRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS -# define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0) -# define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1) -# define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2) -# define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3) -# define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4) -# define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5) -# define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6) -# define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7) -# define _NGPIOBIRQS (_NGPIOAIRQS + 8) -#else -# define _NGPIOBIRQS _NGPIOAIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS -# define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0) -# define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1) -# define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2) -# define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3) -# define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4) -# define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5) -# define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6) -# define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7) -# define _NGPIOCIRQS (_NGPIOBIRQS + 8) -#else -# define _NGPIOCIRQS _NGPIOBIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS -# define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0) -# define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1) -# define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2) -# define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3) -# define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4) -# define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5) -# define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6) -# define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7) -# define _NGPIODIRQS (_NGPIOCIRQS + 8) -#else -# define _NGPIODIRQS _NGPIOCIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS -# define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0) -# define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1) -# define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2) -# define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3) -# define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4) -# define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5) -# define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6) -# define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7) -# define _NGPIOEIRQS (_NGPIODIRQS + 8) -#else -# define _NGPIOEIRQS _NGPIODIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS -# define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0) -# define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1) -# define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2) -# define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3) -# define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4) -# define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5) -# define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6) -# define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7) -# define _NGPIOFIRQS (_NGPIOEIRQS + 8) -#else -# define _NGPIOFIRQS _NGPIOEIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS -# define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0) -# define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1) -# define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2) -# define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3) -# define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4) -# define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5) -# define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6) -# define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7) -# define _NGPIOGIRQS (_NGPIOFIRQS + 8) -#else -# define _NGPIOGIRQS _NGPIOFIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS -# define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0) -# define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1) -# define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2) -# define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3) -# define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4) -# define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5) -# define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6) -# define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7) -# define _NGPIOHIRQS (_NGPIOGIRQS + 8) -#else -# define _NGPIOHIRQS _NGPIOGIRQS -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS -# define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0) -# define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1) -# define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2) -# define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3) -# define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4) -# define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5) -# define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6) -# define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7) -# define _NGPIOJIRQS (_NGPIOHIRQS + 8) -#else -# define _NGPIOJIRQS _NGPIOHIRQS -#endif - -#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/**************************************************************************** - * Name: gpio_irqattach - * - * Description: - * Attach the interrupt handler 'isr' to the GPIO IRQ 'irq' - * - ****************************************************************************/ - -EXTERN int gpio_irqattach(int irq, xcpt_t isr); -#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL) - -/**************************************************************************** - * Name: gpio_irqenable - * - * Description: - * Enable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -EXTERN void gpio_irqenable(int irq); - -/**************************************************************************** - * Name: gpio_irqdisable - * - * Description: - * Disable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -EXTERN void gpio_irqdisable(int irq); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_LM3S_IRQ_H */ - diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig new file mode 100644 index 000000000..74d1712f3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/Kconfig @@ -0,0 +1,217 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +comment "Stellaris Configuration Options" + +choice + prompt "Stellaris Chip Selection" + default ARCH_CHIP_LM3S6965 + depends on ARCH_CHIP_LM + +config ARCH_CHIP_LM3S6918 + bool "LM3S6918" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + select LM3S_HAVE_SSI1 + +config ARCH_CHIP_LM3S9B96 + bool "LM3S9B96" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S6432 + bool "LM3S6432" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S6965 + bool "LM3S6965" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S8962 + bool "LM3S8962" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +endchoice + +# Chip families + +config ARCH_CHIP_LM3S + bool + +config ARCH_CHIP_LM4F + bool + +config LM3S_HAVE_SSI1 + bool + +config LM3S_REVA2 + bool "Rev A2" + default n + ---help--- + Some early silicon returned an increase LDO voltage or 2.75V to work + around a PLL bug + +config LM3S_DFU + bool "DFU" + default y + +menu "Select LM3S Peripheral Support" + +config LM3S_UART0 + bool "UART0" + select ARCH_HAVE_UART0 + default n + +config LM3S_UART1 + bool "UART1" + select ARCH_HAVE_UART1 + default n + +config SSI0_DISABLE + bool "Disable SSI0" + default y + +config SSI1_DISABLE + bool "Disable SSI1" + default y + +config LM3S_UART2 + bool "UART2" + select ARCH_HAVE_UART2 + default n + +config LM3S_ETHERNET + bool "LM3S Ethernet" + default n + ---help--- + This must be set (along with NET) to build the LM3S Ethernet driver. + +endmenu + +menu "Disable GPIO Interrupts" + +config LM3S_DISABLE_GPIOA_IRQS + bool "Disable GPIOA IRQs" + default n + +config LM3S_DISABLE_GPIOB_IRQS + bool "Disable GPIOB IRQs" + default n + +config LM3S_DISABLE_GPIOC_IRQS + bool "Disable GPIOC IRQs" + default n + +config LM3S_DISABLE_GPIOD_IRQS + bool "Disable GPIOD IRQs" + default n + +config LM3S_DISABLE_GPIOE_IRQS + bool "Disable GPIOE IRQs" + default n + +config LM3S_DISABLE_GPIOF_IRQS + bool "Disable GPIOF IRQs" + default n + +config LM3S_DISABLE_GPIOG_IRQS + bool "Disable GPIOG IRQs" + default n + +config LM3S_DISABLE_GPIOH_IRQS + bool "Disable GPIOH IRQs" + default n + +config LM3S_DISABLE_GPIOJ_IRQS + bool "Disable GPIOJ IRQs" + default n + +endmenu + +if LM3S_ETHERNET +menu "LM3S Ethernet Configuration" + +config LM3S_ETHLEDS + bool "Ethernet LEDs" + default n + ---help--- + Enable to use Ethernet LEDs on the board. + +config LM3S_BOARDMAC + bool "Board MAC" + default n + ---help--- + If the board-specific logic can provide a MAC address (via + lm3s_ethernetmac()), then this should be selected. + +config LM3S_ETHHDUPLEX + bool "Force Half Duplex" + default n + ---help--- + Set to force half duplex operation + +config LM3S_ETHNOAUTOCRC + bool "Disable auto-CRC" + default n + ---help--- + Set to suppress auto-CRC generation + +config LM3S_ETHNOPAD + bool "Disable Tx Padding" + default n + ---help--- + Set to suppress Tx padding + +config LM3S_MULTICAST + bool "Enable Multicast" + default n + ---help--- + Set to enable multicast frames + +config LM3S_PROMISCUOUS + bool "Enable Promiscuous Mode" + default n + ---help--- + Set to enable promiscuous mode + +config LM3S_TIMESTAMP + bool "Enable Timestamping" + default n + +config LM3S_BADCRC + bool "Enable Bad CRC Rejection" + default n + ---help--- + Set to enable bad CRC rejection. + +config M3S_DUMPPACKET + bool "Dump Packets" + default n + ---help--- + Dump each packet received/sent to the console. + +endmenu +endif + +if !SSI0_DISABLE || !SSI1_DISABLE +menu "LM3S SSI Configuration" + +config SSI_POLLWAIT + bool "Poll Wait (No-Interrupt) Mode" + default y + +config SSI_TXLIMIT + int "Tx Limit" + default 4 + ---help--- + Default of 4 assumes half of the 8 entry FIFO + +endmenu +endif + + diff --git a/nuttx/arch/arm/src/lm/Make.defs b/nuttx/arch/arm/src/lm/Make.defs new file mode 100644 index 000000000..aacbb1c83 --- /dev/null +++ b/nuttx/arch/arm/src/lm/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# arch/arm/src/lm/Make.defs +# +# Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = lm3s_vectors.S + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + vfork.S +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ + up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ + up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \ + up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ + up_releasepending.c up_releasestack.c up_reprioritizertr.c \ + up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \ + up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ + up_vfork.c + +ifeq ($(CONFIG_ARCH_MEMCPY),y) +CMN_ASRCS += up_memcpy.S +endif + +ifeq ($(CONFIG_ELF),y) +CMN_CSRCS += up_elf.c +endif + +CHIP_ASRCS = +CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \ + lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \ + lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c + +ifdef CONFIG_NET +CHIP_CSRCS += lm3s_ethernet.c +endif diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h new file mode 100644 index 000000000..5857b3094 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip.h @@ -0,0 +1,83 @@ +/************************************************************************************ + * arch/arm/src/lm/chip.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_H +#define __ARCH_ARM_SRC_LM_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Then get all of the register definitions */ + +#include "chip/lm_memorymap.h" /* Memory map */ +#include "chip/lm3s_syscontrol.h" /* System control module */ +#include "chip/lm3s_gpio.h" /* GPIO modules */ +#include "chip/lm3s_uart.h" /* UART modules */ +#include "chip/lm3s_i2c.h" /* I2C modules */ +#include "chip/lm3s_ssi.h" /* SSI modules */ +#include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ +#include "chip/lm3s_flash.h" /* FLASH */ + +/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism + * will only look at the upper N bits of the 8-bit priority level (where N is 3 for + * the Stellaris family), so any prioritization must be performed in those bits. + * The default priority level is set to the middle value + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h new file mode 100644 index 000000000..82fc94f4c --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_epi.h + * + * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. + * Author: Max Neklyudov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* External Peripheral Interface Register Offsets ***********************************/ + +#define LM3S_EPI_CFG_OFFSET 0x000 +#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 +#define LM3S_EPI_ADDRMAP_OFFSET 0x01C +#define LM3S_EPI_STAT_OFFSET 0x060 +#define LM3S_EPI_BAUD_OFFSET 0x004 + +/* External Peripheral Interface Register Addresses *********************************/ + +#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) +#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) +#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) +#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) +#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) + +/* External Peripheral Interface Register Bit Definitions ***************************/ + +/* EPI Configuration (EPICFG), offset 0x000 */ + +#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ +#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) +# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ + +/* EPI Address Map (EPIADDRMAP), offset 0x01C */ + +#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ +#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) +#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ +#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) + +/* EPI Status (EPISTAT), offset 0x060 */ + +#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ +#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) + +/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ + +#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ +#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) +#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ +#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) +# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) +#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ +#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) + +/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ + +#define EPI_BAUD_COUNT0_SHIFT 0 +#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) +# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h new file mode 100644 index 000000000..512e96221 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_ethernet.h + * + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Ethernet Controller Register Offsets *********************************************/ + +/* Ethernet MAC Register Offsets */ + +#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ +#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ +#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ +#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ +#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ +#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ +#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ +#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ +#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ +#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ +#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ +#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ +#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ +#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ +#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ +#endif + +/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ + +/* Ethernet Controller Register Addresses *******************************************/ + +#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) +#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) +#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) +#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) +#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) +#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) +#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) +#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) +#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) +#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) +#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) +#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) +#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) +#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) +#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) +#endif + +/* Memory Mapped MII Management Registers */ + +#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) +#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) +#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) +#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) +#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) +#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) +#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) +#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) +#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) +#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) +#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) +#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) +#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) + +/* Ethernet Controller Register Bit Definitions *************************************/ + +/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ + +#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ +#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ +#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ +#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ +#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ +#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ +#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ + +#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ +#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ +#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ +#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ +#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ +#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ +#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ + +/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ + +#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ +#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ +#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ +#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ +#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ +#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ +#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ +#define MAC_IM_ALLINTS 0x7f + +/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ + +#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ +#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ +#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ +#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ +#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ + +/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ + +#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ +#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ +#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ +#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ + +/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ + +#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ + +/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ + +#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ +#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ +#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ +#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) + +/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ + +#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ + +/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ + +#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ + +/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ + +#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ + +/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ + +#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ + +/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ + +#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h new file mode 100644 index 000000000..2f6dc78fa --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_flash.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* FLASH register offsets ***********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ +#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ +#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ +#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ +#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ +#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ +#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ +#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ +#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ +#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ +#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ +#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ +#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ +#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ +#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ +#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ +#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ +#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ +#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ + +/* FLASH register addresses *********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) +#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) +#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) +#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) +#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) +#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) +#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) +#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) +#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) +#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) +#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) +#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) +#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) +#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) +#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) +#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) +#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) +#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) +#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) + +/* FLASH register bit defitiions ****************************************************/ +/* To be provided */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h new file mode 100644 index 000000000..2c199dae9 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h @@ -0,0 +1,395 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ +#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ +#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ +#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ +#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ +#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ +#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ +#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ +#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ +#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ +#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ +#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ +#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ +#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ +#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ +#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ +#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ +#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ +#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ +#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ +#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ +#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ +#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ +#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ +#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ +#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ +#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ +#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ +#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ +#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ +#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ +#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ + +/* GPIO Register Addresses **********************************************************/ + +#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h new file mode 100644 index 000000000..e029c4f3f --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h @@ -0,0 +1,247 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_i2c.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +/* I2C Master */ + +#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ +#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ +#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ +#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ +#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ +#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ +#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ +#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ +#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ + +/* I2C Slave */ + +#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ +#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ +#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ +#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ +#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ +#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ +#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ + +/* I2C Register Addresses ***********************************************************/ + +#if LM3S_NI2C > 0 + +/* I2C Master */ + +#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) +#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) + +/* I2C Slave */ + +#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) +#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) + +/* I2C0 Master */ + +#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C0 Slave */ + +#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) + +#if LM3S_NI2C > 1 + +/* I2C1 Master */ + +#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C1 Slave */ + +#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) + +#endif +#endif + +/* I2C_Register Bit Definitions *****************************************************/ + +/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ + +#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ +#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ +#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) + +/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ + +#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ +#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ +#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ +#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ +#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ +#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ +#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ + +#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ +#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ +#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ +#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ + +/* I2C Master Data (I2CM_DR), offset 0x008 */ + +#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ + +/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ + +#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ + +/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ + +#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ + +/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ + +#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ + +#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ + +#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Configuration (I2CM_CR), offset 0x020 */ + +#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ +#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ +#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ + +/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ + +#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ + +/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ + +#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ +#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ +#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ + +#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ + +/* I2C Slave Data (I2CS_DR), offset 0x008 */ + +#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ + +/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ + +#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ + +/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ + +#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ + +/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ + +#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ + +/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ + +#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h new file mode 100644 index 000000000..51de04a2b --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h @@ -0,0 +1,360 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_memorymap.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory map ***********************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ + defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0xdfffffff: Reserved */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0x5fffffff: Reserved */ +# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#else +# error "Memory map not specified for this LM3S chip" +#endif + +/* Peripheral base addresses ********************************************************/ +/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt + * peripheral modules. They could probably be combined into one peripheral memory + * map. However, keeping them separate does also provide so early, compile-time + * error detection that makes the duplication worthwhile. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x3fffff: Reserved */ +# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ +# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ +# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ + /* -0x3ffff: Reserved */ +# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ +# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0x49fff: Reserved */ +# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ + /* -0x53fff: Reserved */ +# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ + /* -0x57fff: Reserved */ +# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ +# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ +# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ +# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ +# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ +# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ +# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ +# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ +# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ + /* -0xcffff: Reserved */ +# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ + /* -0xfcfff: Reserved */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ +# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ + /* -0x1ffffff: Reserved */ +#else +# error "Peripheral base addresses not specified for this LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h new file mode 100644 index 000000000..85ec1369a --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h @@ -0,0 +1,281 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_pinmap.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The following lists the input value to lm3s_configgpio to setup the alternate, + * hardware function for each pin. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ +# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ +# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ +#else +# error "Unknown LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h new file mode 100644 index 000000000..be5a766e5 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h @@ -0,0 +1,235 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_ssi.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if LM3S_NSSI > 0 + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* SSI register offsets *************************************************************/ + +#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ +#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ +#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ +#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ +#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ +#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ +#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ +#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ +#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ +#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ +#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ +#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ +#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ +#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ +#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ +#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ +#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ +#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ +#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ +#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ +#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ + +/* SSI register addresses ***********************************************************/ + +#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#if LM3S_NSSI > 1 +#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) + +#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) +#endif /* LM3S_NSSI > 1 */ + +/* SSI register bit defitiions ******************************************************/ + +/* SSI Control 0 (SSICR0), offset 0x000 */ + +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ +#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) +#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ +#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ +#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ +#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ +#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ +#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ +#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) + +/* SSI Control 1 (SSICR1), offset 0x004 */ + +#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ +#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ +#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ +#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ + +/* SSI Data (SSIDR), offset 0x008 */ + +#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ + +/* SSI Status (SSISR), offset 0x00c */ + +#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ +#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ +#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ +#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ +#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ + +/* SSI Clock Prescale (SSICPSR), offset 0x010 */ + +#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ + +/* SSI Interrupt Mask (SSIIM), offset 0x014 */ + +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ + +/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ + +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ + +/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ + +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ + +/* SSI Interrupt Clear (SSIICR), offset 0x020 */ + +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ + +/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ + +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ + +/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ + +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* LM3S_NSSI > 0 */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h new file mode 100644 index 000000000..00a222ee3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h @@ -0,0 +1,495 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System Control Register Offsets **************************************************/ + +#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ +#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ +#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ +#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ +#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ +#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ +#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ +#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ +#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ +#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ +#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ +#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ +#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ +#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ +#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ +#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ +#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ +#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ +#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ +#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ + +/* System Control Register Addresses ************************************************/ + +#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) +#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) +#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) +#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) +#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) +#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) +#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) +#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) +#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) +#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) +#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) +#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) +#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) +#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) +#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) +#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) +#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) +#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) +#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) +#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) +#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) +#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) +#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) +#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) +#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) +#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) +#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) +#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) +#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) + +/* System Control Register Bit Definitions ******************************************/ + +/* Device Identification 0 (DID0), offset 0x000 */ + +#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ +#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) +#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ +#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) +#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ +#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) +#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ +#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) + +/* Device Identification 1 (DID1), offset 0x004 */ + +#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ +#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) +#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) +#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ +#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) +#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ +#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) +#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ +#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) +#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ +#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) +#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ +#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) + +/* Device Capabilities 0 (DC0), offset 0x008 */ + +#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ +#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) +#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ +#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) + +/* Device Capabilities 1 (DC1), offset 0x010 */ + +#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ +#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ +#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ +#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ +#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ +#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ +#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ +#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ +#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ +#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) +#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ +#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ +#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) + +/* Device Capabilities 2 (DC2), offset 0x014 */ + +#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ +#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ +#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ +#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ +#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ +#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ +#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ +#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ +#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ +#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ +#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ +#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ + +/* Device Capabilities 3 (DC3), offset 0x018 */ + +#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ +#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ +#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ +#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ +#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ +#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ +#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ +#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ +#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ +#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ +#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ +#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ +#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ +#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ +#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ +#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ +#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ +#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ +#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ +#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ + +/* Device Capabilities 4 (DC4), offset 0x01c */ + +#define SYSCON_DC4_GPIO(n) (1 << (n)) +#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ +#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ +#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ +#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ +#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ +#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ +#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ +#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ +#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ +#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ + +/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ + +#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ + +/* LDO Power Control (LDOPCTL), offset 0x034 */ + +#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ +#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) +# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ +# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ +# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ +# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ +# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ +# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ +# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ +# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ +# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ +# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ +# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ + +/* Software Reset Control 0 (SRCR0), offset 0x040 */ + +#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ +#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ +#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ + +/* Software Reset Control 1 (SRCR1), offset 0x044 */ + +#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ +#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ +#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ +#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ +#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ +#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ +#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ +#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ +#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ +#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ +#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ +#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ + +/* Software Reset Control 2 (SRCR2), offset 0x048 */ + +#define SYSCON_SRCR2_GPIO(n) (1 << (n)) +#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ +#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ +#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ +#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ +#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ +#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ +#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ +#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ +#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ +#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ + +/* Raw Interrupt Status (RIS), offset 0x050 */ + +#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ +#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ + +/* Interrupt Mask Control (IMC), offset 0x054 */ + +#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ +#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ + +/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ + +#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ +#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ + +/* Reset Cause (RESC), offset 0x05C */ + +#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ +#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ +#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ +#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ +#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ + +/* Run-Mode Clock Configuration (RCC), offset 0x060 */ + +#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ +#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ +#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ +#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) +# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ +# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ +#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ +#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) +# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ +# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ +# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ +# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ +# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ +# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ +# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ +# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ +# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ +# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ +# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ +# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ +# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B96 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif +#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ +#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ +#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ +#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ +#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) +# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) +#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ + +/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ + +#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ +#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) +#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ +#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) + +/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ + +#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ +#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) +# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ +# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ +# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ +#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ +#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ +#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ +#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) +# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) +#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ + +/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ + +#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) +#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ + +#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ + +#define SYSCON_RCGC2_GPIO(n) (1 << (n)) +#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ + +#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) +#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ + +#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ + +#define SYSCON_SCGC2_GPIO(n) (1 << (n)) +#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ + +#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) +#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ + +#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ + +#define SYSCON_DCGC2_GPIO(n) (1 << (n)) +#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ + +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) +#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ +#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h new file mode 100644 index 000000000..6be963cc3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_timer.h + * + * Copyright (C) 2012 Max Nekludov. All rights reserved. + * Author: Max Nekludov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Timer register offsets ***********************************************************/ + +#define TIMER_GPTMCFG_OFFSET 0x000 +#define TIMER_GPTMTAMR_OFFSET 0x004 +#define TIMER_GPTMCTL_OFFSET 0x00C +#define TIMER_GPTMIMR_OFFSET 0x018 +#define TIMER_GPTMRIS_OFFSET 0x01C +#define TIMER_GPTMICR_OFFSET 0x024 +#define TIMER_GPTMTAILR_OFFSET 0x028 +#define TIMER_GPTMTAR_OFFSET 0x048 + +/* SSI register addresses ***********************************************************/ + +#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) + +#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) +#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) +#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) +#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) +#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) +#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) +#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) +#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) + +/* SSI register bit defitiions ******************************************************/ + +/* GPTM Configuration (GPTMCFG), offset 0x000 */ + +#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ +#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) +#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ +#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ +#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ + +/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ + +#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ +#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) +#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ +#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ +#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ +#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ +#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) +#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ +#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ +#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ +#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) +#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ +#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ +#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ +#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) +#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ +#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ +#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ +#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) + +/* GPTM Control (GPTMCTL), offset 0x00C */ + +#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ +#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) +#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ +#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) + +/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ + +#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ +#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) + +/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ + +#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ +#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) + +/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ + +#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ +#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h new file mode 100644 index 000000000..98dcbce12 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h @@ -0,0 +1,347 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_uart.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* UART register offsets ************************************************************/ + +#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ +#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ +#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ +#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ +#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ +#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ +#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ +#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ +#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ +#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ +#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ +#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ +#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ +#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ +#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ +#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ +#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ +#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ +#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ +#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ +#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ +#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ +#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ +#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ +#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ +#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ + +/* UART register addresses **********************************************************/ + +#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) + +#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) +#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) +#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) +#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) +#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) +#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) +#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) +#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) +#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) +#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) +#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) +#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) + +/* UART register bit settings *******************************************************/ + +/* UART Data (DR), offset 0x000 */ + +#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ +#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) +#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ +#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ +#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ +#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ + +/* UART Receive Status (RSR), offset 0x004 */ + +#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ +#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ +#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ +#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ + +/* UART Error Clear (ECR), offset 0x004 */ +/* Writing any value to this register clears pending error indications */ + +/* UART Flag (FR), offset 0x018 */ + +#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ +#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ +#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ +#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ +#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ + +/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ + +#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ + +/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ + +#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ + +/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ + +#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ + +/* Register 7: UART Line Control (LCRH), offset 0x02C */ + +#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ +#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ +#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ +#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ +#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ +#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ +#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) +# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ +# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ +# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ +# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ +#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ + +/* UART Control (CTL), offset 0x030 */ + +#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ +#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ +#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ +#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ +#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ +#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ + +/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ + +#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ +#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) +# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ +#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ +#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) +# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ + +/* UART Interrupt Mask (IM), offset 0x038 */ + +#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ +#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ +#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ +#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ +#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ +#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ +#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ + + +/* UART Raw Interrupt Status (RIS), offset 0x03c */ + +#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ +#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ +#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ +#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ +#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ +#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ +#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ + +/* UART Masked Interrupt Status (MIS), offset 0x040 */ + +#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ +#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ +#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ +#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ +#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ +#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ +#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ + +/* UART Interrupt Clear (ICR), offset 0x044 */ + +#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ +#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ +#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ +#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ +#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ +#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ +#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear + */ + +/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ + +#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ + +#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ + +#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ + +#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ + +#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ + +#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ + +#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ + +#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ + +#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ + +/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ + +#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ + +/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ + +#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ + +/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ + +#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h new file mode 100644 index 000000000..530ecdf64 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_memorymap.h" +#else +# error "Unsupported Stellaris memory map" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h new file mode 100644 index 000000000..b8154dd9f --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_pinmap.h" +#else +# error "Unsupported Stellaris PIN mapping" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c new file mode 100644 index 000000000..a84dc59dd --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_dumpgpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* NOTE: this is duplicated in lm3s_gpio.c */ + +#ifdef LM3S_GPIOH_BASE +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#else +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint32_t lm3s_gpiobaseaddress(int port) +{ + return g_gpiobase[port & 7]; +} + +/**************************************************************************** + * Name: lm3s_gpioport + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint8_t lm3s_gpioport(int port) +{ + return g_portchar[port & 7]; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm3s_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t base; + uint32_t rcgc2; + bool enabled; + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + DEBUGASSERT(base != 0); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + rcgc2 = getreg32(LM3S_SYSCON_RCGC2); + enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); + + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + lm3s_gpioport(port), pinset, base, msg); + lldbg(" RCGC2: %08x (%s)\n", + rcgc2, enabled ? "enabled" : "disabled" ); + + /* Don't bother with the rest unless the port is enabled */ + + if (enabled) + { + lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", + getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), + getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); + lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", + getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), + getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); + lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", + getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), + getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), + getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), + getreg32(base + LM3S_GPIO_SLR_OFFSET)); + } + irqrestore(flags); + return OK; +} diff --git a/nuttx/arch/arm/src/lm/lm3s_ethernet.c b/nuttx/arch/arm/src/lm/lm3s_ethernet.c new file mode 100644 index 000000000..f6edab5ae --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_ethernet.c @@ -0,0 +1,1472 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_ethernet.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "lm_gpio.h" +#include "lm_ethernet.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */ + +#ifdef CONFIG_LM3S_ETHHDUPLEX +# define LM3S_DUPLEX_SETBITS 0 +# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX +#else +# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX +# define LM3S_DUPLEX_CLRBITS 0 +#endif + +/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */ + +#ifdef CONFIG_LM3S_ETHNOAUTOCRC +# define LM3S_CRC_SETBITS 0 +# define LM3S_CRC_CLRBITS MAC_TCTL_CRC +#else +# define LM3S_CRC_SETBITS MAC_TCTL_CRC +# define LM3S_CRC_CLRBITS 0 +#endif + +/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */ + +#ifdef CONFIG_LM3S_ETHNOPAD +# define LM3S_PADEN_SETBITS 0 +# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN +#else +# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN +# define LM3S_PADEN_CLRBITS 0 +#endif + +#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) +#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) + +/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */ + +#ifdef CONFIG_LM3S_MULTICAST +# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL +# define LM3S_AMUL_CLRBITS 0 +#else +# define LM3S_AMUL_SETBITS 0 +# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL +#endif + +/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */ + +#ifdef CONFIG_LM3S_PROMISCUOUS +# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS +# define LM3S_PRMS_CLRBITS 0 +#else +# define LM3S_PRMS_SETBITS 0 +# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS +#endif + +/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */ + +#ifdef CONFIG_LM3S_BADCRC +# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC +# define LM3S_BADCRC_CLRBITS 0 +#else +# define LM3S_BADCRC_SETBITS 0 +# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC +#endif + +#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) +#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) + +/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */ + +#ifdef CONFIG_LM3S_DUMPPACKET +# define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) +#else +# define lm3s_dumppacket(m,a,n) +#endif + +/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ + +#define LM3S_WDDELAY (1*CLK_TCK) +#define LM3S_POLLHSEC (1*2) + +/* TX timeout = 1 minute */ + +#define LM3S_TXTIMEOUT (60*CLK_TCK) + +/* This is a helper pointer for accessing the contents of the Ethernet header */ + +#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf) + +#define LM32S_MAX_MDCCLK 2500000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* EMAC statistics (debug only) */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) +struct lm3s_statistics_s +{ + uint32_t rx_int; /* Number of Rx interrupts received */ + uint32_t rx_packets; /* Number of packets received (sum of the following): */ + uint32_t rx_ip; /* Number of Rx IP packets received */ + uint32_t rx_arp; /* Number of Rx ARP packets received */ + uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */ + uint32_t rx_pktsize; /* Number of dropped, too small or too big */ + uint32_t rx_errors; /* Number of Rx errors (reception error) */ + uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */ + uint32_t tx_int; /* Number of Tx interrupts received */ + uint32_t tx_packets; /* Number of Tx packets queued */ + uint32_t tx_errors; /* Number of Tx errors (transmission error)*/ + uint32_t tx_timeouts; /* Number of Tx timeout errors */ +}; +# define EMAC_STAT(priv,name) priv->ld_stat.name++ +#else +# define EMAC_STAT(priv,name) +#endif + +/* The lm3s_driver_s encapsulates all state information for a single hardware + * interface + */ + +struct lm3s_driver_s +{ + /* The following fields would only be necessary on chips that support + * multiple Ethernet controllers. + */ + +#if LM3S_NETHCONTROLLERS > 1 + uint32_t ld_base; /* Ethernet controller base address */ + int ld_irq; /* Ethernet controller IRQ */ +#endif + + bool ld_bifup; /* true:ifup false:ifdown */ + WDOG_ID ld_txpoll; /* TX poll timer */ + WDOG_ID ld_txtimeout; /* TX timeout timer */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + struct lm3s_statistics_s ld_stat; +#endif + + /* This holds the information visible to uIP/NuttX */ + + struct uip_driver_s ld_dev; /* Interface understood by uIP */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Miscellaneous low level helpers */ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); +static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); +#else +static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); +static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); +#endif +static void lm3s_ethreset(struct lm3s_driver_s *priv); +#if 0 /* Not used */ +static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value); +#endif +static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr); + +/* Common TX logic */ + +static int lm3s_transmit(struct lm3s_driver_s *priv); +static int lm3s_uiptxpoll(struct uip_driver_s *dev); + +/* Interrupt handling */ + +static void lm3s_receive(struct lm3s_driver_s *priv); +static void lm3s_txdone(struct lm3s_driver_s *priv); +static int lm3s_interrupt(int irq, FAR void *context); + +/* Watchdog timer expirations */ + +static void lm3s_polltimer(int argc, uint32_t arg, ...); +static void lm3s_txtimeout(int argc, uint32_t arg, ...); + +/* NuttX callback functions */ + +static int lm3s_ifup(struct uip_driver_s *dev); +static int lm3s_ifdown(struct uip_driver_s *dev); +static int lm3s_txavail(struct uip_driver_s *dev); +#ifdef CONFIG_NET_IGMP +static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethin + * + * Description: + * Read a register from the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * + * Returned Value: + * Register value + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) +{ + return getreg32(priv->ld_base + offset); +} +#else +static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) +{ + return getreg32(LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm3s_ethout + * + * Description: + * Write a register to the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * value - The value to write the Ethernet register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->ld_base + offset); +} +#else +static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm3s_ethreset + * + * Description: + * Configure and reset the Ethernet module, leaving it in a disabled state. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_ethreset(struct lm3s_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + +#if LM3S_NETHCONTROLLERS > 1 +# error "If multiple interfaces are supported, this function would have to be redesigned" +#endif + + /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ + + flags = irqsave(); + regval = getreg32(LM3S_SYSCON_RCGC2); + regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); + putreg32(regval, LM3S_SYSCON_RCGC2); + nllvdbg("RCGC2: %08x\n", regval); + + /* Put the Ethernet controller into the reset state */ + + regval = getreg32(LM3S_SYSCON_SRCR2); + regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + + /* Wait just a bit. This is a much longer delay than necessary */ + + up_mdelay(2); + + /* Then take the Ethernet controller out of the reset state */ + + regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + nllvdbg("SRCR2: %08x\n", regval); + + /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ + + up_mdelay(2); + + /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */ + +#ifdef CONFIG_LM3S_ETHLEDS + /* Configure the pins for the peripheral function */ + + lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); + lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); +#endif + + /* Disable all Ethernet controller interrupts */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Clear any pending interrupts (shouldn't be any) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + irqrestore(flags); +} + +/**************************************************************************** + * Function: lm3s_phywrite + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the data to be written */ + + DEBUGASSERT(value < MAC_MTXD_MASK); + lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); + + /* Set up the PHY register address and start the write operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); +} +#endif + +/**************************************************************************** + * Function: lm3s_phyread + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the PHY register address and start the read operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Read and return the PHY data */ + + return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); +} + +/**************************************************************************** + * Function: lm3s_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int lm3s_transmit(struct lm3s_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + int ret = -EBUSY; + + /* Verify that the hardware is ready to send another packet */ + + flags = irqsave(); + if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* Increment statistics */ + + EMAC_STAT(priv, tx_packets); + lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* Transfer the packet into the Tx FIFO. The LS 16-bits of the first + * 32-bit word written to the Tx FIFO contains the Ethernet payload + * data length. That is the full length of the message (d_len) minus + * the size of the Ethernet header (14). + */ + + pktlen = priv->ld_dev.d_len; + nllvdbg("Sending packet, pktlen: %d\n", pktlen); + DEBUGASSERT(pktlen > UIP_LLH_LEN); + + dbuf = priv->ld_dev.d_buf; + regval = (uint32_t)(pktlen - 14); + regval |= ((uint32_t)(*dbuf++) << 16); + regval |= ((uint32_t)(*dbuf++) << 24); + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + + /* Write all of the whole, 32-bit values in the middle of the packet */ + + for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word from the user buffer. Note, the user + * buffer may be un-aligned. + */ + + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); + } + + /* Write the last, partial word in the FIFO */ + + if (bytesleft > 0) + { + /* Write the last word */ + + regval = 0; + switch (bytesleft) + { + case 0: + default: + break; + + case 3: + regval |= ((uint32_t)dbuf[2] << 16); + case 2: + regval |= ((uint32_t)dbuf[1] << 8); + case 1: + regval |= (uint32_t)dbuf[0]; + break; + } + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + } + + /* Activate the transmitter */ + + lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv); + ret = OK; + } + + irqrestore(flags); + return ret; +} + +/**************************************************************************** + * Function: lm3s_uiptxpoll + * + * Description: + * The transmitter is available, check if uIP has any outgoing packets ready + * to send. This is a callback from uip_poll(). uip_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_uiptxpoll(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + int ret = OK; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len); + if (priv->ld_dev.d_len > 0) + { + /* Send the packet. lm3s_transmit() will return zero if the + * packet was successfully handled. + */ + + DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + uip_arp_out(&priv->ld_dev); + ret = lm3s_transmit(priv); + } + + /* If zero is returned, the polling will continue until all connections have + * been examined. + */ + + return ret; +} + +/**************************************************************************** + * Function: lm3s_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_receive(struct lm3s_driver_s *priv) +{ + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + + /* Loop while there are incoming packets to be processed */ + + while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) + { + /* Update statistics */ + + EMAC_STAT(priv, rx_packets); + + /* Copy the data data from the hardware to priv->ld_dev.d_buf. Set + * amount of data in priv->ld_dev.d_len + */ + + dbuf = priv->ld_dev.d_buf; + + /* The packet frame length begins in the LS 16-bits of the first + * word from the FIFO followed by the Ethernet header beginning + * in the MS 16-bits of the first word. + * + * Pick off the packet length from the first word. This packet length + * includes the len/type field (size 2) and the FCS (size 4). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + pktlen = (int)(regval & 0x0000ffff); + nllvdbg("Receiving packet, pktlen: %d\n", pktlen); + + /* Check if the pktlen is valid. It should be large enough to hold + * an Ethernet header and small enough to fit entirely in the I/O + * buffer. Six is subtracted to acount for the 2-byte length/type + * and 4 byte FCS that are not copied into the uIP packet. + */ + + if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6)) + { + int wordlen; + + /* We will have to drop this packet */ + + nlldbg("Bad packet size dropped (%d)\n", pktlen); + EMAC_STAT(priv, rx_pktsize); + + /* The number of bytes and words left to read is pktlen - 4 (including, + * the final, possibly partial word) because we've already read 4 bytes. + */ + + wordlen = (pktlen - 1) >> 2; + + /* Read and discard the remaining words in the FIFO */ + + while (wordlen--) + { + (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Check for another packet */ + + continue; + } + + /* Save the first two bytes from the first word */ + + *dbuf++ = (uint8_t)((regval >> 16) & 0xff); + *dbuf++ = (uint8_t)((regval >> 24) & 0xff); + + /* Read all of the whole, 32-bit values in the middle of the packet. + * We've already read the length (2 bytes) plus the first two bytes + * of data. + */ + + for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word to the user buffer. Note, the user + * buffer may be un-aligned. + */ + + *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Handle the last, partial word in the FIFO (0-3 bytes) and discard + * the 4-byte FCS. + */ + + for (; bytesleft > 0; bytesleft -= 4) + { + /* Read the last word. And transfer all but the last four + * bytes of the FCS into the user buffer. + */ + + regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + switch (bytesleft) + { + default: + break; + + case 7: + dbuf[2] = (regval >> 16) & 0xff; + case 6: + dbuf[1] = (regval >> 8) & 0xff; + case 5: + dbuf[0] = regval & 0xff; + break; + } + } + + /* Pass the packet length to uIP MINUS 2 bytes for the length and + * 4 bytes for the FCS. + */ + + priv->ld_dev.d_len = pktlen - 6; + lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv6 + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6)) +#else + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP)) +#endif + { + nllvdbg("IP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_ip); + + uip_arp_ipin(&priv->ld_dev); + uip_input(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + uip_arp_out(&priv->ld_dev); + lm3s_transmit(priv); + } + } + else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP)) + { + nllvdbg("ARP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_arp); + + uip_arp_arpin(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + lm3s_transmit(priv); + } + } +#ifdef CONFIG_DEBUG + else + { + nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); + EMAC_STAT(priv, rx_dropped); + } +#endif + } +} + +/**************************************************************************** + * Function: lm3s_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_txdone(struct lm3s_driver_s *priv) +{ + /* Cancel the TX timeout */ + + wd_cancel(priv->ld_txtimeout); + + /* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. Since + * we get here because of of TXEMP which indicates that the packet was + * transmitted and that the TX FIFO is empty, NEWTX should always be zero + * at this point. + */ + + DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); +} + +/**************************************************************************** + * Function: lm3s_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_interrupt(int irq, FAR void *context) +{ + register struct lm3s_driver_s *priv; + uint32_t ris; + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate and interface with an IRQ is needed" +#else + priv = &g_lm3sdev[0]; +#endif + + /* Read the raw interrupt status register */ + + ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + + /* Clear all pending interrupts */ + + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); + + /* Check for errors */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + if ((ris & MAC_RIS_TXER) != 0) + { + EMAC_STAT(priv, tx_errors); /* Number of Tx errors */ + } + + if ((ris & MAC_RIS_FOV) != 0) + { + EMAC_STAT(priv, rx_ovrerrors); /* Number of Rx FIFO overrun errors */ + } + + if ((ris & MAC_RIS_RXER) != 0) + { + EMAC_STAT(priv, rx_errors); /* Number of Rx errors */ + } +#endif + + /* Handle (unmasked) interrupts according to status bit settings */ + + ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + + /* Is this an Rx interrupt (meaning that a packet has been received)? */ + + if ((ris & MAC_RIS_RXINT) != 0) + { + /* Handle the incoming packet */ + + EMAC_STAT(priv, rx_int); + lm3s_receive(priv); + } + + /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ + + if ((ris & MAC_RIS_TXEMP) != 0) + { + /* Handle the complete of the transmission */ + + EMAC_STAT(priv, tx_int); + lm3s_txdone(priv); + } + + /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if + * there are no pending transmissions). + */ + + return OK; +} + +/**************************************************************************** + * Function: lm3s_txtimeout + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_txtimeout(int argc, uint32_t arg, ...) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; + + /* Increment statistics */ + + nlldbg("Tx timeout\n"); + EMAC_STAT(priv, tx_timeouts); + + /* Then reset the hardware */ + + DEBUGASSERT(priv->ld_bifup); + lm3s_ifdown(&priv->ld_dev); + lm3s_ifup(&priv->ld_dev); + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); +} + +/**************************************************************************** + * Function: lm3s_polltimer + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_polltimer(int argc, uint32_t arg, ...) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; + + /* Check if we can send another Tx packet now. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. + * + * NOTE: This can cause missing poll cycles and, hence, some timing + * inaccuracies. + */ + + if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If so, update TCP timing states and poll uIP for new XMIT data */ + + (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg); + } +} + +/**************************************************************************** + * Function: lm3s_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_ifup(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + uint32_t div; + uint16_t phyreg; + + nlldbg("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Enable and reset the Ethernet controller */ + + flags = irqsave(); + lm3s_ethreset(priv); + + /* Set the management clock divider register for access to the PHY + * register set. The MDC clock is divided down from the system clock per: + * + * MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1)) + * div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1 + * + * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will + * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded. + */ + + div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; + lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div); + nllvdbg("MDV: %08x\n", div); + + /* Then configure the Ethernet Controller for normal operation + * + * Setup the transmit control register (Full duplex, TX CRC Auto Generation, + * TX Padding Enabled). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval &= ~LM3S_TCTCL_CLRBITS; + regval |= LM3S_TCTCL_SETBITS; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + nllvdbg("TCTL: %08x\n", regval); + + /* Setup the receive control register (Disable multicast frames, disable + * promiscuous mode, disable bad CRC rejection). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~LM3S_RCTCL_CLRBITS; + regval |= LM3S_RCTCL_SETBITS; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + nllvdbg("RCTL: %08x\n", regval); + + /* Setup the time stamp configuration register */ + +#ifdef LM3S_ETHTS + regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); +#ifdef CONFIG_LM3S_TIMESTAMP + regval |= MAC_TS_EN; +#else + regval &= ~(MAC_TS_EN); +#endif + lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval); + nllvdbg("TS: %08x\n", regval); +#endif + + /* Wait for the link to come up. This following is not very conservative + * of system resources -- it really should wait gracefully on a semaphore + * and the interrupt handler should post the semaphore when LINKSTATUS is + * set + */ + + nlldbg("Waiting for link\n"); + do + { + phyreg = lm3s_phyread(priv, MII_MSR); + } + while ((phyreg & MII_MSR_LINKSTATUS) == 0); + nlldbg("Link established\n"); + + /* Reset the receive FIFO */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet receiver */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RXEN; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet transmitter */ + + regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval |= MAC_TCTL_TXEN; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Enable the Ethernet RX packet receipt interrupt */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval |= MAC_IM_RXINTM; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Program the hardware with it's MAC address (for filtering) */ + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; + lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; + lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); + + /* Set and activate a timer process */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv); + + priv->ld_bifup = true; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_ifdown + * + * Description: + * NuttX Callback: Stop the interface. The only way to restore normal + * behavior is to call lm3s_ifup(). + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_ifdown(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + + nlldbg("Taking down: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Cancel the TX poll timer and TX timeout timers */ + + flags = irqsave(); + wd_cancel(priv->ld_txpoll); + wd_cancel(priv->ld_txtimeout); + + /* Disable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Disable all Ethernet controller interrupt sources */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Reset the receive FIFO */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet receiver */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_RCTL_RXEN; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet transmitter */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_TCTL_TXEN; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Clear any pending interrupts */ + + regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + + /* The interface is now DOWN */ + + priv->ld_bifup = false; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int lm3s_txavail(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + + /* Ignore the notification if the interface is not yet up or if the Tx FIFO + * hardware is not available at this time. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. When the + * transmission completes, lm3s_txdone() will be called and the Tx polling + * will occur at that time. + */ + + flags = irqsave(); + if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If the interface is up and we can use the Tx FIFO, then poll uIP + * for new Tx data + */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); + } + + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Function: lm3s_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +int lm3s_ethinitialize(int intf) +#else +static inline int lm3s_ethinitialize(int intf) +#endif +{ + struct lm3s_driver_s *priv = &g_lm3sdev[intf]; + int ret; + + /* Check if the Ethernet module is present */ + + ndbg("Setting up eth%d\n", intf); + +#if LM3S_NETHCONTROLLERS > 1 +# error "This debug check only works with one interface" +#else + DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); +#endif + DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct lm3s_driver_s)); + priv->ld_dev.d_ifup = lm3s_ifup; /* I/F down callback */ + priv->ld_dev.d_ifdown = lm3s_ifdown; /* I/F up (new IP address) callback */ + priv->ld_dev.d_txavail = lm3s_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_IGMP + priv->ld_dev.d_addmac = lm3s_addmac; /* Add multicast MAC address */ + priv->ld_dev.d_rmmac = lm3s_rmmac; /* Remove multicast MAC address */ +#endif + priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + + /* Create a watchdog for timing polling for and timing of transmisstions */ + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate base address an IRQ with an interface is needed" + priv->ld_base = ??; /* Ethernet controller base address */ + priv->ld_irq = ??; /* Ethernet controller IRQ number */ +#endif + priv->ld_txpoll = wd_create(); /* Create periodic poll timer */ + priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */ + + /* If the board can provide us with a MAC address, get the address + * from the board now. The MAC will not be applied until lm3s_ifup() + * is caleld (and the MAC can be overwritten with a netdev ioctl call). + */ + +#ifdef CONFIG_LM3S_BOARDMAC + lm3s_ethernetmac(&priv->ld_dev.d_mac); +#endif + + /* Perform minimal, one-time initialization -- just reset the controller and + * leave it disabled. The Ethernet controller will be reset and properly + * re-initialized each time lm3s_ifup() is called. + */ + + lm3s_ethreset(priv); + lm3s_ifdown(&priv->ld_dev); + + /* Attach the IRQ to the driver */ + +#if LM3S_NETHCONTROLLERS > 1 + ret = irq_attach(priv->irq, lm3s_interrupt); +#else + ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt); +#endif + if (ret != 0) + { + /* We could not attach the ISR to the IRQ */ + + return -EAGAIN; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + (void)netdev_register(&priv->ld_dev); + return OK; +} + + +/************************************************************************************ + * Name: up_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one interface + * in the chip, then board-specific logic will have to provide this function to + * determine which, if any, Ethernet controllers should be initialized. + * + ************************************************************************************/ + +#if LM3S_NETHCONTROLLERS == 1 +void up_netinitialize(void) +{ + (void)lm3s_ethinitialize(0); +} +#endif + +#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */ + diff --git a/nuttx/arch/arm/src/lm/lm3s_gpio.c b/nuttx/arch/arm/src/lm/lm3s_gpio.c new file mode 100644 index 000000000..48cbefabf --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_gpio.c @@ -0,0 +1,854 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_gpio.c + * arch/arm/src/chip/lm3s_gpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "os_internal.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* These definitions are part of the implementation of the GPIO pad + * configuration of Table 9-1 in the LM3S6918 data sheet. + */ + +#define AFSEL_SHIFT 5 +#define AFSEL_1 (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */ +#define AFSEL_0 0 +#define AFSEL_X 0 + +#define DIR_SHIFT 4 +#define DIR_1 (1 << DIR_SHIFT) /* Set/clear bit in GPIO DIR register */ +#define DIR_0 0 +#define DIR_X 0 + +#define ODR_SHIFT 3 +#define ODR_1 (1 << ODR_SHIFT) /* Set/clear bit in GPIO ODR register */ +#define ODR_0 0 +#define ODR_X 0 + +#define DEN_SHIFT 2 +#define DEN_1 (1 << DEN_SHIFT) /* Set/clear bit in GPIO DEN register */ +#define DEN_0 0 +#define DEN_X 0 + +#define PUR_SHIFT 1 +#define PUR_1 (1 << PUR_SHIFT) /* Set/clear bit in GPIO PUR register */ +#define PUR_0 0 +#define PUR_X 0 + +#define PDR_SHIFT 0 +#define PDR_1 (1 << PDR_SHIFT) /* Set/clear bit in GPIO PDR register */ +#define PDR_0 0 +#define PDR_X 0 + +#define GPIO_INPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_OUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_OUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODOUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODOUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFODIO_SETBITS (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFODIO_CLRBITS (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFIO_SETBITS (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFIO_CLRBITS (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ANINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0) +#define GPIO_ANINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1) + +#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_func_s +{ + uint8_t setbits; /* A set of GPIO register bits to set */ + uint8_t clrbits; /* A set of GPIO register bits to clear */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_func_s g_funcbits[] = +{ + {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ + {GPIO_OUTPUT_SETBITS, GPIO_OUTPUT_CLRBITS}, /* GPIO_FUNC_OUTPUT */ + {GPIO_ODINPUT_SETBITS, GPIO_ODINPUT_CLRBITS}, /* GPIO_FUNC_ODINPUT */ + {GPIO_ODOUTPUT_SETBITS, GPIO_ODOUTPUT_CLRBITS}, /* GPIO_FUNC_ODOUTPUT */ + {GPIO_PFODIO_SETBITS, GPIO_PFODIO_CLRBITS}, /* GPIO_FUNC_PFODIO */ + {GPIO_PFIO_SETBITS, GPIO_PFIO_CLRBITS}, /* GPIO_FUNC_PFIO */ + {GPIO_ANINPUT_SETBITS, GPIO_ANINPUT_CLRBITS}, /* GPIO_FUNC_ANINPUT */ + {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ +}; + +static const uint32_t g_gpiobase[LM3S_NPORTS] = +{ + /* All support LM3S parts have at least 7 ports, GPIOA-G */ + + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, + + /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 7 + LM3S_GPIOH_BASE, +#endif + + /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 8 + LM3S_GPIOJ_BASE, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static uint32_t lm3s_gpiobaseaddress(unsigned int port) +{ + uint32_t gpiobase = 0; + if (port < LM3S_NPORTS) + { + gpiobase = g_gpiobase[port]; + } + return gpiobase; +} + +/**************************************************************************** + * Name: lm3s_gpiofunc + * + * Description: + * Configure GPIO registers for a specific function + * + ****************************************************************************/ + +static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func) +{ + uint32_t setbit; + uint32_t clrbit; + uint32_t regval; + + /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + + setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + } + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + } + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + + setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); + + /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data + * direction register. Bits set to 1 in the GPIODIR register configure + * the corresponding pin to be an output, while bits set to 0 configure the + * pins to be inputs. All bits are cleared by a reset, meaning all GPIO + * pins are inputs by default. + */ + + setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); + + /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode + * control select register. Writing a 1 to any bit in this register selects + * the hardware control for the corresponding GPIO line. All bits are cleared + * by a reset, therefore no GPIO line is set to hardware control by default." + * + * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit + * and unlock the GPIO. That is not implemented here. + */ + + setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); +} + +/**************************************************************************** + * Name: lm3s_gpiopadstrength + * + * Description: + * Set up pad strength and pull-ups + * + ****************************************************************************/ + +static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT; + uint32_t regoffset; + uint32_t regval; + uint32_t slrset; + uint32_t slrclr; + + /* Prepare bits to disable slew */ + + slrset = 0; + slrclr = pin; + + switch (strength) + { + case 0: /* 2mA pad drive strength */ + { + /* "The GPIODR2R register is the 2-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing a DRV2 bit for a GPIO + * signal, the corresponding DRV4 bit in the GPIO DR4R register and the + * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR2R_OFFSET; + } + break; + + case 1: /* 4mA pad drive strength */ + { + /* "The GPIODR4R register is the 4-mA drive control register. It allows + * for each GPIO signal in the port to be individually configured without + * affecting the other pads. When writing the DRV4 bit for a GPIO signal, + * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit + * in the GPIO DR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR4R_OFFSET; + } + break; + + case 3: /* 8mA Pad drive with slew rate control */ + { + /* "The GPIOSLR register is the slew rate control register. Slew rate + * control is only available when using the 8-mA drive strength option + * via the GPIO 8-mA Drive Select (GPIODR8R) register..." + */ + + slrset = pin; + slrclr = 0; + } + /* Fall through */ + + case 2: /* 8mA pad drive strength (without slew rate control) */ + { + /* "The GPIODR8R register is the 8-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing the DRV8 bit for a GPIO + * signal, the corresponding DRV2 bit in the GPIO DR2R register and the + * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR8R_OFFSET; + } + break; + } + + /* Set the selected pad strength and set/clear optional slew rate control */ + + regval = getreg32(base + regoffset); + regval |= pin; + putreg32(regval, base + regoffset); + + regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); + regval &= slrclr; + regval |= slrset; + putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); +} + +/**************************************************************************** + * Name: lm3s_gpiopadtype + * + * Description: + * Set up pad strength and pull-ups. Some of these values may be over- + * written by lm3s_gpiofunc, depending on the function selection. Others + * are optional for different function selections. + * + ****************************************************************************/ + +static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int padtype = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT; +#if 0 /* always overwritten by lm3s_gpiofunc */ + uint32_t odrset; + uint32_t odrclr; +#endif + uint32_t purset; + uint32_t purclr; + uint32_t pdrset; + uint32_t pdrclr; +#if 0 /* always overwritten by lm3s_gpiofunc */ + uint32_t denset; + uint32_t denclr; +#endif + uint32_t regval; + + /* Assume digital GPIO function, push-pull with no pull-up or pull-down */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = 0; + odrclr = pin; +#endif + purset = 0; + purclr = pin; + pdrset = 0; + pdrclr = pin; +#if 0 /* always overwritten by lm3s_gpiofunc */ + denset = pin; + denclr = 0; +#endif + + switch (padtype) + { + case 0: /* Push-pull */ + default: + { + } + break; + + case 1: /* Push-pull with weak pull-up */ + { + purset = pin; + purclr = 0; + } + break; + case 2: /* Push-pull with weak pull-down */ + { + pdrset = pin; + pdrclr = 0; + } + break; + case 3: /* Open-drain */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + } + break; + case 4: /* Open-drain with weak pull-up */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + purset = pin; + purclr = 0; + } + break; + case 5: /* Open-drain with weak pull-down */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + pdrset = pin; + pdrclr = 0; + } + break; + case 6: /* Analog comparator */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + denset = 0; + denclr = pin; +#endif + } + break; + } + + /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~odrclr; + regval |= odrset; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); +#endif + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~purclr; + regval |= purset; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~pdrclr; + regval |= pdrset; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~denclr; + regval |= denset; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); +#endif +} + +/**************************************************************************** + * Name: lm3s_initoutput + * + * Description: + * Set the GPIO output value + * + ****************************************************************************/ + +static inline void lm3s_initoutput(uint32_t cfgset) +{ + bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO); + lm3s_gpiowrite(cfgset, value); +} + +/**************************************************************************** + * Name: lm3s_interrupt + * + * Description: + * Configure the interrupt pin. + * + ****************************************************************************/ + +static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; + uint32_t regval; + uint32_t isset; + uint32_t isclr; + uint32_t ibeset; + uint32_t ibeclr; + uint32_t iveset; + uint32_t iveclr; + + /* Mask and clear the GPIO interrupt + * + * "The GPIOIM register is the interrupt mask register. Bits set to High in + * GPIO IM allow the corresponding pins to trigger their individual interrupts + * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering + * on that pin. All bits are cleared by a reset." + */ + + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + + /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit + * in this register clears the corresponding interrupt edge detection logic + * register. Writing a 0 has no effect." + */ + + regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); + + /* Assume rising edge */ + + isset = 0; /* Not level sensed */ + isclr = pin; + ibeset = 0; /* Single edge */ + ibeclr = pin; + iveset = pin; /* Rising edge or high levels*/ + iveclr = 0; + + /* Then handle according to the selected interrupt type */ + + switch (inttype) + { + case 0: /* Interrupt on falling edge */ + { + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 1: /* Interrupt on rising edge */ + default: + break; + + case 2: /* Interrupt on both edges */ + { + ibeset = pin; /* Both edges */ + ibeclr = 0; + } + break; + + case 3: /* Interrupt on low level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 4: /* Interrupt on high level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + } + break; + } + + /* "The GPIO IS register is the interrupt sense register. Bits set to + * 1 in GPIOIS configure the corresponding pins to detect levels, while + * bits set to 0 configure the pins to detect edges. All bits are cleared + * by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IS_OFFSET); + regval &= isclr; + regval |= isset; + putreg32(regval, base + LM3S_GPIO_IS_OFFSET); + + /* "The GPIO IBE register is the interrupt both-edges register. When the + * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is + * set to detect edges, bits set to High in GPIO IBE configure the + * corresponding pin to detect both rising and falling edges, regardless + * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ... + * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits + * are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); + regval &= ibeclr; + regval |= ibeset; + putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); + + /* "The GPIOIEV register is the interrupt event register. Bits set to + * High in GPIO IEV configure the corresponding pin to detect rising edges + * or high levels, depending on the corresponding bit value in the GPIO + * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to + * detect falling edges or low levels, depending on the corresponding bit + * value in GPIOIS. All bits are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); + regval &= iveclr; + regval |= iveset; + putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm3s_configgpio(uint32_t cfgset) +{ + irqstate_t flags; + unsigned int func; + unsigned int port; + unsigned int pinno; + uint32_t pin; + uint32_t base; + uint32_t regval; + + /* Decode the basics */ + + func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT; + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (cfgset & GPIO_NUMBER_MASK); + pin = (1 <> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + + /* "The GPIO DATA register is the data register. In software control mode, + * values written in the GPIO DATA register are transferred onto the GPIO + * port pins if the respective pins have been configured as outputs through + * the GPIO Direction (GPIO DIR) register ... + * + * "In order to write to GPIO DATA, the corresponding bits in the mask, + * resulting from the address bus bits [9:2], must be High. Otherwise, the + * bit values remain unchanged by the write. + * + * "... All bits are cleared by a reset." + */ + + putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); +} + +/**************************************************************************** + * Name: lm3s_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm3s_gpioread(uint32_t pinset, bool value) +{ + unsigned int port; + unsigned int pinno; + uint32_t base; + + /* Decode the basics */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + + /* "... the values read from this register are determined for each bit + * by the mask bit derived from the address used to access the data register, + * bits [9:2]. Bits that are 1 in the address mask cause the corresponding + * bits in GPIODATA to be read, and bits that are 0 in the address mask cause + * the corresponding bits in GPIO DATA to be read as 0, regardless of their + * value. + * + * "A read from GPIO DATA returns the last bit value written if the respective + * pins are configured as outputs, or it returns the value on the + * corresponding input pin when these are configured as inputs. All bits + * are cleared by a reset." + */ + + return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c new file mode 100644 index 000000000..a54bfe335 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c @@ -0,0 +1,434 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_gpioirq.c + * arch/arm/src/chip/lm3s_gpioirq.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "os_internal.h" +#include "irq_internal.h" + +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A table of handlers for each GPIO interrupt */ + +static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; + +/* A table that maps a GPIO group to a GPIO base address. Overly complicated + * because we support disabling interrupt support for arbitrary ports. This + * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h + */ + +static const uint32_t g_gpiobase[] = +{ +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS + LM3S_GPIOA_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS + LM3S_GPIOB_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS + LM3S_GPIOC_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS + LM3S_GPIOD_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS + LM3S_GPIOE_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS + LM3S_GPIOF_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS + LM3S_GPIOG_BASE, +#endif + + /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip + * does not support these higher ports, then they must be disabled in the + * configuration. Otherwise, the following will likely cause compilation + * errors! + */ + +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS + LM3S_GPIOH_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS + LM3S_GPIOJ_BASE, +#endif +}; + +#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t)) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Input: + * gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS. + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. NOTE that range checking was provided by + * callee + * + ****************************************************************************/ + +static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq) +{ + unsigned int ndx = gpioirq >> 3; + if (ndx < GPIO_NADDRS) + { + return g_gpiobase[ndx]; + } + return 0; +} + +/**************************************************************************** + * Name: lm3s_gpio*handler + * + * Description: + * Handle interrupts on each enabled GPIO port + * + ****************************************************************************/ + +static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context) +{ + uint32_t mis; + int irq; + int pin; + + /* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked + * interrupt status register. Bits read High in GPIO MIS reflect the status + * of input lines triggering an interrupt. Bits read as Low indicate that + * either no interrupt has been generated, or the interrupt is masked." + */ + + mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; + + /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR + * register is the interrupt clear register. Writing a 1 to a bit in this + * register clears the corresponding interrupt edge detection logic register. + * Writing a 0 has no effect." + */ + + putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); + + /* Now process each IRQ pending in the MIS */ + + for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1) + { + if ((mis & 1) != 0) + { + irq = irqbase + pin; + g_gpioirqvector[irq - NR_IRQS](irq, context); + } + } + return OK; +} + +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS +static int lm3s_gpioahandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS +static int lm3s_gpiobhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS +static int lm3s_gpiochandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS +static int lm3s_gpiodhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS +static int lm3s_gpioehandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS +static int lm3s_gpiofhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS +static int lm3s_gpioghandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS +static int lm3s_gpiohhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS +static int lm3s_gpiojhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int gpio_irqinitialize(void) +{ + int i; + + /* Point all interrupt vectors to the unexpected interrupt */ + + for (i = 0; i < NR_GPIO_IRQS; i++) + { + g_gpioirqvector[i] = irq_unexpected_isr; + } + + /* Then attach each GPIO interrupt handlers and enable corresponding GPIO + * interrupts + */ + +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS + irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler); + up_enable_irq(LM3S_IRQ_GPIOA); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS + irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler); + up_enable_irq(LM3S_IRQ_GPIOB); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS + irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler); + up_enable_irq(LM3S_IRQ_GPIOC); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS + irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler); + up_enable_irq(LM3S_IRQ_GPIOD); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS + irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler); + up_enable_irq(LM3S_IRQ_GPIOE); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS + irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler); + up_enable_irq(LM3S_IRQ_GPIOF); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS + irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler); + up_enable_irq(LM3S_IRQ_GPIOG); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS + irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler); + up_enable_irq(LM3S_IRQ_GPIOH); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS + irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler); + up_enable_irq(LM3S_IRQ_GPIOJ); +#endif + + return OK; +} + +/**************************************************************************** + * Name: gpio_irqattach + * + * Description: + * Attach in GPIO interrupt to the provide 'isr' + * + ****************************************************************************/ + +int gpio_irqattach(int irq, xcpt_t isr) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + int ret = ERROR; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + flags = irqsave(); + + /* If the new ISR is NULL, then the ISR is being detached. + * In this case, disable the ISR and direct any interrupts + * to the unexpected interrupt handler. + */ + + if (isr == NULL) + { +#ifndef CONFIG_ARCH_NOINTC + gpio_irqdisable(gpioirq); +#endif + isr = irq_unexpected_isr; + } + + /* Save the new ISR in the table. */ + + g_irqvector[gpioirq] = isr; + irqrestore(flags); + ret = OK; + } + return ret; +} + +/**************************************************************************** + * Name: gpio_irqenable + * + * Description: + * Enable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqenable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm3s_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + +/**************************************************************************** + * Name: gpio_irqdisable + * + * Description: + * Disable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqdisable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm3s_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_irq.c b/nuttx/arch/arm/src/lm/lm3s_irq.c new file mode 100644 index 000000000..2039d84a8 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_irq.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_irq.c + * arch/arm/src/chip/lm3s_irq.c + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enable NVIC debug features that are probably only desireable during + * bringup + */ + +#undef LM3S_IRQ_DEBUG + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +static void lm3s_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = irqsave(); + slldbg("NVIC (%s, irq=%d):\n", msg, irq); + slldbg(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + slldbg(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + slldbg(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqrestore(flags); +} +#else +# define lm3s_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv, + * lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +static int lm3s_nmi(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! NMI received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_busfault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Bus fault recived\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_usagefault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Usage fault received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_pendsv(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! PendSV received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_dbgmonitor(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Debug Monitor receieved\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_reserved(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Reserved interrupt\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} +#endif + +/**************************************************************************** + * Name: lm3s_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) +{ + DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LM3S_IRQ_INTERRUPTS) + { + if (irq < LM3S_IRQ_INTERRUPTS + 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); + } + else if (irq < NR_IRQS) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); + } + else + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handler processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == LM3S_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == LM3S_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == LM3S_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == LM3S_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable all interrupts */ + + putreg32(0, NVIC_IRQ0_31_ENABLE); + putreg32(0, NVIC_IRQ32_63_ENABLE); + + /* Set all interrrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + + /* currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Initialize support for GPIO interrupts if included in this build */ + +#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (gpio_irqinitialize != NULL) +#endif + { + gpio_irqinitialize(); + } +#endif + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(LM3S_IRQ_SVCALL, up_svcall); + irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); + up_enable_irq(LM3S_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG + irq_attach(LM3S_IRQ_NMI, lm3s_nmi); +#ifndef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); +#endif + irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault); + irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault); + irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv); + irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor); + irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved); +#endif + + lm3s_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + setbasepri(NVIC_SYSH_PRIORITY_MAX); + irqrestore(0); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Clear the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + lm3s_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Set the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + lm3s_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_maskack_irq + * + * Description: + * Mask the IRQ and acknowledge it + * + ****************************************************************************/ + +void up_maskack_irq(int irq) +{ + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < LM3S_IRQ_INTERRUPTS) + { + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + } + else + { + irq -= LM3S_IRQ_INTERRUPTS; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + lm3s_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/nuttx/arch/arm/src/lm/lm3s_lowputc.c b/nuttx/arch/arm/src/lm/lm3s_lowputc.c new file mode 100644 index 000000000..7f9a826c8 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_lowputc.c @@ -0,0 +1,309 @@ +/************************************************************************** + * arch/arm/src/lm/lm3s_lowputc.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_gpio.h" +#include "chip/lm_pinmap.h" + +#include "lm_lowputc.h" + +/************************************************************************** + * Pre-processor Definitions + **************************************************************************/ + +/* Configuration **********************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM3S_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM3S_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART0_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART1_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART2_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP +#else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#endif + +/* Get LCRH settings */ + +#if LM3S_CONSOLE_BITS == 5 +# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS +#elif LM3S_CONSOLE_BITS == 6 +# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS +#elif LM3S_CONSOLE_BITS == 7 +# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS +#elif LM3S_CONSOLE_BITS == 8 +# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS +#else +# error "Number of bits not supported" +#endif + +#if LM3S_CONSOLE_PARITY == 0 +# define UART_LCRH_PARITY (0) +#elif LM3S_CONSOLE_PARITY == 1 +# define UART_LCRH_PARITY UART_LCRH_PEN +#elif LM3S_CONSOLE_PARITY == 2 +# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) +#else +# error "Invalid parity selection" +#endif + +#if LM3S_CONSOLE_2STOP != 0 +# define UART_LCRH_NSTOP UART_LCRH_STP2 +#else +# define UART_LCRH_NSTOP (0) +#endif + +#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN) + +/* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit + * fractional part. The number formed by these two values is used by the baud-rate generator + * to determine the bit period. Having a fractional baud-rate divider allows the UART to + * generate all the standard baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) + * register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate + * Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship + * to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional + * part, separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number + * (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated + * by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 + * to account for rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred + * to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is + * used for error detection during receive operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and + * UARTFBRD registers form an internal 30-bit register. This internal register is only + * updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate + * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." + */ + +#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) +#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) +#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) +#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) + +/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: + * + * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 + * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 + * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 + * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 + * + * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 + */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX FIFO is not full */ + + while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); + + /* Then send the character */ + + putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); +#endif +} + +/************************************************************************** + * Name: up_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +void up_lowsetup(void) +{ + uint32_t regval; +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t ctl; +#endif + + /* Enable the selected UARTs and configure GPIO pins to need by the + * the selected UARTs. NOTE: The serial driver later depends on + * this pin configuration -- whether or not a serial console is selected. + */ + +#ifdef CONFIG_LM3S_UART0 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART0; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART0_RX); + lm3s_configgpio(GPIO_UART0_TX); +#endif + +#ifdef CONFIG_LM3S_UART1 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART1; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART1_RX); + lm3s_configgpio(GPIO_UART1_TX); +#endif + + /* Enable the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + + /* Write the integer portion of the BRD to the UART IBRD register */ + + putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); + + /* Write the fractional portion of the BRD to the UART FBRD register */ + + putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); + + /* Write the desired serial parameters to the UART LCRH register */ + + putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); + + /* Enable the UART by setting the UARTEN bit in the UART CTL register */ + + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); +#endif + +} + + diff --git a/nuttx/arch/arm/src/lm/lm3s_serial.c b/nuttx/arch/arm/src/lm/lm3s_serial.c new file mode 100644 index 000000000..79628c765 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_serial.c @@ -0,0 +1,1064 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_serial.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM3S_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM3S_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a UART enabled? */ + +#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2) +# error "No UARTs enabled" +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* If we are not using the serial driver for the console, then we + * still must provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# ifdef CONFIG_LM3S_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM3S_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# ifdef CONFIG_LM3S_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM3S_UART0) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM3S_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM3S_UART1) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +#elifdefined(CONFIG_LM3S_UART2) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#else +# error "No valid TTY devices" +# undef CONSOLE_DEV /* No console device */ +# undef TTYS0_DEV /* No ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t im; /* Saved IM value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_LM3S_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM3S_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM3S_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +/* This describes the state of the LM3S uart0 port. */ + +#ifdef CONFIG_LM3S_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = LM3S_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = LM3S_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM3S_UART1 +static struct up_dev_s g_uart1priv = +{ + .uartbase = LM3S_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = LM3S_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM3S_UART2 +static struct up_dev_s g_uart2priv = +{ + .uartbase = LM3S_UART2_BASE, + .baud = CONFIG_UART2_BAUD, + .irq = LM3S_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) +{ + /* Return the current interrupt mask value */ + + if (im) + { + *im = priv->im; + } + + /* Disable all interrupts */ + + priv->im = 0; + up_serialout(priv, LM3S_UART_IM_OFFSET, 0); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) +{ + priv->im = im; + up_serialout(priv, LM3S_UART_IM_OFFSET, im); +} + +/**************************************************************************** + * Name: up_waittxnotfull + ****************************************************************************/ + +#ifdef HAVE_CONSOLE +static inline void up_waittxnotfull(struct up_dev_s *priv) +{ + int tmp; + + /* Limit how long we will wait for the TX available condition */ + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + /* Check Tx FIFO is full */ + + if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) + { + /* The Tx FIFO is not full... return */ + + break; + } + } + + /* If we get here, then the wait has timed out and the Tx FIFO remains + * full. + */ +} +#endif + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t lcrh; + uint32_t ctl; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t den; + uint32_t brdi; + uint32_t remainder; + uint32_t divfrac; + + /* Note: The logic here depends on the fact that that the UART module + * was enabled and the GPIOs were configured in up_lowsetup(). + */ + + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer + * and a 6-bit fractional part. The number formed by these two values is + * used by the baud-rate generator to determine the bit period. Having a + * fractional baud-rate divider allows the UART to generate all the standard + * baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor + * (UARTIBRD) register ... and the 6-bit fractional part is loaded with the + * UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate + * divisor (BRD) has the following relationship to the system clock (where + * BRDI is the integer part of the BRD and BRDF is the fractional part, + * separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit + * fractional number (that is to be loaded into the DIVFRAC bit field in the + * UARTFBRD register) can be calculated by taking the fractional part of the + * baud-rate divisor, multiplying it by 64, and adding 0.5 to account for + * rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud- + * rate (referred to as Baud16). This reference clock is divided by 16 to + * generate the transmit clock, and is used for error detection during receive + * operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the + * UARTIBRD and UARTFBRD registers form an internal 30-bit register. This + * internal register is only updated when a write operation to UARTLCRH is + * performed, so any changes to the baud-rate divisor must be followed by a + * write to the UARTLCRH register for the changes to take effect. ..." + */ + + den = priv->baud << 4; + brdi = SYSCLK_FREQUENCY / den; + remainder = SYSCLK_FREQUENCY - den * brdi; + divfrac = ((remainder << 6) + (den >> 1)) / den; + + up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); + up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); + + /* Set up the LCRH register */ + + lcrh = 0; + switch (priv->bits) + { + case 5: + lcrh |= UART_LCRH_WLEN_5BITS; + break; + case 6: + lcrh |= UART_LCRH_WLEN_6BITS; + break; + case 7: + lcrh |= UART_LCRH_WLEN_7BITS; + break; + case 8: + default: + lcrh |= UART_LCRH_WLEN_8BITS; + break; + } + + switch (priv->parity) + { + case 0: + default: + break; + case 1: + lcrh |= UART_LCRH_PEN; + break; + case 2: + lcrh |= UART_LCRH_PEN|UART_LCRH_EPS; + break; + } + + if (priv->stopbits2) + { + lcrh |= UART_LCRH_STP2; + } + + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); +#endif + + /* Set the UART to interrupt whenever the TX FIFO is almost empty or when + * any character is received. + */ + + up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); + + /* Flush the Rx and Tx FIFOs -- How do you do that?*/ + + /* Enable Rx interrupts from the UART except for Tx interrupts. We don't want + * Tx interrupts until we have something to send. We will check for serial + * errors as part of Rx interrupt processing (no interrupts will be received + * yet because the interrupt is still disabled at the interrupt controller. + */ + + up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); + + /* Enable the FIFOs */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); +#endif + lcrh |= UART_LCRH_FEN; + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); + + /* Enable Rx, Tx, and the UART */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); +#endif + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Set up the cache IM value */ + + priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked + * when an interrupt received on the 'irq' It should call + * uart_transmitchars or uart_receivechar to perform the + * appropriate data transfers. The interrupt handling logic\ + * must be able to map the 'irq' number into the approprite + * uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + uint32_t mis; + int passes; + bool handled; + +#ifdef CONFIG_LM3S_UART0 + if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_LM3S_UART1 + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked UART status and clear the pending interrupts. */ + + mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); + up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); + + /* Handle incoming, receive bytes (with or without timeout) */ + + if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0) + { + /* Rx buffer not empty ... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + if ((mis & UART_MIS_TXMIS) != 0) + { + /* Tx FIFO not full ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + int ret = OK; + + switch (cmd) + { + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t rxd; + + /* Get the Rx byte + 4 bits of error information. Return those in status */ + + rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); + *status = rxd; + + /* The lower 8bits of the Rx data is the actual recevied byte */ + + return rxd & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx + * timeout occurs. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= (UART_IM_RXIM|UART_IM_RTIM); +#endif + } + else + { + priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); + } + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { + /* Set to receive an interrupt when the TX fifo is half emptied */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + + /* The serial driver wants an interrupt here, but will not get get + * one unless we "prime the pump." I believe that this is because + * behave like a level interrupt and the LM3S interrupts behave + * (at least by default) like edge interrupts. + * + * In any event, faking a TX interrupt here solves the problem; + * Call uart_xmitchars() just as would have been done if we recieved + * the TX interrupt. + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->im &= ~UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + } + irqrestore(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level UART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before up_serialinit. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * up_lowsetup + */ + + /* Disable all UARTS */ + + up_disableuartint(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + up_disableuartint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableuartint(TTYS2_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint32_t im; + + up_disableuartint(priv, &im); + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); + } + + up_waittxnotfull(priv); + up_restoreuartint(priv, im); +#endif + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/nuttx/arch/arm/src/lm/lm3s_ssi.c b/nuttx/arch/arm/src/lm/lm3s_ssi.c new file mode 100644 index 000000000..8cd1cee07 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_ssi.c @@ -0,0 +1,1580 @@ +/**************************************************************************** + * arch/arm/src/lm32/lm3s_ssi.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" +#include "lm_ssi.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG with + * CONFIG_DEBUG_VERBOSE too) + */ + +#undef SSI_DEBUG /* Define to enable debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# define ssivdbg llvdbg +#else +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI + * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in + * such case, the following must be expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* Which SSI modules have been enabled? */ + +#ifndef CONFIG_SSI0_DISABLE +# define SSI0_NDX 0 /* Index to SSI0 in g_ssidev[] */ +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 1 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ +# else +# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ +# define SSI_BASE LM3S_SSI0_BASE +# define SSI_IRQ LM3S_IRQ_SSI0 +# endif +#else +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ +# define SSI_BASE LM3S_SSI1_BASE +# define SSI_IRQ LM3S_IRQ_SSI1 +# else +# define NSSI_ENABLED 0 /* No SSI interfaces */ +# endif +#endif + +/* Compile the rest of the file only if at least one SSI interface has been + * enabled. + */ + +#if NSSI_ENABLED > 0 + +/* The number of (16-bit) words that will fit in the Tx FIFO */ + +#define LM3S_TXFIFO_WORDS 8 + +/* Configuration settings */ + +#ifndef CONFIG_SSI_TXLIMIT +# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) +#endif + +#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS +# error "Invalid range for CONFIG_SSI_TXLIMIT" +#endif + +#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) +# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" +#endif + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +struct lm3s_ssidev_s +{ + const struct spi_ops_s *ops; /* Common SPI operations */ +#ifndef CONFIG_SSI_POLLWAIT + sem_t xfrsem; /* Wait for transfer to complete */ +#endif + + /* These following are the source and destination buffers of the transfer. + * they are retained in this structure so that they will be accessible + * from an interrupt handler. The actual type of the buffer is uint8_t if + * nbits <=8 and uint16_t if nbits >8. + */ + + void *txbuffer; /* Source buffer */ + void *rxbuffer; /* Destination buffer */ + + /* These are functions pointers that are configured to perform the + * appropriate transfer for the particular kind of exchange that is + * occurring. Differnt functions may be selected depending on (1) + * if the tx or txbuffer is NULL and depending on the number of bits + * per word. + */ + + void (*txword)(struct lm3s_ssidev_s *priv); + void (*rxword)(struct lm3s_ssidev_s *priv); + +#if NSSI_ENABLED > 1 + uint32_t base; /* SSI register base address */ +#endif + + int ntxwords; /* Number of words left to transfer on the Tx FIFO */ + int nrxwords; /* Number of words received on the Rx FIFO */ + int nwords; /* Number of words to be exchanged */ + uint8_t nbits; /* Current number of bits per word */ + +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + uint8_t irq; /* SSI IRQ number */ +#endif + + /* If there is more than one device on the SPI bus, then we have to enforce + * mutual exclusion and remember some configuration settings to reduce the + * overhead of constant SPI re-configuration. + */ + +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* For exclusive access to the SSI bus */ + uint32_t frequency; /* Current desired SCLK frequency */ + uint32_t actual; /* Current actual SCLK frequency */ + uint8_t mode; /* Current mode 0,1,2,3 */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SSI register access */ + +static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, + unsigned int offset); +static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, + uint32_t value); + +/* Misc helpers */ + +static uint32_t ssi_disable(struct lm3s_ssidev_s *priv); +static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable); + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem); +#define ssi_semgive(s) sem_post(s); +#endif + +/* SSI data transfer */ + +static void ssi_txnull(struct lm3s_ssidev_s *priv); +static void ssi_txuint16(struct lm3s_ssidev_s *priv); +static void ssi_txuint8(struct lm3s_ssidev_s *priv); +static void ssi_rxnull(struct lm3s_ssidev_s *priv); +static void ssi_rxuint16(struct lm3s_ssidev_s *priv); +static void ssi_rxuint8(struct lm3s_ssidev_s *priv); +static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv); +static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv); +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm3s_ssidev_s *priv); +#else +static int ssi_performtx(struct lm3s_ssidev_s *priv); +#endif +static inline void ssi_performrx(struct lm3s_ssidev_s *priv); +static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords); + +/* Interrupt handling */ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm3s_ssidev_s *ssi_mapirq(int irq); +static int ssi_interrupt(int irq, void *context); +#endif + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, + uint32_t frequency); +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, + enum spi_mode_e mode); +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits); +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd); +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#else +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords); +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Common SSI operations */ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssi_lock, +#endif + .select = lm3s_spiselect, /* Provided externally by board logic */ + .setfrequency = ssi_setfrequency, + .setmode = ssi_setmode, + .setbits = ssi_setbits, + .status = lm3s_spistatus, /* Provided externally by board logic */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lm3s_spicmddata, +#endif + .send = ssi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = ssi_exchange, +#else + .sndblock = ssi_sndblock, + .recvblock = ssi_recvblock, +#endif +}; + +/* This supports is up to two SSI busses/ports */ + +static struct lm3s_ssidev_s g_ssidev[] = +{ +#ifndef CONFIG_SSI0_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI0_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI0, +#endif + }, +#endif +#ifndef CONFIG_SSI1_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI1_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI1, +#endif + }, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ssi_getreg + * + * Description: + * Read the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * + * Returned Value: + * Value of the register at this offset + * + ****************************************************************************/ + +static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset) +{ +#if NSSI_ENABLED > 1 + return getreg32(priv->base + offset); +#else + return getreg32(SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_putreg + * + * Description: + * Write the value to the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * value - Value to write + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value) +{ +#if NSSI_ENABLED > 1 + putreg32(value, priv->base + offset); +#else + putreg32(value, SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_disable + * + * Description: + * Disable SSI operation. NOTE: The SSI must be disabled before any control + * registers can be re-programmed. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * State of the SSI before the SSE was disabled + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_disable(struct lm3s_ssidev_s *priv) +{ + uint32_t retval; + uint32_t regval; + + retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval = (retval & ~SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); + return retval; +} + +/**************************************************************************** + * Name: ssi_enable + * + * Description: + * Restore the SSI operational state + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable) +{ + uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval &= ~SSI_CR1_SSE; + regval |= (enable & SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); +} + +/**************************************************************************** + * Name: ssi_semtake + * + * Description: + * Wait for a semaphore (handling interruption by signals); + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem) +{ + int ret; + do + { + ret = sem_wait(sem); + } + while (ret < 0 && errno == EINTR); + DEBUGASSERT(ret == 0); +} +#endif + +/**************************************************************************** + * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8 + * + * Description: + * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer + * pointer appropriately. The selected function dependes on (1) if there + * is a source txbuffer provided, and (2) if the number of bits per + * word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_txnull(struct lm3s_ssidev_s *priv) +{ + ssivdbg("TX: ->0xffff\n"); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); +} + +static void ssi_txuint16(struct lm3s_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->txbuffer; + ssivdbg("TX: %p->%04x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +static void ssi_txuint8(struct lm3s_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->txbuffer; + ssivdbg("TX: %p->%02x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +/**************************************************************************** + * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8 + * + * Description: + * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the + * user rxvbuffer and update the rxbuffer pointer appropriately. The + * selected function dependes on (1) if there is a desination rxbuffer + * provided, and (2) if the number of bits per word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_rxnull(struct lm3s_ssidev_s *priv) +{ +#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) + uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: discard %04x\n", regval); +#else + (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); +#endif +} + +static void ssi_rxuint16(struct lm3s_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->rxbuffer; + *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%04x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +static void ssi_rxuint8(struct lm3s_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->rxbuffer; + *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%02x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +/**************************************************************************** + * Name: ssi_txfifofull + * + * Description: + * Return true if the Tx FIFO is full + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not full + * + ****************************************************************************/ + +static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; +} + +/**************************************************************************** + * Name: ssi_rxfifoempty + * + * Description: + * Return true if the Rx FIFO is empty + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not empty + * + ****************************************************************************/ + +static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; +} + +/**************************************************************************** + * Name: ssi_performtx + * + * Description: + * If the Tx FIFO is empty, then transfer as many words as we can to + * the FIFO. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * The number of words written to the Tx FIFO (a value from 0 to 8, + * inclusive). + * + ****************************************************************************/ + +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm3s_ssidev_s *priv) +{ + /* Check if the Tx FIFO is full and more data to transfer */ + + if (!ssi_txfifofull(priv) && priv->ntxwords > 0) + { + /* Transfer one word to the Tx FIFO */ + + priv->txword(priv); + priv->ntxwords--; + return 1; + } + return 0; +} + +#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +static int ssi_performtx(struct lm3s_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + int ntxd = 0; /* Number of words written to Tx FIFO */ + + /* Check if the Tx FIFO is full */ + + if (!ssi_txfifofull(priv)) + { + /* Not full.. Check if all of the Tx words have been sent */ + + if (priv->ntxwords > 0) + { + /* No.. Transfer more words until either the Tx FIFO is full or + * until all of the user provided data has been sent. + */ +#ifdef CONFIG_SSI_TXLIMIT + /* Further limit the number of words that we put into the Tx + * FIFO to CONFIG_SSI_TXLIMIT. Otherwise, we could + * overrun the Rx FIFO on a very fast SSI bus. + */ + for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++) +#else + for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++) +#endif + { + priv->txword(priv); + } + + /* Update the count of words to to transferred */ + + priv->ntxwords -= ntxd; + } + + /* Check again... Now have all of the Tx words been sent? */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords > 0) + { + /* No.. Enable the Tx FIFO interrupt. This interrupt occurs + * when the Tx FIFO is 1/2 full or less. + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_TX|SSI_RIS_ROR); +#else + regval |= SSI_IM_TX; +#endif + } + else + { + /* Yes.. Disable the Tx FIFO interrupt. The final stages of + * the transfer will be driven by Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_TX|SSI_RIS_ROR); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ + } + return ntxd; +} + +#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +/**************************************************************************** + * Name: ssi_performrx + * + * Description: + * Transfer as many bytes as possible from the Rx FIFO to the user Rx + * buffer (if one was provided). + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_performrx(struct lm3s_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + + /* Loop while data is available in the Rx FIFO */ + + while (!ssi_rxfifoempty(priv)) + { + /* Have all of the requested words been transferred from the Rx FIFO? */ + + if (priv->nrxwords < priv->nwords) + { + /* No.. Read more data from Rx FIFO */ + + priv->rxword(priv); + priv->nrxwords++; + } + } + + /* The Rx FIFO is now empty. While there is Tx data to be sent, the + * transfer will be driven by Tx FIFO interrupts. The final part + * of the transfer is driven by Rx FIFO interrupts only. + */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) + { + /* There are no more outgoing words to send, but there are + * additional incoming words expected (I would think that this + * a real corner case, be we will handle it with an extra + * interrupt, probably an Rx timeout). + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR); +#else + regval |= (SSI_IM_RX|SSI_IM_RT); +#endif + } + else + { + /* No.. there are either more Tx words to send or all Rx words + * have received. Disable Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_RX|SSI_IM_RT); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ +} + +/**************************************************************************** + * Name: ssi_transfer + * + * Description: + * Exchange a block data with the SPI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords) +{ +#ifndef CONFIG_SSI_POLLWAIT + irqstate_t flags; +#endif + int ntxd; + + ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords); + + /* Set up to perform the transfer */ + + priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */ + priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */ + priv->ntxwords = nwords; /* Number of words left to send */ + priv->nrxwords = 0; /* Number of words received */ + priv->nwords = nwords; /* Total number of exchanges */ + + /* Set up the low-level data transfer function pointers */ + + if (priv->nbits > 8) + { + priv->txword = ssi_txuint16; + priv->rxword = ssi_rxuint16; + } + else + { + priv->txword = ssi_txuint8; + priv->rxword = ssi_rxuint8; + } + + if (!txbuffer) + { + priv->txword = ssi_txnull; + } + + if (!rxbuffer) + { + priv->rxword = ssi_rxnull; + } + + /* Prime the Tx FIFO to start the sequence (saves one interrupt). + * At this point, all SSI interrupts should be disabled, but the + * operation of ssi_performtx() will set up the interrupts + * approapriately (if nwords > TxFIFO size). + */ + +#ifndef CONFIG_SSI_POLLWAIT + flags = irqsave(); + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + ntxd = ssi_performtx(priv); + + /* For the case where nwords < Tx FIFO size, ssi_performrx will + * configure interrupts correctly for the final phase of the + * the transfer. + */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Wait for the transfer to complete. Since there is no handshake + * with SPI, the following should complete even if there are problems + * with the transfer, so it should be safe with no timeout. + */ + + ssivdbg("Waiting for transfer complete\n"); + irqrestore(flags); + do + { + ssi_semtake(&priv->xfrsem); + } + while (priv->nrxwords < priv->nwords); + ssidbg("Transfer complete\n"); + +#else + /* Perform the transfer using polling logic. This will totally + * dominate the CPU until the transfer is complete. Only recommended + * if (1) your SPI is very fast, and (2) if you only use very short + * transfers. + */ + + do + { + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + /* If there are other threads at this same priority level, + * the following may help: + */ + + sched_yield(); + } + while (priv->nrxwords < priv->nwords); +#endif + return OK; +} + +/**************************************************************************** + * Name: ssi_mapirq + * + * Description: + * Map an IRQ number into the appropriate SSI device + * + * Input Parameters: + * irq - The IRQ number to be mapped + * + * Returned Value: + * On success, a reference to the private data structgure for this IRQ. + * NULL on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm3s_ssidev_s *ssi_mapirq(int irq) +{ + switch (irq) + { +#ifndef CONFIG_SSI0_DISABLE + case LM3S_IRQ_SSI0: + return &g_ssidev[SSI0_NDX]; +#endif +#ifndef CONFIG_SSI1_DISABLE + case LM3S_IRQ_SSI1: + return &g_ssidev[SSI1_NDX]; +#endif + default: + return NULL; + } +} +#endif + +/**************************************************************************** + * Name: ssi_interrupt + * + * Description: + * Exchange a block data with the SSI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static int ssi_interrupt(int irq, void *context) +{ + struct lm3s_ssidev_s *priv = ssi_mapirq(irq); + uint32_t regval; + int ntxd; + + DEBUGASSERT(priv != NULL); + + /* Clear pending interrupts */ + + regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); + ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); + + /* Check for Rx FIFO overruns */ + +#ifdef CONFIG_DEBUG + if ((regval & SSI_RIS_ROR) != 0) + { + lldbg("Rx FIFO Overrun!\n"); + } +#endif + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Check if the transfer is complete */ + + if (priv->nrxwords >= priv->nwords) + { + /* Yes.. Disable all SSI interrupt sources */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Wake up the waiting thread */ + + ssidbg("Transfer complete\n"); + ssi_semgive(&priv->xfrsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency) +{ + uint32_t maxdvsr; + uint32_t cpsdvsr; + uint32_t regval; + uint32_t scr; + uint32_t actual; + + ssidbg("frequency: %d\n", frequency); + DEBUGASSERT(frequency); + + /* Has the frequency changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (frequency != priv->frequency) + { +#endif + /* "The serial bit rate is derived by dividing down the input clock + * (FSysClk). The clock is first divided by an even prescale value + * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale + * (SSI_CPSR) register ... The clock is further divided by a value + * from 1 to 256, which is 1 + SCR, where SCR is the value programmed + * i n the SSI Control0 (SSICR0) register ... + * + * "The frequency of the output clock SSIClk is defined by: + * + * "SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) + * + * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz, + * the module may not be able to operate at that speed. For master mode, + * the system clock must be at least two times faster than the SSIClk. + * For slave mode, the system clock must be at least 12 times faster + * than the SSIClk." + */ + + if (frequency > SYSCLK_FREQUENCY/2) + { + frequency = SYSCLK_FREQUENCY/2; + } + + /* Find optimal values for CPSDVSR and SCR. This loop is inefficient, + * but should not have to execute many times. + * + * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000. + * + * maxcvsr = 125 + * 1. cpsdvsr = 2, scr = 61 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (62)) = 403,226 + * + * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000. + * + * maxcvsr = 2 + * 1. cpsdvsr = 2, scr = 0 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (1)) = 25,000,000 + */ + + maxdvsr = SYSCLK_FREQUENCY / frequency; + cpsdvsr = 0; + do + { + cpsdvsr += 2; + scr = (maxdvsr / cpsdvsr) - 1; + } + while (scr > 255); + + /* Set CPDVSR */ + + DEBUGASSERT(cpsdvsr < 255); + ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); + + /* Set SCR */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_SCR_MASK; + regval |= (scr << SSI_CR0_SCR_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); + + /* Calcluate the actual frequency */ + + actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1)); + + /* Save the frequency selection so that subsequent reconfigurations will be + * faster. + */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; + } + return priv->actual; +#else + return actual; +#endif +} + +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + uint32_t actual; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + actual = ssi_setfrequencyinternal(priv, frequency); + ssi_enable(priv, enable); + return actual; +} + +/**************************************************************************** + * Name: ssi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode) +{ + uint32_t modebits; + uint32_t regval; + + ssidbg("mode: %d\n", mode); + DEBUGASSERT(priv); + + /* Has the number of bits per word changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Select the CTL register bits based on the selected mode */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + modebits = 0; + break; + + case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + modebits = SSI_CR0_SPH; + break; + + case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + modebits = SSI_CR0_SPO; + break; + + case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + modebits = SSI_CR0_SPH|SSI_CR0_SPO; + break; + + default: + return; + } + + /* Then set the selected mode: Freescale SPI format, mode0-3 */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); + regval |= modebits; + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + /* Save the mode so that subsequent re-configuratins will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setmodeinternal(priv, mode); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits) +{ + uint32_t regval; + + ssidbg("nbits: %d\n", nbits); + DEBUGASSERT(priv); + if (nbits != priv->nbits && nbits >=4 && nbits <= 16) + { + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_DSS_MASK; + regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + priv->nbits = nbits; + } +} + +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setbitsinternal(priv, nbits); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev; + uint16_t response = 0; + + (void)ssi_transfer(priv, &wd, &response, 1); + return response; +} + +/**************************************************************************** + * Name: SPI_EXCHANGE + * + * Description: + * Exahange a block of data from SPI. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords); +} +#endif + +/************************************************************************* + * Name: ssi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: ssi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize common parts the selected SPI port. Initialization of + * chip select GPIOs must have been performed by board specific logic + * prior to calling this function. Specifically: GPIOs should have + * been configured for output, and all chip selects disabled. + * + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, + * If multiple devices on on the bus, then multiple chip selects will be + * required. Theregore, all GPIO chip management is deferred to board- + * specific logic. + * + * Input Parameter: + * Port number (for hardware that has mutiple SSI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + struct lm3s_ssidev_s *priv; + irqstate_t flags; + uint8_t regval; + + ssidbg("port: %d\n", port); + + /* Set up for the selected port */ + + flags = irqsave(); + switch (port) + { +#ifndef CONFIG_SSI0_DISABLE + case 0: + /* Select SSI0 */ + + priv = &g_ssidev[SSI0_NDX]; + + /* Enable the SSI0 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI0; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the + * logic in this file makes no assumptions about chip select) + */ + + lm3s_configgpio(GPIO_SSI0_CLK); /* PA2: SSI0 clock (SSI0Clk) */ + /* lm3s_configgpio(GPIO_SSI0_FSS); PA3: SSI0 frame (SSI0Fss) */ + lm3s_configgpio(GPIO_SSI0_RX); /* PA4: SSI0 receive (SSI0Rx) */ + lm3s_configgpio(GPIO_SSI0_TX); /* PA5: SSI0 transmit (SSI0Tx) */ + break; +#endif /* CONFIG_SSI0_DISABLE */ + +#ifndef CONFIG_SSI1_DISABLE + case 1: + /* Select SSI0 */ + + priv = &g_ssidev[SSI1_NDX]; + + /* Enable the SSI1 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI1; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI1 GPIOs */ + + lm3s_configgpio(GPIO_SSI1_CLK); /* PE0: SSI1 clock (SSI1Clk) */ + /* lm3s_configgpio(GPIO_SSI1_FSS); PE1: SSI1 frame (SSI1Fss) */ + lm3s_configgpio(GPIO_SSI1_RX); /* PE2: SSI1 receive (SSI1Rx) */ + lm3s_configgpio(GPIO_SSI1_TX); /* PE3: SSI1 transmit (SSI1Tx) */ + break; +#endif /* CONFIG_SSI1_DISABLE */ + + default: + irqrestore(flags); + return NULL; + } + + /* Initialize the state structure */ + +#ifndef CONFIG_SSI_POLLWAIT + sem_init(&priv->xfrsem, 0, 0); +#endif +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + + /* Set all CR1 fields to reset state. This will be master mode. */ + + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); + + /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ + + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); + + /* Set the initial mode to mode 0. The application may override + * this initial setting using the setmode() method. + */ + + ssi_setmodeinternal(priv, SPIDEV_MODE0); + + /* Set the initial data width to 8-bits. The application may + * override this initial setting using the setbits() method. + */ + + ssi_setbitsinternal(priv, 8); + + /* Pick some initialize clock frequency. 400,000Hz is the startup + * MMC/SD frequency used for card detection. The application may + * override this setting using the setfrequency() method. + */ + + ssi_setfrequencyinternal(priv, 400000); + + /* Disable all SSI interrupt sources. They will be enabled only + * while there is an SSI transfer in progress. + */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Attach the interrupt */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + irq_attach(priv->irq, (xcpt_t)ssi_interrupt); +#else + irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + /* Enable the SSI for operation */ + + ssi_enable(priv, SSI_CR1_SSE); + + /* Enable SSI interrupts (They are still disabled at the source). */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(SSI_IRQ); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + irqrestore(flags); + return (FAR struct spi_dev_s *)priv; +} + +#endif /* NSSI_ENABLED > 0 */ diff --git a/nuttx/arch/arm/src/lm/lm3s_start.c b/nuttx/arch/arm/src/lm/lm3s_start.c new file mode 100644 index 000000000..4dfe92844 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_start.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_start.c + * arch/arm/src/chip/lm3s_start.c + * + * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_lowputc.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern void lm3s_vectors(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + up_clockconfig(); + up_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + showprogress('B'); + + /* Move the intialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + showprogress('C'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + showprogress('D'); + + /* Initialize onboard resources */ + + lm3s_boardinitialize(); + showprogress('E'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + os_start(); + + /* Shoulnd't get here */ + + for(;;); +} diff --git a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c new file mode 100644 index 000000000..87545bec7 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c @@ -0,0 +1,315 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_syscontrol.c + * arch/arm/src/chip/lm3s_syscontrol.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "chip.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RCC_OSCMASK (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN) +#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2) +#define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK) +#define FAST_OSCDELAY (512*1024) +#define SLOW_OSCDELAY (4*1024) +#define PLLLOCK_DELAY (32*1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_delay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm3s_delay(uint32_t delay) +{ + __asm__ __volatile__("1:\n" + "\tsubs %0, #1\n" + "\tbne 1b\n" + : "=r"(delay) : "r"(delay)); +} + +/**************************************************************************** + * Name: lm3s_oscdelay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2) +{ + /* Wait for the oscillator to stabilize. A smaller delay is used if the + * current clock rate is very slow. + */ + + uint32_t delay = FAST_OSCDELAY; + + /* Are we currently using RCC2? */ + + if ((rcc2 & SYSCON_RCC2_USERCC2) != 0) + { + uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK; + if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) || + (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ)) + { + delay = SLOW_OSCDELAY; + } + } + + /* No.. using srce in RCC */ + + else + { + uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK; + if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ) + { + delay = SLOW_OSCDELAY; + } + } + + /* Then delay that number of loops */ + + lm3s_delay(delay); +} + +/**************************************************************************** + * Name: lm3s_plllock + * + * Description: + * The new RCC values have been selected... wait for the PLL to lock on + * + ****************************************************************************/ + +static inline void lm3s_plllock(void) +{ + volatile uint32_t delay; + + /* Loop until the lock is achieved or until a timeout occurs */ + + for (delay = PLLLOCK_DELAY; delay > 0; delay--) + { + /* Check if the PLL is locked on */ + + if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) + { + /* Yes.. return now */ + + return; + } + } + + /* If we get here, then PLL lock was not achieved */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2) +{ + uint32_t rcc; + uint32_t rcc2; + + /* Get the current values of the RCC and RCC2 registers */ + + rcc = getreg32(LM3S_SYSCON_RCC); + rcc2 = getreg32(LM3S_SYSCON_RCC2); + + /* Temporarily bypass the PLL and system clock dividers */ + + rcc |= SYSCON_RCC_BYPASS; + rcc &= ~(SYSCON_RCC_USESYSDIV); + putreg32(rcc, LM3S_SYSCON_RCC); + + rcc2 |= SYSCON_RCC2_BYPASS2; + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* We are probably using the main oscillator. The main oscillator is disabled on + * reset and so probably must be enabled here. The internal oscillator is enabled + * on rest and if that is selected, most likely nothing needs to be done. + */ + + if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) || + ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS))) + { + /* Enable any selected osciallators (but don't disable any yet) */ + + rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); + putreg32(rcc, LM3S_SYSCON_RCC); + + /* Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + */ + + lm3s_oscdelay(rcc, rcc2); + } + + /* Set the new crystal value, oscillator source and PLL configuration */ + + rcc &= ~RCC_XTALMASK; + rcc |= newrcc & RCC_XTALMASK; + + rcc2 &= ~RCC2_XTALMASK; + rcc2 |= newrcc2 & RCC2_XTALMASK; + + /* Clear the PLL lock interrupt */ + + putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); + + /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC + * is currently enabled. + */ + + if (rcc2 & SYSCON_RCC2_USERCC2) + { + putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc, LM3S_SYSCON_RCC); + } + else + { + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + } + + /* Wait for the new crystal value and oscillator source to take effect */ + + lm3s_delay(16); + + /* Set the requested system divider and disable the non-selected osciallators */ + + rcc &= ~RCC_DIVMASK; + rcc |= newrcc & RCC_DIVMASK; + + rcc2 &= ~RCC2_DIVMASK; + rcc2 |= newrcc2 & RCC2_DIVMASK; + + /* Will the PLL output be used to clock the system? */ + + if ((newrcc & SYSCON_RCC_BYPASS) == 0) + { + /* Yes, wail untill the PLL is locked */ + + lm3s_plllock(); + + /* Then enable the PLL */ + + rcc &= ~SYSCON_RCC_BYPASS; + rcc2 &= ~SYSCON_RCC2_BYPASS2; + } + + /* Now we can set the final RCC/RCC2 values */ + + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* Wait for the system divider to be effective */ + + lm3s_delay(6); +} + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void) +{ +#ifdef CONFIG_LM3S_REVA2 + /* Some early silicon returned an increase LDO voltage or 2.75V to work + * around a PLL bug + */ + + putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); +#endif + + /* Set the clocking to run with the default settings provided in the board.h + * header file + */ + + lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_timerisr.c b/nuttx/arch/arm/src/lm/lm3s_timerisr.c new file mode 100644 index 000000000..823d810da --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_timerisr.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h + * header file. + */ + +#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify taht the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(LM3S_IRQ_SYSTICK); +} diff --git a/nuttx/arch/arm/src/lm/lm3s_vectors.S b/nuttx/arch/arm/src/lm/lm3s_vectors.S new file mode 100644 index 000000000..fe92fc954 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_vectors.S @@ -0,0 +1,805 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_vectors.S + * arch/arm/src/chip/lm3s_vectors.S + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/* Memory Map: + * + * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader) + * 0x0002:0000 - Address of vectors if using bootloader + * 0x0003:ffff - End of flash + * 0x2000:0000 - Start of SRAM and start of .data (_sdata) + * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap + * 0x2000:ffff - End of SRAM and end of heap + */ + +#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) + +/* The Cortex-M3 return from interrupt is unusual. We provide the following special + * address to the BX instruction. The particular value also forces a return to + * thread mode and covers state from the main stack point, the MSP (vs. the MSP). + */ + +#define EXC_RETURN 0xfffffff9 + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .globl __start + + .syntax unified + .thumb + .file "lm3s_vectors.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 + * registers on the stack, then branches to an instantantiation of the following + * macro. This macro simply loads the IRQ number into R0, then jumps to the common + * IRQ handling logic. + */ + + .macro HANDLER, label, irqno + .thumb_func +\label: + mov r0, #\irqno + b lm3s_irqcommon + .endm + +/************************************************************************************ + * Vectors + ************************************************************************************/ + + .section .vectors, "ax" + .code 16 + .align 2 + .globl lm3s_vectors + .type lm3s_vectors, function + +lm3s_vectors: + +/* Processor Exceptions */ + + .word IDLE_STACK /* Vector 0: Reset stack pointer */ + .word __start /* Vector 1: Reset vector */ + .word lm3s_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */ + .word lm3s_hardfault /* Vector 3: Hard fault */ + .word lm3s_mpu /* Vector 4: Memory management (MPU) */ + .word lm3s_busfault /* Vector 5: Bus fault */ + .word lm3s_usagefault /* Vector 6: Usage fault */ + .word lm3s_reserved /* Vector 7: Reserved */ + .word lm3s_reserved /* Vector 8: Reserved */ + .word lm3s_reserved /* Vector 9: Reserved */ + .word lm3s_reserved /* Vector 10: Reserved */ + .word lm3s_svcall /* Vector 11: SVC call */ + .word lm3s_dbgmonitor /* Vector 12: Debug monitor */ + .word lm3s_reserved /* Vector 13: Reserved */ + .word lm3s_pendsv /* Vector 14: Pendable system service request */ + .word lm3s_systick /* Vector 15: System tick */ + +/* External Interrupts */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_reserved /* Vector 25: Reserved */ + .word lm3s_reserved /* Vector 26: Reserved */ + .word lm3s_reserved /* Vector 27: Reserved */ + .word lm3s_reserved /* Vector 28: Reserved */ + .word lm3s_reserved /* Vector 29: Reserved */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_gpioh /* Vector 48: GPIO Port H */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_ssi1 /* Vector 50: SSI 1 */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_reserved /* Vector 54: Reserved */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_reserved /* Vector 25: Reserved */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_reserved /* Vector 27: Reserved */ + .word lm3s_reserved /* Vector 28: Reserved */ + .word lm3s_reserved /* Vector 29: Reserved */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_reserved /* Vector 51: Reserved */ + .word lm3s_reserved /* Vector 52: Reserved */ + .word lm3s_reserved /* Vector 53: Reserved */ + .word lm3s_reserved /* Vector 54: Reserved */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_reserved /* Vector 59: Reserved */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_uart2 /* Vector 49: UART 2 */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_cmp2 /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_gpioh /* Vector 48: GPIO Port H */ + .word lm3s_uart2 /* Vector 49: UART 2 */ + .word lm3s_ssi1 /* Vector 50: SSI 1 */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_can0 /* Vector 55: CAN 0 */ + .word lm3s_can1 /* Vector 56: CAN 1 */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_reserved /* Vector 59: Reserved */ + .word lm3s_usb /* Vector 60: USB */ + .word lm3s_pwm3 /* Vector 61: PWM 3 */ + .word lm3s_udmasoft /* Vector 62: uDMA Software */ + .word lm3s_udmaerror /* Vector 63: uDMA Error */ + .word lm3s_adc1_0 /* Vector 64: ADC1 Sequence 0 */ + .word lm3s_adc1_1 /* Vector 65: ADC1 Sequence 1 */ + .word lm3s_adc1_2 /* Vector 66: ADC1 Sequence 2 */ + .word lm3s_adc1_3 /* Vector 67: ADC1 Sequence 3 */ + .word lm3s_i2s0 /* Vector 68: I2S 0 */ + .word lm3s_epi /* Vector 69: Reserved */ + .word lm3s_gpioj /* Vector 70: GPIO J */ + .word lm3s_reserved /* Vector 71: Reserved */ + #elif defined(CONFIG_ARCH_CHIP_LM3S8962) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_reserved /* Vector 42: Reserved */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_reserved /* Vector 53: Reserved*/ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_can0 /* Vector 55: Can Controller */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + .size lm3s_vectors, .-lm3s_vectors + +/************************************************************************************ + * .text + ************************************************************************************/ + + .text + .type handlers, function + .thumb_func +handlers: + HANDLER lm3s_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ + HANDLER lm3s_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ + HANDLER lm3s_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ + HANDLER lm3s_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ + HANDLER lm3s_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ + HANDLER lm3s_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ + HANDLER lm3s_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ + HANDLER lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ + HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ + HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm3s_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ + HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm3s_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_usb, LM3S_IRQ_USB /* Vector 60: USB */ + HANDLER lm3s_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ + HANDLER lm3s_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ + HANDLER lm3s_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ + HANDLER lm3s_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ + HANDLER lm3s_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ + HANDLER lm3s_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ + HANDLER lm3s_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ + HANDLER lm3s_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ + HANDLER lm3s_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ + HANDLER lm3s_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: + * + * REG_XPSR + * REG_R15 + * REG_R14 + * REG_R12 + * REG_R3 + * REG_R2 + * REG_R1 + * MSP->REG_R0 + * + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP + */ + +lm3s_irqcommon: + + /* Complete the context save */ + +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else + mrs r1, msp /* R1=The main stack pointer */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ + mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else + stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif + + /* Disable interrupts, select the stack to use for interrupt handling + * and call up_doirq to handle the interrupt + */ + + cpsid i /* Disable further interrupts */ + + /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt + * stack pointer. The way that this is done here prohibits nested interrupts! + * Otherwise, we will re-use the main stack for interrupt level processing. + */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + ldr sp, =g_intstackbase + str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ +#else + mov sp, r1 /* We are using the main stack pointer */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + mov r1, sp /* Recover R1=main stack pointer */ +#endif + + /* On return from up_doirq, R0 will hold a pointer to register context + * array to use for the interrupt return. If that return value is the same + * as current stack pointer, then things are relatively easy. + */ + + cmp r0, r1 /* Context switch? */ + beq 1f /* Branch if no context switch */ + + /* We are returning with a pending context switch. This case is different + * because in this case, the register save structure does not lie on the + * stack but, rather, are within a TCB structure. We'll have to copy some + * values to the stack. + */ + + add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ + ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ + ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ + stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif + b 2f /* Re-join common logic */ + + /* We are returning with no context switch. We simply need to "unwind" + * the same stack frame that we created + */ +1: +#ifdef CONFIG_NUTTX_KERNEL + ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif +2: +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else + msr msp, r1 /* Recover the return MSP value */ + + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). + */ + + ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + + msr primask, r3 /* Restore interrupts */ + + /* Always return with R14 containing the special value that will: (1) + * return to thread mode, and (2) continue to use the MSP + */ + + bx r14 /* And return */ + .size handlers, .-handlers + +/************************************************************************************ + * Name: up_interruptstack/g_intstackbase + * + * Description: + * Shouldn't happen + * + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .global g_intstackbase + .align 4 +up_interruptstack: + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) +g_intstackbase: + .size up_interruptstack, .-up_interruptstack +#endif + +/************************************************************************************ + * .rodata + ************************************************************************************/ + + .section .rodata, "a" + +/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end + * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS + * and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that + * the system boots on and, eventually, becomes the idle, do nothing task that runs + * only when there is nothing else to run. The heap continues from there until the + * end of memory. See g_heapbase below. + */ + + .globl g_heapbase + .type g_heapbase, object +g_heapbase: + .long _ebss+CONFIG_IDLETHREAD_STACKSIZE + .size g_heapbase, .-g_heapbase + + .end diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h new file mode 100644 index 000000000..29fe4fd17 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ethernet.h @@ -0,0 +1,103 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_ethernet.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_ETHERNET_H +#define __ARCH_ARM_SRC_LM_LM_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#if LM3S_NETHCONTROLLERS > 1 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface. If the LM3S chip + * supports multiple Ethernet controllers, then bould specific logic + * must implement up_netinitialize() and call this function to initialize + * the desiresed interfaces. + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int lm3s_ethinitialize(int intf); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* LM3S_NETHCONTROLLERS > 1 */ +#endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/lm_gpio.h b/nuttx/arch/arm/src/lm/lm_gpio.h new file mode 100644 index 000000000..9577fd926 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_gpio.h @@ -0,0 +1,223 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_GPIO_H +#define __ARCH_ARM_SRC_LM_LM_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit-encoded input to lm3s_configgpio() *******************************************/ + +/* Encoding: + * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB + * + * These bits set the primary function of the pin: + * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */ +#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */ +#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */ +#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */ +#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */ +#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */ +#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */ +#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */ +#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */ +#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */ +#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */ +#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT + +/* That primary may be modified by the following options + * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */ +#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT) +#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */ +#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */ +#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */ +#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */ +#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC + +#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) +#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */ +#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */ +#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */ +#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */ +#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */ +#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */ +#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */ + +/* If the pin is an interrupt, then the following options apply + * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */ +#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT) +#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */ +#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */ +#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */ +#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ +#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ + +/* If the pin is an GPIO digital output, then this identifies the initial output value: + * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn + */ + +#define GPIO_VALUE_SHIFT 7 /* Bit 7: If output, inital value of output */ +#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) +#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ +#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ + +/* This identifies the GPIO port + * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn + */ + +#define GPIO_PORT_SHIFT 3 /* Bit 3-6: Port number */ +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ +#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ +#define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */ + +/* This identifies the bit in the port: + * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB + */ + +#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */ +#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm3s_configgpio(uint32_t cfgset); + +/**************************************************************************** + * Name: lm3s_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lm3s_gpiowrite(uint32_t pinset, bool value); + +/**************************************************************************** + * Name: lm3s_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm3s_gpioread(uint32_t pinset, bool value); + +/**************************************************************************** + * Function: lm3s_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm3s_dumpgpio(uint32_t pinset, const char *msg); + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int weak_function gpio_irqinitialize(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.h b/nuttx/arch/arm/src/lm/lm_lowputc.h new file mode 100644 index 000000000..b384bbd80 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_lowputc.h @@ -0,0 +1,87 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_lowputc.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_LOWPUTC_H +#define __ARCH_ARM_SRC_LM_LM_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization. + * + ****************************************************************************/ + +void up_lowsetup(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_LOWPUTC_H */ diff --git a/nuttx/arch/arm/src/lm/lm_ssi.h b/nuttx/arch/arm/src/lm/lm_ssi.h new file mode 100644 index 000000000..4e7119898 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ssi.h @@ -0,0 +1,114 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_ssi.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_SSI_H +#define __ARCH_ARM_SRC_LM_LM_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * The external functions, lm3s_spiselect, lm3s_spistatus, and + * lm3s_spicmddata must be provided by board-specific logic. These are + * implementations of the select, status, and cmddata methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All other methods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. These functions will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide + * the lm3s_spicmddata() function in your board-specific logic. This + * functions will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 4. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 5. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.h b/nuttx/arch/arm/src/lm/lm_syscontrol.h new file mode 100644 index 000000000..79cc2349d --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_syscontrol.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm3s/Kconfig b/nuttx/arch/arm/src/lm3s/Kconfig deleted file mode 100644 index aaf8342fa..000000000 --- a/nuttx/arch/arm/src/lm3s/Kconfig +++ /dev/null @@ -1,199 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see misc/tools/kconfig-language.txt. -# - -comment "LM3S Configuration Options" - -choice - prompt "LM3S Chip Selection" - default ARCH_CHIP_LM3S6965 - depends on ARCH_CHIP_LM3S - -config ARCH_CHIP_LM3S6918 - bool "LM3S6918" - select LM3S_HAVE_SSI1 - -config ARCH_CHIP_LM3S9B96 - bool "LM3S9B96" - -config ARCH_CHIP_LM3S6432 - bool "LM3S6432" - -config ARCH_CHIP_LM3S6965 - bool "LM3S6965" - -config ARCH_CHIP_LM3S8962 - bool "LM3S8962" - -endchoice - -config LM3S_HAVE_SSI1 - bool - -config LM3S_REVA2 - bool "Rev A2" - default n - ---help--- - Some early silicon returned an increase LDO voltage or 2.75V to work - around a PLL bug - -config LM3S_DFU - bool "DFU" - default y - -menu "Select LM3S Peripheral Support" - -config LM3S_UART0 - bool "UART0" - select ARCH_HAVE_UART0 - default n - -config LM3S_UART1 - bool "UART1" - select ARCH_HAVE_UART1 - default n - -config SSI0_DISABLE - bool "Disable SSI0" - default y - -config SSI1_DISABLE - bool "Disable SSI1" - default y - -config LM3S_UART2 - bool "UART2" - select ARCH_HAVE_UART2 - default n - -config LM3S_ETHERNET - bool "LM3S Ethernet" - default n - ---help--- - This must be set (along with NET) to build the LM3S Ethernet driver. - -endmenu - -menu "Disable GPIO Interrupts" - -config LM3S_DISABLE_GPIOA_IRQS - bool "Disable GPIOA IRQs" - default n - -config LM3S_DISABLE_GPIOB_IRQS - bool "Disable GPIOB IRQs" - default n - -config LM3S_DISABLE_GPIOC_IRQS - bool "Disable GPIOC IRQs" - default n - -config LM3S_DISABLE_GPIOD_IRQS - bool "Disable GPIOD IRQs" - default n - -config LM3S_DISABLE_GPIOE_IRQS - bool "Disable GPIOE IRQs" - default n - -config LM3S_DISABLE_GPIOF_IRQS - bool "Disable GPIOF IRQs" - default n - -config LM3S_DISABLE_GPIOG_IRQS - bool "Disable GPIOG IRQs" - default n - -config LM3S_DISABLE_GPIOH_IRQS - bool "Disable GPIOH IRQs" - default n - -config LM3S_DISABLE_GPIOJ_IRQS - bool "Disable GPIOJ IRQs" - default n - -endmenu - -if LM3S_ETHERNET -menu "LM3S Ethernet Configuration" - -config LM3S_ETHLEDS - bool "Ethernet LEDs" - default n - ---help--- - Enable to use Ethernet LEDs on the board. - -config LM3S_BOARDMAC - bool "Board MAC" - default n - ---help--- - If the board-specific logic can provide a MAC address (via - lm3s_ethernetmac()), then this should be selected. - -config LM3S_ETHHDUPLEX - bool "Force Half Duplex" - default n - ---help--- - Set to force half duplex operation - -config LM3S_ETHNOAUTOCRC - bool "Disable auto-CRC" - default n - ---help--- - Set to suppress auto-CRC generation - -config LM3S_ETHNOPAD - bool "Disable Tx Padding" - default n - ---help--- - Set to suppress Tx padding - -config LM3S_MULTICAST - bool "Enable Multicast" - default n - ---help--- - Set to enable multicast frames - -config LM3S_PROMISCUOUS - bool "Enable Promiscuous Mode" - default n - ---help--- - Set to enable promiscuous mode - -config LM3S_TIMESTAMP - bool "Enable Timestamping" - default n - -config LM3S_BADCRC - bool "Enable Bad CRC Rejection" - default n - ---help--- - Set to enable bad CRC rejection. - -config M3S_DUMPPACKET - bool "Dump Packets" - default n - ---help--- - Dump each packet received/sent to the console. - -endmenu -endif - -if !SSI0_DISABLE || !SSI1_DISABLE -menu "LM3S SSI Configuration" - -config SSI_POLLWAIT - bool "Poll Wait (No-Interrupt) Mode" - default y - -config SSI_TXLIMIT - int "Tx Limit" - default 4 - ---help--- - Default of 4 assumes half of the 8 entry FIFO - -endmenu -endif - - diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs deleted file mode 100644 index 66b8f5658..000000000 --- a/nuttx/arch/arm/src/lm3s/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# arch/arm/src/lm3s/Make.defs -# -# Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -HEAD_ASRC = lm3s_vectors.S - -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ - vfork.S -CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ - up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ - up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \ - up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ - up_releasepending.c up_releasestack.c up_reprioritizertr.c \ - up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \ - up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ - up_vfork.c - -ifeq ($(CONFIG_ARCH_MEMCPY),y) -CMN_ASRCS += up_memcpy.S -endif - -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += up_elf.c -endif - -CHIP_ASRCS = -CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \ - lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \ - lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c - -ifdef CONFIG_NET -CHIP_CSRCS += lm3s_ethernet.c -endif diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h deleted file mode 100644 index 481a9be15..000000000 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ /dev/null @@ -1,83 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_H -#define __ARCH_ARM_SRC_LM3S_CHIP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Then get all of the register definitions */ - -#include "chip/lm_memorymap.h" /* Memory map */ -#include "chip/lm3s_syscontrol.h" /* System control module */ -#include "chip/lm3s_gpio.h" /* GPIO modules */ -#include "chip/lm3s_uart.h" /* UART modules */ -#include "chip/lm3s_i2c.h" /* I2C modules */ -#include "chip/lm3s_ssi.h" /* SSI modules */ -#include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ -#include "chip/lm3s_flash.h" /* FLASH */ - -/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism - * will only look at the upper N bits of the 8-bit priority level (where N is 3 for - * the Stellaris family), so any prioritization must be performed in those bits. - * The default priority level is set to the middle value - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h deleted file mode 100644 index 5b54d44ac..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_epi.h +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_epi.h - * - * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. - * Author: Max Neklyudov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* External Peripheral Interface Register Offsets ***********************************/ - -#define LM3S_EPI_CFG_OFFSET 0x000 -#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 -#define LM3S_EPI_ADDRMAP_OFFSET 0x01C -#define LM3S_EPI_STAT_OFFSET 0x060 -#define LM3S_EPI_BAUD_OFFSET 0x004 - -/* External Peripheral Interface Register Addresses *********************************/ - -#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) -#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) -#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) -#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) -#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) - -/* External Peripheral Interface Register Bit Definitions ***************************/ - -/* EPI Configuration (EPICFG), offset 0x000 */ - -#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ -#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) -# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ - -/* EPI Address Map (EPIADDRMAP), offset 0x01C */ - -#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ -#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) -#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ -#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) - -/* EPI Status (EPISTAT), offset 0x060 */ - -#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ -#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) - -/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ - -#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ -#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) -#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ -#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) -# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) -#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ -#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) - -/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ - -#define EPI_BAUD_COUNT0_SHIFT 0 -#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) -# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h deleted file mode 100644 index 940686e7d..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_ethernet.h - * - * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Ethernet Controller Register Offsets *********************************************/ - -/* Ethernet MAC Register Offsets */ - -#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ -#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ -#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ -#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ -#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ -#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ -#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ -#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ -#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ -#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ -#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ -#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ -#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ -#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ -#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ -#endif - -/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ - -/* Ethernet Controller Register Addresses *******************************************/ - -#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) -#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) -#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) -#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) -#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) -#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) -#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) -#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) -#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) -#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) -#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) -#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) -#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) -#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) -#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) -#endif - -/* Memory Mapped MII Management Registers */ - -#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) -#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) -#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) -#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) -#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) -#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) -#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) -#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) -#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) -#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) -#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) -#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) -#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) - -/* Ethernet Controller Register Bit Definitions *************************************/ - -/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ - -#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ -#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ -#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ -#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ -#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ -#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ -#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ - -#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ -#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ -#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ -#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ -#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ -#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ -#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ - -/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ - -#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ -#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ -#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ -#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ -#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ -#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ -#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ -#define MAC_IM_ALLINTS 0x7f - -/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ - -#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ -#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ -#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ -#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ -#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ - -/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ - -#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ -#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ -#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ -#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ - -/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ - -#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ - -/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ - -#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ -#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ -#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ -#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) - -/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ - -#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ - -/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ - -#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ - -/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ - -#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ - -/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ - -#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ - -/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ - -#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h deleted file mode 100644 index 2bd8956b0..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_flash.h +++ /dev/null @@ -1,128 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_flash.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* FLASH register offsets ***********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ -#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ -#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ -#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ -#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ -#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ -#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ -#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ -#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ -#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ -#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ -#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ -#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ -#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ -#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ -#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ -#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ -#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ -#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ - -/* FLASH register addresses *********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) -#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) -#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) -#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) -#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) -#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) -#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) -#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) -#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) -#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) -#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) -#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) -#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) -#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) -#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) -#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) -#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) -#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) -#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) - -/* FLASH register bit defitiions ****************************************************/ -/* To be provided */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h deleted file mode 100644 index 7253c1e7a..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_gpio.h +++ /dev/null @@ -1,395 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_gpio.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* GPIO Register Offsets ************************************************************/ - -#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ -#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ -#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ -#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ -#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ -#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ -#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ -#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ -#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ -#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ -#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ -#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ -#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ -#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ -#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ -#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ -#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ -#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ -#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ -#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ -#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ -#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ -#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ -#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ -#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ -#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ -#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ -#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ -#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ -#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ -#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ -#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ - -/* GPIO Register Addresses **********************************************************/ - -#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h deleted file mode 100644 index 71ebe8fcf..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_i2c.h +++ /dev/null @@ -1,247 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_i2c.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* I2C Register Offsets *************************************************************/ - -/* I2C Master */ - -#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ -#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ -#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ -#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ -#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ -#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ -#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ -#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ -#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ - -/* I2C Slave */ - -#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ -#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ -#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ -#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ -#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ -#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ -#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ - -/* I2C Register Addresses ***********************************************************/ - -#if LM3S_NI2C > 0 - -/* I2C Master */ - -#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) -#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) - -/* I2C Slave */ - -#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) -#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) - -/* I2C0 Master */ - -#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C0 Slave */ - -#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) - -#if LM3S_NI2C > 1 - -/* I2C1 Master */ - -#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C1 Slave */ - -#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) - -#endif -#endif - -/* I2C_Register Bit Definitions *****************************************************/ - -/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ - -#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ -#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ -#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) - -/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ - -#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ -#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ -#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ -#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ -#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ -#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ -#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ - -#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ -#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ -#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ -#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ - -/* I2C Master Data (I2CM_DR), offset 0x008 */ - -#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ - -/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ - -#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ - -/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ - -#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ - -/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ - -#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ - -#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ - -#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Configuration (I2CM_CR), offset 0x020 */ - -#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ -#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ -#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ - -/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ - -#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ - -/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ - -#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ -#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ -#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ - -#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ - -/* I2C Slave Data (I2CS_DR), offset 0x008 */ - -#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ - -/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ - -#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ - -/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ - -#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ - -/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ - -#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ - -/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ - -#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h deleted file mode 100644 index 31dc2b249..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_memorymap.h +++ /dev/null @@ -1,360 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_memorymap.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory map ***********************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ - defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0xdfffffff: Reserved */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0x5fffffff: Reserved */ -# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#else -# error "Memory map not specified for this LM3S chip" -#endif - -/* Peripheral base addresses ********************************************************/ -/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt - * peripheral modules. They could probably be combined into one peripheral memory - * map. However, keeping them separate does also provide so early, compile-time - * error detection that makes the duplication worthwhile. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ - -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x3fffff: Reserved */ -# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -/* FiRM Peripheral Base Addresses */ - -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ -# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ -# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ - /* -0x3ffff: Reserved */ -# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ -# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0x49fff: Reserved */ -# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ - /* -0x53fff: Reserved */ -# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ - /* -0x57fff: Reserved */ -# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ -# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ -# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ -# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ -# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ -# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ -# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ -# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ -# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ - /* -0xcffff: Reserved */ -# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ - /* -0xfcfff: Reserved */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ -# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ - /* -0x1ffffff: Reserved */ -#else -# error "Peripheral base addresses not specified for this LM3S chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h deleted file mode 100644 index 62a4a03fd..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_pinmap.h +++ /dev/null @@ -1,281 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_pinmap.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* The following lists the input value to lm3s_configgpio to setup the alternate, - * hardware function for each pin. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ - -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ -# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ -# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ -#else -# error "Unknown LM3S chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h deleted file mode 100644 index b56ca77cb..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_ssi.h +++ /dev/null @@ -1,235 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_ssi.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#if LM3S_NSSI > 0 - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* SSI register offsets *************************************************************/ - -#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ -#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ -#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ -#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ -#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ -#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ -#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ -#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ -#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ -#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ -#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ -#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ -#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ -#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ -#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ -#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ -#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ -#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ -#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ -#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ -#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ - -/* SSI register addresses ***********************************************************/ - -#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#if LM3S_NSSI > 1 -#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) - -#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) -#endif /* LM3S_NSSI > 1 */ - -/* SSI register bit defitiions ******************************************************/ - -/* SSI Control 0 (SSICR0), offset 0x000 */ - -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ -#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) -#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ -#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ -#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ -#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ -#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ -#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ -#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ -#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) - -/* SSI Control 1 (SSICR1), offset 0x004 */ - -#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ -#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ -#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ -#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ - -/* SSI Data (SSIDR), offset 0x008 */ - -#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ - -/* SSI Status (SSISR), offset 0x00c */ - -#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ -#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ -#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ -#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ -#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ - -/* SSI Clock Prescale (SSICPSR), offset 0x010 */ - -#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ - -/* SSI Interrupt Mask (SSIIM), offset 0x014 */ - -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ - -/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ - -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ - -/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ - -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ - -/* SSI Interrupt Clear (SSIICR), offset 0x020 */ - -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ - -/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ - -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ - -/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ - -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* LM3S_NSSI > 0 */ -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h deleted file mode 100644 index d66cfeb47..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_syscontrol.h +++ /dev/null @@ -1,495 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System Control Register Offsets **************************************************/ - -#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ -#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ -#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ -#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ - -/* System Control Register Addresses ************************************************/ - -#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) -#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) -#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) -#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) -#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) -#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) -#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) -#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) -#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) -#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) -#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) -#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) -#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) -#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) -#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) -#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) -#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) -#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) -#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) -#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) -#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) -#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) -#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) -#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) -#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) -#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) -#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) -#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) -#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) - -/* System Control Register Bit Definitions ******************************************/ - -/* Device Identification 0 (DID0), offset 0x000 */ - -#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ -#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) -#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ -#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) -#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ -#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ -#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) - -/* Device Identification 1 (DID1), offset 0x004 */ - -#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ -#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) -#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ -#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) -#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ -#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) -#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ -#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) -#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ -#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) -#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ -#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) -#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ -#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) - -/* Device Capabilities 0 (DC0), offset 0x008 */ - -#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ -#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) -#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ -#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) - -/* Device Capabilities 1 (DC1), offset 0x010 */ - -#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ -#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ -#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ -#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ -#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ -#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ -#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ -#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ -#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ -#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) -#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ -#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ -#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) - -/* Device Capabilities 2 (DC2), offset 0x014 */ - -#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ -#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ -#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ -#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ -#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ -#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ -#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ -#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ -#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ -#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ -#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ -#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ - -/* Device Capabilities 3 (DC3), offset 0x018 */ - -#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ -#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ -#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ -#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ -#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ -#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ -#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ -#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ -#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ -#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ -#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ -#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ -#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ -#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ -#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ -#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ -#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ -#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ -#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ -#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ - -/* Device Capabilities 4 (DC4), offset 0x01c */ - -#define SYSCON_DC4_GPIO(n) (1 << (n)) -#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ -#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ -#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ -#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ -#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ -#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ -#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ -#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ -#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ -#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ - -/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ - -#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ - -/* LDO Power Control (LDOPCTL), offset 0x034 */ - -#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ -#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) -# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ -# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ -# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ -# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ -# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ -# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ -# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ -# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ -# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ -# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ -# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ - -/* Software Reset Control 0 (SRCR0), offset 0x040 */ - -#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ -#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ -#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ - -/* Software Reset Control 1 (SRCR1), offset 0x044 */ - -#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ -#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ -#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ -#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ -#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ -#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ -#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ -#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ -#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ -#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ -#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ -#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ - -/* Software Reset Control 2 (SRCR2), offset 0x048 */ - -#define SYSCON_SRCR2_GPIO(n) (1 << (n)) -#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ -#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ -#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ -#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ -#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ -#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ -#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ -#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ -#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ -#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ - -/* Raw Interrupt Status (RIS), offset 0x050 */ - -#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ -#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ - -/* Interrupt Mask Control (IMC), offset 0x054 */ - -#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ -#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ - -/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ - -#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ -#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ - -/* Reset Cause (RESC), offset 0x05C */ - -#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ -#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ -#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ -#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ -#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ - -/* Run-Mode Clock Configuration (RCC), offset 0x060 */ - -#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ -#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ -#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ -#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) -# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) -# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ -# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ -# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ -# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ -# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ -# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ -# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ -# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ -# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ -# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ -# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ -# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ -# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ -#ifdef CONFIG_ARCH_CHIP_LM3S9B96 -# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ -# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ -# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ -# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ -# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ -#endif -#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ -#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ -#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ -#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) -# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) -#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ - -/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ - -#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ -#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) -#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ -#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) - -/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ - -#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ -#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) -# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ -# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ -# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ -#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ -#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ -#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) -#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ - -/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ - -#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) -#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ - -#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ - -#define SYSCON_RCGC2_GPIO(n) (1 << (n)) -#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ - -#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) -#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ - -#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ - -#define SYSCON_SCGC2_GPIO(n) (1 << (n)) -#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ - -#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) -#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ - -#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ - -#define SYSCON_DCGC2_GPIO(n) (1 << (n)) -#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ - -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h deleted file mode 100644 index 649737f13..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_timer.h +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_timer.h - * - * Copyright (C) 2012 Max Nekludov. All rights reserved. - * Author: Max Nekludov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Timer register offsets ***********************************************************/ - -#define TIMER_GPTMCFG_OFFSET 0x000 -#define TIMER_GPTMTAMR_OFFSET 0x004 -#define TIMER_GPTMCTL_OFFSET 0x00C -#define TIMER_GPTMIMR_OFFSET 0x018 -#define TIMER_GPTMRIS_OFFSET 0x01C -#define TIMER_GPTMICR_OFFSET 0x024 -#define TIMER_GPTMTAILR_OFFSET 0x028 -#define TIMER_GPTMTAR_OFFSET 0x048 - -/* SSI register addresses ***********************************************************/ - -#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) - -#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) -#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) -#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) -#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) -#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) -#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) -#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) -#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) - -/* SSI register bit defitiions ******************************************************/ - -/* GPTM Configuration (GPTMCFG), offset 0x000 */ - -#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ -#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) -#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ -#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ -#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ - -/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ - -#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ -#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) -#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ -#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ -#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ -#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ -#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) -#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ -#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ -#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ -#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) -#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ -#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ -#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ -#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) -#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ -#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ -#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ -#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) - -/* GPTM Control (GPTMCTL), offset 0x00C */ - -#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ -#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) -#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ -#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) - -/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ - -#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ -#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) - -/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ - -#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ -#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) - -/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ - -#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ -#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h deleted file mode 100644 index 0fef5ccf7..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm3s_uart.h +++ /dev/null @@ -1,347 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm3s_uart.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* UART register offsets ************************************************************/ - -#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ -#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ -#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ -#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ -#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ -#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ -#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ -#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ -#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ -#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ -#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ -#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ -#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ -#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ -#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ -#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ -#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ -#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ -#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ -#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ -#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ -#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ -#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ -#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ -#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ -#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ - -/* UART register addresses **********************************************************/ - -#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) - -#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) -#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) -#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) -#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) -#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) -#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) -#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) -#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) -#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) -#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) -#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) -#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) - -/* UART register bit settings *******************************************************/ - -/* UART Data (DR), offset 0x000 */ - -#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ -#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) -#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ -#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ -#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ -#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ - -/* UART Receive Status (RSR), offset 0x004 */ - -#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ -#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ -#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ -#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ - -/* UART Error Clear (ECR), offset 0x004 */ -/* Writing any value to this register clears pending error indications */ - -/* UART Flag (FR), offset 0x018 */ - -#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ -#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ -#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ -#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ -#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ - -/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ - -#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ - -/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ - -#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ - -/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ - -#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ - -/* Register 7: UART Line Control (LCRH), offset 0x02C */ - -#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ -#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ -#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ -#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ -#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ -#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ -#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) -# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ -# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ -# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ -# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ -#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ - -/* UART Control (CTL), offset 0x030 */ - -#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ -#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ -#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ -#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ -#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ -#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ - -/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ - -#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ -#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) -# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ -#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ -#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) -# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ - -/* UART Interrupt Mask (IM), offset 0x038 */ - -#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ -#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ -#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ -#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ -#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ -#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ -#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ - - -/* UART Raw Interrupt Status (RIS), offset 0x03c */ - -#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ -#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ -#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ -#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ -#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ -#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ -#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ - -/* UART Masked Interrupt Status (MIS), offset 0x040 */ - -#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ -#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ -#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ -#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ -#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ -#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ -#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ - -/* UART Interrupt Clear (ICR), offset 0x044 */ - -#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ -#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ -#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ -#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ -#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ -#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ -#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear - */ - -/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ - -#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ - -#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ - -#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ - -#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ - -#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ - -#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ - -#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ - -#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ - -#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ - -/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ - -#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ - -/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ - -#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ - -/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ - -#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h deleted file mode 100644 index c52857847..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm_memorymap.h +++ /dev/null @@ -1,69 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm_memorymap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/* Include the memory map file for the specific Stellaris chip */ - -#ifdef CONFIG_ARCH_CHIP_LM3S -# include "chip/lm3s_memorymap.h" -#else -# error "Unsupported Stellaris memory map" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h deleted file mode 100644 index b00a6e794..000000000 --- a/nuttx/arch/arm/src/lm3s/chip/lm_pinmap.h +++ /dev/null @@ -1,69 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/chip/lm_pinmap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H -#define __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/* Include the memory map file for the specific Stellaris chip */ - -#ifdef CONFIG_ARCH_CHIP_LM3S -# include "chip/lm3s_pinmap.h" -#else -# error "Unsupported Stellaris PIN mapping" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM3S_CHIP_LM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c deleted file mode 100644 index 9d205b763..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c +++ /dev/null @@ -1,167 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_dumpgpio.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "up_arch.h" - -#include "chip.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* NOTE: this is duplicated in lm3s_gpio.c */ - -#ifdef LM3S_GPIOH_BASE -static const uint32_t g_gpiobase[8] = -{ - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, -}; - -static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#else -static const uint32_t g_gpiobase[8] = -{ - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, -}; - -static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static inline uint32_t lm3s_gpiobaseaddress(int port) -{ - return g_gpiobase[port & 7]; -} - -/**************************************************************************** - * Name: lm3s_gpioport - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static inline uint8_t lm3s_gpioport(int port) -{ - return g_portchar[port & 7]; -} - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -int lm3s_dumpgpio(uint32_t pinset, const char *msg) -{ - irqstate_t flags; - unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - uint32_t base; - uint32_t rcgc2; - bool enabled; - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - DEBUGASSERT(base != 0); - - /* The following requires exclusive access to the GPIO registers */ - - flags = irqsave(); - rcgc2 = getreg32(LM3S_SYSCON_RCGC2); - enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); - - lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", - lm3s_gpioport(port), pinset, base, msg); - lldbg(" RCGC2: %08x (%s)\n", - rcgc2, enabled ? "enabled" : "disabled" ); - - /* Don't bother with the rest unless the port is enabled */ - - if (enabled) - { - lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", - getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), - getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); - lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", - getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), - getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); - lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", - getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), - getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), - getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), - getreg32(base + LM3S_GPIO_SLR_OFFSET)); - } - irqrestore(flags); - return OK; -} diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c deleted file mode 100644 index f44b6654f..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c +++ /dev/null @@ -1,1472 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_ethernet.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET) - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "chip.h" -#include "up_arch.h" - -#include "lm_gpio.h" -#include "lm_ethernet.h" -#include "chip/lm_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */ - -#ifdef CONFIG_LM3S_ETHHDUPLEX -# define LM3S_DUPLEX_SETBITS 0 -# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX -#else -# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX -# define LM3S_DUPLEX_CLRBITS 0 -#endif - -/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */ - -#ifdef CONFIG_LM3S_ETHNOAUTOCRC -# define LM3S_CRC_SETBITS 0 -# define LM3S_CRC_CLRBITS MAC_TCTL_CRC -#else -# define LM3S_CRC_SETBITS MAC_TCTL_CRC -# define LM3S_CRC_CLRBITS 0 -#endif - -/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */ - -#ifdef CONFIG_LM3S_ETHNOPAD -# define LM3S_PADEN_SETBITS 0 -# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN -#else -# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN -# define LM3S_PADEN_CLRBITS 0 -#endif - -#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) -#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) - -/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */ - -#ifdef CONFIG_LM3S_MULTICAST -# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL -# define LM3S_AMUL_CLRBITS 0 -#else -# define LM3S_AMUL_SETBITS 0 -# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL -#endif - -/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */ - -#ifdef CONFIG_LM3S_PROMISCUOUS -# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS -# define LM3S_PRMS_CLRBITS 0 -#else -# define LM3S_PRMS_SETBITS 0 -# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS -#endif - -/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */ - -#ifdef CONFIG_LM3S_BADCRC -# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC -# define LM3S_BADCRC_CLRBITS 0 -#else -# define LM3S_BADCRC_SETBITS 0 -# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC -#endif - -#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) -#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) - -/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */ - -#ifdef CONFIG_LM3S_DUMPPACKET -# define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) -#else -# define lm3s_dumppacket(m,a,n) -#endif - -/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ - -#define LM3S_WDDELAY (1*CLK_TCK) -#define LM3S_POLLHSEC (1*2) - -/* TX timeout = 1 minute */ - -#define LM3S_TXTIMEOUT (60*CLK_TCK) - -/* This is a helper pointer for accessing the contents of the Ethernet header */ - -#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf) - -#define LM32S_MAX_MDCCLK 2500000 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* EMAC statistics (debug only) */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) -struct lm3s_statistics_s -{ - uint32_t rx_int; /* Number of Rx interrupts received */ - uint32_t rx_packets; /* Number of packets received (sum of the following): */ - uint32_t rx_ip; /* Number of Rx IP packets received */ - uint32_t rx_arp; /* Number of Rx ARP packets received */ - uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */ - uint32_t rx_pktsize; /* Number of dropped, too small or too big */ - uint32_t rx_errors; /* Number of Rx errors (reception error) */ - uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */ - uint32_t tx_int; /* Number of Tx interrupts received */ - uint32_t tx_packets; /* Number of Tx packets queued */ - uint32_t tx_errors; /* Number of Tx errors (transmission error)*/ - uint32_t tx_timeouts; /* Number of Tx timeout errors */ -}; -# define EMAC_STAT(priv,name) priv->ld_stat.name++ -#else -# define EMAC_STAT(priv,name) -#endif - -/* The lm3s_driver_s encapsulates all state information for a single hardware - * interface - */ - -struct lm3s_driver_s -{ - /* The following fields would only be necessary on chips that support - * multiple Ethernet controllers. - */ - -#if LM3S_NETHCONTROLLERS > 1 - uint32_t ld_base; /* Ethernet controller base address */ - int ld_irq; /* Ethernet controller IRQ */ -#endif - - bool ld_bifup; /* true:ifup false:ifdown */ - WDOG_ID ld_txpoll; /* TX poll timer */ - WDOG_ID ld_txtimeout; /* TX timeout timer */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) - struct lm3s_statistics_s ld_stat; -#endif - - /* This holds the information visible to uIP/NuttX */ - - struct uip_driver_s ld_dev; /* Interface understood by uIP */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Miscellaneous low level helpers */ - -#if LM3S_NETHCONTROLLERS > 1 -static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); -static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); -#else -static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); -static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); -#endif -static void lm3s_ethreset(struct lm3s_driver_s *priv); -#if 0 /* Not used */ -static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value); -#endif -static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr); - -/* Common TX logic */ - -static int lm3s_transmit(struct lm3s_driver_s *priv); -static int lm3s_uiptxpoll(struct uip_driver_s *dev); - -/* Interrupt handling */ - -static void lm3s_receive(struct lm3s_driver_s *priv); -static void lm3s_txdone(struct lm3s_driver_s *priv); -static int lm3s_interrupt(int irq, FAR void *context); - -/* Watchdog timer expirations */ - -static void lm3s_polltimer(int argc, uint32_t arg, ...); -static void lm3s_txtimeout(int argc, uint32_t arg, ...); - -/* NuttX callback functions */ - -static int lm3s_ifup(struct uip_driver_s *dev); -static int lm3s_ifdown(struct uip_driver_s *dev); -static int lm3s_txavail(struct uip_driver_s *dev); -#ifdef CONFIG_NET_IGMP -static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); -static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_ethin - * - * Description: - * Read a register from the Ethernet module - * - * Parameters: - * priv - Reference to the driver state structure - * offset - Byte offset of the register from the ethernet base address - * - * Returned Value: - * Register value - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) -{ - return getreg32(priv->ld_base + offset); -} -#else -static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) -{ - return getreg32(LM3S_ETHCON_BASE + offset); -} -#endif - -/**************************************************************************** - * Function: lm3s_ethout - * - * Description: - * Write a register to the Ethernet module - * - * Parameters: - * priv - Reference to the driver state structure - * offset - Byte offset of the register from the ethernet base address - * value - The value to write the Ethernet register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) -{ - putreg32(value, priv->ld_base + offset); -} -#else -static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) -{ - putreg32(value, LM3S_ETHCON_BASE + offset); -} -#endif - -/**************************************************************************** - * Function: lm3s_ethreset - * - * Description: - * Configure and reset the Ethernet module, leaving it in a disabled state. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_ethreset(struct lm3s_driver_s *priv) -{ - irqstate_t flags; - uint32_t regval; - -#if LM3S_NETHCONTROLLERS > 1 -# error "If multiple interfaces are supported, this function would have to be redesigned" -#endif - - /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ - - flags = irqsave(); - regval = getreg32(LM3S_SYSCON_RCGC2); - regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); - putreg32(regval, LM3S_SYSCON_RCGC2); - nllvdbg("RCGC2: %08x\n", regval); - - /* Put the Ethernet controller into the reset state */ - - regval = getreg32(LM3S_SYSCON_SRCR2); - regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); - - /* Wait just a bit. This is a much longer delay than necessary */ - - up_mdelay(2); - - /* Then take the Ethernet controller out of the reset state */ - - regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); - nllvdbg("SRCR2: %08x\n", regval); - - /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ - - up_mdelay(2); - - /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */ - -#ifdef CONFIG_LM3S_ETHLEDS - /* Configure the pins for the peripheral function */ - - lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); - lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); -#endif - - /* Disable all Ethernet controller interrupts */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval &= ~MAC_IM_ALLINTS; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Clear any pending interrupts (shouldn't be any) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); - irqrestore(flags); -} - -/**************************************************************************** - * Function: lm3s_phywrite - * - * Description: - * Write a 16-bit word to a PHY register - * - * Parameters: - * priv - Reference to the driver state structure - * regaddr - Address of the PHY register to write - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value) -{ - /* Wait for any MII transactions in progress to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Set up the data to be written */ - - DEBUGASSERT(value < MAC_MTXD_MASK); - lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); - - /* Set up the PHY register address and start the write operation */ - - regaddr <<= MAC_MCTL_REGADR_SHIFT; - DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); - - /* Wait for the write transaction to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); -} -#endif - -/**************************************************************************** - * Function: lm3s_phyread - * - * Description: - * Write a 16-bit word to a PHY register - * - * Parameters: - * priv - Reference to the driver state structure - * regaddr - Address of the PHY register to write - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr) -{ - /* Wait for any MII transactions in progress to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Set up the PHY register address and start the read operation */ - - regaddr <<= MAC_MCTL_REGADR_SHIFT; - DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); - - /* Wait for the write transaction to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Read and return the PHY data */ - - return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); -} - -/**************************************************************************** - * Function: lm3s_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -static int lm3s_transmit(struct lm3s_driver_s *priv) -{ - irqstate_t flags; - uint32_t regval; - uint8_t *dbuf; - int pktlen; - int bytesleft; - int ret = -EBUSY; - - /* Verify that the hardware is ready to send another packet */ - - flags = irqsave(); - if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* Increment statistics */ - - EMAC_STAT(priv, tx_packets); - lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); - - /* Transfer the packet into the Tx FIFO. The LS 16-bits of the first - * 32-bit word written to the Tx FIFO contains the Ethernet payload - * data length. That is the full length of the message (d_len) minus - * the size of the Ethernet header (14). - */ - - pktlen = priv->ld_dev.d_len; - nllvdbg("Sending packet, pktlen: %d\n", pktlen); - DEBUGASSERT(pktlen > UIP_LLH_LEN); - - dbuf = priv->ld_dev.d_buf; - regval = (uint32_t)(pktlen - 14); - regval |= ((uint32_t)(*dbuf++) << 16); - regval |= ((uint32_t)(*dbuf++) << 24); - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); - - /* Write all of the whole, 32-bit values in the middle of the packet */ - - for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4) - { - /* Transfer a whole word from the user buffer. Note, the user - * buffer may be un-aligned. - */ - - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); - } - - /* Write the last, partial word in the FIFO */ - - if (bytesleft > 0) - { - /* Write the last word */ - - regval = 0; - switch (bytesleft) - { - case 0: - default: - break; - - case 3: - regval |= ((uint32_t)dbuf[2] << 16); - case 2: - regval |= ((uint32_t)dbuf[1] << 8); - case 1: - regval |= (uint32_t)dbuf[0]; - break; - } - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); - } - - /* Activate the transmitter */ - - lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); - - /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - - (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv); - ret = OK; - } - - irqrestore(flags); - return ret; -} - -/**************************************************************************** - * Function: lm3s_uiptxpoll - * - * Description: - * The transmitter is available, check if uIP has any outgoing packets ready - * to send. This is a callback from uip_poll(). uip_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_uiptxpoll(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - int ret = OK; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len); - if (priv->ld_dev.d_len > 0) - { - /* Send the packet. lm3s_transmit() will return zero if the - * packet was successfully handled. - */ - - DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - uip_arp_out(&priv->ld_dev); - ret = lm3s_transmit(priv); - } - - /* If zero is returned, the polling will continue until all connections have - * been examined. - */ - - return ret; -} - -/**************************************************************************** - * Function: lm3s_receive - * - * Description: - * An interrupt was received indicating the availability of a new RX packet - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_receive(struct lm3s_driver_s *priv) -{ - uint32_t regval; - uint8_t *dbuf; - int pktlen; - int bytesleft; - - /* Loop while there are incoming packets to be processed */ - - while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) - { - /* Update statistics */ - - EMAC_STAT(priv, rx_packets); - - /* Copy the data data from the hardware to priv->ld_dev.d_buf. Set - * amount of data in priv->ld_dev.d_len - */ - - dbuf = priv->ld_dev.d_buf; - - /* The packet frame length begins in the LS 16-bits of the first - * word from the FIFO followed by the Ethernet header beginning - * in the MS 16-bits of the first word. - * - * Pick off the packet length from the first word. This packet length - * includes the len/type field (size 2) and the FCS (size 4). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - pktlen = (int)(regval & 0x0000ffff); - nllvdbg("Receiving packet, pktlen: %d\n", pktlen); - - /* Check if the pktlen is valid. It should be large enough to hold - * an Ethernet header and small enough to fit entirely in the I/O - * buffer. Six is subtracted to acount for the 2-byte length/type - * and 4 byte FCS that are not copied into the uIP packet. - */ - - if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6)) - { - int wordlen; - - /* We will have to drop this packet */ - - nlldbg("Bad packet size dropped (%d)\n", pktlen); - EMAC_STAT(priv, rx_pktsize); - - /* The number of bytes and words left to read is pktlen - 4 (including, - * the final, possibly partial word) because we've already read 4 bytes. - */ - - wordlen = (pktlen - 1) >> 2; - - /* Read and discard the remaining words in the FIFO */ - - while (wordlen--) - { - (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - } - - /* Check for another packet */ - - continue; - } - - /* Save the first two bytes from the first word */ - - *dbuf++ = (uint8_t)((regval >> 16) & 0xff); - *dbuf++ = (uint8_t)((regval >> 24) & 0xff); - - /* Read all of the whole, 32-bit values in the middle of the packet. - * We've already read the length (2 bytes) plus the first two bytes - * of data. - */ - - for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4) - { - /* Transfer a whole word to the user buffer. Note, the user - * buffer may be un-aligned. - */ - - *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - } - - /* Handle the last, partial word in the FIFO (0-3 bytes) and discard - * the 4-byte FCS. - */ - - for (; bytesleft > 0; bytesleft -= 4) - { - /* Read the last word. And transfer all but the last four - * bytes of the FCS into the user buffer. - */ - - regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - switch (bytesleft) - { - default: - break; - - case 7: - dbuf[2] = (regval >> 16) & 0xff; - case 6: - dbuf[1] = (regval >> 8) & 0xff; - case 5: - dbuf[0] = regval & 0xff; - break; - } - } - - /* Pass the packet length to uIP MINUS 2 bytes for the length and - * 4 bytes for the FCS. - */ - - priv->ld_dev.d_len = pktlen - 6; - lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); - - /* We only accept IP packets of the configured type and ARP packets */ - -#ifdef CONFIG_NET_IPv6 - if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6)) -#else - if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP)) -#endif - { - nllvdbg("IP packet received (%02x)\n", ETHBUF->type); - EMAC_STAT(priv, rx_ip); - - uip_arp_ipin(&priv->ld_dev); - uip_input(&priv->ld_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->ld_dev.d_len > 0) - { - uip_arp_out(&priv->ld_dev); - lm3s_transmit(priv); - } - } - else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP)) - { - nllvdbg("ARP packet received (%02x)\n", ETHBUF->type); - EMAC_STAT(priv, rx_arp); - - uip_arp_arpin(&priv->ld_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->ld_dev.d_len > 0) - { - lm3s_transmit(priv); - } - } -#ifdef CONFIG_DEBUG - else - { - nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); - EMAC_STAT(priv, rx_dropped); - } -#endif - } -} - -/**************************************************************************** - * Function: lm3s_txdone - * - * Description: - * An interrupt was received indicating that the last TX packet(s) is done - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_txdone(struct lm3s_driver_s *priv) -{ - /* Cancel the TX timeout */ - - wd_cancel(priv->ld_txtimeout); - - /* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. Since - * we get here because of of TXEMP which indicates that the packet was - * transmitted and that the TX FIFO is empty, NEWTX should always be zero - * at this point. - */ - - DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - - /* Then poll uIP for new XMIT data */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); -} - -/**************************************************************************** - * Function: lm3s_interrupt - * - * Description: - * Hardware interrupt handler - * - * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) - * - * Returned Value: - * OK on success - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_interrupt(int irq, FAR void *context) -{ - register struct lm3s_driver_s *priv; - uint32_t ris; - -#if LM3S_NETHCONTROLLERS > 1 -# error "A mechanism to associate and interface with an IRQ is needed" -#else - priv = &g_lm3sdev[0]; -#endif - - /* Read the raw interrupt status register */ - - ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - - /* Clear all pending interrupts */ - - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); - - /* Check for errors */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) - if ((ris & MAC_RIS_TXER) != 0) - { - EMAC_STAT(priv, tx_errors); /* Number of Tx errors */ - } - - if ((ris & MAC_RIS_FOV) != 0) - { - EMAC_STAT(priv, rx_ovrerrors); /* Number of Rx FIFO overrun errors */ - } - - if ((ris & MAC_RIS_RXER) != 0) - { - EMAC_STAT(priv, rx_errors); /* Number of Rx errors */ - } -#endif - - /* Handle (unmasked) interrupts according to status bit settings */ - - ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - - /* Is this an Rx interrupt (meaning that a packet has been received)? */ - - if ((ris & MAC_RIS_RXINT) != 0) - { - /* Handle the incoming packet */ - - EMAC_STAT(priv, rx_int); - lm3s_receive(priv); - } - - /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ - - if ((ris & MAC_RIS_TXEMP) != 0) - { - /* Handle the complete of the transmission */ - - EMAC_STAT(priv, tx_int); - lm3s_txdone(priv); - } - - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if - * there are no pending transmissions). - */ - - return OK; -} - -/**************************************************************************** - * Function: lm3s_txtimeout - * - * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_txtimeout(int argc, uint32_t arg, ...) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; - - /* Increment statistics */ - - nlldbg("Tx timeout\n"); - EMAC_STAT(priv, tx_timeouts); - - /* Then reset the hardware */ - - DEBUGASSERT(priv->ld_bifup); - lm3s_ifdown(&priv->ld_dev); - lm3s_ifup(&priv->ld_dev); - - /* Then poll uIP for new XMIT data */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); -} - -/**************************************************************************** - * Function: lm3s_polltimer - * - * Description: - * Periodic timer handler. Called from the timer interrupt handler. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_polltimer(int argc, uint32_t arg, ...) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; - - /* Check if we can send another Tx packet now. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. - * - * NOTE: This can cause missing poll cycles and, hence, some timing - * inaccuracies. - */ - - if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* If so, update TCP timing states and poll uIP for new XMIT data */ - - (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg); - } -} - -/**************************************************************************** - * Function: lm3s_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_ifup(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - uint32_t regval; - uint32_t div; - uint16_t phyreg; - - nlldbg("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); - - /* Enable and reset the Ethernet controller */ - - flags = irqsave(); - lm3s_ethreset(priv); - - /* Set the management clock divider register for access to the PHY - * register set. The MDC clock is divided down from the system clock per: - * - * MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1)) - * div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1 - * - * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will - * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded. - */ - - div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; - lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div); - nllvdbg("MDV: %08x\n", div); - - /* Then configure the Ethernet Controller for normal operation - * - * Setup the transmit control register (Full duplex, TX CRC Auto Generation, - * TX Padding Enabled). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); - regval &= ~LM3S_TCTCL_CLRBITS; - regval |= LM3S_TCTCL_SETBITS; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - nllvdbg("TCTL: %08x\n", regval); - - /* Setup the receive control register (Disable multicast frames, disable - * promiscuous mode, disable bad CRC rejection). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~LM3S_RCTCL_CLRBITS; - regval |= LM3S_RCTCL_SETBITS; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - nllvdbg("RCTL: %08x\n", regval); - - /* Setup the time stamp configuration register */ - -#ifdef LM3S_ETHTS - regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); -#ifdef CONFIG_LM3S_TIMESTAMP - regval |= MAC_TS_EN; -#else - regval &= ~(MAC_TS_EN); -#endif - lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval); - nllvdbg("TS: %08x\n", regval); -#endif - - /* Wait for the link to come up. This following is not very conservative - * of system resources -- it really should wait gracefully on a semaphore - * and the interrupt handler should post the semaphore when LINKSTATUS is - * set - */ - - nlldbg("Waiting for link\n"); - do - { - phyreg = lm3s_phyread(priv, MII_MSR); - } - while ((phyreg & MII_MSR_LINKSTATUS) == 0); - nlldbg("Link established\n"); - - /* Reset the receive FIFO */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet receiver */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RXEN; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet transmitter */ - - regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); - regval |= MAC_TCTL_TXEN; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - - /* Reset the receive FIFO (again) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet interrupt */ - -#if LM3S_NETHCONTROLLERS > 1 - up_enable_irq(priv->irq); -#else - up_enable_irq(LM3S_IRQ_ETHCON); -#endif - - /* Enable the Ethernet RX packet receipt interrupt */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval |= MAC_IM_RXINTM; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Program the hardware with it's MAC address (for filtering) */ - - regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; - lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); - - regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; - lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); - - /* Set and activate a timer process */ - - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv); - - priv->ld_bifup = true; - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_ifdown - * - * Description: - * NuttX Callback: Stop the interface. The only way to restore normal - * behavior is to call lm3s_ifup(). - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_ifdown(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - uint32_t regval; - - nlldbg("Taking down: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); - - /* Cancel the TX poll timer and TX timeout timers */ - - flags = irqsave(); - wd_cancel(priv->ld_txpoll); - wd_cancel(priv->ld_txtimeout); - - /* Disable the Ethernet interrupt */ - -#if LM3S_NETHCONTROLLERS > 1 - up_disable_irq(priv->irq); -#else - up_disable_irq(LM3S_IRQ_ETHCON); -#endif - - /* Disable all Ethernet controller interrupt sources */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval &= ~MAC_IM_ALLINTS; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Reset the receive FIFO */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Disable the Ethernet receiver */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~MAC_RCTL_RXEN; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Disable the Ethernet transmitter */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~MAC_TCTL_TXEN; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - - /* Reset the receive FIFO (again) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Clear any pending interrupts */ - - regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); - - /* The interface is now DOWN */ - - priv->ld_bifup = false; - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int lm3s_txavail(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - - /* Ignore the notification if the interface is not yet up or if the Tx FIFO - * hardware is not available at this time. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. When the - * transmission completes, lm3s_txdone() will be called and the Tx polling - * will occur at that time. - */ - - flags = irqsave(); - if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* If the interface is up and we can use the Tx FIFO, then poll uIP - * for new Tx data - */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); - } - - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_addmac - * - * Description: - * NuttX Callback: Add the specified MAC address to the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - -#warning "Multicast MAC support not implemented" - return OK; -} -#endif - -/**************************************************************************** - * Function: lm3s_rmmac - * - * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - -#warning "Multicast MAC support not implemented" - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface - * - * Parameters: - * None - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -int lm3s_ethinitialize(int intf) -#else -static inline int lm3s_ethinitialize(int intf) -#endif -{ - struct lm3s_driver_s *priv = &g_lm3sdev[intf]; - int ret; - - /* Check if the Ethernet module is present */ - - ndbg("Setting up eth%d\n", intf); - -#if LM3S_NETHCONTROLLERS > 1 -# error "This debug check only works with one interface" -#else - DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); -#endif - DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); - - /* Initialize the driver structure */ - - memset(priv, 0, sizeof(struct lm3s_driver_s)); - priv->ld_dev.d_ifup = lm3s_ifup; /* I/F down callback */ - priv->ld_dev.d_ifdown = lm3s_ifdown; /* I/F up (new IP address) callback */ - priv->ld_dev.d_txavail = lm3s_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_IGMP - priv->ld_dev.d_addmac = lm3s_addmac; /* Add multicast MAC address */ - priv->ld_dev.d_rmmac = lm3s_rmmac; /* Remove multicast MAC address */ -#endif - priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */ - - /* Create a watchdog for timing polling for and timing of transmisstions */ - -#if LM3S_NETHCONTROLLERS > 1 -# error "A mechanism to associate base address an IRQ with an interface is needed" - priv->ld_base = ??; /* Ethernet controller base address */ - priv->ld_irq = ??; /* Ethernet controller IRQ number */ -#endif - priv->ld_txpoll = wd_create(); /* Create periodic poll timer */ - priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */ - - /* If the board can provide us with a MAC address, get the address - * from the board now. The MAC will not be applied until lm3s_ifup() - * is caleld (and the MAC can be overwritten with a netdev ioctl call). - */ - -#ifdef CONFIG_LM3S_BOARDMAC - lm3s_ethernetmac(&priv->ld_dev.d_mac); -#endif - - /* Perform minimal, one-time initialization -- just reset the controller and - * leave it disabled. The Ethernet controller will be reset and properly - * re-initialized each time lm3s_ifup() is called. - */ - - lm3s_ethreset(priv); - lm3s_ifdown(&priv->ld_dev); - - /* Attach the IRQ to the driver */ - -#if LM3S_NETHCONTROLLERS > 1 - ret = irq_attach(priv->irq, lm3s_interrupt); -#else - ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt); -#endif - if (ret != 0) - { - /* We could not attach the ISR to the IRQ */ - - return -EAGAIN; - } - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - (void)netdev_register(&priv->ld_dev); - return OK; -} - - -/************************************************************************************ - * Name: up_netinitialize - * - * Description: - * Initialize the first network interface. If there are more than one interface - * in the chip, then board-specific logic will have to provide this function to - * determine which, if any, Ethernet controllers should be initialized. - * - ************************************************************************************/ - -#if LM3S_NETHCONTROLLERS == 1 -void up_netinitialize(void) -{ - (void)lm3s_ethinitialize(0); -} -#endif - -#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */ - diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c deleted file mode 100644 index dd005fdd1..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c +++ /dev/null @@ -1,854 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_gpio.c - * arch/arm/src/chip/lm3s_gpio.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "os_internal.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions are part of the implementation of the GPIO pad - * configuration of Table 9-1 in the LM3S6918 data sheet. - */ - -#define AFSEL_SHIFT 5 -#define AFSEL_1 (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */ -#define AFSEL_0 0 -#define AFSEL_X 0 - -#define DIR_SHIFT 4 -#define DIR_1 (1 << DIR_SHIFT) /* Set/clear bit in GPIO DIR register */ -#define DIR_0 0 -#define DIR_X 0 - -#define ODR_SHIFT 3 -#define ODR_1 (1 << ODR_SHIFT) /* Set/clear bit in GPIO ODR register */ -#define ODR_0 0 -#define ODR_X 0 - -#define DEN_SHIFT 2 -#define DEN_1 (1 << DEN_SHIFT) /* Set/clear bit in GPIO DEN register */ -#define DEN_0 0 -#define DEN_X 0 - -#define PUR_SHIFT 1 -#define PUR_1 (1 << PUR_SHIFT) /* Set/clear bit in GPIO PUR register */ -#define PUR_0 0 -#define PUR_X 0 - -#define PDR_SHIFT 0 -#define PDR_1 (1 << PDR_SHIFT) /* Set/clear bit in GPIO PDR register */ -#define PDR_0 0 -#define PDR_X 0 - -#define GPIO_INPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_INPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_OUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_OUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ODINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_ODINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ODOUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_ODOUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_PFODIO_SETBITS (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_PFODIO_CLRBITS (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_PFIO_SETBITS (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_PFIO_CLRBITS (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ANINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0) -#define GPIO_ANINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1) - -#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_func_s -{ - uint8_t setbits; /* A set of GPIO register bits to set */ - uint8_t clrbits; /* A set of GPIO register bits to clear */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_func_s g_funcbits[] = -{ - {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ - {GPIO_OUTPUT_SETBITS, GPIO_OUTPUT_CLRBITS}, /* GPIO_FUNC_OUTPUT */ - {GPIO_ODINPUT_SETBITS, GPIO_ODINPUT_CLRBITS}, /* GPIO_FUNC_ODINPUT */ - {GPIO_ODOUTPUT_SETBITS, GPIO_ODOUTPUT_CLRBITS}, /* GPIO_FUNC_ODOUTPUT */ - {GPIO_PFODIO_SETBITS, GPIO_PFODIO_CLRBITS}, /* GPIO_FUNC_PFODIO */ - {GPIO_PFIO_SETBITS, GPIO_PFIO_CLRBITS}, /* GPIO_FUNC_PFIO */ - {GPIO_ANINPUT_SETBITS, GPIO_ANINPUT_CLRBITS}, /* GPIO_FUNC_ANINPUT */ - {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ -}; - -static const uint32_t g_gpiobase[LM3S_NPORTS] = -{ - /* All support LM3S parts have at least 7 ports, GPIOA-G */ - - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, - - /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ - -#if LM3S_NPORTS > 7 - LM3S_GPIOH_BASE, -#endif - - /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ - -#if LM3S_NPORTS > 8 - LM3S_GPIOJ_BASE, -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static uint32_t lm3s_gpiobaseaddress(unsigned int port) -{ - uint32_t gpiobase = 0; - if (port < LM3S_NPORTS) - { - gpiobase = g_gpiobase[port]; - } - return gpiobase; -} - -/**************************************************************************** - * Name: lm3s_gpiofunc - * - * Description: - * Configure GPIO registers for a specific function - * - ****************************************************************************/ - -static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func) -{ - uint32_t setbit; - uint32_t clrbit; - uint32_t regval; - - /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain - * control register. Setting a bit in this register enables the open drain - * configuration of the corresponding GPIO pad. When open drain mode is enabled, - * the corresponding bit should also be set in the GPIO Digital Input Enable - * (GPIO DEN) register ... Corresponding bits in the drive strength registers - * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the - * desired rise and fall times. The GPIO acts as an open drain input if the - * corresponding bit in the GPIO DIR register is set to 0; and as an open - * drain output when set to 1." - */ - - setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); - - /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control - * register. When a bit is set to 1, it enables a weak pull-up resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the - * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." - */ - - setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno; - - if (setbit || clrbit) - { - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); - } - - /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control - * register. When a bit is set to 1, it enables a weak pull-down resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears - * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." - */ - - setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno; - - if (setbit || clrbit) - { - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); - } - - /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable - * register. By default, with the exception of the GPIO signals used for JTAG/SWD - * function, all other GPIO signals are configured out of reset to be undriven - * (tristate). Their digital function is disabled; they do not drive a logic - * value on the pin and they do not allow the pin voltage into the GPIO receiver. - * To use the pin in a digital function (either GPIO or alternate function), the - * corresponding GPIODEN bit must be set." - */ - - setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); - - /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data - * direction register. Bits set to 1 in the GPIODIR register configure - * the corresponding pin to be an output, while bits set to 0 configure the - * pins to be inputs. All bits are cleared by a reset, meaning all GPIO - * pins are inputs by default. - */ - - setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); - - /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode - * control select register. Writing a 1 to any bit in this register selects - * the hardware control for the corresponding GPIO line. All bits are cleared - * by a reset, therefore no GPIO line is set to hardware control by default." - * - * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit - * and unlock the GPIO. That is not implemented here. - */ - - setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); -} - -/**************************************************************************** - * Name: lm3s_gpiopadstrength - * - * Description: - * Set up pad strength and pull-ups - * - ****************************************************************************/ - -static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT; - uint32_t regoffset; - uint32_t regval; - uint32_t slrset; - uint32_t slrclr; - - /* Prepare bits to disable slew */ - - slrset = 0; - slrclr = pin; - - switch (strength) - { - case 0: /* 2mA pad drive strength */ - { - /* "The GPIODR2R register is the 2-mA drive control register. It - * allows for each GPIO signal in the port to be individually configured - * without affecting the other pads. When writing a DRV2 bit for a GPIO - * signal, the corresponding DRV4 bit in the GPIO DR4R register and the - * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR2R_OFFSET; - } - break; - - case 1: /* 4mA pad drive strength */ - { - /* "The GPIODR4R register is the 4-mA drive control register. It allows - * for each GPIO signal in the port to be individually configured without - * affecting the other pads. When writing the DRV4 bit for a GPIO signal, - * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit - * in the GPIO DR8R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR4R_OFFSET; - } - break; - - case 3: /* 8mA Pad drive with slew rate control */ - { - /* "The GPIOSLR register is the slew rate control register. Slew rate - * control is only available when using the 8-mA drive strength option - * via the GPIO 8-mA Drive Select (GPIODR8R) register..." - */ - - slrset = pin; - slrclr = 0; - } - /* Fall through */ - - case 2: /* 8mA pad drive strength (without slew rate control) */ - { - /* "The GPIODR8R register is the 8-mA drive control register. It - * allows for each GPIO signal in the port to be individually configured - * without affecting the other pads. When writing the DRV8 bit for a GPIO - * signal, the corresponding DRV2 bit in the GPIO DR2R register and the - * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR8R_OFFSET; - } - break; - } - - /* Set the selected pad strength and set/clear optional slew rate control */ - - regval = getreg32(base + regoffset); - regval |= pin; - putreg32(regval, base + regoffset); - - regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); - regval &= slrclr; - regval |= slrset; - putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); -} - -/**************************************************************************** - * Name: lm3s_gpiopadtype - * - * Description: - * Set up pad strength and pull-ups. Some of these values may be over- - * written by lm3s_gpiofunc, depending on the function selection. Others - * are optional for different function selections. - * - ****************************************************************************/ - -static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int padtype = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT; -#if 0 /* always overwritten by lm3s_gpiofunc */ - uint32_t odrset; - uint32_t odrclr; -#endif - uint32_t purset; - uint32_t purclr; - uint32_t pdrset; - uint32_t pdrclr; -#if 0 /* always overwritten by lm3s_gpiofunc */ - uint32_t denset; - uint32_t denclr; -#endif - uint32_t regval; - - /* Assume digital GPIO function, push-pull with no pull-up or pull-down */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = 0; - odrclr = pin; -#endif - purset = 0; - purclr = pin; - pdrset = 0; - pdrclr = pin; -#if 0 /* always overwritten by lm3s_gpiofunc */ - denset = pin; - denclr = 0; -#endif - - switch (padtype) - { - case 0: /* Push-pull */ - default: - { - } - break; - - case 1: /* Push-pull with weak pull-up */ - { - purset = pin; - purclr = 0; - } - break; - case 2: /* Push-pull with weak pull-down */ - { - pdrset = pin; - pdrclr = 0; - } - break; - case 3: /* Open-drain */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - } - break; - case 4: /* Open-drain with weak pull-up */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - purset = pin; - purclr = 0; - } - break; - case 5: /* Open-drain with weak pull-down */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - pdrset = pin; - pdrclr = 0; - } - break; - case 6: /* Analog comparator */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - denset = 0; - denclr = pin; -#endif - } - break; - } - - /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain - * control register. Setting a bit in this register enables the open drain - * configuration of the corresponding GPIO pad. When open drain mode is enabled, - * the corresponding bit should also be set in the GPIO Digital Input Enable - * (GPIO DEN) register ... Corresponding bits in the drive strength registers - * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the - * desired rise and fall times. The GPIO acts as an open drain input if the - * corresponding bit in the GPIO DIR register is set to 0; and as an open - * drain output when set to 1." - */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); - regval &= ~odrclr; - regval |= odrset; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); -#endif - - /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control - * register. When a bit is set to 1, it enables a weak pull-up resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the - * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." - */ - - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); - regval &= ~purclr; - regval |= purset; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); - - /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control - * register. When a bit is set to 1, it enables a weak pull-down resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears - * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." - */ - - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); - regval &= ~pdrclr; - regval |= pdrset; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); - - /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable - * register. By default, with the exception of the GPIO signals used for JTAG/SWD - * function, all other GPIO signals are configured out of reset to be undriven - * (tristate). Their digital function is disabled; they do not drive a logic - * value on the pin and they do not allow the pin voltage into the GPIO receiver. - * To use the pin in a digital function (either GPIO or alternate function), the - * corresponding GPIODEN bit must be set." - */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); - regval &= ~denclr; - regval |= denset; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); -#endif -} - -/**************************************************************************** - * Name: lm3s_initoutput - * - * Description: - * Set the GPIO output value - * - ****************************************************************************/ - -static inline void lm3s_initoutput(uint32_t cfgset) -{ - bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO); - lm3s_gpiowrite(cfgset, value); -} - -/**************************************************************************** - * Name: lm3s_interrupt - * - * Description: - * Configure the interrupt pin. - * - ****************************************************************************/ - -static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; - uint32_t regval; - uint32_t isset; - uint32_t isclr; - uint32_t ibeset; - uint32_t ibeclr; - uint32_t iveset; - uint32_t iveclr; - - /* Mask and clear the GPIO interrupt - * - * "The GPIOIM register is the interrupt mask register. Bits set to High in - * GPIO IM allow the corresponding pins to trigger their individual interrupts - * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering - * on that pin. All bits are cleared by a reset." - */ - - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - - /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit - * in this register clears the corresponding interrupt edge detection logic - * register. Writing a 0 has no effect." - */ - - regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); - regval |= pin; - putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); - - /* Assume rising edge */ - - isset = 0; /* Not level sensed */ - isclr = pin; - ibeset = 0; /* Single edge */ - ibeclr = pin; - iveset = pin; /* Rising edge or high levels*/ - iveclr = 0; - - /* Then handle according to the selected interrupt type */ - - switch (inttype) - { - case 0: /* Interrupt on falling edge */ - { - iveset = 0; /* Falling edge or low levels*/ - iveclr = pin; - } - break; - - case 1: /* Interrupt on rising edge */ - default: - break; - - case 2: /* Interrupt on both edges */ - { - ibeset = pin; /* Both edges */ - ibeclr = 0; - } - break; - - case 3: /* Interrupt on low level */ - { - isset = pin; /* Level sensed */ - isclr = 0; - iveset = 0; /* Falling edge or low levels*/ - iveclr = pin; - } - break; - - case 4: /* Interrupt on high level */ - { - isset = pin; /* Level sensed */ - isclr = 0; - } - break; - } - - /* "The GPIO IS register is the interrupt sense register. Bits set to - * 1 in GPIOIS configure the corresponding pins to detect levels, while - * bits set to 0 configure the pins to detect edges. All bits are cleared - * by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IS_OFFSET); - regval &= isclr; - regval |= isset; - putreg32(regval, base + LM3S_GPIO_IS_OFFSET); - - /* "The GPIO IBE register is the interrupt both-edges register. When the - * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is - * set to detect edges, bits set to High in GPIO IBE configure the - * corresponding pin to detect both rising and falling edges, regardless - * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ... - * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits - * are cleared by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); - regval &= ibeclr; - regval |= ibeset; - putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); - - /* "The GPIOIEV register is the interrupt event register. Bits set to - * High in GPIO IEV configure the corresponding pin to detect rising edges - * or high levels, depending on the corresponding bit value in the GPIO - * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to - * detect falling edges or low levels, depending on the corresponding bit - * value in GPIOIS. All bits are cleared by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); - regval &= iveclr; - regval |= iveset; - putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -int lm3s_configgpio(uint32_t cfgset) -{ - irqstate_t flags; - unsigned int func; - unsigned int port; - unsigned int pinno; - uint32_t pin; - uint32_t base; - uint32_t regval; - - /* Decode the basics */ - - func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT; - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pinno = (cfgset & GPIO_NUMBER_MASK); - pin = (1 <> GPIO_PORT_SHIFT; - pinno = (pinset & GPIO_NUMBER_MASK); - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - - /* "The GPIO DATA register is the data register. In software control mode, - * values written in the GPIO DATA register are transferred onto the GPIO - * port pins if the respective pins have been configured as outputs through - * the GPIO Direction (GPIO DIR) register ... - * - * "In order to write to GPIO DATA, the corresponding bits in the mask, - * resulting from the address bus bits [9:2], must be High. Otherwise, the - * bit values remain unchanged by the write. - * - * "... All bits are cleared by a reset." - */ - - putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); -} - -/**************************************************************************** - * Name: lm3s_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool lm3s_gpioread(uint32_t pinset, bool value) -{ - unsigned int port; - unsigned int pinno; - uint32_t base; - - /* Decode the basics */ - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pinno = (pinset & GPIO_NUMBER_MASK); - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - - /* "... the values read from this register are determined for each bit - * by the mask bit derived from the address used to access the data register, - * bits [9:2]. Bits that are 1 in the address mask cause the corresponding - * bits in GPIODATA to be read, and bits that are 0 in the address mask cause - * the corresponding bits in GPIO DATA to be read as 0, regardless of their - * value. - * - * "A read from GPIO DATA returns the last bit value written if the respective - * pins are configured as outputs, or it returns the value on the - * corresponding input pin when these are configured as inputs. All bits - * are cleared by a reset." - */ - - return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); -} - diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c deleted file mode 100644 index 511195f2d..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c +++ /dev/null @@ -1,434 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_gpioirq.c - * arch/arm/src/chip/lm3s_gpioirq.c - * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "os_internal.h" -#include "irq_internal.h" - -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A table of handlers for each GPIO interrupt */ - -static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; - -/* A table that maps a GPIO group to a GPIO base address. Overly complicated - * because we support disabling interrupt support for arbitrary ports. This - * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h - */ - -static const uint32_t g_gpiobase[] = -{ -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS - LM3S_GPIOA_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS - LM3S_GPIOB_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS - LM3S_GPIOC_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS - LM3S_GPIOD_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS - LM3S_GPIOE_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS - LM3S_GPIOF_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS - LM3S_GPIOG_BASE, -#endif - - /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip - * does not support these higher ports, then they must be disabled in the - * configuration. Otherwise, the following will likely cause compilation - * errors! - */ - -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS - LM3S_GPIOH_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS - LM3S_GPIOJ_BASE, -#endif -}; - -#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t)) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Input: - * gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS. - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. NOTE that range checking was provided by - * callee - * - ****************************************************************************/ - -static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq) -{ - unsigned int ndx = gpioirq >> 3; - if (ndx < GPIO_NADDRS) - { - return g_gpiobase[ndx]; - } - return 0; -} - -/**************************************************************************** - * Name: lm3s_gpio*handler - * - * Description: - * Handle interrupts on each enabled GPIO port - * - ****************************************************************************/ - -static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context) -{ - uint32_t mis; - int irq; - int pin; - - /* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked - * interrupt status register. Bits read High in GPIO MIS reflect the status - * of input lines triggering an interrupt. Bits read as Low indicate that - * either no interrupt has been generated, or the interrupt is masked." - */ - - mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; - - /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR - * register is the interrupt clear register. Writing a 1 to a bit in this - * register clears the corresponding interrupt edge detection logic register. - * Writing a 0 has no effect." - */ - - putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); - - /* Now process each IRQ pending in the MIS */ - - for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1) - { - if ((mis & 1) != 0) - { - irq = irqbase + pin; - g_gpioirqvector[irq - NR_IRQS](irq, context); - } - } - return OK; -} - -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS -static int lm3s_gpioahandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS -static int lm3s_gpiobhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS -static int lm3s_gpiochandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS -static int lm3s_gpiodhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS -static int lm3s_gpioehandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS -static int lm3s_gpiofhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS -static int lm3s_gpioghandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS -static int lm3s_gpiohhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS -static int lm3s_gpiojhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpio_irqinitialize - * - * Description: - * Initialize all vectors to the unexpected interrupt handler - * - ****************************************************************************/ - -int gpio_irqinitialize(void) -{ - int i; - - /* Point all interrupt vectors to the unexpected interrupt */ - - for (i = 0; i < NR_GPIO_IRQS; i++) - { - g_gpioirqvector[i] = irq_unexpected_isr; - } - - /* Then attach each GPIO interrupt handlers and enable corresponding GPIO - * interrupts - */ - -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS - irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler); - up_enable_irq(LM3S_IRQ_GPIOA); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS - irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler); - up_enable_irq(LM3S_IRQ_GPIOB); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS - irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler); - up_enable_irq(LM3S_IRQ_GPIOC); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS - irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler); - up_enable_irq(LM3S_IRQ_GPIOD); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS - irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler); - up_enable_irq(LM3S_IRQ_GPIOE); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS - irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler); - up_enable_irq(LM3S_IRQ_GPIOF); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS - irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler); - up_enable_irq(LM3S_IRQ_GPIOG); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS - irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler); - up_enable_irq(LM3S_IRQ_GPIOH); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS - irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler); - up_enable_irq(LM3S_IRQ_GPIOJ); -#endif - - return OK; -} - -/**************************************************************************** - * Name: gpio_irqattach - * - * Description: - * Attach in GPIO interrupt to the provide 'isr' - * - ****************************************************************************/ - -int gpio_irqattach(int irq, xcpt_t isr) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - int ret = ERROR; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - flags = irqsave(); - - /* If the new ISR is NULL, then the ISR is being detached. - * In this case, disable the ISR and direct any interrupts - * to the unexpected interrupt handler. - */ - - if (isr == NULL) - { -#ifndef CONFIG_ARCH_NOINTC - gpio_irqdisable(gpioirq); -#endif - isr = irq_unexpected_isr; - } - - /* Save the new ISR in the table. */ - - g_irqvector[gpioirq] = isr; - irqrestore(flags); - ret = OK; - } - return ret; -} - -/**************************************************************************** - * Name: gpio_irqenable - * - * Description: - * Enable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -void gpio_irqenable(int irq) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - uint32_t base; - uint32_t regval; - int pin; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - /* Get the base address of the GPIO module associated with this IRQ */ - - base = lm3s_gpiobaseaddress(gpioirq); - DEBUGASSERT(base != 0); - pin = (1 << (gpioirq & 7)); - - /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt - * mask register. Bits set to High in GPIO IM allow the corresponding - * pins to trigger their individual interrupts and the combined GPIO INTR - * line. Clearing a bit disables interrupt triggering on that pin. All - * bits are cleared by a reset. - */ - - flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval |= pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - irqrestore(flags); - } -} - -/**************************************************************************** - * Name: gpio_irqdisable - * - * Description: - * Disable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -void gpio_irqdisable(int irq) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - uint32_t base; - uint32_t regval; - int pin; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - /* Get the base address of the GPIO module associated with this IRQ */ - - base = lm3s_gpiobaseaddress(gpioirq); - DEBUGASSERT(base != 0); - pin = (1 << (gpioirq & 7)); - - /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt - * mask register. Bits set to High in GPIO IM allow the corresponding - * pins to trigger their individual interrupts and the combined GPIO INTR - * line. Clearing a bit disables interrupt triggering on that pin. All - * bits are cleared by a reset. - */ - - flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - irqrestore(flags); - } -} - diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c deleted file mode 100644 index 2f0b9fa72..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c +++ /dev/null @@ -1,458 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_irq.c - * arch/arm/src/chip/lm3s_irq.c - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nvic.h" -#include "up_arch.h" -#include "os_internal.h" -#include "up_internal.h" - -#include "chip.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Enable NVIC debug features that are probably only desireable during - * bringup - */ - -#undef LM3S_IRQ_DEBUG - -/* Get a 32-bit version of the default priority */ - -#define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ - NVIC_SYSH_PRIORITY_DEFAULT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_dumpnvic - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) -static void lm3s_dumpnvic(const char *msg, int irq) -{ - irqstate_t flags; - - flags = irqsave(); - slldbg("NVIC (%s, irq=%d):\n", msg, irq); - slldbg(" INTCTRL: %08x VECTAB: %08x\n", - getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); -#if 0 - slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", - getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), - getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); -#endif - slldbg(" IRQ ENABLE: %08x %08x\n", - getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); - slldbg(" SYSH_PRIO: %08x %08x %08x\n", - getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), - getreg32(NVIC_SYSH12_15_PRIORITY)); - slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), - getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); - slldbg(" %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), - getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); - slldbg(" %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), - getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); - irqrestore(flags); -} -#else -# define lm3s_dumpnvic(msg, irq) -#endif - -/**************************************************************************** - * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv, - * lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved - * - * Description: - * Handlers for various execptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG -static int lm3s_nmi(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! NMI received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_busfault(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Bus fault recived\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_usagefault(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Usage fault received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_pendsv(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! PendSV received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_dbgmonitor(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Debug Monitor receieved\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_reserved(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Reserved interrupt\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} -#endif - -/**************************************************************************** - * Name: lm3s_irqinfo - * - * Description: - * Given an IRQ number, provide the register and bit setting to enable or - * disable the irq. - * - ****************************************************************************/ - -static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) -{ - DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); - - /* Check for external interrupt */ - - if (irq >= LM3S_IRQ_INTERRUPTS) - { - if (irq < LM3S_IRQ_INTERRUPTS + 32) - { - *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); - } - else if (irq < NR_IRQS) - { - *regaddr = NVIC_IRQ32_63_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); - } - else - { - return ERROR; /* Invalid interrupt */ - } - } - - /* Handler processor exceptions. Only a few can be disabled */ - - else - { - *regaddr = NVIC_SYSHCON; - if (irq == LM3S_IRQ_MEMFAULT) - { - *bit = NVIC_SYSHCON_MEMFAULTENA; - } - else if (irq == LM3S_IRQ_BUSFAULT) - { - *bit = NVIC_SYSHCON_BUSFAULTENA; - } - else if (irq == LM3S_IRQ_USAGEFAULT) - { - *bit = NVIC_SYSHCON_USGFAULTENA; - } - else if (irq == LM3S_IRQ_SYSTICK) - { - *regaddr = NVIC_SYSTICK_CTRL; - *bit = NVIC_SYSTICK_CTRL_ENABLE; - } - else - { - return ERROR; /* Invalid or unsupported exception */ - } - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - /* Disable all interrupts */ - - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); - - /* Set all interrrupts (and exceptions) to the default priority */ - - putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); - - /* currents_regs is non-NULL only while processing an interrupt */ - - current_regs = NULL; - - /* Initialize support for GPIO interrupts if included in this build */ - -#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS -#ifdef CONFIG_HAVE_WEAKFUNCTIONS - if (gpio_irqinitialize != NULL) -#endif - { - gpio_irqinitialize(); - } -#endif - - /* Attach the SVCall and Hard Fault exception handlers. The SVCall - * exception is used for performing context switches; The Hard Fault - * must also be caught because a SVCall may show up as a Hard Fault - * under certain conditions. - */ - - irq_attach(LM3S_IRQ_SVCALL, up_svcall); - irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); - - /* Set the priority of the SVCall interrupt */ - -#ifdef CONFIG_ARCH_IRQPRIO -/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ -#endif - - /* If the MPU is enabled, then attach and enable the Memory Management - * Fault handler. - */ - -#ifdef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); - up_enable_irq(LM3S_IRQ_MEMFAULT); -#endif - - /* Attach all other processor exceptions (except reset and sys tick) */ - -#ifdef CONFIG_DEBUG - irq_attach(LM3S_IRQ_NMI, lm3s_nmi); -#ifndef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); -#endif - irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault); - irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault); - irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv); - irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor); - irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved); -#endif - - lm3s_dumpnvic("initial", NR_IRQS); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t bit; - - if (lm3s_irqinfo(irq, ®addr, &bit) == 0) - { - /* Clear the appropriate bit in the register to enable the interrupt */ - - regval = getreg32(regaddr); - regval &= ~bit; - putreg32(regval, regaddr); - } - lm3s_dumpnvic("disable", irq); -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t bit; - - if (lm3s_irqinfo(irq, ®addr, &bit) == 0) - { - /* Set the appropriate bit in the register to enable the interrupt */ - - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); - } - lm3s_dumpnvic("enable", irq); -} - -/**************************************************************************** - * Name: up_maskack_irq - * - * Description: - * Mask the IRQ and acknowledge it - * - ****************************************************************************/ - -void up_maskack_irq(int irq) -{ - up_disable_irq(irq); -} - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - * Since this API is not supported on all architectures, it should be - * avoided in common implementations where possible. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int irq, int priority) -{ - uint32_t regaddr; - uint32_t regval; - int shift; - - DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - - if (irq < LM3S_IRQ_INTERRUPTS) - { - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - } - else - { - irq -= LM3S_IRQ_INTERRUPTS; - regaddr = NVIC_IRQ_PRIORITY(irq); - } - - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); - - lm3s_dumpnvic("prioritize", irq); - return OK; -} -#endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c deleted file mode 100644 index bdbd5a906..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c +++ /dev/null @@ -1,309 +0,0 @@ -/************************************************************************** - * arch/arm/src/lm3s/lm3s_lowputc.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include - -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -#include "lm_gpio.h" -#include "chip/lm_pinmap.h" - -#include "lm_lowputc.h" - -/************************************************************************** - * Pre-processor Definitions - **************************************************************************/ - -/* Configuration **********************************************************/ - -#if LM3S_NUARTS < 2 -# undef CONFIG_LM3S_UART1 -# undef CONFIG_UART1_SERIAL_CONSOLE -#endif - -#if LM3S_NUARTS < 3 -# undef CONFIG_LM3S_UART2 -# undef CONFIG_UART2_SERIAL_CONSOLE -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#else -# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef HAVE_CONSOLE -#endif - -/* Select UART parameters for the selected console */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART0_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART1_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART2_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP -#else -# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" -#endif - -/* Get LCRH settings */ - -#if LM3S_CONSOLE_BITS == 5 -# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS -#elif LM3S_CONSOLE_BITS == 6 -# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS -#elif LM3S_CONSOLE_BITS == 7 -# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS -#elif LM3S_CONSOLE_BITS == 8 -# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS -#else -# error "Number of bits not supported" -#endif - -#if LM3S_CONSOLE_PARITY == 0 -# define UART_LCRH_PARITY (0) -#elif LM3S_CONSOLE_PARITY == 1 -# define UART_LCRH_PARITY UART_LCRH_PEN -#elif LM3S_CONSOLE_PARITY == 2 -# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) -#else -# error "Invalid parity selection" -#endif - -#if LM3S_CONSOLE_2STOP != 0 -# define UART_LCRH_NSTOP UART_LCRH_STP2 -#else -# define UART_LCRH_NSTOP (0) -#endif - -#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN) - -/* Calculate BAUD rate from the SYS clock: - * - * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit - * fractional part. The number formed by these two values is used by the baud-rate generator - * to determine the bit period. Having a fractional baud-rate divider allows the UART to - * generate all the standard baud rates. - * - * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) - * register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate - * Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship - * to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional - * part, separated by a decimal place.): - * - * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) - * - * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number - * (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated - * by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 - * to account for rounding errors: - * - * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) - * - * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred - * to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is - * used for error detection during receive operations. - * - * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and - * UARTFBRD registers form an internal 30-bit register. This internal register is only - * updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate - * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." - */ - -#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) -#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) -#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) -#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) - -/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: - * - * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 - * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 - * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 - * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 - * - * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 - */ - -/************************************************************************** - * Private Types - **************************************************************************/ - -/************************************************************************** - * Private Function Prototypes - **************************************************************************/ - -/************************************************************************** - * Global Variables - **************************************************************************/ - -/************************************************************************** - * Private Variables - **************************************************************************/ - -/************************************************************************** - * Private Functions - **************************************************************************/ - -/************************************************************************** - * Public Functions - **************************************************************************/ - -/************************************************************************** - * Name: up_lowputc - * - * Description: - * Output one byte on the serial console - * - **************************************************************************/ - -void up_lowputc(char ch) -{ -#ifdef HAVE_CONSOLE - /* Wait until the TX FIFO is not full */ - - while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); - - /* Then send the character */ - - putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); -#endif -} - -/************************************************************************** - * Name: up_lowsetup - * - * Description: - * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output availabe as soon - * as possible. - * - **************************************************************************/ - -void up_lowsetup(void) -{ - uint32_t regval; -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t ctl; -#endif - - /* Enable the selected UARTs and configure GPIO pins to need by the - * the selected UARTs. NOTE: The serial driver later depends on - * this pin configuration -- whether or not a serial console is selected. - */ - -#ifdef CONFIG_LM3S_UART0 - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_UART0; - putreg32(regval, LM3S_SYSCON_RCGC1); - - lm3s_configgpio(GPIO_UART0_RX); - lm3s_configgpio(GPIO_UART0_TX); -#endif - -#ifdef CONFIG_LM3S_UART1 - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_UART1; - putreg32(regval, LM3S_SYSCON_RCGC1); - - lm3s_configgpio(GPIO_UART1_RX); - lm3s_configgpio(GPIO_UART1_TX); -#endif - - /* Enable the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - - ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); - ctl &= ~UART_CTL_UARTEN; - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); - - /* Write the integer portion of the BRD to the UART IBRD register */ - - putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); - - /* Write the fractional portion of the BRD to the UART FBRD register */ - - putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); - - /* Write the desired serial parameters to the UART LCRH register */ - - putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); - - /* Enable the UART by setting the UARTEN bit in the UART CTL register */ - - ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); -#endif - -} - - diff --git a/nuttx/arch/arm/src/lm3s/lm3s_serial.c b/nuttx/arch/arm/src/lm3s/lm3s_serial.c deleted file mode 100644 index 7ed9b6fa8..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_serial.c +++ /dev/null @@ -1,1064 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_serial.c - * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" -#include "os_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -#if LM3S_NUARTS < 2 -# undef CONFIG_LM3S_UART1 -# undef CONFIG_UART1_SERIAL_CONSOLE -#endif - -#if LM3S_NUARTS < 3 -# undef CONFIG_LM3S_UART2 -# undef CONFIG_UART2_SERIAL_CONSOLE -#endif - -/* Is there a UART enabled? */ - -#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2) -# error "No UARTs enabled" -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#else -# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef HAVE_CONSOLE -#endif - -/* If we are not using the serial driver for the console, then we - * still must provide some minimal implementation of up_putc. - */ - -#ifdef USE_SERIALDRIVER - -/* Which UART with be tty0/console and which tty1? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* UART0 is console */ -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# ifdef CONFIG_LM3S_UART1 -# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart1port /* UART1 is console */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# ifdef CONFIG_LM3S_UART0 -# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart2port /* UART2 is console */ -# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ -# ifdef CONFIG_LM3S_UART0 -# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elifdefined(CONFIG_LM3S_UART0) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# ifdef CONFIG_LM3S_UART1 -# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elifdefined(CONFIG_LM3S_UART1) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -#elifdefined(CONFIG_LM3S_UART2) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ -# undef TTYS1_DEV /* No ttyS1 */ -# undef TTYS2_DEV /* No ttyS2 */ -#else -# error "No valid TTY devices" -# undef CONSOLE_DEV /* No console device */ -# undef TTYS0_DEV /* No ttyS0 */ -# undef TTYS1_DEV /* No ttyS1 */ -# undef TTYS2_DEV /* No ttyS2 */ -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - uint32_t uartbase; /* Base address of UART registers */ - uint32_t baud; /* Configured baud */ - uint32_t im; /* Saved IM value */ - uint8_t irq; /* IRQ associated with this UART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -#ifdef CONFIG_LM3S_UART0 -static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -#endif -#ifdef CONFIG_LM3S_UART1 -static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; -static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; -#endif -#ifdef CONFIG_LM3S_UART2 -static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; -static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; -#endif - -/* This describes the state of the LM3S uart0 port. */ - -#ifdef CONFIG_LM3S_UART0 -static struct up_dev_s g_uart0priv = -{ - .uartbase = LM3S_UART0_BASE, - .baud = CONFIG_UART0_BAUD, - .irq = LM3S_IRQ_UART0, - .parity = CONFIG_UART0_PARITY, - .bits = CONFIG_UART0_BITS, - .stopbits2 = CONFIG_UART0_2STOP, -}; - -static uart_dev_t g_uart0port = -{ - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, -}; -#endif - -/* This describes the state of the LM3S uart1 port. */ - -#ifdef CONFIG_LM3S_UART1 -static struct up_dev_s g_uart1priv = -{ - .uartbase = LM3S_UART1_BASE, - .baud = CONFIG_UART1_BAUD, - .irq = LM3S_IRQ_UART1, - .parity = CONFIG_UART1_PARITY, - .bits = CONFIG_UART1_BITS, - .stopbits2 = CONFIG_UART1_2STOP, -}; - -static uart_dev_t g_uart1port = -{ - .recv = - { - .size = CONFIG_UART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart1priv, -}; -#endif - -/* This describes the state of the LM3S uart1 port. */ - -#ifdef CONFIG_LM3S_UART2 -static struct up_dev_s g_uart2priv = -{ - .uartbase = LM3S_UART2_BASE, - .baud = CONFIG_UART2_BAUD, - .irq = LM3S_IRQ_UART2, - .parity = CONFIG_UART2_PARITY, - .bits = CONFIG_UART2_BITS, - .stopbits2 = CONFIG_UART2_2STOP, -}; - -static uart_dev_t g_uart2port = -{ - .recv = - { - .size = CONFIG_UART2_RXBUFSIZE, - .buffer = g_uart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART2_TXBUFSIZE, - .buffer = g_uart2txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart2priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialin - ****************************************************************************/ - -static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) -{ - return getreg32(priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) -{ - putreg32(value, priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_disableuartint - ****************************************************************************/ - -static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) -{ - /* Return the current interrupt mask value */ - - if (im) - { - *im = priv->im; - } - - /* Disable all interrupts */ - - priv->im = 0; - up_serialout(priv, LM3S_UART_IM_OFFSET, 0); -} - -/**************************************************************************** - * Name: up_restoreuartint - ****************************************************************************/ - -static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) -{ - priv->im = im; - up_serialout(priv, LM3S_UART_IM_OFFSET, im); -} - -/**************************************************************************** - * Name: up_waittxnotfull - ****************************************************************************/ - -#ifdef HAVE_CONSOLE -static inline void up_waittxnotfull(struct up_dev_s *priv) -{ - int tmp; - - /* Limit how long we will wait for the TX available condition */ - - for (tmp = 1000 ; tmp > 0 ; tmp--) - { - /* Check Tx FIFO is full */ - - if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) - { - /* The Tx FIFO is not full... return */ - - break; - } - } - - /* If we get here, then the wait has timed out and the Tx FIFO remains - * full. - */ -} -#endif - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is - * opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32_t lcrh; - uint32_t ctl; -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t den; - uint32_t brdi; - uint32_t remainder; - uint32_t divfrac; - - /* Note: The logic here depends on the fact that that the UART module - * was enabled and the GPIOs were configured in up_lowsetup(). - */ - - /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); - ctl &= ~UART_CTL_UARTEN; - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); - - /* Calculate BAUD rate from the SYS clock: - * - * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer - * and a 6-bit fractional part. The number formed by these two values is - * used by the baud-rate generator to determine the bit period. Having a - * fractional baud-rate divider allows the UART to generate all the standard - * baud rates. - * - * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor - * (UARTIBRD) register ... and the 6-bit fractional part is loaded with the - * UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate - * divisor (BRD) has the following relationship to the system clock (where - * BRDI is the integer part of the BRD and BRDF is the fractional part, - * separated by a decimal place.): - * - * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) - * - * "where UARTSysClk is the system clock connected to the UART. The 6-bit - * fractional number (that is to be loaded into the DIVFRAC bit field in the - * UARTFBRD register) can be calculated by taking the fractional part of the - * baud-rate divisor, multiplying it by 64, and adding 0.5 to account for - * rounding errors: - * - * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) - * - * "The UART generates an internal baud-rate reference clock at 16x the baud- - * rate (referred to as Baud16). This reference clock is divided by 16 to - * generate the transmit clock, and is used for error detection during receive - * operations. - * - * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the - * UARTIBRD and UARTFBRD registers form an internal 30-bit register. This - * internal register is only updated when a write operation to UARTLCRH is - * performed, so any changes to the baud-rate divisor must be followed by a - * write to the UARTLCRH register for the changes to take effect. ..." - */ - - den = priv->baud << 4; - brdi = SYSCLK_FREQUENCY / den; - remainder = SYSCLK_FREQUENCY - den * brdi; - divfrac = ((remainder << 6) + (den >> 1)) / den; - - up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); - up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); - - /* Set up the LCRH register */ - - lcrh = 0; - switch (priv->bits) - { - case 5: - lcrh |= UART_LCRH_WLEN_5BITS; - break; - case 6: - lcrh |= UART_LCRH_WLEN_6BITS; - break; - case 7: - lcrh |= UART_LCRH_WLEN_7BITS; - break; - case 8: - default: - lcrh |= UART_LCRH_WLEN_8BITS; - break; - } - - switch (priv->parity) - { - case 0: - default: - break; - case 1: - lcrh |= UART_LCRH_PEN; - break; - case 2: - lcrh |= UART_LCRH_PEN|UART_LCRH_EPS; - break; - } - - if (priv->stopbits2) - { - lcrh |= UART_LCRH_STP2; - } - - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); -#endif - - /* Set the UART to interrupt whenever the TX FIFO is almost empty or when - * any character is received. - */ - - up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); - - /* Flush the Rx and Tx FIFOs -- How do you do that?*/ - - /* Enable Rx interrupts from the UART except for Tx interrupts. We don't want - * Tx interrupts until we have something to send. We will check for serial - * errors as part of Rx interrupt processing (no interrupts will be received - * yet because the interrupt is still disabled at the interrupt controller. - */ - - up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); - - /* Enable the FIFOs */ - -#ifdef CONFIG_SUPPRESS_UART_CONFIG - lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); -#endif - lcrh |= UART_LCRH_FEN; - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); - - /* Enable Rx, Tx, and the UART */ - -#ifdef CONFIG_SUPPRESS_UART_CONFIG - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); -#endif - ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); - - /* Set up the cache IM value */ - - priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_disableuartint(priv, NULL); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked - * when an interrupt received on the 'irq' It should call - * uart_transmitchars or uart_receivechar to perform the - * appropriate data transfers. The interrupt handling logic\ - * must be able to map the 'irq' number into the approprite - * uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context) -{ - struct uart_dev_s *dev = NULL; - struct up_dev_s *priv; - uint32_t mis; - int passes; - bool handled; - -#ifdef CONFIG_LM3S_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_LM3S_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif - { - PANIC(OSERR_INTERNAL); - } - priv = (struct up_dev_s*)dev->priv; - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the masked UART status and clear the pending interrupts. */ - - mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); - up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); - - /* Handle incoming, receive bytes (with or without timeout) */ - - if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0) - { - /* Rx buffer not empty ... process incoming bytes */ - - uart_recvchars(dev); - handled = true; - } - - /* Handle outgoing, transmit bytes */ - - if ((mis & UART_MIS_TXMIS) != 0) - { - /* Tx FIFO not full ... process outgoing bytes */ - - uart_xmitchars(dev); - handled = true; - } - } - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; - int ret = OK; - - switch (cmd) - { - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s*)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, uint32_t *status) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32_t rxd; - - /* Get the Rx byte + 4 bits of error information. Return those in status */ - - rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); - *status = rxd; - - /* The lower 8bits of the Rx data is the actual recevied byte */ - - return rxd & 0xff; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - if (enable) - { - /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx - * timeout occurs. - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->im |= (UART_IM_RXIM|UART_IM_RTIM); -#endif - } - else - { - priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); - } - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - irqstate_t flags; - - flags = irqsave(); - if (enable) - { - /* Set to receive an interrupt when the TX fifo is half emptied */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->im |= UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); - - /* The serial driver wants an interrupt here, but will not get get - * one unless we "prime the pump." I believe that this is because - * behave like a level interrupt and the LM3S interrupts behave - * (at least by default) like edge interrupts. - * - * In any event, faking a TX interrupt here solves the problem; - * Call uart_xmitchars() just as would have been done if we recieved - * the TX interrupt. - */ - - uart_xmitchars(dev); -#endif - } - else - { - /* Disable the TX interrupt */ - - priv->im &= ~UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); - } - irqrestore(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Performs the low level UART initialization early in - * debug so that the serial console will be available - * during bootup. This must be called before up_serialinit. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ - /* NOTE: All GPIO configuration for the UARTs was performed in - * up_lowsetup - */ - - /* Disable all UARTS */ - - up_disableuartint(TTYS0_DEV.priv, NULL); -#ifdef TTYS1_DEV - up_disableuartint(TTYS1_DEV.priv, NULL); -#endif -#ifdef TTYS2_DEV - up_disableuartint(TTYS2_DEV.priv, NULL); -#endif - - /* Configuration whichever one is the console */ - -#ifdef HAVE_CONSOLE - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -#endif -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ - /* Register the console */ - -#ifdef HAVE_CONSOLE - (void)uart_register("/dev/console", &CONSOLE_DEV); -#endif - - /* Register all UARTs */ - - (void)uart_register("/dev/ttyS0", &TTYS0_DEV); -#ifdef TTYS1_DEV - (void)uart_register("/dev/ttyS1", &TTYS1_DEV); -#endif -#ifdef TTYS2_DEV - (void)uart_register("/dev/ttyS2", &TTYS2_DEV); -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; - uint32_t im; - - up_disableuartint(priv, &im); - up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); - } - - up_waittxnotfull(priv); - up_restoreuartint(priv, im); -#endif - return ch; -} - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_CONSOLE - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_lowputc('\r'); - } - - up_lowputc(ch); -#endif - return ch; -} - -#endif /* USE_SERIALDRIVER */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c deleted file mode 100644 index 8cd1cee07..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c +++ /dev/null @@ -1,1580 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm32/lm3s_ssi.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "lm_gpio.h" -#include "lm_ssi.h" -#include "chip/lm_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG with - * CONFIG_DEBUG_VERBOSE too) - */ - -#undef SSI_DEBUG /* Define to enable debug */ - -#ifdef SSI_DEBUG -# define ssidbg lldbg -# define ssivdbg llvdbg -#else -# define ssidbg(x...) -# define ssivdbg(x...) -#endif - -/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI - * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in - * such case, the following must be expanded). - */ - -#if LM3S_NSSI == 0 -# undef CONFIG_SSI0_DISABLE -# define CONFIG_SSI0_DISABLE 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#endif - -/* Which SSI modules have been enabled? */ - -#ifndef CONFIG_SSI0_DISABLE -# define SSI0_NDX 0 /* Index to SSI0 in g_ssidev[] */ -# ifndef CONFIG_SSI1_DISABLE -# define SSI1_NDX 1 /* Index to SSI1 in g_ssidev[] */ -# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ -# else -# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ -# define SSI_BASE LM3S_SSI0_BASE -# define SSI_IRQ LM3S_IRQ_SSI0 -# endif -#else -# ifndef CONFIG_SSI1_DISABLE -# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ -# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ -# define SSI_BASE LM3S_SSI1_BASE -# define SSI_IRQ LM3S_IRQ_SSI1 -# else -# define NSSI_ENABLED 0 /* No SSI interfaces */ -# endif -#endif - -/* Compile the rest of the file only if at least one SSI interface has been - * enabled. - */ - -#if NSSI_ENABLED > 0 - -/* The number of (16-bit) words that will fit in the Tx FIFO */ - -#define LM3S_TXFIFO_WORDS 8 - -/* Configuration settings */ - -#ifndef CONFIG_SSI_TXLIMIT -# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) -#endif - -#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS -# error "Invalid range for CONFIG_SSI_TXLIMIT" -#endif - -#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) -# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" -#endif - -/**************************************************************************** - * Private Type Definitions - ****************************************************************************/ - -struct lm3s_ssidev_s -{ - const struct spi_ops_s *ops; /* Common SPI operations */ -#ifndef CONFIG_SSI_POLLWAIT - sem_t xfrsem; /* Wait for transfer to complete */ -#endif - - /* These following are the source and destination buffers of the transfer. - * they are retained in this structure so that they will be accessible - * from an interrupt handler. The actual type of the buffer is uint8_t if - * nbits <=8 and uint16_t if nbits >8. - */ - - void *txbuffer; /* Source buffer */ - void *rxbuffer; /* Destination buffer */ - - /* These are functions pointers that are configured to perform the - * appropriate transfer for the particular kind of exchange that is - * occurring. Differnt functions may be selected depending on (1) - * if the tx or txbuffer is NULL and depending on the number of bits - * per word. - */ - - void (*txword)(struct lm3s_ssidev_s *priv); - void (*rxword)(struct lm3s_ssidev_s *priv); - -#if NSSI_ENABLED > 1 - uint32_t base; /* SSI register base address */ -#endif - - int ntxwords; /* Number of words left to transfer on the Tx FIFO */ - int nrxwords; /* Number of words received on the Rx FIFO */ - int nwords; /* Number of words to be exchanged */ - uint8_t nbits; /* Current number of bits per word */ - -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - uint8_t irq; /* SSI IRQ number */ -#endif - - /* If there is more than one device on the SPI bus, then we have to enforce - * mutual exclusion and remember some configuration settings to reduce the - * overhead of constant SPI re-configuration. - */ - -#ifndef CONFIG_SPI_OWNBUS - sem_t exclsem; /* For exclusive access to the SSI bus */ - uint32_t frequency; /* Current desired SCLK frequency */ - uint32_t actual; /* Current actual SCLK frequency */ - uint8_t mode; /* Current mode 0,1,2,3 */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* SSI register access */ - -static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, - unsigned int offset); -static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, - uint32_t value); - -/* Misc helpers */ - -static uint32_t ssi_disable(struct lm3s_ssidev_s *priv); -static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable); - -#ifndef CONFIG_SSI_POLLWAIT -static void ssi_semtake(sem_t *sem); -#define ssi_semgive(s) sem_post(s); -#endif - -/* SSI data transfer */ - -static void ssi_txnull(struct lm3s_ssidev_s *priv); -static void ssi_txuint16(struct lm3s_ssidev_s *priv); -static void ssi_txuint8(struct lm3s_ssidev_s *priv); -static void ssi_rxnull(struct lm3s_ssidev_s *priv); -static void ssi_rxuint16(struct lm3s_ssidev_s *priv); -static void ssi_rxuint8(struct lm3s_ssidev_s *priv); -static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv); -static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv); -#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) -static inline int ssi_performtx(struct lm3s_ssidev_s *priv); -#else -static int ssi_performtx(struct lm3s_ssidev_s *priv); -#endif -static inline void ssi_performrx(struct lm3s_ssidev_s *priv); -static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, - void *rxbuffer, unsigned int nwords); - -/* Interrupt handling */ - -#ifndef CONFIG_SSI_POLLWAIT -static inline struct lm3s_ssidev_s *ssi_mapirq(int irq); -static int ssi_interrupt(int irq, void *context); -#endif - -/* SPI methods */ - -#ifndef CONFIG_SPI_OWNBUS -static int ssi_lock(FAR struct spi_dev_s *dev, bool lock); -#endif -static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, - uint32_t frequency); -static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, - uint32_t frequency); -static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, - enum spi_mode_e mode); -static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); -static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits); -static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits); -static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd); -#ifdef CONFIG_SPI_EXCHANGE -static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords); -#else -static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, - size_t nwords); -static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Common SSI operations */ - -static const struct spi_ops_s g_spiops = -{ -#ifndef CONFIG_SPI_OWNBUS - .lock = ssi_lock, -#endif - .select = lm3s_spiselect, /* Provided externally by board logic */ - .setfrequency = ssi_setfrequency, - .setmode = ssi_setmode, - .setbits = ssi_setbits, - .status = lm3s_spistatus, /* Provided externally by board logic */ -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lm3s_spicmddata, -#endif - .send = ssi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = ssi_exchange, -#else - .sndblock = ssi_sndblock, - .recvblock = ssi_recvblock, -#endif -}; - -/* This supports is up to two SSI busses/ports */ - -static struct lm3s_ssidev_s g_ssidev[] = -{ -#ifndef CONFIG_SSI0_DISABLE - { - .ops = &g_spiops, -#if NSSI_ENABLED > 1 - .base = LM3S_SSI0_BASE, -#endif -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI0, -#endif - }, -#endif -#ifndef CONFIG_SSI1_DISABLE - { - .ops = &g_spiops, -#if NSSI_ENABLED > 1 - .base = LM3S_SSI1_BASE, -#endif -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI1, -#endif - }, -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ssi_getreg - * - * Description: - * Read the SSI register at this offeset - * - * Input Parameters: - * priv - Device-specific state data - * offset - Offset to the SSI register from the register base address - * - * Returned Value: - * Value of the register at this offset - * - ****************************************************************************/ - -static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset) -{ -#if NSSI_ENABLED > 1 - return getreg32(priv->base + offset); -#else - return getreg32(SSI_BASE + offset); -#endif -} - -/**************************************************************************** - * Name: ssi_putreg - * - * Description: - * Write the value to the SSI register at this offeset - * - * Input Parameters: - * priv - Device-specific state data - * offset - Offset to the SSI register from the register base address - * value - Value to write - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value) -{ -#if NSSI_ENABLED > 1 - putreg32(value, priv->base + offset); -#else - putreg32(value, SSI_BASE + offset); -#endif -} - -/**************************************************************************** - * Name: ssi_disable - * - * Description: - * Disable SSI operation. NOTE: The SSI must be disabled before any control - * registers can be re-programmed. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * State of the SSI before the SSE was disabled - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static uint32_t ssi_disable(struct lm3s_ssidev_s *priv) -{ - uint32_t retval; - uint32_t regval; - - retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); - regval = (retval & ~SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); - ssivdbg("CR1: %08x\n", regval); - return retval; -} - -/**************************************************************************** - * Name: ssi_enable - * - * Description: - * Restore the SSI operational state - * - * Input Parameters: - * priv - Device-specific state data - * enable - The previous operational state - * - * Returned Value: - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable) -{ - uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); - regval &= ~SSI_CR1_SSE; - regval |= (enable & SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); - ssivdbg("CR1: %08x\n", regval); -} - -/**************************************************************************** - * Name: ssi_semtake - * - * Description: - * Wait for a semaphore (handling interruption by signals); - * - * Input Parameters: - * priv - Device-specific state data - * enable - The previous operational state - * - * Returned Value: - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static void ssi_semtake(sem_t *sem) -{ - int ret; - do - { - ret = sem_wait(sem); - } - while (ret < 0 && errno == EINTR); - DEBUGASSERT(ret == 0); -} -#endif - -/**************************************************************************** - * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8 - * - * Description: - * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer - * pointer appropriately. The selected function dependes on (1) if there - * is a source txbuffer provided, and (2) if the number of bits per - * word is <=8 or >8. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssi_txnull(struct lm3s_ssidev_s *priv) -{ - ssivdbg("TX: ->0xffff\n"); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); -} - -static void ssi_txuint16(struct lm3s_ssidev_s *priv) -{ - uint16_t *ptr = (uint16_t*)priv->txbuffer; - ssivdbg("TX: %p->%04x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); - priv->txbuffer = (void*)ptr; -} - -static void ssi_txuint8(struct lm3s_ssidev_s *priv) -{ - uint8_t *ptr = (uint8_t*)priv->txbuffer; - ssivdbg("TX: %p->%02x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); - priv->txbuffer = (void*)ptr; -} - -/**************************************************************************** - * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8 - * - * Description: - * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the - * user rxvbuffer and update the rxbuffer pointer appropriately. The - * selected function dependes on (1) if there is a desination rxbuffer - * provided, and (2) if the number of bits per word is <=8 or >8. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssi_rxnull(struct lm3s_ssidev_s *priv) -{ -#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) - uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: discard %04x\n", regval); -#else - (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); -#endif -} - -static void ssi_rxuint16(struct lm3s_ssidev_s *priv) -{ - uint16_t *ptr = (uint16_t*)priv->rxbuffer; - *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: %p<-%04x\n", ptr, *ptr); - priv->rxbuffer = (void*)(++ptr); -} - -static void ssi_rxuint8(struct lm3s_ssidev_s *priv) -{ - uint8_t *ptr = (uint8_t*)priv->rxbuffer; - *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: %p<-%02x\n", ptr, *ptr); - priv->rxbuffer = (void*)(++ptr); -} - -/**************************************************************************** - * Name: ssi_txfifofull - * - * Description: - * Return true if the Tx FIFO is full - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * true: Not full - * - ****************************************************************************/ - -static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv) -{ - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; -} - -/**************************************************************************** - * Name: ssi_rxfifoempty - * - * Description: - * Return true if the Rx FIFO is empty - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * true: Not empty - * - ****************************************************************************/ - -static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv) -{ - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; -} - -/**************************************************************************** - * Name: ssi_performtx - * - * Description: - * If the Tx FIFO is empty, then transfer as many words as we can to - * the FIFO. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * The number of words written to the Tx FIFO (a value from 0 to 8, - * inclusive). - * - ****************************************************************************/ - -#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) -static inline int ssi_performtx(struct lm3s_ssidev_s *priv) -{ - /* Check if the Tx FIFO is full and more data to transfer */ - - if (!ssi_txfifofull(priv) && priv->ntxwords > 0) - { - /* Transfer one word to the Tx FIFO */ - - priv->txword(priv); - priv->ntxwords--; - return 1; - } - return 0; -} - -#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ - -static int ssi_performtx(struct lm3s_ssidev_s *priv) -{ -#ifndef CONFIG_SSI_POLLWAIT - uint32_t regval; -#endif - int ntxd = 0; /* Number of words written to Tx FIFO */ - - /* Check if the Tx FIFO is full */ - - if (!ssi_txfifofull(priv)) - { - /* Not full.. Check if all of the Tx words have been sent */ - - if (priv->ntxwords > 0) - { - /* No.. Transfer more words until either the Tx FIFO is full or - * until all of the user provided data has been sent. - */ -#ifdef CONFIG_SSI_TXLIMIT - /* Further limit the number of words that we put into the Tx - * FIFO to CONFIG_SSI_TXLIMIT. Otherwise, we could - * overrun the Rx FIFO on a very fast SSI bus. - */ - for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++) -#else - for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++) -#endif - { - priv->txword(priv); - } - - /* Update the count of words to to transferred */ - - priv->ntxwords -= ntxd; - } - - /* Check again... Now have all of the Tx words been sent? */ - -#ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); - if (priv->ntxwords > 0) - { - /* No.. Enable the Tx FIFO interrupt. This interrupt occurs - * when the Tx FIFO is 1/2 full or less. - */ - -#ifdef CONFIG_DEBUG - regval |= (SSI_IM_TX|SSI_RIS_ROR); -#else - regval |= SSI_IM_TX; -#endif - } - else - { - /* Yes.. Disable the Tx FIFO interrupt. The final stages of - * the transfer will be driven by Rx FIFO interrupts. - */ - - regval &= ~(SSI_IM_TX|SSI_RIS_ROR); - } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); -#endif /* CONFIG_SSI_POLLWAIT */ - } - return ntxd; -} - -#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ - -/**************************************************************************** - * Name: ssi_performrx - * - * Description: - * Transfer as many bytes as possible from the Rx FIFO to the user Rx - * buffer (if one was provided). - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ssi_performrx(struct lm3s_ssidev_s *priv) -{ -#ifndef CONFIG_SSI_POLLWAIT - uint32_t regval; -#endif - - /* Loop while data is available in the Rx FIFO */ - - while (!ssi_rxfifoempty(priv)) - { - /* Have all of the requested words been transferred from the Rx FIFO? */ - - if (priv->nrxwords < priv->nwords) - { - /* No.. Read more data from Rx FIFO */ - - priv->rxword(priv); - priv->nrxwords++; - } - } - - /* The Rx FIFO is now empty. While there is Tx data to be sent, the - * transfer will be driven by Tx FIFO interrupts. The final part - * of the transfer is driven by Rx FIFO interrupts only. - */ - -#ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); - if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) - { - /* There are no more outgoing words to send, but there are - * additional incoming words expected (I would think that this - * a real corner case, be we will handle it with an extra - * interrupt, probably an Rx timeout). - */ - -#ifdef CONFIG_DEBUG - regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR); -#else - regval |= (SSI_IM_RX|SSI_IM_RT); -#endif - } - else - { - /* No.. there are either more Tx words to send or all Rx words - * have received. Disable Rx FIFO interrupts. - */ - - regval &= ~(SSI_IM_RX|SSI_IM_RT); - } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); -#endif /* CONFIG_SSI_POLLWAIT */ -} - -/**************************************************************************** - * Name: ssi_transfer - * - * Description: - * Exchange a block data with the SPI device - * - * Input Parameters: - * priv - Device-specific state data - * txbuffer - The buffer of data to send to the device (may be NULL). - * rxbuffer - The buffer to receive data from the device (may be NULL). - * nwords - The total number of words to be exchanged. If the interface - * uses <= 8 bits per word, then this is the number of uint8_t's; - * if the interface uses >8 bits per word, then this is the - * number of uint16_t's - * - * Returned Value: - * 0: success, <0:Negated error number on failure - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, - void *rxbuffer, unsigned int nwords) -{ -#ifndef CONFIG_SSI_POLLWAIT - irqstate_t flags; -#endif - int ntxd; - - ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords); - - /* Set up to perform the transfer */ - - priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */ - priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */ - priv->ntxwords = nwords; /* Number of words left to send */ - priv->nrxwords = 0; /* Number of words received */ - priv->nwords = nwords; /* Total number of exchanges */ - - /* Set up the low-level data transfer function pointers */ - - if (priv->nbits > 8) - { - priv->txword = ssi_txuint16; - priv->rxword = ssi_rxuint16; - } - else - { - priv->txword = ssi_txuint8; - priv->rxword = ssi_rxuint8; - } - - if (!txbuffer) - { - priv->txword = ssi_txnull; - } - - if (!rxbuffer) - { - priv->rxword = ssi_rxnull; - } - - /* Prime the Tx FIFO to start the sequence (saves one interrupt). - * At this point, all SSI interrupts should be disabled, but the - * operation of ssi_performtx() will set up the interrupts - * approapriately (if nwords > TxFIFO size). - */ - -#ifndef CONFIG_SSI_POLLWAIT - flags = irqsave(); - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); - - ntxd = ssi_performtx(priv); - - /* For the case where nwords < Tx FIFO size, ssi_performrx will - * configure interrupts correctly for the final phase of the - * the transfer. - */ - - ssi_performrx(priv); - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); - - /* Wait for the transfer to complete. Since there is no handshake - * with SPI, the following should complete even if there are problems - * with the transfer, so it should be safe with no timeout. - */ - - ssivdbg("Waiting for transfer complete\n"); - irqrestore(flags); - do - { - ssi_semtake(&priv->xfrsem); - } - while (priv->nrxwords < priv->nwords); - ssidbg("Transfer complete\n"); - -#else - /* Perform the transfer using polling logic. This will totally - * dominate the CPU until the transfer is complete. Only recommended - * if (1) your SPI is very fast, and (2) if you only use very short - * transfers. - */ - - do - { - /* Handle outgoing Tx FIFO transfers */ - - ntxd = ssi_performtx(priv); - - /* Handle incoming Rx FIFO transfers */ - - ssi_performrx(priv); - - /* If there are other threads at this same priority level, - * the following may help: - */ - - sched_yield(); - } - while (priv->nrxwords < priv->nwords); -#endif - return OK; -} - -/**************************************************************************** - * Name: ssi_mapirq - * - * Description: - * Map an IRQ number into the appropriate SSI device - * - * Input Parameters: - * irq - The IRQ number to be mapped - * - * Returned Value: - * On success, a reference to the private data structgure for this IRQ. - * NULL on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static inline struct lm3s_ssidev_s *ssi_mapirq(int irq) -{ - switch (irq) - { -#ifndef CONFIG_SSI0_DISABLE - case LM3S_IRQ_SSI0: - return &g_ssidev[SSI0_NDX]; -#endif -#ifndef CONFIG_SSI1_DISABLE - case LM3S_IRQ_SSI1: - return &g_ssidev[SSI1_NDX]; -#endif - default: - return NULL; - } -} -#endif - -/**************************************************************************** - * Name: ssi_interrupt - * - * Description: - * Exchange a block data with the SSI device - * - * Input Parameters: - * priv - Device-specific state data - * txbuffer - The buffer of data to send to the device (may be NULL). - * rxbuffer - The buffer to receive data from the device (may be NULL). - * nwords - The total number of words to be exchanged. If the interface - * uses <= 8 bits per word, then this is the number of uint8_t's; - * if the interface uses >8 bits per word, then this is the - * number of uint16_t's - * - * Returned Value: - * 0: success, <0:Negated error number on failure - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static int ssi_interrupt(int irq, void *context) -{ - struct lm3s_ssidev_s *priv = ssi_mapirq(irq); - uint32_t regval; - int ntxd; - - DEBUGASSERT(priv != NULL); - - /* Clear pending interrupts */ - - regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); - ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); - - /* Check for Rx FIFO overruns */ - -#ifdef CONFIG_DEBUG - if ((regval & SSI_RIS_ROR) != 0) - { - lldbg("Rx FIFO Overrun!\n"); - } -#endif - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); - - /* Handle outgoing Tx FIFO transfers */ - - ntxd = ssi_performtx(priv); - - /* Handle incoming Rx FIFO transfers */ - - ssi_performrx(priv); - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); - - /* Check if the transfer is complete */ - - if (priv->nrxwords >= priv->nwords) - { - /* Yes.. Disable all SSI interrupt sources */ - - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); - - /* Wake up the waiting thread */ - - ssidbg("Transfer complete\n"); - ssi_semgive(&priv->xfrsem); - } - return OK; -} -#endif - -/**************************************************************************** - * Name: ssi_lock - * - * Description: - * On SPI busses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the busses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_OWNBUS -static int ssi_lock(FAR struct spi_dev_s *dev, bool lock) -{ - FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev; - - if (lock) - { - /* Take the semaphore (perhaps waiting) */ - - while (sem_wait(&priv->exclsem) != 0) - { - /* The only case that an error should occur here is if the wait was awakened - * by a signal. - */ - - ASSERT(errno == EINTR); - } - } - else - { - (void)sem_post(&priv->exclsem); - } - return OK; -} -#endif - -/**************************************************************************** - * Name: ssi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency) -{ - uint32_t maxdvsr; - uint32_t cpsdvsr; - uint32_t regval; - uint32_t scr; - uint32_t actual; - - ssidbg("frequency: %d\n", frequency); - DEBUGASSERT(frequency); - - /* Has the frequency changed? */ - -#ifndef CONFIG_SPI_OWNBUS - if (frequency != priv->frequency) - { -#endif - /* "The serial bit rate is derived by dividing down the input clock - * (FSysClk). The clock is first divided by an even prescale value - * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale - * (SSI_CPSR) register ... The clock is further divided by a value - * from 1 to 256, which is 1 + SCR, where SCR is the value programmed - * i n the SSI Control0 (SSICR0) register ... - * - * "The frequency of the output clock SSIClk is defined by: - * - * "SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) - * - * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz, - * the module may not be able to operate at that speed. For master mode, - * the system clock must be at least two times faster than the SSIClk. - * For slave mode, the system clock must be at least 12 times faster - * than the SSIClk." - */ - - if (frequency > SYSCLK_FREQUENCY/2) - { - frequency = SYSCLK_FREQUENCY/2; - } - - /* Find optimal values for CPSDVSR and SCR. This loop is inefficient, - * but should not have to execute many times. - * - * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000. - * - * maxcvsr = 125 - * 1. cpsdvsr = 2, scr = 61 -> DONE - * - * This would correspond to an actual frequency of: - * 50,000,000 / (2 * (62)) = 403,226 - * - * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000. - * - * maxcvsr = 2 - * 1. cpsdvsr = 2, scr = 0 -> DONE - * - * This would correspond to an actual frequency of: - * 50,000,000 / (2 * (1)) = 25,000,000 - */ - - maxdvsr = SYSCLK_FREQUENCY / frequency; - cpsdvsr = 0; - do - { - cpsdvsr += 2; - scr = (maxdvsr / cpsdvsr) - 1; - } - while (scr > 255); - - /* Set CPDVSR */ - - DEBUGASSERT(cpsdvsr < 255); - ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); - - /* Set SCR */ - - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~SSI_CR0_SCR_MASK; - regval |= (scr << SSI_CR0_SCR_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); - - /* Calcluate the actual frequency */ - - actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1)); - - /* Save the frequency selection so that subsequent reconfigurations will be - * faster. - */ - -#ifndef CONFIG_SPI_OWNBUS - priv->frequency = frequency; - priv->actual = actual; - } - return priv->actual; -#else - return actual; -#endif -} - -static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - uint32_t actual; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - actual = ssi_setfrequencyinternal(priv, frequency); - ssi_enable(priv, enable); - return actual; -} - -/**************************************************************************** - * Name: ssi_setmode - * - * Description: - * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * none - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode) -{ - uint32_t modebits; - uint32_t regval; - - ssidbg("mode: %d\n", mode); - DEBUGASSERT(priv); - - /* Has the number of bits per word changed? */ - -#ifndef CONFIG_SPI_OWNBUS - if (mode != priv->mode) - { -#endif - /* Select the CTL register bits based on the selected mode */ - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ - modebits = 0; - break; - - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ - modebits = SSI_CR0_SPH; - break; - - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ - modebits = SSI_CR0_SPO; - break; - - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ - modebits = SSI_CR0_SPH|SSI_CR0_SPO; - break; - - default: - return; - } - - /* Then set the selected mode: Freescale SPI format, mode0-3 */ - - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); - regval |= modebits; - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x\n", regval); - - /* Save the mode so that subsequent re-configuratins will be faster */ - -#ifndef CONFIG_SPI_OWNBUS - priv->mode = mode; - } -#endif -} - -static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - ssi_setmodeinternal(priv, mode); - ssi_enable(priv, enable); -} - -/**************************************************************************** - * Name: ssi_setbits - * - * Description: - * Set the number if bits per word. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requests - * - * Returned Value: - * none - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits) -{ - uint32_t regval; - - ssidbg("nbits: %d\n", nbits); - DEBUGASSERT(priv); - if (nbits != priv->nbits && nbits >=4 && nbits <= 16) - { - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~SSI_CR0_DSS_MASK; - regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x\n", regval); - - priv->nbits = nbits; - } -} - -static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - ssi_setbitsinternal(priv, nbits); - ssi_enable(priv, enable); -} - -/**************************************************************************** - * Name: ssi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev; - uint16_t response = 0; - - (void)ssi_transfer(priv, &wd, &response, 1); - return response; -} - -/**************************************************************************** - * Name: SPI_EXCHANGE - * - * Description: - * Exahange a block of data from SPI. Required. - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_EXCHANGE -static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords); -} -#endif - -/************************************************************************* - * Name: ssi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, buffer, NULL, nwords); -} -#endif - -/**************************************************************************** - * Name: ssi_recvblock - * - * Description: - * Revice a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, NULL, buffer, nwords); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_spiinitialize - * - * Description: - * Initialize common parts the selected SPI port. Initialization of - * chip select GPIOs must have been performed by board specific logic - * prior to calling this function. Specifically: GPIOs should have - * been configured for output, and all chip selects disabled. - * - * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, - * If multiple devices on on the bus, then multiple chip selects will be - * required. Theregore, all GPIO chip management is deferred to board- - * specific logic. - * - * Input Parameter: - * Port number (for hardware that has mutiple SSI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *up_spiinitialize(int port) -{ - struct lm3s_ssidev_s *priv; - irqstate_t flags; - uint8_t regval; - - ssidbg("port: %d\n", port); - - /* Set up for the selected port */ - - flags = irqsave(); - switch (port) - { -#ifndef CONFIG_SSI0_DISABLE - case 0: - /* Select SSI0 */ - - priv = &g_ssidev[SSI0_NDX]; - - /* Enable the SSI0 peripheral */ - - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_SSI0; - putreg32(regval, LM3S_SYSCON_RCGC1); - ssivdbg("RCGC1: %08x\n", regval); - - /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the - * logic in this file makes no assumptions about chip select) - */ - - lm3s_configgpio(GPIO_SSI0_CLK); /* PA2: SSI0 clock (SSI0Clk) */ - /* lm3s_configgpio(GPIO_SSI0_FSS); PA3: SSI0 frame (SSI0Fss) */ - lm3s_configgpio(GPIO_SSI0_RX); /* PA4: SSI0 receive (SSI0Rx) */ - lm3s_configgpio(GPIO_SSI0_TX); /* PA5: SSI0 transmit (SSI0Tx) */ - break; -#endif /* CONFIG_SSI0_DISABLE */ - -#ifndef CONFIG_SSI1_DISABLE - case 1: - /* Select SSI0 */ - - priv = &g_ssidev[SSI1_NDX]; - - /* Enable the SSI1 peripheral */ - - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_SSI1; - putreg32(regval, LM3S_SYSCON_RCGC1); - ssivdbg("RCGC1: %08x\n", regval); - - /* Configure SSI1 GPIOs */ - - lm3s_configgpio(GPIO_SSI1_CLK); /* PE0: SSI1 clock (SSI1Clk) */ - /* lm3s_configgpio(GPIO_SSI1_FSS); PE1: SSI1 frame (SSI1Fss) */ - lm3s_configgpio(GPIO_SSI1_RX); /* PE2: SSI1 receive (SSI1Rx) */ - lm3s_configgpio(GPIO_SSI1_TX); /* PE3: SSI1 transmit (SSI1Tx) */ - break; -#endif /* CONFIG_SSI1_DISABLE */ - - default: - irqrestore(flags); - return NULL; - } - - /* Initialize the state structure */ - -#ifndef CONFIG_SSI_POLLWAIT - sem_init(&priv->xfrsem, 0, 0); -#endif -#ifndef CONFIG_SPI_OWNBUS - sem_init(&priv->exclsem, 0, 1); -#endif - - /* Set all CR1 fields to reset state. This will be master mode. */ - - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); - - /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ - - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); - - /* Set the initial mode to mode 0. The application may override - * this initial setting using the setmode() method. - */ - - ssi_setmodeinternal(priv, SPIDEV_MODE0); - - /* Set the initial data width to 8-bits. The application may - * override this initial setting using the setbits() method. - */ - - ssi_setbitsinternal(priv, 8); - - /* Pick some initialize clock frequency. 400,000Hz is the startup - * MMC/SD frequency used for card detection. The application may - * override this setting using the setfrequency() method. - */ - - ssi_setfrequencyinternal(priv, 400000); - - /* Disable all SSI interrupt sources. They will be enabled only - * while there is an SSI transfer in progress. - */ - - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); - - /* Attach the interrupt */ - -#ifndef CONFIG_SSI_POLLWAIT -#if NSSI_ENABLED > 1 - irq_attach(priv->irq, (xcpt_t)ssi_interrupt); -#else - irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); -#endif -#endif /* CONFIG_SSI_POLLWAIT */ - - /* Enable the SSI for operation */ - - ssi_enable(priv, SSI_CR1_SSE); - - /* Enable SSI interrupts (They are still disabled at the source). */ - -#ifndef CONFIG_SSI_POLLWAIT -#if NSSI_ENABLED > 1 - up_enable_irq(priv->irq); -#else - up_enable_irq(SSI_IRQ); -#endif -#endif /* CONFIG_SSI_POLLWAIT */ - - irqrestore(flags); - return (FAR struct spi_dev_s *)priv; -} - -#endif /* NSSI_ENABLED > 0 */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c deleted file mode 100644 index 341b82e50..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_start.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_start.c - * arch/arm/src/chip/lm3s_start.c - * - * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "lm_lowputc.h" -#include "lm_syscontrol.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -extern void lm3s_vectors(void); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: showprogress - * - * Description: - * Print a character on the UART to show boot status. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG -# define showprogress(c) up_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: _start - * - * Description: - * This is the reset entry point. - * - ****************************************************************************/ - -void __start(void) -{ - const uint32_t *src; - uint32_t *dest; - - /* Configure the uart so that we can get debug output as soon as possible */ - - up_clockconfig(); - up_lowsetup(); - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (dest = &_sbss; dest < &_ebss; ) - { - *dest++ = 0; - } - showprogress('B'); - - /* Move the intialized data section from his temporary holding spot in - * FLASH into the correct place in SRAM. The correct place in SRAM is - * give by _sdata and _edata. The temporary location is in FLASH at the - * end of all of the other read-only data (.text, .rodata) at _eronly. - */ - - for (src = &_eronly, dest = &_sdata; dest < &_edata; ) - { - *dest++ = *src++; - } - showprogress('C'); - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - up_earlyserialinit(); -#endif - showprogress('D'); - - /* Initialize onboard resources */ - - lm3s_boardinitialize(); - showprogress('E'); - - /* Then start NuttX */ - - showprogress('\r'); - showprogress('\n'); - os_start(); - - /* Shoulnd't get here */ - - for(;;); -} diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c deleted file mode 100644 index 3ad0cacb5..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c +++ /dev/null @@ -1,315 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_syscontrol.c - * arch/arm/src/chip/lm3s_syscontrol.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "chip.h" -#include "lm_syscontrol.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RCC_OSCMASK (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) -#define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN) -#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2) -#define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) -#define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK) -#define FAST_OSCDELAY (512*1024) -#define SLOW_OSCDELAY (4*1024) -#define PLLLOCK_DELAY (32*1024) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_delay - * - * Description: - * Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - * - ****************************************************************************/ - -static inline void lm3s_delay(uint32_t delay) -{ - __asm__ __volatile__("1:\n" - "\tsubs %0, #1\n" - "\tbne 1b\n" - : "=r"(delay) : "r"(delay)); -} - -/**************************************************************************** - * Name: lm3s_oscdelay - * - * Description: - * Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - * - ****************************************************************************/ - -static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2) -{ - /* Wait for the oscillator to stabilize. A smaller delay is used if the - * current clock rate is very slow. - */ - - uint32_t delay = FAST_OSCDELAY; - - /* Are we currently using RCC2? */ - - if ((rcc2 & SYSCON_RCC2_USERCC2) != 0) - { - uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK; - if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) || - (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ)) - { - delay = SLOW_OSCDELAY; - } - } - - /* No.. using srce in RCC */ - - else - { - uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK; - if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ) - { - delay = SLOW_OSCDELAY; - } - } - - /* Then delay that number of loops */ - - lm3s_delay(delay); -} - -/**************************************************************************** - * Name: lm3s_plllock - * - * Description: - * The new RCC values have been selected... wait for the PLL to lock on - * - ****************************************************************************/ - -static inline void lm3s_plllock(void) -{ - volatile uint32_t delay; - - /* Loop until the lock is achieved or until a timeout occurs */ - - for (delay = PLLLOCK_DELAY; delay > 0; delay--) - { - /* Check if the PLL is locked on */ - - if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) - { - /* Yes.. return now */ - - return; - } - } - - /* If we get here, then PLL lock was not achieved */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_clockconfig - * - * Description: - * Called to change to new clock based on desired rcc and rcc2 settings. - * This is use to set up the initial clocking but can be used later to - * support slow clocked, low power consumption modes. - * - ****************************************************************************/ - -void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2) -{ - uint32_t rcc; - uint32_t rcc2; - - /* Get the current values of the RCC and RCC2 registers */ - - rcc = getreg32(LM3S_SYSCON_RCC); - rcc2 = getreg32(LM3S_SYSCON_RCC2); - - /* Temporarily bypass the PLL and system clock dividers */ - - rcc |= SYSCON_RCC_BYPASS; - rcc &= ~(SYSCON_RCC_USESYSDIV); - putreg32(rcc, LM3S_SYSCON_RCC); - - rcc2 |= SYSCON_RCC2_BYPASS2; - putreg32(rcc2, LM3S_SYSCON_RCC2); - - /* We are probably using the main oscillator. The main oscillator is disabled on - * reset and so probably must be enabled here. The internal oscillator is enabled - * on rest and if that is selected, most likely nothing needs to be done. - */ - - if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) || - ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS))) - { - /* Enable any selected osciallators (but don't disable any yet) */ - - rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); - putreg32(rcc, LM3S_SYSCON_RCC); - - /* Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - */ - - lm3s_oscdelay(rcc, rcc2); - } - - /* Set the new crystal value, oscillator source and PLL configuration */ - - rcc &= ~RCC_XTALMASK; - rcc |= newrcc & RCC_XTALMASK; - - rcc2 &= ~RCC2_XTALMASK; - rcc2 |= newrcc2 & RCC2_XTALMASK; - - /* Clear the PLL lock interrupt */ - - putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); - - /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC - * is currently enabled. - */ - - if (rcc2 & SYSCON_RCC2_USERCC2) - { - putreg32(rcc2, LM3S_SYSCON_RCC2); - putreg32(rcc, LM3S_SYSCON_RCC); - } - else - { - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); - } - - /* Wait for the new crystal value and oscillator source to take effect */ - - lm3s_delay(16); - - /* Set the requested system divider and disable the non-selected osciallators */ - - rcc &= ~RCC_DIVMASK; - rcc |= newrcc & RCC_DIVMASK; - - rcc2 &= ~RCC2_DIVMASK; - rcc2 |= newrcc2 & RCC2_DIVMASK; - - /* Will the PLL output be used to clock the system? */ - - if ((newrcc & SYSCON_RCC_BYPASS) == 0) - { - /* Yes, wail untill the PLL is locked */ - - lm3s_plllock(); - - /* Then enable the PLL */ - - rcc &= ~SYSCON_RCC_BYPASS; - rcc2 &= ~SYSCON_RCC2_BYPASS2; - } - - /* Now we can set the final RCC/RCC2 values */ - - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); - - /* Wait for the system divider to be effective */ - - lm3s_delay(6); -} - -/**************************************************************************** - * Name: up_clockconfig - * - * Description: - * Called early in the bootsequence (before .data and .bss are available) - * in order to configure initial clocking. - * - ****************************************************************************/ - -void up_clockconfig(void) -{ -#ifdef CONFIG_LM3S_REVA2 - /* Some early silicon returned an increase LDO voltage or 2.75V to work - * around a PLL bug - */ - - putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); -#endif - - /* Set the clocking to run with the default settings provided in the board.h - * header file - */ - - lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); -} - diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c deleted file mode 100644 index 9cd912249..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm3s/lm3s_timerisr.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "nvic.h" -#include "clock_internal.h" -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h - * header file. - */ - -#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify taht the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -int up_timerisr(int irq, uint32_t *regs) -{ - /* Process timer interrupt */ - - sched_process_timer(); - return 0; -} - -/**************************************************************************** - * Function: up_timerinit - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timerinit(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(LM3S_IRQ_SYSTICK); -} diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S deleted file mode 100644 index 71db122a0..000000000 --- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S +++ /dev/null @@ -1,805 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_vectors.S - * arch/arm/src/chip/lm3s_vectors.S - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/* Memory Map: - * - * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader) - * 0x0002:0000 - Address of vectors if using bootloader - * 0x0003:ffff - End of flash - * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) - * - End of .bss (_ebss) and bottom of idle stack - * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap - * 0x2000:ffff - End of SRAM and end of heap - */ - -#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) -#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) - -/* The Cortex-M3 return from interrupt is unusual. We provide the following special - * address to the BX instruction. The particular value also forces a return to - * thread mode and covers state from the main stack point, the MSP (vs. the MSP). - */ - -#define EXC_RETURN 0xfffffff9 - -/************************************************************************************ - * Global Symbols - ************************************************************************************/ - - .globl __start - - .syntax unified - .thumb - .file "lm3s_vectors.S" - -/************************************************************************************ - * Macros - ************************************************************************************/ - -/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 - * registers on the stack, then branches to an instantantiation of the following - * macro. This macro simply loads the IRQ number into R0, then jumps to the common - * IRQ handling logic. - */ - - .macro HANDLER, label, irqno - .thumb_func -\label: - mov r0, #\irqno - b lm3s_irqcommon - .endm - -/************************************************************************************ - * Vectors - ************************************************************************************/ - - .section .vectors, "ax" - .code 16 - .align 2 - .globl lm3s_vectors - .type lm3s_vectors, function - -lm3s_vectors: - -/* Processor Exceptions */ - - .word IDLE_STACK /* Vector 0: Reset stack pointer */ - .word __start /* Vector 1: Reset vector */ - .word lm3s_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */ - .word lm3s_hardfault /* Vector 3: Hard fault */ - .word lm3s_mpu /* Vector 4: Memory management (MPU) */ - .word lm3s_busfault /* Vector 5: Bus fault */ - .word lm3s_usagefault /* Vector 6: Usage fault */ - .word lm3s_reserved /* Vector 7: Reserved */ - .word lm3s_reserved /* Vector 8: Reserved */ - .word lm3s_reserved /* Vector 9: Reserved */ - .word lm3s_reserved /* Vector 10: Reserved */ - .word lm3s_svcall /* Vector 11: SVC call */ - .word lm3s_dbgmonitor /* Vector 12: Debug monitor */ - .word lm3s_reserved /* Vector 13: Reserved */ - .word lm3s_pendsv /* Vector 14: Pendable system service request */ - .word lm3s_systick /* Vector 15: System tick */ - -/* External Interrupts */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_reserved /* Vector 25: Reserved */ - .word lm3s_reserved /* Vector 26: Reserved */ - .word lm3s_reserved /* Vector 27: Reserved */ - .word lm3s_reserved /* Vector 28: Reserved */ - .word lm3s_reserved /* Vector 29: Reserved */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_gpioh /* Vector 48: GPIO Port H */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_ssi1 /* Vector 50: SSI 1 */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_reserved /* Vector 54: Reserved */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_reserved /* Vector 25: Reserved */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_reserved /* Vector 27: Reserved */ - .word lm3s_reserved /* Vector 28: Reserved */ - .word lm3s_reserved /* Vector 29: Reserved */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_reserved /* Vector 51: Reserved */ - .word lm3s_reserved /* Vector 52: Reserved */ - .word lm3s_reserved /* Vector 53: Reserved */ - .word lm3s_reserved /* Vector 54: Reserved */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_reserved /* Vector 59: Reserved */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_uart2 /* Vector 49: UART 2 */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_cmp2 /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_gpioh /* Vector 48: GPIO Port H */ - .word lm3s_uart2 /* Vector 49: UART 2 */ - .word lm3s_ssi1 /* Vector 50: SSI 1 */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_can0 /* Vector 55: CAN 0 */ - .word lm3s_can1 /* Vector 56: CAN 1 */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_reserved /* Vector 59: Reserved */ - .word lm3s_usb /* Vector 60: USB */ - .word lm3s_pwm3 /* Vector 61: PWM 3 */ - .word lm3s_udmasoft /* Vector 62: uDMA Software */ - .word lm3s_udmaerror /* Vector 63: uDMA Error */ - .word lm3s_adc1_0 /* Vector 64: ADC1 Sequence 0 */ - .word lm3s_adc1_1 /* Vector 65: ADC1 Sequence 1 */ - .word lm3s_adc1_2 /* Vector 66: ADC1 Sequence 2 */ - .word lm3s_adc1_3 /* Vector 67: ADC1 Sequence 3 */ - .word lm3s_i2s0 /* Vector 68: I2S 0 */ - .word lm3s_epi /* Vector 69: Reserved */ - .word lm3s_gpioj /* Vector 70: GPIO J */ - .word lm3s_reserved /* Vector 71: Reserved */ - #elif defined(CONFIG_ARCH_CHIP_LM3S8962) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_reserved /* Vector 42: Reserved */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_reserved /* Vector 53: Reserved*/ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_can0 /* Vector 55: Can Controller */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#else -# error "Vectors not specified for this LM3S chip" -#endif - .size lm3s_vectors, .-lm3s_vectors - -/************************************************************************************ - * .text - ************************************************************************************/ - - .text - .type handlers, function - .thumb_func -handlers: - HANDLER lm3s_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ - HANDLER lm3s_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ - HANDLER lm3s_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ - HANDLER lm3s_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ - HANDLER lm3s_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ - HANDLER lm3s_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ - HANDLER lm3s_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ - HANDLER lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ - HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ - HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm3s_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ - HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm3s_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_usb, LM3S_IRQ_USB /* Vector 60: USB */ - HANDLER lm3s_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ - HANDLER lm3s_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ - HANDLER lm3s_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ - HANDLER lm3s_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ - HANDLER lm3s_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ - HANDLER lm3s_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ - HANDLER lm3s_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ - HANDLER lm3s_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ - HANDLER lm3s_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ - HANDLER lm3s_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ -#else -# error "Vectors not specified for this LM3S chip" -#endif - -/* Common IRQ handling logic. On entry here, the return stack is on either - * the PSP or the MSP and looks like the following: - * - * REG_XPSR - * REG_R15 - * REG_R14 - * REG_R12 - * REG_R3 - * REG_R2 - * REG_R1 - * MSP->REG_R0 - * - * And - * R0 contains the IRQ number - * R14 Contains the EXC_RETURN value - * We are in handler mode and the current SP is the MSP - */ - -lm3s_irqcommon: - - /* Complete the context save */ - -#ifdef CONFIG_NUTTX_KERNEL - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the state is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ - ite ne /* Next two instructions are condition */ - mrsne r1, msp /* R1=The main stack pointer */ - mrseq r1, psp /* R1=The process stack pointer */ -#else - mrs r1, msp /* R1=The main stack pointer */ -#endif - - mov r2, r1 /* R2=Copy of the main/process stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ - mrs r3, primask /* R3=Current PRIMASK setting */ -#ifdef CONFIG_NUTTX_KERNEL - stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ -#else - stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ -#endif - - /* Disable interrupts, select the stack to use for interrupt handling - * and call up_doirq to handle the interrupt - */ - - cpsid i /* Disable further interrupts */ - - /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt - * stack pointer. The way that this is done here prohibits nested interrupts! - * Otherwise, we will re-use the main stack for interrupt level processing. - */ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - ldr sp, =g_intstackbase - str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ -#else - mov sp, r1 /* We are using the main stack pointer */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - mov r1, sp /* Recover R1=main stack pointer */ -#endif - - /* On return from up_doirq, R0 will hold a pointer to register context - * array to use for the interrupt return. If that return value is the same - * as current stack pointer, then things are relatively easy. - */ - - cmp r0, r1 /* Context switch? */ - beq 1f /* Branch if no context switch */ - - /* We are returning with a pending context switch. This case is different - * because in this case, the register save structure does not lie on the - * stack but, rather, are within a TCB structure. We'll have to copy some - * values to the stack. - */ - - add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ - ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ - ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ - stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ -#ifdef CONFIG_NUTTX_KERNEL - ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif - b 2f /* Re-join common logic */ - - /* We are returning with no context switch. We simply need to "unwind" - * the same stack frame that we created - */ -1: -#ifdef CONFIG_NUTTX_KERNEL - ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif -2: -#ifdef CONFIG_NUTTX_KERNEL - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the state is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ - ite ne /* Next two instructions are condition */ - msrne msp, r1 /* R1=The main stack pointer */ - msreq psp, r1 /* R1=The process stack pointer */ -#else - msr msp, r1 /* Recover the return MSP value */ - - /* Preload r14 with the special return value first (so that the return - * actually occurs with interrupts still disabled). - */ - - ldr r14, =EXC_RETURN /* Load the special value */ -#endif - - /* Restore the interrupt state */ - - msr primask, r3 /* Restore interrupts */ - - /* Always return with R14 containing the special value that will: (1) - * return to thread mode, and (2) continue to use the MSP - */ - - bx r14 /* And return */ - .size handlers, .-handlers - -/************************************************************************************ - * Name: up_interruptstack/g_intstackbase - * - * Description: - * Shouldn't happen - * - ************************************************************************************/ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - .bss - .global g_intstackbase - .align 4 -up_interruptstack: - .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) -g_intstackbase: - .size up_interruptstack, .-up_interruptstack -#endif - -/************************************************************************************ - * .rodata - ************************************************************************************/ - - .section .rodata, "a" - -/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end - * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS - * and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that - * the system boots on and, eventually, becomes the idle, do nothing task that runs - * only when there is nothing else to run. The heap continues from there until the - * end of memory. See g_heapbase below. - */ - - .globl g_heapbase - .type g_heapbase, object -g_heapbase: - .long _ebss+CONFIG_IDLETHREAD_STACKSIZE - .size g_heapbase, .-g_heapbase - - .end diff --git a/nuttx/arch/arm/src/lm3s/lm_ethernet.h b/nuttx/arch/arm/src/lm3s/lm_ethernet.h deleted file mode 100644 index 600955b95..000000000 --- a/nuttx/arch/arm/src/lm3s/lm_ethernet.h +++ /dev/null @@ -1,103 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm_ethernet.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H -#define __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -#if LM3S_NETHCONTROLLERS > 1 - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface. If the LM3S chip - * supports multiple Ethernet controllers, then bould specific logic - * must implement up_netinitialize() and call this function to initialize - * the desiresed interfaces. - * - * Parameters: - * None - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -int lm3s_ethinitialize(int intf); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* LM3S_NETHCONTROLLERS > 1 */ -#endif /* __ARCH_ARM_SRC_LM3S_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_gpio.h b/nuttx/arch/arm/src/lm3s/lm_gpio.h deleted file mode 100644 index 1bfb79fc9..000000000 --- a/nuttx/arch/arm/src/lm3s/lm_gpio.h +++ /dev/null @@ -1,223 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm_gpio.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM_GPIO_H -#define __ARCH_ARM_SRC_LM3S_LM_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include -#include - -#include "up_internal.h" -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Bit-encoded input to lm3s_configgpio() *******************************************/ - -/* Encoding: - * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB - * - * These bits set the primary function of the pin: - * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */ -#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */ -#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */ -#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */ -#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */ -#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */ -#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */ -#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */ -#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */ -#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */ -#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */ -#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */ -#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT - -/* That primary may be modified by the following options - * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */ -#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT) -#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */ -#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */ -#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */ -#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */ -#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC - -#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */ -#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) -#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */ -#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */ -#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */ -#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */ -#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */ -#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */ -#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */ - -/* If the pin is an interrupt, then the following options apply - * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn - */ - -#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */ -#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT) -#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */ -#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */ -#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */ -#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ -#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ - -/* If the pin is an GPIO digital output, then this identifies the initial output value: - * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn - */ - -#define GPIO_VALUE_SHIFT 7 /* Bit 7: If output, inital value of output */ -#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) -#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ -#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ - -/* This identifies the GPIO port - * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn - */ - -#define GPIO_PORT_SHIFT 3 /* Bit 3-6: Port number */ -#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ -#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ -#define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */ - -/* This identifies the bit in the port: - * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB - */ - -#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */ -#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -int lm3s_configgpio(uint32_t cfgset); - -/**************************************************************************** - * Name: lm3s_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void lm3s_gpiowrite(uint32_t pinset, bool value); - -/**************************************************************************** - * Name: lm3s_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool lm3s_gpioread(uint32_t pinset, bool value); - -/**************************************************************************** - * Function: lm3s_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -int lm3s_dumpgpio(uint32_t pinset, const char *msg); - -/**************************************************************************** - * Name: gpio_irqinitialize - * - * Description: - * Initialize all vectors to the unexpected interrupt handler - * - ****************************************************************************/ - -int weak_function gpio_irqinitialize(void); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LM3S_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_lowputc.h b/nuttx/arch/arm/src/lm3s/lm_lowputc.h deleted file mode 100644 index 8e2858ebf..000000000 --- a/nuttx/arch/arm/src/lm3s/lm_lowputc.h +++ /dev/null @@ -1,87 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_lowputc.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H -#define __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: up_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level initialization. - * - ****************************************************************************/ - -void up_lowsetup(void); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LM3S_LM_LOWPUTC_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_ssi.h b/nuttx/arch/arm/src/lm3s/lm_ssi.h deleted file mode 100644 index dd1e30817..000000000 --- a/nuttx/arch/arm/src/lm3s/lm_ssi.h +++ /dev/null @@ -1,114 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm_ssi.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM_SSI_H -#define __ARCH_ARM_SRC_LM3S_LM_SSI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * The external functions, lm3s_spiselect, lm3s_spistatus, and - * lm3s_spicmddata must be provided by board-specific logic. These are - * implementations of the select, status, and cmddata methods of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi.h). - * All other methods (including up_spiinitialize()) are provided by common - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide - * the lm3s_spicmddata() function in your board-specific logic. This - * functions will perform cmd/data selection operations using GPIOs in - * the way your board is configured. - * 4. Add a call to up_spiinitialize() in your low level application - * initialization logic - * 5. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -struct spi_dev_s; -enum spi_dev_e; -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LM3S_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm_syscontrol.h deleted file mode 100644 index 7c49da565..000000000 --- a/nuttx/arch/arm/src/lm3s/lm_syscontrol.h +++ /dev/null @@ -1,100 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm3s/lm3s_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_clockconfig - * - * Description: - * Called to change to new clock based on desired rcc and rcc2 settings. - * This is use to set up the initial clocking but can be used later to - * support slow clocked, low power consumption modes. - * - ****************************************************************************/ - -void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); - -/**************************************************************************** - * Name: up_clockconfig - * - * Description: - * Called early in the bootsequence (before .data and .bss are available) - * in order to configure initial clocking. - * - ****************************************************************************/ - -void up_clockconfig(void); - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LM3S_LM_SYSCONTROL_H */ diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt index a79ac2b2d..3f9da652b 100644 --- a/nuttx/configs/eagle100/README.txt +++ b/nuttx/configs/eagle100/README.txt @@ -273,7 +273,7 @@ Eagle100-specific Configuration Options CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - CONFIG_ARCH_CHIP=lm3s + CONFIG_ARCH_CHIP=lm CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: @@ -371,7 +371,7 @@ Eagle100-specific Configuration Options to build the LM3S Ethernet driver CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide - a MAC address (via lm3s_ethernetmac()), then this should be selected. + a MAC address (via lm_ethernetmac()), then this should be selected. CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig index c2ea86bed..cf4f97930 100644 --- a/nuttx/configs/eagle100/httpd/defconfig +++ b/nuttx/configs/eagle100/httpd/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig index 2dab94846..a3b50ead6 100644 --- a/nuttx/configs/eagle100/nettest/defconfig +++ b/nuttx/configs/eagle100/nettest/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig index fd141bc80..342023d6a 100644 --- a/nuttx/configs/eagle100/nsh/defconfig +++ b/nuttx/configs/eagle100/nsh/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig index 20cd50432..fe02ab4b9 100644 --- a/nuttx/configs/eagle100/nxflat/defconfig +++ b/nuttx/configs/eagle100/nxflat/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig index 01f3be334..52496c4a3 100644 --- a/nuttx/configs/eagle100/ostest/defconfig +++ b/nuttx/configs/eagle100/ostest/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig index 460bd64b3..7efbbed11 100644 --- a/nuttx/configs/eagle100/thttpd/defconfig +++ b/nuttx/configs/eagle100/thttpd/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6918=y CONFIG_ARCH_BOARD="eagle100" diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt index d331c1cd5..f7896118e 100644 --- a/nuttx/configs/ekk-lm3s9b96/README.txt +++ b/nuttx/configs/ekk-lm3s9b96/README.txt @@ -173,13 +173,13 @@ IDEs 2) Start the NuttX build at least one time from the Cygwin command line before trying to create your project. This is necessary to create certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm3s, + 3) Set up include pathes: You will need include/, arch/arm/src/lm, arch/arm/src/common, arch/arm/src/armv7-m, and sched/. 4) All assembly files need to have the definition option -D __ASSEMBLY__ on the command line. Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lm3s/lm3s_vectors.S. + is arch/arm/src/lm/lm_vectors.S. NuttX EABI "buildroot" Toolchain ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -294,7 +294,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - CONFIG_ARCH_CHIP=lm3s + CONFIG_ARCH_CHIP=lm CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: @@ -389,7 +389,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options to build the LM3S Ethernet driver CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide - a MAC address (via lm3s_ethernetmac()), then this should be selected. + a MAC address (via lm_ethernetmac()), then this should be selected. CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig index d8ae63cff..b614c0316 100644 --- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig @@ -39,7 +39,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S9B96=y CONFIG_ARCH_BOARD="ekk-lm3s9b96" diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig index 62a092d1f..df5622360 100644 --- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig @@ -39,7 +39,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S9B96=y CONFIG_ARCH_BOARD="ekk-lm3s9b96" diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h index bb3315f5b..17b0d0e27 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h +++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h @@ -1,6 +1,6 @@ /************************************************************************************ * configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h - * arch/arm/src/board/lm3s6965ek_internal.n + * arch/arm/src/board/lm3s6965ek_internal.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt index 296a10f05..669708c16 100644 --- a/nuttx/configs/lm3s6432-s2e/README.txt +++ b/nuttx/configs/lm3s6432-s2e/README.txt @@ -163,13 +163,13 @@ IDEs 2) Start the NuttX build at least one time from the Cygwin command line before trying to create your project. This is necessary to create certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm3s, + 3) Set up include pathes: You will need include/, arch/arm/src/lm, arch/arm/src/common, arch/arm/src/armv7-m, and sched/. 4) All assembly files need to have the definition option -D __ASSEMBLY__ on the command line. Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lm3s/lm3s_vectors.S. + is arch/arm/src/lm/lm_vectors.S. NuttX EABI "buildroot" Toolchain ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -288,7 +288,7 @@ Stellaris MDL-S2E Reference Design Configuration Options CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - CONFIG_ARCH_CHIP=lm3s + CONFIG_ARCH_CHIP=lm CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig index 7d1657cda..edd61eacc 100644 --- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig +++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6432=y CONFIG_ARCH_BOARD="lm3s6432-s2e" diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig index 90357ce7f..2d32db81c 100644 --- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig +++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S6432=y CONFIG_ARCH_BOARD="lm3s6432-s2e" diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index 09a07ec68..5a9cdbf4e 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -197,13 +197,13 @@ IDEs 2) Start the NuttX build at least one time from the Cygwin command line before trying to create your project. This is necessary to create certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm3s, + 3) Set up include pathes: You will need include/, arch/arm/src/lm, arch/arm/src/common, arch/arm/src/armv7-m, and sched/. 4) All assembly files need to have the definition option -D __ASSEMBLY__ on the command line. Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lm3s/lm3s_vectors.S. + is arch/arm/src/lm/lm_vectors.S. NuttX EABI "buildroot" Toolchain ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -357,7 +357,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - CONFIG_ARCH_CHIP=lm3s + CONFIG_ARCH_CHIP=lm CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: @@ -452,7 +452,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options to build the LM3S Ethernet driver CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide - a MAC address (via lm3s_ethernetmac()), then this should be selected. + a MAC address (via lm_ethernetmac()), then this should be selected. CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 64f4397cb..c1827920b 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -65,6 +65,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX is not set # CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_LPC17XX is not set # CONFIG_ARCH_CHIP_LPC214X is not set @@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index be75c2875..e3cac8dd7 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -65,6 +65,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX is not set # CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_LPC17XX is not set # CONFIG_ARCH_CHIP_LPC214X is not set @@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index 83e89a6ae..81247c795 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -65,6 +65,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX is not set # CONFIG_ARCH_CHIP_KINETIS is not set +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_LPC17XX is not set # CONFIG_ARCH_CHIP_LPC214X is not set @@ -76,7 +77,7 @@ CONFIG_ARCH_CHIP_LM3S=y # CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=4531 diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h index 8ebd4cf65..4cd2eddc7 100644 --- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h +++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h @@ -1,6 +1,6 @@ /************************************************************************************ * configs/lm3s6965-ek/src/lm3s6965ek_internal.h - * arch/arm/src/board/lm3s6965ek_internal.n + * arch/arm/src/board/lm3s6965ek_internal.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt index fdb783466..0f796e38d 100644 --- a/nuttx/configs/lm3s8962-ek/README.txt +++ b/nuttx/configs/lm3s8962-ek/README.txt @@ -181,13 +181,13 @@ IDEs 2) Start the NuttX build at least one time from the Cygwin command line before trying to create your project. This is necessary to create certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm3s, + 3) Set up include pathes: You will need include/, arch/arm/src/lm, arch/arm/src/common, arch/arm/src/armv7-m, and sched/. 4) All assembly files need to have the definition option -D __ASSEMBLY__ on the command line. Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lm3s/lm3s_vectors.S. + is arch/arm/src/lm/lm_vectors.S. NuttX EABI "buildroot" Toolchain ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -341,7 +341,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory - CONFIG_ARCH_CHIP=lm3s + CONFIG_ARCH_CHIP=lm CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: @@ -436,7 +436,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options to build the LM3S Ethernet driver CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide - a MAC address (via lm3s_ethernetmac()), then this should be selected. + a MAC address (via lm_ethernetmac()), then this should be selected. CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig index 79f90d5f9..1d3df2fa7 100755 --- a/nuttx/configs/lm3s8962-ek/nsh/defconfig +++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig index 8424b6623..37fc8903d 100755 --- a/nuttx/configs/lm3s8962-ek/nx/defconfig +++ b/nuttx/configs/lm3s8962-ek/nx/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig index 73fbff29f..731003fd0 100755 --- a/nuttx/configs/lm3s8962-ek/ostest/defconfig +++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig @@ -38,7 +38,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM3=y -CONFIG_ARCH_CHIP="lm3s" +CONFIG_ARCH_CHIP="lm" +CONFIG_ARCH_CHIP_LM=y CONFIG_ARCH_CHIP_LM3S=y CONFIG_ARCH_CHIP_LM3S8962=y CONFIG_ARCH_BOARD="lm3s8962-ek" -- cgit v1.2.3 From 8156a2bed16d732d2489f7d6fe410b110c29b1d5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 9 Jan 2013 12:55:13 +0000 Subject: Use kconfig- prefix to avoid tool name conflicts (from Jose Pablo Carballo) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5496 42af7a65-404d-4744-a932-0658087f49c3 --- misc/tools/README.txt | 61 ++++++++++--- nuttx/Makefile.unix | 6 +- nuttx/Makefile.win | 6 +- nuttx/README.txt | 20 ++--- nuttx/arch/arm/src/lm/Kconfig | 10 +-- nuttx/configs/amber/README.txt | 2 +- nuttx/configs/ea3131/README.txt | 2 +- nuttx/configs/ea3152/README.txt | 4 +- nuttx/configs/ez80f910200kitg/README.txt | 4 +- nuttx/configs/ez80f910200zco/README.txt | 4 +- nuttx/configs/fire-stm32v2/README.txt | 8 +- nuttx/configs/lm3s6965-ek/README.txt | 12 +-- nuttx/configs/mcu123-lpc214x/README.txt | 4 +- nuttx/configs/micropendous3/README.txt | 2 +- nuttx/configs/mirtoo/README.txt | 2 +- nuttx/configs/ntosd-dm320/README.txt | 4 +- nuttx/configs/olimex-lpc1766stk/README.txt | 4 +- nuttx/configs/sim/README.txt | 16 ++-- nuttx/configs/stm3220g-eval/README.txt | 8 +- nuttx/configs/stm3240g-eval/README.txt | 6 +- nuttx/configs/stm32f4discovery/README.txt | 16 ++-- nuttx/configs/teensy/README.txt | 2 +- nuttx/configs/xtrs/README.txt | 2 +- nuttx/configs/z16f2800100zcog/README.txt | 8 +- nuttx/configs/z80sim/README.txt | 2 +- nuttx/configs/z8encore000zco/README.txt | 4 +- nuttx/configs/z8f64200100kit/README.txt | 4 +- nuttx/configs/zp214xpa/README.txt | 8 +- nuttx/include/spawn.h | 137 +++++++++++++++++++++++++++++ nuttx/libc/Kconfig | 28 +++--- nuttx/libc/Makefile | 1 + nuttx/libc/spawn/Make.defs | 46 ++++++++++ nuttx/tools/README.txt | 8 +- nuttx/tools/kconfig.bat | 6 +- 34 files changed, 340 insertions(+), 117 deletions(-) create mode 100644 nuttx/include/spawn.h create mode 100644 nuttx/libc/spawn/Make.defs diff --git a/misc/tools/README.txt b/misc/tools/README.txt index 512d8ebaa..1546c6f39 100644 --- a/misc/tools/README.txt +++ b/misc/tools/README.txt @@ -1,8 +1,18 @@ misc/tools/README.txt ===================== +Contents: + + o genromfs-0.5.2.tar.gz + o kconfig-frontends + - --program-prefix= + - kconfig-frontends-3.3.0-1-libintl.patch + - kconfig-macos.patch + - kconfig-macos.patch + - kconfig-frontends for Windows + genromfs-0.5.2.tar.gz ---------------------- +===================== This is a snapshot of the genromfs tarball taken from http://sourceforge.net/projects/romfs/. This snapshot is provided to @@ -12,34 +22,60 @@ genromfs-0.5.2.tar.gz from the buildroot. kconfig-frontends ------------------ +================= - This is a snapshot of the kconfig-frontends version 3.6.0 tarball taken + This is a snapshot of the kconfig-frontends version 3.7.0 tarball taken from http://ymorin.is-a-geek.org/projects/kconfig-frontends. General build instructions: cd kconfig-frontends - ./configure --program-prefix= + ./configure make make install - If you do not specify --program-prefix= in the configuration, then the - current kconfig-frontends code will add the prefix kconfig- to the generated - tools. + To suppress the nconf and the graphical interfaces which are not used by + NuttX: + + ./configure --disable-gconf --disable-qconf + make + make install - To suppress the graphical interfaces: + To suppress the graphical interfaces, use static libraries, and disable + creation of other utilities: - ./configure --disable-gconf --disable-qconf --program-prefix= + ./configure --disable-shared --enable-static --disable-gconf --disable-qconf --disable-nconf --disable-utils make make install + You may require root privileges to 'make install'. + +--program-prefix= +----------------- + + Beginning somwhere between version 3.3.0 and 3.6.0, the prefix was added + to the kconfig-frontends tools. The default prefix is kconfig-. So, + after 3.3.0, conf becomes kconfig-conf, mconf becomes kconfig-mconf, etc. + All of the NuttX documentation, Makefiles, scripts have been updated to + used this default prefix. + + This introduces an incompatibility with the 3.3.0 version. In the 3.6.0 + timeframe, the configure argument --program-prefix= was added to + eliminated the kconfig- prefix. This, however, caused problems when we + got to the 3.7.0 version which generates a binary called kconfig-diff + (installed at /usr/local/bin). Without the prefix, may conflict with + the standard diff utility (at /bin), depending upon how your PATH + variable is configured. Because of this, we decided to "bite the bullet" + and use the standard prefix at 3.7.0 and later. + + This problem could probably also be avoided using --disable-utils. + kconfig-frontends-3.3.0-1-libintl.patch --------------------------------------- The above build instructions did not work for me under my Cygwin installation with kconfig-frontends-3.3.0. This patch is a awful hack - but will successfully build 'mconf' under Cygwin. + but will successfully build 'kconfig-mconf' under Cygwin. cat kconfig-frontends-3.3.0-1-libintl.patch | patch -p0 cd kconfig-frontends-3.3.0-1 @@ -49,8 +85,7 @@ kconfig-frontends-3.3.0-1-libintl.patch See: http://ymorin.is-a-geek.org/hg/kconfig-frontends/file/tip/docs/known-issues.txt - Update: According to the release notes, version 3.6.0 (and above) - will build on Cygwin with no patches: + Update: Version 3.6.0 (and above) will build on Cygwin with no patches: http://ymorin.is-a-geek.org/download/kconfig-frontends/ @@ -66,7 +101,7 @@ kconfig-macos.patch make install kconfig-frontends for Windows -============================= +----------------------------- From http://tech.groups.yahoo.com/group/nuttx/message/2900: diff --git a/nuttx/Makefile.unix b/nuttx/Makefile.unix index d66c06bd8..47debcccf 100644 --- a/nuttx/Makefile.unix +++ b/nuttx/Makefile.unix @@ -642,13 +642,13 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) # misc/tools/README.txt for additional information. config: - $(Q) APPSDIR=${CONFIG_APPS_DIR} conf Kconfig + $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig oldconfig: - $(Q) APPSDIR=${CONFIG_APPS_DIR} conf --oldconfig Kconfig + $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig menuconfig: - $(Q) APPSDIR=${CONFIG_APPS_DIR} mconf Kconfig + $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig # export # diff --git a/nuttx/Makefile.win b/nuttx/Makefile.win index 803d073b2..5c4404f57 100644 --- a/nuttx/Makefile.win +++ b/nuttx/Makefile.win @@ -651,13 +651,13 @@ configenv: $(Q) set APPSDIR=${CONFIG_APPS_DIR} config: configenv - $(Q) conf Kconfig + $(Q) kconfig-conf Kconfig oldconfig: configenv - $(Q) conf --oldconfig Kconfig + $(Q) kconfig-conf --oldconfig Kconfig menuconfig: configenv - $(Q) mconf Kconfig + $(Q) kconfig-mconf Kconfig # export # diff --git a/nuttx/README.txt b/nuttx/README.txt index 0348f7f30..23d0e1a81 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -243,8 +243,8 @@ additional file to the directory the NuttX application package (APPSDIR)): The appconfig file describes the applications that need to be built in the appliction directory (APPSDIR). Not all configurations have an appconfig file. This file is deprecated and will not be - used with new defconfig files produced with the mconf configuration - tool. + used with new defconfig files produced with the kconfig-mconf + configuration tool. General information about configuring NuttX can be found in: @@ -439,14 +439,14 @@ NuttX Configuration Tool under DOS And of course, after you use the configuration tool you need to restore CONFIG_WINDOWS_NATIVE=y and the correct CONFIG_APPS_DIR. - 2) You can, with some effort, run the the Cygwin mconf tool directly - in the CMD.exe shell. In this case, you do not have to modify the - .config file, but there are other complexities: + 2) You can, with some effort, run the the Cygwin kconfig-mconf tool + directly in the CMD.exe shell. In this case, you do not have to + modify the .config file, but there are other complexities: a. You need to temporarily set the Cgywin directories in the PATH - variable then run mconf manually like: + variable then run kconfig-mconf manually like: - mconf Kconfig + kconfig-mconf Kconfig There is a Windows bacht file at tools/kconfig.bat that automates these steps: @@ -454,9 +454,9 @@ NuttX Configuration Tool under DOS tools/kconfig menuconfig b. There is an issue with accessing DOS environment variables from - the Cygwin mconf running in the CMD.exe shell. The following - change to the top-level Kconfig file seems to work around these - problems: + the Cygwin kconfig-mconf running in the CMD.exe shell. The + following change to the top-level Kconfig file seems to work + around these problems: config APPSDIR string diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig index 74d1712f3..2d2504c7e 100644 --- a/nuttx/arch/arm/src/lm/Kconfig +++ b/nuttx/arch/arm/src/lm/Kconfig @@ -60,7 +60,7 @@ config LM3S_DFU bool "DFU" default y -menu "Select LM3S Peripheral Support" +menu "Stellaris Peripheral Support" config LM3S_UART0 bool "UART0" @@ -86,10 +86,10 @@ config LM3S_UART2 default n config LM3S_ETHERNET - bool "LM3S Ethernet" + bool "Stellaris Ethernet" default n ---help--- - This must be set (along with NET) to build the LM3S Ethernet driver. + This must be set (along with NET) to build the Stellaris Ethernet driver. endmenu @@ -134,7 +134,7 @@ config LM3S_DISABLE_GPIOJ_IRQS endmenu if LM3S_ETHERNET -menu "LM3S Ethernet Configuration" +menu "Stellaris Ethernet Configuration" config LM3S_ETHLEDS bool "Ethernet LEDs" @@ -199,7 +199,7 @@ endmenu endif if !SSI0_DISABLE || !SSI1_DISABLE -menu "LM3S SSI Configuration" +menu "Stellaris SSI Configuration" config SSI_POLLWAIT bool "Poll Wait (No-Interrupt) Mode" diff --git a/nuttx/configs/amber/README.txt b/nuttx/configs/amber/README.txt index 56e31ba7f..9f40dcdd2 100644 --- a/nuttx/configs/amber/README.txt +++ b/nuttx/configs/amber/README.txt @@ -187,7 +187,7 @@ Atmel AVRISP mkII Connection Toolchains ^^^^^^^^^^ -The toolchain may be selected using the mconf tool (via 'make menuconfig'), +The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'), by editing the existing configuration file (defconfig), or by overriding the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=. diff --git a/nuttx/configs/ea3131/README.txt b/nuttx/configs/ea3131/README.txt index fcfc0792f..986b7778c 100644 --- a/nuttx/configs/ea3131/README.txt +++ b/nuttx/configs/ea3131/README.txt @@ -53,7 +53,7 @@ GNU Toolchain Options If you are not using CONFIG_LPC31_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. - The toolchain may also be set using the mconf utility (make menuconfig) or by + The toolchain may also be set using the kconfig-mconf utility (make menuconfig) or by passing CONFIG_ARM_TOOLCHAIN= to make, where is one of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described above. diff --git a/nuttx/configs/ea3152/README.txt b/nuttx/configs/ea3152/README.txt index da57945bd..4f507e7b0 100644 --- a/nuttx/configs/ea3152/README.txt +++ b/nuttx/configs/ea3152/README.txt @@ -52,8 +52,8 @@ GNU Toolchain Options If you are not using CONFIG_LPC31_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. - The toolchain may also be set using the mconf utility (make menuconfig) or by - passing CONFIG_ARM_TOOLCHAIN= to make, where is one + The toolchain may also be set using the kconfig-mconf utility (make menuconfig) + or by passing CONFIG_ARM_TOOLCHAIN= to make, where is one of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described above. diff --git a/nuttx/configs/ez80f910200kitg/README.txt b/nuttx/configs/ez80f910200kitg/README.txt index e314b0fe1..8d9086b4e 100644 --- a/nuttx/configs/ez80f910200kitg/README.txt +++ b/nuttx/configs/ez80f910200kitg/README.txt @@ -88,8 +88,8 @@ available: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/ez80f910200zco/README.txt b/nuttx/configs/ez80f910200zco/README.txt index 1bc9e56b8..7df503217 100644 --- a/nuttx/configs/ez80f910200zco/README.txt +++ b/nuttx/configs/ez80f910200zco/README.txt @@ -102,8 +102,8 @@ ostest 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/fire-stm32v2/README.txt b/nuttx/configs/fire-stm32v2/README.txt index 88b5bf583..d12a9b27d 100644 --- a/nuttx/configs/fire-stm32v2/README.txt +++ b/nuttx/configs/fire-stm32v2/README.txt @@ -826,9 +826,9 @@ Where is one of the following: contains support for some built-in applications that can be enabled by making some additional minor change to the configuration file. - Reconfiguring: This configuration uses to the mconf configuration tool to control - the configuration. See the section entitled "NuttX Configuration Tool" - in the top-level README.txt file. + Reconfiguring: This configuration uses to the kconfig-mconf configuration tool + to control the configuration. See the section entitled "NuttX Configuration + Tool" in the top-level README.txt file. Start Delays: If no SD card is present in the slot, or if the network is not connected, then there will be long start-up delays before you get the NSH @@ -842,7 +842,7 @@ Where is one of the following: verified. The ENC28J60 network is not yet functional. Networking is enabled by default in this configuration for testing purposes. To use this configuration, the network must currently be disabled. To do this using - the mconf configuration tool: + the kconfig-mconf configuration tool: > make menuconfig diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index 5a9cdbf4e..e0349f5de 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -482,8 +482,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -512,8 +512,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -532,8 +532,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/mcu123-lpc214x/README.txt b/nuttx/configs/mcu123-lpc214x/README.txt index 4c7c608b7..1c6c9bde8 100644 --- a/nuttx/configs/mcu123-lpc214x/README.txt +++ b/nuttx/configs/mcu123-lpc214x/README.txt @@ -354,8 +354,8 @@ nsh: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/micropendous3/README.txt b/nuttx/configs/micropendous3/README.txt index 1b0f2c8ce..6b586bd64 100644 --- a/nuttx/configs/micropendous3/README.txt +++ b/nuttx/configs/micropendous3/README.txt @@ -200,7 +200,7 @@ There are several toolchain options. However, testing has been performed using *only* the NuttX buildroot toolchain described below. Therefore, the NuttX buildroot toolchain is the recommended choice. -The toolchain may be selected using the mconf tool (via 'make menuconfig'), +The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'), by editing the existing configuration file (defconfig), or by overriding the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=. diff --git a/nuttx/configs/mirtoo/README.txt b/nuttx/configs/mirtoo/README.txt index 89c137a03..6d3ea234e 100644 --- a/nuttx/configs/mirtoo/README.txt +++ b/nuttx/configs/mirtoo/README.txt @@ -324,7 +324,7 @@ Toolchains ========== Note that in addition to the configuration options listed below, the - toolchain can be configured using the mconf utility ('make menuconfig') + toolchain can be configured using the kconfig-mconf utility ('make menuconfig') or by passing CONFIG_MIPS32_TOOLCHAIN= to make, where is one of GNU_ELF, MICROCHIPL, MICROCHIPW, MICROCHIPL_LITE, MICROCHIPW_LITE, MICROCHIPOPENL or PINGUINOW as described below. diff --git a/nuttx/configs/ntosd-dm320/README.txt b/nuttx/configs/ntosd-dm320/README.txt index d85e53525..675716154 100644 --- a/nuttx/configs/ntosd-dm320/README.txt +++ b/nuttx/configs/ntosd-dm320/README.txt @@ -72,8 +72,8 @@ GNU Toolchain Options If you are not using CONFIG_DM320_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. - The toolchain may also be set using the mconf utility (make menuconfig) or by - passing CONFIG_ARM_TOOLCHAIN= to make, where is one + The toolchain may also be set using the kconfig-mconf utility (make menuconfig) + or by passing CONFIG_ARM_TOOLCHAIN= to make, where is one of CODESOURCERYW, CODESOURCERYL, DEVKITARM, BUILDROOT or GNU_EABI as described above. diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt index 35f00e9f2..13c63d18b 100644 --- a/nuttx/configs/olimex-lpc1766stk/README.txt +++ b/nuttx/configs/olimex-lpc1766stk/README.txt @@ -904,8 +904,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index ff756fb4b..8abfd9c23 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -209,8 +209,8 @@ cxxtest 2. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -455,8 +455,8 @@ nxlines 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -481,8 +481,8 @@ nxwm 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -543,8 +543,8 @@ ostest 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/stm3220g-eval/README.txt b/nuttx/configs/stm3220g-eval/README.txt index e7bdd4de0..40c918582 100644 --- a/nuttx/configs/stm3220g-eval/README.txt +++ b/nuttx/configs/stm3220g-eval/README.txt @@ -65,8 +65,8 @@ GNU Toolchain Options If you change the default toolchain, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. - The toolchain may also be set using the mconf utility (make menuconfig) or by - passing CONFIG_ARMV7M_TOOLCHAIN= to make, where is one + The toolchain may also be set using the kconfig-mconf utility (make menuconfig) + or by passing CONFIG_ARMV7M_TOOLCHAIN= to make, where is one of CODESOURCERYW, CODESOURCERYL, ATOLLOC, DEVKITARM, RAISONANCE, BUILDROOT or GNU_EABI as described above. @@ -1082,8 +1082,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt index 829f3a777..e8a3c4b25 100644 --- a/nuttx/configs/stm3240g-eval/README.txt +++ b/nuttx/configs/stm3240g-eval/README.txt @@ -951,9 +951,9 @@ Where is one of the following: CONFIG_EXAMPLES_DISCOVER_IPADDR - (not defined) CONFIG_EXAMPLES_DISCOVER_DRIPADDR - Router IP address - NOTE: This configuration uses to the mconf configuration tool to control - the configuration. See the section entitled "NuttX Configuration Tool" - in the top-level README.txt file. + NOTE: This configuration uses to the kconfig-mconf configuration tool to + control the configuration. See the section entitled "NuttX Configuration + Tool" in the top-level README.txt file. nettest: ------- diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index 28072f44b..ef61b05e6 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -1038,8 +1038,8 @@ Where is one of the following: 2. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -1087,8 +1087,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -1121,8 +1121,8 @@ Where is one of the following: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -1350,8 +1350,8 @@ Where is one of the following: 2. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/teensy/README.txt b/nuttx/configs/teensy/README.txt index 951f4a87e..23e7d6c98 100644 --- a/nuttx/configs/teensy/README.txt +++ b/nuttx/configs/teensy/README.txt @@ -203,7 +203,7 @@ There are several toolchain options. However, testing has been performed using *only* the NuttX buildroot toolchain described below. Therefore, the NuttX buildroot toolchain is the recommended choice. -The toolchain may be selected using the mconf tool (via 'make menuconfig'), +The toolchain may be selected using the kconfig-mconf tool (via 'make menuconfig'), by editing the existing configuration file (defconfig), or by overriding the toolchain on the make commandline with CONFIG_AVR_TOOLCHAIN=. diff --git a/nuttx/configs/xtrs/README.txt b/nuttx/configs/xtrs/README.txt index d462dcab1..f8b3d0e73 100644 --- a/nuttx/configs/xtrs/README.txt +++ b/nuttx/configs/xtrs/README.txt @@ -165,7 +165,7 @@ Reconfiguring NuttX These configurations all use the kconfig-frontends, mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and + a. Build and install the kconfig-mconf tool. See nuttx/README.txt and misc/tools/README.txt b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration diff --git a/nuttx/configs/z16f2800100zcog/README.txt b/nuttx/configs/z16f2800100zcog/README.txt index e12931df2..4d61a41da 100644 --- a/nuttx/configs/z16f2800100zcog/README.txt +++ b/nuttx/configs/z16f2800100zcog/README.txt @@ -105,8 +105,8 @@ ostest 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -154,8 +154,8 @@ pashello 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/z80sim/README.txt b/nuttx/configs/z80sim/README.txt index 595a17783..f4055207c 100644 --- a/nuttx/configs/z80sim/README.txt +++ b/nuttx/configs/z80sim/README.txt @@ -112,7 +112,7 @@ Reconfiguring NuttX These configurations all use the kconfig-frontends, mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and + a. Build and install the kconfig-mconf tool. See nuttx/README.txt and misc/tools/README.txt b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration diff --git a/nuttx/configs/z8encore000zco/README.txt b/nuttx/configs/z8encore000zco/README.txt index 7ca50db8c..70d62ea80 100644 --- a/nuttx/configs/z8encore000zco/README.txt +++ b/nuttx/configs/z8encore000zco/README.txt @@ -73,8 +73,8 @@ available: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/z8f64200100kit/README.txt b/nuttx/configs/z8f64200100kit/README.txt index b0f224ad8..e3c22d87b 100644 --- a/nuttx/configs/z8f64200100kit/README.txt +++ b/nuttx/configs/z8f64200100kit/README.txt @@ -73,8 +73,8 @@ available: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/configs/zp214xpa/README.txt b/nuttx/configs/zp214xpa/README.txt index 58a2242d0..88d03b9de 100644 --- a/nuttx/configs/zp214xpa/README.txt +++ b/nuttx/configs/zp214xpa/README.txt @@ -303,8 +303,8 @@ Configurations: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. @@ -327,8 +327,8 @@ Configurations: 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the mconf tool. See nuttx/README.txt and - misc/tools/ + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration process. diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h new file mode 100644 index 000000000..3463670b5 --- /dev/null +++ b/nuttx/include/spawn.h @@ -0,0 +1,137 @@ +/**************************************************************************** + * include/spawn.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_LIBGEN_H +#define __INCLUDE_LIBGEN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* "The spawn.h header shall define the flags that may be set in a + * posix_spawnattr_t object using the posix_spawnattr_setflags() function:" + */ + +#define POSIX_SPAWN_RESETIDS (1 << 0) +#define POSIX_SPAWN_SETPGROUP (1 << 1) +#define POSIX_SPAWN_SETSCHEDPARAM (1 << 2) +#define POSIX_SPAWN_SETSCHEDULER (1 << 3) +#define POSIX_SPAWN_SETSIGDEF (1 << 4) +#define POSIX_SPAWN_SETSIGMASK (1 << 5) + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ +/* "The spawn.h header shall define the posix_spawnattr_t and + * posix_spawn_file_actions_t types used in performing spawn operations. + */ + +struct posix_spawnattr_s +{ +/* To be provided */ +}; +typedef struct posix_spawnattr_s posix_spawnattr_t; + +struct posix_spawn_file_actions_s +{ +/* To be provided */ +}; +typedef struct posix_spawn_file_actions_s posix_spawn_file_actions_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ +/* "The following shall be declared as functions and may also be defined as + * macros. Function prototypes shall be provided." + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +int posix_spawn(FAR pid_t *, FAR const char *, + FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, + FAR char *const [], FAR char *const []); +int posix_spawnp(FAR pid_t *, FAR const char *, + FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, + FAR char *const [], FAR char *const []); + +int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *); +int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *); + +int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *, + int); +int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *, + int, int); +int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *, + int, FAR const char *, int, mode_t); + +int posix_spawnattr_init(FAR posix_spawnattr_t *); +int posix_spawnattr_destroy(FAR posix_spawnattr_t *); + +int posix_spawnattr_getflags(FAR const posix_spawnattr_t *, FAR short *); +int posix_spawnattr_getpgroup(FAR const posix_spawnattr_t *, FAR pid_t *); +int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *, + FAR struct sched_param *); +int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *, + FAR int *); +int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *, + FAR sigset_t *); +int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *, + FAR sigset_t *); + +int posix_spawnattr_setflags(FAR posix_spawnattr_t *, short); +int posix_spawnattr_setpgroup(FAR posix_spawnattr_t *, pid_t); +int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *, + FAR const struct sched_param *); +int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *, int); +int posix_spawnattr_setsigdefault(FAR posix_spawnattr_t *, + FAR const sigset_t *); +int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *, + FAR const sigset_t *); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_LIBGEN_H */ diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index 699b3ebb2..d739b6351 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -72,15 +72,17 @@ config EOL_IS_EITHER_CRLF endchoice config LIBC_EXECFUNCS - bool "Enable exec[l|v] Support" + bool "Enable exec[l|v] / posix_spawn() Support" default n depends on !BINFMT_DISABLE ---help--- Enable support for the exec[l|v] family of functions that can be - used to start other programs, terminating the current program. - Typical usage is (1) first call vfork() to create a new thread, then - (2) call exec[l|v] to replace the new thread with a program from the - file system. + used to start other programs, terminating the current program and + the posix_spawn() familty of functions that can be used start other + programs without terminating the current program. The typical + usage of the exec[l|v] functions is (1) first call vfork() to create + a new thread, then (2) call exec[l|v] to replace the new thread with + a program from the file system. NOTE 1: This two step process start is completely unnecessary in NuttX and is provided only for compatibily with Unix systems. These @@ -89,9 +91,11 @@ config LIBC_EXECFUNCS the new thread will be terminated by the exec[l|v] call, it really served no purpose other than to suport Unix compatility. - NOTE 2: Support for exec[l|v] is conditional because is requires - additional support for symbol tables that will not be available in - the typical system. + The posix_spawn() functions do not have this inefficiency. + + NOTE 2: Support for exec[l|v] and posix_spawn() is conditional + because they require additional support for symbol tables that + will not be available in the typical system. if LIBC_EXECFUNCS @@ -99,8 +103,8 @@ config EXECFUNCS_SYMTAB string "Symbol table used by exec[l|v]" default "g_symtab" ---help--- - The exec[l|v] functions are wrapper functions that (1) call the non- - standard binfmt function 'exec', and then (2) exit(0). The binfmt + The exec[l|v] and posix_spawn() functions are wrapper functions that + call the non-standard binfmt function 'exec'). The binfmt function 'exec' needs to have (1) a symbol table that provides the list of symbols exported by the base code, and (2) the number of symbols in that table. This selection provides the name of that @@ -110,8 +114,8 @@ config EXECFUNCS_NSYMBOLS int "Number of Symbols in the Table" default 0 ---help--- - The exec[l|v] functions are wrapper functions that (1) call the non- - standard binfmt function 'exec', and then (2) exit(0). The binfmt + The exec[l|v] and posix_spawn() functions are wrapper functions that + call the non-standard binfmt function 'exec'). The binfmt function 'exec' needs to have (1) a symbol table that provides the list of symbols exported by the base code, and (2) the number of symbols in that table. This selection provides the number of diff --git a/nuttx/libc/Makefile b/nuttx/libc/Makefile index 22dbba1d9..a76620585 100644 --- a/nuttx/libc/Makefile +++ b/nuttx/libc/Makefile @@ -57,6 +57,7 @@ include time/Make.defs include libgen/Make.defs include dirent/Make.defs include termios/Make.defs +include spawn/Make.defs include queue/Make.defs include misc/Make.defs diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs new file mode 100644 index 000000000..17d9f393a --- /dev/null +++ b/nuttx/libc/spawn/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# libc/spawn/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Add the spawn C files to the build + +ifeq ($(CONFIG_LIBC_EXECFUNCS),y) + +CSRCS += + +# Add the spawn directory to the build + +DEPPATH += --dep-path spawn +VPATH += :spawn +endif diff --git a/nuttx/tools/README.txt b/nuttx/tools/README.txt index 5651ff2f0..8df4a7783 100644 --- a/nuttx/tools/README.txt +++ b/nuttx/tools/README.txt @@ -445,11 +445,11 @@ kconfig.bat only a few options for the Windows user (see the top-level README.txt file). - You can, with some effort, run the the Cygwin mconf tool directly + You can, with some effort, run the the Cygwin kconfig-mconf tool directly in the CMD.exe shell. In this case, you do not have to modify the .config file, but there are other complexities: You need to temporarily set the Cgywin directories in the PATH variable and - then run mconf outside of the Make system. + then run kconfig-mconf outside of the Make system. kconfig.bat is a Windows batch file at tools/kconfig.bat that automates these steps. It is used from the top-level NuttX directory like: @@ -457,8 +457,8 @@ kconfig.bat tools/kconfig menuconfig NOTE: There is an currently an issue with accessing DOS environment - variables from the Cygwin mconf running in the CMD.exe shell. The - following change to the top-level Kconfig file seems to work around + variables from the Cygwin kconfig-mconf running in the CMD.exe shell. + The following change to the top-level Kconfig file seems to work around these problems: config APPSDIR diff --git a/nuttx/tools/kconfig.bat b/nuttx/tools/kconfig.bat index 65ab60506..db01e7515 100755 --- a/nuttx/tools/kconfig.bat +++ b/nuttx/tools/kconfig.bat @@ -100,15 +100,15 @@ echo ERROR: Unrecognized action: %action% goto :ShowUsage :DoConfig -conf Kconfig +kconfig-conf Kconfig goto End :DoOldConfig -conf --oldconfig Kconfig +kconfig-conf --oldconfig Kconfig goto End :DoMenuConfig -mconf Kconfig +kconfig-mconf Kconfig goto End :MissingArgument -- cgit v1.2.3 From 51fc8af31f24540bd567bd6d808b8a1fffc4adbc Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 9 Jan 2013 14:48:55 +0000 Subject: Rename LM3S files, variables, and types from lm3s_ to lm_; Rename configuration variables from CONFIG_LM3S_ to CONFIG_LM_ git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5497 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/Documentation/NuttxPortingGuide.html | 2 +- nuttx/arch/arm/include/lm/irq.h | 18 +- nuttx/arch/arm/src/armv7-m/Toolchain.defs | 8 +- nuttx/arch/arm/src/lm/Kconfig | 56 +- nuttx/arch/arm/src/lm/Make.defs | 9 +- nuttx/arch/arm/src/lm/chip.h | 16 +- nuttx/arch/arm/src/lm/chip/lm3s_epi.h | 113 -- nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h | 203 --- nuttx/arch/arm/src/lm/chip/lm3s_flash.h | 128 -- nuttx/arch/arm/src/lm/chip/lm3s_gpio.h | 395 ----- nuttx/arch/arm/src/lm/chip/lm3s_i2c.h | 247 --- nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h | 2 +- nuttx/arch/arm/src/lm/chip/lm3s_ssi.h | 235 --- nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h | 495 ------ nuttx/arch/arm/src/lm/chip/lm3s_timer.h | 125 -- nuttx/arch/arm/src/lm/chip/lm3s_uart.h | 347 ----- nuttx/arch/arm/src/lm/chip/lm_epi.h | 113 ++ nuttx/arch/arm/src/lm/chip/lm_ethernet.h | 203 +++ nuttx/arch/arm/src/lm/chip/lm_flash.h | 128 ++ nuttx/arch/arm/src/lm/chip/lm_gpio.h | 395 +++++ nuttx/arch/arm/src/lm/chip/lm_i2c.h | 247 +++ nuttx/arch/arm/src/lm/chip/lm_ssi.h | 235 +++ nuttx/arch/arm/src/lm/chip/lm_syscontrol.h | 495 ++++++ nuttx/arch/arm/src/lm/chip/lm_timer.h | 125 ++ nuttx/arch/arm/src/lm/chip/lm_uart.h | 347 +++++ nuttx/arch/arm/src/lm/lm3s_dumpgpio.c | 167 --- nuttx/arch/arm/src/lm/lm3s_ethernet.c | 1472 ------------------ nuttx/arch/arm/src/lm/lm3s_gpio.c | 854 ----------- nuttx/arch/arm/src/lm/lm3s_gpioirq.c | 434 ------ nuttx/arch/arm/src/lm/lm3s_irq.c | 458 ------ nuttx/arch/arm/src/lm/lm3s_lowputc.c | 309 ---- nuttx/arch/arm/src/lm/lm3s_serial.c | 1064 ------------- nuttx/arch/arm/src/lm/lm3s_ssi.c | 1580 -------------------- nuttx/arch/arm/src/lm/lm3s_start.c | 154 -- nuttx/arch/arm/src/lm/lm3s_syscontrol.c | 315 ---- nuttx/arch/arm/src/lm/lm3s_timerisr.c | 142 -- nuttx/arch/arm/src/lm/lm3s_vectors.S | 805 ---------- nuttx/arch/arm/src/lm/lm_dumpgpio.c | 167 +++ nuttx/arch/arm/src/lm/lm_ethernet.c | 1472 ++++++++++++++++++ nuttx/arch/arm/src/lm/lm_ethernet.h | 4 +- nuttx/arch/arm/src/lm/lm_gpio.c | 854 +++++++++++ nuttx/arch/arm/src/lm/lm_gpio.h | 42 +- nuttx/arch/arm/src/lm/lm_gpioirq.c | 434 ++++++ nuttx/arch/arm/src/lm/lm_irq.c | 458 ++++++ nuttx/arch/arm/src/lm/lm_lowputc.c | 309 ++++ nuttx/arch/arm/src/lm/lm_lowputc.h | 2 +- nuttx/arch/arm/src/lm/lm_serial.c | 1064 +++++++++++++ nuttx/arch/arm/src/lm/lm_ssi.c | 1580 ++++++++++++++++++++ nuttx/arch/arm/src/lm/lm_ssi.h | 16 +- nuttx/arch/arm/src/lm/lm_start.c | 154 ++ nuttx/arch/arm/src/lm/lm_syscontrol.c | 315 ++++ nuttx/arch/arm/src/lm/lm_syscontrol.h | 6 +- nuttx/arch/arm/src/lm/lm_timerisr.c | 142 ++ nuttx/arch/arm/src/lm/lm_vectors.S | 805 ++++++++++ nuttx/configs/eagle100/README.txt | 38 +- nuttx/configs/eagle100/httpd/defconfig | 42 +- nuttx/configs/eagle100/include/board.h | 12 +- nuttx/configs/eagle100/nettest/defconfig | 42 +- nuttx/configs/eagle100/nsh/defconfig | 42 +- nuttx/configs/eagle100/nxflat/defconfig | 42 +- nuttx/configs/eagle100/ostest/defconfig | 42 +- nuttx/configs/eagle100/src/eagle100_internal.h | 4 +- nuttx/configs/eagle100/src/up_boot.c | 10 +- nuttx/configs/eagle100/src/up_ethernet.c | 8 +- nuttx/configs/eagle100/src/up_leds.c | 20 +- nuttx/configs/eagle100/src/up_ssi.c | 26 +- nuttx/configs/eagle100/thttpd/defconfig | 42 +- nuttx/configs/ekk-lm3s9b96/README.txt | 48 +- nuttx/configs/ekk-lm3s9b96/include/board.h | 12 +- nuttx/configs/ekk-lm3s9b96/nsh/defconfig | 54 +- nuttx/configs/ekk-lm3s9b96/ostest/defconfig | 54 +- .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h | 4 +- nuttx/configs/ekk-lm3s9b96/src/up_boot.c | 10 +- nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c | 8 +- nuttx/configs/ekk-lm3s9b96/src/up_leds.c | 20 +- nuttx/configs/ekk-lm3s9b96/src/up_ssi.c | 26 +- nuttx/configs/lm3s6432-s2e/README.txt | 48 +- nuttx/configs/lm3s6432-s2e/include/board.h | 12 +- nuttx/configs/lm3s6432-s2e/nsh/defconfig | 52 +- nuttx/configs/lm3s6432-s2e/ostest/defconfig | 52 +- .../lm3s6432-s2e/src/lm3s6432s2e_internal.h | 4 +- nuttx/configs/lm3s6432-s2e/src/up_boot.c | 20 +- nuttx/configs/lm3s6432-s2e/src/up_ethernet.c | 8 +- nuttx/configs/lm3s6432-s2e/src/up_leds.c | 22 +- nuttx/configs/lm3s6432-s2e/src/up_ssi.c | 26 +- nuttx/configs/lm3s6965-ek/README.txt | 48 +- nuttx/configs/lm3s6965-ek/include/board.h | 12 +- nuttx/configs/lm3s6965-ek/nsh/defconfig | 48 +- nuttx/configs/lm3s6965-ek/nx/defconfig | 30 +- nuttx/configs/lm3s6965-ek/ostest/defconfig | 30 +- .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h | 4 +- nuttx/configs/lm3s6965-ek/src/up_boot.c | 10 +- nuttx/configs/lm3s6965-ek/src/up_ethernet.c | 8 +- nuttx/configs/lm3s6965-ek/src/up_leds.c | 20 +- nuttx/configs/lm3s6965-ek/src/up_oled.c | 14 +- nuttx/configs/lm3s6965-ek/src/up_ssi.c | 30 +- nuttx/configs/lm3s8962-ek/README.txt | 48 +- nuttx/configs/lm3s8962-ek/include/board.h | 12 +- nuttx/configs/lm3s8962-ek/nsh/defconfig | 54 +- nuttx/configs/lm3s8962-ek/nx/defconfig | 54 +- nuttx/configs/lm3s8962-ek/ostest/defconfig | 54 +- .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h | 4 +- nuttx/configs/lm3s8962-ek/src/up_boot.c | 10 +- nuttx/configs/lm3s8962-ek/src/up_ethernet.c | 8 +- nuttx/configs/lm3s8962-ek/src/up_leds.c | 20 +- nuttx/configs/lm3s8962-ek/src/up_oled.c | 14 +- nuttx/configs/lm3s8962-ek/src/up_ssi.c | 30 +- 107 files changed, 10838 insertions(+), 10839 deletions(-) delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_epi.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_flash.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_gpio.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_i2c.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_ssi.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_timer.h delete mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_uart.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_epi.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_ethernet.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_flash.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_gpio.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_i2c.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_ssi.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_syscontrol.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_timer.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_uart.h delete mode 100644 nuttx/arch/arm/src/lm/lm3s_dumpgpio.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_ethernet.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_gpio.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_gpioirq.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_irq.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_lowputc.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_serial.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_ssi.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_start.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_syscontrol.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_timerisr.c delete mode 100644 nuttx/arch/arm/src/lm/lm3s_vectors.S create mode 100644 nuttx/arch/arm/src/lm/lm_dumpgpio.c create mode 100644 nuttx/arch/arm/src/lm/lm_ethernet.c create mode 100644 nuttx/arch/arm/src/lm/lm_gpio.c create mode 100644 nuttx/arch/arm/src/lm/lm_gpioirq.c create mode 100644 nuttx/arch/arm/src/lm/lm_irq.c create mode 100644 nuttx/arch/arm/src/lm/lm_lowputc.c create mode 100644 nuttx/arch/arm/src/lm/lm_serial.c create mode 100644 nuttx/arch/arm/src/lm/lm_ssi.c create mode 100644 nuttx/arch/arm/src/lm/lm_start.c create mode 100644 nuttx/arch/arm/src/lm/lm_syscontrol.c create mode 100644 nuttx/arch/arm/src/lm/lm_timerisr.c create mode 100644 nuttx/arch/arm/src/lm/lm_vectors.S diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index 48fafb89f..b1664f3f0 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -2901,7 +2901,7 @@ extern void up_ledoff(int led);

        • Examples: - arch/arm/src/chip/lm3s_serial.c, arch/arm/src/lpc214x/lpc214x_serial.c, arch/z16/src/z16f/z16f_serial.c, etc. + arch/arm/src/chip/lm_serial.c, arch/arm/src/lpc214x/lpc214x_serial.c, arch/z16/src/z16f/z16f_serial.c, etc.

          • diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h index a80517e40..136496fef 100644 --- a/nuttx/arch/arm/include/lm/irq.h +++ b/nuttx/arch/arm/include/lm/irq.h @@ -308,7 +308,7 @@ * be disabled in order to reduce the size of the implemenation. */ -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS # define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0) # define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1) # define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2) @@ -322,7 +322,7 @@ # define _NGPIOAIRQS NR_IRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS # define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0) # define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1) # define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2) @@ -336,7 +336,7 @@ # define _NGPIOBIRQS _NGPIOAIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS # define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0) # define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1) # define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2) @@ -350,7 +350,7 @@ # define _NGPIOCIRQS _NGPIOBIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS # define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0) # define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1) # define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2) @@ -364,7 +364,7 @@ # define _NGPIODIRQS _NGPIOCIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS # define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0) # define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1) # define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2) @@ -378,7 +378,7 @@ # define _NGPIOEIRQS _NGPIODIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS # define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0) # define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1) # define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2) @@ -392,7 +392,7 @@ # define _NGPIOFIRQS _NGPIOEIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS # define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0) # define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1) # define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2) @@ -406,7 +406,7 @@ # define _NGPIOGIRQS _NGPIOFIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS # define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0) # define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1) # define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2) @@ -420,7 +420,7 @@ # define _NGPIOHIRQS _NGPIOGIRQS #endif -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS +#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS # define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0) # define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1) # define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2) diff --git a/nuttx/arch/arm/src/armv7-m/Toolchain.defs b/nuttx/arch/arm/src/armv7-m/Toolchain.defs index d7f2ed77f..45ee9e36c 100644 --- a/nuttx/arch/arm/src/armv7-m/Toolchain.defs +++ b/nuttx/arch/arm/src/armv7-m/Toolchain.defs @@ -53,7 +53,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_BUILDROOT) \ - $(CONFIG_LM3S_BUILDROOT) \ + $(CONFIG_LM_BUILDROOT) \ $(CONFIG_LPC17_BUILDROOT) \ $(CONFIG_LPC43_BUILDROOT) \ $(CONFIG_SAM3U_BUILDROOT) \ @@ -77,7 +77,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_CODESOURCERYL) \ - $(CONFIG_LM3S_CODESOURCERYL) \ + $(CONFIG_LM_CODESOURCERYL) \ $(CONFIG_LPC17_CODESOURCERYL) \ $(CONFIG_LPC43_CODESOURCERYL) \ $(CONFIG_SAM3U_CODESOURCERYL) \ @@ -88,7 +88,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_CODESOURCERYW) \ - $(CONFIG_LM3S_CODESOURCERYW) \ + $(CONFIG_LM_CODESOURCERYW) \ $(CONFIG_LPC17_CODESOURCERYW) \ $(CONFIG_LPC43_CODESOURCERYW) \ $(CONFIG_SAM3U_CODESOURCERYW) \ @@ -99,7 +99,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_DEVKITARM) \ - $(CONFIG_LM3S_DEVKITARM) \ + $(CONFIG_LM_DEVKITARM) \ $(CONFIG_LPC17_DEVKITARM) \ $(CONFIG_LPC43_DEVKITARM) \ $(CONFIG_SAM3U_DEVKITARM) \ diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig index 2d2504c7e..5d6bccc92 100644 --- a/nuttx/arch/arm/src/lm/Kconfig +++ b/nuttx/arch/arm/src/lm/Kconfig @@ -14,7 +14,7 @@ config ARCH_CHIP_LM3S6918 bool "LM3S6918" select ARCH_CORTEXM3 select ARCH_CHIP_LM3S - select LM3S_HAVE_SSI1 + select LM_HAVE_SSI1 config ARCH_CHIP_LM3S9B96 bool "LM3S9B96" @@ -46,28 +46,28 @@ config ARCH_CHIP_LM3S config ARCH_CHIP_LM4F bool -config LM3S_HAVE_SSI1 +config LM_HAVE_SSI1 bool -config LM3S_REVA2 +config LM_REVA2 bool "Rev A2" default n ---help--- Some early silicon returned an increase LDO voltage or 2.75V to work around a PLL bug -config LM3S_DFU +config LM_DFU bool "DFU" default y menu "Stellaris Peripheral Support" -config LM3S_UART0 +config LM_UART0 bool "UART0" select ARCH_HAVE_UART0 default n -config LM3S_UART1 +config LM_UART1 bool "UART1" select ARCH_HAVE_UART1 default n @@ -80,12 +80,12 @@ config SSI1_DISABLE bool "Disable SSI1" default y -config LM3S_UART2 +config LM_UART2 bool "UART2" select ARCH_HAVE_UART2 default n -config LM3S_ETHERNET +config LM_ETHERNET bool "Stellaris Ethernet" default n ---help--- @@ -95,95 +95,95 @@ endmenu menu "Disable GPIO Interrupts" -config LM3S_DISABLE_GPIOA_IRQS +config LM_DISABLE_GPIOA_IRQS bool "Disable GPIOA IRQs" default n -config LM3S_DISABLE_GPIOB_IRQS +config LM_DISABLE_GPIOB_IRQS bool "Disable GPIOB IRQs" default n -config LM3S_DISABLE_GPIOC_IRQS +config LM_DISABLE_GPIOC_IRQS bool "Disable GPIOC IRQs" default n -config LM3S_DISABLE_GPIOD_IRQS +config LM_DISABLE_GPIOD_IRQS bool "Disable GPIOD IRQs" default n -config LM3S_DISABLE_GPIOE_IRQS +config LM_DISABLE_GPIOE_IRQS bool "Disable GPIOE IRQs" default n -config LM3S_DISABLE_GPIOF_IRQS +config LM_DISABLE_GPIOF_IRQS bool "Disable GPIOF IRQs" default n -config LM3S_DISABLE_GPIOG_IRQS +config LM_DISABLE_GPIOG_IRQS bool "Disable GPIOG IRQs" default n -config LM3S_DISABLE_GPIOH_IRQS +config LM_DISABLE_GPIOH_IRQS bool "Disable GPIOH IRQs" default n -config LM3S_DISABLE_GPIOJ_IRQS +config LM_DISABLE_GPIOJ_IRQS bool "Disable GPIOJ IRQs" default n endmenu -if LM3S_ETHERNET +if LM_ETHERNET menu "Stellaris Ethernet Configuration" -config LM3S_ETHLEDS +config LM_ETHLEDS bool "Ethernet LEDs" default n ---help--- Enable to use Ethernet LEDs on the board. -config LM3S_BOARDMAC +config LM_BOARDMAC bool "Board MAC" default n ---help--- If the board-specific logic can provide a MAC address (via - lm3s_ethernetmac()), then this should be selected. + lm_ethernetmac()), then this should be selected. -config LM3S_ETHHDUPLEX +config LM_ETHHDUPLEX bool "Force Half Duplex" default n ---help--- Set to force half duplex operation -config LM3S_ETHNOAUTOCRC +config LM_ETHNOAUTOCRC bool "Disable auto-CRC" default n ---help--- Set to suppress auto-CRC generation -config LM3S_ETHNOPAD +config LM_ETHNOPAD bool "Disable Tx Padding" default n ---help--- Set to suppress Tx padding -config LM3S_MULTICAST +config LM_MULTICAST bool "Enable Multicast" default n ---help--- Set to enable multicast frames -config LM3S_PROMISCUOUS +config LM_PROMISCUOUS bool "Enable Promiscuous Mode" default n ---help--- Set to enable promiscuous mode -config LM3S_TIMESTAMP +config LM_TIMESTAMP bool "Enable Timestamping" default n -config LM3S_BADCRC +config LM_BADCRC bool "Enable Bad CRC Rejection" default n ---help--- diff --git a/nuttx/arch/arm/src/lm/Make.defs b/nuttx/arch/arm/src/lm/Make.defs index aacbb1c83..e760f7e01 100644 --- a/nuttx/arch/arm/src/lm/Make.defs +++ b/nuttx/arch/arm/src/lm/Make.defs @@ -33,7 +33,7 @@ # ############################################################################ -HEAD_ASRC = lm3s_vectors.S +HEAD_ASRC = lm_vectors.S CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ vfork.S @@ -55,10 +55,9 @@ CMN_CSRCS += up_elf.c endif CHIP_ASRCS = -CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \ - lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \ - lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c +CHIP_CSRCS = lm_start.c lm_syscontrol.c lm_irq.c lm_gpio.c lm_gpioirq.c \ + lm_timerisr.c lm_lowputc.c lm_serial.c lm_ssi.c lm_dumpgpio.c ifdef CONFIG_NET -CHIP_CSRCS += lm3s_ethernet.c +CHIP_CSRCS += lm_ethernet.c endif diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h index 5857b3094..b5974b5dc 100644 --- a/nuttx/arch/arm/src/lm/chip.h +++ b/nuttx/arch/arm/src/lm/chip.h @@ -49,14 +49,14 @@ /* Then get all of the register definitions */ -#include "chip/lm_memorymap.h" /* Memory map */ -#include "chip/lm3s_syscontrol.h" /* System control module */ -#include "chip/lm3s_gpio.h" /* GPIO modules */ -#include "chip/lm3s_uart.h" /* UART modules */ -#include "chip/lm3s_i2c.h" /* I2C modules */ -#include "chip/lm3s_ssi.h" /* SSI modules */ -#include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ -#include "chip/lm3s_flash.h" /* FLASH */ +#include "chip/lm_memorymap.h" /* Memory map */ +#include "chip/lm_syscontrol.h" /* System control module */ +#include "chip/lm_gpio.h" /* GPIO modules */ +#include "chip/lm_uart.h" /* UART modules */ +#include "chip/lm_i2c.h" /* I2C modules */ +#include "chip/lm_ssi.h" /* SSI modules */ +#include "chip/lm_ethernet.h" /* Ethernet MAC and PHY */ +#include "chip/lm_flash.h" /* FLASH */ /* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism * will only look at the upper N bits of the 8-bit priority level (where N is 3 for diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h deleted file mode 100644 index 82fc94f4c..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_epi.h - * - * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. - * Author: Max Neklyudov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* External Peripheral Interface Register Offsets ***********************************/ - -#define LM3S_EPI_CFG_OFFSET 0x000 -#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 -#define LM3S_EPI_ADDRMAP_OFFSET 0x01C -#define LM3S_EPI_STAT_OFFSET 0x060 -#define LM3S_EPI_BAUD_OFFSET 0x004 - -/* External Peripheral Interface Register Addresses *********************************/ - -#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) -#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) -#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) -#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) -#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) - -/* External Peripheral Interface Register Bit Definitions ***************************/ - -/* EPI Configuration (EPICFG), offset 0x000 */ - -#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ -#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) -# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ - -/* EPI Address Map (EPIADDRMAP), offset 0x01C */ - -#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ -#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) -#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ -#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) - -/* EPI Status (EPISTAT), offset 0x060 */ - -#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ -#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) - -/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ - -#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ -#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) -#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ -#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) -# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) -#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ -#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) - -/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ - -#define EPI_BAUD_COUNT0_SHIFT 0 -#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) -# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h deleted file mode 100644 index 512e96221..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_ethernet.h - * - * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Ethernet Controller Register Offsets *********************************************/ - -/* Ethernet MAC Register Offsets */ - -#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ -#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ -#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ -#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ -#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ -#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ -#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ -#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ -#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ -#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ -#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ -#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ -#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ -#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ -#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ -#endif - -/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ - -/* Ethernet Controller Register Addresses *******************************************/ - -#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) -#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) -#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) -#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) -#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) -#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) -#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) -#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) -#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) -#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) -#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) -#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) -#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) -#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) -#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) -#endif - -/* Memory Mapped MII Management Registers */ - -#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) -#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) -#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) -#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) -#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) -#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) -#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) -#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) -#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) -#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) -#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) -#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) -#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) - -/* Ethernet Controller Register Bit Definitions *************************************/ - -/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ - -#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ -#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ -#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ -#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ -#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ -#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ -#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ - -#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ -#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ -#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ -#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ -#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ -#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ -#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ - -/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ - -#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ -#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ -#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ -#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ -#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ -#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ -#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ -#define MAC_IM_ALLINTS 0x7f - -/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ - -#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ -#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ -#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ -#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ -#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ - -/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ - -#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ -#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ -#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ -#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ - -/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ - -#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ - -/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ - -#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ -#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ -#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ -#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) - -/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ - -#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ - -/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ - -#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ - -/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ - -#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ - -/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ - -#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ - -/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ - -#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h deleted file mode 100644 index 2f6dc78fa..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h +++ /dev/null @@ -1,128 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_flash.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* FLASH register offsets ***********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ -#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ -#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ -#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ -#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ -#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ -#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ -#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ -#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ -#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ -#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ -#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ -#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ -#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ -#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ -#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ -#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ -#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ -#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ - -/* FLASH register addresses *********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. - */ - -#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) -#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) -#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) -#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) -#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) -#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE - */ - -#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) -#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) -#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) -#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) -#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) -#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) -#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) -#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) -#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) -#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) -#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) -#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) -#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) -#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) - -/* FLASH register bit defitiions ****************************************************/ -/* To be provided */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h deleted file mode 100644 index 2c199dae9..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h +++ /dev/null @@ -1,395 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_gpio.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* GPIO Register Offsets ************************************************************/ - -#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ -#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ -#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ -#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ -#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ -#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ -#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ -#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ -#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ -#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ -#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ -#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ -#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ -#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ -#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ -#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ -#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ -#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ -#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ -#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ -#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ -#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ -#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ -#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ -#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ -#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ -#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ -#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ -#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ -#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ -#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ -#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ - -/* GPIO Register Addresses **********************************************************/ - -#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h deleted file mode 100644 index e029c4f3f..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h +++ /dev/null @@ -1,247 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_i2c.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* I2C Register Offsets *************************************************************/ - -/* I2C Master */ - -#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ -#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ -#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ -#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ -#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ -#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ -#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ -#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ -#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ - -/* I2C Slave */ - -#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ -#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ -#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ -#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ -#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ -#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ -#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ - -/* I2C Register Addresses ***********************************************************/ - -#if LM3S_NI2C > 0 - -/* I2C Master */ - -#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) -#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) - -/* I2C Slave */ - -#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) -#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) - -/* I2C0 Master */ - -#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C0 Slave */ - -#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) - -#if LM3S_NI2C > 1 - -/* I2C1 Master */ - -#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) - -/* I2C1 Slave */ - -#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) - -#endif -#endif - -/* I2C_Register Bit Definitions *****************************************************/ - -/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ - -#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ -#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ -#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) - -/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ - -#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ -#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ -#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ -#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ -#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ -#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ -#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ - -#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ -#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ -#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ -#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ - -/* I2C Master Data (I2CM_DR), offset 0x008 */ - -#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ - -/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ - -#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ - -/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ - -#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ - -/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ - -#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ - -#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ - -#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Configuration (I2CM_CR), offset 0x020 */ - -#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ -#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ -#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ - -/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ - -#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ - -/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ - -#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ -#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ -#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ - -#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ - -/* I2C Slave Data (I2CS_DR), offset 0x008 */ - -#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ - -/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ - -#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ - -/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ - -#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ - -/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ - -#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ - -/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ - -#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h index 85ec1369a..a478304b0 100644 --- a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h +++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h @@ -46,7 +46,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* The following lists the input value to lm3s_configgpio to setup the alternate, +/* The following lists the input value to lm_configgpio to setup the alternate, * hardware function for each pin. */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h deleted file mode 100644 index be5a766e5..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h +++ /dev/null @@ -1,235 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_ssi.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#if LM3S_NSSI > 0 - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* SSI register offsets *************************************************************/ - -#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ -#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ -#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ -#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ -#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ -#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ -#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ -#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ -#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ -#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ -#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ -#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ -#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ -#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ -#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ -#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ -#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ -#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ -#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ -#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ -#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ - -/* SSI register addresses ***********************************************************/ - -#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#if LM3S_NSSI > 1 -#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) - -#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) -#endif /* LM3S_NSSI > 1 */ - -/* SSI register bit defitiions ******************************************************/ - -/* SSI Control 0 (SSICR0), offset 0x000 */ - -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ -#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) -#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ -#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ -#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ -#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ -#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ -#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ -#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ -#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) - -/* SSI Control 1 (SSICR1), offset 0x004 */ - -#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ -#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ -#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ -#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ - -/* SSI Data (SSIDR), offset 0x008 */ - -#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ - -/* SSI Status (SSISR), offset 0x00c */ - -#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ -#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ -#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ -#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ -#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ - -/* SSI Clock Prescale (SSICPSR), offset 0x010 */ - -#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ - -/* SSI Interrupt Mask (SSIIM), offset 0x014 */ - -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ - -/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ - -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ - -/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ - -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ - -/* SSI Interrupt Clear (SSIICR), offset 0x020 */ - -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ - -/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ - -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ - -/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ - -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* LM3S_NSSI > 0 */ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h deleted file mode 100644 index 00a222ee3..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h +++ /dev/null @@ -1,495 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System Control Register Offsets **************************************************/ - -#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ -#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ -#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ -#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ - -/* System Control Register Addresses ************************************************/ - -#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) -#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) -#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) -#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) -#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) -#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) -#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) -#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) -#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) -#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) -#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) -#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) -#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) -#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) -#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) -#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) -#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) -#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) -#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) -#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) -#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) -#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) -#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) -#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) -#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) -#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) -#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) -#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) -#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) - -/* System Control Register Bit Definitions ******************************************/ - -/* Device Identification 0 (DID0), offset 0x000 */ - -#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ -#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) -#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ -#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) -#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ -#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ -#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) - -/* Device Identification 1 (DID1), offset 0x004 */ - -#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ -#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) -#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ -#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) -#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ -#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) -#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ -#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) -#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ -#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) -#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ -#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) -#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ -#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) - -/* Device Capabilities 0 (DC0), offset 0x008 */ - -#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ -#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) -#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ -#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) - -/* Device Capabilities 1 (DC1), offset 0x010 */ - -#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ -#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ -#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ -#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ -#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ -#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ -#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ -#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ -#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ -#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) -#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ -#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ -#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) - -/* Device Capabilities 2 (DC2), offset 0x014 */ - -#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ -#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ -#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ -#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ -#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ -#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ -#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ -#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ -#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ -#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ -#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ -#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ - -/* Device Capabilities 3 (DC3), offset 0x018 */ - -#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ -#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ -#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ -#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ -#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ -#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ -#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ -#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ -#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ -#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ -#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ -#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ -#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ -#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ -#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ -#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ -#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ -#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ -#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ -#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ - -/* Device Capabilities 4 (DC4), offset 0x01c */ - -#define SYSCON_DC4_GPIO(n) (1 << (n)) -#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ -#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ -#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ -#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ -#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ -#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ -#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ -#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ -#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ -#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ - -/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ - -#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ - -/* LDO Power Control (LDOPCTL), offset 0x034 */ - -#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ -#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) -# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ -# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ -# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ -# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ -# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ -# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ -# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ -# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ -# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ -# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ -# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ - -/* Software Reset Control 0 (SRCR0), offset 0x040 */ - -#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ -#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ -#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ - -/* Software Reset Control 1 (SRCR1), offset 0x044 */ - -#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ -#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ -#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ -#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ -#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ -#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ -#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ -#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ -#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ -#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ -#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ -#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ - -/* Software Reset Control 2 (SRCR2), offset 0x048 */ - -#define SYSCON_SRCR2_GPIO(n) (1 << (n)) -#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ -#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ -#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ -#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ -#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ -#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ -#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ -#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ -#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ -#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ - -/* Raw Interrupt Status (RIS), offset 0x050 */ - -#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ -#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ - -/* Interrupt Mask Control (IMC), offset 0x054 */ - -#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ -#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ - -/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ - -#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ -#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ - -/* Reset Cause (RESC), offset 0x05C */ - -#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ -#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ -#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ -#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ -#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ - -/* Run-Mode Clock Configuration (RCC), offset 0x060 */ - -#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ -#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ -#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ -#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) -# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) -# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ -# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ -# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ -# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ -# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ -# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ -# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ -# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ -# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ -# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ -# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ -# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ -# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ -#ifdef CONFIG_ARCH_CHIP_LM3S9B96 -# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ -# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ -# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ -# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ -# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ -#endif -#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ -#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ -#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ -#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) -# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) -#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ - -/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ - -#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ -#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) -#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ -#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) - -/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ - -#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ -#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) -# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ -# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ -# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ -#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ -#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ -#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) -#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ - -/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ - -#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) -#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ - -#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ - -#define SYSCON_RCGC2_GPIO(n) (1 << (n)) -#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ - -#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) -#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ - -#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ - -#define SYSCON_SCGC2_GPIO(n) (1 << (n)) -#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ - -#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) -#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ - -#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ - -#define SYSCON_DCGC2_GPIO(n) (1 << (n)) -#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ - -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h deleted file mode 100644 index 6be963cc3..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_timer.h - * - * Copyright (C) 2012 Max Nekludov. All rights reserved. - * Author: Max Nekludov - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Timer register offsets ***********************************************************/ - -#define TIMER_GPTMCFG_OFFSET 0x000 -#define TIMER_GPTMTAMR_OFFSET 0x004 -#define TIMER_GPTMCTL_OFFSET 0x00C -#define TIMER_GPTMIMR_OFFSET 0x018 -#define TIMER_GPTMRIS_OFFSET 0x01C -#define TIMER_GPTMICR_OFFSET 0x024 -#define TIMER_GPTMTAILR_OFFSET 0x028 -#define TIMER_GPTMTAR_OFFSET 0x048 - -/* SSI register addresses ***********************************************************/ - -#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) - -#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) -#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) -#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) -#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) -#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) -#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) -#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) -#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) - -/* SSI register bit defitiions ******************************************************/ - -/* GPTM Configuration (GPTMCFG), offset 0x000 */ - -#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ -#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) -#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ -#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ -#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ - -/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ - -#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ -#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) -#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ -#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ -#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ -#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ -#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) -#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ -#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ -#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ -#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) -#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ -#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ -#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ -#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) -#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ -#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ -#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ -#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) - -/* GPTM Control (GPTMCTL), offset 0x00C */ - -#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ -#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) -#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ -#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) - -/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ - -#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ -#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) - -/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ - -#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ -#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) - -/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ - -#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ -#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h deleted file mode 100644 index 98dcbce12..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h +++ /dev/null @@ -1,347 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_uart.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* UART register offsets ************************************************************/ - -#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ -#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ -#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ -#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ -#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ -#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ -#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ -#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ -#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ -#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ -#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ -#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ -#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ -#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ -#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ -#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ -#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ -#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ -#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ -#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ -#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ -#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ -#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ -#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ -#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ -#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ - -/* UART register addresses **********************************************************/ - -#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) - -#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) -#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) -#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) -#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) -#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) -#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) -#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) -#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) -#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) -#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) -#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) -#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) - -/* UART register bit settings *******************************************************/ - -/* UART Data (DR), offset 0x000 */ - -#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ -#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) -#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ -#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ -#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ -#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ - -/* UART Receive Status (RSR), offset 0x004 */ - -#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ -#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ -#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ -#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ - -/* UART Error Clear (ECR), offset 0x004 */ -/* Writing any value to this register clears pending error indications */ - -/* UART Flag (FR), offset 0x018 */ - -#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ -#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ -#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ -#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ -#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ - -/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ - -#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ - -/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ - -#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ - -/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ - -#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ - -/* Register 7: UART Line Control (LCRH), offset 0x02C */ - -#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ -#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ -#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ -#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ -#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ -#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ -#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) -# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ -# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ -# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ -# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ -#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ - -/* UART Control (CTL), offset 0x030 */ - -#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ -#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ -#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ -#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ -#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ -#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ - -/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ - -#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ -#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) -# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ -#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ -#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) -# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ - -/* UART Interrupt Mask (IM), offset 0x038 */ - -#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ -#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ -#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ -#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ -#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ -#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ -#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ - - -/* UART Raw Interrupt Status (RIS), offset 0x03c */ - -#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ -#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ -#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ -#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ -#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ -#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ -#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ - -/* UART Masked Interrupt Status (MIS), offset 0x040 */ - -#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ -#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ -#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ -#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ -#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ -#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ -#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ - -/* UART Interrupt Clear (ICR), offset 0x044 */ - -#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ -#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ -#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ -#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ -#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ -#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ -#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear - */ - -/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ - -#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ - -#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ - -#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ - -#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ - -#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ - -#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ - -#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ - -#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ - -#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ - -/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ - -#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ - -/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ - -#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ - -/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ - -#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_epi.h b/nuttx/arch/arm/src/lm/chip/lm_epi.h new file mode 100644 index 000000000..e36986079 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_epi.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_epi.h + * + * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. + * Author: Max Neklyudov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* External Peripheral Interface Register Offsets ***********************************/ + +#define LM3S_EPI_CFG_OFFSET 0x000 +#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 +#define LM3S_EPI_ADDRMAP_OFFSET 0x01C +#define LM3S_EPI_STAT_OFFSET 0x060 +#define LM3S_EPI_BAUD_OFFSET 0x004 + +/* External Peripheral Interface Register Addresses *********************************/ + +#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) +#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) +#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) +#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) +#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) + +/* External Peripheral Interface Register Bit Definitions ***************************/ + +/* EPI Configuration (EPICFG), offset 0x000 */ + +#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ +#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) +# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ + +/* EPI Address Map (EPIADDRMAP), offset 0x01C */ + +#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ +#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) +#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ +#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) + +/* EPI Status (EPISTAT), offset 0x060 */ + +#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ +#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) + +/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ + +#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ +#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) +#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ +#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) +# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) +#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ +#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) + +/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ + +#define EPI_BAUD_COUNT0_SHIFT 0 +#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) +# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h new file mode 100644 index 000000000..46a101005 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_ethernet.h + * + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Ethernet Controller Register Offsets *********************************************/ + +/* Ethernet MAC Register Offsets */ + +#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ +#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ +#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ +#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ +#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ +#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ +#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ +#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ +#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ +#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ +#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ +#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ +#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ +#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ +#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ +#endif + +/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ + +/* Ethernet Controller Register Addresses *******************************************/ + +#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) +#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) +#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) +#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) +#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) +#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) +#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) +#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) +#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) +#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) +#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) +#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) +#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) +#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) +#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) +#endif + +/* Memory Mapped MII Management Registers */ + +#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) +#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) +#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) +#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) +#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) +#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) +#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) +#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) +#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) +#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) +#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) +#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) +#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) + +/* Ethernet Controller Register Bit Definitions *************************************/ + +/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ + +#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ +#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ +#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ +#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ +#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ +#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ +#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ + +#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ +#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ +#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ +#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ +#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ +#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ +#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ + +/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ + +#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ +#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ +#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ +#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ +#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ +#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ +#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ +#define MAC_IM_ALLINTS 0x7f + +/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ + +#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ +#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ +#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ +#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ +#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ + +/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ + +#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ +#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ +#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ +#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ + +/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ + +#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ + +/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ + +#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ +#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ +#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ +#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) + +/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ + +#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ + +/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ + +#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ + +/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ + +#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ + +/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ + +#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ + +/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ + +#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_flash.h b/nuttx/arch/arm/src/lm/chip/lm_flash.h new file mode 100644 index 000000000..0d4808526 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_flash.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_flash.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* FLASH register offsets ***********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ +#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ +#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ +#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ +#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ +#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ +#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ +#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ +#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ +#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ +#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ +#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ +#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ +#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ +#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ +#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ +#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ +#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ +#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ + +/* FLASH register addresses *********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) +#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) +#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) +#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) +#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) +#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) +#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) +#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) +#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) +#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) +#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) +#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) +#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) +#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) +#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) +#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) +#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) +#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) +#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) + +/* FLASH register bit defitiions ****************************************************/ +/* To be provided */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_gpio.h b/nuttx/arch/arm/src/lm/chip/lm_gpio.h new file mode 100644 index 000000000..4ca8e8ff9 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_gpio.h @@ -0,0 +1,395 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ +#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ +#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ +#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ +#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ +#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ +#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ +#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ +#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ +#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ +#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ +#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ +#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ +#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ +#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ +#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ +#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ +#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ +#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ +#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ +#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ +#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ +#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ +#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ +#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ +#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ +#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ +#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ +#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ +#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ +#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ +#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ + +/* GPIO Register Addresses **********************************************************/ + +#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_i2c.h b/nuttx/arch/arm/src/lm/chip/lm_i2c.h new file mode 100644 index 000000000..919ac1348 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_i2c.h @@ -0,0 +1,247 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_i2c.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +/* I2C Master */ + +#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ +#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ +#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ +#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ +#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ +#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ +#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ +#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ +#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ + +/* I2C Slave */ + +#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ +#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ +#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ +#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ +#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ +#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ +#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ + +/* I2C Register Addresses ***********************************************************/ + +#if LM3S_NI2C > 0 + +/* I2C Master */ + +#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) +#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) + +/* I2C Slave */ + +#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) +#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) + +/* I2C0 Master */ + +#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C0 Slave */ + +#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) + +#if LM3S_NI2C > 1 + +/* I2C1 Master */ + +#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C1 Slave */ + +#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) + +#endif +#endif + +/* I2C_Register Bit Definitions *****************************************************/ + +/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ + +#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ +#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ +#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) + +/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ + +#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ +#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ +#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ +#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ +#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ +#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ +#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ + +#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ +#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ +#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ +#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ + +/* I2C Master Data (I2CM_DR), offset 0x008 */ + +#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ + +/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ + +#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ + +/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ + +#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ + +/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ + +#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ + +#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ + +#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Configuration (I2CM_CR), offset 0x020 */ + +#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ +#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ +#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ + +/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ + +#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ + +/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ + +#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ +#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ +#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ + +#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ + +/* I2C Slave Data (I2CS_DR), offset 0x008 */ + +#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ + +/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ + +#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ + +/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ + +#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ + +/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ + +#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ + +/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ + +#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_ssi.h b/nuttx/arch/arm/src/lm/chip/lm_ssi.h new file mode 100644 index 000000000..b58aec733 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_ssi.h @@ -0,0 +1,235 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_ssi.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if LM3S_NSSI > 0 + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* SSI register offsets *************************************************************/ + +#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ +#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ +#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ +#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ +#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ +#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ +#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ +#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ +#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ +#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ +#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ +#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ +#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ +#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ +#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ +#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ +#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ +#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ +#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ +#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ +#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ + +/* SSI register addresses ***********************************************************/ + +#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#if LM3S_NSSI > 1 +#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) + +#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) +#endif /* LM3S_NSSI > 1 */ + +/* SSI register bit defitiions ******************************************************/ + +/* SSI Control 0 (SSICR0), offset 0x000 */ + +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ +#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) +#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ +#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ +#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ +#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ +#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ +#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ +#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) + +/* SSI Control 1 (SSICR1), offset 0x004 */ + +#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ +#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ +#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ +#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ + +/* SSI Data (SSIDR), offset 0x008 */ + +#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ + +/* SSI Status (SSISR), offset 0x00c */ + +#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ +#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ +#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ +#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ +#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ + +/* SSI Clock Prescale (SSICPSR), offset 0x010 */ + +#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ + +/* SSI Interrupt Mask (SSIIM), offset 0x014 */ + +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ + +/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ + +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ + +/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ + +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ + +/* SSI Interrupt Clear (SSIICR), offset 0x020 */ + +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ + +/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ + +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ + +/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ + +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* LM3S_NSSI > 0 */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h new file mode 100644 index 000000000..6ca8ac3ff --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h @@ -0,0 +1,495 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System Control Register Offsets **************************************************/ + +#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ +#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ +#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ +#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ +#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ +#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ +#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ +#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ +#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ +#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ +#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ +#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ +#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ +#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ +#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ +#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ +#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ +#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ +#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ +#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ + +/* System Control Register Addresses ************************************************/ + +#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) +#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) +#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) +#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) +#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) +#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) +#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) +#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) +#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) +#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) +#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) +#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) +#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) +#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) +#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) +#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) +#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) +#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) +#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) +#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) +#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) +#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) +#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) +#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) +#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) +#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) +#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) +#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) +#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) + +/* System Control Register Bit Definitions ******************************************/ + +/* Device Identification 0 (DID0), offset 0x000 */ + +#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ +#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) +#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ +#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) +#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ +#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) +#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ +#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) + +/* Device Identification 1 (DID1), offset 0x004 */ + +#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ +#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) +#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) +#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ +#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) +#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ +#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) +#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ +#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) +#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ +#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) +#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ +#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) + +/* Device Capabilities 0 (DC0), offset 0x008 */ + +#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ +#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) +#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ +#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) + +/* Device Capabilities 1 (DC1), offset 0x010 */ + +#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ +#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ +#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ +#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ +#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ +#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ +#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ +#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ +#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ +#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) +#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ +#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ +#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) + +/* Device Capabilities 2 (DC2), offset 0x014 */ + +#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ +#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ +#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ +#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ +#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ +#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ +#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ +#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ +#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ +#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ +#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ +#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ + +/* Device Capabilities 3 (DC3), offset 0x018 */ + +#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ +#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ +#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ +#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ +#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ +#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ +#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ +#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ +#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ +#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ +#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ +#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ +#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ +#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ +#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ +#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ +#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ +#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ +#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ +#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ + +/* Device Capabilities 4 (DC4), offset 0x01c */ + +#define SYSCON_DC4_GPIO(n) (1 << (n)) +#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ +#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ +#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ +#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ +#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ +#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ +#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ +#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ +#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ +#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ + +/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ + +#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ + +/* LDO Power Control (LDOPCTL), offset 0x034 */ + +#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ +#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) +# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ +# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ +# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ +# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ +# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ +# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ +# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ +# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ +# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ +# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ +# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ + +/* Software Reset Control 0 (SRCR0), offset 0x040 */ + +#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ +#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ +#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ + +/* Software Reset Control 1 (SRCR1), offset 0x044 */ + +#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ +#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ +#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ +#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ +#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ +#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ +#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ +#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ +#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ +#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ +#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ +#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ + +/* Software Reset Control 2 (SRCR2), offset 0x048 */ + +#define SYSCON_SRCR2_GPIO(n) (1 << (n)) +#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ +#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ +#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ +#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ +#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ +#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ +#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ +#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ +#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ +#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ + +/* Raw Interrupt Status (RIS), offset 0x050 */ + +#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ +#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ + +/* Interrupt Mask Control (IMC), offset 0x054 */ + +#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ +#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ + +/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ + +#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ +#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ + +/* Reset Cause (RESC), offset 0x05C */ + +#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ +#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ +#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ +#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ +#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ + +/* Run-Mode Clock Configuration (RCC), offset 0x060 */ + +#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ +#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ +#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ +#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) +# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ +# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ +#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ +#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) +# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ +# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ +# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ +# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ +# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ +# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ +# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ +# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ +# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ +# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ +# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ +# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ +# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B96 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif +#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ +#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ +#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ +#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ +#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) +# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) +#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ + +/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ + +#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ +#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) +#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ +#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) + +/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ + +#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ +#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) +# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ +# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ +# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ +#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ +#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ +#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ +#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) +# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) +#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ + +/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ + +#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) +#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ + +#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ + +#define SYSCON_RCGC2_GPIO(n) (1 << (n)) +#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ + +#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) +#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ + +#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ + +#define SYSCON_SCGC2_GPIO(n) (1 << (n)) +#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ + +#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) +#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ + +#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ + +#define SYSCON_DCGC2_GPIO(n) (1 << (n)) +#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ + +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) +#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ +#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_timer.h b/nuttx/arch/arm/src/lm/chip/lm_timer.h new file mode 100644 index 000000000..f2824ce1f --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_timer.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_timer.h + * + * Copyright (C) 2012 Max Nekludov. All rights reserved. + * Author: Max Nekludov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Timer register offsets ***********************************************************/ + +#define TIMER_GPTMCFG_OFFSET 0x000 +#define TIMER_GPTMTAMR_OFFSET 0x004 +#define TIMER_GPTMCTL_OFFSET 0x00C +#define TIMER_GPTMIMR_OFFSET 0x018 +#define TIMER_GPTMRIS_OFFSET 0x01C +#define TIMER_GPTMICR_OFFSET 0x024 +#define TIMER_GPTMTAILR_OFFSET 0x028 +#define TIMER_GPTMTAR_OFFSET 0x048 + +/* SSI register addresses ***********************************************************/ + +#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) + +#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) +#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) +#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) +#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) +#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) +#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) +#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) +#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) + +/* SSI register bit defitiions ******************************************************/ + +/* GPTM Configuration (GPTMCFG), offset 0x000 */ + +#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ +#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) +#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ +#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ +#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ + +/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ + +#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ +#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) +#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ +#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ +#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ +#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ +#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) +#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ +#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ +#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ +#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) +#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ +#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ +#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ +#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) +#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ +#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ +#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ +#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) + +/* GPTM Control (GPTMCTL), offset 0x00C */ + +#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ +#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) +#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ +#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) + +/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ + +#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ +#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) + +/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ + +#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ +#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) + +/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ + +#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ +#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_uart.h b/nuttx/arch/arm/src/lm/chip/lm_uart.h new file mode 100644 index 000000000..9a03ff063 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_uart.h @@ -0,0 +1,347 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_uart.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* UART register offsets ************************************************************/ + +#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ +#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ +#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ +#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ +#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ +#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ +#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ +#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ +#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ +#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ +#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ +#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ +#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ +#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ +#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ +#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ +#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ +#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ +#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ +#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ +#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ +#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ +#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ +#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ +#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ +#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ + +/* UART register addresses **********************************************************/ + +#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) + +#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) +#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) +#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) +#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) +#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) +#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) +#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) +#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) +#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) +#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) +#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) +#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) + +/* UART register bit settings *******************************************************/ + +/* UART Data (DR), offset 0x000 */ + +#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ +#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) +#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ +#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ +#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ +#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ + +/* UART Receive Status (RSR), offset 0x004 */ + +#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ +#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ +#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ +#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ + +/* UART Error Clear (ECR), offset 0x004 */ +/* Writing any value to this register clears pending error indications */ + +/* UART Flag (FR), offset 0x018 */ + +#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ +#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ +#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ +#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ +#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ + +/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ + +#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ + +/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ + +#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ + +/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ + +#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ + +/* Register 7: UART Line Control (LCRH), offset 0x02C */ + +#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ +#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ +#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ +#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ +#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ +#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ +#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) +# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ +# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ +# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ +# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ +#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ + +/* UART Control (CTL), offset 0x030 */ + +#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ +#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ +#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ +#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ +#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ +#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ + +/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ + +#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ +#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) +# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ +#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ +#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) +# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ + +/* UART Interrupt Mask (IM), offset 0x038 */ + +#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ +#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ +#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ +#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ +#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ +#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ +#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ + + +/* UART Raw Interrupt Status (RIS), offset 0x03c */ + +#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ +#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ +#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ +#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ +#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ +#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ +#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ + +/* UART Masked Interrupt Status (MIS), offset 0x040 */ + +#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ +#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ +#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ +#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ +#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ +#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ +#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ + +/* UART Interrupt Clear (ICR), offset 0x044 */ + +#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ +#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ +#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ +#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ +#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ +#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ +#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear + */ + +/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ + +#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ + +#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ + +#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ + +#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ + +#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ + +#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ + +#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ + +#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ + +#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ + +/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ + +#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ + +/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ + +#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ + +/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ + +#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c deleted file mode 100644 index a84dc59dd..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c +++ /dev/null @@ -1,167 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_dumpgpio.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "up_arch.h" - -#include "chip.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* NOTE: this is duplicated in lm3s_gpio.c */ - -#ifdef LM3S_GPIOH_BASE -static const uint32_t g_gpiobase[8] = -{ - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, -}; - -static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#else -static const uint32_t g_gpiobase[8] = -{ - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, -}; - -static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static inline uint32_t lm3s_gpiobaseaddress(int port) -{ - return g_gpiobase[port & 7]; -} - -/**************************************************************************** - * Name: lm3s_gpioport - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static inline uint8_t lm3s_gpioport(int port) -{ - return g_portchar[port & 7]; -} - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -int lm3s_dumpgpio(uint32_t pinset, const char *msg) -{ - irqstate_t flags; - unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - uint32_t base; - uint32_t rcgc2; - bool enabled; - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - DEBUGASSERT(base != 0); - - /* The following requires exclusive access to the GPIO registers */ - - flags = irqsave(); - rcgc2 = getreg32(LM3S_SYSCON_RCGC2); - enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); - - lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", - lm3s_gpioport(port), pinset, base, msg); - lldbg(" RCGC2: %08x (%s)\n", - rcgc2, enabled ? "enabled" : "disabled" ); - - /* Don't bother with the rest unless the port is enabled */ - - if (enabled) - { - lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", - getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), - getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); - lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", - getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), - getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); - lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", - getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), - getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), - getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), - getreg32(base + LM3S_GPIO_SLR_OFFSET)); - } - irqrestore(flags); - return OK; -} diff --git a/nuttx/arch/arm/src/lm/lm3s_ethernet.c b/nuttx/arch/arm/src/lm/lm3s_ethernet.c deleted file mode 100644 index f6edab5ae..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_ethernet.c +++ /dev/null @@ -1,1472 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_ethernet.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET) - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "chip.h" -#include "up_arch.h" - -#include "lm_gpio.h" -#include "lm_ethernet.h" -#include "chip/lm_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */ - -#ifdef CONFIG_LM3S_ETHHDUPLEX -# define LM3S_DUPLEX_SETBITS 0 -# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX -#else -# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX -# define LM3S_DUPLEX_CLRBITS 0 -#endif - -/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */ - -#ifdef CONFIG_LM3S_ETHNOAUTOCRC -# define LM3S_CRC_SETBITS 0 -# define LM3S_CRC_CLRBITS MAC_TCTL_CRC -#else -# define LM3S_CRC_SETBITS MAC_TCTL_CRC -# define LM3S_CRC_CLRBITS 0 -#endif - -/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */ - -#ifdef CONFIG_LM3S_ETHNOPAD -# define LM3S_PADEN_SETBITS 0 -# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN -#else -# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN -# define LM3S_PADEN_CLRBITS 0 -#endif - -#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) -#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) - -/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */ - -#ifdef CONFIG_LM3S_MULTICAST -# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL -# define LM3S_AMUL_CLRBITS 0 -#else -# define LM3S_AMUL_SETBITS 0 -# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL -#endif - -/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */ - -#ifdef CONFIG_LM3S_PROMISCUOUS -# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS -# define LM3S_PRMS_CLRBITS 0 -#else -# define LM3S_PRMS_SETBITS 0 -# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS -#endif - -/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */ - -#ifdef CONFIG_LM3S_BADCRC -# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC -# define LM3S_BADCRC_CLRBITS 0 -#else -# define LM3S_BADCRC_SETBITS 0 -# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC -#endif - -#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) -#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) - -/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */ - -#ifdef CONFIG_LM3S_DUMPPACKET -# define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) -#else -# define lm3s_dumppacket(m,a,n) -#endif - -/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ - -#define LM3S_WDDELAY (1*CLK_TCK) -#define LM3S_POLLHSEC (1*2) - -/* TX timeout = 1 minute */ - -#define LM3S_TXTIMEOUT (60*CLK_TCK) - -/* This is a helper pointer for accessing the contents of the Ethernet header */ - -#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf) - -#define LM32S_MAX_MDCCLK 2500000 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* EMAC statistics (debug only) */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) -struct lm3s_statistics_s -{ - uint32_t rx_int; /* Number of Rx interrupts received */ - uint32_t rx_packets; /* Number of packets received (sum of the following): */ - uint32_t rx_ip; /* Number of Rx IP packets received */ - uint32_t rx_arp; /* Number of Rx ARP packets received */ - uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */ - uint32_t rx_pktsize; /* Number of dropped, too small or too big */ - uint32_t rx_errors; /* Number of Rx errors (reception error) */ - uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */ - uint32_t tx_int; /* Number of Tx interrupts received */ - uint32_t tx_packets; /* Number of Tx packets queued */ - uint32_t tx_errors; /* Number of Tx errors (transmission error)*/ - uint32_t tx_timeouts; /* Number of Tx timeout errors */ -}; -# define EMAC_STAT(priv,name) priv->ld_stat.name++ -#else -# define EMAC_STAT(priv,name) -#endif - -/* The lm3s_driver_s encapsulates all state information for a single hardware - * interface - */ - -struct lm3s_driver_s -{ - /* The following fields would only be necessary on chips that support - * multiple Ethernet controllers. - */ - -#if LM3S_NETHCONTROLLERS > 1 - uint32_t ld_base; /* Ethernet controller base address */ - int ld_irq; /* Ethernet controller IRQ */ -#endif - - bool ld_bifup; /* true:ifup false:ifdown */ - WDOG_ID ld_txpoll; /* TX poll timer */ - WDOG_ID ld_txtimeout; /* TX timeout timer */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) - struct lm3s_statistics_s ld_stat; -#endif - - /* This holds the information visible to uIP/NuttX */ - - struct uip_driver_s ld_dev; /* Interface understood by uIP */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Miscellaneous low level helpers */ - -#if LM3S_NETHCONTROLLERS > 1 -static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); -static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); -#else -static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); -static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); -#endif -static void lm3s_ethreset(struct lm3s_driver_s *priv); -#if 0 /* Not used */ -static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value); -#endif -static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr); - -/* Common TX logic */ - -static int lm3s_transmit(struct lm3s_driver_s *priv); -static int lm3s_uiptxpoll(struct uip_driver_s *dev); - -/* Interrupt handling */ - -static void lm3s_receive(struct lm3s_driver_s *priv); -static void lm3s_txdone(struct lm3s_driver_s *priv); -static int lm3s_interrupt(int irq, FAR void *context); - -/* Watchdog timer expirations */ - -static void lm3s_polltimer(int argc, uint32_t arg, ...); -static void lm3s_txtimeout(int argc, uint32_t arg, ...); - -/* NuttX callback functions */ - -static int lm3s_ifup(struct uip_driver_s *dev); -static int lm3s_ifdown(struct uip_driver_s *dev); -static int lm3s_txavail(struct uip_driver_s *dev); -#ifdef CONFIG_NET_IGMP -static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); -static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_ethin - * - * Description: - * Read a register from the Ethernet module - * - * Parameters: - * priv - Reference to the driver state structure - * offset - Byte offset of the register from the ethernet base address - * - * Returned Value: - * Register value - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) -{ - return getreg32(priv->ld_base + offset); -} -#else -static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) -{ - return getreg32(LM3S_ETHCON_BASE + offset); -} -#endif - -/**************************************************************************** - * Function: lm3s_ethout - * - * Description: - * Write a register to the Ethernet module - * - * Parameters: - * priv - Reference to the driver state structure - * offset - Byte offset of the register from the ethernet base address - * value - The value to write the Ethernet register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) -{ - putreg32(value, priv->ld_base + offset); -} -#else -static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) -{ - putreg32(value, LM3S_ETHCON_BASE + offset); -} -#endif - -/**************************************************************************** - * Function: lm3s_ethreset - * - * Description: - * Configure and reset the Ethernet module, leaving it in a disabled state. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_ethreset(struct lm3s_driver_s *priv) -{ - irqstate_t flags; - uint32_t regval; - -#if LM3S_NETHCONTROLLERS > 1 -# error "If multiple interfaces are supported, this function would have to be redesigned" -#endif - - /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ - - flags = irqsave(); - regval = getreg32(LM3S_SYSCON_RCGC2); - regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); - putreg32(regval, LM3S_SYSCON_RCGC2); - nllvdbg("RCGC2: %08x\n", regval); - - /* Put the Ethernet controller into the reset state */ - - regval = getreg32(LM3S_SYSCON_SRCR2); - regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); - - /* Wait just a bit. This is a much longer delay than necessary */ - - up_mdelay(2); - - /* Then take the Ethernet controller out of the reset state */ - - regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); - nllvdbg("SRCR2: %08x\n", regval); - - /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ - - up_mdelay(2); - - /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */ - -#ifdef CONFIG_LM3S_ETHLEDS - /* Configure the pins for the peripheral function */ - - lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); - lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); -#endif - - /* Disable all Ethernet controller interrupts */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval &= ~MAC_IM_ALLINTS; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Clear any pending interrupts (shouldn't be any) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); - irqrestore(flags); -} - -/**************************************************************************** - * Function: lm3s_phywrite - * - * Description: - * Write a 16-bit word to a PHY register - * - * Parameters: - * priv - Reference to the driver state structure - * regaddr - Address of the PHY register to write - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value) -{ - /* Wait for any MII transactions in progress to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Set up the data to be written */ - - DEBUGASSERT(value < MAC_MTXD_MASK); - lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); - - /* Set up the PHY register address and start the write operation */ - - regaddr <<= MAC_MCTL_REGADR_SHIFT; - DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); - - /* Wait for the write transaction to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); -} -#endif - -/**************************************************************************** - * Function: lm3s_phyread - * - * Description: - * Write a 16-bit word to a PHY register - * - * Parameters: - * priv - Reference to the driver state structure - * regaddr - Address of the PHY register to write - * value - The value to write to the register - * - * Returned Value: - * None - * - ****************************************************************************/ - -static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr) -{ - /* Wait for any MII transactions in progress to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Set up the PHY register address and start the read operation */ - - regaddr <<= MAC_MCTL_REGADR_SHIFT; - DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); - - /* Wait for the write transaction to complete */ - - while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); - - /* Read and return the PHY data */ - - return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); -} - -/**************************************************************************** - * Function: lm3s_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -static int lm3s_transmit(struct lm3s_driver_s *priv) -{ - irqstate_t flags; - uint32_t regval; - uint8_t *dbuf; - int pktlen; - int bytesleft; - int ret = -EBUSY; - - /* Verify that the hardware is ready to send another packet */ - - flags = irqsave(); - if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* Increment statistics */ - - EMAC_STAT(priv, tx_packets); - lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); - - /* Transfer the packet into the Tx FIFO. The LS 16-bits of the first - * 32-bit word written to the Tx FIFO contains the Ethernet payload - * data length. That is the full length of the message (d_len) minus - * the size of the Ethernet header (14). - */ - - pktlen = priv->ld_dev.d_len; - nllvdbg("Sending packet, pktlen: %d\n", pktlen); - DEBUGASSERT(pktlen > UIP_LLH_LEN); - - dbuf = priv->ld_dev.d_buf; - regval = (uint32_t)(pktlen - 14); - regval |= ((uint32_t)(*dbuf++) << 16); - regval |= ((uint32_t)(*dbuf++) << 24); - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); - - /* Write all of the whole, 32-bit values in the middle of the packet */ - - for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4) - { - /* Transfer a whole word from the user buffer. Note, the user - * buffer may be un-aligned. - */ - - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); - } - - /* Write the last, partial word in the FIFO */ - - if (bytesleft > 0) - { - /* Write the last word */ - - regval = 0; - switch (bytesleft) - { - case 0: - default: - break; - - case 3: - regval |= ((uint32_t)dbuf[2] << 16); - case 2: - regval |= ((uint32_t)dbuf[1] << 8); - case 1: - regval |= (uint32_t)dbuf[0]; - break; - } - lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); - } - - /* Activate the transmitter */ - - lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); - - /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - - (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv); - ret = OK; - } - - irqrestore(flags); - return ret; -} - -/**************************************************************************** - * Function: lm3s_uiptxpoll - * - * Description: - * The transmitter is available, check if uIP has any outgoing packets ready - * to send. This is a callback from uip_poll(). uip_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_uiptxpoll(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - int ret = OK; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len); - if (priv->ld_dev.d_len > 0) - { - /* Send the packet. lm3s_transmit() will return zero if the - * packet was successfully handled. - */ - - DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - uip_arp_out(&priv->ld_dev); - ret = lm3s_transmit(priv); - } - - /* If zero is returned, the polling will continue until all connections have - * been examined. - */ - - return ret; -} - -/**************************************************************************** - * Function: lm3s_receive - * - * Description: - * An interrupt was received indicating the availability of a new RX packet - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_receive(struct lm3s_driver_s *priv) -{ - uint32_t regval; - uint8_t *dbuf; - int pktlen; - int bytesleft; - - /* Loop while there are incoming packets to be processed */ - - while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) - { - /* Update statistics */ - - EMAC_STAT(priv, rx_packets); - - /* Copy the data data from the hardware to priv->ld_dev.d_buf. Set - * amount of data in priv->ld_dev.d_len - */ - - dbuf = priv->ld_dev.d_buf; - - /* The packet frame length begins in the LS 16-bits of the first - * word from the FIFO followed by the Ethernet header beginning - * in the MS 16-bits of the first word. - * - * Pick off the packet length from the first word. This packet length - * includes the len/type field (size 2) and the FCS (size 4). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - pktlen = (int)(regval & 0x0000ffff); - nllvdbg("Receiving packet, pktlen: %d\n", pktlen); - - /* Check if the pktlen is valid. It should be large enough to hold - * an Ethernet header and small enough to fit entirely in the I/O - * buffer. Six is subtracted to acount for the 2-byte length/type - * and 4 byte FCS that are not copied into the uIP packet. - */ - - if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6)) - { - int wordlen; - - /* We will have to drop this packet */ - - nlldbg("Bad packet size dropped (%d)\n", pktlen); - EMAC_STAT(priv, rx_pktsize); - - /* The number of bytes and words left to read is pktlen - 4 (including, - * the final, possibly partial word) because we've already read 4 bytes. - */ - - wordlen = (pktlen - 1) >> 2; - - /* Read and discard the remaining words in the FIFO */ - - while (wordlen--) - { - (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - } - - /* Check for another packet */ - - continue; - } - - /* Save the first two bytes from the first word */ - - *dbuf++ = (uint8_t)((regval >> 16) & 0xff); - *dbuf++ = (uint8_t)((regval >> 24) & 0xff); - - /* Read all of the whole, 32-bit values in the middle of the packet. - * We've already read the length (2 bytes) plus the first two bytes - * of data. - */ - - for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4) - { - /* Transfer a whole word to the user buffer. Note, the user - * buffer may be un-aligned. - */ - - *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - } - - /* Handle the last, partial word in the FIFO (0-3 bytes) and discard - * the 4-byte FCS. - */ - - for (; bytesleft > 0; bytesleft -= 4) - { - /* Read the last word. And transfer all but the last four - * bytes of the FCS into the user buffer. - */ - - regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); - switch (bytesleft) - { - default: - break; - - case 7: - dbuf[2] = (regval >> 16) & 0xff; - case 6: - dbuf[1] = (regval >> 8) & 0xff; - case 5: - dbuf[0] = regval & 0xff; - break; - } - } - - /* Pass the packet length to uIP MINUS 2 bytes for the length and - * 4 bytes for the FCS. - */ - - priv->ld_dev.d_len = pktlen - 6; - lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); - - /* We only accept IP packets of the configured type and ARP packets */ - -#ifdef CONFIG_NET_IPv6 - if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6)) -#else - if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP)) -#endif - { - nllvdbg("IP packet received (%02x)\n", ETHBUF->type); - EMAC_STAT(priv, rx_ip); - - uip_arp_ipin(&priv->ld_dev); - uip_input(&priv->ld_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->ld_dev.d_len > 0) - { - uip_arp_out(&priv->ld_dev); - lm3s_transmit(priv); - } - } - else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP)) - { - nllvdbg("ARP packet received (%02x)\n", ETHBUF->type); - EMAC_STAT(priv, rx_arp); - - uip_arp_arpin(&priv->ld_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->ld_dev.d_len > 0) - { - lm3s_transmit(priv); - } - } -#ifdef CONFIG_DEBUG - else - { - nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); - EMAC_STAT(priv, rx_dropped); - } -#endif - } -} - -/**************************************************************************** - * Function: lm3s_txdone - * - * Description: - * An interrupt was received indicating that the last TX packet(s) is done - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_txdone(struct lm3s_driver_s *priv) -{ - /* Cancel the TX timeout */ - - wd_cancel(priv->ld_txtimeout); - - /* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. Since - * we get here because of of TXEMP which indicates that the packet was - * transmitted and that the TX FIFO is empty, NEWTX should always be zero - * at this point. - */ - - DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - - /* Then poll uIP for new XMIT data */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); -} - -/**************************************************************************** - * Function: lm3s_interrupt - * - * Description: - * Hardware interrupt handler - * - * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) - * - * Returned Value: - * OK on success - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_interrupt(int irq, FAR void *context) -{ - register struct lm3s_driver_s *priv; - uint32_t ris; - -#if LM3S_NETHCONTROLLERS > 1 -# error "A mechanism to associate and interface with an IRQ is needed" -#else - priv = &g_lm3sdev[0]; -#endif - - /* Read the raw interrupt status register */ - - ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - - /* Clear all pending interrupts */ - - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); - - /* Check for errors */ - -#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) - if ((ris & MAC_RIS_TXER) != 0) - { - EMAC_STAT(priv, tx_errors); /* Number of Tx errors */ - } - - if ((ris & MAC_RIS_FOV) != 0) - { - EMAC_STAT(priv, rx_ovrerrors); /* Number of Rx FIFO overrun errors */ - } - - if ((ris & MAC_RIS_RXER) != 0) - { - EMAC_STAT(priv, rx_errors); /* Number of Rx errors */ - } -#endif - - /* Handle (unmasked) interrupts according to status bit settings */ - - ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - - /* Is this an Rx interrupt (meaning that a packet has been received)? */ - - if ((ris & MAC_RIS_RXINT) != 0) - { - /* Handle the incoming packet */ - - EMAC_STAT(priv, rx_int); - lm3s_receive(priv); - } - - /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ - - if ((ris & MAC_RIS_TXEMP) != 0) - { - /* Handle the complete of the transmission */ - - EMAC_STAT(priv, tx_int); - lm3s_txdone(priv); - } - - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if - * there are no pending transmissions). - */ - - return OK; -} - -/**************************************************************************** - * Function: lm3s_txtimeout - * - * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_txtimeout(int argc, uint32_t arg, ...) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; - - /* Increment statistics */ - - nlldbg("Tx timeout\n"); - EMAC_STAT(priv, tx_timeouts); - - /* Then reset the hardware */ - - DEBUGASSERT(priv->ld_bifup); - lm3s_ifdown(&priv->ld_dev); - lm3s_ifup(&priv->ld_dev); - - /* Then poll uIP for new XMIT data */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); -} - -/**************************************************************************** - * Function: lm3s_polltimer - * - * Description: - * Periodic timer handler. Called from the timer interrupt handler. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static void lm3s_polltimer(int argc, uint32_t arg, ...) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; - - /* Check if we can send another Tx packet now. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. - * - * NOTE: This can cause missing poll cycles and, hence, some timing - * inaccuracies. - */ - - if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* If so, update TCP timing states and poll uIP for new XMIT data */ - - (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg); - } -} - -/**************************************************************************** - * Function: lm3s_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_ifup(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - uint32_t regval; - uint32_t div; - uint16_t phyreg; - - nlldbg("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); - - /* Enable and reset the Ethernet controller */ - - flags = irqsave(); - lm3s_ethreset(priv); - - /* Set the management clock divider register for access to the PHY - * register set. The MDC clock is divided down from the system clock per: - * - * MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1)) - * div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1 - * - * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will - * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded. - */ - - div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; - lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div); - nllvdbg("MDV: %08x\n", div); - - /* Then configure the Ethernet Controller for normal operation - * - * Setup the transmit control register (Full duplex, TX CRC Auto Generation, - * TX Padding Enabled). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); - regval &= ~LM3S_TCTCL_CLRBITS; - regval |= LM3S_TCTCL_SETBITS; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - nllvdbg("TCTL: %08x\n", regval); - - /* Setup the receive control register (Disable multicast frames, disable - * promiscuous mode, disable bad CRC rejection). - */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~LM3S_RCTCL_CLRBITS; - regval |= LM3S_RCTCL_SETBITS; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - nllvdbg("RCTL: %08x\n", regval); - - /* Setup the time stamp configuration register */ - -#ifdef LM3S_ETHTS - regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); -#ifdef CONFIG_LM3S_TIMESTAMP - regval |= MAC_TS_EN; -#else - regval &= ~(MAC_TS_EN); -#endif - lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval); - nllvdbg("TS: %08x\n", regval); -#endif - - /* Wait for the link to come up. This following is not very conservative - * of system resources -- it really should wait gracefully on a semaphore - * and the interrupt handler should post the semaphore when LINKSTATUS is - * set - */ - - nlldbg("Waiting for link\n"); - do - { - phyreg = lm3s_phyread(priv, MII_MSR); - } - while ((phyreg & MII_MSR_LINKSTATUS) == 0); - nlldbg("Link established\n"); - - /* Reset the receive FIFO */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet receiver */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RXEN; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet transmitter */ - - regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); - regval |= MAC_TCTL_TXEN; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - - /* Reset the receive FIFO (again) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Enable the Ethernet interrupt */ - -#if LM3S_NETHCONTROLLERS > 1 - up_enable_irq(priv->irq); -#else - up_enable_irq(LM3S_IRQ_ETHCON); -#endif - - /* Enable the Ethernet RX packet receipt interrupt */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval |= MAC_IM_RXINTM; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Program the hardware with it's MAC address (for filtering) */ - - regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; - lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); - - regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | - (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; - lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); - - /* Set and activate a timer process */ - - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv); - - priv->ld_bifup = true; - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_ifdown - * - * Description: - * NuttX Callback: Stop the interface. The only way to restore normal - * behavior is to call lm3s_ifup(). - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int lm3s_ifdown(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - uint32_t regval; - - nlldbg("Taking down: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); - - /* Cancel the TX poll timer and TX timeout timers */ - - flags = irqsave(); - wd_cancel(priv->ld_txpoll); - wd_cancel(priv->ld_txtimeout); - - /* Disable the Ethernet interrupt */ - -#if LM3S_NETHCONTROLLERS > 1 - up_disable_irq(priv->irq); -#else - up_disable_irq(LM3S_IRQ_ETHCON); -#endif - - /* Disable all Ethernet controller interrupt sources */ - - regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); - regval &= ~MAC_IM_ALLINTS; - lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); - - /* Reset the receive FIFO */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Disable the Ethernet receiver */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~MAC_RCTL_RXEN; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Disable the Ethernet transmitter */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~MAC_TCTL_TXEN; - lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); - - /* Reset the receive FIFO (again) */ - - regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval |= MAC_RCTL_RSTFIFO; - lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); - - /* Clear any pending interrupts */ - - regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); - - /* The interface is now DOWN */ - - priv->ld_bifup = false; - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int lm3s_txavail(struct uip_driver_s *dev) -{ - struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; - irqstate_t flags; - - /* Ignore the notification if the interface is not yet up or if the Tx FIFO - * hardware is not available at this time. The NEWTX bit initiates an - * Ethernet transmission once the packet has been placed in the TX FIFO. - * This bit is cleared once the transmission has been completed. When the - * transmission completes, lm3s_txdone() will be called and the Tx polling - * will occur at that time. - */ - - flags = irqsave(); - if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) - { - /* If the interface is up and we can use the Tx FIFO, then poll uIP - * for new Tx data - */ - - (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); - } - - irqrestore(flags); - return OK; -} - -/**************************************************************************** - * Function: lm3s_addmac - * - * Description: - * NuttX Callback: Add the specified MAC address to the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - -#warning "Multicast MAC support not implemented" - return OK; -} -#endif - -/**************************************************************************** - * Function: lm3s_rmmac - * - * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - -#warning "Multicast MAC support not implemented" - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: lm3s_ethinitialize - * - * Description: - * Initialize the Ethernet driver for one interface - * - * Parameters: - * None - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -#if LM3S_NETHCONTROLLERS > 1 -int lm3s_ethinitialize(int intf) -#else -static inline int lm3s_ethinitialize(int intf) -#endif -{ - struct lm3s_driver_s *priv = &g_lm3sdev[intf]; - int ret; - - /* Check if the Ethernet module is present */ - - ndbg("Setting up eth%d\n", intf); - -#if LM3S_NETHCONTROLLERS > 1 -# error "This debug check only works with one interface" -#else - DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); -#endif - DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); - - /* Initialize the driver structure */ - - memset(priv, 0, sizeof(struct lm3s_driver_s)); - priv->ld_dev.d_ifup = lm3s_ifup; /* I/F down callback */ - priv->ld_dev.d_ifdown = lm3s_ifdown; /* I/F up (new IP address) callback */ - priv->ld_dev.d_txavail = lm3s_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_IGMP - priv->ld_dev.d_addmac = lm3s_addmac; /* Add multicast MAC address */ - priv->ld_dev.d_rmmac = lm3s_rmmac; /* Remove multicast MAC address */ -#endif - priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */ - - /* Create a watchdog for timing polling for and timing of transmisstions */ - -#if LM3S_NETHCONTROLLERS > 1 -# error "A mechanism to associate base address an IRQ with an interface is needed" - priv->ld_base = ??; /* Ethernet controller base address */ - priv->ld_irq = ??; /* Ethernet controller IRQ number */ -#endif - priv->ld_txpoll = wd_create(); /* Create periodic poll timer */ - priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */ - - /* If the board can provide us with a MAC address, get the address - * from the board now. The MAC will not be applied until lm3s_ifup() - * is caleld (and the MAC can be overwritten with a netdev ioctl call). - */ - -#ifdef CONFIG_LM3S_BOARDMAC - lm3s_ethernetmac(&priv->ld_dev.d_mac); -#endif - - /* Perform minimal, one-time initialization -- just reset the controller and - * leave it disabled. The Ethernet controller will be reset and properly - * re-initialized each time lm3s_ifup() is called. - */ - - lm3s_ethreset(priv); - lm3s_ifdown(&priv->ld_dev); - - /* Attach the IRQ to the driver */ - -#if LM3S_NETHCONTROLLERS > 1 - ret = irq_attach(priv->irq, lm3s_interrupt); -#else - ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt); -#endif - if (ret != 0) - { - /* We could not attach the ISR to the IRQ */ - - return -EAGAIN; - } - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - (void)netdev_register(&priv->ld_dev); - return OK; -} - - -/************************************************************************************ - * Name: up_netinitialize - * - * Description: - * Initialize the first network interface. If there are more than one interface - * in the chip, then board-specific logic will have to provide this function to - * determine which, if any, Ethernet controllers should be initialized. - * - ************************************************************************************/ - -#if LM3S_NETHCONTROLLERS == 1 -void up_netinitialize(void) -{ - (void)lm3s_ethinitialize(0); -} -#endif - -#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */ - diff --git a/nuttx/arch/arm/src/lm/lm3s_gpio.c b/nuttx/arch/arm/src/lm/lm3s_gpio.c deleted file mode 100644 index 48cbefabf..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_gpio.c +++ /dev/null @@ -1,854 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_gpio.c - * arch/arm/src/chip/lm3s_gpio.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "os_internal.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions are part of the implementation of the GPIO pad - * configuration of Table 9-1 in the LM3S6918 data sheet. - */ - -#define AFSEL_SHIFT 5 -#define AFSEL_1 (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */ -#define AFSEL_0 0 -#define AFSEL_X 0 - -#define DIR_SHIFT 4 -#define DIR_1 (1 << DIR_SHIFT) /* Set/clear bit in GPIO DIR register */ -#define DIR_0 0 -#define DIR_X 0 - -#define ODR_SHIFT 3 -#define ODR_1 (1 << ODR_SHIFT) /* Set/clear bit in GPIO ODR register */ -#define ODR_0 0 -#define ODR_X 0 - -#define DEN_SHIFT 2 -#define DEN_1 (1 << DEN_SHIFT) /* Set/clear bit in GPIO DEN register */ -#define DEN_0 0 -#define DEN_X 0 - -#define PUR_SHIFT 1 -#define PUR_1 (1 << PUR_SHIFT) /* Set/clear bit in GPIO PUR register */ -#define PUR_0 0 -#define PUR_X 0 - -#define PDR_SHIFT 0 -#define PDR_1 (1 << PDR_SHIFT) /* Set/clear bit in GPIO PDR register */ -#define PDR_0 0 -#define PDR_X 0 - -#define GPIO_INPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_INPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_OUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_OUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ODINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_ODINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ODOUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_ODOUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_PFODIO_SETBITS (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X) -#define GPIO_PFODIO_CLRBITS (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_PFIO_SETBITS (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_PFIO_CLRBITS (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X) - -#define GPIO_ANINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0) -#define GPIO_ANINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1) - -#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) -#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_func_s -{ - uint8_t setbits; /* A set of GPIO register bits to set */ - uint8_t clrbits; /* A set of GPIO register bits to clear */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_func_s g_funcbits[] = -{ - {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ - {GPIO_OUTPUT_SETBITS, GPIO_OUTPUT_CLRBITS}, /* GPIO_FUNC_OUTPUT */ - {GPIO_ODINPUT_SETBITS, GPIO_ODINPUT_CLRBITS}, /* GPIO_FUNC_ODINPUT */ - {GPIO_ODOUTPUT_SETBITS, GPIO_ODOUTPUT_CLRBITS}, /* GPIO_FUNC_ODOUTPUT */ - {GPIO_PFODIO_SETBITS, GPIO_PFODIO_CLRBITS}, /* GPIO_FUNC_PFODIO */ - {GPIO_PFIO_SETBITS, GPIO_PFIO_CLRBITS}, /* GPIO_FUNC_PFIO */ - {GPIO_ANINPUT_SETBITS, GPIO_ANINPUT_CLRBITS}, /* GPIO_FUNC_ANINPUT */ - {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ -}; - -static const uint32_t g_gpiobase[LM3S_NPORTS] = -{ - /* All support LM3S parts have at least 7 ports, GPIOA-G */ - - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, - - /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ - -#if LM3S_NPORTS > 7 - LM3S_GPIOH_BASE, -#endif - - /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ - -#if LM3S_NPORTS > 8 - LM3S_GPIOJ_BASE, -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. - * - ****************************************************************************/ - -static uint32_t lm3s_gpiobaseaddress(unsigned int port) -{ - uint32_t gpiobase = 0; - if (port < LM3S_NPORTS) - { - gpiobase = g_gpiobase[port]; - } - return gpiobase; -} - -/**************************************************************************** - * Name: lm3s_gpiofunc - * - * Description: - * Configure GPIO registers for a specific function - * - ****************************************************************************/ - -static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func) -{ - uint32_t setbit; - uint32_t clrbit; - uint32_t regval; - - /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain - * control register. Setting a bit in this register enables the open drain - * configuration of the corresponding GPIO pad. When open drain mode is enabled, - * the corresponding bit should also be set in the GPIO Digital Input Enable - * (GPIO DEN) register ... Corresponding bits in the drive strength registers - * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the - * desired rise and fall times. The GPIO acts as an open drain input if the - * corresponding bit in the GPIO DIR register is set to 0; and as an open - * drain output when set to 1." - */ - - setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); - - /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control - * register. When a bit is set to 1, it enables a weak pull-up resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the - * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." - */ - - setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno; - - if (setbit || clrbit) - { - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); - } - - /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control - * register. When a bit is set to 1, it enables a weak pull-down resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears - * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." - */ - - setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno; - - if (setbit || clrbit) - { - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); - } - - /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable - * register. By default, with the exception of the GPIO signals used for JTAG/SWD - * function, all other GPIO signals are configured out of reset to be undriven - * (tristate). Their digital function is disabled; they do not drive a logic - * value on the pin and they do not allow the pin voltage into the GPIO receiver. - * To use the pin in a digital function (either GPIO or alternate function), the - * corresponding GPIODEN bit must be set." - */ - - setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); - - /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data - * direction register. Bits set to 1 in the GPIODIR register configure - * the corresponding pin to be an output, while bits set to 0 configure the - * pins to be inputs. All bits are cleared by a reset, meaning all GPIO - * pins are inputs by default. - */ - - setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); - - /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode - * control select register. Writing a 1 to any bit in this register selects - * the hardware control for the corresponding GPIO line. All bits are cleared - * by a reset, therefore no GPIO line is set to hardware control by default." - * - * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit - * and unlock the GPIO. That is not implemented here. - */ - - setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; - clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; - - regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); - regval &= ~clrbit; - regval |= setbit; - putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); -} - -/**************************************************************************** - * Name: lm3s_gpiopadstrength - * - * Description: - * Set up pad strength and pull-ups - * - ****************************************************************************/ - -static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT; - uint32_t regoffset; - uint32_t regval; - uint32_t slrset; - uint32_t slrclr; - - /* Prepare bits to disable slew */ - - slrset = 0; - slrclr = pin; - - switch (strength) - { - case 0: /* 2mA pad drive strength */ - { - /* "The GPIODR2R register is the 2-mA drive control register. It - * allows for each GPIO signal in the port to be individually configured - * without affecting the other pads. When writing a DRV2 bit for a GPIO - * signal, the corresponding DRV4 bit in the GPIO DR4R register and the - * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR2R_OFFSET; - } - break; - - case 1: /* 4mA pad drive strength */ - { - /* "The GPIODR4R register is the 4-mA drive control register. It allows - * for each GPIO signal in the port to be individually configured without - * affecting the other pads. When writing the DRV4 bit for a GPIO signal, - * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit - * in the GPIO DR8R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR4R_OFFSET; - } - break; - - case 3: /* 8mA Pad drive with slew rate control */ - { - /* "The GPIOSLR register is the slew rate control register. Slew rate - * control is only available when using the 8-mA drive strength option - * via the GPIO 8-mA Drive Select (GPIODR8R) register..." - */ - - slrset = pin; - slrclr = 0; - } - /* Fall through */ - - case 2: /* 8mA pad drive strength (without slew rate control) */ - { - /* "The GPIODR8R register is the 8-mA drive control register. It - * allows for each GPIO signal in the port to be individually configured - * without affecting the other pads. When writing the DRV8 bit for a GPIO - * signal, the corresponding DRV2 bit in the GPIO DR2R register and the - * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." - */ - - regoffset = LM3S_GPIO_DR8R_OFFSET; - } - break; - } - - /* Set the selected pad strength and set/clear optional slew rate control */ - - regval = getreg32(base + regoffset); - regval |= pin; - putreg32(regval, base + regoffset); - - regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); - regval &= slrclr; - regval |= slrset; - putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); -} - -/**************************************************************************** - * Name: lm3s_gpiopadtype - * - * Description: - * Set up pad strength and pull-ups. Some of these values may be over- - * written by lm3s_gpiofunc, depending on the function selection. Others - * are optional for different function selections. - * - ****************************************************************************/ - -static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int padtype = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT; -#if 0 /* always overwritten by lm3s_gpiofunc */ - uint32_t odrset; - uint32_t odrclr; -#endif - uint32_t purset; - uint32_t purclr; - uint32_t pdrset; - uint32_t pdrclr; -#if 0 /* always overwritten by lm3s_gpiofunc */ - uint32_t denset; - uint32_t denclr; -#endif - uint32_t regval; - - /* Assume digital GPIO function, push-pull with no pull-up or pull-down */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = 0; - odrclr = pin; -#endif - purset = 0; - purclr = pin; - pdrset = 0; - pdrclr = pin; -#if 0 /* always overwritten by lm3s_gpiofunc */ - denset = pin; - denclr = 0; -#endif - - switch (padtype) - { - case 0: /* Push-pull */ - default: - { - } - break; - - case 1: /* Push-pull with weak pull-up */ - { - purset = pin; - purclr = 0; - } - break; - case 2: /* Push-pull with weak pull-down */ - { - pdrset = pin; - pdrclr = 0; - } - break; - case 3: /* Open-drain */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - } - break; - case 4: /* Open-drain with weak pull-up */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - purset = pin; - purclr = 0; - } - break; - case 5: /* Open-drain with weak pull-down */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - odrset = pin; - odrclr = 0; -#endif - pdrset = pin; - pdrclr = 0; - } - break; - case 6: /* Analog comparator */ - { -#if 0 /* always overwritten by lm3s_gpiofunc */ - denset = 0; - denclr = pin; -#endif - } - break; - } - - /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain - * control register. Setting a bit in this register enables the open drain - * configuration of the corresponding GPIO pad. When open drain mode is enabled, - * the corresponding bit should also be set in the GPIO Digital Input Enable - * (GPIO DEN) register ... Corresponding bits in the drive strength registers - * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the - * desired rise and fall times. The GPIO acts as an open drain input if the - * corresponding bit in the GPIO DIR register is set to 0; and as an open - * drain output when set to 1." - */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); - regval &= ~odrclr; - regval |= odrset; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); -#endif - - /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control - * register. When a bit is set to 1, it enables a weak pull-up resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the - * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." - */ - - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); - regval &= ~purclr; - regval |= purset; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); - - /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control - * register. When a bit is set to 1, it enables a weak pull-down resistor on the - * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears - * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." - */ - - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); - regval &= ~pdrclr; - regval |= pdrset; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); - - /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable - * register. By default, with the exception of the GPIO signals used for JTAG/SWD - * function, all other GPIO signals are configured out of reset to be undriven - * (tristate). Their digital function is disabled; they do not drive a logic - * value on the pin and they do not allow the pin voltage into the GPIO receiver. - * To use the pin in a digital function (either GPIO or alternate function), the - * corresponding GPIODEN bit must be set." - */ - -#if 0 /* always overwritten by lm3s_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); - regval &= ~denclr; - regval |= denset; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); -#endif -} - -/**************************************************************************** - * Name: lm3s_initoutput - * - * Description: - * Set the GPIO output value - * - ****************************************************************************/ - -static inline void lm3s_initoutput(uint32_t cfgset) -{ - bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO); - lm3s_gpiowrite(cfgset, value); -} - -/**************************************************************************** - * Name: lm3s_interrupt - * - * Description: - * Configure the interrupt pin. - * - ****************************************************************************/ - -static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) -{ - int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; - uint32_t regval; - uint32_t isset; - uint32_t isclr; - uint32_t ibeset; - uint32_t ibeclr; - uint32_t iveset; - uint32_t iveclr; - - /* Mask and clear the GPIO interrupt - * - * "The GPIOIM register is the interrupt mask register. Bits set to High in - * GPIO IM allow the corresponding pins to trigger their individual interrupts - * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering - * on that pin. All bits are cleared by a reset." - */ - - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - - /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit - * in this register clears the corresponding interrupt edge detection logic - * register. Writing a 0 has no effect." - */ - - regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); - regval |= pin; - putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); - - /* Assume rising edge */ - - isset = 0; /* Not level sensed */ - isclr = pin; - ibeset = 0; /* Single edge */ - ibeclr = pin; - iveset = pin; /* Rising edge or high levels*/ - iveclr = 0; - - /* Then handle according to the selected interrupt type */ - - switch (inttype) - { - case 0: /* Interrupt on falling edge */ - { - iveset = 0; /* Falling edge or low levels*/ - iveclr = pin; - } - break; - - case 1: /* Interrupt on rising edge */ - default: - break; - - case 2: /* Interrupt on both edges */ - { - ibeset = pin; /* Both edges */ - ibeclr = 0; - } - break; - - case 3: /* Interrupt on low level */ - { - isset = pin; /* Level sensed */ - isclr = 0; - iveset = 0; /* Falling edge or low levels*/ - iveclr = pin; - } - break; - - case 4: /* Interrupt on high level */ - { - isset = pin; /* Level sensed */ - isclr = 0; - } - break; - } - - /* "The GPIO IS register is the interrupt sense register. Bits set to - * 1 in GPIOIS configure the corresponding pins to detect levels, while - * bits set to 0 configure the pins to detect edges. All bits are cleared - * by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IS_OFFSET); - regval &= isclr; - regval |= isset; - putreg32(regval, base + LM3S_GPIO_IS_OFFSET); - - /* "The GPIO IBE register is the interrupt both-edges register. When the - * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is - * set to detect edges, bits set to High in GPIO IBE configure the - * corresponding pin to detect both rising and falling edges, regardless - * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ... - * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits - * are cleared by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); - regval &= ibeclr; - regval |= ibeset; - putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); - - /* "The GPIOIEV register is the interrupt event register. Bits set to - * High in GPIO IEV configure the corresponding pin to detect rising edges - * or high levels, depending on the corresponding bit value in the GPIO - * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to - * detect falling edges or low levels, depending on the corresponding bit - * value in GPIOIS. All bits are cleared by a reset. - */ - - regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); - regval &= iveclr; - regval |= iveset; - putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ****************************************************************************/ - -int lm3s_configgpio(uint32_t cfgset) -{ - irqstate_t flags; - unsigned int func; - unsigned int port; - unsigned int pinno; - uint32_t pin; - uint32_t base; - uint32_t regval; - - /* Decode the basics */ - - func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT; - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pinno = (cfgset & GPIO_NUMBER_MASK); - pin = (1 <> GPIO_PORT_SHIFT; - pinno = (pinset & GPIO_NUMBER_MASK); - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - - /* "The GPIO DATA register is the data register. In software control mode, - * values written in the GPIO DATA register are transferred onto the GPIO - * port pins if the respective pins have been configured as outputs through - * the GPIO Direction (GPIO DIR) register ... - * - * "In order to write to GPIO DATA, the corresponding bits in the mask, - * resulting from the address bus bits [9:2], must be High. Otherwise, the - * bit values remain unchanged by the write. - * - * "... All bits are cleared by a reset." - */ - - putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); -} - -/**************************************************************************** - * Name: lm3s_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool lm3s_gpioread(uint32_t pinset, bool value) -{ - unsigned int port; - unsigned int pinno; - uint32_t base; - - /* Decode the basics */ - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pinno = (pinset & GPIO_NUMBER_MASK); - - /* Get the base address associated with the GPIO port */ - - base = lm3s_gpiobaseaddress(port); - - /* "... the values read from this register are determined for each bit - * by the mask bit derived from the address used to access the data register, - * bits [9:2]. Bits that are 1 in the address mask cause the corresponding - * bits in GPIODATA to be read, and bits that are 0 in the address mask cause - * the corresponding bits in GPIO DATA to be read as 0, regardless of their - * value. - * - * "A read from GPIO DATA returns the last bit value written if the respective - * pins are configured as outputs, or it returns the value on the - * corresponding input pin when these are configured as inputs. All bits - * are cleared by a reset." - */ - - return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); -} - diff --git a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c deleted file mode 100644 index a54bfe335..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c +++ /dev/null @@ -1,434 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_gpioirq.c - * arch/arm/src/chip/lm3s_gpioirq.c - * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "up_arch.h" -#include "os_internal.h" -#include "irq_internal.h" - -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A table of handlers for each GPIO interrupt */ - -static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; - -/* A table that maps a GPIO group to a GPIO base address. Overly complicated - * because we support disabling interrupt support for arbitrary ports. This - * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h - */ - -static const uint32_t g_gpiobase[] = -{ -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS - LM3S_GPIOA_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS - LM3S_GPIOB_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS - LM3S_GPIOC_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS - LM3S_GPIOD_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS - LM3S_GPIOE_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS - LM3S_GPIOF_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS - LM3S_GPIOG_BASE, -#endif - - /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip - * does not support these higher ports, then they must be disabled in the - * configuration. Otherwise, the following will likely cause compilation - * errors! - */ - -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS - LM3S_GPIOH_BASE, -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS - LM3S_GPIOJ_BASE, -#endif -}; - -#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t)) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_gpiobaseaddress - * - * Input: - * gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS. - * - * Description: - * Given a GPIO enumeration value, return the base address of the - * associated GPIO registers. NOTE that range checking was provided by - * callee - * - ****************************************************************************/ - -static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq) -{ - unsigned int ndx = gpioirq >> 3; - if (ndx < GPIO_NADDRS) - { - return g_gpiobase[ndx]; - } - return 0; -} - -/**************************************************************************** - * Name: lm3s_gpio*handler - * - * Description: - * Handle interrupts on each enabled GPIO port - * - ****************************************************************************/ - -static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context) -{ - uint32_t mis; - int irq; - int pin; - - /* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked - * interrupt status register. Bits read High in GPIO MIS reflect the status - * of input lines triggering an interrupt. Bits read as Low indicate that - * either no interrupt has been generated, or the interrupt is masked." - */ - - mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; - - /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR - * register is the interrupt clear register. Writing a 1 to a bit in this - * register clears the corresponding interrupt edge detection logic register. - * Writing a 0 has no effect." - */ - - putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); - - /* Now process each IRQ pending in the MIS */ - - for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1) - { - if ((mis & 1) != 0) - { - irq = irqbase + pin; - g_gpioirqvector[irq - NR_IRQS](irq, context); - } - } - return OK; -} - -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS -static int lm3s_gpioahandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS -static int lm3s_gpiobhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS -static int lm3s_gpiochandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS -static int lm3s_gpiodhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS -static int lm3s_gpioehandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS -static int lm3s_gpiofhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS -static int lm3s_gpioghandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS -static int lm3s_gpiohhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); -} -#endif - -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS -static int lm3s_gpiojhandler(int irq, FAR void *context) -{ - return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpio_irqinitialize - * - * Description: - * Initialize all vectors to the unexpected interrupt handler - * - ****************************************************************************/ - -int gpio_irqinitialize(void) -{ - int i; - - /* Point all interrupt vectors to the unexpected interrupt */ - - for (i = 0; i < NR_GPIO_IRQS; i++) - { - g_gpioirqvector[i] = irq_unexpected_isr; - } - - /* Then attach each GPIO interrupt handlers and enable corresponding GPIO - * interrupts - */ - -#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS - irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler); - up_enable_irq(LM3S_IRQ_GPIOA); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS - irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler); - up_enable_irq(LM3S_IRQ_GPIOB); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS - irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler); - up_enable_irq(LM3S_IRQ_GPIOC); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS - irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler); - up_enable_irq(LM3S_IRQ_GPIOD); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS - irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler); - up_enable_irq(LM3S_IRQ_GPIOE); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS - irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler); - up_enable_irq(LM3S_IRQ_GPIOF); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS - irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler); - up_enable_irq(LM3S_IRQ_GPIOG); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS - irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler); - up_enable_irq(LM3S_IRQ_GPIOH); -#endif -#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS - irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler); - up_enable_irq(LM3S_IRQ_GPIOJ); -#endif - - return OK; -} - -/**************************************************************************** - * Name: gpio_irqattach - * - * Description: - * Attach in GPIO interrupt to the provide 'isr' - * - ****************************************************************************/ - -int gpio_irqattach(int irq, xcpt_t isr) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - int ret = ERROR; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - flags = irqsave(); - - /* If the new ISR is NULL, then the ISR is being detached. - * In this case, disable the ISR and direct any interrupts - * to the unexpected interrupt handler. - */ - - if (isr == NULL) - { -#ifndef CONFIG_ARCH_NOINTC - gpio_irqdisable(gpioirq); -#endif - isr = irq_unexpected_isr; - } - - /* Save the new ISR in the table. */ - - g_irqvector[gpioirq] = isr; - irqrestore(flags); - ret = OK; - } - return ret; -} - -/**************************************************************************** - * Name: gpio_irqenable - * - * Description: - * Enable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -void gpio_irqenable(int irq) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - uint32_t base; - uint32_t regval; - int pin; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - /* Get the base address of the GPIO module associated with this IRQ */ - - base = lm3s_gpiobaseaddress(gpioirq); - DEBUGASSERT(base != 0); - pin = (1 << (gpioirq & 7)); - - /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt - * mask register. Bits set to High in GPIO IM allow the corresponding - * pins to trigger their individual interrupts and the combined GPIO INTR - * line. Clearing a bit disables interrupt triggering on that pin. All - * bits are cleared by a reset. - */ - - flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval |= pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - irqrestore(flags); - } -} - -/**************************************************************************** - * Name: gpio_irqdisable - * - * Description: - * Disable the GPIO IRQ specified by 'irq' - * - ****************************************************************************/ - -void gpio_irqdisable(int irq) -{ - irqstate_t flags; - int gpioirq = irq - NR_IRQS; - uint32_t base; - uint32_t regval; - int pin; - - if ((unsigned)gpioirq < NR_GPIO_IRQS) - { - /* Get the base address of the GPIO module associated with this IRQ */ - - base = lm3s_gpiobaseaddress(gpioirq); - DEBUGASSERT(base != 0); - pin = (1 << (gpioirq & 7)); - - /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt - * mask register. Bits set to High in GPIO IM allow the corresponding - * pins to trigger their individual interrupts and the combined GPIO INTR - * line. Clearing a bit disables interrupt triggering on that pin. All - * bits are cleared by a reset. - */ - - flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); - regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); - irqrestore(flags); - } -} - diff --git a/nuttx/arch/arm/src/lm/lm3s_irq.c b/nuttx/arch/arm/src/lm/lm3s_irq.c deleted file mode 100644 index 2039d84a8..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_irq.c +++ /dev/null @@ -1,458 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_irq.c - * arch/arm/src/chip/lm3s_irq.c - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nvic.h" -#include "up_arch.h" -#include "os_internal.h" -#include "up_internal.h" - -#include "chip.h" -#include "lm_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Enable NVIC debug features that are probably only desireable during - * bringup - */ - -#undef LM3S_IRQ_DEBUG - -/* Get a 32-bit version of the default priority */ - -#define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ - NVIC_SYSH_PRIORITY_DEFAULT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uint32_t *current_regs; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_dumpnvic - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) -static void lm3s_dumpnvic(const char *msg, int irq) -{ - irqstate_t flags; - - flags = irqsave(); - slldbg("NVIC (%s, irq=%d):\n", msg, irq); - slldbg(" INTCTRL: %08x VECTAB: %08x\n", - getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); -#if 0 - slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", - getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), - getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); -#endif - slldbg(" IRQ ENABLE: %08x %08x\n", - getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); - slldbg(" SYSH_PRIO: %08x %08x %08x\n", - getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), - getreg32(NVIC_SYSH12_15_PRIORITY)); - slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), - getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); - slldbg(" %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), - getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); - slldbg(" %08x %08x %08x %08x\n", - getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), - getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); - irqrestore(flags); -} -#else -# define lm3s_dumpnvic(msg, irq) -#endif - -/**************************************************************************** - * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv, - * lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved - * - * Description: - * Handlers for various execptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG -static int lm3s_nmi(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! NMI received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_busfault(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Bus fault recived\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_usagefault(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Usage fault received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_pendsv(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! PendSV received\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_dbgmonitor(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Debug Monitor receieved\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} - -static int lm3s_reserved(int irq, FAR void *context) -{ - (void)irqsave(); - dbg("PANIC!!! Reserved interrupt\n"); - PANIC(OSERR_UNEXPECTEDISR); - return 0; -} -#endif - -/**************************************************************************** - * Name: lm3s_irqinfo - * - * Description: - * Given an IRQ number, provide the register and bit setting to enable or - * disable the irq. - * - ****************************************************************************/ - -static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) -{ - DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); - - /* Check for external interrupt */ - - if (irq >= LM3S_IRQ_INTERRUPTS) - { - if (irq < LM3S_IRQ_INTERRUPTS + 32) - { - *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); - } - else if (irq < NR_IRQS) - { - *regaddr = NVIC_IRQ32_63_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); - } - else - { - return ERROR; /* Invalid interrupt */ - } - } - - /* Handler processor exceptions. Only a few can be disabled */ - - else - { - *regaddr = NVIC_SYSHCON; - if (irq == LM3S_IRQ_MEMFAULT) - { - *bit = NVIC_SYSHCON_MEMFAULTENA; - } - else if (irq == LM3S_IRQ_BUSFAULT) - { - *bit = NVIC_SYSHCON_BUSFAULTENA; - } - else if (irq == LM3S_IRQ_USAGEFAULT) - { - *bit = NVIC_SYSHCON_USGFAULTENA; - } - else if (irq == LM3S_IRQ_SYSTICK) - { - *regaddr = NVIC_SYSTICK_CTRL; - *bit = NVIC_SYSTICK_CTRL_ENABLE; - } - else - { - return ERROR; /* Invalid or unsupported exception */ - } - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - /* Disable all interrupts */ - - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); - - /* Set all interrrupts (and exceptions) to the default priority */ - - putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); - - /* currents_regs is non-NULL only while processing an interrupt */ - - current_regs = NULL; - - /* Initialize support for GPIO interrupts if included in this build */ - -#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS -#ifdef CONFIG_HAVE_WEAKFUNCTIONS - if (gpio_irqinitialize != NULL) -#endif - { - gpio_irqinitialize(); - } -#endif - - /* Attach the SVCall and Hard Fault exception handlers. The SVCall - * exception is used for performing context switches; The Hard Fault - * must also be caught because a SVCall may show up as a Hard Fault - * under certain conditions. - */ - - irq_attach(LM3S_IRQ_SVCALL, up_svcall); - irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); - - /* Set the priority of the SVCall interrupt */ - -#ifdef CONFIG_ARCH_IRQPRIO -/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ -#endif - - /* If the MPU is enabled, then attach and enable the Memory Management - * Fault handler. - */ - -#ifdef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); - up_enable_irq(LM3S_IRQ_MEMFAULT); -#endif - - /* Attach all other processor exceptions (except reset and sys tick) */ - -#ifdef CONFIG_DEBUG - irq_attach(LM3S_IRQ_NMI, lm3s_nmi); -#ifndef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); -#endif - irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault); - irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault); - irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv); - irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor); - irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved); -#endif - - lm3s_dumpnvic("initial", NR_IRQS); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t bit; - - if (lm3s_irqinfo(irq, ®addr, &bit) == 0) - { - /* Clear the appropriate bit in the register to enable the interrupt */ - - regval = getreg32(regaddr); - regval &= ~bit; - putreg32(regval, regaddr); - } - lm3s_dumpnvic("disable", irq); -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - uint32_t regaddr; - uint32_t regval; - uint32_t bit; - - if (lm3s_irqinfo(irq, ®addr, &bit) == 0) - { - /* Set the appropriate bit in the register to enable the interrupt */ - - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); - } - lm3s_dumpnvic("enable", irq); -} - -/**************************************************************************** - * Name: up_maskack_irq - * - * Description: - * Mask the IRQ and acknowledge it - * - ****************************************************************************/ - -void up_maskack_irq(int irq) -{ - up_disable_irq(irq); -} - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - * Since this API is not supported on all architectures, it should be - * avoided in common implementations where possible. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int irq, int priority) -{ - uint32_t regaddr; - uint32_t regval; - int shift; - - DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - - if (irq < LM3S_IRQ_INTERRUPTS) - { - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - } - else - { - irq -= LM3S_IRQ_INTERRUPTS; - regaddr = NVIC_IRQ_PRIORITY(irq); - } - - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); - - lm3s_dumpnvic("prioritize", irq); - return OK; -} -#endif diff --git a/nuttx/arch/arm/src/lm/lm3s_lowputc.c b/nuttx/arch/arm/src/lm/lm3s_lowputc.c deleted file mode 100644 index 7f9a826c8..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_lowputc.c +++ /dev/null @@ -1,309 +0,0 @@ -/************************************************************************** - * arch/arm/src/lm/lm3s_lowputc.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include - -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -#include "lm_gpio.h" -#include "chip/lm_pinmap.h" - -#include "lm_lowputc.h" - -/************************************************************************** - * Pre-processor Definitions - **************************************************************************/ - -/* Configuration **********************************************************/ - -#if LM3S_NUARTS < 2 -# undef CONFIG_LM3S_UART1 -# undef CONFIG_UART1_SERIAL_CONSOLE -#endif - -#if LM3S_NUARTS < 3 -# undef CONFIG_LM3S_UART2 -# undef CONFIG_UART2_SERIAL_CONSOLE -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#else -# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef HAVE_CONSOLE -#endif - -/* Select UART parameters for the selected console */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART0_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART1_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART2_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP -#else -# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" -#endif - -/* Get LCRH settings */ - -#if LM3S_CONSOLE_BITS == 5 -# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS -#elif LM3S_CONSOLE_BITS == 6 -# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS -#elif LM3S_CONSOLE_BITS == 7 -# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS -#elif LM3S_CONSOLE_BITS == 8 -# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS -#else -# error "Number of bits not supported" -#endif - -#if LM3S_CONSOLE_PARITY == 0 -# define UART_LCRH_PARITY (0) -#elif LM3S_CONSOLE_PARITY == 1 -# define UART_LCRH_PARITY UART_LCRH_PEN -#elif LM3S_CONSOLE_PARITY == 2 -# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) -#else -# error "Invalid parity selection" -#endif - -#if LM3S_CONSOLE_2STOP != 0 -# define UART_LCRH_NSTOP UART_LCRH_STP2 -#else -# define UART_LCRH_NSTOP (0) -#endif - -#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN) - -/* Calculate BAUD rate from the SYS clock: - * - * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit - * fractional part. The number formed by these two values is used by the baud-rate generator - * to determine the bit period. Having a fractional baud-rate divider allows the UART to - * generate all the standard baud rates. - * - * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) - * register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate - * Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship - * to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional - * part, separated by a decimal place.): - * - * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) - * - * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number - * (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated - * by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 - * to account for rounding errors: - * - * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) - * - * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred - * to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is - * used for error detection during receive operations. - * - * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and - * UARTFBRD registers form an internal 30-bit register. This internal register is only - * updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate - * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." - */ - -#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) -#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) -#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) -#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) - -/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: - * - * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 - * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 - * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 - * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 - * - * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 - */ - -/************************************************************************** - * Private Types - **************************************************************************/ - -/************************************************************************** - * Private Function Prototypes - **************************************************************************/ - -/************************************************************************** - * Global Variables - **************************************************************************/ - -/************************************************************************** - * Private Variables - **************************************************************************/ - -/************************************************************************** - * Private Functions - **************************************************************************/ - -/************************************************************************** - * Public Functions - **************************************************************************/ - -/************************************************************************** - * Name: up_lowputc - * - * Description: - * Output one byte on the serial console - * - **************************************************************************/ - -void up_lowputc(char ch) -{ -#ifdef HAVE_CONSOLE - /* Wait until the TX FIFO is not full */ - - while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); - - /* Then send the character */ - - putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); -#endif -} - -/************************************************************************** - * Name: up_lowsetup - * - * Description: - * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output availabe as soon - * as possible. - * - **************************************************************************/ - -void up_lowsetup(void) -{ - uint32_t regval; -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - uint32_t ctl; -#endif - - /* Enable the selected UARTs and configure GPIO pins to need by the - * the selected UARTs. NOTE: The serial driver later depends on - * this pin configuration -- whether or not a serial console is selected. - */ - -#ifdef CONFIG_LM3S_UART0 - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_UART0; - putreg32(regval, LM3S_SYSCON_RCGC1); - - lm3s_configgpio(GPIO_UART0_RX); - lm3s_configgpio(GPIO_UART0_TX); -#endif - -#ifdef CONFIG_LM3S_UART1 - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_UART1; - putreg32(regval, LM3S_SYSCON_RCGC1); - - lm3s_configgpio(GPIO_UART1_RX); - lm3s_configgpio(GPIO_UART1_TX); -#endif - - /* Enable the selected console device */ - -#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - - ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); - ctl &= ~UART_CTL_UARTEN; - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); - - /* Write the integer portion of the BRD to the UART IBRD register */ - - putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); - - /* Write the fractional portion of the BRD to the UART FBRD register */ - - putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); - - /* Write the desired serial parameters to the UART LCRH register */ - - putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); - - /* Enable the UART by setting the UARTEN bit in the UART CTL register */ - - ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); -#endif - -} - - diff --git a/nuttx/arch/arm/src/lm/lm3s_serial.c b/nuttx/arch/arm/src/lm/lm3s_serial.c deleted file mode 100644 index 79628c765..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_serial.c +++ /dev/null @@ -1,1064 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_serial.c - * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" -#include "os_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Some sanity checks *******************************************************/ - -#if LM3S_NUARTS < 2 -# undef CONFIG_LM3S_UART1 -# undef CONFIG_UART1_SERIAL_CONSOLE -#endif - -#if LM3S_NUARTS < 3 -# undef CONFIG_LM3S_UART2 -# undef CONFIG_UART2_SERIAL_CONSOLE -#endif - -/* Is there a UART enabled? */ - -#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2) -# error "No UARTs enabled" -#endif - -/* Is there a serial console? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#else -# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef HAVE_CONSOLE -#endif - -/* If we are not using the serial driver for the console, then we - * still must provide some minimal implementation of up_putc. - */ - -#ifdef USE_SERIALDRIVER - -/* Which UART with be tty0/console and which tty1? */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0port /* UART0 is console */ -# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# ifdef CONFIG_LM3S_UART1 -# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart1port /* UART1 is console */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# ifdef CONFIG_LM3S_UART0 -# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart2port /* UART2 is console */ -# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ -# ifdef CONFIG_LM3S_UART0 -# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elifdefined(CONFIG_LM3S_UART0) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# ifdef CONFIG_LM3S_UART1 -# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ -# else -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# else -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -# endif -#elifdefined(CONFIG_LM3S_UART1) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# undef TTYS2_DEV /* No ttyS2 */ -# ifdef CONFIG_LM3S_UART2 -# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ -# else -# undef TTYS1_DEV /* No ttyS1 */ -# endif -#elifdefined(CONFIG_LM3S_UART2) -# undef CONSOLE_DEV /* No console device */ -# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ -# undef TTYS1_DEV /* No ttyS1 */ -# undef TTYS2_DEV /* No ttyS2 */ -#else -# error "No valid TTY devices" -# undef CONSOLE_DEV /* No console device */ -# undef TTYS0_DEV /* No ttyS0 */ -# undef TTYS1_DEV /* No ttyS1 */ -# undef TTYS2_DEV /* No ttyS2 */ -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct up_dev_s -{ - uint32_t uartbase; /* Base address of UART registers */ - uint32_t baud; /* Configured baud */ - uint32_t im; /* Saved IM value */ - uint8_t irq; /* IRQ associated with this UART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, uint32_t *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -#ifdef CONFIG_LM3S_UART0 -static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -#endif -#ifdef CONFIG_LM3S_UART1 -static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; -static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; -#endif -#ifdef CONFIG_LM3S_UART2 -static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; -static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; -#endif - -/* This describes the state of the LM3S uart0 port. */ - -#ifdef CONFIG_LM3S_UART0 -static struct up_dev_s g_uart0priv = -{ - .uartbase = LM3S_UART0_BASE, - .baud = CONFIG_UART0_BAUD, - .irq = LM3S_IRQ_UART0, - .parity = CONFIG_UART0_PARITY, - .bits = CONFIG_UART0_BITS, - .stopbits2 = CONFIG_UART0_2STOP, -}; - -static uart_dev_t g_uart0port = -{ - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart0priv, -}; -#endif - -/* This describes the state of the LM3S uart1 port. */ - -#ifdef CONFIG_LM3S_UART1 -static struct up_dev_s g_uart1priv = -{ - .uartbase = LM3S_UART1_BASE, - .baud = CONFIG_UART1_BAUD, - .irq = LM3S_IRQ_UART1, - .parity = CONFIG_UART1_PARITY, - .bits = CONFIG_UART1_BITS, - .stopbits2 = CONFIG_UART1_2STOP, -}; - -static uart_dev_t g_uart1port = -{ - .recv = - { - .size = CONFIG_UART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart1priv, -}; -#endif - -/* This describes the state of the LM3S uart1 port. */ - -#ifdef CONFIG_LM3S_UART2 -static struct up_dev_s g_uart2priv = -{ - .uartbase = LM3S_UART2_BASE, - .baud = CONFIG_UART2_BAUD, - .irq = LM3S_IRQ_UART2, - .parity = CONFIG_UART2_PARITY, - .bits = CONFIG_UART2_BITS, - .stopbits2 = CONFIG_UART2_2STOP, -}; - -static uart_dev_t g_uart2port = -{ - .recv = - { - .size = CONFIG_UART2_RXBUFSIZE, - .buffer = g_uart2rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART2_TXBUFSIZE, - .buffer = g_uart2txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart2priv, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialin - ****************************************************************************/ - -static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) -{ - return getreg32(priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) -{ - putreg32(value, priv->uartbase + offset); -} - -/**************************************************************************** - * Name: up_disableuartint - ****************************************************************************/ - -static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) -{ - /* Return the current interrupt mask value */ - - if (im) - { - *im = priv->im; - } - - /* Disable all interrupts */ - - priv->im = 0; - up_serialout(priv, LM3S_UART_IM_OFFSET, 0); -} - -/**************************************************************************** - * Name: up_restoreuartint - ****************************************************************************/ - -static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) -{ - priv->im = im; - up_serialout(priv, LM3S_UART_IM_OFFSET, im); -} - -/**************************************************************************** - * Name: up_waittxnotfull - ****************************************************************************/ - -#ifdef HAVE_CONSOLE -static inline void up_waittxnotfull(struct up_dev_s *priv) -{ - int tmp; - - /* Limit how long we will wait for the TX available condition */ - - for (tmp = 1000 ; tmp > 0 ; tmp--) - { - /* Check Tx FIFO is full */ - - if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) - { - /* The Tx FIFO is not full... return */ - - break; - } - } - - /* If we get here, then the wait has timed out and the Tx FIFO remains - * full. - */ -} -#endif - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is - * opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32_t lcrh; - uint32_t ctl; -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t den; - uint32_t brdi; - uint32_t remainder; - uint32_t divfrac; - - /* Note: The logic here depends on the fact that that the UART module - * was enabled and the GPIOs were configured in up_lowsetup(). - */ - - /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); - ctl &= ~UART_CTL_UARTEN; - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); - - /* Calculate BAUD rate from the SYS clock: - * - * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer - * and a 6-bit fractional part. The number formed by these two values is - * used by the baud-rate generator to determine the bit period. Having a - * fractional baud-rate divider allows the UART to generate all the standard - * baud rates. - * - * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor - * (UARTIBRD) register ... and the 6-bit fractional part is loaded with the - * UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate - * divisor (BRD) has the following relationship to the system clock (where - * BRDI is the integer part of the BRD and BRDF is the fractional part, - * separated by a decimal place.): - * - * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) - * - * "where UARTSysClk is the system clock connected to the UART. The 6-bit - * fractional number (that is to be loaded into the DIVFRAC bit field in the - * UARTFBRD register) can be calculated by taking the fractional part of the - * baud-rate divisor, multiplying it by 64, and adding 0.5 to account for - * rounding errors: - * - * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) - * - * "The UART generates an internal baud-rate reference clock at 16x the baud- - * rate (referred to as Baud16). This reference clock is divided by 16 to - * generate the transmit clock, and is used for error detection during receive - * operations. - * - * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the - * UARTIBRD and UARTFBRD registers form an internal 30-bit register. This - * internal register is only updated when a write operation to UARTLCRH is - * performed, so any changes to the baud-rate divisor must be followed by a - * write to the UARTLCRH register for the changes to take effect. ..." - */ - - den = priv->baud << 4; - brdi = SYSCLK_FREQUENCY / den; - remainder = SYSCLK_FREQUENCY - den * brdi; - divfrac = ((remainder << 6) + (den >> 1)) / den; - - up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); - up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); - - /* Set up the LCRH register */ - - lcrh = 0; - switch (priv->bits) - { - case 5: - lcrh |= UART_LCRH_WLEN_5BITS; - break; - case 6: - lcrh |= UART_LCRH_WLEN_6BITS; - break; - case 7: - lcrh |= UART_LCRH_WLEN_7BITS; - break; - case 8: - default: - lcrh |= UART_LCRH_WLEN_8BITS; - break; - } - - switch (priv->parity) - { - case 0: - default: - break; - case 1: - lcrh |= UART_LCRH_PEN; - break; - case 2: - lcrh |= UART_LCRH_PEN|UART_LCRH_EPS; - break; - } - - if (priv->stopbits2) - { - lcrh |= UART_LCRH_STP2; - } - - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); -#endif - - /* Set the UART to interrupt whenever the TX FIFO is almost empty or when - * any character is received. - */ - - up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); - - /* Flush the Rx and Tx FIFOs -- How do you do that?*/ - - /* Enable Rx interrupts from the UART except for Tx interrupts. We don't want - * Tx interrupts until we have something to send. We will check for serial - * errors as part of Rx interrupt processing (no interrupts will be received - * yet because the interrupt is still disabled at the interrupt controller. - */ - - up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); - - /* Enable the FIFOs */ - -#ifdef CONFIG_SUPPRESS_UART_CONFIG - lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); -#endif - lcrh |= UART_LCRH_FEN; - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); - - /* Enable Rx, Tx, and the UART */ - -#ifdef CONFIG_SUPPRESS_UART_CONFIG - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); -#endif - ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); - - /* Set up the cache IM value */ - - priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_disableuartint(priv, NULL); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked - * when an interrupt received on the 'irq' It should call - * uart_transmitchars or uart_receivechar to perform the - * appropriate data transfers. The interrupt handling logic\ - * must be able to map the 'irq' number into the approprite - * uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context) -{ - struct uart_dev_s *dev = NULL; - struct up_dev_s *priv; - uint32_t mis; - int passes; - bool handled; - -#ifdef CONFIG_LM3S_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_LM3S_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif - { - PANIC(OSERR_INTERNAL); - } - priv = (struct up_dev_s*)dev->priv; - - /* Loop until there are no characters to be transferred or, - * until we have been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the masked UART status and clear the pending interrupts. */ - - mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); - up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); - - /* Handle incoming, receive bytes (with or without timeout) */ - - if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0) - { - /* Rx buffer not empty ... process incoming bytes */ - - uart_recvchars(dev); - handled = true; - } - - /* Handle outgoing, transmit bytes */ - - if ((mis & UART_MIS_TXMIS) != 0) - { - /* Tx FIFO not full ... process outgoing bytes */ - - uart_xmitchars(dev); - handled = true; - } - } - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; - int ret = OK; - - switch (cmd) - { - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s*)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, uint32_t *status) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint32_t rxd; - - /* Get the Rx byte + 4 bits of error information. Return those in status */ - - rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); - *status = rxd; - - /* The lower 8bits of the Rx data is the actual recevied byte */ - - return rxd & 0xff; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - if (enable) - { - /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx - * timeout occurs. - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->im |= (UART_IM_RXIM|UART_IM_RTIM); -#endif - } - else - { - priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); - } - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - irqstate_t flags; - - flags = irqsave(); - if (enable) - { - /* Set to receive an interrupt when the TX fifo is half emptied */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->im |= UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); - - /* The serial driver wants an interrupt here, but will not get get - * one unless we "prime the pump." I believe that this is because - * behave like a level interrupt and the LM3S interrupts behave - * (at least by default) like edge interrupts. - * - * In any event, faking a TX interrupt here solves the problem; - * Call uart_xmitchars() just as would have been done if we recieved - * the TX interrupt. - */ - - uart_xmitchars(dev); -#endif - } - else - { - /* Disable the TX interrupt */ - - priv->im &= ~UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); - } - irqrestore(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Performs the low level UART initialization early in - * debug so that the serial console will be available - * during bootup. This must be called before up_serialinit. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ - /* NOTE: All GPIO configuration for the UARTs was performed in - * up_lowsetup - */ - - /* Disable all UARTS */ - - up_disableuartint(TTYS0_DEV.priv, NULL); -#ifdef TTYS1_DEV - up_disableuartint(TTYS1_DEV.priv, NULL); -#endif -#ifdef TTYS2_DEV - up_disableuartint(TTYS2_DEV.priv, NULL); -#endif - - /* Configuration whichever one is the console */ - -#ifdef HAVE_CONSOLE - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -#endif -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ - /* Register the console */ - -#ifdef HAVE_CONSOLE - (void)uart_register("/dev/console", &CONSOLE_DEV); -#endif - - /* Register all UARTs */ - - (void)uart_register("/dev/ttyS0", &TTYS0_DEV); -#ifdef TTYS1_DEV - (void)uart_register("/dev/ttyS1", &TTYS1_DEV); -#endif -#ifdef TTYS2_DEV - (void)uart_register("/dev/ttyS2", &TTYS2_DEV); -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_CONSOLE - struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; - uint32_t im; - - up_disableuartint(priv, &im); - up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); - } - - up_waittxnotfull(priv); - up_restoreuartint(priv, im); -#endif - return ch; -} - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef HAVE_CONSOLE - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_lowputc('\r'); - } - - up_lowputc(ch); -#endif - return ch; -} - -#endif /* USE_SERIALDRIVER */ diff --git a/nuttx/arch/arm/src/lm/lm3s_ssi.c b/nuttx/arch/arm/src/lm/lm3s_ssi.c deleted file mode 100644 index 8cd1cee07..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_ssi.c +++ /dev/null @@ -1,1580 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm32/lm3s_ssi.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" -#include "lm_gpio.h" -#include "lm_ssi.h" -#include "chip/lm_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG with - * CONFIG_DEBUG_VERBOSE too) - */ - -#undef SSI_DEBUG /* Define to enable debug */ - -#ifdef SSI_DEBUG -# define ssidbg lldbg -# define ssivdbg llvdbg -#else -# define ssidbg(x...) -# define ssivdbg(x...) -#endif - -/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI - * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in - * such case, the following must be expanded). - */ - -#if LM3S_NSSI == 0 -# undef CONFIG_SSI0_DISABLE -# define CONFIG_SSI0_DISABLE 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#endif - -/* Which SSI modules have been enabled? */ - -#ifndef CONFIG_SSI0_DISABLE -# define SSI0_NDX 0 /* Index to SSI0 in g_ssidev[] */ -# ifndef CONFIG_SSI1_DISABLE -# define SSI1_NDX 1 /* Index to SSI1 in g_ssidev[] */ -# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ -# else -# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ -# define SSI_BASE LM3S_SSI0_BASE -# define SSI_IRQ LM3S_IRQ_SSI0 -# endif -#else -# ifndef CONFIG_SSI1_DISABLE -# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ -# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ -# define SSI_BASE LM3S_SSI1_BASE -# define SSI_IRQ LM3S_IRQ_SSI1 -# else -# define NSSI_ENABLED 0 /* No SSI interfaces */ -# endif -#endif - -/* Compile the rest of the file only if at least one SSI interface has been - * enabled. - */ - -#if NSSI_ENABLED > 0 - -/* The number of (16-bit) words that will fit in the Tx FIFO */ - -#define LM3S_TXFIFO_WORDS 8 - -/* Configuration settings */ - -#ifndef CONFIG_SSI_TXLIMIT -# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) -#endif - -#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS -# error "Invalid range for CONFIG_SSI_TXLIMIT" -#endif - -#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) -# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" -#endif - -/**************************************************************************** - * Private Type Definitions - ****************************************************************************/ - -struct lm3s_ssidev_s -{ - const struct spi_ops_s *ops; /* Common SPI operations */ -#ifndef CONFIG_SSI_POLLWAIT - sem_t xfrsem; /* Wait for transfer to complete */ -#endif - - /* These following are the source and destination buffers of the transfer. - * they are retained in this structure so that they will be accessible - * from an interrupt handler. The actual type of the buffer is uint8_t if - * nbits <=8 and uint16_t if nbits >8. - */ - - void *txbuffer; /* Source buffer */ - void *rxbuffer; /* Destination buffer */ - - /* These are functions pointers that are configured to perform the - * appropriate transfer for the particular kind of exchange that is - * occurring. Differnt functions may be selected depending on (1) - * if the tx or txbuffer is NULL and depending on the number of bits - * per word. - */ - - void (*txword)(struct lm3s_ssidev_s *priv); - void (*rxword)(struct lm3s_ssidev_s *priv); - -#if NSSI_ENABLED > 1 - uint32_t base; /* SSI register base address */ -#endif - - int ntxwords; /* Number of words left to transfer on the Tx FIFO */ - int nrxwords; /* Number of words received on the Rx FIFO */ - int nwords; /* Number of words to be exchanged */ - uint8_t nbits; /* Current number of bits per word */ - -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - uint8_t irq; /* SSI IRQ number */ -#endif - - /* If there is more than one device on the SPI bus, then we have to enforce - * mutual exclusion and remember some configuration settings to reduce the - * overhead of constant SPI re-configuration. - */ - -#ifndef CONFIG_SPI_OWNBUS - sem_t exclsem; /* For exclusive access to the SSI bus */ - uint32_t frequency; /* Current desired SCLK frequency */ - uint32_t actual; /* Current actual SCLK frequency */ - uint8_t mode; /* Current mode 0,1,2,3 */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* SSI register access */ - -static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, - unsigned int offset); -static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, - uint32_t value); - -/* Misc helpers */ - -static uint32_t ssi_disable(struct lm3s_ssidev_s *priv); -static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable); - -#ifndef CONFIG_SSI_POLLWAIT -static void ssi_semtake(sem_t *sem); -#define ssi_semgive(s) sem_post(s); -#endif - -/* SSI data transfer */ - -static void ssi_txnull(struct lm3s_ssidev_s *priv); -static void ssi_txuint16(struct lm3s_ssidev_s *priv); -static void ssi_txuint8(struct lm3s_ssidev_s *priv); -static void ssi_rxnull(struct lm3s_ssidev_s *priv); -static void ssi_rxuint16(struct lm3s_ssidev_s *priv); -static void ssi_rxuint8(struct lm3s_ssidev_s *priv); -static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv); -static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv); -#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) -static inline int ssi_performtx(struct lm3s_ssidev_s *priv); -#else -static int ssi_performtx(struct lm3s_ssidev_s *priv); -#endif -static inline void ssi_performrx(struct lm3s_ssidev_s *priv); -static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, - void *rxbuffer, unsigned int nwords); - -/* Interrupt handling */ - -#ifndef CONFIG_SSI_POLLWAIT -static inline struct lm3s_ssidev_s *ssi_mapirq(int irq); -static int ssi_interrupt(int irq, void *context); -#endif - -/* SPI methods */ - -#ifndef CONFIG_SPI_OWNBUS -static int ssi_lock(FAR struct spi_dev_s *dev, bool lock); -#endif -static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, - uint32_t frequency); -static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, - uint32_t frequency); -static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, - enum spi_mode_e mode); -static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); -static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits); -static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits); -static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd); -#ifdef CONFIG_SPI_EXCHANGE -static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords); -#else -static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, - size_t nwords); -static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, - size_t nwords); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Common SSI operations */ - -static const struct spi_ops_s g_spiops = -{ -#ifndef CONFIG_SPI_OWNBUS - .lock = ssi_lock, -#endif - .select = lm3s_spiselect, /* Provided externally by board logic */ - .setfrequency = ssi_setfrequency, - .setmode = ssi_setmode, - .setbits = ssi_setbits, - .status = lm3s_spistatus, /* Provided externally by board logic */ -#ifdef CONFIG_SPI_CMDDATA - .cmddata = lm3s_spicmddata, -#endif - .send = ssi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = ssi_exchange, -#else - .sndblock = ssi_sndblock, - .recvblock = ssi_recvblock, -#endif -}; - -/* This supports is up to two SSI busses/ports */ - -static struct lm3s_ssidev_s g_ssidev[] = -{ -#ifndef CONFIG_SSI0_DISABLE - { - .ops = &g_spiops, -#if NSSI_ENABLED > 1 - .base = LM3S_SSI0_BASE, -#endif -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI0, -#endif - }, -#endif -#ifndef CONFIG_SSI1_DISABLE - { - .ops = &g_spiops, -#if NSSI_ENABLED > 1 - .base = LM3S_SSI1_BASE, -#endif -#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI1, -#endif - }, -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ssi_getreg - * - * Description: - * Read the SSI register at this offeset - * - * Input Parameters: - * priv - Device-specific state data - * offset - Offset to the SSI register from the register base address - * - * Returned Value: - * Value of the register at this offset - * - ****************************************************************************/ - -static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset) -{ -#if NSSI_ENABLED > 1 - return getreg32(priv->base + offset); -#else - return getreg32(SSI_BASE + offset); -#endif -} - -/**************************************************************************** - * Name: ssi_putreg - * - * Description: - * Write the value to the SSI register at this offeset - * - * Input Parameters: - * priv - Device-specific state data - * offset - Offset to the SSI register from the register base address - * value - Value to write - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value) -{ -#if NSSI_ENABLED > 1 - putreg32(value, priv->base + offset); -#else - putreg32(value, SSI_BASE + offset); -#endif -} - -/**************************************************************************** - * Name: ssi_disable - * - * Description: - * Disable SSI operation. NOTE: The SSI must be disabled before any control - * registers can be re-programmed. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * State of the SSI before the SSE was disabled - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static uint32_t ssi_disable(struct lm3s_ssidev_s *priv) -{ - uint32_t retval; - uint32_t regval; - - retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); - regval = (retval & ~SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); - ssivdbg("CR1: %08x\n", regval); - return retval; -} - -/**************************************************************************** - * Name: ssi_enable - * - * Description: - * Restore the SSI operational state - * - * Input Parameters: - * priv - Device-specific state data - * enable - The previous operational state - * - * Returned Value: - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable) -{ - uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); - regval &= ~SSI_CR1_SSE; - regval |= (enable & SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); - ssivdbg("CR1: %08x\n", regval); -} - -/**************************************************************************** - * Name: ssi_semtake - * - * Description: - * Wait for a semaphore (handling interruption by signals); - * - * Input Parameters: - * priv - Device-specific state data - * enable - The previous operational state - * - * Returned Value: - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static void ssi_semtake(sem_t *sem) -{ - int ret; - do - { - ret = sem_wait(sem); - } - while (ret < 0 && errno == EINTR); - DEBUGASSERT(ret == 0); -} -#endif - -/**************************************************************************** - * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8 - * - * Description: - * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer - * pointer appropriately. The selected function dependes on (1) if there - * is a source txbuffer provided, and (2) if the number of bits per - * word is <=8 or >8. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssi_txnull(struct lm3s_ssidev_s *priv) -{ - ssivdbg("TX: ->0xffff\n"); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); -} - -static void ssi_txuint16(struct lm3s_ssidev_s *priv) -{ - uint16_t *ptr = (uint16_t*)priv->txbuffer; - ssivdbg("TX: %p->%04x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); - priv->txbuffer = (void*)ptr; -} - -static void ssi_txuint8(struct lm3s_ssidev_s *priv) -{ - uint8_t *ptr = (uint8_t*)priv->txbuffer; - ssivdbg("TX: %p->%02x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); - priv->txbuffer = (void*)ptr; -} - -/**************************************************************************** - * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8 - * - * Description: - * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the - * user rxvbuffer and update the rxbuffer pointer appropriately. The - * selected function dependes on (1) if there is a desination rxbuffer - * provided, and (2) if the number of bits per word is <=8 or >8. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ssi_rxnull(struct lm3s_ssidev_s *priv) -{ -#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) - uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: discard %04x\n", regval); -#else - (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); -#endif -} - -static void ssi_rxuint16(struct lm3s_ssidev_s *priv) -{ - uint16_t *ptr = (uint16_t*)priv->rxbuffer; - *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: %p<-%04x\n", ptr, *ptr); - priv->rxbuffer = (void*)(++ptr); -} - -static void ssi_rxuint8(struct lm3s_ssidev_s *priv) -{ - uint8_t *ptr = (uint8_t*)priv->rxbuffer; - *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); - ssivdbg("RX: %p<-%02x\n", ptr, *ptr); - priv->rxbuffer = (void*)(++ptr); -} - -/**************************************************************************** - * Name: ssi_txfifofull - * - * Description: - * Return true if the Tx FIFO is full - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * true: Not full - * - ****************************************************************************/ - -static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv) -{ - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; -} - -/**************************************************************************** - * Name: ssi_rxfifoempty - * - * Description: - * Return true if the Rx FIFO is empty - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * true: Not empty - * - ****************************************************************************/ - -static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv) -{ - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; -} - -/**************************************************************************** - * Name: ssi_performtx - * - * Description: - * If the Tx FIFO is empty, then transfer as many words as we can to - * the FIFO. - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * The number of words written to the Tx FIFO (a value from 0 to 8, - * inclusive). - * - ****************************************************************************/ - -#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) -static inline int ssi_performtx(struct lm3s_ssidev_s *priv) -{ - /* Check if the Tx FIFO is full and more data to transfer */ - - if (!ssi_txfifofull(priv) && priv->ntxwords > 0) - { - /* Transfer one word to the Tx FIFO */ - - priv->txword(priv); - priv->ntxwords--; - return 1; - } - return 0; -} - -#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ - -static int ssi_performtx(struct lm3s_ssidev_s *priv) -{ -#ifndef CONFIG_SSI_POLLWAIT - uint32_t regval; -#endif - int ntxd = 0; /* Number of words written to Tx FIFO */ - - /* Check if the Tx FIFO is full */ - - if (!ssi_txfifofull(priv)) - { - /* Not full.. Check if all of the Tx words have been sent */ - - if (priv->ntxwords > 0) - { - /* No.. Transfer more words until either the Tx FIFO is full or - * until all of the user provided data has been sent. - */ -#ifdef CONFIG_SSI_TXLIMIT - /* Further limit the number of words that we put into the Tx - * FIFO to CONFIG_SSI_TXLIMIT. Otherwise, we could - * overrun the Rx FIFO on a very fast SSI bus. - */ - for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++) -#else - for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++) -#endif - { - priv->txword(priv); - } - - /* Update the count of words to to transferred */ - - priv->ntxwords -= ntxd; - } - - /* Check again... Now have all of the Tx words been sent? */ - -#ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); - if (priv->ntxwords > 0) - { - /* No.. Enable the Tx FIFO interrupt. This interrupt occurs - * when the Tx FIFO is 1/2 full or less. - */ - -#ifdef CONFIG_DEBUG - regval |= (SSI_IM_TX|SSI_RIS_ROR); -#else - regval |= SSI_IM_TX; -#endif - } - else - { - /* Yes.. Disable the Tx FIFO interrupt. The final stages of - * the transfer will be driven by Rx FIFO interrupts. - */ - - regval &= ~(SSI_IM_TX|SSI_RIS_ROR); - } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); -#endif /* CONFIG_SSI_POLLWAIT */ - } - return ntxd; -} - -#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ - -/**************************************************************************** - * Name: ssi_performrx - * - * Description: - * Transfer as many bytes as possible from the Rx FIFO to the user Rx - * buffer (if one was provided). - * - * Input Parameters: - * priv - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ssi_performrx(struct lm3s_ssidev_s *priv) -{ -#ifndef CONFIG_SSI_POLLWAIT - uint32_t regval; -#endif - - /* Loop while data is available in the Rx FIFO */ - - while (!ssi_rxfifoempty(priv)) - { - /* Have all of the requested words been transferred from the Rx FIFO? */ - - if (priv->nrxwords < priv->nwords) - { - /* No.. Read more data from Rx FIFO */ - - priv->rxword(priv); - priv->nrxwords++; - } - } - - /* The Rx FIFO is now empty. While there is Tx data to be sent, the - * transfer will be driven by Tx FIFO interrupts. The final part - * of the transfer is driven by Rx FIFO interrupts only. - */ - -#ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); - if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) - { - /* There are no more outgoing words to send, but there are - * additional incoming words expected (I would think that this - * a real corner case, be we will handle it with an extra - * interrupt, probably an Rx timeout). - */ - -#ifdef CONFIG_DEBUG - regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR); -#else - regval |= (SSI_IM_RX|SSI_IM_RT); -#endif - } - else - { - /* No.. there are either more Tx words to send or all Rx words - * have received. Disable Rx FIFO interrupts. - */ - - regval &= ~(SSI_IM_RX|SSI_IM_RT); - } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); -#endif /* CONFIG_SSI_POLLWAIT */ -} - -/**************************************************************************** - * Name: ssi_transfer - * - * Description: - * Exchange a block data with the SPI device - * - * Input Parameters: - * priv - Device-specific state data - * txbuffer - The buffer of data to send to the device (may be NULL). - * rxbuffer - The buffer to receive data from the device (may be NULL). - * nwords - The total number of words to be exchanged. If the interface - * uses <= 8 bits per word, then this is the number of uint8_t's; - * if the interface uses >8 bits per word, then this is the - * number of uint16_t's - * - * Returned Value: - * 0: success, <0:Negated error number on failure - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, - void *rxbuffer, unsigned int nwords) -{ -#ifndef CONFIG_SSI_POLLWAIT - irqstate_t flags; -#endif - int ntxd; - - ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords); - - /* Set up to perform the transfer */ - - priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */ - priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */ - priv->ntxwords = nwords; /* Number of words left to send */ - priv->nrxwords = 0; /* Number of words received */ - priv->nwords = nwords; /* Total number of exchanges */ - - /* Set up the low-level data transfer function pointers */ - - if (priv->nbits > 8) - { - priv->txword = ssi_txuint16; - priv->rxword = ssi_rxuint16; - } - else - { - priv->txword = ssi_txuint8; - priv->rxword = ssi_rxuint8; - } - - if (!txbuffer) - { - priv->txword = ssi_txnull; - } - - if (!rxbuffer) - { - priv->rxword = ssi_rxnull; - } - - /* Prime the Tx FIFO to start the sequence (saves one interrupt). - * At this point, all SSI interrupts should be disabled, but the - * operation of ssi_performtx() will set up the interrupts - * approapriately (if nwords > TxFIFO size). - */ - -#ifndef CONFIG_SSI_POLLWAIT - flags = irqsave(); - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); - - ntxd = ssi_performtx(priv); - - /* For the case where nwords < Tx FIFO size, ssi_performrx will - * configure interrupts correctly for the final phase of the - * the transfer. - */ - - ssi_performrx(priv); - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); - - /* Wait for the transfer to complete. Since there is no handshake - * with SPI, the following should complete even if there are problems - * with the transfer, so it should be safe with no timeout. - */ - - ssivdbg("Waiting for transfer complete\n"); - irqrestore(flags); - do - { - ssi_semtake(&priv->xfrsem); - } - while (priv->nrxwords < priv->nwords); - ssidbg("Transfer complete\n"); - -#else - /* Perform the transfer using polling logic. This will totally - * dominate the CPU until the transfer is complete. Only recommended - * if (1) your SPI is very fast, and (2) if you only use very short - * transfers. - */ - - do - { - /* Handle outgoing Tx FIFO transfers */ - - ntxd = ssi_performtx(priv); - - /* Handle incoming Rx FIFO transfers */ - - ssi_performrx(priv); - - /* If there are other threads at this same priority level, - * the following may help: - */ - - sched_yield(); - } - while (priv->nrxwords < priv->nwords); -#endif - return OK; -} - -/**************************************************************************** - * Name: ssi_mapirq - * - * Description: - * Map an IRQ number into the appropriate SSI device - * - * Input Parameters: - * irq - The IRQ number to be mapped - * - * Returned Value: - * On success, a reference to the private data structgure for this IRQ. - * NULL on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static inline struct lm3s_ssidev_s *ssi_mapirq(int irq) -{ - switch (irq) - { -#ifndef CONFIG_SSI0_DISABLE - case LM3S_IRQ_SSI0: - return &g_ssidev[SSI0_NDX]; -#endif -#ifndef CONFIG_SSI1_DISABLE - case LM3S_IRQ_SSI1: - return &g_ssidev[SSI1_NDX]; -#endif - default: - return NULL; - } -} -#endif - -/**************************************************************************** - * Name: ssi_interrupt - * - * Description: - * Exchange a block data with the SSI device - * - * Input Parameters: - * priv - Device-specific state data - * txbuffer - The buffer of data to send to the device (may be NULL). - * rxbuffer - The buffer to receive data from the device (may be NULL). - * nwords - The total number of words to be exchanged. If the interface - * uses <= 8 bits per word, then this is the number of uint8_t's; - * if the interface uses >8 bits per word, then this is the - * number of uint16_t's - * - * Returned Value: - * 0: success, <0:Negated error number on failure - * - ****************************************************************************/ - -#ifndef CONFIG_SSI_POLLWAIT -static int ssi_interrupt(int irq, void *context) -{ - struct lm3s_ssidev_s *priv = ssi_mapirq(irq); - uint32_t regval; - int ntxd; - - DEBUGASSERT(priv != NULL); - - /* Clear pending interrupts */ - - regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); - ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); - - /* Check for Rx FIFO overruns */ - -#ifdef CONFIG_DEBUG - if ((regval & SSI_RIS_ROR) != 0) - { - lldbg("Rx FIFO Overrun!\n"); - } -#endif - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); - - /* Handle outgoing Tx FIFO transfers */ - - ntxd = ssi_performtx(priv); - - /* Handle incoming Rx FIFO transfers */ - - ssi_performrx(priv); - - ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", - priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); - - /* Check if the transfer is complete */ - - if (priv->nrxwords >= priv->nwords) - { - /* Yes.. Disable all SSI interrupt sources */ - - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); - - /* Wake up the waiting thread */ - - ssidbg("Transfer complete\n"); - ssi_semgive(&priv->xfrsem); - } - return OK; -} -#endif - -/**************************************************************************** - * Name: ssi_lock - * - * Description: - * On SPI busses where there are multiple devices, it will be necessary to - * lock SPI to have exclusive access to the busses for a sequence of - * transfers. The bus should be locked before the chip is selected. After - * locking the SPI bus, the caller should then also call the setfrequency, - * setbits, and setmode methods to make sure that the SPI is properly - * configured for the device. If the SPI buss is being shared, then it - * may have been left in an incompatible state. - * - * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock spi bus, false: unlock SPI bus - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_OWNBUS -static int ssi_lock(FAR struct spi_dev_s *dev, bool lock) -{ - FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev; - - if (lock) - { - /* Take the semaphore (perhaps waiting) */ - - while (sem_wait(&priv->exclsem) != 0) - { - /* The only case that an error should occur here is if the wait was awakened - * by a signal. - */ - - ASSERT(errno == EINTR); - } - } - else - { - (void)sem_post(&priv->exclsem); - } - return OK; -} -#endif - -/**************************************************************************** - * Name: ssi_setfrequency - * - * Description: - * Set the SPI frequency. - * - * Input Parameters: - * dev - Device-specific state data - * frequency - The SPI frequency requested - * - * Returned Value: - * Returns the actual frequency selected - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency) -{ - uint32_t maxdvsr; - uint32_t cpsdvsr; - uint32_t regval; - uint32_t scr; - uint32_t actual; - - ssidbg("frequency: %d\n", frequency); - DEBUGASSERT(frequency); - - /* Has the frequency changed? */ - -#ifndef CONFIG_SPI_OWNBUS - if (frequency != priv->frequency) - { -#endif - /* "The serial bit rate is derived by dividing down the input clock - * (FSysClk). The clock is first divided by an even prescale value - * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale - * (SSI_CPSR) register ... The clock is further divided by a value - * from 1 to 256, which is 1 + SCR, where SCR is the value programmed - * i n the SSI Control0 (SSICR0) register ... - * - * "The frequency of the output clock SSIClk is defined by: - * - * "SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) - * - * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz, - * the module may not be able to operate at that speed. For master mode, - * the system clock must be at least two times faster than the SSIClk. - * For slave mode, the system clock must be at least 12 times faster - * than the SSIClk." - */ - - if (frequency > SYSCLK_FREQUENCY/2) - { - frequency = SYSCLK_FREQUENCY/2; - } - - /* Find optimal values for CPSDVSR and SCR. This loop is inefficient, - * but should not have to execute many times. - * - * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000. - * - * maxcvsr = 125 - * 1. cpsdvsr = 2, scr = 61 -> DONE - * - * This would correspond to an actual frequency of: - * 50,000,000 / (2 * (62)) = 403,226 - * - * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000. - * - * maxcvsr = 2 - * 1. cpsdvsr = 2, scr = 0 -> DONE - * - * This would correspond to an actual frequency of: - * 50,000,000 / (2 * (1)) = 25,000,000 - */ - - maxdvsr = SYSCLK_FREQUENCY / frequency; - cpsdvsr = 0; - do - { - cpsdvsr += 2; - scr = (maxdvsr / cpsdvsr) - 1; - } - while (scr > 255); - - /* Set CPDVSR */ - - DEBUGASSERT(cpsdvsr < 255); - ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); - - /* Set SCR */ - - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~SSI_CR0_SCR_MASK; - regval |= (scr << SSI_CR0_SCR_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); - - /* Calcluate the actual frequency */ - - actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1)); - - /* Save the frequency selection so that subsequent reconfigurations will be - * faster. - */ - -#ifndef CONFIG_SPI_OWNBUS - priv->frequency = frequency; - priv->actual = actual; - } - return priv->actual; -#else - return actual; -#endif -} - -static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - uint32_t actual; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - actual = ssi_setfrequencyinternal(priv, frequency); - ssi_enable(priv, enable); - return actual; -} - -/**************************************************************************** - * Name: ssi_setmode - * - * Description: - * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions - * - * Input Parameters: - * dev - Device-specific state data - * mode - The SPI mode requested - * - * Returned Value: - * none - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode) -{ - uint32_t modebits; - uint32_t regval; - - ssidbg("mode: %d\n", mode); - DEBUGASSERT(priv); - - /* Has the number of bits per word changed? */ - -#ifndef CONFIG_SPI_OWNBUS - if (mode != priv->mode) - { -#endif - /* Select the CTL register bits based on the selected mode */ - - switch (mode) - { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ - modebits = 0; - break; - - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ - modebits = SSI_CR0_SPH; - break; - - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ - modebits = SSI_CR0_SPO; - break; - - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ - modebits = SSI_CR0_SPH|SSI_CR0_SPO; - break; - - default: - return; - } - - /* Then set the selected mode: Freescale SPI format, mode0-3 */ - - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); - regval |= modebits; - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x\n", regval); - - /* Save the mode so that subsequent re-configuratins will be faster */ - -#ifndef CONFIG_SPI_OWNBUS - priv->mode = mode; - } -#endif -} - -static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - ssi_setmodeinternal(priv, mode); - ssi_enable(priv, enable); -} - -/**************************************************************************** - * Name: ssi_setbits - * - * Description: - * Set the number if bits per word. - * - * Input Parameters: - * dev - Device-specific state data - * nbits - The number of bits requests - * - * Returned Value: - * none - * - * Assumption: - * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) - * - ****************************************************************************/ - -static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits) -{ - uint32_t regval; - - ssidbg("nbits: %d\n", nbits); - DEBUGASSERT(priv); - if (nbits != priv->nbits && nbits >=4 && nbits <= 16) - { - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); - regval &= ~SSI_CR0_DSS_MASK; - regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); - ssivdbg("CR0: %08x\n", regval); - - priv->nbits = nbits; - } -} - -static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - uint32_t enable; - - /* NOTE that the SSI must be disabled when setting any configuration registers. */ - - enable = ssi_disable(priv); - ssi_setbitsinternal(priv, nbits); - ssi_enable(priv, enable); -} - -/**************************************************************************** - * Name: ssi_send - * - * Description: - * Exchange one word on SPI - * - * Input Parameters: - * dev - Device-specific state data - * wd - The word to send. the size of the data is determined by the - * number of bits selected for the SPI interface. - * - * Returned Value: - * response - * - ****************************************************************************/ - -static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev; - uint16_t response = 0; - - (void)ssi_transfer(priv, &wd, &response, 1); - return response; -} - -/**************************************************************************** - * Name: SPI_EXCHANGE - * - * Description: - * Exahange a block of data from SPI. Required. - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * rxbuffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that to be exchanged in units of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_EXCHANGE -static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords); -} -#endif - -/************************************************************************* - * Name: ssi_sndblock - * - * Description: - * Send a block of data on SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, buffer, NULL, nwords); -} -#endif - -/**************************************************************************** - * Name: ssi_recvblock - * - * Description: - * Revice a block of data from SPI - * - * Input Parameters: - * dev - Device-specific state data - * buffer - A pointer to the buffer in which to recieve data - * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_SPI_EXCHANGE -static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) -{ - struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; - (void)ssi_transfer(priv, NULL, buffer, nwords); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_spiinitialize - * - * Description: - * Initialize common parts the selected SPI port. Initialization of - * chip select GPIOs must have been performed by board specific logic - * prior to calling this function. Specifically: GPIOs should have - * been configured for output, and all chip selects disabled. - * - * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, - * If multiple devices on on the bus, then multiple chip selects will be - * required. Theregore, all GPIO chip management is deferred to board- - * specific logic. - * - * Input Parameter: - * Port number (for hardware that has mutiple SSI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *up_spiinitialize(int port) -{ - struct lm3s_ssidev_s *priv; - irqstate_t flags; - uint8_t regval; - - ssidbg("port: %d\n", port); - - /* Set up for the selected port */ - - flags = irqsave(); - switch (port) - { -#ifndef CONFIG_SSI0_DISABLE - case 0: - /* Select SSI0 */ - - priv = &g_ssidev[SSI0_NDX]; - - /* Enable the SSI0 peripheral */ - - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_SSI0; - putreg32(regval, LM3S_SYSCON_RCGC1); - ssivdbg("RCGC1: %08x\n", regval); - - /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the - * logic in this file makes no assumptions about chip select) - */ - - lm3s_configgpio(GPIO_SSI0_CLK); /* PA2: SSI0 clock (SSI0Clk) */ - /* lm3s_configgpio(GPIO_SSI0_FSS); PA3: SSI0 frame (SSI0Fss) */ - lm3s_configgpio(GPIO_SSI0_RX); /* PA4: SSI0 receive (SSI0Rx) */ - lm3s_configgpio(GPIO_SSI0_TX); /* PA5: SSI0 transmit (SSI0Tx) */ - break; -#endif /* CONFIG_SSI0_DISABLE */ - -#ifndef CONFIG_SSI1_DISABLE - case 1: - /* Select SSI0 */ - - priv = &g_ssidev[SSI1_NDX]; - - /* Enable the SSI1 peripheral */ - - regval = getreg32(LM3S_SYSCON_RCGC1); - regval |= SYSCON_RCGC1_SSI1; - putreg32(regval, LM3S_SYSCON_RCGC1); - ssivdbg("RCGC1: %08x\n", regval); - - /* Configure SSI1 GPIOs */ - - lm3s_configgpio(GPIO_SSI1_CLK); /* PE0: SSI1 clock (SSI1Clk) */ - /* lm3s_configgpio(GPIO_SSI1_FSS); PE1: SSI1 frame (SSI1Fss) */ - lm3s_configgpio(GPIO_SSI1_RX); /* PE2: SSI1 receive (SSI1Rx) */ - lm3s_configgpio(GPIO_SSI1_TX); /* PE3: SSI1 transmit (SSI1Tx) */ - break; -#endif /* CONFIG_SSI1_DISABLE */ - - default: - irqrestore(flags); - return NULL; - } - - /* Initialize the state structure */ - -#ifndef CONFIG_SSI_POLLWAIT - sem_init(&priv->xfrsem, 0, 0); -#endif -#ifndef CONFIG_SPI_OWNBUS - sem_init(&priv->exclsem, 0, 1); -#endif - - /* Set all CR1 fields to reset state. This will be master mode. */ - - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); - - /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ - - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); - - /* Set the initial mode to mode 0. The application may override - * this initial setting using the setmode() method. - */ - - ssi_setmodeinternal(priv, SPIDEV_MODE0); - - /* Set the initial data width to 8-bits. The application may - * override this initial setting using the setbits() method. - */ - - ssi_setbitsinternal(priv, 8); - - /* Pick some initialize clock frequency. 400,000Hz is the startup - * MMC/SD frequency used for card detection. The application may - * override this setting using the setfrequency() method. - */ - - ssi_setfrequencyinternal(priv, 400000); - - /* Disable all SSI interrupt sources. They will be enabled only - * while there is an SSI transfer in progress. - */ - - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); - - /* Attach the interrupt */ - -#ifndef CONFIG_SSI_POLLWAIT -#if NSSI_ENABLED > 1 - irq_attach(priv->irq, (xcpt_t)ssi_interrupt); -#else - irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); -#endif -#endif /* CONFIG_SSI_POLLWAIT */ - - /* Enable the SSI for operation */ - - ssi_enable(priv, SSI_CR1_SSE); - - /* Enable SSI interrupts (They are still disabled at the source). */ - -#ifndef CONFIG_SSI_POLLWAIT -#if NSSI_ENABLED > 1 - up_enable_irq(priv->irq); -#else - up_enable_irq(SSI_IRQ); -#endif -#endif /* CONFIG_SSI_POLLWAIT */ - - irqrestore(flags); - return (FAR struct spi_dev_s *)priv; -} - -#endif /* NSSI_ENABLED > 0 */ diff --git a/nuttx/arch/arm/src/lm/lm3s_start.c b/nuttx/arch/arm/src/lm/lm3s_start.c deleted file mode 100644 index 4dfe92844..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_start.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_start.c - * arch/arm/src/chip/lm3s_start.c - * - * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "lm_lowputc.h" -#include "lm_syscontrol.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -extern void lm3s_vectors(void); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: showprogress - * - * Description: - * Print a character on the UART to show boot status. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG -# define showprogress(c) up_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: _start - * - * Description: - * This is the reset entry point. - * - ****************************************************************************/ - -void __start(void) -{ - const uint32_t *src; - uint32_t *dest; - - /* Configure the uart so that we can get debug output as soon as possible */ - - up_clockconfig(); - up_lowsetup(); - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (dest = &_sbss; dest < &_ebss; ) - { - *dest++ = 0; - } - showprogress('B'); - - /* Move the intialized data section from his temporary holding spot in - * FLASH into the correct place in SRAM. The correct place in SRAM is - * give by _sdata and _edata. The temporary location is in FLASH at the - * end of all of the other read-only data (.text, .rodata) at _eronly. - */ - - for (src = &_eronly, dest = &_sdata; dest < &_edata; ) - { - *dest++ = *src++; - } - showprogress('C'); - - /* Perform early serial initialization */ - -#ifdef USE_EARLYSERIALINIT - up_earlyserialinit(); -#endif - showprogress('D'); - - /* Initialize onboard resources */ - - lm3s_boardinitialize(); - showprogress('E'); - - /* Then start NuttX */ - - showprogress('\r'); - showprogress('\n'); - os_start(); - - /* Shoulnd't get here */ - - for(;;); -} diff --git a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c deleted file mode 100644 index 87545bec7..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c +++ /dev/null @@ -1,315 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_syscontrol.c - * arch/arm/src/chip/lm3s_syscontrol.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "chip.h" -#include "lm_syscontrol.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RCC_OSCMASK (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) -#define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN) -#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2) -#define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) -#define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK) -#define FAST_OSCDELAY (512*1024) -#define SLOW_OSCDELAY (4*1024) -#define PLLLOCK_DELAY (32*1024) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_delay - * - * Description: - * Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - * - ****************************************************************************/ - -static inline void lm3s_delay(uint32_t delay) -{ - __asm__ __volatile__("1:\n" - "\tsubs %0, #1\n" - "\tbne 1b\n" - : "=r"(delay) : "r"(delay)); -} - -/**************************************************************************** - * Name: lm3s_oscdelay - * - * Description: - * Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - * - ****************************************************************************/ - -static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2) -{ - /* Wait for the oscillator to stabilize. A smaller delay is used if the - * current clock rate is very slow. - */ - - uint32_t delay = FAST_OSCDELAY; - - /* Are we currently using RCC2? */ - - if ((rcc2 & SYSCON_RCC2_USERCC2) != 0) - { - uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK; - if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) || - (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ)) - { - delay = SLOW_OSCDELAY; - } - } - - /* No.. using srce in RCC */ - - else - { - uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK; - if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ) - { - delay = SLOW_OSCDELAY; - } - } - - /* Then delay that number of loops */ - - lm3s_delay(delay); -} - -/**************************************************************************** - * Name: lm3s_plllock - * - * Description: - * The new RCC values have been selected... wait for the PLL to lock on - * - ****************************************************************************/ - -static inline void lm3s_plllock(void) -{ - volatile uint32_t delay; - - /* Loop until the lock is achieved or until a timeout occurs */ - - for (delay = PLLLOCK_DELAY; delay > 0; delay--) - { - /* Check if the PLL is locked on */ - - if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) - { - /* Yes.. return now */ - - return; - } - } - - /* If we get here, then PLL lock was not achieved */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lm3s_clockconfig - * - * Description: - * Called to change to new clock based on desired rcc and rcc2 settings. - * This is use to set up the initial clocking but can be used later to - * support slow clocked, low power consumption modes. - * - ****************************************************************************/ - -void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2) -{ - uint32_t rcc; - uint32_t rcc2; - - /* Get the current values of the RCC and RCC2 registers */ - - rcc = getreg32(LM3S_SYSCON_RCC); - rcc2 = getreg32(LM3S_SYSCON_RCC2); - - /* Temporarily bypass the PLL and system clock dividers */ - - rcc |= SYSCON_RCC_BYPASS; - rcc &= ~(SYSCON_RCC_USESYSDIV); - putreg32(rcc, LM3S_SYSCON_RCC); - - rcc2 |= SYSCON_RCC2_BYPASS2; - putreg32(rcc2, LM3S_SYSCON_RCC2); - - /* We are probably using the main oscillator. The main oscillator is disabled on - * reset and so probably must be enabled here. The internal oscillator is enabled - * on rest and if that is selected, most likely nothing needs to be done. - */ - - if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) || - ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS))) - { - /* Enable any selected osciallators (but don't disable any yet) */ - - rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); - putreg32(rcc, LM3S_SYSCON_RCC); - - /* Wait for the newly selected oscillator(s) to settle. This is tricky because - * the time that we wait can be significant and is determined by the previous - * clock setting, not the one that we are configuring. - */ - - lm3s_oscdelay(rcc, rcc2); - } - - /* Set the new crystal value, oscillator source and PLL configuration */ - - rcc &= ~RCC_XTALMASK; - rcc |= newrcc & RCC_XTALMASK; - - rcc2 &= ~RCC2_XTALMASK; - rcc2 |= newrcc2 & RCC2_XTALMASK; - - /* Clear the PLL lock interrupt */ - - putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); - - /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC - * is currently enabled. - */ - - if (rcc2 & SYSCON_RCC2_USERCC2) - { - putreg32(rcc2, LM3S_SYSCON_RCC2); - putreg32(rcc, LM3S_SYSCON_RCC); - } - else - { - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); - } - - /* Wait for the new crystal value and oscillator source to take effect */ - - lm3s_delay(16); - - /* Set the requested system divider and disable the non-selected osciallators */ - - rcc &= ~RCC_DIVMASK; - rcc |= newrcc & RCC_DIVMASK; - - rcc2 &= ~RCC2_DIVMASK; - rcc2 |= newrcc2 & RCC2_DIVMASK; - - /* Will the PLL output be used to clock the system? */ - - if ((newrcc & SYSCON_RCC_BYPASS) == 0) - { - /* Yes, wail untill the PLL is locked */ - - lm3s_plllock(); - - /* Then enable the PLL */ - - rcc &= ~SYSCON_RCC_BYPASS; - rcc2 &= ~SYSCON_RCC2_BYPASS2; - } - - /* Now we can set the final RCC/RCC2 values */ - - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); - - /* Wait for the system divider to be effective */ - - lm3s_delay(6); -} - -/**************************************************************************** - * Name: up_clockconfig - * - * Description: - * Called early in the bootsequence (before .data and .bss are available) - * in order to configure initial clocking. - * - ****************************************************************************/ - -void up_clockconfig(void) -{ -#ifdef CONFIG_LM3S_REVA2 - /* Some early silicon returned an increase LDO voltage or 2.75V to work - * around a PLL bug - */ - - putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); -#endif - - /* Set the clocking to run with the default settings provided in the board.h - * header file - */ - - lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); -} - diff --git a/nuttx/arch/arm/src/lm/lm3s_timerisr.c b/nuttx/arch/arm/src/lm/lm3s_timerisr.c deleted file mode 100644 index 823d810da..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_timerisr.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lm/lm3s_timerisr.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "nvic.h" -#include "clock_internal.h" -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). - * - * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h - * header file. - */ - -#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) - -/* The size of the reload field is 24 bits. Verify taht the reload value - * will fit in the reload register. - */ - -#if SYSTICK_RELOAD > 0x00ffffff -# error SYSTICK_RELOAD exceeds the range of the RELOAD register -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -int up_timerisr(int irq, uint32_t *regs) -{ - /* Process timer interrupt */ - - sched_process_timer(); - return 0; -} - -/**************************************************************************** - * Function: up_timerinit - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timerinit(void) -{ - uint32_t regval; - - /* Set the SysTick interrupt to the default priority */ - - regval = getreg32(NVIC_SYSH12_15_PRIORITY); - regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; - regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); - putreg32(regval, NVIC_SYSH12_15_PRIORITY); - - /* Configure SysTick to interrupt at the requested rate */ - - putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); - - /* Attach the timer interrupt vector */ - - (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); - - /* Enable SysTick interrupts */ - - putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); - - /* And enable the timer interrupt */ - - up_enable_irq(LM3S_IRQ_SYSTICK); -} diff --git a/nuttx/arch/arm/src/lm/lm3s_vectors.S b/nuttx/arch/arm/src/lm/lm3s_vectors.S deleted file mode 100644 index fe92fc954..000000000 --- a/nuttx/arch/arm/src/lm/lm3s_vectors.S +++ /dev/null @@ -1,805 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/lm3s_vectors.S - * arch/arm/src/chip/lm3s_vectors.S - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/* Memory Map: - * - * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader) - * 0x0002:0000 - Address of vectors if using bootloader - * 0x0003:ffff - End of flash - * 0x2000:0000 - Start of SRAM and start of .data (_sdata) - * - End of .data (_edata) abd start of .bss (_sbss) - * - End of .bss (_ebss) and bottom of idle stack - * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap - * 0x2000:ffff - End of SRAM and end of heap - */ - -#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) -#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) - -/* The Cortex-M3 return from interrupt is unusual. We provide the following special - * address to the BX instruction. The particular value also forces a return to - * thread mode and covers state from the main stack point, the MSP (vs. the MSP). - */ - -#define EXC_RETURN 0xfffffff9 - -/************************************************************************************ - * Global Symbols - ************************************************************************************/ - - .globl __start - - .syntax unified - .thumb - .file "lm3s_vectors.S" - -/************************************************************************************ - * Macros - ************************************************************************************/ - -/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 - * registers on the stack, then branches to an instantantiation of the following - * macro. This macro simply loads the IRQ number into R0, then jumps to the common - * IRQ handling logic. - */ - - .macro HANDLER, label, irqno - .thumb_func -\label: - mov r0, #\irqno - b lm3s_irqcommon - .endm - -/************************************************************************************ - * Vectors - ************************************************************************************/ - - .section .vectors, "ax" - .code 16 - .align 2 - .globl lm3s_vectors - .type lm3s_vectors, function - -lm3s_vectors: - -/* Processor Exceptions */ - - .word IDLE_STACK /* Vector 0: Reset stack pointer */ - .word __start /* Vector 1: Reset vector */ - .word lm3s_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */ - .word lm3s_hardfault /* Vector 3: Hard fault */ - .word lm3s_mpu /* Vector 4: Memory management (MPU) */ - .word lm3s_busfault /* Vector 5: Bus fault */ - .word lm3s_usagefault /* Vector 6: Usage fault */ - .word lm3s_reserved /* Vector 7: Reserved */ - .word lm3s_reserved /* Vector 8: Reserved */ - .word lm3s_reserved /* Vector 9: Reserved */ - .word lm3s_reserved /* Vector 10: Reserved */ - .word lm3s_svcall /* Vector 11: SVC call */ - .word lm3s_dbgmonitor /* Vector 12: Debug monitor */ - .word lm3s_reserved /* Vector 13: Reserved */ - .word lm3s_pendsv /* Vector 14: Pendable system service request */ - .word lm3s_systick /* Vector 15: System tick */ - -/* External Interrupts */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_reserved /* Vector 25: Reserved */ - .word lm3s_reserved /* Vector 26: Reserved */ - .word lm3s_reserved /* Vector 27: Reserved */ - .word lm3s_reserved /* Vector 28: Reserved */ - .word lm3s_reserved /* Vector 29: Reserved */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_gpioh /* Vector 48: GPIO Port H */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_ssi1 /* Vector 50: SSI 1 */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_reserved /* Vector 54: Reserved */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_reserved /* Vector 25: Reserved */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_reserved /* Vector 27: Reserved */ - .word lm3s_reserved /* Vector 28: Reserved */ - .word lm3s_reserved /* Vector 29: Reserved */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_reserved /* Vector 51: Reserved */ - .word lm3s_reserved /* Vector 52: Reserved */ - .word lm3s_reserved /* Vector 53: Reserved */ - .word lm3s_reserved /* Vector 54: Reserved */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_reserved /* Vector 59: Reserved */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_uart2 /* Vector 49: UART 2 */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_reserved /* Vector 55: Reserved */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm3s_cmp2 /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_gpioh /* Vector 48: GPIO Port H */ - .word lm3s_uart2 /* Vector 49: UART 2 */ - .word lm3s_ssi1 /* Vector 50: SSI 1 */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_i2c1 /* Vector 53: I2C 1 */ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_can0 /* Vector 55: CAN 0 */ - .word lm3s_can1 /* Vector 56: CAN 1 */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_reserved /* Vector 59: Reserved */ - .word lm3s_usb /* Vector 60: USB */ - .word lm3s_pwm3 /* Vector 61: PWM 3 */ - .word lm3s_udmasoft /* Vector 62: uDMA Software */ - .word lm3s_udmaerror /* Vector 63: uDMA Error */ - .word lm3s_adc1_0 /* Vector 64: ADC1 Sequence 0 */ - .word lm3s_adc1_1 /* Vector 65: ADC1 Sequence 1 */ - .word lm3s_adc1_2 /* Vector 66: ADC1 Sequence 2 */ - .word lm3s_adc1_3 /* Vector 67: ADC1 Sequence 3 */ - .word lm3s_i2s0 /* Vector 68: I2S 0 */ - .word lm3s_epi /* Vector 69: Reserved */ - .word lm3s_gpioj /* Vector 70: GPIO J */ - .word lm3s_reserved /* Vector 71: Reserved */ - #elif defined(CONFIG_ARCH_CHIP_LM3S8962) - .word lm3s_gpioa /* Vector 16: GPIO Port A */ - .word lm3s_gpiob /* Vector 17: GPIO Port B */ - .word lm3s_gpioc /* Vector 18: GPIO Port C */ - .word lm3s_gpiod /* Vector 19: GPIO Port D */ - .word lm3s_gpioe /* Vector 20: GPIO Port E */ - .word lm3s_uart0 /* Vector 21: UART 0 */ - .word lm3s_uart1 /* Vector 22: UART 1 */ - .word lm3s_ssi0 /* Vector 23: SSI 0 */ - .word lm3s_i2c0 /* Vector 24: I2C 0 */ - .word lm3s_pwmfault /* Vector 25: PWM Fault */ - .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm3s_qei0 /* Vector 29: QEI0 */ - .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm3s_wdog /* Vector 34: Watchdog Timer */ - .word lm3s_tmr0a /* Vector 35: Timer 0 A */ - .word lm3s_tmr0b /* Vector 36: Timer 0 B */ - .word lm3s_tmr1a /* Vector 37: Timer 1 A */ - .word lm3s_tmr1b /* Vector 38: Timer 1 B */ - .word lm3s_tmr2a /* Vector 39: Timer 2 A */ - .word lm3s_tmr2b /* Vector 40: Timer 3 B */ - .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm3s_reserved /* Vector 42: Reserved */ - .word lm3s_reserved /* Vector 43: Reserved */ - .word lm3s_syscon /* Vector 44: System Control */ - .word lm3s_flashcon /* Vector 45: FLASH Control */ - .word lm3s_gpiof /* Vector 46: GPIO Port F */ - .word lm3s_gpiog /* Vector 47: GPIO Port G */ - .word lm3s_reserved /* Vector 48: Reserved */ - .word lm3s_reserved /* Vector 49: Reserved */ - .word lm3s_reserved /* Vector 50: Reserved */ - .word lm3s_tmr3a /* Vector 51: Timer 3 A */ - .word lm3s_tmr3b /* Vector 52: Timer 3 B */ - .word lm3s_reserved /* Vector 53: Reserved*/ - .word lm3s_qei1 /* Vector 54: QEI1 */ - .word lm3s_can0 /* Vector 55: Can Controller */ - .word lm3s_reserved /* Vector 56: Reserved */ - .word lm3s_reserved /* Vector 57: Reserved */ - .word lm3s_eth /* Vector 58: Ethernet Controller */ - .word lm3s_hib /* Vector 59: Hibernation Module */ - .word lm3s_reserved /* Vector 60: Reserved */ - .word lm3s_reserved /* Vector 61: Reserved */ - .word lm3s_reserved /* Vector 62: Reserved */ - .word lm3s_reserved /* Vector 63: Reserved */ - .word lm3s_reserved /* Vector 64: Reserved */ - .word lm3s_reserved /* Vector 65: Reserved */ - .word lm3s_reserved /* Vector 66: Reserved */ - .word lm3s_reserved /* Vector 67: Reserved */ - .word lm3s_reserved /* Vector 68: Reserved */ - .word lm3s_reserved /* Vector 69: Reserved */ - .word lm3s_reserved /* Vector 70: Reserved */ -#else -# error "Vectors not specified for this LM3S chip" -#endif - .size lm3s_vectors, .-lm3s_vectors - -/************************************************************************************ - * .text - ************************************************************************************/ - - .text - .type handlers, function - .thumb_func -handlers: - HANDLER lm3s_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ - HANDLER lm3s_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ - HANDLER lm3s_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ - HANDLER lm3s_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ - HANDLER lm3s_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ - HANDLER lm3s_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ - HANDLER lm3s_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ - HANDLER lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ - HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ - HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm3s_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ - HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm3s_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ - HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ - HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm3s_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ - HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm3s_usb, LM3S_IRQ_USB /* Vector 60: USB */ - HANDLER lm3s_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ - HANDLER lm3s_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ - HANDLER lm3s_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ - HANDLER lm3s_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ - HANDLER lm3s_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ - HANDLER lm3s_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ - HANDLER lm3s_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ - HANDLER lm3s_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ - HANDLER lm3s_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ - HANDLER lm3s_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ -#else -# error "Vectors not specified for this LM3S chip" -#endif - -/* Common IRQ handling logic. On entry here, the return stack is on either - * the PSP or the MSP and looks like the following: - * - * REG_XPSR - * REG_R15 - * REG_R14 - * REG_R12 - * REG_R3 - * REG_R2 - * REG_R1 - * MSP->REG_R0 - * - * And - * R0 contains the IRQ number - * R14 Contains the EXC_RETURN value - * We are in handler mode and the current SP is the MSP - */ - -lm3s_irqcommon: - - /* Complete the context save */ - -#ifdef CONFIG_NUTTX_KERNEL - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the state is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ - ite ne /* Next two instructions are condition */ - mrsne r1, msp /* R1=The main stack pointer */ - mrseq r1, psp /* R1=The process stack pointer */ -#else - mrs r1, msp /* R1=The main stack pointer */ -#endif - - mov r2, r1 /* R2=Copy of the main/process stack pointer */ - add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ - mrs r3, primask /* R3=Current PRIMASK setting */ -#ifdef CONFIG_NUTTX_KERNEL - stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ -#else - stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ -#endif - - /* Disable interrupts, select the stack to use for interrupt handling - * and call up_doirq to handle the interrupt - */ - - cpsid i /* Disable further interrupts */ - - /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt - * stack pointer. The way that this is done here prohibits nested interrupts! - * Otherwise, we will re-use the main stack for interrupt level processing. - */ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - ldr sp, =g_intstackbase - str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ -#else - mov sp, r1 /* We are using the main stack pointer */ - bl up_doirq /* R0=IRQ, R1=register save (msp) */ - mov r1, sp /* Recover R1=main stack pointer */ -#endif - - /* On return from up_doirq, R0 will hold a pointer to register context - * array to use for the interrupt return. If that return value is the same - * as current stack pointer, then things are relatively easy. - */ - - cmp r0, r1 /* Context switch? */ - beq 1f /* Branch if no context switch */ - - /* We are returning with a pending context switch. This case is different - * because in this case, the register save structure does not lie on the - * stack but, rather, are within a TCB structure. We'll have to copy some - * values to the stack. - */ - - add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ - ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ - ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ - stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ -#ifdef CONFIG_NUTTX_KERNEL - ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif - b 2f /* Re-join common logic */ - - /* We are returning with no context switch. We simply need to "unwind" - * the same stack frame that we created - */ -1: -#ifdef CONFIG_NUTTX_KERNEL - ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ -#else - ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ -#endif -2: -#ifdef CONFIG_NUTTX_KERNEL - /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 - * (handler mode) if the state is on the MSP. It can only be on the PSP if - * EXC_RETURN is 0xfffffffd (unprivileged thread) - */ - - adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ - ite ne /* Next two instructions are condition */ - msrne msp, r1 /* R1=The main stack pointer */ - msreq psp, r1 /* R1=The process stack pointer */ -#else - msr msp, r1 /* Recover the return MSP value */ - - /* Preload r14 with the special return value first (so that the return - * actually occurs with interrupts still disabled). - */ - - ldr r14, =EXC_RETURN /* Load the special value */ -#endif - - /* Restore the interrupt state */ - - msr primask, r3 /* Restore interrupts */ - - /* Always return with R14 containing the special value that will: (1) - * return to thread mode, and (2) continue to use the MSP - */ - - bx r14 /* And return */ - .size handlers, .-handlers - -/************************************************************************************ - * Name: up_interruptstack/g_intstackbase - * - * Description: - * Shouldn't happen - * - ************************************************************************************/ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - .bss - .global g_intstackbase - .align 4 -up_interruptstack: - .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) -g_intstackbase: - .size up_interruptstack, .-up_interruptstack -#endif - -/************************************************************************************ - * .rodata - ************************************************************************************/ - - .section .rodata, "a" - -/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end - * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS - * and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that - * the system boots on and, eventually, becomes the idle, do nothing task that runs - * only when there is nothing else to run. The heap continues from there until the - * end of memory. See g_heapbase below. - */ - - .globl g_heapbase - .type g_heapbase, object -g_heapbase: - .long _ebss+CONFIG_IDLETHREAD_STACKSIZE - .size g_heapbase, .-g_heapbase - - .end diff --git a/nuttx/arch/arm/src/lm/lm_dumpgpio.c b/nuttx/arch/arm/src/lm/lm_dumpgpio.c new file mode 100644 index 000000000..a3190784b --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_dumpgpio.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_dumpgpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* NOTE: this is duplicated in lm_gpio.c */ + +#ifdef LM3S_GPIOH_BASE +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#else +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint32_t lm_gpiobaseaddress(int port) +{ + return g_gpiobase[port & 7]; +} + +/**************************************************************************** + * Name: lm_gpioport + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint8_t lm_gpioport(int port) +{ + return g_portchar[port & 7]; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t base; + uint32_t rcgc2; + bool enabled; + + /* Get the base address associated with the GPIO port */ + + base = lm_gpiobaseaddress(port); + DEBUGASSERT(base != 0); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + rcgc2 = getreg32(LM3S_SYSCON_RCGC2); + enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); + + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + lm_gpioport(port), pinset, base, msg); + lldbg(" RCGC2: %08x (%s)\n", + rcgc2, enabled ? "enabled" : "disabled" ); + + /* Don't bother with the rest unless the port is enabled */ + + if (enabled) + { + lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", + getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), + getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); + lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", + getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), + getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); + lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", + getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), + getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), + getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), + getreg32(base + LM3S_GPIO_SLR_OFFSET)); + } + irqrestore(flags); + return OK; +} diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.c b/nuttx/arch/arm/src/lm/lm_ethernet.c new file mode 100644 index 000000000..1d8def2e9 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ethernet.c @@ -0,0 +1,1472 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_ethernet.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#if defined(CONFIG_NET) && defined(CONFIG_LM_ETHERNET) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "lm_gpio.h" +#include "lm_ethernet.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */ + +#ifdef CONFIG_LM_ETHHDUPLEX +# define LM3S_DUPLEX_SETBITS 0 +# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX +#else +# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX +# define LM3S_DUPLEX_CLRBITS 0 +#endif + +/* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */ + +#ifdef CONFIG_LM_ETHNOAUTOCRC +# define LM3S_CRC_SETBITS 0 +# define LM3S_CRC_CLRBITS MAC_TCTL_CRC +#else +# define LM3S_CRC_SETBITS MAC_TCTL_CRC +# define LM3S_CRC_CLRBITS 0 +#endif + +/* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */ + +#ifdef CONFIG_LM_ETHNOPAD +# define LM3S_PADEN_SETBITS 0 +# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN +#else +# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN +# define LM3S_PADEN_CLRBITS 0 +#endif + +#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) +#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) + +/* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */ + +#ifdef CONFIG_LM_MULTICAST +# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL +# define LM3S_AMUL_CLRBITS 0 +#else +# define LM3S_AMUL_SETBITS 0 +# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL +#endif + +/* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */ + +#ifdef CONFIG_LM_PROMISCUOUS +# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS +# define LM3S_PRMS_CLRBITS 0 +#else +# define LM3S_PRMS_SETBITS 0 +# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS +#endif + +/* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */ + +#ifdef CONFIG_LM_BADCRC +# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC +# define LM3S_BADCRC_CLRBITS 0 +#else +# define LM3S_BADCRC_SETBITS 0 +# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC +#endif + +#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) +#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) + +/* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */ + +#ifdef CONFIG_LM_DUMPPACKET +# define lm_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) +#else +# define lm_dumppacket(m,a,n) +#endif + +/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ + +#define LM3S_WDDELAY (1*CLK_TCK) +#define LM3S_POLLHSEC (1*2) + +/* TX timeout = 1 minute */ + +#define LM3S_TXTIMEOUT (60*CLK_TCK) + +/* This is a helper pointer for accessing the contents of the Ethernet header */ + +#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf) + +#define LM32S_MAX_MDCCLK 2500000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* EMAC statistics (debug only) */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) +struct lm_statistics_s +{ + uint32_t rx_int; /* Number of Rx interrupts received */ + uint32_t rx_packets; /* Number of packets received (sum of the following): */ + uint32_t rx_ip; /* Number of Rx IP packets received */ + uint32_t rx_arp; /* Number of Rx ARP packets received */ + uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */ + uint32_t rx_pktsize; /* Number of dropped, too small or too big */ + uint32_t rx_errors; /* Number of Rx errors (reception error) */ + uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */ + uint32_t tx_int; /* Number of Tx interrupts received */ + uint32_t tx_packets; /* Number of Tx packets queued */ + uint32_t tx_errors; /* Number of Tx errors (transmission error)*/ + uint32_t tx_timeouts; /* Number of Tx timeout errors */ +}; +# define EMAC_STAT(priv,name) priv->ld_stat.name++ +#else +# define EMAC_STAT(priv,name) +#endif + +/* The lm_driver_s encapsulates all state information for a single hardware + * interface + */ + +struct lm_driver_s +{ + /* The following fields would only be necessary on chips that support + * multiple Ethernet controllers. + */ + +#if LM3S_NETHCONTROLLERS > 1 + uint32_t ld_base; /* Ethernet controller base address */ + int ld_irq; /* Ethernet controller IRQ */ +#endif + + bool ld_bifup; /* true:ifup false:ifdown */ + WDOG_ID ld_txpoll; /* TX poll timer */ + WDOG_ID ld_txtimeout; /* TX timeout timer */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + struct lm_statistics_s ld_stat; +#endif + + /* This holds the information visible to uIP/NuttX */ + + struct uip_driver_s ld_dev; /* Interface understood by uIP */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Miscellaneous low level helpers */ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm_ethin(struct lm_driver_s *priv, int offset); +static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value); +#else +static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset); +static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value); +#endif +static void lm_ethreset(struct lm_driver_s *priv); +#if 0 /* Not used */ +static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value); +#endif +static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr); + +/* Common TX logic */ + +static int lm_transmit(struct lm_driver_s *priv); +static int lm_uiptxpoll(struct uip_driver_s *dev); + +/* Interrupt handling */ + +static void lm_receive(struct lm_driver_s *priv); +static void lm_txdone(struct lm_driver_s *priv); +static int lm_interrupt(int irq, FAR void *context); + +/* Watchdog timer expirations */ + +static void lm_polltimer(int argc, uint32_t arg, ...); +static void lm_txtimeout(int argc, uint32_t arg, ...); + +/* NuttX callback functions */ + +static int lm_ifup(struct uip_driver_s *dev); +static int lm_ifdown(struct uip_driver_s *dev); +static int lm_txavail(struct uip_driver_s *dev); +#ifdef CONFIG_NET_IGMP +static int lm_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm_ethin + * + * Description: + * Read a register from the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * + * Returned Value: + * Register value + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm_ethin(struct lm_driver_s *priv, int offset) +{ + return getreg32(priv->ld_base + offset); +} +#else +static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset) +{ + return getreg32(LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm_ethout + * + * Description: + * Write a register to the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * value - The value to write the Ethernet register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->ld_base + offset); +} +#else +static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm_ethreset + * + * Description: + * Configure and reset the Ethernet module, leaving it in a disabled state. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static void lm_ethreset(struct lm_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + +#if LM3S_NETHCONTROLLERS > 1 +# error "If multiple interfaces are supported, this function would have to be redesigned" +#endif + + /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ + + flags = irqsave(); + regval = getreg32(LM3S_SYSCON_RCGC2); + regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); + putreg32(regval, LM3S_SYSCON_RCGC2); + nllvdbg("RCGC2: %08x\n", regval); + + /* Put the Ethernet controller into the reset state */ + + regval = getreg32(LM3S_SYSCON_SRCR2); + regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + + /* Wait just a bit. This is a much longer delay than necessary */ + + up_mdelay(2); + + /* Then take the Ethernet controller out of the reset state */ + + regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + nllvdbg("SRCR2: %08x\n", regval); + + /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ + + up_mdelay(2); + + /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */ + +#ifdef CONFIG_LM_ETHLEDS + /* Configure the pins for the peripheral function */ + + lm_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); + lm_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); +#endif + + /* Disable all Ethernet controller interrupts */ + + regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Clear any pending interrupts (shouldn't be any) */ + + regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + irqrestore(flags); +} + +/**************************************************************************** + * Function: lm_phywrite + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the data to be written */ + + DEBUGASSERT(value < MAC_MTXD_MASK); + lm_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); + + /* Set up the PHY register address and start the write operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); +} +#endif + +/**************************************************************************** + * Function: lm_phyread + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the PHY register address and start the read operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Read and return the PHY data */ + + return (uint16_t)(lm_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); +} + +/**************************************************************************** + * Function: lm_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int lm_transmit(struct lm_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + int ret = -EBUSY; + + /* Verify that the hardware is ready to send another packet */ + + flags = irqsave(); + if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* Increment statistics */ + + EMAC_STAT(priv, tx_packets); + lm_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* Transfer the packet into the Tx FIFO. The LS 16-bits of the first + * 32-bit word written to the Tx FIFO contains the Ethernet payload + * data length. That is the full length of the message (d_len) minus + * the size of the Ethernet header (14). + */ + + pktlen = priv->ld_dev.d_len; + nllvdbg("Sending packet, pktlen: %d\n", pktlen); + DEBUGASSERT(pktlen > UIP_LLH_LEN); + + dbuf = priv->ld_dev.d_buf; + regval = (uint32_t)(pktlen - 14); + regval |= ((uint32_t)(*dbuf++) << 16); + regval |= ((uint32_t)(*dbuf++) << 24); + lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + + /* Write all of the whole, 32-bit values in the middle of the packet */ + + for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word from the user buffer. Note, the user + * buffer may be un-aligned. + */ + + lm_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); + } + + /* Write the last, partial word in the FIFO */ + + if (bytesleft > 0) + { + /* Write the last word */ + + regval = 0; + switch (bytesleft) + { + case 0: + default: + break; + + case 3: + regval |= ((uint32_t)dbuf[2] << 16); + case 2: + regval |= ((uint32_t)dbuf[1] << 8); + case 1: + regval |= (uint32_t)dbuf[0]; + break; + } + lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + } + + /* Activate the transmitter */ + + lm_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv); + ret = OK; + } + + irqrestore(flags); + return ret; +} + +/**************************************************************************** + * Function: lm_uiptxpoll + * + * Description: + * The transmitter is available, check if uIP has any outgoing packets ready + * to send. This is a callback from uip_poll(). uip_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static int lm_uiptxpoll(struct uip_driver_s *dev) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private; + int ret = OK; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len); + if (priv->ld_dev.d_len > 0) + { + /* Send the packet. lm_transmit() will return zero if the + * packet was successfully handled. + */ + + DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + uip_arp_out(&priv->ld_dev); + ret = lm_transmit(priv); + } + + /* If zero is returned, the polling will continue until all connections have + * been examined. + */ + + return ret; +} + +/**************************************************************************** + * Function: lm_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm_receive(struct lm_driver_s *priv) +{ + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + + /* Loop while there are incoming packets to be processed */ + + while ((lm_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) + { + /* Update statistics */ + + EMAC_STAT(priv, rx_packets); + + /* Copy the data data from the hardware to priv->ld_dev.d_buf. Set + * amount of data in priv->ld_dev.d_len + */ + + dbuf = priv->ld_dev.d_buf; + + /* The packet frame length begins in the LS 16-bits of the first + * word from the FIFO followed by the Ethernet header beginning + * in the MS 16-bits of the first word. + * + * Pick off the packet length from the first word. This packet length + * includes the len/type field (size 2) and the FCS (size 4). + */ + + regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + pktlen = (int)(regval & 0x0000ffff); + nllvdbg("Receiving packet, pktlen: %d\n", pktlen); + + /* Check if the pktlen is valid. It should be large enough to hold + * an Ethernet header and small enough to fit entirely in the I/O + * buffer. Six is subtracted to acount for the 2-byte length/type + * and 4 byte FCS that are not copied into the uIP packet. + */ + + if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6)) + { + int wordlen; + + /* We will have to drop this packet */ + + nlldbg("Bad packet size dropped (%d)\n", pktlen); + EMAC_STAT(priv, rx_pktsize); + + /* The number of bytes and words left to read is pktlen - 4 (including, + * the final, possibly partial word) because we've already read 4 bytes. + */ + + wordlen = (pktlen - 1) >> 2; + + /* Read and discard the remaining words in the FIFO */ + + while (wordlen--) + { + (void)lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Check for another packet */ + + continue; + } + + /* Save the first two bytes from the first word */ + + *dbuf++ = (uint8_t)((regval >> 16) & 0xff); + *dbuf++ = (uint8_t)((regval >> 24) & 0xff); + + /* Read all of the whole, 32-bit values in the middle of the packet. + * We've already read the length (2 bytes) plus the first two bytes + * of data. + */ + + for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word to the user buffer. Note, the user + * buffer may be un-aligned. + */ + + *(uint32_t*)dbuf = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Handle the last, partial word in the FIFO (0-3 bytes) and discard + * the 4-byte FCS. + */ + + for (; bytesleft > 0; bytesleft -= 4) + { + /* Read the last word. And transfer all but the last four + * bytes of the FCS into the user buffer. + */ + + regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + switch (bytesleft) + { + default: + break; + + case 7: + dbuf[2] = (regval >> 16) & 0xff; + case 6: + dbuf[1] = (regval >> 8) & 0xff; + case 5: + dbuf[0] = regval & 0xff; + break; + } + } + + /* Pass the packet length to uIP MINUS 2 bytes for the length and + * 4 bytes for the FCS. + */ + + priv->ld_dev.d_len = pktlen - 6; + lm_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv6 + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6)) +#else + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP)) +#endif + { + nllvdbg("IP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_ip); + + uip_arp_ipin(&priv->ld_dev); + uip_input(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + uip_arp_out(&priv->ld_dev); + lm_transmit(priv); + } + } + else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP)) + { + nllvdbg("ARP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_arp); + + uip_arp_arpin(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + lm_transmit(priv); + } + } +#ifdef CONFIG_DEBUG + else + { + nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); + EMAC_STAT(priv, rx_dropped); + } +#endif + } +} + +/**************************************************************************** + * Function: lm_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm_txdone(struct lm_driver_s *priv) +{ + /* Cancel the TX timeout */ + + wd_cancel(priv->ld_txtimeout); + + /* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. Since + * we get here because of of TXEMP which indicates that the packet was + * transmitted and that the TX FIFO is empty, NEWTX should always be zero + * at this point. + */ + + DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm_uiptxpoll); +} + +/**************************************************************************** + * Function: lm_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int lm_interrupt(int irq, FAR void *context) +{ + register struct lm_driver_s *priv; + uint32_t ris; + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate and interface with an IRQ is needed" +#else + priv = &g_lm3sdev[0]; +#endif + + /* Read the raw interrupt status register */ + + ris = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); + + /* Clear all pending interrupts */ + + lm_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); + + /* Check for errors */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + if ((ris & MAC_RIS_TXER) != 0) + { + EMAC_STAT(priv, tx_errors); /* Number of Tx errors */ + } + + if ((ris & MAC_RIS_FOV) != 0) + { + EMAC_STAT(priv, rx_ovrerrors); /* Number of Rx FIFO overrun errors */ + } + + if ((ris & MAC_RIS_RXER) != 0) + { + EMAC_STAT(priv, rx_errors); /* Number of Rx errors */ + } +#endif + + /* Handle (unmasked) interrupts according to status bit settings */ + + ris &= lm_ethin(priv, LM3S_MAC_IM_OFFSET); + + /* Is this an Rx interrupt (meaning that a packet has been received)? */ + + if ((ris & MAC_RIS_RXINT) != 0) + { + /* Handle the incoming packet */ + + EMAC_STAT(priv, rx_int); + lm_receive(priv); + } + + /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ + + if ((ris & MAC_RIS_TXEMP) != 0) + { + /* Handle the complete of the transmission */ + + EMAC_STAT(priv, tx_int); + lm_txdone(priv); + } + + /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if + * there are no pending transmissions). + */ + + return OK; +} + +/**************************************************************************** + * Function: lm_txtimeout + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm_txtimeout(int argc, uint32_t arg, ...) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)arg; + + /* Increment statistics */ + + nlldbg("Tx timeout\n"); + EMAC_STAT(priv, tx_timeouts); + + /* Then reset the hardware */ + + DEBUGASSERT(priv->ld_bifup); + lm_ifdown(&priv->ld_dev); + lm_ifup(&priv->ld_dev); + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm_uiptxpoll); +} + +/**************************************************************************** + * Function: lm_polltimer + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm_polltimer(int argc, uint32_t arg, ...) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)arg; + + /* Check if we can send another Tx packet now. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. + * + * NOTE: This can cause missing poll cycles and, hence, some timing + * inaccuracies. + */ + + if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If so, update TCP timing states and poll uIP for new XMIT data */ + + (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM3S_POLLHSEC); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, arg); + } +} + +/**************************************************************************** + * Function: lm_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm_ifup(struct uip_driver_s *dev) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + uint32_t div; + uint16_t phyreg; + + nlldbg("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Enable and reset the Ethernet controller */ + + flags = irqsave(); + lm_ethreset(priv); + + /* Set the management clock divider register for access to the PHY + * register set. The MDC clock is divided down from the system clock per: + * + * MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1)) + * div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1 + * + * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will + * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded. + */ + + div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; + lm_ethout(priv, LM3S_MAC_MDV_OFFSET, div); + nllvdbg("MDV: %08x\n", div); + + /* Then configure the Ethernet Controller for normal operation + * + * Setup the transmit control register (Full duplex, TX CRC Auto Generation, + * TX Padding Enabled). + */ + + regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval &= ~LM3S_TCTCL_CLRBITS; + regval |= LM3S_TCTCL_SETBITS; + lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + nllvdbg("TCTL: %08x\n", regval); + + /* Setup the receive control register (Disable multicast frames, disable + * promiscuous mode, disable bad CRC rejection). + */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~LM3S_RCTCL_CLRBITS; + regval |= LM3S_RCTCL_SETBITS; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + nllvdbg("RCTL: %08x\n", regval); + + /* Setup the time stamp configuration register */ + +#ifdef LM3S_ETHTS + regval = lm_ethin(priv, LM3S_MAC_TS_OFFSET); +#ifdef CONFIG_LM_TIMESTAMP + regval |= MAC_TS_EN; +#else + regval &= ~(MAC_TS_EN); +#endif + lm_ethout(priv, LM3S_MAC_TS_OFFSET, regval); + nllvdbg("TS: %08x\n", regval); +#endif + + /* Wait for the link to come up. This following is not very conservative + * of system resources -- it really should wait gracefully on a semaphore + * and the interrupt handler should post the semaphore when LINKSTATUS is + * set + */ + + nlldbg("Waiting for link\n"); + do + { + phyreg = lm_phyread(priv, MII_MSR); + } + while ((phyreg & MII_MSR_LINKSTATUS) == 0); + nlldbg("Link established\n"); + + /* Reset the receive FIFO */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet receiver */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RXEN; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet transmitter */ + + regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval |= MAC_TCTL_TXEN; + lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Enable the Ethernet RX packet receipt interrupt */ + + regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval |= MAC_IM_RXINTM; + lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Program the hardware with it's MAC address (for filtering) */ + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; + lm_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; + lm_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); + + /* Set and activate a timer process */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, (uint32_t)priv); + + priv->ld_bifup = true; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm_ifdown + * + * Description: + * NuttX Callback: Stop the interface. The only way to restore normal + * behavior is to call lm_ifup(). + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm_ifdown(struct uip_driver_s *dev) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + + nlldbg("Taking down: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Cancel the TX poll timer and TX timeout timers */ + + flags = irqsave(); + wd_cancel(priv->ld_txpoll); + wd_cancel(priv->ld_txtimeout); + + /* Disable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Disable all Ethernet controller interrupt sources */ + + regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Reset the receive FIFO */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet receiver */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_RCTL_RXEN; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet transmitter */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_TCTL_TXEN; + lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Clear any pending interrupts */ + + regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + + /* The interface is now DOWN */ + + priv->ld_bifup = false; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int lm_txavail(struct uip_driver_s *dev) +{ + struct lm_driver_s *priv = (struct lm_driver_s *)dev->d_private; + irqstate_t flags; + + /* Ignore the notification if the interface is not yet up or if the Tx FIFO + * hardware is not available at this time. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. When the + * transmission completes, lm_txdone() will be called and the Tx polling + * will occur at that time. + */ + + flags = irqsave(); + if (priv->ld_bifup && (lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If the interface is up and we can use the Tx FIFO, then poll uIP + * for new Tx data + */ + + (void)uip_poll(&priv->ld_dev, lm_uiptxpoll); + } + + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm_driver_s *priv = (FAR struct lm_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Function: lm_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm_driver_s *priv = (FAR struct lm_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +int lm_ethinitialize(int intf) +#else +static inline int lm_ethinitialize(int intf) +#endif +{ + struct lm_driver_s *priv = &g_lm3sdev[intf]; + int ret; + + /* Check if the Ethernet module is present */ + + ndbg("Setting up eth%d\n", intf); + +#if LM3S_NETHCONTROLLERS > 1 +# error "This debug check only works with one interface" +#else + DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); +#endif + DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct lm_driver_s)); + priv->ld_dev.d_ifup = lm_ifup; /* I/F down callback */ + priv->ld_dev.d_ifdown = lm_ifdown; /* I/F up (new IP address) callback */ + priv->ld_dev.d_txavail = lm_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_IGMP + priv->ld_dev.d_addmac = lm_addmac; /* Add multicast MAC address */ + priv->ld_dev.d_rmmac = lm_rmmac; /* Remove multicast MAC address */ +#endif + priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + + /* Create a watchdog for timing polling for and timing of transmisstions */ + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate base address an IRQ with an interface is needed" + priv->ld_base = ??; /* Ethernet controller base address */ + priv->ld_irq = ??; /* Ethernet controller IRQ number */ +#endif + priv->ld_txpoll = wd_create(); /* Create periodic poll timer */ + priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */ + + /* If the board can provide us with a MAC address, get the address + * from the board now. The MAC will not be applied until lm_ifup() + * is caleld (and the MAC can be overwritten with a netdev ioctl call). + */ + +#ifdef CONFIG_LM_BOARDMAC + lm_ethernetmac(&priv->ld_dev.d_mac); +#endif + + /* Perform minimal, one-time initialization -- just reset the controller and + * leave it disabled. The Ethernet controller will be reset and properly + * re-initialized each time lm_ifup() is called. + */ + + lm_ethreset(priv); + lm_ifdown(&priv->ld_dev); + + /* Attach the IRQ to the driver */ + +#if LM3S_NETHCONTROLLERS > 1 + ret = irq_attach(priv->irq, lm_interrupt); +#else + ret = irq_attach(LM3S_IRQ_ETHCON, lm_interrupt); +#endif + if (ret != 0) + { + /* We could not attach the ISR to the IRQ */ + + return -EAGAIN; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + (void)netdev_register(&priv->ld_dev); + return OK; +} + + +/************************************************************************************ + * Name: up_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one interface + * in the chip, then board-specific logic will have to provide this function to + * determine which, if any, Ethernet controllers should be initialized. + * + ************************************************************************************/ + +#if LM3S_NETHCONTROLLERS == 1 +void up_netinitialize(void) +{ + (void)lm_ethinitialize(0); +} +#endif + +#endif /* CONFIG_NET && CONFIG_LM_ETHERNET */ + diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h index 29fe4fd17..e71e9d077 100644 --- a/nuttx/arch/arm/src/lm/lm_ethernet.h +++ b/nuttx/arch/arm/src/lm/lm_ethernet.h @@ -74,7 +74,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Function: lm3s_ethinitialize + * Function: lm_ethinitialize * * Description: * Initialize the Ethernet driver for one interface. If the LM3S chip @@ -92,7 +92,7 @@ extern "C" * ****************************************************************************/ -int lm3s_ethinitialize(int intf); +int lm_ethinitialize(int intf); #if defined(__cplusplus) } diff --git a/nuttx/arch/arm/src/lm/lm_gpio.c b/nuttx/arch/arm/src/lm/lm_gpio.c new file mode 100644 index 000000000..499bf07a2 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_gpio.c @@ -0,0 +1,854 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_gpio.c + * arch/arm/src/chip/lm_gpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "os_internal.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* These definitions are part of the implementation of the GPIO pad + * configuration of Table 9-1 in the LM3S6918 data sheet. + */ + +#define AFSEL_SHIFT 5 +#define AFSEL_1 (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */ +#define AFSEL_0 0 +#define AFSEL_X 0 + +#define DIR_SHIFT 4 +#define DIR_1 (1 << DIR_SHIFT) /* Set/clear bit in GPIO DIR register */ +#define DIR_0 0 +#define DIR_X 0 + +#define ODR_SHIFT 3 +#define ODR_1 (1 << ODR_SHIFT) /* Set/clear bit in GPIO ODR register */ +#define ODR_0 0 +#define ODR_X 0 + +#define DEN_SHIFT 2 +#define DEN_1 (1 << DEN_SHIFT) /* Set/clear bit in GPIO DEN register */ +#define DEN_0 0 +#define DEN_X 0 + +#define PUR_SHIFT 1 +#define PUR_1 (1 << PUR_SHIFT) /* Set/clear bit in GPIO PUR register */ +#define PUR_0 0 +#define PUR_X 0 + +#define PDR_SHIFT 0 +#define PDR_1 (1 << PDR_SHIFT) /* Set/clear bit in GPIO PDR register */ +#define PDR_0 0 +#define PDR_X 0 + +#define GPIO_INPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_OUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_OUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODOUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODOUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFODIO_SETBITS (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFODIO_CLRBITS (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFIO_SETBITS (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFIO_CLRBITS (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ANINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0) +#define GPIO_ANINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1) + +#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_func_s +{ + uint8_t setbits; /* A set of GPIO register bits to set */ + uint8_t clrbits; /* A set of GPIO register bits to clear */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_func_s g_funcbits[] = +{ + {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ + {GPIO_OUTPUT_SETBITS, GPIO_OUTPUT_CLRBITS}, /* GPIO_FUNC_OUTPUT */ + {GPIO_ODINPUT_SETBITS, GPIO_ODINPUT_CLRBITS}, /* GPIO_FUNC_ODINPUT */ + {GPIO_ODOUTPUT_SETBITS, GPIO_ODOUTPUT_CLRBITS}, /* GPIO_FUNC_ODOUTPUT */ + {GPIO_PFODIO_SETBITS, GPIO_PFODIO_CLRBITS}, /* GPIO_FUNC_PFODIO */ + {GPIO_PFIO_SETBITS, GPIO_PFIO_CLRBITS}, /* GPIO_FUNC_PFIO */ + {GPIO_ANINPUT_SETBITS, GPIO_ANINPUT_CLRBITS}, /* GPIO_FUNC_ANINPUT */ + {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ +}; + +static const uint32_t g_gpiobase[LM3S_NPORTS] = +{ + /* All support LM3S parts have at least 7 ports, GPIOA-G */ + + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, + + /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 7 + LM3S_GPIOH_BASE, +#endif + + /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 8 + LM3S_GPIOJ_BASE, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static uint32_t lm_gpiobaseaddress(unsigned int port) +{ + uint32_t gpiobase = 0; + if (port < LM3S_NPORTS) + { + gpiobase = g_gpiobase[port]; + } + return gpiobase; +} + +/**************************************************************************** + * Name: lm_gpiofunc + * + * Description: + * Configure GPIO registers for a specific function + * + ****************************************************************************/ + +static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func) +{ + uint32_t setbit; + uint32_t clrbit; + uint32_t regval; + + /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + + setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + } + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + } + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + + setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); + + /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data + * direction register. Bits set to 1 in the GPIODIR register configure + * the corresponding pin to be an output, while bits set to 0 configure the + * pins to be inputs. All bits are cleared by a reset, meaning all GPIO + * pins are inputs by default. + */ + + setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); + + /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode + * control select register. Writing a 1 to any bit in this register selects + * the hardware control for the corresponding GPIO line. All bits are cleared + * by a reset, therefore no GPIO line is set to hardware control by default." + * + * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit + * and unlock the GPIO. That is not implemented here. + */ + + setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); +} + +/**************************************************************************** + * Name: lm_gpiopadstrength + * + * Description: + * Set up pad strength and pull-ups + * + ****************************************************************************/ + +static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT; + uint32_t regoffset; + uint32_t regval; + uint32_t slrset; + uint32_t slrclr; + + /* Prepare bits to disable slew */ + + slrset = 0; + slrclr = pin; + + switch (strength) + { + case 0: /* 2mA pad drive strength */ + { + /* "The GPIODR2R register is the 2-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing a DRV2 bit for a GPIO + * signal, the corresponding DRV4 bit in the GPIO DR4R register and the + * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR2R_OFFSET; + } + break; + + case 1: /* 4mA pad drive strength */ + { + /* "The GPIODR4R register is the 4-mA drive control register. It allows + * for each GPIO signal in the port to be individually configured without + * affecting the other pads. When writing the DRV4 bit for a GPIO signal, + * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit + * in the GPIO DR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR4R_OFFSET; + } + break; + + case 3: /* 8mA Pad drive with slew rate control */ + { + /* "The GPIOSLR register is the slew rate control register. Slew rate + * control is only available when using the 8-mA drive strength option + * via the GPIO 8-mA Drive Select (GPIODR8R) register..." + */ + + slrset = pin; + slrclr = 0; + } + /* Fall through */ + + case 2: /* 8mA pad drive strength (without slew rate control) */ + { + /* "The GPIODR8R register is the 8-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing the DRV8 bit for a GPIO + * signal, the corresponding DRV2 bit in the GPIO DR2R register and the + * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR8R_OFFSET; + } + break; + } + + /* Set the selected pad strength and set/clear optional slew rate control */ + + regval = getreg32(base + regoffset); + regval |= pin; + putreg32(regval, base + regoffset); + + regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); + regval &= slrclr; + regval |= slrset; + putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); +} + +/**************************************************************************** + * Name: lm_gpiopadtype + * + * Description: + * Set up pad strength and pull-ups. Some of these values may be over- + * written by lm_gpiofunc, depending on the function selection. Others + * are optional for different function selections. + * + ****************************************************************************/ + +static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int padtype = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT; +#if 0 /* always overwritten by lm_gpiofunc */ + uint32_t odrset; + uint32_t odrclr; +#endif + uint32_t purset; + uint32_t purclr; + uint32_t pdrset; + uint32_t pdrclr; +#if 0 /* always overwritten by lm_gpiofunc */ + uint32_t denset; + uint32_t denclr; +#endif + uint32_t regval; + + /* Assume digital GPIO function, push-pull with no pull-up or pull-down */ + +#if 0 /* always overwritten by lm_gpiofunc */ + odrset = 0; + odrclr = pin; +#endif + purset = 0; + purclr = pin; + pdrset = 0; + pdrclr = pin; +#if 0 /* always overwritten by lm_gpiofunc */ + denset = pin; + denclr = 0; +#endif + + switch (padtype) + { + case 0: /* Push-pull */ + default: + { + } + break; + + case 1: /* Push-pull with weak pull-up */ + { + purset = pin; + purclr = 0; + } + break; + case 2: /* Push-pull with weak pull-down */ + { + pdrset = pin; + pdrclr = 0; + } + break; + case 3: /* Open-drain */ + { +#if 0 /* always overwritten by lm_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + } + break; + case 4: /* Open-drain with weak pull-up */ + { +#if 0 /* always overwritten by lm_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + purset = pin; + purclr = 0; + } + break; + case 5: /* Open-drain with weak pull-down */ + { +#if 0 /* always overwritten by lm_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + pdrset = pin; + pdrclr = 0; + } + break; + case 6: /* Analog comparator */ + { +#if 0 /* always overwritten by lm_gpiofunc */ + denset = 0; + denclr = pin; +#endif + } + break; + } + + /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + +#if 0 /* always overwritten by lm_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~odrclr; + regval |= odrset; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); +#endif + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~purclr; + regval |= purset; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~pdrclr; + regval |= pdrset; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + +#if 0 /* always overwritten by lm_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~denclr; + regval |= denset; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); +#endif +} + +/**************************************************************************** + * Name: lm_initoutput + * + * Description: + * Set the GPIO output value + * + ****************************************************************************/ + +static inline void lm_initoutput(uint32_t cfgset) +{ + bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO); + lm_gpiowrite(cfgset, value); +} + +/**************************************************************************** + * Name: lm_interrupt + * + * Description: + * Configure the interrupt pin. + * + ****************************************************************************/ + +static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; + uint32_t regval; + uint32_t isset; + uint32_t isclr; + uint32_t ibeset; + uint32_t ibeclr; + uint32_t iveset; + uint32_t iveclr; + + /* Mask and clear the GPIO interrupt + * + * "The GPIOIM register is the interrupt mask register. Bits set to High in + * GPIO IM allow the corresponding pins to trigger their individual interrupts + * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering + * on that pin. All bits are cleared by a reset." + */ + + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + + /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit + * in this register clears the corresponding interrupt edge detection logic + * register. Writing a 0 has no effect." + */ + + regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); + + /* Assume rising edge */ + + isset = 0; /* Not level sensed */ + isclr = pin; + ibeset = 0; /* Single edge */ + ibeclr = pin; + iveset = pin; /* Rising edge or high levels*/ + iveclr = 0; + + /* Then handle according to the selected interrupt type */ + + switch (inttype) + { + case 0: /* Interrupt on falling edge */ + { + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 1: /* Interrupt on rising edge */ + default: + break; + + case 2: /* Interrupt on both edges */ + { + ibeset = pin; /* Both edges */ + ibeclr = 0; + } + break; + + case 3: /* Interrupt on low level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 4: /* Interrupt on high level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + } + break; + } + + /* "The GPIO IS register is the interrupt sense register. Bits set to + * 1 in GPIOIS configure the corresponding pins to detect levels, while + * bits set to 0 configure the pins to detect edges. All bits are cleared + * by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IS_OFFSET); + regval &= isclr; + regval |= isset; + putreg32(regval, base + LM3S_GPIO_IS_OFFSET); + + /* "The GPIO IBE register is the interrupt both-edges register. When the + * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is + * set to detect edges, bits set to High in GPIO IBE configure the + * corresponding pin to detect both rising and falling edges, regardless + * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ... + * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits + * are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); + regval &= ibeclr; + regval |= ibeset; + putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); + + /* "The GPIOIEV register is the interrupt event register. Bits set to + * High in GPIO IEV configure the corresponding pin to detect rising edges + * or high levels, depending on the corresponding bit value in the GPIO + * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to + * detect falling edges or low levels, depending on the corresponding bit + * value in GPIOIS. All bits are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); + regval &= iveclr; + regval |= iveset; + putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm_configgpio(uint32_t cfgset) +{ + irqstate_t flags; + unsigned int func; + unsigned int port; + unsigned int pinno; + uint32_t pin; + uint32_t base; + uint32_t regval; + + /* Decode the basics */ + + func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT; + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (cfgset & GPIO_NUMBER_MASK); + pin = (1 <> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm_gpiobaseaddress(port); + + /* "The GPIO DATA register is the data register. In software control mode, + * values written in the GPIO DATA register are transferred onto the GPIO + * port pins if the respective pins have been configured as outputs through + * the GPIO Direction (GPIO DIR) register ... + * + * "In order to write to GPIO DATA, the corresponding bits in the mask, + * resulting from the address bus bits [9:2], must be High. Otherwise, the + * bit values remain unchanged by the write. + * + * "... All bits are cleared by a reset." + */ + + putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); +} + +/**************************************************************************** + * Name: lm_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm_gpioread(uint32_t pinset, bool value) +{ + unsigned int port; + unsigned int pinno; + uint32_t base; + + /* Decode the basics */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm_gpiobaseaddress(port); + + /* "... the values read from this register are determined for each bit + * by the mask bit derived from the address used to access the data register, + * bits [9:2]. Bits that are 1 in the address mask cause the corresponding + * bits in GPIODATA to be read, and bits that are 0 in the address mask cause + * the corresponding bits in GPIO DATA to be read as 0, regardless of their + * value. + * + * "A read from GPIO DATA returns the last bit value written if the respective + * pins are configured as outputs, or it returns the value on the + * corresponding input pin when these are configured as inputs. All bits + * are cleared by a reset." + */ + + return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); +} + diff --git a/nuttx/arch/arm/src/lm/lm_gpio.h b/nuttx/arch/arm/src/lm/lm_gpio.h index 9577fd926..1447eb065 100644 --- a/nuttx/arch/arm/src/lm/lm_gpio.h +++ b/nuttx/arch/arm/src/lm/lm_gpio.h @@ -53,7 +53,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* Bit-encoded input to lm3s_configgpio() *******************************************/ +/* Bit-encoded input to lm_configgpio() *********************************************/ /* Encoding: * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB @@ -161,57 +161,57 @@ extern "C" { #endif -/**************************************************************************** +/************************************************************************************ * Public Function Prototypes - ****************************************************************************/ + ************************************************************************************/ -/**************************************************************************** - * Name: lm3s_configgpio +/************************************************************************************ + * Name: lm_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ****************************************************************************/ + ************************************************************************************/ -int lm3s_configgpio(uint32_t cfgset); +int lm_configgpio(uint32_t cfgset); -/**************************************************************************** - * Name: lm3s_gpiowrite +/************************************************************************************ + * Name: lm_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ****************************************************************************/ + ************************************************************************************/ -void lm3s_gpiowrite(uint32_t pinset, bool value); +void lm_gpiowrite(uint32_t pinset, bool value); -/**************************************************************************** - * Name: lm3s_gpioread +/************************************************************************************ + * Name: lm_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ****************************************************************************/ + ************************************************************************************/ -bool lm3s_gpioread(uint32_t pinset, bool value); +bool lm_gpioread(uint32_t pinset, bool value); -/**************************************************************************** - * Function: lm3s_dumpgpio +/************************************************************************************ + * Function: lm_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * - ****************************************************************************/ + ************************************************************************************/ -int lm3s_dumpgpio(uint32_t pinset, const char *msg); +int lm_dumpgpio(uint32_t pinset, const char *msg); -/**************************************************************************** +/************************************************************************************ * Name: gpio_irqinitialize * * Description: * Initialize all vectors to the unexpected interrupt handler * - ****************************************************************************/ + ************************************************************************************/ int weak_function gpio_irqinitialize(void); diff --git a/nuttx/arch/arm/src/lm/lm_gpioirq.c b/nuttx/arch/arm/src/lm/lm_gpioirq.c new file mode 100644 index 000000000..f77f878de --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_gpioirq.c @@ -0,0 +1,434 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_gpioirq.c + * arch/arm/src/chip/lm_gpioirq.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "os_internal.h" +#include "irq_internal.h" + +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A table of handlers for each GPIO interrupt */ + +static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; + +/* A table that maps a GPIO group to a GPIO base address. Overly complicated + * because we support disabling interrupt support for arbitrary ports. This + * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h + */ + +static const uint32_t g_gpiobase[] = +{ +#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS + LM3S_GPIOA_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS + LM3S_GPIOB_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS + LM3S_GPIOC_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS + LM3S_GPIOD_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS + LM3S_GPIOE_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS + LM3S_GPIOF_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS + LM3S_GPIOG_BASE, +#endif + + /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip + * does not support these higher ports, then they must be disabled in the + * configuration. Otherwise, the following will likely cause compilation + * errors! + */ + +#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS + LM3S_GPIOH_BASE, +#endif +#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS + LM3S_GPIOJ_BASE, +#endif +}; + +#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t)) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_gpiobaseaddress + * + * Input: + * gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS. + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. NOTE that range checking was provided by + * callee + * + ****************************************************************************/ + +static uint32_t lm_gpiobaseaddress(unsigned int gpioirq) +{ + unsigned int ndx = gpioirq >> 3; + if (ndx < GPIO_NADDRS) + { + return g_gpiobase[ndx]; + } + return 0; +} + +/**************************************************************************** + * Name: lm_gpio*handler + * + * Description: + * Handle interrupts on each enabled GPIO port + * + ****************************************************************************/ + +static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context) +{ + uint32_t mis; + int irq; + int pin; + + /* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked + * interrupt status register. Bits read High in GPIO MIS reflect the status + * of input lines triggering an interrupt. Bits read as Low indicate that + * either no interrupt has been generated, or the interrupt is masked." + */ + + mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; + + /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR + * register is the interrupt clear register. Writing a 1 to a bit in this + * register clears the corresponding interrupt edge detection logic register. + * Writing a 0 has no effect." + */ + + putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); + + /* Now process each IRQ pending in the MIS */ + + for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1) + { + if ((mis & 1) != 0) + { + irq = irqbase + pin; + g_gpioirqvector[irq - NR_IRQS](irq, context); + } + } + return OK; +} + +#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS +static int lm_gpioahandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS +static int lm_gpiobhandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS +static int lm_gpiochandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS +static int lm_gpiodhandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS +static int lm_gpioehandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS +static int lm_gpiofhandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS +static int lm_gpioghandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS +static int lm_gpiohhandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); +} +#endif + +#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS +static int lm_gpiojhandler(int irq, FAR void *context) +{ + return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int gpio_irqinitialize(void) +{ + int i; + + /* Point all interrupt vectors to the unexpected interrupt */ + + for (i = 0; i < NR_GPIO_IRQS; i++) + { + g_gpioirqvector[i] = irq_unexpected_isr; + } + + /* Then attach each GPIO interrupt handlers and enable corresponding GPIO + * interrupts + */ + +#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS + irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler); + up_enable_irq(LM3S_IRQ_GPIOA); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS + irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler); + up_enable_irq(LM3S_IRQ_GPIOB); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS + irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler); + up_enable_irq(LM3S_IRQ_GPIOC); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS + irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler); + up_enable_irq(LM3S_IRQ_GPIOD); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS + irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler); + up_enable_irq(LM3S_IRQ_GPIOE); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS + irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler); + up_enable_irq(LM3S_IRQ_GPIOF); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS + irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler); + up_enable_irq(LM3S_IRQ_GPIOG); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS + irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler); + up_enable_irq(LM3S_IRQ_GPIOH); +#endif +#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS + irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler); + up_enable_irq(LM3S_IRQ_GPIOJ); +#endif + + return OK; +} + +/**************************************************************************** + * Name: gpio_irqattach + * + * Description: + * Attach in GPIO interrupt to the provide 'isr' + * + ****************************************************************************/ + +int gpio_irqattach(int irq, xcpt_t isr) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + int ret = ERROR; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + flags = irqsave(); + + /* If the new ISR is NULL, then the ISR is being detached. + * In this case, disable the ISR and direct any interrupts + * to the unexpected interrupt handler. + */ + + if (isr == NULL) + { +#ifndef CONFIG_ARCH_NOINTC + gpio_irqdisable(gpioirq); +#endif + isr = irq_unexpected_isr; + } + + /* Save the new ISR in the table. */ + + g_irqvector[gpioirq] = isr; + irqrestore(flags); + ret = OK; + } + return ret; +} + +/**************************************************************************** + * Name: gpio_irqenable + * + * Description: + * Enable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqenable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + +/**************************************************************************** + * Name: gpio_irqdisable + * + * Description: + * Disable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqdisable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c new file mode 100644 index 000000000..700944202 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_irq.c + * arch/arm/src/chip/lm_irq.c + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enable NVIC debug features that are probably only desireable during + * bringup + */ + +#undef LM3S_IRQ_DEBUG + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +static void lm_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = irqsave(); + slldbg("NVIC (%s, irq=%d):\n", msg, irq); + slldbg(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + slldbg(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + slldbg(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqrestore(flags); +} +#else +# define lm_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: lm_nmi, lm_busfault, lm_usagefault, lm_pendsv, + * lm_dbgmonitor, lm_pendsv, lm_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +static int lm_nmi(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! NMI received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm_busfault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Bus fault recived\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm_usagefault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Usage fault received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm_pendsv(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! PendSV received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm_dbgmonitor(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Debug Monitor receieved\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm_reserved(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Reserved interrupt\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} +#endif + +/**************************************************************************** + * Name: lm_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) +{ + DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LM3S_IRQ_INTERRUPTS) + { + if (irq < LM3S_IRQ_INTERRUPTS + 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); + } + else if (irq < NR_IRQS) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); + } + else + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handler processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == LM3S_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == LM3S_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == LM3S_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == LM3S_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable all interrupts */ + + putreg32(0, NVIC_IRQ0_31_ENABLE); + putreg32(0, NVIC_IRQ32_63_ENABLE); + + /* Set all interrrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + + /* currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Initialize support for GPIO interrupts if included in this build */ + +#ifndef CONFIG_LM_DISABLE_GPIO_IRQS +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (gpio_irqinitialize != NULL) +#endif + { + gpio_irqinitialize(); + } +#endif + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(LM3S_IRQ_SVCALL, up_svcall); + irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); + up_enable_irq(LM3S_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG + irq_attach(LM3S_IRQ_NMI, lm_nmi); +#ifndef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); +#endif + irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault); + irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault); + irq_attach(LM3S_IRQ_PENDSV, lm_pendsv); + irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor); + irq_attach(LM3S_IRQ_RESERVED, lm_reserved); +#endif + + lm_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + setbasepri(NVIC_SYSH_PRIORITY_MAX); + irqrestore(0); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm_irqinfo(irq, ®addr, &bit) == 0) + { + /* Clear the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + lm_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm_irqinfo(irq, ®addr, &bit) == 0) + { + /* Set the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + lm_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_maskack_irq + * + * Description: + * Mask the IRQ and acknowledge it + * + ****************************************************************************/ + +void up_maskack_irq(int irq) +{ + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < LM3S_IRQ_INTERRUPTS) + { + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + } + else + { + irq -= LM3S_IRQ_INTERRUPTS; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + lm_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.c b/nuttx/arch/arm/src/lm/lm_lowputc.c new file mode 100644 index 000000000..d2c1f5be5 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_lowputc.c @@ -0,0 +1,309 @@ +/************************************************************************** + * arch/arm/src/lm/lm_lowputc.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_gpio.h" +#include "chip/lm_pinmap.h" + +#include "lm_lowputc.h" + +/************************************************************************** + * Pre-processor Definitions + **************************************************************************/ + +/* Configuration **********************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART0_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART1_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART2_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP +#else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#endif + +/* Get LCRH settings */ + +#if LM3S_CONSOLE_BITS == 5 +# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS +#elif LM3S_CONSOLE_BITS == 6 +# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS +#elif LM3S_CONSOLE_BITS == 7 +# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS +#elif LM3S_CONSOLE_BITS == 8 +# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS +#else +# error "Number of bits not supported" +#endif + +#if LM3S_CONSOLE_PARITY == 0 +# define UART_LCRH_PARITY (0) +#elif LM3S_CONSOLE_PARITY == 1 +# define UART_LCRH_PARITY UART_LCRH_PEN +#elif LM3S_CONSOLE_PARITY == 2 +# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) +#else +# error "Invalid parity selection" +#endif + +#if LM3S_CONSOLE_2STOP != 0 +# define UART_LCRH_NSTOP UART_LCRH_STP2 +#else +# define UART_LCRH_NSTOP (0) +#endif + +#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN) + +/* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit + * fractional part. The number formed by these two values is used by the baud-rate generator + * to determine the bit period. Having a fractional baud-rate divider allows the UART to + * generate all the standard baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) + * register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate + * Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship + * to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional + * part, separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number + * (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated + * by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 + * to account for rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred + * to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is + * used for error detection during receive operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and + * UARTFBRD registers form an internal 30-bit register. This internal register is only + * updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate + * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." + */ + +#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) +#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) +#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) +#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) + +/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: + * + * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 + * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 + * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 + * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 + * + * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 + */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX FIFO is not full */ + + while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); + + /* Then send the character */ + + putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); +#endif +} + +/************************************************************************** + * Name: up_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +void up_lowsetup(void) +{ + uint32_t regval; +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t ctl; +#endif + + /* Enable the selected UARTs and configure GPIO pins to need by the + * the selected UARTs. NOTE: The serial driver later depends on + * this pin configuration -- whether or not a serial console is selected. + */ + +#ifdef CONFIG_LM_UART0 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART0; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm_configgpio(GPIO_UART0_RX); + lm_configgpio(GPIO_UART0_TX); +#endif + +#ifdef CONFIG_LM_UART1 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART1; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm_configgpio(GPIO_UART1_RX); + lm_configgpio(GPIO_UART1_TX); +#endif + + /* Enable the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + + /* Write the integer portion of the BRD to the UART IBRD register */ + + putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); + + /* Write the fractional portion of the BRD to the UART FBRD register */ + + putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); + + /* Write the desired serial parameters to the UART LCRH register */ + + putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); + + /* Enable the UART by setting the UARTEN bit in the UART CTL register */ + + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); +#endif + +} + + diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.h b/nuttx/arch/arm/src/lm/lm_lowputc.h index b384bbd80..49d6e2df9 100644 --- a/nuttx/arch/arm/src/lm/lm_lowputc.h +++ b/nuttx/arch/arm/src/lm/lm_lowputc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lm/lm3s_lowputc.h + * arch/arm/src/lm/lm_lowputc.h * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/nuttx/arch/arm/src/lm/lm_serial.c b/nuttx/arch/arm/src/lm/lm_serial.c new file mode 100644 index 000000000..e9f604989 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_serial.c @@ -0,0 +1,1064 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_serial.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a UART enabled? */ + +#if !defined(CONFIG_LM_UART0) && !defined(CONFIG_LM_UART1) && !defined(CONFIG_LM_UART2) +# error "No UARTs enabled" +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* If we are not using the serial driver for the console, then we + * still must provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# ifdef CONFIG_LM_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# ifdef CONFIG_LM_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM_UART0) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM_UART1) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +#elifdefined(CONFIG_LM_UART2) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#else +# error "No valid TTY devices" +# undef CONSOLE_DEV /* No console device */ +# undef TTYS0_DEV /* No ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t im; /* Saved IM value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_LM_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +/* This describes the state of the LM3S uart0 port. */ + +#ifdef CONFIG_LM_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = LM3S_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = LM3S_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM_UART1 +static struct up_dev_s g_uart1priv = +{ + .uartbase = LM3S_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = LM3S_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM_UART2 +static struct up_dev_s g_uart2priv = +{ + .uartbase = LM3S_UART2_BASE, + .baud = CONFIG_UART2_BAUD, + .irq = LM3S_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) +{ + /* Return the current interrupt mask value */ + + if (im) + { + *im = priv->im; + } + + /* Disable all interrupts */ + + priv->im = 0; + up_serialout(priv, LM3S_UART_IM_OFFSET, 0); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) +{ + priv->im = im; + up_serialout(priv, LM3S_UART_IM_OFFSET, im); +} + +/**************************************************************************** + * Name: up_waittxnotfull + ****************************************************************************/ + +#ifdef HAVE_CONSOLE +static inline void up_waittxnotfull(struct up_dev_s *priv) +{ + int tmp; + + /* Limit how long we will wait for the TX available condition */ + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + /* Check Tx FIFO is full */ + + if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) + { + /* The Tx FIFO is not full... return */ + + break; + } + } + + /* If we get here, then the wait has timed out and the Tx FIFO remains + * full. + */ +} +#endif + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t lcrh; + uint32_t ctl; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t den; + uint32_t brdi; + uint32_t remainder; + uint32_t divfrac; + + /* Note: The logic here depends on the fact that that the UART module + * was enabled and the GPIOs were configured in up_lowsetup(). + */ + + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer + * and a 6-bit fractional part. The number formed by these two values is + * used by the baud-rate generator to determine the bit period. Having a + * fractional baud-rate divider allows the UART to generate all the standard + * baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor + * (UARTIBRD) register ... and the 6-bit fractional part is loaded with the + * UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate + * divisor (BRD) has the following relationship to the system clock (where + * BRDI is the integer part of the BRD and BRDF is the fractional part, + * separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit + * fractional number (that is to be loaded into the DIVFRAC bit field in the + * UARTFBRD register) can be calculated by taking the fractional part of the + * baud-rate divisor, multiplying it by 64, and adding 0.5 to account for + * rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud- + * rate (referred to as Baud16). This reference clock is divided by 16 to + * generate the transmit clock, and is used for error detection during receive + * operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the + * UARTIBRD and UARTFBRD registers form an internal 30-bit register. This + * internal register is only updated when a write operation to UARTLCRH is + * performed, so any changes to the baud-rate divisor must be followed by a + * write to the UARTLCRH register for the changes to take effect. ..." + */ + + den = priv->baud << 4; + brdi = SYSCLK_FREQUENCY / den; + remainder = SYSCLK_FREQUENCY - den * brdi; + divfrac = ((remainder << 6) + (den >> 1)) / den; + + up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); + up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); + + /* Set up the LCRH register */ + + lcrh = 0; + switch (priv->bits) + { + case 5: + lcrh |= UART_LCRH_WLEN_5BITS; + break; + case 6: + lcrh |= UART_LCRH_WLEN_6BITS; + break; + case 7: + lcrh |= UART_LCRH_WLEN_7BITS; + break; + case 8: + default: + lcrh |= UART_LCRH_WLEN_8BITS; + break; + } + + switch (priv->parity) + { + case 0: + default: + break; + case 1: + lcrh |= UART_LCRH_PEN; + break; + case 2: + lcrh |= UART_LCRH_PEN|UART_LCRH_EPS; + break; + } + + if (priv->stopbits2) + { + lcrh |= UART_LCRH_STP2; + } + + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); +#endif + + /* Set the UART to interrupt whenever the TX FIFO is almost empty or when + * any character is received. + */ + + up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); + + /* Flush the Rx and Tx FIFOs -- How do you do that?*/ + + /* Enable Rx interrupts from the UART except for Tx interrupts. We don't want + * Tx interrupts until we have something to send. We will check for serial + * errors as part of Rx interrupt processing (no interrupts will be received + * yet because the interrupt is still disabled at the interrupt controller. + */ + + up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); + + /* Enable the FIFOs */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); +#endif + lcrh |= UART_LCRH_FEN; + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); + + /* Enable Rx, Tx, and the UART */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); +#endif + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Set up the cache IM value */ + + priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked + * when an interrupt received on the 'irq' It should call + * uart_transmitchars or uart_receivechar to perform the + * appropriate data transfers. The interrupt handling logic\ + * must be able to map the 'irq' number into the approprite + * uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + uint32_t mis; + int passes; + bool handled; + +#ifdef CONFIG_LM_UART0 + if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_LM_UART1 + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked UART status and clear the pending interrupts. */ + + mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); + up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); + + /* Handle incoming, receive bytes (with or without timeout) */ + + if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0) + { + /* Rx buffer not empty ... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + if ((mis & UART_MIS_TXMIS) != 0) + { + /* Tx FIFO not full ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + int ret = OK; + + switch (cmd) + { + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t rxd; + + /* Get the Rx byte + 4 bits of error information. Return those in status */ + + rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); + *status = rxd; + + /* The lower 8bits of the Rx data is the actual recevied byte */ + + return rxd & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx + * timeout occurs. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= (UART_IM_RXIM|UART_IM_RTIM); +#endif + } + else + { + priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); + } + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { + /* Set to receive an interrupt when the TX fifo is half emptied */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + + /* The serial driver wants an interrupt here, but will not get get + * one unless we "prime the pump." I believe that this is because + * behave like a level interrupt and the LM3S interrupts behave + * (at least by default) like edge interrupts. + * + * In any event, faking a TX interrupt here solves the problem; + * Call uart_xmitchars() just as would have been done if we recieved + * the TX interrupt. + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->im &= ~UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + } + irqrestore(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level UART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before up_serialinit. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * up_lowsetup + */ + + /* Disable all UARTS */ + + up_disableuartint(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + up_disableuartint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableuartint(TTYS2_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint32_t im; + + up_disableuartint(priv, &im); + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); + } + + up_waittxnotfull(priv); + up_restoreuartint(priv, im); +#endif + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/nuttx/arch/arm/src/lm/lm_ssi.c b/nuttx/arch/arm/src/lm/lm_ssi.c new file mode 100644 index 000000000..c6f8dcdb1 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ssi.c @@ -0,0 +1,1580 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_ssi.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" +#include "lm_ssi.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG with + * CONFIG_DEBUG_VERBOSE too) + */ + +#undef SSI_DEBUG /* Define to enable debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# define ssivdbg llvdbg +#else +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI + * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in + * such case, the following must be expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* Which SSI modules have been enabled? */ + +#ifndef CONFIG_SSI0_DISABLE +# define SSI0_NDX 0 /* Index to SSI0 in g_ssidev[] */ +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 1 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ +# else +# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ +# define SSI_BASE LM3S_SSI0_BASE +# define SSI_IRQ LM3S_IRQ_SSI0 +# endif +#else +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ +# define SSI_BASE LM3S_SSI1_BASE +# define SSI_IRQ LM3S_IRQ_SSI1 +# else +# define NSSI_ENABLED 0 /* No SSI interfaces */ +# endif +#endif + +/* Compile the rest of the file only if at least one SSI interface has been + * enabled. + */ + +#if NSSI_ENABLED > 0 + +/* The number of (16-bit) words that will fit in the Tx FIFO */ + +#define LM3S_TXFIFO_WORDS 8 + +/* Configuration settings */ + +#ifndef CONFIG_SSI_TXLIMIT +# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) +#endif + +#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS +# error "Invalid range for CONFIG_SSI_TXLIMIT" +#endif + +#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) +# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" +#endif + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +struct lm_ssidev_s +{ + const struct spi_ops_s *ops; /* Common SPI operations */ +#ifndef CONFIG_SSI_POLLWAIT + sem_t xfrsem; /* Wait for transfer to complete */ +#endif + + /* These following are the source and destination buffers of the transfer. + * they are retained in this structure so that they will be accessible + * from an interrupt handler. The actual type of the buffer is uint8_t if + * nbits <=8 and uint16_t if nbits >8. + */ + + void *txbuffer; /* Source buffer */ + void *rxbuffer; /* Destination buffer */ + + /* These are functions pointers that are configured to perform the + * appropriate transfer for the particular kind of exchange that is + * occurring. Differnt functions may be selected depending on (1) + * if the tx or txbuffer is NULL and depending on the number of bits + * per word. + */ + + void (*txword)(struct lm_ssidev_s *priv); + void (*rxword)(struct lm_ssidev_s *priv); + +#if NSSI_ENABLED > 1 + uint32_t base; /* SSI register base address */ +#endif + + int ntxwords; /* Number of words left to transfer on the Tx FIFO */ + int nrxwords; /* Number of words received on the Rx FIFO */ + int nwords; /* Number of words to be exchanged */ + uint8_t nbits; /* Current number of bits per word */ + +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + uint8_t irq; /* SSI IRQ number */ +#endif + + /* If there is more than one device on the SPI bus, then we have to enforce + * mutual exclusion and remember some configuration settings to reduce the + * overhead of constant SPI re-configuration. + */ + +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* For exclusive access to the SSI bus */ + uint32_t frequency; /* Current desired SCLK frequency */ + uint32_t actual; /* Current actual SCLK frequency */ + uint8_t mode; /* Current mode 0,1,2,3 */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SSI register access */ + +static inline uint32_t ssi_getreg(struct lm_ssidev_s *priv, + unsigned int offset); +static inline void ssi_putreg(struct lm_ssidev_s *priv, unsigned int offset, + uint32_t value); + +/* Misc helpers */ + +static uint32_t ssi_disable(struct lm_ssidev_s *priv); +static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable); + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem); +#define ssi_semgive(s) sem_post(s); +#endif + +/* SSI data transfer */ + +static void ssi_txnull(struct lm_ssidev_s *priv); +static void ssi_txuint16(struct lm_ssidev_s *priv); +static void ssi_txuint8(struct lm_ssidev_s *priv); +static void ssi_rxnull(struct lm_ssidev_s *priv); +static void ssi_rxuint16(struct lm_ssidev_s *priv); +static void ssi_rxuint8(struct lm_ssidev_s *priv); +static inline bool ssi_txfifofull(struct lm_ssidev_s *priv); +static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv); +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm_ssidev_s *priv); +#else +static int ssi_performtx(struct lm_ssidev_s *priv); +#endif +static inline void ssi_performrx(struct lm_ssidev_s *priv); +static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords); + +/* Interrupt handling */ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm_ssidev_s *ssi_mapirq(int irq); +static int ssi_interrupt(int irq, void *context); +#endif + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, + uint32_t frequency); +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void ssi_setmodeinternal(struct lm_ssidev_s *priv, + enum spi_mode_e mode); +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits); +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd); +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#else +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords); +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Common SSI operations */ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssi_lock, +#endif + .select = lm_spiselect, /* Provided externally by board logic */ + .setfrequency = ssi_setfrequency, + .setmode = ssi_setmode, + .setbits = ssi_setbits, + .status = lm_spistatus, /* Provided externally by board logic */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lm_spicmddata, +#endif + .send = ssi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = ssi_exchange, +#else + .sndblock = ssi_sndblock, + .recvblock = ssi_recvblock, +#endif +}; + +/* This supports is up to two SSI busses/ports */ + +static struct lm_ssidev_s g_ssidev[] = +{ +#ifndef CONFIG_SSI0_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI0_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI0, +#endif + }, +#endif +#ifndef CONFIG_SSI1_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI1_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI1, +#endif + }, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ssi_getreg + * + * Description: + * Read the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * + * Returned Value: + * Value of the register at this offset + * + ****************************************************************************/ + +static inline uint32_t ssi_getreg(struct lm_ssidev_s *priv, unsigned int offset) +{ +#if NSSI_ENABLED > 1 + return getreg32(priv->base + offset); +#else + return getreg32(SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_putreg + * + * Description: + * Write the value to the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * value - Value to write + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_putreg(struct lm_ssidev_s *priv, unsigned int offset, uint32_t value) +{ +#if NSSI_ENABLED > 1 + putreg32(value, priv->base + offset); +#else + putreg32(value, SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_disable + * + * Description: + * Disable SSI operation. NOTE: The SSI must be disabled before any control + * registers can be re-programmed. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * State of the SSI before the SSE was disabled + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_disable(struct lm_ssidev_s *priv) +{ + uint32_t retval; + uint32_t regval; + + retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval = (retval & ~SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); + return retval; +} + +/**************************************************************************** + * Name: ssi_enable + * + * Description: + * Restore the SSI operational state + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable) +{ + uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval &= ~SSI_CR1_SSE; + regval |= (enable & SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); +} + +/**************************************************************************** + * Name: ssi_semtake + * + * Description: + * Wait for a semaphore (handling interruption by signals); + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem) +{ + int ret; + do + { + ret = sem_wait(sem); + } + while (ret < 0 && errno == EINTR); + DEBUGASSERT(ret == 0); +} +#endif + +/**************************************************************************** + * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8 + * + * Description: + * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer + * pointer appropriately. The selected function dependes on (1) if there + * is a source txbuffer provided, and (2) if the number of bits per + * word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_txnull(struct lm_ssidev_s *priv) +{ + ssivdbg("TX: ->0xffff\n"); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); +} + +static void ssi_txuint16(struct lm_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->txbuffer; + ssivdbg("TX: %p->%04x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +static void ssi_txuint8(struct lm_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->txbuffer; + ssivdbg("TX: %p->%02x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +/**************************************************************************** + * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8 + * + * Description: + * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the + * user rxvbuffer and update the rxbuffer pointer appropriately. The + * selected function dependes on (1) if there is a desination rxbuffer + * provided, and (2) if the number of bits per word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_rxnull(struct lm_ssidev_s *priv) +{ +#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) + uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: discard %04x\n", regval); +#else + (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); +#endif +} + +static void ssi_rxuint16(struct lm_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->rxbuffer; + *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%04x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +static void ssi_rxuint8(struct lm_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->rxbuffer; + *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%02x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +/**************************************************************************** + * Name: ssi_txfifofull + * + * Description: + * Return true if the Tx FIFO is full + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not full + * + ****************************************************************************/ + +static inline bool ssi_txfifofull(struct lm_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; +} + +/**************************************************************************** + * Name: ssi_rxfifoempty + * + * Description: + * Return true if the Rx FIFO is empty + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not empty + * + ****************************************************************************/ + +static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; +} + +/**************************************************************************** + * Name: ssi_performtx + * + * Description: + * If the Tx FIFO is empty, then transfer as many words as we can to + * the FIFO. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * The number of words written to the Tx FIFO (a value from 0 to 8, + * inclusive). + * + ****************************************************************************/ + +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm_ssidev_s *priv) +{ + /* Check if the Tx FIFO is full and more data to transfer */ + + if (!ssi_txfifofull(priv) && priv->ntxwords > 0) + { + /* Transfer one word to the Tx FIFO */ + + priv->txword(priv); + priv->ntxwords--; + return 1; + } + return 0; +} + +#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +static int ssi_performtx(struct lm_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + int ntxd = 0; /* Number of words written to Tx FIFO */ + + /* Check if the Tx FIFO is full */ + + if (!ssi_txfifofull(priv)) + { + /* Not full.. Check if all of the Tx words have been sent */ + + if (priv->ntxwords > 0) + { + /* No.. Transfer more words until either the Tx FIFO is full or + * until all of the user provided data has been sent. + */ +#ifdef CONFIG_SSI_TXLIMIT + /* Further limit the number of words that we put into the Tx + * FIFO to CONFIG_SSI_TXLIMIT. Otherwise, we could + * overrun the Rx FIFO on a very fast SSI bus. + */ + for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++) +#else + for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++) +#endif + { + priv->txword(priv); + } + + /* Update the count of words to to transferred */ + + priv->ntxwords -= ntxd; + } + + /* Check again... Now have all of the Tx words been sent? */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords > 0) + { + /* No.. Enable the Tx FIFO interrupt. This interrupt occurs + * when the Tx FIFO is 1/2 full or less. + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_TX|SSI_RIS_ROR); +#else + regval |= SSI_IM_TX; +#endif + } + else + { + /* Yes.. Disable the Tx FIFO interrupt. The final stages of + * the transfer will be driven by Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_TX|SSI_RIS_ROR); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ + } + return ntxd; +} + +#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +/**************************************************************************** + * Name: ssi_performrx + * + * Description: + * Transfer as many bytes as possible from the Rx FIFO to the user Rx + * buffer (if one was provided). + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_performrx(struct lm_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + + /* Loop while data is available in the Rx FIFO */ + + while (!ssi_rxfifoempty(priv)) + { + /* Have all of the requested words been transferred from the Rx FIFO? */ + + if (priv->nrxwords < priv->nwords) + { + /* No.. Read more data from Rx FIFO */ + + priv->rxword(priv); + priv->nrxwords++; + } + } + + /* The Rx FIFO is now empty. While there is Tx data to be sent, the + * transfer will be driven by Tx FIFO interrupts. The final part + * of the transfer is driven by Rx FIFO interrupts only. + */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) + { + /* There are no more outgoing words to send, but there are + * additional incoming words expected (I would think that this + * a real corner case, be we will handle it with an extra + * interrupt, probably an Rx timeout). + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR); +#else + regval |= (SSI_IM_RX|SSI_IM_RT); +#endif + } + else + { + /* No.. there are either more Tx words to send or all Rx words + * have received. Disable Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_RX|SSI_IM_RT); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ +} + +/**************************************************************************** + * Name: ssi_transfer + * + * Description: + * Exchange a block data with the SPI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords) +{ +#ifndef CONFIG_SSI_POLLWAIT + irqstate_t flags; +#endif + int ntxd; + + ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords); + + /* Set up to perform the transfer */ + + priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */ + priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */ + priv->ntxwords = nwords; /* Number of words left to send */ + priv->nrxwords = 0; /* Number of words received */ + priv->nwords = nwords; /* Total number of exchanges */ + + /* Set up the low-level data transfer function pointers */ + + if (priv->nbits > 8) + { + priv->txword = ssi_txuint16; + priv->rxword = ssi_rxuint16; + } + else + { + priv->txword = ssi_txuint8; + priv->rxword = ssi_rxuint8; + } + + if (!txbuffer) + { + priv->txword = ssi_txnull; + } + + if (!rxbuffer) + { + priv->rxword = ssi_rxnull; + } + + /* Prime the Tx FIFO to start the sequence (saves one interrupt). + * At this point, all SSI interrupts should be disabled, but the + * operation of ssi_performtx() will set up the interrupts + * approapriately (if nwords > TxFIFO size). + */ + +#ifndef CONFIG_SSI_POLLWAIT + flags = irqsave(); + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + ntxd = ssi_performtx(priv); + + /* For the case where nwords < Tx FIFO size, ssi_performrx will + * configure interrupts correctly for the final phase of the + * the transfer. + */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Wait for the transfer to complete. Since there is no handshake + * with SPI, the following should complete even if there are problems + * with the transfer, so it should be safe with no timeout. + */ + + ssivdbg("Waiting for transfer complete\n"); + irqrestore(flags); + do + { + ssi_semtake(&priv->xfrsem); + } + while (priv->nrxwords < priv->nwords); + ssidbg("Transfer complete\n"); + +#else + /* Perform the transfer using polling logic. This will totally + * dominate the CPU until the transfer is complete. Only recommended + * if (1) your SPI is very fast, and (2) if you only use very short + * transfers. + */ + + do + { + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + /* If there are other threads at this same priority level, + * the following may help: + */ + + sched_yield(); + } + while (priv->nrxwords < priv->nwords); +#endif + return OK; +} + +/**************************************************************************** + * Name: ssi_mapirq + * + * Description: + * Map an IRQ number into the appropriate SSI device + * + * Input Parameters: + * irq - The IRQ number to be mapped + * + * Returned Value: + * On success, a reference to the private data structgure for this IRQ. + * NULL on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm_ssidev_s *ssi_mapirq(int irq) +{ + switch (irq) + { +#ifndef CONFIG_SSI0_DISABLE + case LM3S_IRQ_SSI0: + return &g_ssidev[SSI0_NDX]; +#endif +#ifndef CONFIG_SSI1_DISABLE + case LM3S_IRQ_SSI1: + return &g_ssidev[SSI1_NDX]; +#endif + default: + return NULL; + } +} +#endif + +/**************************************************************************** + * Name: ssi_interrupt + * + * Description: + * Exchange a block data with the SSI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static int ssi_interrupt(int irq, void *context) +{ + struct lm_ssidev_s *priv = ssi_mapirq(irq); + uint32_t regval; + int ntxd; + + DEBUGASSERT(priv != NULL); + + /* Clear pending interrupts */ + + regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); + ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); + + /* Check for Rx FIFO overruns */ + +#ifdef CONFIG_DEBUG + if ((regval & SSI_RIS_ROR) != 0) + { + lldbg("Rx FIFO Overrun!\n"); + } +#endif + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Check if the transfer is complete */ + + if (priv->nrxwords >= priv->nwords) + { + /* Yes.. Disable all SSI interrupt sources */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Wake up the waiting thread */ + + ssidbg("Transfer complete\n"); + ssi_semgive(&priv->xfrsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lm_ssidev_s *priv = (FAR struct lm_ssidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t frequency) +{ + uint32_t maxdvsr; + uint32_t cpsdvsr; + uint32_t regval; + uint32_t scr; + uint32_t actual; + + ssidbg("frequency: %d\n", frequency); + DEBUGASSERT(frequency); + + /* Has the frequency changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (frequency != priv->frequency) + { +#endif + /* "The serial bit rate is derived by dividing down the input clock + * (FSysClk). The clock is first divided by an even prescale value + * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale + * (SSI_CPSR) register ... The clock is further divided by a value + * from 1 to 256, which is 1 + SCR, where SCR is the value programmed + * i n the SSI Control0 (SSICR0) register ... + * + * "The frequency of the output clock SSIClk is defined by: + * + * "SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) + * + * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz, + * the module may not be able to operate at that speed. For master mode, + * the system clock must be at least two times faster than the SSIClk. + * For slave mode, the system clock must be at least 12 times faster + * than the SSIClk." + */ + + if (frequency > SYSCLK_FREQUENCY/2) + { + frequency = SYSCLK_FREQUENCY/2; + } + + /* Find optimal values for CPSDVSR and SCR. This loop is inefficient, + * but should not have to execute many times. + * + * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000. + * + * maxcvsr = 125 + * 1. cpsdvsr = 2, scr = 61 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (62)) = 403,226 + * + * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000. + * + * maxcvsr = 2 + * 1. cpsdvsr = 2, scr = 0 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (1)) = 25,000,000 + */ + + maxdvsr = SYSCLK_FREQUENCY / frequency; + cpsdvsr = 0; + do + { + cpsdvsr += 2; + scr = (maxdvsr / cpsdvsr) - 1; + } + while (scr > 255); + + /* Set CPDVSR */ + + DEBUGASSERT(cpsdvsr < 255); + ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); + + /* Set SCR */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_SCR_MASK; + regval |= (scr << SSI_CR0_SCR_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); + + /* Calcluate the actual frequency */ + + actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1)); + + /* Save the frequency selection so that subsequent reconfigurations will be + * faster. + */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; + } + return priv->actual; +#else + return actual; +#endif +} + +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + uint32_t enable; + uint32_t actual; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + actual = ssi_setfrequencyinternal(priv, frequency); + ssi_enable(priv, enable); + return actual; +} + +/**************************************************************************** + * Name: ssi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode) +{ + uint32_t modebits; + uint32_t regval; + + ssidbg("mode: %d\n", mode); + DEBUGASSERT(priv); + + /* Has the number of bits per word changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Select the CTL register bits based on the selected mode */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + modebits = 0; + break; + + case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + modebits = SSI_CR0_SPH; + break; + + case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + modebits = SSI_CR0_SPO; + break; + + case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + modebits = SSI_CR0_SPH|SSI_CR0_SPO; + break; + + default: + return; + } + + /* Then set the selected mode: Freescale SPI format, mode0-3 */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); + regval |= modebits; + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + /* Save the mode so that subsequent re-configuratins will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setmodeinternal(priv, mode); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits) +{ + uint32_t regval; + + ssidbg("nbits: %d\n", nbits); + DEBUGASSERT(priv); + if (nbits != priv->nbits && nbits >=4 && nbits <= 16) + { + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_DSS_MASK; + regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + priv->nbits = nbits; + } +} + +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setbitsinternal(priv, nbits); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s*)dev; + uint16_t response = 0; + + (void)ssi_transfer(priv, &wd, &response, 1); + return response; +} + +/**************************************************************************** + * Name: SPI_EXCHANGE + * + * Description: + * Exahange a block of data from SPI. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords); +} +#endif + +/************************************************************************* + * Name: ssi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + (void)ssi_transfer(priv, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: ssi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + struct lm_ssidev_s *priv = (struct lm_ssidev_s *)dev; + (void)ssi_transfer(priv, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize common parts the selected SPI port. Initialization of + * chip select GPIOs must have been performed by board specific logic + * prior to calling this function. Specifically: GPIOs should have + * been configured for output, and all chip selects disabled. + * + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, + * If multiple devices on on the bus, then multiple chip selects will be + * required. Theregore, all GPIO chip management is deferred to board- + * specific logic. + * + * Input Parameter: + * Port number (for hardware that has mutiple SSI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + struct lm_ssidev_s *priv; + irqstate_t flags; + uint8_t regval; + + ssidbg("port: %d\n", port); + + /* Set up for the selected port */ + + flags = irqsave(); + switch (port) + { +#ifndef CONFIG_SSI0_DISABLE + case 0: + /* Select SSI0 */ + + priv = &g_ssidev[SSI0_NDX]; + + /* Enable the SSI0 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI0; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the + * logic in this file makes no assumptions about chip select) + */ + + lm_configgpio(GPIO_SSI0_CLK); /* PA2: SSI0 clock (SSI0Clk) */ + /* lm_configgpio(GPIO_SSI0_FSS); PA3: SSI0 frame (SSI0Fss) */ + lm_configgpio(GPIO_SSI0_RX); /* PA4: SSI0 receive (SSI0Rx) */ + lm_configgpio(GPIO_SSI0_TX); /* PA5: SSI0 transmit (SSI0Tx) */ + break; +#endif /* CONFIG_SSI0_DISABLE */ + +#ifndef CONFIG_SSI1_DISABLE + case 1: + /* Select SSI0 */ + + priv = &g_ssidev[SSI1_NDX]; + + /* Enable the SSI1 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI1; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI1 GPIOs */ + + lm_configgpio(GPIO_SSI1_CLK); /* PE0: SSI1 clock (SSI1Clk) */ + /* lm_configgpio(GPIO_SSI1_FSS); PE1: SSI1 frame (SSI1Fss) */ + lm_configgpio(GPIO_SSI1_RX); /* PE2: SSI1 receive (SSI1Rx) */ + lm_configgpio(GPIO_SSI1_TX); /* PE3: SSI1 transmit (SSI1Tx) */ + break; +#endif /* CONFIG_SSI1_DISABLE */ + + default: + irqrestore(flags); + return NULL; + } + + /* Initialize the state structure */ + +#ifndef CONFIG_SSI_POLLWAIT + sem_init(&priv->xfrsem, 0, 0); +#endif +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + + /* Set all CR1 fields to reset state. This will be master mode. */ + + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); + + /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ + + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); + + /* Set the initial mode to mode 0. The application may override + * this initial setting using the setmode() method. + */ + + ssi_setmodeinternal(priv, SPIDEV_MODE0); + + /* Set the initial data width to 8-bits. The application may + * override this initial setting using the setbits() method. + */ + + ssi_setbitsinternal(priv, 8); + + /* Pick some initialize clock frequency. 400,000Hz is the startup + * MMC/SD frequency used for card detection. The application may + * override this setting using the setfrequency() method. + */ + + ssi_setfrequencyinternal(priv, 400000); + + /* Disable all SSI interrupt sources. They will be enabled only + * while there is an SSI transfer in progress. + */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Attach the interrupt */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + irq_attach(priv->irq, (xcpt_t)ssi_interrupt); +#else + irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + /* Enable the SSI for operation */ + + ssi_enable(priv, SSI_CR1_SSE); + + /* Enable SSI interrupts (They are still disabled at the source). */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(SSI_IRQ); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + irqrestore(flags); + return (FAR struct spi_dev_s *)priv; +} + +#endif /* NSSI_ENABLED > 0 */ diff --git a/nuttx/arch/arm/src/lm/lm_ssi.h b/nuttx/arch/arm/src/lm/lm_ssi.h index 4e7119898..07cd2ce77 100644 --- a/nuttx/arch/arm/src/lm/lm_ssi.h +++ b/nuttx/arch/arm/src/lm/lm_ssi.h @@ -73,20 +73,20 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * The external functions, lm3s_spiselect, lm3s_spistatus, and - * lm3s_spicmddata must be provided by board-specific logic. These are + * The external functions, lm_spiselect, lm_spistatus, and + * lm_spicmddata must be provided by board-specific logic. These are * implementations of the select, status, and cmddata methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All other methods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select + * 1. Provide logic in lm_boardinitialize() to configure SPI chip select * pins. - * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 2. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. These functions will perform chip selection and * status operations using GPIOs in the way your board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide - * the lm3s_spicmddata() function in your board-specific logic. This + * the lm_spicmddata() function in your board-specific logic. This * functions will perform cmd/data selection operations using GPIOs in * the way your board is configured. * 4. Add a call to up_spiinitialize() in your low level application @@ -100,10 +100,10 @@ extern "C" struct spi_dev_s; enum spi_dev_e; -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA -int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif #if defined(__cplusplus) diff --git a/nuttx/arch/arm/src/lm/lm_start.c b/nuttx/arch/arm/src/lm/lm_start.c new file mode 100644 index 000000000..f4985709e --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_start.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_start.c + * arch/arm/src/chip/lm_start.c + * + * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_lowputc.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern void lm_vectors(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + up_clockconfig(); + up_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + showprogress('B'); + + /* Move the intialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + showprogress('C'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + showprogress('D'); + + /* Initialize onboard resources */ + + lm_boardinitialize(); + showprogress('E'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + os_start(); + + /* Shoulnd't get here */ + + for(;;); +} diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.c b/nuttx/arch/arm/src/lm/lm_syscontrol.c new file mode 100644 index 000000000..f0d0bd3c9 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_syscontrol.c @@ -0,0 +1,315 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_syscontrol.c + * arch/arm/src/chip/lm_syscontrol.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "chip.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RCC_OSCMASK (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN) +#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2) +#define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK) +#define FAST_OSCDELAY (512*1024) +#define SLOW_OSCDELAY (4*1024) +#define PLLLOCK_DELAY (32*1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_delay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm_delay(uint32_t delay) +{ + __asm__ __volatile__("1:\n" + "\tsubs %0, #1\n" + "\tbne 1b\n" + : "=r"(delay) : "r"(delay)); +} + +/**************************************************************************** + * Name: lm_oscdelay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm_oscdelay(uint32_t rcc, uint32_t rcc2) +{ + /* Wait for the oscillator to stabilize. A smaller delay is used if the + * current clock rate is very slow. + */ + + uint32_t delay = FAST_OSCDELAY; + + /* Are we currently using RCC2? */ + + if ((rcc2 & SYSCON_RCC2_USERCC2) != 0) + { + uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK; + if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) || + (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ)) + { + delay = SLOW_OSCDELAY; + } + } + + /* No.. using srce in RCC */ + + else + { + uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK; + if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ) + { + delay = SLOW_OSCDELAY; + } + } + + /* Then delay that number of loops */ + + lm_delay(delay); +} + +/**************************************************************************** + * Name: lm_plllock + * + * Description: + * The new RCC values have been selected... wait for the PLL to lock on + * + ****************************************************************************/ + +static inline void lm_plllock(void) +{ + volatile uint32_t delay; + + /* Loop until the lock is achieved or until a timeout occurs */ + + for (delay = PLLLOCK_DELAY; delay > 0; delay--) + { + /* Check if the PLL is locked on */ + + if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) + { + /* Yes.. return now */ + + return; + } + } + + /* If we get here, then PLL lock was not achieved */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) +{ + uint32_t rcc; + uint32_t rcc2; + + /* Get the current values of the RCC and RCC2 registers */ + + rcc = getreg32(LM3S_SYSCON_RCC); + rcc2 = getreg32(LM3S_SYSCON_RCC2); + + /* Temporarily bypass the PLL and system clock dividers */ + + rcc |= SYSCON_RCC_BYPASS; + rcc &= ~(SYSCON_RCC_USESYSDIV); + putreg32(rcc, LM3S_SYSCON_RCC); + + rcc2 |= SYSCON_RCC2_BYPASS2; + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* We are probably using the main oscillator. The main oscillator is disabled on + * reset and so probably must be enabled here. The internal oscillator is enabled + * on rest and if that is selected, most likely nothing needs to be done. + */ + + if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) || + ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS))) + { + /* Enable any selected osciallators (but don't disable any yet) */ + + rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); + putreg32(rcc, LM3S_SYSCON_RCC); + + /* Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + */ + + lm_oscdelay(rcc, rcc2); + } + + /* Set the new crystal value, oscillator source and PLL configuration */ + + rcc &= ~RCC_XTALMASK; + rcc |= newrcc & RCC_XTALMASK; + + rcc2 &= ~RCC2_XTALMASK; + rcc2 |= newrcc2 & RCC2_XTALMASK; + + /* Clear the PLL lock interrupt */ + + putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); + + /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC + * is currently enabled. + */ + + if (rcc2 & SYSCON_RCC2_USERCC2) + { + putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc, LM3S_SYSCON_RCC); + } + else + { + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + } + + /* Wait for the new crystal value and oscillator source to take effect */ + + lm_delay(16); + + /* Set the requested system divider and disable the non-selected osciallators */ + + rcc &= ~RCC_DIVMASK; + rcc |= newrcc & RCC_DIVMASK; + + rcc2 &= ~RCC2_DIVMASK; + rcc2 |= newrcc2 & RCC2_DIVMASK; + + /* Will the PLL output be used to clock the system? */ + + if ((newrcc & SYSCON_RCC_BYPASS) == 0) + { + /* Yes, wail untill the PLL is locked */ + + lm_plllock(); + + /* Then enable the PLL */ + + rcc &= ~SYSCON_RCC_BYPASS; + rcc2 &= ~SYSCON_RCC2_BYPASS2; + } + + /* Now we can set the final RCC/RCC2 values */ + + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* Wait for the system divider to be effective */ + + lm_delay(6); +} + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void) +{ +#ifdef CONFIG_LM_REVA2 + /* Some early silicon returned an increase LDO voltage or 2.75V to work + * around a PLL bug + */ + + putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); +#endif + + /* Set the clocking to run with the default settings provided in the board.h + * header file + */ + + lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); +} + diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.h b/nuttx/arch/arm/src/lm/lm_syscontrol.h index 79cc2349d..98fbc81cb 100644 --- a/nuttx/arch/arm/src/lm/lm_syscontrol.h +++ b/nuttx/arch/arm/src/lm/lm_syscontrol.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lm/lm3s_syscontrol.h + * arch/arm/src/lm/lm_syscontrol.h * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -70,7 +70,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: lm3s_clockconfig + * Name: lm_clockconfig * * Description: * Called to change to new clock based on desired rcc and rcc2 settings. @@ -79,7 +79,7 @@ extern "C" * ****************************************************************************/ -void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); +void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2); /**************************************************************************** * Name: up_clockconfig diff --git a/nuttx/arch/arm/src/lm/lm_timerisr.c b/nuttx/arch/arm/src/lm/lm_timerisr.c new file mode 100644 index 000000000..0469a473b --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_timerisr.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/lm/lm_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h + * header file. + */ + +#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify taht the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(LM3S_IRQ_SYSTICK); +} diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S new file mode 100644 index 000000000..93350a9ff --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_vectors.S @@ -0,0 +1,805 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_vectors.S + * arch/arm/src/chip/lm_vectors.S + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/* Memory Map: + * + * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader) + * 0x0002:0000 - Address of vectors if using bootloader + * 0x0003:ffff - End of flash + * 0x2000:0000 - Start of SRAM and start of .data (_sdata) + * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap + * 0x2000:ffff - End of SRAM and end of heap + */ + +#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) + +/* The Cortex-M3 return from interrupt is unusual. We provide the following special + * address to the BX instruction. The particular value also forces a return to + * thread mode and covers state from the main stack point, the MSP (vs. the MSP). + */ + +#define EXC_RETURN 0xfffffff9 + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .globl __start + + .syntax unified + .thumb + .file "lm_vectors.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 + * registers on the stack, then branches to an instantantiation of the following + * macro. This macro simply loads the IRQ number into R0, then jumps to the common + * IRQ handling logic. + */ + + .macro HANDLER, label, irqno + .thumb_func +\label: + mov r0, #\irqno + b lm_irqcommon + .endm + +/************************************************************************************ + * Vectors + ************************************************************************************/ + + .section .vectors, "ax" + .code 16 + .align 2 + .globl lm_vectors + .type lm_vectors, function + +lm_vectors: + +/* Processor Exceptions */ + + .word IDLE_STACK /* Vector 0: Reset stack pointer */ + .word __start /* Vector 1: Reset vector */ + .word lm_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */ + .word lm_hardfault /* Vector 3: Hard fault */ + .word lm_mpu /* Vector 4: Memory management (MPU) */ + .word lm_busfault /* Vector 5: Bus fault */ + .word lm_usagefault /* Vector 6: Usage fault */ + .word lm_reserved /* Vector 7: Reserved */ + .word lm_reserved /* Vector 8: Reserved */ + .word lm_reserved /* Vector 9: Reserved */ + .word lm_reserved /* Vector 10: Reserved */ + .word lm_svcall /* Vector 11: SVC call */ + .word lm_dbgmonitor /* Vector 12: Debug monitor */ + .word lm_reserved /* Vector 13: Reserved */ + .word lm_pendsv /* Vector 14: Pendable system service request */ + .word lm_systick /* Vector 15: System tick */ + +/* External Interrupts */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + .word lm_gpioa /* Vector 16: GPIO Port A */ + .word lm_gpiob /* Vector 17: GPIO Port B */ + .word lm_gpioc /* Vector 18: GPIO Port C */ + .word lm_gpiod /* Vector 19: GPIO Port D */ + .word lm_gpioe /* Vector 20: GPIO Port E */ + .word lm_uart0 /* Vector 21: UART 0 */ + .word lm_uart1 /* Vector 22: UART 1 */ + .word lm_ssi0 /* Vector 23: SSI 0 */ + .word lm_i2c0 /* Vector 24: I2C 0 */ + .word lm_reserved /* Vector 25: Reserved */ + .word lm_reserved /* Vector 26: Reserved */ + .word lm_reserved /* Vector 27: Reserved */ + .word lm_reserved /* Vector 28: Reserved */ + .word lm_reserved /* Vector 29: Reserved */ + .word lm_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm_wdog /* Vector 34: Watchdog Timer */ + .word lm_tmr0a /* Vector 35: Timer 0 A */ + .word lm_tmr0b /* Vector 36: Timer 0 B */ + .word lm_tmr1a /* Vector 37: Timer 1 A */ + .word lm_tmr1b /* Vector 38: Timer 1 B */ + .word lm_tmr2a /* Vector 39: Timer 2 A */ + .word lm_tmr2b /* Vector 40: Timer 3 B */ + .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm_reserved /* Vector 43: Reserved */ + .word lm_syscon /* Vector 44: System Control */ + .word lm_flashcon /* Vector 45: FLASH Control */ + .word lm_gpiof /* Vector 46: GPIO Port F */ + .word lm_gpiog /* Vector 47: GPIO Port G */ + .word lm_gpioh /* Vector 48: GPIO Port H */ + .word lm_reserved /* Vector 49: Reserved */ + .word lm_ssi1 /* Vector 50: SSI 1 */ + .word lm_tmr3a /* Vector 51: Timer 3 A */ + .word lm_tmr3b /* Vector 52: Timer 3 B */ + .word lm_i2c1 /* Vector 53: I2C 1 */ + .word lm_reserved /* Vector 54: Reserved */ + .word lm_reserved /* Vector 55: Reserved */ + .word lm_reserved /* Vector 56: Reserved */ + .word lm_reserved /* Vector 57: Reserved */ + .word lm_eth /* Vector 58: Ethernet Controller */ + .word lm_hib /* Vector 59: Hibernation Module */ + .word lm_reserved /* Vector 60: Reserved */ + .word lm_reserved /* Vector 61: Reserved */ + .word lm_reserved /* Vector 62: Reserved */ + .word lm_reserved /* Vector 63: Reserved */ + .word lm_reserved /* Vector 64: Reserved */ + .word lm_reserved /* Vector 65: Reserved */ + .word lm_reserved /* Vector 66: Reserved */ + .word lm_reserved /* Vector 67: Reserved */ + .word lm_reserved /* Vector 68: Reserved */ + .word lm_reserved /* Vector 69: Reserved */ + .word lm_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + .word lm_gpioa /* Vector 16: GPIO Port A */ + .word lm_gpiob /* Vector 17: GPIO Port B */ + .word lm_gpioc /* Vector 18: GPIO Port C */ + .word lm_gpiod /* Vector 19: GPIO Port D */ + .word lm_gpioe /* Vector 20: GPIO Port E */ + .word lm_uart0 /* Vector 21: UART 0 */ + .word lm_uart1 /* Vector 22: UART 1 */ + .word lm_ssi0 /* Vector 23: SSI 0 */ + .word lm_i2c0 /* Vector 24: I2C 0 */ + .word lm_reserved /* Vector 25: Reserved */ + .word lm_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm_reserved /* Vector 27: Reserved */ + .word lm_reserved /* Vector 28: Reserved */ + .word lm_reserved /* Vector 29: Reserved */ + .word lm_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm_wdog /* Vector 34: Watchdog Timer */ + .word lm_tmr0a /* Vector 35: Timer 0 A */ + .word lm_tmr0b /* Vector 36: Timer 0 B */ + .word lm_tmr1a /* Vector 37: Timer 1 A */ + .word lm_tmr1b /* Vector 38: Timer 1 B */ + .word lm_tmr2a /* Vector 39: Timer 2 A */ + .word lm_tmr2b /* Vector 40: Timer 3 B */ + .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm_reserved /* Vector 43: Reserved */ + .word lm_syscon /* Vector 44: System Control */ + .word lm_flashcon /* Vector 45: FLASH Control */ + .word lm_gpiof /* Vector 46: GPIO Port F */ + .word lm_gpiog /* Vector 47: GPIO Port G */ + .word lm_reserved /* Vector 48: Reserved */ + .word lm_reserved /* Vector 49: Reserved */ + .word lm_reserved /* Vector 50: Reserved */ + .word lm_reserved /* Vector 51: Reserved */ + .word lm_reserved /* Vector 52: Reserved */ + .word lm_reserved /* Vector 53: Reserved */ + .word lm_reserved /* Vector 54: Reserved */ + .word lm_reserved /* Vector 55: Reserved */ + .word lm_reserved /* Vector 56: Reserved */ + .word lm_reserved /* Vector 57: Reserved */ + .word lm_eth /* Vector 58: Ethernet Controller */ + .word lm_reserved /* Vector 59: Reserved */ + .word lm_reserved /* Vector 60: Reserved */ + .word lm_reserved /* Vector 61: Reserved */ + .word lm_reserved /* Vector 62: Reserved */ + .word lm_reserved /* Vector 63: Reserved */ + .word lm_reserved /* Vector 64: Reserved */ + .word lm_reserved /* Vector 65: Reserved */ + .word lm_reserved /* Vector 66: Reserved */ + .word lm_reserved /* Vector 67: Reserved */ + .word lm_reserved /* Vector 68: Reserved */ + .word lm_reserved /* Vector 69: Reserved */ + .word lm_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + .word lm_gpioa /* Vector 16: GPIO Port A */ + .word lm_gpiob /* Vector 17: GPIO Port B */ + .word lm_gpioc /* Vector 18: GPIO Port C */ + .word lm_gpiod /* Vector 19: GPIO Port D */ + .word lm_gpioe /* Vector 20: GPIO Port E */ + .word lm_uart0 /* Vector 21: UART 0 */ + .word lm_uart1 /* Vector 22: UART 1 */ + .word lm_ssi0 /* Vector 23: SSI 0 */ + .word lm_i2c0 /* Vector 24: I2C 0 */ + .word lm_pwmfault /* Vector 25: PWM Fault */ + .word lm_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm_qei0 /* Vector 29: QEI0 */ + .word lm_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm_wdog /* Vector 34: Watchdog Timer */ + .word lm_tmr0a /* Vector 35: Timer 0 A */ + .word lm_tmr0b /* Vector 36: Timer 0 B */ + .word lm_tmr1a /* Vector 37: Timer 1 A */ + .word lm_tmr1b /* Vector 38: Timer 1 B */ + .word lm_tmr2a /* Vector 39: Timer 2 A */ + .word lm_tmr2b /* Vector 40: Timer 3 B */ + .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm_reserved /* Vector 43: Reserved */ + .word lm_syscon /* Vector 44: System Control */ + .word lm_flashcon /* Vector 45: FLASH Control */ + .word lm_gpiof /* Vector 46: GPIO Port F */ + .word lm_gpiog /* Vector 47: GPIO Port G */ + .word lm_reserved /* Vector 48: Reserved */ + .word lm_uart2 /* Vector 49: UART 2 */ + .word lm_reserved /* Vector 50: Reserved */ + .word lm_tmr3a /* Vector 51: Timer 3 A */ + .word lm_tmr3b /* Vector 52: Timer 3 B */ + .word lm_i2c1 /* Vector 53: I2C 1 */ + .word lm_qei1 /* Vector 54: QEI1 */ + .word lm_reserved /* Vector 55: Reserved */ + .word lm_reserved /* Vector 56: Reserved */ + .word lm_reserved /* Vector 57: Reserved */ + .word lm_eth /* Vector 58: Ethernet Controller */ + .word lm_hib /* Vector 59: Hibernation Module */ + .word lm_reserved /* Vector 60: Reserved */ + .word lm_reserved /* Vector 61: Reserved */ + .word lm_reserved /* Vector 62: Reserved */ + .word lm_reserved /* Vector 63: Reserved */ + .word lm_reserved /* Vector 64: Reserved */ + .word lm_reserved /* Vector 65: Reserved */ + .word lm_reserved /* Vector 66: Reserved */ + .word lm_reserved /* Vector 67: Reserved */ + .word lm_reserved /* Vector 68: Reserved */ + .word lm_reserved /* Vector 69: Reserved */ + .word lm_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + .word lm_gpioa /* Vector 16: GPIO Port A */ + .word lm_gpiob /* Vector 17: GPIO Port B */ + .word lm_gpioc /* Vector 18: GPIO Port C */ + .word lm_gpiod /* Vector 19: GPIO Port D */ + .word lm_gpioe /* Vector 20: GPIO Port E */ + .word lm_uart0 /* Vector 21: UART 0 */ + .word lm_uart1 /* Vector 22: UART 1 */ + .word lm_ssi0 /* Vector 23: SSI 0 */ + .word lm_i2c0 /* Vector 24: I2C 0 */ + .word lm_pwmfault /* Vector 25: PWM Fault */ + .word lm_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm_qei0 /* Vector 29: QEI0 */ + .word lm_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm_wdog /* Vector 34: Watchdog Timer */ + .word lm_tmr0a /* Vector 35: Timer 0 A */ + .word lm_tmr0b /* Vector 36: Timer 0 B */ + .word lm_tmr1a /* Vector 37: Timer 1 A */ + .word lm_tmr1b /* Vector 38: Timer 1 B */ + .word lm_tmr2a /* Vector 39: Timer 2 A */ + .word lm_tmr2b /* Vector 40: Timer 3 B */ + .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm_cmp2 /* Vector 43: Reserved */ + .word lm_syscon /* Vector 44: System Control */ + .word lm_flashcon /* Vector 45: FLASH Control */ + .word lm_gpiof /* Vector 46: GPIO Port F */ + .word lm_gpiog /* Vector 47: GPIO Port G */ + .word lm_gpioh /* Vector 48: GPIO Port H */ + .word lm_uart2 /* Vector 49: UART 2 */ + .word lm_ssi1 /* Vector 50: SSI 1 */ + .word lm_tmr3a /* Vector 51: Timer 3 A */ + .word lm_tmr3b /* Vector 52: Timer 3 B */ + .word lm_i2c1 /* Vector 53: I2C 1 */ + .word lm_qei1 /* Vector 54: QEI1 */ + .word lm_can0 /* Vector 55: CAN 0 */ + .word lm_can1 /* Vector 56: CAN 1 */ + .word lm_reserved /* Vector 57: Reserved */ + .word lm_eth /* Vector 58: Ethernet Controller */ + .word lm_reserved /* Vector 59: Reserved */ + .word lm_usb /* Vector 60: USB */ + .word lm_pwm3 /* Vector 61: PWM 3 */ + .word lm_udmasoft /* Vector 62: uDMA Software */ + .word lm_udmaerror /* Vector 63: uDMA Error */ + .word lm_adc1_0 /* Vector 64: ADC1 Sequence 0 */ + .word lm_adc1_1 /* Vector 65: ADC1 Sequence 1 */ + .word lm_adc1_2 /* Vector 66: ADC1 Sequence 2 */ + .word lm_adc1_3 /* Vector 67: ADC1 Sequence 3 */ + .word lm_i2s0 /* Vector 68: I2S 0 */ + .word lm_epi /* Vector 69: Reserved */ + .word lm_gpioj /* Vector 70: GPIO J */ + .word lm_reserved /* Vector 71: Reserved */ + #elif defined(CONFIG_ARCH_CHIP_LM3S8962) + .word lm_gpioa /* Vector 16: GPIO Port A */ + .word lm_gpiob /* Vector 17: GPIO Port B */ + .word lm_gpioc /* Vector 18: GPIO Port C */ + .word lm_gpiod /* Vector 19: GPIO Port D */ + .word lm_gpioe /* Vector 20: GPIO Port E */ + .word lm_uart0 /* Vector 21: UART 0 */ + .word lm_uart1 /* Vector 22: UART 1 */ + .word lm_ssi0 /* Vector 23: SSI 0 */ + .word lm_i2c0 /* Vector 24: I2C 0 */ + .word lm_pwmfault /* Vector 25: PWM Fault */ + .word lm_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm_qei0 /* Vector 29: QEI0 */ + .word lm_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm_wdog /* Vector 34: Watchdog Timer */ + .word lm_tmr0a /* Vector 35: Timer 0 A */ + .word lm_tmr0b /* Vector 36: Timer 0 B */ + .word lm_tmr1a /* Vector 37: Timer 1 A */ + .word lm_tmr1b /* Vector 38: Timer 1 B */ + .word lm_tmr2a /* Vector 39: Timer 2 A */ + .word lm_tmr2b /* Vector 40: Timer 3 B */ + .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm_reserved /* Vector 42: Reserved */ + .word lm_reserved /* Vector 43: Reserved */ + .word lm_syscon /* Vector 44: System Control */ + .word lm_flashcon /* Vector 45: FLASH Control */ + .word lm_gpiof /* Vector 46: GPIO Port F */ + .word lm_gpiog /* Vector 47: GPIO Port G */ + .word lm_reserved /* Vector 48: Reserved */ + .word lm_reserved /* Vector 49: Reserved */ + .word lm_reserved /* Vector 50: Reserved */ + .word lm_tmr3a /* Vector 51: Timer 3 A */ + .word lm_tmr3b /* Vector 52: Timer 3 B */ + .word lm_reserved /* Vector 53: Reserved*/ + .word lm_qei1 /* Vector 54: QEI1 */ + .word lm_can0 /* Vector 55: Can Controller */ + .word lm_reserved /* Vector 56: Reserved */ + .word lm_reserved /* Vector 57: Reserved */ + .word lm_eth /* Vector 58: Ethernet Controller */ + .word lm_hib /* Vector 59: Hibernation Module */ + .word lm_reserved /* Vector 60: Reserved */ + .word lm_reserved /* Vector 61: Reserved */ + .word lm_reserved /* Vector 62: Reserved */ + .word lm_reserved /* Vector 63: Reserved */ + .word lm_reserved /* Vector 64: Reserved */ + .word lm_reserved /* Vector 65: Reserved */ + .word lm_reserved /* Vector 66: Reserved */ + .word lm_reserved /* Vector 67: Reserved */ + .word lm_reserved /* Vector 68: Reserved */ + .word lm_reserved /* Vector 69: Reserved */ + .word lm_reserved /* Vector 70: Reserved */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + .size lm_vectors, .-lm_vectors + +/************************************************************************************ + * .text + ************************************************************************************/ + + .text + .type handlers, function + .thumb_func +handlers: + HANDLER lm_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ + HANDLER lm_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ + HANDLER lm_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ + HANDLER lm_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ + HANDLER lm_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ + HANDLER lm_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ + HANDLER lm_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ + HANDLER lm_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ + HANDLER lm_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ + HANDLER lm_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ + HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) + HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ + HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ + HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ + HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ + HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_usb, LM3S_IRQ_USB /* Vector 60: USB */ + HANDLER lm_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ + HANDLER lm_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ + HANDLER lm_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ + HANDLER lm_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ + HANDLER lm_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ + HANDLER lm_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ + HANDLER lm_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ + HANDLER lm_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ + HANDLER lm_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ + HANDLER lm_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: + * + * REG_XPSR + * REG_R15 + * REG_R14 + * REG_R12 + * REG_R3 + * REG_R2 + * REG_R1 + * MSP->REG_R0 + * + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP + */ + +lm_irqcommon: + + /* Complete the context save */ + +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else + mrs r1, msp /* R1=The main stack pointer */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ + mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else + stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif + + /* Disable interrupts, select the stack to use for interrupt handling + * and call up_doirq to handle the interrupt + */ + + cpsid i /* Disable further interrupts */ + + /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt + * stack pointer. The way that this is done here prohibits nested interrupts! + * Otherwise, we will re-use the main stack for interrupt level processing. + */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + ldr sp, =g_intstackbase + str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ +#else + mov sp, r1 /* We are using the main stack pointer */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + mov r1, sp /* Recover R1=main stack pointer */ +#endif + + /* On return from up_doirq, R0 will hold a pointer to register context + * array to use for the interrupt return. If that return value is the same + * as current stack pointer, then things are relatively easy. + */ + + cmp r0, r1 /* Context switch? */ + beq 1f /* Branch if no context switch */ + + /* We are returning with a pending context switch. This case is different + * because in this case, the register save structure does not lie on the + * stack but, rather, are within a TCB structure. We'll have to copy some + * values to the stack. + */ + + add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ + ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ + ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ + stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif + b 2f /* Re-join common logic */ + + /* We are returning with no context switch. We simply need to "unwind" + * the same stack frame that we created + */ +1: +#ifdef CONFIG_NUTTX_KERNEL + ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif +2: +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else + msr msp, r1 /* Recover the return MSP value */ + + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). + */ + + ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + + msr primask, r3 /* Restore interrupts */ + + /* Always return with R14 containing the special value that will: (1) + * return to thread mode, and (2) continue to use the MSP + */ + + bx r14 /* And return */ + .size handlers, .-handlers + +/************************************************************************************ + * Name: up_interruptstack/g_intstackbase + * + * Description: + * Shouldn't happen + * + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .global g_intstackbase + .align 4 +up_interruptstack: + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) +g_intstackbase: + .size up_interruptstack, .-up_interruptstack +#endif + +/************************************************************************************ + * .rodata + ************************************************************************************/ + + .section .rodata, "a" + +/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end + * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS + * and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that + * the system boots on and, eventually, becomes the idle, do nothing task that runs + * only when there is nothing else to run. The heap continues from there until the + * end of memory. See g_heapbase below. + */ + + .globl g_heapbase + .type g_heapbase, object +g_heapbase: + .long _ebss+CONFIG_IDLETHREAD_STACKSIZE + .size g_heapbase, .-g_heapbase + + .end diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt index 3f9da652b..378f5a25b 100644 --- a/nuttx/configs/eagle100/README.txt +++ b/nuttx/configs/eagle100/README.txt @@ -334,15 +334,15 @@ Eagle100-specific Configuration Options Additional interrupt support can be disabled if desired to reduce memory footprint. - CONFIG_LM3S_DISABLE_GPIOA_IRQS=n - CONFIG_LM3S_DISABLE_GPIOB_IRQS=n - CONFIG_LM3S_DISABLE_GPIOC_IRQS=n - CONFIG_LM3S_DISABLE_GPIOD_IRQS=n - CONFIG_LM3S_DISABLE_GPIOE_IRQS=n - CONFIG_LM3S_DISABLE_GPIOF_IRQS=n - CONFIG_LM3S_DISABLE_GPIOG_IRQS=n - CONFIG_LM3S_DISABLE_GPIOH_IRQS=y - CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y + CONFIG_LM_DISABLE_GPIOA_IRQS=n + CONFIG_LM_DISABLE_GPIOB_IRQS=n + CONFIG_LM_DISABLE_GPIOC_IRQS=n + CONFIG_LM_DISABLE_GPIOD_IRQS=n + CONFIG_LM_DISABLE_GPIOE_IRQS=n + CONFIG_LM_DISABLE_GPIOF_IRQS=n + CONFIG_LM_DISABLE_GPIOG_IRQS=n + CONFIG_LM_DISABLE_GPIOH_IRQS=y + CONFIG_LM_DISABLE_GPIOJ_IRQS=y LM3S6818 specific device driver settings @@ -367,18 +367,18 @@ Eagle100-specific Configuration Options value is large, then larger values of this setting may cause Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). - CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET) + CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) to build the LM3S Ethernet driver - CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. - CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide + CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. + CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. - CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation - CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation - CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding - CONFIG_LM3S_MULTICAST - Set to enable multicast frames - CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode - CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection. - CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console. + CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation + CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation + CONFIG_LM_ETHNOPAD - Set to suppress Tx padding + CONFIG_LM_MULTICAST - Set to enable multicast frames + CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode + CONFIG_LM_BADCRC - Set to enable bad CRC rejection. + CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console. Configurations ^^^^^^^^^^^^^^ diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig index cf4f97930..bd0ac7664 100644 --- a/nuttx/configs/eagle100/httpd/defconfig +++ b/nuttx/configs/eagle100/httpd/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/eagle100/include/board.h b/nuttx/configs/eagle100/include/board.h index 40a12327f..597f801ac 100644 --- a/nuttx/configs/eagle100/include/board.h +++ b/nuttx/configs/eagle100/include/board.h @@ -112,7 +112,7 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -121,21 +121,21 @@ * ************************************************************************************/ -extern void lm3s_boardinitialize(void); +extern void lm_boardinitialize(void); /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC +#ifdef CONFIG_LM_BOARDMAC struct ether_addr; -extern void lm3s_ethernetmac(struct ether_addr *ethaddr); +extern void lm_ethernetmac(struct ether_addr *ethaddr); #endif #endif /* __ASSEMBLY__ */ diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig index a3b50ead6..9b1f616c6 100644 --- a/nuttx/configs/eagle100/nettest/defconfig +++ b/nuttx/configs/eagle100/nettest/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig index 342023d6a..079bbc60e 100644 --- a/nuttx/configs/eagle100/nsh/defconfig +++ b/nuttx/configs/eagle100/nsh/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig index fe02ab4b9..110f906cb 100644 --- a/nuttx/configs/eagle100/nxflat/defconfig +++ b/nuttx/configs/eagle100/nxflat/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig index 52496c4a3..6d3b4ddad 100644 --- a/nuttx/configs/eagle100/ostest/defconfig +++ b/nuttx/configs/eagle100/ostest/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h index d8bcd6a81..8a76e2eb5 100644 --- a/nuttx/configs/eagle100/src/eagle100_internal.h +++ b/nuttx/configs/eagle100/src/eagle100_internal.h @@ -81,14 +81,14 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Eagle100 board. * ************************************************************************************/ -extern void weak_function lm3s_ssiinitialize(void); +extern void weak_function lm_ssiinitialize(void); /**************************************************************************** * Name: up_ledinit diff --git a/nuttx/configs/eagle100/src/up_boot.c b/nuttx/configs/eagle100/src/up_boot.c index 44f003e0b..8fed389f8 100644 --- a/nuttx/configs/eagle100/src/up_boot.c +++ b/nuttx/configs/eagle100/src/up_boot.c @@ -60,7 +60,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -68,18 +68,18 @@ * and mapped but before any devices have been initialized. ************************************************************************************/ -void lm3s_boardinitialize(void) +void lm_boardinitialize(void) { /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. + * lm_ssiinitialize() has been brought into the link. */ /* The Eagle100 microSD CS is on SSI0 */ #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) + if (lm_ssiinitialize) { - lm3s_ssiinitialize(); + lm_ssiinitialize(); } #endif diff --git a/nuttx/configs/eagle100/src/up_ethernet.c b/nuttx/configs/eagle100/src/up_ethernet.c index a071fcca9..42876b3b5 100644 --- a/nuttx/configs/eagle100/src/up_ethernet.c +++ b/nuttx/configs/eagle100/src/up_ethernet.c @@ -63,17 +63,17 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) +#ifdef CONFIG_LM_BOARDMAC +void lm_ethernetmac(struct ether_addr *ethaddr) { uint32_t user0; uint32_t user1; diff --git a/nuttx/configs/eagle100/src/up_leds.c b/nuttx/configs/eagle100/src/up_leds.c index 0124b964b..5566b58b2 100644 --- a/nuttx/configs/eagle100/src/up_leds.c +++ b/nuttx/configs/eagle100/src/up_leds.c @@ -72,7 +72,7 @@ /* Dump GPIO registers */ #ifdef LED_DEBUG -# define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m) +# define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m) #else # define led_dumpgpio(m) #endif @@ -106,9 +106,9 @@ void up_ledinit(void) /* Configure Port E, Bit 1 as an output, initial value=OFF */ - led_dumpgpio("up_ledinit before lm3s_configgpio()"); - lm3s_configgpio(LED_GPIO); - led_dumpgpio("up_ledinit after lm3s_configgpio()"); + led_dumpgpio("up_ledinit before lm_configgpio()"); + lm_configgpio(LED_GPIO); + led_dumpgpio("up_ledinit after lm_configgpio()"); g_nest = 0; } @@ -132,9 +132,9 @@ void up_ledon(int led) g_nest++; case LED_IRQSENABLED: case LED_STACKCREATED: - led_dumpgpio("up_ledon: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, false); - led_dumpgpio("up_ledon: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledon: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, false); + led_dumpgpio("up_ledon: after lm_gpiowrite()"); break; } } @@ -160,9 +160,9 @@ void up_ledoff(int led) case LED_PANIC: if (--g_nest <= 0) { - led_dumpgpio("up_ledoff: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, true); - led_dumpgpio("up_ledoff: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledoff: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, true); + led_dumpgpio("up_ledoff: after lm_gpiowrite()"); } break; } diff --git a/nuttx/configs/eagle100/src/up_ssi.c b/nuttx/configs/eagle100/src/up_ssi.c index b78a0d67c..c18cf52a5 100644 --- a/nuttx/configs/eagle100/src/up_ssi.c +++ b/nuttx/configs/eagle100/src/up_ssi.c @@ -81,7 +81,7 @@ /* Dump GPIO registers */ #ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +# define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m) #else # define ssi_dumpgpio(m) #endif @@ -95,30 +95,30 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Eagle100 board. * ************************************************************************************/ -void weak_function lm3s_ssiinitialize(void) +void weak_function lm_ssiinitialize(void) { /* Configure the SPI-based microSD CS GPIO */ - ssi_dumpgpio("lm3s_ssiinitialize() before lm3s_configgpio()"); - lm3s_configgpio(SDCCS_GPIO); - ssi_dumpgpio("lm3s_ssiinitialize() after lm3s_configgpio()"); + ssi_dumpgpio("lm_ssiinitialize() before lm_configgpio()"); + lm_configgpio(SDCCS_GPIO); + ssi_dumpgpio("lm_ssiinitialize() after lm_configgpio()"); } /**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * The external functions, lm_spiselect and lm_spistatus must be provided * by board-specific logic. The are implementations of the select and status * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All othermethods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 1. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. This function will perform chip selection and * status operations using GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization @@ -130,20 +130,20 @@ void weak_function lm3s_ssiinitialize(void) * ****************************************************************************/ -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_MMCSD) { /* Assert the CS pin to the card */ - ssi_dumpgpio("lm3s_spiselect() before lm3s_gpiowrite()"); - lm3s_gpiowrite(SDCCS_GPIO, !selected); - ssi_dumpgpio("lm3s_spiselect() after lm3s_gpiowrite()"); + ssi_dumpgpio("lm_spiselect() before lm_gpiowrite()"); + lm_gpiowrite(SDCCS_GPIO, !selected); + ssi_dumpgpio("lm_spiselect() after lm_gpiowrite()"); } } -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { ssidbg("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig index 7efbbed11..2aca2582e 100644 --- a/nuttx/configs/eagle100/thttpd/defconfig +++ b/nuttx/configs/eagle100/thttpd/defconfig @@ -58,21 +58,21 @@ CONFIG_ARCH_CALIBRATION=n # Disable support for interrupts on GPIOJ which does not # exist on the LM3S6918. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=n -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=n +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART0_TXBUFSIZE=256 @@ -99,16 +99,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6918 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt index f7896118e..78f7f7b8c 100644 --- a/nuttx/configs/ekk-lm3s9b96/README.txt +++ b/nuttx/configs/ekk-lm3s9b96/README.txt @@ -102,12 +102,12 @@ GNU Toolchain Options the CodeSourcery or devkitARM, you simply need to add one of the following configuration options to your .config (or defconfig) file: - CONFIG_LM3S_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_LM3S_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_LM3S_DEVKITARM=y : devkitARM under Windows - CONFIG_LM3S_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_LM_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LM_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_LM_DEVKITARM=y : devkitARM under Windows + CONFIG_LM_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify + If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. @@ -352,15 +352,15 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options Additional interrupt support can be disabled if desired to reduce memory footprint. - CONFIG_LM3S_DISABLE_GPIOA_IRQS=n - CONFIG_LM3S_DISABLE_GPIOB_IRQS=n - CONFIG_LM3S_DISABLE_GPIOC_IRQS=n - CONFIG_LM3S_DISABLE_GPIOD_IRQS=n - CONFIG_LM3S_DISABLE_GPIOE_IRQS=n - CONFIG_LM3S_DISABLE_GPIOF_IRQS=n - CONFIG_LM3S_DISABLE_GPIOG_IRQS=n - CONFIG_LM3S_DISABLE_GPIOH_IRQS=n - CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y + CONFIG_LM_DISABLE_GPIOA_IRQS=n + CONFIG_LM_DISABLE_GPIOB_IRQS=n + CONFIG_LM_DISABLE_GPIOC_IRQS=n + CONFIG_LM_DISABLE_GPIOD_IRQS=n + CONFIG_LM_DISABLE_GPIOE_IRQS=n + CONFIG_LM_DISABLE_GPIOF_IRQS=n + CONFIG_LM_DISABLE_GPIOG_IRQS=n + CONFIG_LM_DISABLE_GPIOH_IRQS=n + CONFIG_LM_DISABLE_GPIOJ_IRQS=y LM3S6818 specific device driver settings @@ -385,18 +385,18 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options value is large, then larger values of this setting may cause Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). - CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET) + CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) to build the LM3S Ethernet driver - CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. - CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide + CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. + CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. - CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation - CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation - CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding - CONFIG_LM3S_MULTICAST - Set to enable multicast frames - CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode - CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection. - CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console. + CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation + CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation + CONFIG_LM_ETHNOPAD - Set to suppress Tx padding + CONFIG_LM_MULTICAST - Set to enable multicast frames + CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode + CONFIG_LM_BADCRC - Set to enable bad CRC rejection. + CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console. Configurations ^^^^^^^^^^^^^^ diff --git a/nuttx/configs/ekk-lm3s9b96/include/board.h b/nuttx/configs/ekk-lm3s9b96/include/board.h index 2e6cd93f1..f5c997539 100644 --- a/nuttx/configs/ekk-lm3s9b96/include/board.h +++ b/nuttx/configs/ekk-lm3s9b96/include/board.h @@ -113,7 +113,7 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -122,21 +122,21 @@ * ************************************************************************************/ -extern void lm3s_boardinitialize(void); +extern void lm_boardinitialize(void); /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC +#ifdef CONFIG_LM_BOARDMAC struct ether_addr; -extern void lm3s_ethernetmac(struct ether_addr *ethaddr); +extern void lm_ethernetmac(struct ether_addr *ethaddr); #endif #endif /* __ASSEMBLY__ */ diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig index b614c0316..adb9bb5fa 100644 --- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig @@ -57,32 +57,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=n +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=y +CONFIG_LM_DFU=y # # Disable support for interrupts on GPIOH and GPIOJ which do not # exist on the LM3S6B96. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6B96 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n @@ -116,16 +116,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6B96 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=n -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=n +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig index df5622360..821502036 100644 --- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig @@ -57,32 +57,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=n +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=y +CONFIG_LM_DFU=y # # Disable support for interrupts on GPIOH and GPIOJ which do not # exist on the LM3S6B96. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6B96 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n @@ -116,16 +116,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6B96 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h index 17b0d0e27..d7ab916c8 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h +++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h @@ -102,14 +102,14 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. * ************************************************************************************/ -extern void weak_function lm3s_ssiinitialize(void); +extern void weak_function lm_ssiinitialize(void); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_EKK_LM3S9B96_SRC_EKKLM3S9B96_INTERNAL_H */ diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c index 528d150e1..16057ccb9 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c @@ -62,7 +62,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -70,16 +70,16 @@ * and mapped but before any devices have been initialized. ************************************************************************************/ -void lm3s_boardinitialize(void) +void lm_boardinitialize(void) { /* Configure chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. + * lm_ssiinitialize() has been brought into the link. */ #if !defined(CONFIG_SSI0_DISABLE) || !defined(CONFIG_SSI1_DISABLE) - if (lm3s_ssiinitialize) + if (lm_ssiinitialize) { - lm3s_ssiinitialize(); + lm_ssiinitialize(); } #endif diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c index a1963f0d5..bc4149082 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c @@ -64,17 +64,17 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) +#ifdef CONFIG_LM_BOARDMAC +void lm_ethernetmac(struct ether_addr *ethaddr) { uint32_t user0; uint32_t user1; diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c index 7628fcfe0..e6abe1a8a 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_leds.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_leds.c @@ -73,7 +73,7 @@ /* Dump GPIO registers */ #ifdef LED_DEBUG -# define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m) +# define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m) #else # define led_dumpgpio(m) #endif @@ -103,9 +103,9 @@ void up_ledinit(void) /* Configure Port D, Bit 0 as an output, initial value=OFF */ - led_dumpgpio("up_ledinit before lm3s_configgpio()"); - lm3s_configgpio(LED_GPIO); - led_dumpgpio("up_ledinit after lm3s_configgpio()"); + led_dumpgpio("up_ledinit before lm_configgpio()"); + lm_configgpio(LED_GPIO); + led_dumpgpio("up_ledinit after lm_configgpio()"); g_nest = 0; } @@ -129,9 +129,9 @@ void up_ledon(int led) g_nest++; case LED_IRQSENABLED: case LED_STACKCREATED: - led_dumpgpio("up_ledon: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, false); - led_dumpgpio("up_ledon: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledon: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, false); + led_dumpgpio("up_ledon: after lm_gpiowrite()"); break; } } @@ -157,9 +157,9 @@ void up_ledoff(int led) case LED_PANIC: if (--g_nest <= 0) { - led_dumpgpio("up_ledoff: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, true); - led_dumpgpio("up_ledoff: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledoff: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, true); + led_dumpgpio("up_ledoff: after lm_gpiowrite()"); } break; } diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c index 8f297e7a7..d7ee0ef16 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_ssi.c @@ -81,7 +81,7 @@ #ifdef SSI_VERBOSE #if 0 -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +# define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m) #endif #else # define ssi_dumpgpio(m) @@ -96,31 +96,31 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure chip select GPIO pins for the LM3S9B96 Eval board. * ************************************************************************************/ -void weak_function lm3s_ssiinitialize(void) +void weak_function lm_ssiinitialize(void) { /* Configure the CS GPIO */ #if 0 - ssi_dumpgpio("lm3s_ssiinitialize() Entry"); - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); + ssi_dumpgpio("lm_ssiinitialize() Entry"); + ssi_dumpgpio("lm_ssiinitialize() Exit"); #endif } #if 0 /**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * The external functions, lm_spiselect and lm_spistatus must be provided * by board-specific logic. The are implementations of the select and status * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All othermethods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 1. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. This function will perform chip selection and * status operations using GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization @@ -132,28 +132,28 @@ void weak_function lm3s_ssiinitialize(void) * ****************************************************************************/ -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); + ssi_dumpgpio("lm_spiselect() Entry"); if (devid == SPIDEV_MMCSD) { /* Assert the CS pin to the card */ - lm3s_gpiowrite(SDCCS_GPIO, !selected); + lm_gpiowrite(SDCCS_GPIO, !selected); } #ifdef CONFIG_NX_LCDDRIVER else if (devid == SPIDEV_DISPLAY) { /* Assert the CS pin to the display */ - lm3s_gpiowrite(OLEDCS_GPIO, !selected); + lm_gpiowrite(OLEDCS_GPIO, !selected); } #endif - ssi_dumpgpio("lm3s_spiselect() Exit"); + ssi_dumpgpio("lm_spiselect() Exit"); } -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { ssidbg("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt index 669708c16..29cf80fae 100644 --- a/nuttx/configs/lm3s6432-s2e/README.txt +++ b/nuttx/configs/lm3s6432-s2e/README.txt @@ -97,12 +97,12 @@ GNU Toolchain Options To use a specific toolchain, you simply need to add one of the following configuration options to your .config (or defconfig) file: - CONFIG_LM3S_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_LM3S_CODESOURCERYL=y : CodeSourcery under Linux or on Mac OS X. - CONFIG_LM3S_DEVKITARM=y : devkitARM under Windows - CONFIG_LM3S_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_LM_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LM_CODESOURCERYL=y : CodeSourcery under Linux or on Mac OS X. + CONFIG_LM_DEVKITARM=y : devkitARM under Windows + CONFIG_LM_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify + If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. @@ -346,15 +346,15 @@ Stellaris MDL-S2E Reference Design Configuration Options Additional interrupt support can be disabled if desired to reduce memory footprint - GPIOs C-G are not pinned out on the MDL-S2E board. - CONFIG_LM3S_DISABLE_GPIOA_IRQS=n - CONFIG_LM3S_DISABLE_GPIOB_IRQS=n - CONFIG_LM3S_DISABLE_GPIOC_IRQS=y - CONFIG_LM3S_DISABLE_GPIOD_IRQS=y - CONFIG_LM3S_DISABLE_GPIOE_IRQS=y - CONFIG_LM3S_DISABLE_GPIOF_IRQS=y - CONFIG_LM3S_DISABLE_GPIOG_IRQS=y - CONFIG_LM3S_DISABLE_GPIOH_IRQS=y - CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y + CONFIG_LM_DISABLE_GPIOA_IRQS=n + CONFIG_LM_DISABLE_GPIOB_IRQS=n + CONFIG_LM_DISABLE_GPIOC_IRQS=y + CONFIG_LM_DISABLE_GPIOD_IRQS=y + CONFIG_LM_DISABLE_GPIOE_IRQS=y + CONFIG_LM_DISABLE_GPIOF_IRQS=y + CONFIG_LM_DISABLE_GPIOG_IRQS=y + CONFIG_LM_DISABLE_GPIOH_IRQS=y + CONFIG_LM_DISABLE_GPIOJ_IRQS=y LM3S6432 specific device driver settings @@ -388,18 +388,18 @@ Stellaris MDL-S2E Reference Design Configuration Options value is large, then larger values of this setting may cause Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). - CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET) + CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) to build the LM3S Ethernet driver - CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. - CONFIG_LM3S_BOARDMAC - This should be set in order to use the + CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. + CONFIG_LM_BOARDMAC - This should be set in order to use the MAC address configured in the flash USER registers. - CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation - CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation - CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding - CONFIG_LM3S_MULTICAST - Set to enable multicast frames - CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode - CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection. - CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console. + CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation + CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation + CONFIG_LM_ETHNOPAD - Set to suppress Tx padding + CONFIG_LM_MULTICAST - Set to enable multicast frames + CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode + CONFIG_LM_BADCRC - Set to enable bad CRC rejection. + CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console. Configurations ^^^^^^^^^^^^^^ diff --git a/nuttx/configs/lm3s6432-s2e/include/board.h b/nuttx/configs/lm3s6432-s2e/include/board.h index 06504ec4f..7fdcabf76 100644 --- a/nuttx/configs/lm3s6432-s2e/include/board.h +++ b/nuttx/configs/lm3s6432-s2e/include/board.h @@ -114,7 +114,7 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -123,21 +123,21 @@ * ************************************************************************************/ -extern void lm3s_boardinitialize(void); +extern void lm_boardinitialize(void); /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the MDL-S2E Reference Design, the MAC address will be stored in the - * non-volatile USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, + * non-volatile USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, * this function will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC +#ifdef CONFIG_LM_BOARDMAC struct ether_addr; -extern void lm3s_ethernetmac(struct ether_addr *ethaddr); +extern void lm_ethernetmac(struct ether_addr *ethaddr); #endif #endif /* __ASSEMBLY__ */ diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig index edd61eacc..a09bc6717 100644 --- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig +++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig @@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=y -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=n +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=y +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=n # # Disable support for interrupts on GPIOs which do not # exist on the LM3S6432 or are not pinned anywhere useful # on the S2E. # -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=y -CONFIG_LM3S_DISABLE_GPIOD_IRQS=y -CONFIG_LM3S_DISABLE_GPIOE_IRQS=y -CONFIG_LM3S_DISABLE_GPIOF_IRQS=y -CONFIG_LM3S_DISABLE_GPIOG_IRQS=y -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=y +CONFIG_LM_DISABLE_GPIOD_IRQS=y +CONFIG_LM_DISABLE_GPIOE_IRQS=y +CONFIG_LM_DISABLE_GPIOF_IRQS=y +CONFIG_LM_DISABLE_GPIOG_IRQS=y +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6432 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=y -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=y +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=n CONFIG_UART1_SERIAL_CONSOLE=y CONFIG_UART2_SERIAL_CONSOLE=n @@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6432 specific ethernet device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig index 2d32db81c..9387fd086 100644 --- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig +++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig @@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=y -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=n +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=y +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=n # # Disable support for interrupts on GPIOs which do not # exist on the LM3S6432 or are not pinned anywhere useful # on the S2E. # -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=y -CONFIG_LM3S_DISABLE_GPIOD_IRQS=y -CONFIG_LM3S_DISABLE_GPIOE_IRQS=y -CONFIG_LM3S_DISABLE_GPIOF_IRQS=y -CONFIG_LM3S_DISABLE_GPIOG_IRQS=y -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=y +CONFIG_LM_DISABLE_GPIOD_IRQS=y +CONFIG_LM_DISABLE_GPIOE_IRQS=y +CONFIG_LM_DISABLE_GPIOF_IRQS=y +CONFIG_LM_DISABLE_GPIOG_IRQS=y +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S6432 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=y -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=y +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=n CONFIG_UART1_SERIAL_CONSOLE=y CONFIG_UART2_SERIAL_CONSOLE=n @@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S6432 specific ethernet device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h index f54403c7a..f95b118ad 100644 --- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h +++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h @@ -112,14 +112,14 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the MDL-S2E. * ************************************************************************************/ -extern void weak_function lm3s_ssiinitialize(void); +extern void weak_function lm_ssiinitialize(void); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LM3S6432_S2E_SRC_LM3S6432S2E_INTERNAL_H */ diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c index 184529638..da900282f 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c @@ -54,7 +54,7 @@ * Definitions ************************************************************************************/ -#if defined(CONFIG_LM3S_UART1) && !defined(CONFIG_SSI0_DISABLE) +#if defined(CONFIG_LM_UART1) && !defined(CONFIG_SSI0_DISABLE) # error Only one of UART1 and SSI0 can be enabled on this board. #endif @@ -67,7 +67,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -75,16 +75,16 @@ * and mapped but before any devices have been initialized. ************************************************************************************/ -void lm3s_boardinitialize(void) +void lm_boardinitialize(void) { /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. + * lm_ssiinitialize() has been brought into the link. */ #if !defined(CONFIG_SSI0_DISABLE) - if (lm3s_ssiinitialize) + if (lm_ssiinitialize) { - lm3s_ssiinitialize(); + lm_ssiinitialize(); } #endif @@ -96,8 +96,8 @@ void lm3s_boardinitialize(void) /* Configure serial transciever */ - lm3s_configgpio(XCVR_INV_GPIO); - lm3s_configgpio(XCVR_ENA_GPIO); - lm3s_configgpio(XCVR_ON_GPIO); - lm3s_configgpio(XCVR_OFF_GPIO); + lm_configgpio(XCVR_INV_GPIO); + lm_configgpio(XCVR_ENA_GPIO); + lm_configgpio(XCVR_ON_GPIO); + lm_configgpio(XCVR_OFF_GPIO); } diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c index 09d5040c4..434ffe2c5 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c @@ -63,17 +63,17 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) +#ifdef CONFIG_LM_BOARDMAC +void lm_ethernetmac(struct ether_addr *ethaddr) { uint32_t user0; uint32_t user1; diff --git a/nuttx/configs/lm3s6432-s2e/src/up_leds.c b/nuttx/configs/lm3s6432-s2e/src/up_leds.c index 81610db34..e0dd53f28 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_leds.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_leds.c @@ -72,7 +72,7 @@ /* Dump GPIO registers */ #ifdef LED_DEBUG -# define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m) +# define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m) #else # define led_dumpgpio(m) #endif @@ -102,10 +102,10 @@ void up_ledinit(void) /* Configure Port F, Bit 2 as an output, initial value=OFF */ - led_dumpgpio("up_ledinit before lm3s_configgpio()"); - lm3s_configgpio(LED0_GPIO); - lm3s_configgpio(LED1_GPIO); - led_dumpgpio("up_ledinit after lm3s_configgpio()"); + led_dumpgpio("up_ledinit before lm_configgpio()"); + lm_configgpio(LED0_GPIO); + lm_configgpio(LED1_GPIO); + led_dumpgpio("up_ledinit after lm_configgpio()"); g_nest = 0; } @@ -129,9 +129,9 @@ void up_ledon(int led) g_nest++; case LED_IRQSENABLED: case LED_STACKCREATED: - led_dumpgpio("up_ledon: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED1_GPIO, false); - led_dumpgpio("up_ledon: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledon: before lm_gpiowrite()"); + lm_gpiowrite(LED1_GPIO, false); + led_dumpgpio("up_ledon: after lm_gpiowrite()"); break; } } @@ -157,9 +157,9 @@ void up_ledoff(int led) case LED_PANIC: if (--g_nest <= 0) { - led_dumpgpio("up_ledoff: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED1_GPIO, true); - led_dumpgpio("up_ledoff: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledoff: before lm_gpiowrite()"); + lm_gpiowrite(LED1_GPIO, true); + led_dumpgpio("up_ledoff: after lm_gpiowrite()"); } break; } diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c index a7844a979..5468e2b4d 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_ssi.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_ssi.c @@ -79,7 +79,7 @@ /* Dump GPIO registers */ #ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +# define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m) #else # define ssi_dumpgpio(m) #endif @@ -93,30 +93,30 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the MDL-S2E. * ************************************************************************************/ -void weak_function lm3s_ssiinitialize(void) +void weak_function lm_ssiinitialize(void) { /* Configure the SPI CS GPIO */ - ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); - lm3s_configgpio(SSICS_GPIO); - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); + ssi_dumpgpio("lm_ssiinitialize() Entry)"); + lm_configgpio(SSICS_GPIO); + ssi_dumpgpio("lm_ssiinitialize() Exit"); } /**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * The external functions, lm_spiselect and lm_spistatus must be provided * by board-specific logic. The are implementations of the select and status * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All othermethods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 1. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. This function will perform chip selection and * status operations using GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization @@ -128,21 +128,21 @@ void weak_function lm3s_ssiinitialize(void) * ****************************************************************************/ -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); + ssi_dumpgpio("lm_spiselect() Entry"); if (devid == SPIDEV_MMCSD) { /* Assert the CS pin to the card */ - lm3s_gpiowrite(SDCCS_GPIO, !selected); + lm_gpiowrite(SDCCS_GPIO, !selected); } - ssi_dumpgpio("lm3s_spiselect() Exit"); + ssi_dumpgpio("lm_spiselect() Exit"); } -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { ssidbg("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index e0349f5de..813e11467 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -126,12 +126,12 @@ GNU Toolchain Options the CodeSourcery or devkitARM, you simply need to add one of the following configuration options to your .config (or defconfig) file: - CONFIG_LM3S_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_LM3S_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_LM3S_DEVKITARM=y : devkitARM under Windows - CONFIG_LM3S_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_LM_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LM_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_LM_DEVKITARM=y : devkitARM under Windows + CONFIG_LM_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify + If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. @@ -415,15 +415,15 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options Additional interrupt support can be disabled if desired to reduce memory footprint. - CONFIG_LM3S_DISABLE_GPIOA_IRQS=n - CONFIG_LM3S_DISABLE_GPIOB_IRQS=n - CONFIG_LM3S_DISABLE_GPIOC_IRQS=n - CONFIG_LM3S_DISABLE_GPIOD_IRQS=n - CONFIG_LM3S_DISABLE_GPIOE_IRQS=n - CONFIG_LM3S_DISABLE_GPIOF_IRQS=n - CONFIG_LM3S_DISABLE_GPIOG_IRQS=n - CONFIG_LM3S_DISABLE_GPIOH_IRQS=n - CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y + CONFIG_LM_DISABLE_GPIOA_IRQS=n + CONFIG_LM_DISABLE_GPIOB_IRQS=n + CONFIG_LM_DISABLE_GPIOC_IRQS=n + CONFIG_LM_DISABLE_GPIOD_IRQS=n + CONFIG_LM_DISABLE_GPIOE_IRQS=n + CONFIG_LM_DISABLE_GPIOF_IRQS=n + CONFIG_LM_DISABLE_GPIOG_IRQS=n + CONFIG_LM_DISABLE_GPIOH_IRQS=n + CONFIG_LM_DISABLE_GPIOJ_IRQS=y LM3S6818 specific device driver settings @@ -448,18 +448,18 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options value is large, then larger values of this setting may cause Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). - CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET) + CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) to build the LM3S Ethernet driver - CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. - CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide + CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. + CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. - CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation - CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation - CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding - CONFIG_LM3S_MULTICAST - Set to enable multicast frames - CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode - CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection. - CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console. + CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation + CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation + CONFIG_LM_ETHNOPAD - Set to suppress Tx padding + CONFIG_LM_MULTICAST - Set to enable multicast frames + CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode + CONFIG_LM_BADCRC - Set to enable bad CRC rejection. + CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console. Configurations ^^^^^^^^^^^^^^ diff --git a/nuttx/configs/lm3s6965-ek/include/board.h b/nuttx/configs/lm3s6965-ek/include/board.h index e8eaf9dd1..808d009cc 100644 --- a/nuttx/configs/lm3s6965-ek/include/board.h +++ b/nuttx/configs/lm3s6965-ek/include/board.h @@ -112,7 +112,7 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -121,21 +121,21 @@ * ************************************************************************************/ -extern void lm3s_boardinitialize(void); +extern void lm_boardinitialize(void); /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC +#ifdef CONFIG_LM_BOARDMAC struct ether_addr; -extern void lm3s_ethernetmac(struct ether_addr *ethaddr); +extern void lm_ethernetmac(struct ether_addr *ethaddr); #endif #endif /* __ASSEMBLY__ */ diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index c1827920b..99f2f50ab 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -100,44 +100,44 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARCH_CHIP_LM3S6432 is not set CONFIG_ARCH_CHIP_LM3S6965=y # CONFIG_ARCH_CHIP_LM3S8962 is not set -# CONFIG_LM3S_REVA2 is not set -CONFIG_LM3S_DFU=y +# CONFIG_LM_REVA2 is not set +CONFIG_LM_DFU=y # # Select LM3S Peripheral Support # -CONFIG_LM3S_UART0=y -# CONFIG_LM3S_UART1 is not set +CONFIG_LM_UART0=y +# CONFIG_LM_UART1 is not set # CONFIG_SSI0_DISABLE is not set CONFIG_SSI1_DISABLE=y -# CONFIG_LM3S_UART2 is not set -CONFIG_LM3S_ETHERNET=y +# CONFIG_LM_UART2 is not set +CONFIG_LM_ETHERNET=y # # Disable GPIO Interrupts # -# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +# CONFIG_LM_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM_DISABLE_GPIOG_IRQS is not set +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S Ethernet Configuration # -# CONFIG_LM3S_ETHLEDS is not set -# CONFIG_LM3S_BOARDMAC is not set -# CONFIG_LM3S_ETHHDUPLEX is not set -# CONFIG_LM3S_ETHNOAUTOCRC is not set -# CONFIG_LM3S_ETHNOPAD is not set -# CONFIG_LM3S_MULTICAST is not set -# CONFIG_LM3S_PROMISCUOUS is not set -# CONFIG_LM3S_TIMESTAMP is not set -# CONFIG_LM3S_BADCRC is not set +# CONFIG_LM_ETHLEDS is not set +# CONFIG_LM_BOARDMAC is not set +# CONFIG_LM_ETHHDUPLEX is not set +# CONFIG_LM_ETHNOAUTOCRC is not set +# CONFIG_LM_ETHNOPAD is not set +# CONFIG_LM_MULTICAST is not set +# CONFIG_LM_PROMISCUOUS is not set +# CONFIG_LM_TIMESTAMP is not set +# CONFIG_LM_BADCRC is not set # CONFIG_M3S_DUMPPACKET is not set # diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index e3cac8dd7..b86d06dc9 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -100,31 +100,31 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARCH_CHIP_LM3S6432 is not set CONFIG_ARCH_CHIP_LM3S6965=y # CONFIG_ARCH_CHIP_LM3S8962 is not set -# CONFIG_LM3S_REVA2 is not set -CONFIG_LM3S_DFU=y +# CONFIG_LM_REVA2 is not set +CONFIG_LM_DFU=y # # Select LM3S Peripheral Support # -CONFIG_LM3S_UART0=y -# CONFIG_LM3S_UART1 is not set +CONFIG_LM_UART0=y +# CONFIG_LM_UART1 is not set # CONFIG_SSI0_DISABLE is not set CONFIG_SSI1_DISABLE=y -# CONFIG_LM3S_UART2 is not set -# CONFIG_LM3S_ETHERNET is not set +# CONFIG_LM_UART2 is not set +# CONFIG_LM_ETHERNET is not set # # Disable GPIO Interrupts # -# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +# CONFIG_LM_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM_DISABLE_GPIOG_IRQS is not set +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S SSI Configuration diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index 81247c795..bc433e116 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -100,31 +100,31 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARCH_CHIP_LM3S6432 is not set CONFIG_ARCH_CHIP_LM3S6965=y # CONFIG_ARCH_CHIP_LM3S8962 is not set -# CONFIG_LM3S_REVA2 is not set -CONFIG_LM3S_DFU=y +# CONFIG_LM_REVA2 is not set +CONFIG_LM_DFU=y # # Select LM3S Peripheral Support # -CONFIG_LM3S_UART0=y -# CONFIG_LM3S_UART1 is not set +CONFIG_LM_UART0=y +# CONFIG_LM_UART1 is not set # CONFIG_SSI0_DISABLE is not set CONFIG_SSI1_DISABLE=y -# CONFIG_LM3S_UART2 is not set -# CONFIG_LM3S_ETHERNET is not set +# CONFIG_LM_UART2 is not set +# CONFIG_LM_ETHERNET is not set # # Disable GPIO Interrupts # -# CONFIG_LM3S_DISABLE_GPIOA_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOB_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOC_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOD_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOE_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOF_IRQS is not set -# CONFIG_LM3S_DISABLE_GPIOG_IRQS is not set -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +# CONFIG_LM_DISABLE_GPIOA_IRQS is not set +# CONFIG_LM_DISABLE_GPIOB_IRQS is not set +# CONFIG_LM_DISABLE_GPIOC_IRQS is not set +# CONFIG_LM_DISABLE_GPIOD_IRQS is not set +# CONFIG_LM_DISABLE_GPIOE_IRQS is not set +# CONFIG_LM_DISABLE_GPIOF_IRQS is not set +# CONFIG_LM_DISABLE_GPIOG_IRQS is not set +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S SSI Configuration diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h index 4cd2eddc7..c2fc50df1 100644 --- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h +++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h @@ -123,14 +123,14 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. * ************************************************************************************/ -extern void weak_function lm3s_ssiinitialize(void); +extern void weak_function lm_ssiinitialize(void); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H */ diff --git a/nuttx/configs/lm3s6965-ek/src/up_boot.c b/nuttx/configs/lm3s6965-ek/src/up_boot.c index 7f887be62..7ffd37f17 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_boot.c +++ b/nuttx/configs/lm3s6965-ek/src/up_boot.c @@ -61,7 +61,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -69,18 +69,18 @@ * and mapped but before any devices have been initialized. ************************************************************************************/ -void lm3s_boardinitialize(void) +void lm_boardinitialize(void) { /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. + * lm_ssiinitialize() has been brought into the link. */ /* The LM3S6965 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) + if (lm_ssiinitialize) { - lm3s_ssiinitialize(); + lm_ssiinitialize(); } #endif diff --git a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c index 4f402cae7..2d114baaa 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c +++ b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c @@ -63,17 +63,17 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) +#ifdef CONFIG_LM_BOARDMAC +void lm_ethernetmac(struct ether_addr *ethaddr) { uint32_t user0; uint32_t user1; diff --git a/nuttx/configs/lm3s6965-ek/src/up_leds.c b/nuttx/configs/lm3s6965-ek/src/up_leds.c index efa1eb738..0e6c5e50f 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_leds.c +++ b/nuttx/configs/lm3s6965-ek/src/up_leds.c @@ -72,7 +72,7 @@ /* Dump GPIO registers */ #ifdef LED_DEBUG -# define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m) +# define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m) #else # define led_dumpgpio(m) #endif @@ -102,9 +102,9 @@ void up_ledinit(void) /* Configure Port E, Bit 1 as an output, initial value=OFF */ - led_dumpgpio("up_ledinit before lm3s_configgpio()"); - lm3s_configgpio(LED_GPIO); - led_dumpgpio("up_ledinit after lm3s_configgpio()"); + led_dumpgpio("up_ledinit before lm_configgpio()"); + lm_configgpio(LED_GPIO); + led_dumpgpio("up_ledinit after lm_configgpio()"); g_nest = 0; } @@ -128,9 +128,9 @@ void up_ledon(int led) g_nest++; case LED_IRQSENABLED: case LED_STACKCREATED: - led_dumpgpio("up_ledon: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, false); - led_dumpgpio("up_ledon: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledon: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, false); + led_dumpgpio("up_ledon: after lm_gpiowrite()"); break; } } @@ -156,9 +156,9 @@ void up_ledoff(int led) case LED_PANIC: if (--g_nest <= 0) { - led_dumpgpio("up_ledoff: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, true); - led_dumpgpio("up_ledoff: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledoff: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, true); + led_dumpgpio("up_ledoff: after lm_gpiowrite()"); } break; } diff --git a/nuttx/configs/lm3s6965-ek/src/up_oled.c b/nuttx/configs/lm3s6965-ek/src/up_oled.c index 23ce7e036..07e7859b4 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_oled.c +++ b/nuttx/configs/lm3s6965-ek/src/up_oled.c @@ -72,8 +72,8 @@ #ifdef CONFIG_LCD_RITDEBUG # define ritdbg(format, arg...) vdbg(format, ##arg) -# define oleddc_dumpgpio(m) lm3s_dumpgpio(OLEDDC_GPIO, m) -# define oledcs_dumpgpio(m) lm3s_dumpgpio(OLEDCS_GPIO, m) +# define oleddc_dumpgpio(m) lm_dumpgpio(OLEDDC_GPIO, m) +# define oledcs_dumpgpio(m) lm_dumpgpio(OLEDCS_GPIO, m) #else # define ritdbg(x...) # define oleddc_dumpgpio(m) @@ -102,8 +102,8 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) oledcs_dumpgpio("up_nxdrvinit: After OLEDCS setup"); oleddc_dumpgpio("up_nxdrvinit: On entry"); - lm3s_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */ - lm3s_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */ + lm_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */ + lm_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */ oleddc_dumpgpio("up_nxdrvinit: After OLEDDC/EN setup"); @@ -137,7 +137,7 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) } /****************************************************************************** - * Name: lm3s_spicmddata + * Name: lm_spicmddata * * Description: * Set or clear the SD1329 D/Cn bit to select data (true) or command @@ -159,13 +159,13 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) * ******************************************************************************/ -int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) { if (devid == SPIDEV_DISPLAY) { /* Set GPIO to 1 for data, 0 for command */ - lm3s_gpiowrite(OLEDDC_GPIO, !cmd); + lm_gpiowrite(OLEDDC_GPIO, !cmd); return OK; } return -ENODEV; diff --git a/nuttx/configs/lm3s6965-ek/src/up_ssi.c b/nuttx/configs/lm3s6965-ek/src/up_ssi.c index b52116f14..92138f3a6 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_ssi.c +++ b/nuttx/configs/lm3s6965-ek/src/up_ssi.c @@ -81,7 +81,7 @@ /* Dump GPIO registers */ #ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +# define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m) #else # define ssi_dumpgpio(m) #endif @@ -95,33 +95,33 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. * ************************************************************************************/ -void weak_function lm3s_ssiinitialize(void) +void weak_function lm_ssiinitialize(void) { /* Configure the SPI-based microSD CS GPIO */ - ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); - lm3s_configgpio(SDCCS_GPIO); + ssi_dumpgpio("lm_ssiinitialize() Entry)"); + lm_configgpio(SDCCS_GPIO); #ifdef CONFIG_NX_LCDDRIVER - lm3s_configgpio(OLEDCS_GPIO); + lm_configgpio(OLEDCS_GPIO); #endif - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); + ssi_dumpgpio("lm_ssiinitialize() Exit"); } /**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * The external functions, lm_spiselect and lm_spistatus must be provided * by board-specific logic. The are implementations of the select and status * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All othermethods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 1. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. This function will perform chip selection and * status operations using GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization @@ -133,29 +133,29 @@ void weak_function lm3s_ssiinitialize(void) * ****************************************************************************/ -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); + ssi_dumpgpio("lm_spiselect() Entry"); if (devid == SPIDEV_MMCSD) { /* Assert the CS pin to the card */ - lm3s_gpiowrite(SDCCS_GPIO, !selected); + lm_gpiowrite(SDCCS_GPIO, !selected); } #ifdef CONFIG_NX_LCDDRIVER else if (devid == SPIDEV_DISPLAY) { /* Assert the CS pin to the display */ - lm3s_gpiowrite(OLEDCS_GPIO, !selected); + lm_gpiowrite(OLEDCS_GPIO, !selected); } #endif - ssi_dumpgpio("lm3s_spiselect() Exit"); + ssi_dumpgpio("lm_spiselect() Exit"); } -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { ssidbg("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt index 0f796e38d..38ed76aea 100644 --- a/nuttx/configs/lm3s8962-ek/README.txt +++ b/nuttx/configs/lm3s8962-ek/README.txt @@ -126,12 +126,12 @@ GNU Toolchain Options the CodeSourcery or devkitARM, you simply need to add one of the following configuration options to your .config (or defconfig) file: - CONFIG_LM3S_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_LM3S_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_LM3S_DEVKITARM=y : devkitARM under Windows - CONFIG_LM3S_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_LM_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LM_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_LM_DEVKITARM=y : devkitARM under Windows + CONFIG_LM_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - If you are not using CONFIG_LM3S_BUILDROOT, then you may also have to modify + If you are not using CONFIG_LM_BUILDROOT, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. @@ -399,15 +399,15 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options Additional interrupt support can be disabled if desired to reduce memory footprint. - CONFIG_LM3S_DISABLE_GPIOA_IRQS=n - CONFIG_LM3S_DISABLE_GPIOB_IRQS=n - CONFIG_LM3S_DISABLE_GPIOC_IRQS=n - CONFIG_LM3S_DISABLE_GPIOD_IRQS=n - CONFIG_LM3S_DISABLE_GPIOE_IRQS=n - CONFIG_LM3S_DISABLE_GPIOF_IRQS=n - CONFIG_LM3S_DISABLE_GPIOG_IRQS=n - CONFIG_LM3S_DISABLE_GPIOH_IRQS=n - CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y + CONFIG_LM_DISABLE_GPIOA_IRQS=n + CONFIG_LM_DISABLE_GPIOB_IRQS=n + CONFIG_LM_DISABLE_GPIOC_IRQS=n + CONFIG_LM_DISABLE_GPIOD_IRQS=n + CONFIG_LM_DISABLE_GPIOE_IRQS=n + CONFIG_LM_DISABLE_GPIOF_IRQS=n + CONFIG_LM_DISABLE_GPIOG_IRQS=n + CONFIG_LM_DISABLE_GPIOH_IRQS=n + CONFIG_LM_DISABLE_GPIOJ_IRQS=y LM3S6818 specific device driver settings @@ -432,18 +432,18 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options value is large, then larger values of this setting may cause Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). - CONFIG_LM3S_ETHERNET - This must be set (along with CONFIG_NET) + CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) to build the LM3S Ethernet driver - CONFIG_LM3S_ETHLEDS - Enable to use Ethernet LEDs on the board. - CONFIG_LM3S_BOARDMAC - If the board-specific logic can provide + CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. + CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. - CONFIG_LM3S_ETHHDUPLEX - Set to force half duplex operation - CONFIG_LM3S_ETHNOAUTOCRC - Set to suppress auto-CRC generation - CONFIG_LM3S_ETHNOPAD - Set to suppress Tx padding - CONFIG_LM3S_MULTICAST - Set to enable multicast frames - CONFIG_LM3S_PROMISCUOUS - Set to enable promiscuous mode - CONFIG_LM3S_BADCRC - Set to enable bad CRC rejection. - CONFIG_LM3S_DUMPPACKET - Dump each packet received/sent to the console. + CONFIG_LM_ETHHDUPLEX - Set to force half duplex operation + CONFIG_LM_ETHNOAUTOCRC - Set to suppress auto-CRC generation + CONFIG_LM_ETHNOPAD - Set to suppress Tx padding + CONFIG_LM_MULTICAST - Set to enable multicast frames + CONFIG_LM_PROMISCUOUS - Set to enable promiscuous mode + CONFIG_LM_BADCRC - Set to enable bad CRC rejection. + CONFIG_LM_DUMPPACKET - Dump each packet received/sent to the console. Configurations ^^^^^^^^^^^^^^ diff --git a/nuttx/configs/lm3s8962-ek/include/board.h b/nuttx/configs/lm3s8962-ek/include/board.h index 0b03f96f0..4d6a0c302 100644 --- a/nuttx/configs/lm3s8962-ek/include/board.h +++ b/nuttx/configs/lm3s8962-ek/include/board.h @@ -112,7 +112,7 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -121,21 +121,21 @@ * ************************************************************************************/ -extern void lm3s_boardinitialize(void); +extern void lm_boardinitialize(void); /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC +#ifdef CONFIG_LM_BOARDMAC struct ether_addr; -extern void lm3s_ethernetmac(struct ether_addr *ethaddr); +extern void lm_ethernetmac(struct ether_addr *ethaddr); #endif #endif /* __ASSEMBLY__ */ diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig index 1d3df2fa7..4a35f8d4a 100755 --- a/nuttx/configs/lm3s8962-ek/nsh/defconfig +++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig @@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=n +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=y +CONFIG_LM_DFU=y # # Disable support for interrupts on GPIOH and GPIOJ which do not # exist on the LM3S6B96. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n @@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=y -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=n -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=y +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=n +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig index 37fc8903d..3ca6ade21 100755 --- a/nuttx/configs/lm3s8962-ek/nx/defconfig +++ b/nuttx/configs/lm3s8962-ek/nx/defconfig @@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=n +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=y +CONFIG_LM_DFU=y # # Disable support for interrupts on GPIOH and GPIOJ which do not # exist on the LM3S6B96. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n @@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig index 731003fd0..169ac9c8f 100755 --- a/nuttx/configs/lm3s8962-ek/ostest/defconfig +++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig @@ -56,32 +56,32 @@ CONFIG_ARCH_CALIBRATION=n # # Identify toolchain and linker options # -CONFIG_LM3S_CODESOURCERYW=n -CONFIG_LM3S_CODESOURCERYL=n -CONFIG_LM3S_DEVKITARM=n -CONFIG_LM3S_BUILDROOT=y -CONFIG_LM3S_DFU=y +CONFIG_LM_CODESOURCERYW=n +CONFIG_LM_CODESOURCERYL=n +CONFIG_LM_DEVKITARM=n +CONFIG_LM_BUILDROOT=y +CONFIG_LM_DFU=y # # Disable support for interrupts on GPIOH and GPIOJ which do not # exist on the LM3S6B96. Additional interrupt support can be # disabled if desired to reduce memory footprint. -CONFIG_LM3S_DISABLE_GPIOA_IRQS=n -CONFIG_LM3S_DISABLE_GPIOB_IRQS=n -CONFIG_LM3S_DISABLE_GPIOC_IRQS=n -CONFIG_LM3S_DISABLE_GPIOD_IRQS=n -CONFIG_LM3S_DISABLE_GPIOE_IRQS=n -CONFIG_LM3S_DISABLE_GPIOF_IRQS=n -CONFIG_LM3S_DISABLE_GPIOG_IRQS=n -CONFIG_LM3S_DISABLE_GPIOH_IRQS=y -CONFIG_LM3S_DISABLE_GPIOJ_IRQS=y +CONFIG_LM_DISABLE_GPIOA_IRQS=n +CONFIG_LM_DISABLE_GPIOB_IRQS=n +CONFIG_LM_DISABLE_GPIOC_IRQS=n +CONFIG_LM_DISABLE_GPIOD_IRQS=n +CONFIG_LM_DISABLE_GPIOE_IRQS=n +CONFIG_LM_DISABLE_GPIOF_IRQS=n +CONFIG_LM_DISABLE_GPIOG_IRQS=n +CONFIG_LM_DISABLE_GPIOH_IRQS=y +CONFIG_LM_DISABLE_GPIOJ_IRQS=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_UART0=y -CONFIG_LM3S_UART1=n -CONFIG_LM3S_UART2=n +CONFIG_LM_UART0=y +CONFIG_LM_UART1=n +CONFIG_LM_UART2=n CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n CONFIG_UART2_SERIAL_CONSOLE=n @@ -115,16 +115,16 @@ CONFIG_SSI_POLLWAIT=y # # LM3S8962 specific serial device driver settings # -CONFIG_LM3S_ETHERNET=n -CONFIG_LM3S_ETHLEDS=n -CONFIG_LM3S_BOARDMAC=y -CONFIG_LM3S_ETHHDUPLEX=n -CONFIG_LM3S_ETHNOAUTOCRC=n -CONFIG_LM3S_ETHNOPAD=n -CONFIG_LM3S_MULTICAST=n -CONFIG_LM3S_PROMISCUOUS=n -CONFIG_LM3S_BADCRC=n -CONFIG_LM3S_DUMPPACKET=n +CONFIG_LM_ETHERNET=n +CONFIG_LM_ETHLEDS=n +CONFIG_LM_BOARDMAC=y +CONFIG_LM_ETHHDUPLEX=n +CONFIG_LM_ETHNOAUTOCRC=n +CONFIG_LM_ETHNOPAD=n +CONFIG_LM_MULTICAST=n +CONFIG_LM_PROMISCUOUS=n +CONFIG_LM_BADCRC=n +CONFIG_LM_DUMPPACKET=n # # General build options diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h index 689472f15..7fc8fa331 100644 --- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h +++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h @@ -123,14 +123,14 @@ #ifndef __ASSEMBLY__ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. * ************************************************************************************/ -extern void weak_function lm3s_ssiinitialize(void); +extern void weak_function lm_ssiinitialize(void); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H */ diff --git a/nuttx/configs/lm3s8962-ek/src/up_boot.c b/nuttx/configs/lm3s8962-ek/src/up_boot.c index 0a976e857..8dc5b81cc 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_boot.c +++ b/nuttx/configs/lm3s8962-ek/src/up_boot.c @@ -61,7 +61,7 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_boardinitialize + * Name: lm_boardinitialize * * Description: * All LM3S architectures must provide the following entry point. This entry point @@ -69,18 +69,18 @@ * and mapped but before any devices have been initialized. ************************************************************************************/ -void lm3s_boardinitialize(void) +void lm_boardinitialize(void) { /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. + * lm_ssiinitialize() has been brought into the link. */ /* The LM3S8962 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ #if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) + if (lm_ssiinitialize) { - lm3s_ssiinitialize(); + lm_ssiinitialize(); } #endif diff --git a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c index 2cad50bef..0d73233a4 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c +++ b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c @@ -63,17 +63,17 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ethernetmac + * Name: lm_ethernetmac * * Description: * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * USER0 and USER1 registers. If CONFIG_LM_BOARDMAC is defined, this function * will obtain the MAC address from these registers. * ************************************************************************************/ -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) +#ifdef CONFIG_LM_BOARDMAC +void lm_ethernetmac(struct ether_addr *ethaddr) { uint32_t user0; uint32_t user1; diff --git a/nuttx/configs/lm3s8962-ek/src/up_leds.c b/nuttx/configs/lm3s8962-ek/src/up_leds.c index d5000d037..a20617f1e 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_leds.c +++ b/nuttx/configs/lm3s8962-ek/src/up_leds.c @@ -72,7 +72,7 @@ /* Dump GPIO registers */ #ifdef LED_DEBUG -# define led_dumpgpio(m) lm3s_dumpgpio(LED_GPIO, m) +# define led_dumpgpio(m) lm_dumpgpio(LED_GPIO, m) #else # define led_dumpgpio(m) #endif @@ -102,9 +102,9 @@ void up_ledinit(void) /* Configure Port E, Bit 1 as an output, initial value=OFF */ - led_dumpgpio("up_ledinit before lm3s_configgpio()"); - lm3s_configgpio(LED_GPIO); - led_dumpgpio("up_ledinit after lm3s_configgpio()"); + led_dumpgpio("up_ledinit before lm_configgpio()"); + lm_configgpio(LED_GPIO); + led_dumpgpio("up_ledinit after lm_configgpio()"); g_nest = 0; } @@ -128,9 +128,9 @@ void up_ledon(int led) g_nest++; case LED_IRQSENABLED: case LED_STACKCREATED: - led_dumpgpio("up_ledon: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, false); - led_dumpgpio("up_ledon: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledon: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, false); + led_dumpgpio("up_ledon: after lm_gpiowrite()"); break; } } @@ -156,9 +156,9 @@ void up_ledoff(int led) case LED_PANIC: if (--g_nest <= 0) { - led_dumpgpio("up_ledoff: before lm3s_gpiowrite()"); - lm3s_gpiowrite(LED_GPIO, true); - led_dumpgpio("up_ledoff: after lm3s_gpiowrite()"); + led_dumpgpio("up_ledoff: before lm_gpiowrite()"); + lm_gpiowrite(LED_GPIO, true); + led_dumpgpio("up_ledoff: after lm_gpiowrite()"); } break; } diff --git a/nuttx/configs/lm3s8962-ek/src/up_oled.c b/nuttx/configs/lm3s8962-ek/src/up_oled.c index 3324b3897..05934e8bd 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_oled.c +++ b/nuttx/configs/lm3s8962-ek/src/up_oled.c @@ -72,8 +72,8 @@ #ifdef CONFIG_LCD_RITDEBUG # define ritdbg(format, arg...) vdbg(format, ##arg) -# define oleddc_dumpgpio(m) lm3s_dumpgpio(OLEDDC_GPIO, m) -# define oledcs_dumpgpio(m) lm3s_dumpgpio(OLEDCS_GPIO, m) +# define oleddc_dumpgpio(m) lm_dumpgpio(OLEDDC_GPIO, m) +# define oledcs_dumpgpio(m) lm_dumpgpio(OLEDCS_GPIO, m) #else # define ritdbg(x...) # define oleddc_dumpgpio(m) @@ -102,8 +102,8 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) oledcs_dumpgpio("up_nxdrvinit: After OLEDCS setup"); oleddc_dumpgpio("up_nxdrvinit: On entry"); - lm3s_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */ - lm3s_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */ + lm_configgpio(OLEDDC_GPIO); /* PC7: OLED display data/control select (D/Cn) */ + lm_configgpio(OLEDEN_GPIO); /* PC6: Enable +15V needed by OLED (EN+15V) */ oleddc_dumpgpio("up_nxdrvinit: After OLEDDC/EN setup"); @@ -137,7 +137,7 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) } /****************************************************************************** - * Name: lm3s_spicmddata + * Name: lm_spicmddata * * Description: * Set or clear the SD1329 D/Cn bit to select data (true) or command @@ -159,13 +159,13 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno) * ******************************************************************************/ -int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +int lm_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) { if (devid == SPIDEV_DISPLAY) { /* Set GPIO to 1 for data, 0 for command */ - lm3s_gpiowrite(OLEDDC_GPIO, !cmd); + lm_gpiowrite(OLEDDC_GPIO, !cmd); return OK; } return -ENODEV; diff --git a/nuttx/configs/lm3s8962-ek/src/up_ssi.c b/nuttx/configs/lm3s8962-ek/src/up_ssi.c index 7f78b3477..50344857a 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_ssi.c +++ b/nuttx/configs/lm3s8962-ek/src/up_ssi.c @@ -81,7 +81,7 @@ /* Dump GPIO registers */ #ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +# define ssi_dumpgpio(m) lm_dumpgpio(SDCCS_GPIO, m) #else # define ssi_dumpgpio(m) #endif @@ -95,33 +95,33 @@ ************************************************************************************/ /************************************************************************************ - * Name: lm3s_ssiinitialize + * Name: lm_ssiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. * ************************************************************************************/ -void weak_function lm3s_ssiinitialize(void) +void weak_function lm_ssiinitialize(void) { /* Configure the SPI-based microSD CS GPIO */ - ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); - lm3s_configgpio(SDCCS_GPIO); + ssi_dumpgpio("lm_ssiinitialize() Entry)"); + lm_configgpio(SDCCS_GPIO); #ifdef CONFIG_NX_LCDDRIVER - lm3s_configgpio(OLEDCS_GPIO); + lm_configgpio(OLEDCS_GPIO); #endif - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); + ssi_dumpgpio("lm_ssiinitialize() Exit"); } /**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * The external functions, lm_spiselect and lm_spistatus must be provided * by board-specific logic. The are implementations of the select and status * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). * All othermethods (including up_spiinitialize()) are provided by common * logic. To use this common SPI logic on your board: * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * 1. Provide lm_spiselect() and lm_spistatus() functions in your * board-specific logic. This function will perform chip selection and * status operations using GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization @@ -133,29 +133,29 @@ void weak_function lm3s_ssiinitialize(void) * ****************************************************************************/ -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +void lm_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); + ssi_dumpgpio("lm_spiselect() Entry"); if (devid == SPIDEV_MMCSD) { /* Assert the CS pin to the card */ - lm3s_gpiowrite(SDCCS_GPIO, !selected); + lm_gpiowrite(SDCCS_GPIO, !selected); } #ifdef CONFIG_NX_LCDDRIVER else if (devid == SPIDEV_DISPLAY) { /* Assert the CS pin to the display */ - lm3s_gpiowrite(OLEDCS_GPIO, !selected); + lm_gpiowrite(OLEDCS_GPIO, !selected); } #endif - ssi_dumpgpio("lm3s_spiselect() Exit"); + ssi_dumpgpio("lm_spiselect() Exit"); } -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +uint8_t lm_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { ssidbg("Returning SPI_STATUS_PRESENT\n"); return SPI_STATUS_PRESENT; -- cgit v1.2.3 From 35cc14be43ed9ed33da6eb63d66627765cf9f157 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 9 Jan 2013 18:15:02 +0000 Subject: Change naming of all Stellaris pre-processor symbols from LM3S_ to LM_ to make room in the namespace for LM4F git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5498 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lm/chip.h | 104 ++-- nuttx/arch/arm/include/lm/irq.h | 650 ++++++++++----------- nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h | 506 ++++++++-------- nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h | 2 +- nuttx/arch/arm/src/lm/chip/lm_epi.h | 26 +- nuttx/arch/arm/src/lm/chip/lm_ethernet.h | 100 ++-- nuttx/arch/arm/src/lm/chip/lm_flash.h | 94 +-- nuttx/arch/arm/src/lm/chip/lm_gpio.h | 646 ++++++++++---------- nuttx/arch/arm/src/lm/chip/lm_i2c.h | 142 ++--- nuttx/arch/arm/src/lm/chip/lm_pinmap.h | 2 +- nuttx/arch/arm/src/lm/chip/lm_ssi.h | 268 ++++----- nuttx/arch/arm/src/lm/chip/lm_syscontrol.h | 122 ++-- nuttx/arch/arm/src/lm/chip/lm_timer.h | 40 +- nuttx/arch/arm/src/lm/chip/lm_uart.h | 260 ++++----- nuttx/arch/arm/src/lm/lm_dumpgpio.c | 28 +- nuttx/arch/arm/src/lm/lm_ethernet.c | 252 ++++---- nuttx/arch/arm/src/lm/lm_ethernet.h | 6 +- nuttx/arch/arm/src/lm/lm_gpio.c | 96 +-- nuttx/arch/arm/src/lm/lm_gpioirq.c | 91 ++- nuttx/arch/arm/src/lm/lm_irq.c | 52 +- nuttx/arch/arm/src/lm/lm_lowputc.c | 92 +-- nuttx/arch/arm/src/lm/lm_serial.c | 78 +-- nuttx/arch/arm/src/lm/lm_ssi.c | 112 ++-- nuttx/arch/arm/src/lm/lm_syscontrol.c | 30 +- nuttx/arch/arm/src/lm/lm_timerisr.c | 4 +- nuttx/arch/arm/src/lm/lm_vectors.S | 402 ++++++------- nuttx/configs/avr32dev1/README.txt | 6 +- nuttx/configs/eagle100/README.txt | 4 +- nuttx/configs/eagle100/include/board.h | 12 +- nuttx/configs/eagle100/src/eagle100_internal.h | 4 +- nuttx/configs/eagle100/src/up_boot.c | 7 +- nuttx/configs/eagle100/src/up_ethernet.c | 4 +- nuttx/configs/ekk-lm3s9b96/README.txt | 8 +- nuttx/configs/ekk-lm3s9b96/include/board.h | 12 +- .../ekk-lm3s9b96/src/ekklm3s9b96_internal.h | 4 +- nuttx/configs/ekk-lm3s9b96/src/up_boot.c | 7 +- nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c | 4 +- nuttx/configs/lm3s6432-s2e/README.txt | 4 +- nuttx/configs/lm3s6432-s2e/include/board.h | 12 +- .../lm3s6432-s2e/src/lm3s6432s2e_internal.h | 2 +- nuttx/configs/lm3s6432-s2e/src/up_boot.c | 7 +- nuttx/configs/lm3s6432-s2e/src/up_ethernet.c | 4 +- nuttx/configs/lm3s6965-ek/README.txt | 8 +- nuttx/configs/lm3s6965-ek/include/board.h | 12 +- nuttx/configs/lm3s6965-ek/nsh/defconfig | 8 +- nuttx/configs/lm3s6965-ek/nx/defconfig | 6 +- nuttx/configs/lm3s6965-ek/ostest/defconfig | 6 +- .../configs/lm3s6965-ek/src/lm3s6965ek_internal.h | 4 +- nuttx/configs/lm3s6965-ek/src/up_boot.c | 7 +- nuttx/configs/lm3s6965-ek/src/up_ethernet.c | 4 +- nuttx/configs/lm3s8962-ek/README.txt | 8 +- nuttx/configs/lm3s8962-ek/include/board.h | 12 +- .../configs/lm3s8962-ek/src/lm3s8962ek_internal.h | 4 +- nuttx/configs/lm3s8962-ek/src/up_boot.c | 7 +- nuttx/configs/lm3s8962-ek/src/up_ethernet.c | 4 +- nuttx/configs/lpcxpresso-lpc1768/README.txt | 2 +- nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c | 4 +- nuttx/configs/nucleus2g/src/up_ssp.c | 4 +- nuttx/include/nuttx/net/mii.h | 168 +++--- 59 files changed, 2288 insertions(+), 2286 deletions(-) diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h index 9eee51922..8293c7938 100644 --- a/nuttx/arch/arm/include/lm/chip.h +++ b/nuttx/arch/arm/include/lm/chip.h @@ -49,63 +49,63 @@ /* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */ #if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 0 /* No PWM generator modules */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ +# define LM_NTIMERS 4 /* Four general purpose timers */ +# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM_ETHTS /* No timestamp register */ +# define LM_NSSI 2 /* Two SSI modules */ +# define LM_NUARTS 2 /* Two UART modules */ +# define LM_NI2C 2 /* Two I2C modules */ +# define LM_NADC 1 /* One ADC module */ +# define LM_NPWM 0 /* No PWM generator modules */ +# define LM_NQEI 0 /* No quadrature encoders */ +# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */ #elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM3S_NTIMERS 3 /* Three general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 2 /* Two UART modules */ -# define LM3S_NI2C 1 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 1 /* One PWM generator module */ -# define LM3S_NQEI 0 /* No quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +# define LM_NTIMERS 3 /* Three general purpose timers */ +# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM_ETHTS /* No timestamp register */ +# define LM_NSSI 1 /* One SSI module */ +# define LM_NUARTS 2 /* Two UART modules */ +# define LM_NI2C 1 /* Two I2C modules */ +# define LM_NADC 1 /* One ADC module */ +# define LM_NPWM 1 /* One PWM generator module */ +# define LM_NQEI 0 /* No quadrature encoders */ +# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ #elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ +# define LM_NTIMERS 4 /* Four general purpose timers */ +# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM_ETHTS /* No timestamp register */ +# define LM_NSSI 1 /* One SSI module */ +# define LM_NUARTS 3 /* Three UART modules */ +# define LM_NI2C 2 /* Two I2C modules */ +# define LM_NADC 1 /* One ADC module */ +# define LM_NPWM 3 /* Three PWM generator modules */ +# define LM_NQEI 2 /* Two quadrature encoders */ +# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# undef LM3S_ETHTS /* No timestamp register */ -# define LM3S_NSSI 2 /* Two SSI modules */ -# define LM3S_NUARTS 3 /* Three UART modules */ -# define LM3S_NI2C 2 /* Two I2C modules */ -# define LM3S_NADC 2 /* Two ADC module */ -# define LM3S_CAN 2 /* Two CAN module */ -# define LM3S_NPWM 4 /* Four PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ +# define LM_NTIMERS 4 /* Four general purpose timers */ +# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM_ETHTS /* No timestamp register */ +# define LM_NSSI 2 /* Two SSI modules */ +# define LM_NUARTS 3 /* Three UART modules */ +# define LM_NI2C 2 /* Two I2C modules */ +# define LM_NADC 2 /* Two ADC module */ +# define LM_CAN 2 /* Two CAN module */ +# define LM_NPWM 4 /* Four PWM generator modules */ +# define LM_NQEI 2 /* Two quadrature encoders */ +# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */ #elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_NTIMERS 4 /* Four general purpose timers */ -# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LM3S_NSSI 1 /* One SSI module */ -# define LM3S_NUARTS 3 /* Two UART modules */ -# define LM3S_NI2C 2 /* One I2C module */ -# define LM3S_NADC 1 /* One ADC module */ -# define LM2S_NPWM 3 /* Three PWM generator modules */ -# define LM3S_NQEI 2 /* Two quadrature encoders */ -# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ -# define LC3S_CANCONTROLLER 1 /* One CAN controller */ +# define LM_NTIMERS 4 /* Four general purpose timers */ +# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LM_NSSI 1 /* One SSI module */ +# define LM_NUARTS 3 /* Two UART modules */ +# define LM_NI2C 2 /* One I2C module */ +# define LM_NADC 1 /* One ADC module */ +# define LM_NPWM 3 /* Three PWM generator modules */ +# define LM_NQEI 2 /* Two quadrature encoders */ +# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */ +# define LM_CANCONTROLLER 1 /* One CAN controller */ #else -# error "Capabilities not specified for this LM3S chip" +# error "Capabilities not specified for this Stellaris chip" #endif /************************************************************************************ diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h index 136496fef..9a5a3d153 100644 --- a/nuttx/arch/arm/include/lm/irq.h +++ b/nuttx/arch/arm/include/lm/irq.h @@ -58,250 +58,250 @@ /* Processor Exceptions (vectors 0-15) */ -#define LM3S_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LM3S_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LM3S_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LM3S_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16) */ -#define LM3S_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ +#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ #if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25-29: Reserved */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ - /* Vector 49: Reserved */ -# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ - /* Vectors 54-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ + /* Vector 25-29: Reserved */ +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ + /* Vector 49: Reserved */ +# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ + /* Vectors 54-57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ #elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25: Reserved */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ - /* Vectors 27-29: Reserved */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vectors 48-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vectors 59-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ + /* Vector 25: Reserved */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ + /* Vectors 27-29: Reserved */ +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vectors 48-57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ + /* Vectors 59-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ #elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ -# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ - /* Vector 50: Reserved */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ - /* Vectors 55-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ + /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vector 48: Reserved */ +# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ + /* Vector 50: Reserved */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ + /* Vectors 55-57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ -# define LM3S_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ -# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */ -# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM3S_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ -# define LM3S_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ - /* Vector 57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vector 59: Reserved */ -# define LM3S_IRQ_USB (60) /* Vector 60: USB */ -# define LM3S_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ -# define LM3S_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ -# define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ -# define LM3S_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ -# define LM3S_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ -# define LM3S_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ -# define LM3S_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ -# define LM3S_IRQ_I2S0 (68) /* Vector 68: I2S0 */ -# define LM3S_IRQ_EPI (69) /* Vector 69: EPI */ -# define LM3S_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ - /* Vector 71: Reserved */ -# define NR_IRQS (71) /* (Really less because of reserved vectors) */ +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ +# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ +# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ +# define LM_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ + /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ + /* Vector 59: Reserved */ +# define LM_IRQ_USB (60) /* Vector 60: USB */ +# define LM_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ +# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ +# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ +# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ +# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ +# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ +# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ +# define LM_IRQ_I2S0 (68) /* Vector 68: I2S0 */ +# define LM_IRQ_EPI (69) /* Vector 69: EPI */ +# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ + /* Vector 71: Reserved */ +# define NR_IRQS (71) /* (Really less because of reserved vectors) */ #elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ - /* Vector 42: Reserved */ - /* Vector 43: Reserved */ -# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ - /* Vector 49: Reserved */ - /* Vector 50: Reserved */ -# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM3S_IRQ_CAN0 (54) /* Vector 55: CAN0 */ - /* Vectors 56-57: Reserved */ -# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ + /* Vector 42: Reserved */ + /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ + /* Vector 48: Reserved */ + /* Vector 49: Reserved */ + /* Vector 50: Reserved */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM_IRQ_CAN0 (54) /* Vector 55: CAN0 */ + /* Vectors 56-57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + /* Vectors 60-70: Reserved */ +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ #else -# error "IRQ Numbers not specified for this LM3S chip" +# error "IRQ Numbers not specified for this Stellaris chip" #endif /* GPIO IRQs -- Note that support for individual GPIO ports can @@ -309,132 +309,132 @@ */ #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS -# define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0) -# define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1) -# define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2) -# define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3) -# define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4) -# define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5) -# define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6) -# define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7) -# define _NGPIOAIRQS (NR_IRQS + 8) +# define LM_IRQ_GPIOA_0 (NR_IRQS + 0) +# define LM_IRQ_GPIOA_1 (NR_IRQS + 1) +# define LM_IRQ_GPIOA_2 (NR_IRQS + 2) +# define LM_IRQ_GPIOA_3 (NR_IRQS + 3) +# define LM_IRQ_GPIOA_4 (NR_IRQS + 4) +# define LM_IRQ_GPIOA_5 (NR_IRQS + 5) +# define LM_IRQ_GPIOA_6 (NR_IRQS + 6) +# define LM_IRQ_GPIOA_7 (NR_IRQS + 7) +# define _NGPIOAIRQS (NR_IRQS + 8) #else -# define _NGPIOAIRQS NR_IRQS +# define _NGPIOAIRQS NR_IRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS -# define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0) -# define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1) -# define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2) -# define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3) -# define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4) -# define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5) -# define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6) -# define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7) -# define _NGPIOBIRQS (_NGPIOAIRQS + 8) +# define LM_IRQ_GPIOB_0 (_NGPIOAIRQS + 0) +# define LM_IRQ_GPIOB_1 (_NGPIOAIRQS + 1) +# define LM_IRQ_GPIOB_2 (_NGPIOAIRQS + 2) +# define LM_IRQ_GPIOB_3 (_NGPIOAIRQS + 3) +# define LM_IRQ_GPIOB_4 (_NGPIOAIRQS + 4) +# define LM_IRQ_GPIOB_5 (_NGPIOAIRQS + 5) +# define LM_IRQ_GPIOB_6 (_NGPIOAIRQS + 6) +# define LM_IRQ_GPIOB_7 (_NGPIOAIRQS + 7) +# define _NGPIOBIRQS (_NGPIOAIRQS + 8) #else -# define _NGPIOBIRQS _NGPIOAIRQS +# define _NGPIOBIRQS _NGPIOAIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS -# define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0) -# define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1) -# define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2) -# define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3) -# define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4) -# define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5) -# define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6) -# define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7) -# define _NGPIOCIRQS (_NGPIOBIRQS + 8) +# define LM_IRQ_GPIOC_0 (_NGPIOBIRQS + 0) +# define LM_IRQ_GPIOC_1 (_NGPIOBIRQS + 1) +# define LM_IRQ_GPIOC_2 (_NGPIOBIRQS + 2) +# define LM_IRQ_GPIOC_3 (_NGPIOBIRQS + 3) +# define LM_IRQ_GPIOC_4 (_NGPIOBIRQS + 4) +# define LM_IRQ_GPIOC_5 (_NGPIOBIRQS + 5) +# define LM_IRQ_GPIOC_6 (_NGPIOBIRQS + 6) +# define LM_IRQ_GPIOC_7 (_NGPIOBIRQS + 7) +# define _NGPIOCIRQS (_NGPIOBIRQS + 8) #else -# define _NGPIOCIRQS _NGPIOBIRQS +# define _NGPIOCIRQS _NGPIOBIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS -# define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0) -# define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1) -# define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2) -# define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3) -# define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4) -# define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5) -# define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6) -# define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7) -# define _NGPIODIRQS (_NGPIOCIRQS + 8) +# define LM_IRQ_GPIOD_0 (_NGPIOCIRQS + 0) +# define LM_IRQ_GPIOD_1 (_NGPIOCIRQS + 1) +# define LM_IRQ_GPIOD_2 (_NGPIOCIRQS + 2) +# define LM_IRQ_GPIOD_3 (_NGPIOCIRQS + 3) +# define LM_IRQ_GPIOD_4 (_NGPIOCIRQS + 4) +# define LM_IRQ_GPIOD_5 (_NGPIOCIRQS + 5) +# define LM_IRQ_GPIOD_6 (_NGPIOCIRQS + 6) +# define LM_IRQ_GPIOD_7 (_NGPIOCIRQS + 7) +# define _NGPIODIRQS (_NGPIOCIRQS + 8) #else -# define _NGPIODIRQS _NGPIOCIRQS +# define _NGPIODIRQS _NGPIOCIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS -# define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0) -# define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1) -# define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2) -# define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3) -# define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4) -# define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5) -# define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6) -# define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7) -# define _NGPIOEIRQS (_NGPIODIRQS + 8) +# define LM_IRQ_GPIOE_0 (_NGPIODIRQS + 0) +# define LM_IRQ_GPIOE_1 (_NGPIODIRQS + 1) +# define LM_IRQ_GPIOE_2 (_NGPIODIRQS + 2) +# define LM_IRQ_GPIOE_3 (_NGPIODIRQS + 3) +# define LM_IRQ_GPIOE_4 (_NGPIODIRQS + 4) +# define LM_IRQ_GPIOE_5 (_NGPIODIRQS + 5) +# define LM_IRQ_GPIOE_6 (_NGPIODIRQS + 6) +# define LM_IRQ_GPIOE_7 (_NGPIODIRQS + 7) +# define _NGPIOEIRQS (_NGPIODIRQS + 8) #else -# define _NGPIOEIRQS _NGPIODIRQS +# define _NGPIOEIRQS _NGPIODIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS -# define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0) -# define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1) -# define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2) -# define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3) -# define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4) -# define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5) -# define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6) -# define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7) -# define _NGPIOFIRQS (_NGPIOEIRQS + 8) +# define LM_IRQ_GPIOF_0 (_NGPIOEIRQS + 0) +# define LM_IRQ_GPIOF_1 (_NGPIOEIRQS + 1) +# define LM_IRQ_GPIOF_2 (_NGPIOEIRQS + 2) +# define LM_IRQ_GPIOF_3 (_NGPIOEIRQS + 3) +# define LM_IRQ_GPIOF_4 (_NGPIOEIRQS + 4) +# define LM_IRQ_GPIOF_5 (_NGPIOEIRQS + 5) +# define LM_IRQ_GPIOF_6 (_NGPIOEIRQS + 6) +# define LM_IRQ_GPIOF_7 (_NGPIOEIRQS + 7) +# define _NGPIOFIRQS (_NGPIOEIRQS + 8) #else -# define _NGPIOFIRQS _NGPIOEIRQS +# define _NGPIOFIRQS _NGPIOEIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS -# define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0) -# define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1) -# define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2) -# define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3) -# define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4) -# define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5) -# define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6) -# define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7) -# define _NGPIOGIRQS (_NGPIOFIRQS + 8) +# define LM_IRQ_GPIOG_0 (_NGPIOFIRQS + 0) +# define LM_IRQ_GPIOG_1 (_NGPIOFIRQS + 1) +# define LM_IRQ_GPIOG_2 (_NGPIOFIRQS + 2) +# define LM_IRQ_GPIOG_3 (_NGPIOFIRQS + 3) +# define LM_IRQ_GPIOG_4 (_NGPIOFIRQS + 4) +# define LM_IRQ_GPIOG_5 (_NGPIOFIRQS + 5) +# define LM_IRQ_GPIOG_6 (_NGPIOFIRQS + 6) +# define LM_IRQ_GPIOG_7 (_NGPIOFIRQS + 7) +# define _NGPIOGIRQS (_NGPIOFIRQS + 8) #else -# define _NGPIOGIRQS _NGPIOFIRQS +# define _NGPIOGIRQS _NGPIOFIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS -# define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0) -# define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1) -# define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2) -# define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3) -# define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4) -# define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5) -# define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6) -# define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7) -# define _NGPIOHIRQS (_NGPIOGIRQS + 8) +# define LM_IRQ_GPIOH_0 (_NGPIOGIRQS + 0) +# define LM_IRQ_GPIOH_1 (_NGPIOGIRQS + 1) +# define LM_IRQ_GPIOH_2 (_NGPIOGIRQS + 2) +# define LM_IRQ_GPIOH_3 (_NGPIOGIRQS + 3) +# define LM_IRQ_GPIOH_4 (_NGPIOGIRQS + 4) +# define LM_IRQ_GPIOH_5 (_NGPIOGIRQS + 5) +# define LM_IRQ_GPIOH_6 (_NGPIOGIRQS + 6) +# define LM_IRQ_GPIOH_7 (_NGPIOGIRQS + 7) +# define _NGPIOHIRQS (_NGPIOGIRQS + 8) #else -# define _NGPIOHIRQS _NGPIOGIRQS +# define _NGPIOHIRQS _NGPIOGIRQS #endif #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS -# define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0) -# define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1) -# define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2) -# define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3) -# define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4) -# define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5) -# define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6) -# define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7) -# define _NGPIOJIRQS (_NGPIOHIRQS + 8) +# define LM_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0) +# define LM_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1) +# define LM_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2) +# define LM_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3) +# define LM_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4) +# define LM_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5) +# define LM_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6) +# define LM_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7) +# define _NGPIOJIRQS (_NGPIOHIRQS + 8) #else -# define _NGPIOJIRQS _NGPIOHIRQS +# define _NGPIOJIRQS _NGPIOHIRQS #endif -#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS) +#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS) /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h index 51de04a2b..32b7a9f18 100644 --- a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h +++ b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h @@ -50,44 +50,44 @@ #if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0xdfffffff: Reserved */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ +# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0xdfffffff: Reserved */ +# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0x5fffffff: Reserved */ -# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ -# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ +# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0x5fffffff: Reserved */ +# define LM_EPI0RAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */ +# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ #else # error "Memory map not specified for this LM3S chip" #endif @@ -102,247 +102,247 @@ #if defined(CONFIG_ARCH_CHIP_LM3S6918) /* FiRM Peripheral Base Addresses */ -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ +# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ + /* -0x0bfff: Reserved */ +# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ /* Peripheral Base Addresses */ -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ +# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + /* -0x2ffff: Reserved */ +# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ #elif defined(CONFIG_ARCH_CHIP_LM3S6432) /* FiRM Peripheral Base Addresses */ -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ +# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ /* Peripheral Base Addresses */ -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ +# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2ffff: Reserved */ +# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ + /* -0x37fff: Reserved */ +# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ #elif defined(CONFIG_ARCH_CHIP_LM3S6965) /* FiRM Peripheral Base Addresses */ -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ +# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ /* Peripheral Base Addresses */ -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ +# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ #elif defined(CONFIG_ARCH_CHIP_LM3S8962) /* FiRM Peripheral Base Addresses */ -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ +# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ /* Peripheral Base Addresses */ -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x3fffff: Reserved */ -# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ +# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x3fffff: Reserved */ +# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ + /* -0x47fff: Reserved */ +# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ +# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) /* FiRM Peripheral Base Addresses */ -# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ +# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ /* Peripheral Base Addresses */ -# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ +# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ -# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ -# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ - /* -0x3bfff: Reserved */ -# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ -# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ - /* -0x3ffff: Reserved */ -# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ -# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ - /* -0x47fff: Reserved */ -# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0x49fff: Reserved */ -# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ - /* -0x53fff: Reserved */ -# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ - /* -0x57fff: Reserved */ -# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ -# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ -# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ -# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ -# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ -# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ -# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ -# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ -# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ - /* -0xcffff: Reserved */ -# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ - /* -0xfcfff: Reserved */ -# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ -# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ - /* -0x1ffffff: Reserved */ +# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ +# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ + /* -0x3bfff: Reserved */ +# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ +# define LM_GPIOJ_BASE (LM_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ + /* -0x3ffff: Reserved */ +# define LM_CAN0_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ +# define LM_CAN1_BASE (LM_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ + /* -0x47fff: Reserved */ +# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0x49fff: Reserved */ +# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ + /* -0x53fff: Reserved */ +# define LM_I2S0_BASE (LM_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ + /* -0x57fff: Reserved */ +# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ +# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ +# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ +# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ +# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ +# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ +# define LM_GPIOGAHB_BASE (LM_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ +# define LM_GPIOHAHB_BASE (LM_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ +# define LM_GPIOJAHB_BASE (LM_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ + /* -0xcffff: Reserved */ +# define LM_EPI0_BASE (LM_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ + /* -0xfcfff: Reserved */ +# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ +# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ + /* -0x1ffffff: Reserved */ #else -# error "Peripheral base addresses not specified for this LM3S chip" +# error "Peripheral base addresses not specified for this Stellaris chip" #endif /************************************************************************************ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h index a478304b0..ca1d53064 100644 --- a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h +++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h @@ -263,7 +263,7 @@ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ #else -# error "Unknown LM3S chip" +# error "Unknown Stellaris chip" #endif /************************************************************************************ diff --git a/nuttx/arch/arm/src/lm/chip/lm_epi.h b/nuttx/arch/arm/src/lm/chip/lm_epi.h index e36986079..47d790615 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_epi.h +++ b/nuttx/arch/arm/src/lm/chip/lm_epi.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H /************************************************************************************ * Included Files @@ -46,19 +46,19 @@ /* External Peripheral Interface Register Offsets ***********************************/ -#define LM3S_EPI_CFG_OFFSET 0x000 -#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 -#define LM3S_EPI_ADDRMAP_OFFSET 0x01C -#define LM3S_EPI_STAT_OFFSET 0x060 -#define LM3S_EPI_BAUD_OFFSET 0x004 +#define LM_EPI_CFG_OFFSET 0x000 +#define LM_EPI_SDRAMCFG_OFFSET 0x010 +#define LM_EPI_ADDRMAP_OFFSET 0x01C +#define LM_EPI_STAT_OFFSET 0x060 +#define LM_EPI_BAUD_OFFSET 0x004 /* External Peripheral Interface Register Addresses *********************************/ -#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) -#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) -#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) -#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) -#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) +#define LM_EPI0_CFG (LM_EPI0_BASE + LM_EPI_CFG_OFFSET) +#define LM_EPI0_SDRAMCFG (LM_EPI0_BASE + LM_EPI_SDRAMCFG_OFFSET) +#define LM_EPI0_ADDRMAP (LM_EPI0_BASE + LM_EPI_ADDRMAP_OFFSET) +#define LM_EPI0_STAT (LM_EPI0_BASE + LM_EPI_STAT_OFFSET) +#define LM_EPI0_BAUD (LM_EPI0_BASE + LM_EPI_BAUD_OFFSET) /* External Peripheral Interface Register Bit Definitions ***************************/ @@ -110,4 +110,4 @@ #define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) # define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h index 46a101005..02908d222 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h +++ b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H /************************************************************************************ * Included Files @@ -53,63 +53,63 @@ /* Ethernet MAC Register Offsets */ -#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ -#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ -#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ -#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ -#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ -#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ -#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ -#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ -#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ -#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ -#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ -#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ -#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ -#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ -#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ +#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ +#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ +#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ +#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ +#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ +#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ +#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ +#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ +#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ +#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ +#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ +#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ +#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ +#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ +#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ +#ifdef LM_ETHTS +# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ #endif /* MII Management Register Offsets (see include/nuttx/net/mii.h) */ /* Ethernet Controller Register Addresses *******************************************/ -#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) -#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) -#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) -#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) -#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) -#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) -#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) -#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) -#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) -#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) -#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) -#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) -#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) -#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) -#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) -#ifdef LM3S_ETHTS -# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) +#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET) +#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET) +#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET) +#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET) +#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET) +#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET) +#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET) +#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET) +#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET) +#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET) +#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET) +#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET) +#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET) +#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET) +#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET) +#ifdef LM_ETHTS +# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET) #endif /* Memory Mapped MII Management Registers */ -#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) -#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) -#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) -#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) -#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) -#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) -#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) -#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) -#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) -#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) -#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) -#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) -#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) +#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR) +#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR) +#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1) +#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2) +#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE) +#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA) +#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION) +#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC) +#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS) +#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC) +#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL) +#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG) +#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL) /* Ethernet Controller Register Bit Definitions *************************************/ @@ -200,4 +200,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_flash.h b/nuttx/arch/arm/src/lm/chip/lm_flash.h index 0d4808526..e5869bb0e 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_flash.h +++ b/nuttx/arch/arm/src/lm/chip/lm_flash.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H /************************************************************************************ * Included Files @@ -49,66 +49,66 @@ /* FLASH register offsets ***********************************************************/ /* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. + * control base address of LM_FLASHCON_BASE. */ -#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ -#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ -#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ -#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ -#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ -#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ +#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ +#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ +#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ +#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ +#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ +#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ /* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE + * System Control base address of LM_SYSCON_BASE */ -#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ -#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ -#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ -#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ -#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ -#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ -#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ -#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ -#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ -#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ -#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ -#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ -#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ -#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ +#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ +#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ +#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ +#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ +#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ +#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ +#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ +#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ +#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ +#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ +#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ +#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ +#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ +#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ /* FLASH register addresses *********************************************************/ /* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM3S_FLASHCON_BASE. + * control base address of LM_FLASHCON_BASE. */ -#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) -#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) -#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) -#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) -#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) -#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) +#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET) +#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET) +#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET) +#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET) +#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET) +#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET) /* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM3S_SYSCON_BASE + * System Control base address of LM_SYSCON_BASE */ -#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) -#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) -#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) -#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) -#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) -#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) -#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) -#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) -#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) -#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) -#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) -#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) -#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) -#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) +#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET) +#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET) +#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET) +#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET) +#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET) +#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET) +#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET) +#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET) +#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET) +#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET) +#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET) +#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET) +#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET) +#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET) /* FLASH register bit defitiions ****************************************************/ /* To be provided */ @@ -125,4 +125,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_gpio.h b/nuttx/arch/arm/src/lm/chip/lm_gpio.h index 4ca8e8ff9..30b850fca 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_gpio.h +++ b/nuttx/arch/arm/src/lm/chip/lm_gpio.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H /************************************************************************************ * Included Files @@ -48,337 +48,337 @@ /* GPIO Register Offsets ************************************************************/ -#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ -#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ -#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ -#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ -#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ -#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ -#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ -#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ -#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ -#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ -#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ -#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ -#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ -#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ -#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ -#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ -#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ -#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ -#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ -#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ -#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ -#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ -#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ -#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ -#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ -#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ -#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ -#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ -#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ -#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ -#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ -#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ +#define LM_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ +#define LM_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ +#define LM_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ +#define LM_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ +#define LM_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ +#define LM_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ +#define LM_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ +#define LM_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ +#define LM_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ +#define LM_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ +#define LM_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ +#define LM_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ +#define LM_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ +#define LM_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ +#define LM_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ +#define LM_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ +#define LM_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ +#define LM_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ +#define LM_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ +#define LM_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ +#define LM_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ +#define LM_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ +#define LM_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ +#define LM_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ +#define LM_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ +#define LM_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ +#define LM_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ +#define LM_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ +#define LM_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ +#define LM_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ +#define LM_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ +#define LM_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ /* GPIO Register Addresses **********************************************************/ -#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOA_DATA (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOA_DIR (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOA_IS (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOA_IBE (LM_GPIOA_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOA_IEV (LM_GPIOA_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOA_IM (LM_GPIOA_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOA_RIS (LM_GPIOA_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOA_MIS (LM_GPIOA_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOA_ICR (LM_GPIOA_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOA_AFSEL (LM_GPIOA_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOA_DR2R (LM_GPIOA_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOA_DR4R (LM_GPIOA_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOA_DR8R (LM_GPIOA_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOA_ODR (LM_GPIOA_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOA_PUR (LM_GPIOA_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOA_PDR (LM_GPIOA_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOA_SLR (LM_GPIOA_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOA_DEN (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOA_LOCK (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOA_CR (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOA_PERIPHID4 (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOA_PERIPHID5 (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOA_PERIPHID6 (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOA_PERIPHID7 (LM_GPIOA_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOA_PERIPHID0 (LM_GPIOA_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOA_PERIPHID1 (LM_GPIOA_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOA_PERIPHID2 (LM_GPIOA_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOA_PERIPHID3 (LM_GPIOA_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOA_PCELLID0 (LM_GPIOA_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOA_PCELLID1 (LM_GPIOA_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOA_PCELLID2 (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOA_PCELLID3 (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOB_DATA (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOB_DIR (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOB_IS (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOB_IBE (LM_GPIOB_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOB_IEV (LM_GPIOB_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOB_IM (LM_GPIOB_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOB_RIS (LM_GPIOB_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOB_MIS (LM_GPIOB_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOB_ICR (LM_GPIOB_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOB_AFSEL (LM_GPIOB_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOB_DR2R (LM_GPIOB_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOB_DR4R (LM_GPIOB_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOB_DR8R (LM_GPIOB_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOB_ODR (LM_GPIOB_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOB_PUR (LM_GPIOB_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOB_PDR (LM_GPIOB_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOB_SLR (LM_GPIOB_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOB_DEN (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOB_LOCK (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOB_CR (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOB_PERIPHID4 (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOB_PERIPHID5 (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOB_PERIPHID6 (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOB_PERIPHID7 (LM_GPIOB_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOB_PERIPHID0 (LM_GPIOB_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOB_PERIPHID1 (LM_GPIOB_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOB_PERIPHID2 (LM_GPIOB_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOB_PERIPHID3 (LM_GPIOB_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOB_PCELLID0 (LM_GPIOB_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOB_PCELLID1 (LM_GPIOB_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOB_PCELLID2 (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOB_PCELLID3 (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOC_DATA (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOC_DIR (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOC_IS (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOC_IBE (LM_GPIOC_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOC_IEV (LM_GPIOC_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOC_IM (LM_GPIOC_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOC_RIS (LM_GPIOC_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOC_MIS (LM_GPIOC_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOC_ICR (LM_GPIOC_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOC_AFSEL (LM_GPIOC_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOC_DR2R (LM_GPIOC_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOC_DR4R (LM_GPIOC_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOC_DR8R (LM_GPIOC_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOC_ODR (LM_GPIOC_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOC_PUR (LM_GPIOC_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOC_PDR (LM_GPIOC_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOC_SLR (LM_GPIOC_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOC_DEN (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOC_LOCK (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOC_CR (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOC_PERIPHID4 (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOC_PERIPHID5 (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOC_PERIPHID6 (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOC_PERIPHID7 (LM_GPIOC_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOC_PERIPHID0 (LM_GPIOC_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOC_PERIPHID1 (LM_GPIOC_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOC_PERIPHID2 (LM_GPIOC_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOC_PERIPHID3 (LM_GPIOC_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOC_PCELLID0 (LM_GPIOC_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOC_PCELLID1 (LM_GPIOC_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOC_PCELLID2 (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOC_PCELLID3 (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOD_DATA (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOD_DIR (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOD_IS (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOD_IBE (LM_GPIOD_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOD_IEV (LM_GPIOD_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOD_IM (LM_GPIOD_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOD_RIS (LM_GPIOD_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOD_MIS (LM_GPIOD_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOD_ICR (LM_GPIOD_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOD_AFSEL (LM_GPIOD_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOD_DR2R (LM_GPIOD_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOD_DR4R (LM_GPIOD_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOD_DR8R (LM_GPIOD_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOD_ODR (LM_GPIOD_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOD_PUR (LM_GPIOD_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOD_PDR (LM_GPIOD_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOD_SLR (LM_GPIOD_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOD_DEN (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOD_LOCK (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOD_CR (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOD_PERIPHID4 (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOD_PERIPHID5 (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOD_PERIPHID6 (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOD_PERIPHID7 (LM_GPIOD_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOD_PERIPHID0 (LM_GPIOD_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOD_PERIPHID1 (LM_GPIOD_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOD_PERIPHID2 (LM_GPIOD_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOD_PERIPHID3 (LM_GPIOD_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOD_PCELLID0 (LM_GPIOD_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOD_PCELLID1 (LM_GPIOD_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOD_PCELLID2 (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOD_PCELLID3 (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOE_DATA (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOE_DIR (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOE_IS (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOE_IBE (LM_GPIOE_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOE_IEV (LM_GPIOE_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOE_IM (LM_GPIOE_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOE_RIS (LM_GPIOE_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOE_MIS (LM_GPIOE_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOE_ICR (LM_GPIOE_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOE_AFSEL (LM_GPIOE_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOE_DR2R (LM_GPIOE_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOE_DR4R (LM_GPIOE_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOE_DR8R (LM_GPIOE_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOE_ODR (LM_GPIOE_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOE_PUR (LM_GPIOE_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOE_PDR (LM_GPIOE_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOE_SLR (LM_GPIOE_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOE_DEN (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOE_LOCK (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOE_CR (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOE_PERIPHID4 (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOE_PERIPHID5 (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOE_PERIPHID6 (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOE_PERIPHID7 (LM_GPIOE_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOE_PERIPHID0 (LM_GPIOE_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOE_PERIPHID1 (LM_GPIOE_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOE_PERIPHID2 (LM_GPIOE_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOE_PERIPHID3 (LM_GPIOE_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOE_PCELLID0 (LM_GPIOE_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOE_PCELLID1 (LM_GPIOE_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOE_PCELLID2 (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOE_PCELLID3 (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOF_DATA (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOF_DIR (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOF_IS (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOF_IBE (LM_GPIOF_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOF_IEV (LM_GPIOF_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOF_IM (LM_GPIOF_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOF_RIS (LM_GPIOF_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOF_MIS (LM_GPIOF_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOF_ICR (LM_GPIOF_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOF_AFSEL (LM_GPIOF_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOF_DR2R (LM_GPIOF_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOF_DR4R (LM_GPIOF_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOF_DR8R (LM_GPIOF_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOF_ODR (LM_GPIOF_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOF_PUR (LM_GPIOF_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOF_PDR (LM_GPIOF_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOF_SLR (LM_GPIOF_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOF_DEN (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOF_LOCK (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOF_CR (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOF_PERIPHID4 (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOF_PERIPHID5 (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOF_PERIPHID6 (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOF_PERIPHID7 (LM_GPIOF_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOF_PERIPHID0 (LM_GPIOF_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOF_PERIPHID1 (LM_GPIOF_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOF_PERIPHID2 (LM_GPIOF_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOF_PERIPHID3 (LM_GPIOF_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOF_PCELLID0 (LM_GPIOF_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOF_PCELLID1 (LM_GPIOF_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOF_PCELLID2 (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOF_PCELLID3 (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOG_DATA (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOG_DIR (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOG_IS (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOG_IBE (LM_GPIOG_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOG_IEV (LM_GPIOG_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOG_IM (LM_GPIOG_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOG_RIS (LM_GPIOG_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOG_MIS (LM_GPIOG_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOG_ICR (LM_GPIOG_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOG_AFSEL (LM_GPIOG_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOG_DR2R (LM_GPIOG_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOG_DR4R (LM_GPIOG_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOG_DR8R (LM_GPIOG_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOG_ODR (LM_GPIOG_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOG_PUR (LM_GPIOG_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOG_PDR (LM_GPIOG_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOG_SLR (LM_GPIOG_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOG_DEN (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOG_LOCK (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOG_CR (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOG_PERIPHID4 (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOG_PERIPHID5 (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOG_PERIPHID6 (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOG_PERIPHID7 (LM_GPIOG_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOG_PERIPHID0 (LM_GPIOG_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOG_PERIPHID1 (LM_GPIOG_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOG_PERIPHID2 (LM_GPIOG_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOG_PERIPHID3 (LM_GPIOG_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOG_PCELLID0 (LM_GPIOG_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOG_PCELLID1 (LM_GPIOG_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOG_PCELLID2 (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOG_PCELLID3 (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOH_DATA (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOH_DIR (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOH_IS (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOH_IBE (LM_GPIOH_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOH_IEV (LM_GPIOH_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOH_IM (LM_GPIOH_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOH_RIS (LM_GPIOH_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOH_MIS (LM_GPIOH_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOH_ICR (LM_GPIOH_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOH_AFSEL (LM_GPIOH_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOH_DR2R (LM_GPIOH_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOH_DR4R (LM_GPIOH_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOH_DR8R (LM_GPIOH_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOH_ODR (LM_GPIOH_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOH_PUR (LM_GPIOH_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOH_PDR (LM_GPIOH_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOH_SLR (LM_GPIOH_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOH_DEN (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOH_LOCK (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOH_CR (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOH_PERIPHID4 (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOH_PERIPHID5 (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOH_PERIPHID6 (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOH_PERIPHID7 (LM_GPIOH_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOH_PERIPHID0 (LM_GPIOH_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOH_PERIPHID1 (LM_GPIOH_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOH_PERIPHID2 (LM_GPIOH_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOH_PERIPHID3 (LM_GPIOH_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOH_PCELLID0 (LM_GPIOH_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOH_PCELLID1 (LM_GPIOH_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOH_PCELLID2 (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOH_PCELLID3 (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET) -#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) -#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) -#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) -#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) -#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) -#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) -#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) -#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) -#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) -#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) -#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) -#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) -#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) -#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) -#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) -#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) -#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) -#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) -#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) -#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) -#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) -#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) -#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) -#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) -#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) -#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) -#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) -#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) -#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) -#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) -#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) -#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM_GPIOJ_DATA (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET) +#define LM_GPIOJ_DIR (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET) +#define LM_GPIOJ_IS (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET) +#define LM_GPIOJ_IBE (LM_GPIOJ_BASE + LM_GPIO_IBE_OFFSET) +#define LM_GPIOJ_IEV (LM_GPIOJ_BASE + LM_GPIO_IEV_OFFSET) +#define LM_GPIOJ_IM (LM_GPIOJ_BASE + LM_GPIO_IM_OFFSET) +#define LM_GPIOJ_RIS (LM_GPIOJ_BASE + LM_GPIO_RIS_OFFSET) +#define LM_GPIOJ_MIS (LM_GPIOJ_BASE + LM_GPIO_MIS_OFFSET) +#define LM_GPIOJ_ICR (LM_GPIOJ_BASE + LM_GPIO_ICR_OFFSET) +#define LM_GPIOJ_AFSEL (LM_GPIOJ_BASE + LM_GPIO_AFSEL_OFFSET) +#define LM_GPIOJ_DR2R (LM_GPIOJ_BASE + LM_GPIO_DR2R_OFFSET) +#define LM_GPIOJ_DR4R (LM_GPIOJ_BASE + LM_GPIO_DR4R_OFFSET) +#define LM_GPIOJ_DR8R (LM_GPIOJ_BASE + LM_GPIO_DR8R_OFFSET) +#define LM_GPIOJ_ODR (LM_GPIOJ_BASE + LM_GPIO_ODR_OFFSET) +#define LM_GPIOJ_PUR (LM_GPIOJ_BASE + LM_GPIO_PUR_OFFSET) +#define LM_GPIOJ_PDR (LM_GPIOJ_BASE + LM_GPIO_PDR_OFFSET) +#define LM_GPIOJ_SLR (LM_GPIOJ_BASE + LM_GPIO_SLR_OFFSET) +#define LM_GPIOJ_DEN (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET) +#define LM_GPIOJ_LOCK (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET) +#define LM_GPIOJ_CR (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET) +#define LM_GPIOJ_PERIPHID4 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET) +#define LM_GPIOJ_PERIPHID5 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET) +#define LM_GPIOJ_PERIPHID6 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET) +#define LM_GPIOJ_PERIPHID7 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID7_OFFSET) +#define LM_GPIOJ_PERIPHID0 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID0_OFFSET) +#define LM_GPIOJ_PERIPHID1 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID1_OFFSET) +#define LM_GPIOJ_PERIPHID2 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID2_OFFSET) +#define LM_GPIOJ_PERIPHID3 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID3_OFFSET) +#define LM_GPIOJ_PCELLID0 (LM_GPIOJ_BASE + LM_GPIO_PCELLID0_OFFSET) +#define LM_GPIOJ_PCELLID1 (LM_GPIOJ_BASE + LM_GPIO_PCELLID1_OFFSET) +#define LM_GPIOJ_PCELLID2 (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET) +#define LM_GPIOJ_PCELLID3 (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET) /************************************************************************************ * Public Types @@ -392,4 +392,4 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_i2c.h b/nuttx/arch/arm/src/lm/chip/lm_i2c.h index 919ac1348..88ce31b77 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_i2c.h +++ b/nuttx/arch/arm/src/lm/chip/lm_i2c.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H /************************************************************************************ * Included Files @@ -50,99 +50,99 @@ /* I2C Master */ -#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ -#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ -#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ -#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ -#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ -#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ -#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ -#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ -#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ +#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ +#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ +#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ +#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ +#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ +#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ +#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ +#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ +#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ /* I2C Slave */ -#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ -#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ -#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ -#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ -#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ -#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ -#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ +#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ +#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ +#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ +#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ +#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ +#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ +#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ /* I2C Register Addresses ***********************************************************/ -#if LM3S_NI2C > 0 +#if LM_NI2C > 0 /* I2C Master */ -#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) -#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) +#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000) +#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET) +#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET) +#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET) +#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET) +#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET) +#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET) +#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET) +#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET) +#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET) /* I2C Slave */ -#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) -#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) +#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000) +#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET) +#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET) +#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET) +#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET) +#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET) +#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET) +#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET) /* I2C0 Master */ -#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) +#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET) +#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET) +#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET) +#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET) +#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET) +#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET) +#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET) +#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET) +#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET) /* I2C0 Slave */ -#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) +#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET) +#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET) +#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET) +#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET) +#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET) +#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET) +#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET) -#if LM3S_NI2C > 1 +#if LM_NI2C > 1 /* I2C1 Master */ -#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) -#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) -#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) -#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) -#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) -#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) -#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) -#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) -#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) +#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET) +#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET) +#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET) +#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET) +#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET) +#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET) +#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET) +#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET) +#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET) /* I2C1 Slave */ -#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) -#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) -#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) -#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) -#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) -#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) -#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) +#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET) +#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET) +#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET) +#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET) +#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET) +#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET) +#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET) #endif #endif @@ -244,4 +244,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h index b8154dd9f..311d6fcdc 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h +++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h @@ -42,7 +42,7 @@ #include -/* Include the memory map file for the specific Stellaris chip */ +/* Include the pin mapping file for the specific Stellaris chip */ #ifdef CONFIG_ARCH_CHIP_LM3S # include "chip/lm3s_pinmap.h" diff --git a/nuttx/arch/arm/src/lm/chip/lm_ssi.h b/nuttx/arch/arm/src/lm/chip/lm_ssi.h index b58aec733..5243bf112 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_ssi.h +++ b/nuttx/arch/arm/src/lm/chip/lm_ssi.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H /************************************************************************************ * Included Files @@ -43,7 +43,7 @@ #include #include -#if LM3S_NSSI > 0 +#if LM_NSSI > 0 /************************************************************************************ * Definitions @@ -51,173 +51,173 @@ /* SSI register offsets *************************************************************/ -#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ -#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ -#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ -#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ -#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ -#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ -#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ -#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ -#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ -#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ -#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ -#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ -#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ -#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ -#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ -#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ -#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ -#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ -#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ -#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ -#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ +#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ +#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ +#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */ +#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */ +#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ +#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ +#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ +#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ +#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ +#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ +#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ +#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ +#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ +#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ +#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ +#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ +#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ +#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ +#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ +#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ +#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ /* SSI register addresses ***********************************************************/ -#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#if LM3S_NSSI > 1 -#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) - -#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) - -#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) -#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) -#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) -#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) -#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) -#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) -#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) -#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) -#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) -#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) -#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) -#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) -#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) -#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) -#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) -#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) -#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) -#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) -#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) -#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) -#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) -#endif /* LM3S_NSSI > 1 */ +#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET) +#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET) +#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET) +#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET) +#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET) +#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET) +#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET) +#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET) +#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET) +#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET) +#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET) +#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET) +#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET) +#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET) +#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET) +#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET) +#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET) +#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET) +#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET) +#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET) +#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET) + +#if LM_NSSI > 1 +#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET) +#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET) +#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET) +#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET) +#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET) +#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET) +#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET) +#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET) +#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET) +#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET) +#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET) +#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET) +#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET) +#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET) +#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET) +#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET) +#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET) +#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET) +#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET) +#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET) +#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET) + +#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000) + +#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET) +#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET) +#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET) +#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET) +#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET) +#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET) +#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET) +#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET) +#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET) +#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET) +#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET) +#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET) +#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET) +#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET) +#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET) +#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET) +#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET) +#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET) +#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET) +#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET) +#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET) +#endif /* LM_NSSI > 1 */ /* SSI register bit defitiions ******************************************************/ /* SSI Control 0 (SSICR0), offset 0x000 */ -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ -#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) -#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ -#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ -#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ -#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ -#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ -#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ -#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ -#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ +#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) +#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ +#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ +#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ +#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ +#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ +#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ +#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) /* SSI Control 1 (SSICR1), offset 0x004 */ -#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ -#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ -#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ -#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ +#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ +#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ +#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ +#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ /* SSI Data (SSIDR), offset 0x008 */ -#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ +#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ /* SSI Status (SSISR), offset 0x00c */ -#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ -#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ -#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ -#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ -#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ +#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ +#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ +#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ +#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ +#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ /* SSI Clock Prescale (SSICPSR), offset 0x010 */ -#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ +#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ /* SSI Interrupt Mask (SSIIM), offset 0x014 */ -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ /* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ /* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ /* SSI Interrupt Clear (SSIICR), offset 0x020 */ -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ /* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ /* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ /************************************************************************************ * Public Types @@ -231,5 +231,5 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* LM3S_NSSI > 0 */ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */ +#endif /* LM_NSSI > 0 */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h index 6ca8ac3ff..444a1271c 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h +++ b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H /************************************************************************************ * Included Files @@ -48,67 +48,67 @@ /* System Control Register Offsets **************************************************/ -#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ -#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ -#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ -#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ -#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ +#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ +#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ +#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ +#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ +#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ +#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ +#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ +#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ +#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ +#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ +#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ +#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ +#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ +#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ +#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ +#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ +#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ +#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ +#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ +#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ +#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ +#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ +#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ +#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ +#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ +#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ +#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ +#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ +#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ /* System Control Register Addresses ************************************************/ -#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) -#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) -#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) -#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) -#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) -#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) -#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) -#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) -#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) -#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) -#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) -#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) -#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) -#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) -#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) -#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) -#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) -#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) -#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) -#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) -#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) -#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) -#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) -#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) -#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) -#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) -#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) -#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) -#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) +#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET) +#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET) +#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET) +#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET) +#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET) +#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET) +#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET) +#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET) +#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET) +#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET) +#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET) +#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET) +#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET) +#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET) +#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET) +#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET) +#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET) +#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET) +#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET) +#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET) +#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET) +#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET) +#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET) +#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET) +#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET) +#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET) +#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET) +#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET) +#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET) /* System Control Register Bit Definitions ******************************************/ @@ -492,4 +492,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_timer.h b/nuttx/arch/arm/src/lm/chip/lm_timer.h index f2824ce1f..5ed68f13a 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_timer.h +++ b/nuttx/arch/arm/src/lm/chip/lm_timer.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H /************************************************************************************ * Included Files @@ -46,27 +46,27 @@ /* Timer register offsets ***********************************************************/ -#define TIMER_GPTMCFG_OFFSET 0x000 -#define TIMER_GPTMTAMR_OFFSET 0x004 -#define TIMER_GPTMCTL_OFFSET 0x00C -#define TIMER_GPTMIMR_OFFSET 0x018 -#define TIMER_GPTMRIS_OFFSET 0x01C -#define TIMER_GPTMICR_OFFSET 0x024 -#define TIMER_GPTMTAILR_OFFSET 0x028 -#define TIMER_GPTMTAR_OFFSET 0x048 +#define LM_TIMER_GPTMCFG_OFFSET 0x000 +#define LM_TIMER_GPTMTAMR_OFFSET 0x004 +#define LM_TIMER_GPTMCTL_OFFSET 0x00c +#define LM_TIMER_GPTMIMR_OFFSET 0x018 +#define LM_TIMER_GPTMRIS_OFFSET 0x01c +#define LM_TIMER_GPTMICR_OFFSET 0x024 +#define LM_TIMER_GPTMTAILR_OFFSET 0x028 +#define LM_TIMER_GPTMTAR_OFFSET 0x048 /* SSI register addresses ***********************************************************/ -#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) +#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000) -#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) -#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) -#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) -#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) -#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) -#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) -#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) -#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) +#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET) +#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET) +#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET) +#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET) +#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET) +#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET) +#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET) +#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET) /* SSI register bit defitiions ******************************************************/ @@ -122,4 +122,4 @@ #define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ #define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_uart.h b/nuttx/arch/arm/src/lm/chip/lm_uart.h index 9a03ff063..2ad065294 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_uart.h +++ b/nuttx/arch/arm/src/lm/chip/lm_uart.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_UART_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_UART_H /************************************************************************************ * Included Files @@ -48,117 +48,117 @@ /* UART register offsets ************************************************************/ -#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ -#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ -#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ -#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ -#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ -#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ -#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ -#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ -#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ -#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ -#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ -#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ -#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ -#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ -#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ -#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ -#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ -#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ -#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ -#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ -#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ -#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ -#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ -#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ -#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ -#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ +#define LM_UART_DR_OFFSET 0x000 /* UART Data */ +#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */ +#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */ +#define LM_UART_FR_OFFSET 0x018 /* UART Flag */ +#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ +#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ +#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ +#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */ +#define LM_UART_CTL_OFFSET 0x030 /* UART Control */ +#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ +#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ +#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ +#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ +#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ +#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ +#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ +#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ +#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ +#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ +#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ +#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ +#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ +#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ +#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ +#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ +#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ /* UART register addresses **********************************************************/ -#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) - -#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) -#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) -#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) -#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) -#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) -#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) -#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) -#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) -#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) -#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) -#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) - -#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) -#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) -#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) -#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) -#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) -#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) -#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) -#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) -#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) -#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) -#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) -#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) -#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) -#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) -#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) -#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) -#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) -#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) -#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) -#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) -#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) -#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) -#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) -#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) -#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) -#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) +#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000) + +#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET) +#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET) +#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET) +#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET) +#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET) +#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET) +#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET) +#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET) +#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET) +#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET) +#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET) +#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET) +#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET) +#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET) +#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET) +#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET) +#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET) +#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET) +#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET) +#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET) +#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET) +#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET) +#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET) +#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET) +#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET) +#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET) + +#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET) +#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET) +#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET) +#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET) +#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET) +#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET) +#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET) +#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET) +#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET) +#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET) +#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET) +#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET) +#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET) +#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET) +#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET) +#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET) +#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET) +#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET) +#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET) +#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET) +#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET) +#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET) +#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET) +#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET) +#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET) +#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET) + +#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET) +#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET) +#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET) +#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET) +#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET) +#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET) +#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET) +#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET) +#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET) +#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET) +#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET) +#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET) +#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET) +#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET) +#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET) +#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET) +#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET) +#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET) +#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET) +#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET) +#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET) +#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET) +#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET) +#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET) +#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET) +#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET) /* UART register bit settings *******************************************************/ @@ -275,62 +275,62 @@ /* UART Interrupt Clear (ICR), offset 0x044 */ -#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ -#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ -#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ -#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ -#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ -#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ -#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear +#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ +#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ +#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ +#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ +#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ +#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ +#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear */ /* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ -#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ +#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ /* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ -#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ +#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ /* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ -#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ +#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ /* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ -#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ +#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ /* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ -#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ +#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ /* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ -#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ +#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ /* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ -#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ +#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ /* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ -#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ +#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ /* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ -#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ +#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ /* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ -#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ +#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ /* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ -#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ +#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ /* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ -#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ +#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ /************************************************************************************ * Public Types @@ -344,4 +344,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_UART_H */ diff --git a/nuttx/arch/arm/src/lm/lm_dumpgpio.c b/nuttx/arch/arm/src/lm/lm_dumpgpio.c index a3190784b..f71e9c9a0 100644 --- a/nuttx/arch/arm/src/lm/lm_dumpgpio.c +++ b/nuttx/arch/arm/src/lm/lm_dumpgpio.c @@ -60,19 +60,19 @@ /* NOTE: this is duplicated in lm_gpio.c */ -#ifdef LM3S_GPIOH_BASE +#ifdef LM_GPIOH_BASE static const uint32_t g_gpiobase[8] = { - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, + LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE, + LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, LM_GPIOH_BASE, }; static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; #else static const uint32_t g_gpiobase[8] = { - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, + LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE, + LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, 0, }; static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; @@ -138,7 +138,7 @@ int lm_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ flags = irqsave(); - rcgc2 = getreg32(LM3S_SYSCON_RCGC2); + rcgc2 = getreg32(LM_SYSCON_RCGC2); enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", @@ -151,16 +151,16 @@ int lm_dumpgpio(uint32_t pinset, const char *msg) if (enabled) { lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", - getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), - getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); + getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET), + getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc)); lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", - getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), - getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); + getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET), + getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET)); lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", - getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), - getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), - getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), - getreg32(base + LM3S_GPIO_SLR_OFFSET)); + getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET), + getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET), + getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET), + getreg32(base + LM_GPIO_SLR_OFFSET)); } irqrestore(flags); return OK; diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.c b/nuttx/arch/arm/src/lm/lm_ethernet.c index 1d8def2e9..861d64d95 100644 --- a/nuttx/arch/arm/src/lm/lm_ethernet.c +++ b/nuttx/arch/arm/src/lm/lm_ethernet.c @@ -69,68 +69,68 @@ /* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */ #ifdef CONFIG_LM_ETHHDUPLEX -# define LM3S_DUPLEX_SETBITS 0 -# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX +# define LM_DUPLEX_SETBITS 0 +# define LM_DUPLEX_CLRBITS MAC_TCTL_DUPLEX #else -# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX -# define LM3S_DUPLEX_CLRBITS 0 +# define LM_DUPLEX_SETBITS MAC_TCTL_DUPLEX +# define LM_DUPLEX_CLRBITS 0 #endif /* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */ #ifdef CONFIG_LM_ETHNOAUTOCRC -# define LM3S_CRC_SETBITS 0 -# define LM3S_CRC_CLRBITS MAC_TCTL_CRC +# define LM_CRC_SETBITS 0 +# define LM_CRC_CLRBITS MAC_TCTL_CRC #else -# define LM3S_CRC_SETBITS MAC_TCTL_CRC -# define LM3S_CRC_CLRBITS 0 +# define LM_CRC_SETBITS MAC_TCTL_CRC +# define LM_CRC_CLRBITS 0 #endif /* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */ #ifdef CONFIG_LM_ETHNOPAD -# define LM3S_PADEN_SETBITS 0 -# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN +# define LM_PADEN_SETBITS 0 +# define LM_PADEN_CLRBITS MAC_TCTL_PADEN #else -# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN -# define LM3S_PADEN_CLRBITS 0 +# define LM_PADEN_SETBITS MAC_TCTL_PADEN +# define LM_PADEN_CLRBITS 0 #endif -#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) -#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) +#define LM_TCTCL_SETBITS (LM_DUPLEX_SETBITS|LM_CRC_SETBITS|LM_PADEN_SETBITS) +#define LM_TCTCL_CLRBITS (LM_DUPLEX_CLRBITS|LM_CRC_CLRBITS|LM_PADEN_CLRBITS) /* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */ #ifdef CONFIG_LM_MULTICAST -# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL -# define LM3S_AMUL_CLRBITS 0 +# define LM_AMUL_SETBITS MAC_RCTL_AMUL +# define LM_AMUL_CLRBITS 0 #else -# define LM3S_AMUL_SETBITS 0 -# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL +# define LM_AMUL_SETBITS 0 +# define LM_AMUL_CLRBITS MAC_RCTL_AMUL #endif /* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */ #ifdef CONFIG_LM_PROMISCUOUS -# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS -# define LM3S_PRMS_CLRBITS 0 +# define LM_PRMS_SETBITS MAC_RCTL_PRMS +# define LM_PRMS_CLRBITS 0 #else -# define LM3S_PRMS_SETBITS 0 -# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS +# define LM_PRMS_SETBITS 0 +# define LM_PRMS_CLRBITS MAC_RCTL_PRMS #endif /* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */ #ifdef CONFIG_LM_BADCRC -# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC -# define LM3S_BADCRC_CLRBITS 0 +# define LM_BADCRC_SETBITS MAC_RCTL_BADCRC +# define LM_BADCRC_CLRBITS 0 #else -# define LM3S_BADCRC_SETBITS 0 -# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC +# define LM_BADCRC_SETBITS 0 +# define LM_BADCRC_CLRBITS MAC_RCTL_BADCRC #endif -#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) -#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) +#define LM_RCTCL_SETBITS (LM_AMUL_SETBITS|LM_PRMS_SETBITS|LM_BADCRC_SETBITS) +#define LM_RCTCL_CLRBITS (LM_AMUL_CLRBITS|LM_PRMS_CLRBITS|LM_BADCRC_CLRBITS) /* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */ @@ -142,12 +142,12 @@ /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ -#define LM3S_WDDELAY (1*CLK_TCK) -#define LM3S_POLLHSEC (1*2) +#define LM_WDDELAY (1*CLK_TCK) +#define LM_POLLHSEC (1*2) /* TX timeout = 1 minute */ -#define LM3S_TXTIMEOUT (60*CLK_TCK) +#define LM_TXTIMEOUT (60*CLK_TCK) /* This is a helper pointer for accessing the contents of the Ethernet header */ @@ -192,7 +192,7 @@ struct lm_driver_s * multiple Ethernet controllers. */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 uint32_t ld_base; /* Ethernet controller base address */ int ld_irq; /* Ethernet controller IRQ */ #endif @@ -214,7 +214,7 @@ struct lm_driver_s * Private Data ****************************************************************************/ -static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; +static struct lm_driver_s g_lm3sdev[LM_NETHCONTROLLERS]; /**************************************************************************** * Private Function Prototypes @@ -222,7 +222,7 @@ static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; /* Miscellaneous low level helpers */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 static uint32_t lm_ethin(struct lm_driver_s *priv, int offset); static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value); #else @@ -280,7 +280,7 @@ static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); * ****************************************************************************/ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 static uint32_t lm_ethin(struct lm_driver_s *priv, int offset) { return getreg32(priv->ld_base + offset); @@ -288,7 +288,7 @@ static uint32_t lm_ethin(struct lm_driver_s *priv, int offset) #else static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset) { - return getreg32(LM3S_ETHCON_BASE + offset); + return getreg32(LM_ETHCON_BASE + offset); } #endif @@ -308,7 +308,7 @@ static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset) * ****************************************************************************/ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value) { putreg32(value, priv->ld_base + offset); @@ -316,7 +316,7 @@ static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value) #else static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value) { - putreg32(value, LM3S_ETHCON_BASE + offset); + putreg32(value, LM_ETHCON_BASE + offset); } #endif @@ -341,23 +341,23 @@ static void lm_ethreset(struct lm_driver_s *priv) irqstate_t flags; uint32_t regval; -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 # error "If multiple interfaces are supported, this function would have to be redesigned" #endif /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ flags = irqsave(); - regval = getreg32(LM3S_SYSCON_RCGC2); + regval = getreg32(LM_SYSCON_RCGC2); regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); - putreg32(regval, LM3S_SYSCON_RCGC2); + putreg32(regval, LM_SYSCON_RCGC2); nllvdbg("RCGC2: %08x\n", regval); /* Put the Ethernet controller into the reset state */ - regval = getreg32(LM3S_SYSCON_SRCR2); + regval = getreg32(LM_SYSCON_SRCR2); regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); + putreg32(regval, LM_SYSCON_SRCR2); /* Wait just a bit. This is a much longer delay than necessary */ @@ -366,7 +366,7 @@ static void lm_ethreset(struct lm_driver_s *priv) /* Then take the Ethernet controller out of the reset state */ regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); - putreg32(regval, LM3S_SYSCON_SRCR2); + putreg32(regval, LM_SYSCON_SRCR2); nllvdbg("SRCR2: %08x\n", regval); /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ @@ -384,14 +384,14 @@ static void lm_ethreset(struct lm_driver_s *priv) /* Disable all Ethernet controller interrupts */ - regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval = lm_ethin(priv, LM_MAC_IM_OFFSET); regval &= ~MAC_IM_ALLINTS; - lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + lm_ethout(priv, LM_MAC_IM_OFFSET, regval); /* Clear any pending interrupts (shouldn't be any) */ - regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + regval = lm_ethin(priv, LM_MAC_RIS_OFFSET); + lm_ethout(priv, LM_MAC_IACK_OFFSET, regval); irqrestore(flags); } @@ -416,22 +416,22 @@ static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value) { /* Wait for any MII transactions in progress to complete */ - while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); /* Set up the data to be written */ DEBUGASSERT(value < MAC_MTXD_MASK); - lm_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); + lm_ethout(priv, LM_MAC_MTXD_OFFSET, value); /* Set up the PHY register address and start the write operation */ regaddr <<= MAC_MCTL_REGADR_SHIFT; DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); + lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); /* Wait for the write transaction to complete */ - while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); } #endif @@ -455,21 +455,21 @@ static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr) { /* Wait for any MII transactions in progress to complete */ - while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); /* Set up the PHY register address and start the read operation */ regaddr <<= MAC_MCTL_REGADR_SHIFT; DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); - lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); + lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); /* Wait for the write transaction to complete */ - while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); /* Read and return the PHY data */ - return (uint16_t)(lm_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); + return (uint16_t)(lm_ethin(priv, LM_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); } /**************************************************************************** @@ -499,7 +499,7 @@ static int lm_transmit(struct lm_driver_s *priv) /* Verify that the hardware is ready to send another packet */ flags = irqsave(); - if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* Increment statistics */ @@ -520,7 +520,7 @@ static int lm_transmit(struct lm_driver_s *priv) regval = (uint32_t)(pktlen - 14); regval |= ((uint32_t)(*dbuf++) << 16); regval |= ((uint32_t)(*dbuf++) << 24); - lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + lm_ethout(priv, LM_MAC_DATA_OFFSET, regval); /* Write all of the whole, 32-bit values in the middle of the packet */ @@ -530,7 +530,7 @@ static int lm_transmit(struct lm_driver_s *priv) * buffer may be un-aligned. */ - lm_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); + lm_ethout(priv, LM_MAC_DATA_OFFSET, *(uint32_t*)dbuf); } /* Write the last, partial word in the FIFO */ @@ -554,16 +554,16 @@ static int lm_transmit(struct lm_driver_s *priv) regval |= (uint32_t)dbuf[0]; break; } - lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + lm_ethout(priv, LM_MAC_DATA_OFFSET, regval); } /* Activate the transmitter */ - lm_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); + lm_ethout(priv, LM_MAC_TR_OFFSET, MAC_TR_NEWTX); /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv); + (void)wd_start(priv->ld_txtimeout, LM_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv); ret = OK; } @@ -608,7 +608,7 @@ static int lm_uiptxpoll(struct uip_driver_s *dev) * packet was successfully handled. */ - DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) uip_arp_out(&priv->ld_dev); ret = lm_transmit(priv); } @@ -645,7 +645,7 @@ static void lm_receive(struct lm_driver_s *priv) /* Loop while there are incoming packets to be processed */ - while ((lm_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) + while ((lm_ethin(priv, LM_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) { /* Update statistics */ @@ -665,7 +665,7 @@ static void lm_receive(struct lm_driver_s *priv) * includes the len/type field (size 2) and the FCS (size 4). */ - regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + regval = lm_ethin(priv, LM_MAC_DATA_OFFSET); pktlen = (int)(regval & 0x0000ffff); nllvdbg("Receiving packet, pktlen: %d\n", pktlen); @@ -694,7 +694,7 @@ static void lm_receive(struct lm_driver_s *priv) while (wordlen--) { - (void)lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + (void)lm_ethin(priv, LM_MAC_DATA_OFFSET); } /* Check for another packet */ @@ -718,7 +718,7 @@ static void lm_receive(struct lm_driver_s *priv) * buffer may be un-aligned. */ - *(uint32_t*)dbuf = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + *(uint32_t*)dbuf = lm_ethin(priv, LM_MAC_DATA_OFFSET); } /* Handle the last, partial word in the FIFO (0-3 bytes) and discard @@ -731,7 +731,7 @@ static void lm_receive(struct lm_driver_s *priv) * bytes of the FCS into the user buffer. */ - regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET); + regval = lm_ethin(priv, LM_MAC_DATA_OFFSET); switch (bytesleft) { default: @@ -834,7 +834,7 @@ static void lm_txdone(struct lm_driver_s *priv) * at this point. */ - DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) /* Then poll uIP for new XMIT data */ @@ -863,7 +863,7 @@ static int lm_interrupt(int irq, FAR void *context) register struct lm_driver_s *priv; uint32_t ris; -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 # error "A mechanism to associate and interface with an IRQ is needed" #else priv = &g_lm3sdev[0]; @@ -871,11 +871,11 @@ static int lm_interrupt(int irq, FAR void *context) /* Read the raw interrupt status register */ - ris = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); + ris = lm_ethin(priv, LM_MAC_RIS_OFFSET); /* Clear all pending interrupts */ - lm_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); + lm_ethout(priv, LM_MAC_IACK_OFFSET, ris); /* Check for errors */ @@ -898,7 +898,7 @@ static int lm_interrupt(int irq, FAR void *context) /* Handle (unmasked) interrupts according to status bit settings */ - ris &= lm_ethin(priv, LM3S_MAC_IM_OFFSET); + ris &= lm_ethin(priv, LM_MAC_IM_OFFSET); /* Is this an Rx interrupt (meaning that a packet has been received)? */ @@ -994,15 +994,15 @@ static void lm_polltimer(int argc, uint32_t arg, ...) * inaccuracies. */ - if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* If so, update TCP timing states and poll uIP for new XMIT data */ - (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM3S_POLLHSEC); + (void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM_POLLHSEC); /* Setup the watchdog poll timer again */ - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, arg); + (void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, arg); } } @@ -1051,7 +1051,7 @@ static int lm_ifup(struct uip_driver_s *dev) */ div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; - lm_ethout(priv, LM3S_MAC_MDV_OFFSET, div); + lm_ethout(priv, LM_MAC_MDV_OFFSET, div); nllvdbg("MDV: %08x\n", div); /* Then configure the Ethernet Controller for normal operation @@ -1060,32 +1060,32 @@ static int lm_ifup(struct uip_driver_s *dev) * TX Padding Enabled). */ - regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET); - regval &= ~LM3S_TCTCL_CLRBITS; - regval |= LM3S_TCTCL_SETBITS; - lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + regval = lm_ethin(priv, LM_MAC_TCTL_OFFSET); + regval &= ~LM_TCTCL_CLRBITS; + regval |= LM_TCTCL_SETBITS; + lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval); nllvdbg("TCTL: %08x\n", regval); /* Setup the receive control register (Disable multicast frames, disable * promiscuous mode, disable bad CRC rejection). */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); - regval &= ~LM3S_RCTCL_CLRBITS; - regval |= LM3S_RCTCL_SETBITS; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); + regval &= ~LM_RCTCL_CLRBITS; + regval |= LM_RCTCL_SETBITS; + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); nllvdbg("RCTL: %08x\n", regval); /* Setup the time stamp configuration register */ -#ifdef LM3S_ETHTS - regval = lm_ethin(priv, LM3S_MAC_TS_OFFSET); +#ifdef LM_ETHTS + regval = lm_ethin(priv, LM_MAC_TS_OFFSET); #ifdef CONFIG_LM_TIMESTAMP regval |= MAC_TS_EN; #else regval &= ~(MAC_TS_EN); #endif - lm_ethout(priv, LM3S_MAC_TS_OFFSET, regval); + lm_ethout(priv, LM_MAC_TS_OFFSET, regval); nllvdbg("TS: %08x\n", regval); #endif @@ -1105,41 +1105,41 @@ static int lm_ifup(struct uip_driver_s *dev) /* Reset the receive FIFO */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval |= MAC_RCTL_RSTFIFO; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Enable the Ethernet receiver */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval |= MAC_RCTL_RXEN; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Enable the Ethernet transmitter */ - regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_TCTL_OFFSET); regval |= MAC_TCTL_TXEN; - lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval); /* Reset the receive FIFO (again) */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval |= MAC_RCTL_RSTFIFO; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Enable the Ethernet interrupt */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 up_enable_irq(priv->irq); #else - up_enable_irq(LM3S_IRQ_ETHCON); + up_enable_irq(LM_IRQ_ETHCON); #endif /* Enable the Ethernet RX packet receipt interrupt */ - regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval = lm_ethin(priv, LM_MAC_IM_OFFSET); regval |= MAC_IM_RXINTM; - lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + lm_ethout(priv, LM_MAC_IM_OFFSET, regval); /* Program the hardware with it's MAC address (for filtering) */ @@ -1147,15 +1147,15 @@ static int lm_ifup(struct uip_driver_s *dev) (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; - lm_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); + lm_ethout(priv, LM_MAC_IA0_OFFSET, regval); regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; - lm_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); + lm_ethout(priv, LM_MAC_IA1_OFFSET, regval); /* Set and activate a timer process */ - (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, (uint32_t)priv); + (void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, (uint32_t)priv); priv->ld_bifup = true; irqrestore(flags); @@ -1197,46 +1197,46 @@ static int lm_ifdown(struct uip_driver_s *dev) /* Disable the Ethernet interrupt */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 up_disable_irq(priv->irq); #else - up_disable_irq(LM3S_IRQ_ETHCON); + up_disable_irq(LM_IRQ_ETHCON); #endif /* Disable all Ethernet controller interrupt sources */ - regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET); + regval = lm_ethin(priv, LM_MAC_IM_OFFSET); regval &= ~MAC_IM_ALLINTS; - lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + lm_ethout(priv, LM_MAC_IM_OFFSET, regval); /* Reset the receive FIFO */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval |= MAC_RCTL_RSTFIFO; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Disable the Ethernet receiver */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval &= ~MAC_RCTL_RXEN; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Disable the Ethernet transmitter */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval &= ~MAC_TCTL_TXEN; - lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval); /* Reset the receive FIFO (again) */ - regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET); regval |= MAC_RCTL_RSTFIFO; - lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval); /* Clear any pending interrupts */ - regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET); - lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + regval = lm_ethin(priv, LM_MAC_RIS_OFFSET); + lm_ethout(priv, LM_MAC_IACK_OFFSET, regval); /* The interface is now DOWN */ @@ -1278,7 +1278,7 @@ static int lm_txavail(struct uip_driver_s *dev) */ flags = irqsave(); - if (priv->ld_bifup && (lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + if (priv->ld_bifup && (lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* If the interface is up and we can use the Tx FIFO, then poll uIP * for new Tx data @@ -1371,7 +1371,7 @@ static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) * ****************************************************************************/ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 int lm_ethinitialize(int intf) #else static inline int lm_ethinitialize(int intf) @@ -1384,12 +1384,12 @@ static inline int lm_ethinitialize(int intf) ndbg("Setting up eth%d\n", intf); -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 # error "This debug check only works with one interface" #else - DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); + DEBUGASSERT((getreg32(LM_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); #endif - DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); + DEBUGASSERT((unsigned)intf < LM_NETHCONTROLLERS); /* Initialize the driver structure */ @@ -1405,7 +1405,7 @@ static inline int lm_ethinitialize(int intf) /* Create a watchdog for timing polling for and timing of transmisstions */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" priv->ld_base = ??; /* Ethernet controller base address */ priv->ld_irq = ??; /* Ethernet controller IRQ number */ @@ -1432,10 +1432,10 @@ static inline int lm_ethinitialize(int intf) /* Attach the IRQ to the driver */ -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 ret = irq_attach(priv->irq, lm_interrupt); #else - ret = irq_attach(LM3S_IRQ_ETHCON, lm_interrupt); + ret = irq_attach(LM_IRQ_ETHCON, lm_interrupt); #endif if (ret != 0) { @@ -1461,7 +1461,7 @@ static inline int lm_ethinitialize(int intf) * ************************************************************************************/ -#if LM3S_NETHCONTROLLERS == 1 +#if LM_NETHCONTROLLERS == 1 void up_netinitialize(void) { (void)lm_ethinitialize(0); diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h index e71e9d077..e3cc65067 100644 --- a/nuttx/arch/arm/src/lm/lm_ethernet.h +++ b/nuttx/arch/arm/src/lm/lm_ethernet.h @@ -44,7 +44,7 @@ #include "chip.h" -#if LM3S_NETHCONTROLLERS > 1 +#if LM_NETHCONTROLLERS > 1 /************************************************************************************ * Pre-processor Definitions @@ -77,7 +77,7 @@ extern "C" * Function: lm_ethinitialize * * Description: - * Initialize the Ethernet driver for one interface. If the LM3S chip + * Initialize the Ethernet driver for one interface. If the Stellaris chip * supports multiple Ethernet controllers, then bould specific logic * must implement up_netinitialize() and call this function to initialize * the desiresed interfaces. @@ -99,5 +99,5 @@ int lm_ethinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* LM3S_NETHCONTROLLERS > 1 */ +#endif /* LM_NETHCONTROLLERS > 1 */ #endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/lm_gpio.c b/nuttx/arch/arm/src/lm/lm_gpio.c index 499bf07a2..be851e67c 100644 --- a/nuttx/arch/arm/src/lm/lm_gpio.c +++ b/nuttx/arch/arm/src/lm/lm_gpio.c @@ -140,23 +140,23 @@ static const struct gpio_func_s g_funcbits[] = {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ }; -static const uint32_t g_gpiobase[LM3S_NPORTS] = +static const uint32_t g_gpiobase[LM_NPORTS] = { - /* All support LM3S parts have at least 7 ports, GPIOA-G */ + /* All support Stellaris parts have at least 7 ports, GPIOA-G */ - LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, - LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, + LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE, + LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ -#if LM3S_NPORTS > 7 - LM3S_GPIOH_BASE, +#if LM_NPORTS > 7 + LM_GPIOH_BASE, #endif /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ -#if LM3S_NPORTS > 8 - LM3S_GPIOJ_BASE, +#if LM_NPORTS > 8 + LM_GPIOJ_BASE, #endif }; @@ -180,7 +180,7 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] = static uint32_t lm_gpiobaseaddress(unsigned int port) { uint32_t gpiobase = 0; - if (port < LM3S_NPORTS) + if (port < LM_NPORTS) { gpiobase = g_gpiobase[port]; } @@ -215,10 +215,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval = getreg32(base + LM_GPIO_ODR_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); + putreg32(regval, base + LM_GPIO_ODR_OFFSET); /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control * register. When a bit is set to 1, it enables a weak pull-up resistor on the @@ -231,10 +231,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s if (setbit || clrbit) { - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval = getreg32(base + LM_GPIO_PUR_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + putreg32(regval, base + LM_GPIO_PUR_OFFSET); } /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control @@ -248,10 +248,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s if (setbit || clrbit) { - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval = getreg32(base + LM_GPIO_PDR_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + putreg32(regval, base + LM_GPIO_PDR_OFFSET); } /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable @@ -266,10 +266,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval = getreg32(base + LM_GPIO_DEN_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); + putreg32(regval, base + LM_GPIO_DEN_OFFSET); /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data * direction register. Bits set to 1 in the GPIODIR register configure @@ -281,10 +281,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; - regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); + regval = getreg32(base + LM_GPIO_DIR_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); + putreg32(regval, base + LM_GPIO_DIR_OFFSET); /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode * control select register. Writing a 1 to any bit in this register selects @@ -298,10 +298,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; - regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); + regval = getreg32(base + LM_GPIO_AFSEL_OFFSET); regval &= ~clrbit; regval |= setbit; - putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); + putreg32(regval, base + LM_GPIO_AFSEL_OFFSET); } /**************************************************************************** @@ -336,7 +336,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." */ - regoffset = LM3S_GPIO_DR2R_OFFSET; + regoffset = LM_GPIO_DR2R_OFFSET; } break; @@ -349,7 +349,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs * in the GPIO DR8R register are automatically cleared by hardware." */ - regoffset = LM3S_GPIO_DR4R_OFFSET; + regoffset = LM_GPIO_DR4R_OFFSET; } break; @@ -374,7 +374,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." */ - regoffset = LM3S_GPIO_DR8R_OFFSET; + regoffset = LM_GPIO_DR8R_OFFSET; } break; } @@ -385,10 +385,10 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs regval |= pin; putreg32(regval, base + regoffset); - regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); + regval = getreg32(base + LM_GPIO_SLR_OFFSET); regval &= slrclr; regval |= slrset; - putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); + putreg32(regval, base + LM_GPIO_SLR_OFFSET); } /**************************************************************************** @@ -503,10 +503,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) */ #if 0 /* always overwritten by lm_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval = getreg32(base + LM_GPIO_ODR_OFFSET); regval &= ~odrclr; regval |= odrset; - putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); + putreg32(regval, base + LM_GPIO_ODR_OFFSET); #endif /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control @@ -515,10 +515,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." */ - regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval = getreg32(base + LM_GPIO_PUR_OFFSET); regval &= ~purclr; regval |= purset; - putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + putreg32(regval, base + LM_GPIO_PUR_OFFSET); /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control * register. When a bit is set to 1, it enables a weak pull-down resistor on the @@ -526,10 +526,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." */ - regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval = getreg32(base + LM_GPIO_PDR_OFFSET); regval &= ~pdrclr; regval |= pdrset; - putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + putreg32(regval, base + LM_GPIO_PDR_OFFSET); /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable * register. By default, with the exception of the GPIO signals used for JTAG/SWD @@ -541,10 +541,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) */ #if 0 /* always overwritten by lm_gpiofunc */ - regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval = getreg32(base + LM_GPIO_DEN_OFFSET); regval &= ~denclr; regval |= denset; - putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); + putreg32(regval, base + LM_GPIO_DEN_OFFSET); #endif } @@ -589,18 +589,18 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) * on that pin. All bits are cleared by a reset." */ - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval = getreg32(base + LM_GPIO_IM_OFFSET); regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + putreg32(regval, base + LM_GPIO_IM_OFFSET); /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit * in this register clears the corresponding interrupt edge detection logic * register. Writing a 0 has no effect." */ - regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); + regval = getreg32(base + LM_GPIO_ICR_OFFSET); regval |= pin; - putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); + putreg32(regval, base + LM_GPIO_ICR_OFFSET); /* Assume rising edge */ @@ -656,10 +656,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) * by a reset. */ - regval = getreg32(base + LM3S_GPIO_IS_OFFSET); + regval = getreg32(base + LM_GPIO_IS_OFFSET); regval &= isclr; regval |= isset; - putreg32(regval, base + LM3S_GPIO_IS_OFFSET); + putreg32(regval, base + LM_GPIO_IS_OFFSET); /* "The GPIO IBE register is the interrupt both-edges register. When the * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is @@ -670,10 +670,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) * are cleared by a reset. */ - regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); + regval = getreg32(base + LM_GPIO_IBE_OFFSET); regval &= ibeclr; regval |= ibeset; - putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); + putreg32(regval, base + LM_GPIO_IBE_OFFSET); /* "The GPIOIEV register is the interrupt event register. Bits set to * High in GPIO IEV configure the corresponding pin to detect rising edges @@ -683,10 +683,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) * value in GPIOIS. All bits are cleared by a reset. */ - regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); + regval = getreg32(base + LM_GPIO_IEV_OFFSET); regval &= iveclr; regval |= iveset; - putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); + putreg32(regval, base + LM_GPIO_IEV_OFFSET); } /**************************************************************************** @@ -734,9 +734,9 @@ int lm_configgpio(uint32_t cfgset) * in the RCGC2 register." */ - regval = getreg32(LM3S_SYSCON_RCGC2); + regval = getreg32(LM_SYSCON_RCGC2); regval |= SYSCON_RCGC2_GPIO(port); - putreg32(regval, LM3S_SYSCON_RCGC2); + putreg32(regval, LM_SYSCON_RCGC2); /* First, set the port to digital input. This is the safest state in which * to perform reconfiguration. @@ -810,7 +810,7 @@ void lm_gpiowrite(uint32_t pinset, bool value) * "... All bits are cleared by a reset." */ - putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); + putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))); } /**************************************************************************** @@ -849,6 +849,6 @@ bool lm_gpioread(uint32_t pinset, bool value) * are cleared by a reset." */ - return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); + return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); } diff --git a/nuttx/arch/arm/src/lm/lm_gpioirq.c b/nuttx/arch/arm/src/lm/lm_gpioirq.c index f77f878de..e8423f4c0 100644 --- a/nuttx/arch/arm/src/lm/lm_gpioirq.c +++ b/nuttx/arch/arm/src/lm/lm_gpioirq.c @@ -73,38 +73,38 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; static const uint32_t g_gpiobase[] = { #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS - LM3S_GPIOA_BASE, + LM_GPIOA_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS - LM3S_GPIOB_BASE, + LM_GPIOB_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS - LM3S_GPIOC_BASE, + LM_GPIOC_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS - LM3S_GPIOD_BASE, + LM_GPIOD_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS - LM3S_GPIOE_BASE, + LM_GPIOE_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS - LM3S_GPIOF_BASE, + LM_GPIOF_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS - LM3S_GPIOG_BASE, + LM_GPIOG_BASE, #endif - /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip - * does not support these higher ports, then they must be disabled in the - * configuration. Otherwise, the following will likely cause compilation + /* NOTE: Not all Stellaris architectures support GPIOs above GPIOG. If the + * chip does not support these higher ports, then they must be disabled in + * the configuration. Otherwise, the following will likely cause compilation * errors! */ #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS - LM3S_GPIOH_BASE, + LM_GPIOH_BASE, #endif #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS - LM3S_GPIOJ_BASE, + LM_GPIOJ_BASE, #endif }; @@ -161,7 +161,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context) * either no interrupt has been generated, or the interrupt is masked." */ - mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; + mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff; /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR * register is the interrupt clear register. Writing a 1 to a bit in this @@ -169,7 +169,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context) * Writing a 0 has no effect." */ - putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); + putreg32(mis, regbase + LM_GPIO_ICR_OFFSET); /* Now process each IRQ pending in the MIS */ @@ -187,63 +187,63 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context) #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS static int lm_gpioahandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); + return lm_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS static int lm_gpiobhandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); + return lm_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS static int lm_gpiochandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); + return lm_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS static int lm_gpiodhandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); + return lm_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS static int lm_gpioehandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); + return lm_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS static int lm_gpiofhandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); + return lm_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS static int lm_gpioghandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); + return lm_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS static int lm_gpiohhandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); + return lm_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context); } #endif #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS static int lm_gpiojhandler(int irq, FAR void *context) { - return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); + return lm_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context); } #endif @@ -275,40 +275,40 @@ int gpio_irqinitialize(void) */ #ifndef CONFIG_LM_DISABLE_GPIOA_IRQS - irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler); - up_enable_irq(LM3S_IRQ_GPIOA); + irq_attach(LM_IRQ_GPIOA, lm_gpioahandler); + up_enable_irq(LM_IRQ_GPIOA); #endif #ifndef CONFIG_LM_DISABLE_GPIOB_IRQS - irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler); - up_enable_irq(LM3S_IRQ_GPIOB); + irq_attach(LM_IRQ_GPIOB, lm_gpiobhandler); + up_enable_irq(LM_IRQ_GPIOB); #endif #ifndef CONFIG_LM_DISABLE_GPIOC_IRQS - irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler); - up_enable_irq(LM3S_IRQ_GPIOC); + irq_attach(LM_IRQ_GPIOC, lm_gpiochandler); + up_enable_irq(LM_IRQ_GPIOC); #endif #ifndef CONFIG_LM_DISABLE_GPIOD_IRQS - irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler); - up_enable_irq(LM3S_IRQ_GPIOD); + irq_attach(LM_IRQ_GPIOD, lm_gpiodhandler); + up_enable_irq(LM_IRQ_GPIOD); #endif #ifndef CONFIG_LM_DISABLE_GPIOE_IRQS - irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler); - up_enable_irq(LM3S_IRQ_GPIOE); + irq_attach(LM_IRQ_GPIOE, lm_gpioehandler); + up_enable_irq(LM_IRQ_GPIOE); #endif #ifndef CONFIG_LM_DISABLE_GPIOF_IRQS - irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler); - up_enable_irq(LM3S_IRQ_GPIOF); + irq_attach(LM_IRQ_GPIOF, lm_gpiofhandler); + up_enable_irq(LM_IRQ_GPIOF); #endif #ifndef CONFIG_LM_DISABLE_GPIOG_IRQS - irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler); - up_enable_irq(LM3S_IRQ_GPIOG); + irq_attach(LM_IRQ_GPIOG, lm_gpioghandler); + up_enable_irq(LM_IRQ_GPIOG); #endif #ifndef CONFIG_LM_DISABLE_GPIOH_IRQS - irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler); - up_enable_irq(LM3S_IRQ_GPIOH); + irq_attach(LM_IRQ_GPIOH, lm_gpiohhandler); + up_enable_irq(LM_IRQ_GPIOH); #endif #ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS - irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler); - up_enable_irq(LM3S_IRQ_GPIOJ); + irq_attach(LM_IRQ_GPIOJ, lm_gpiojhandler); + up_enable_irq(LM_IRQ_GPIOJ); #endif return OK; @@ -386,9 +386,9 @@ void gpio_irqenable(int irq) */ flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval = getreg32(base + LM_GPIO_IM_OFFSET); regval |= pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + putreg32(regval, base + LM_GPIO_IM_OFFSET); irqrestore(flags); } } @@ -425,10 +425,9 @@ void gpio_irqdisable(int irq) */ flags = irqsave(); - regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval = getreg32(base + LM_GPIO_IM_OFFSET); regval &= ~pin; - putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + putreg32(regval, base + LM_GPIO_IM_OFFSET); irqrestore(flags); } } - diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index 700944202..fa8e271bc 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -63,7 +63,7 @@ * bringup */ -#undef LM3S_IRQ_DEBUG +#undef LM_IRQ_DEBUG /* Get a 32-bit version of the default priority */ @@ -95,7 +95,7 @@ volatile uint32_t *current_regs; * ****************************************************************************/ -#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +#if defined(LM_IRQ_DEBUG) && defined (CONFIG_DEBUG) static void lm_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -201,21 +201,21 @@ static int lm_reserved(int irq, FAR void *context) static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) { - DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= LM3S_IRQ_INTERRUPTS) + if (irq >= LM_IRQ_INTERRUPTS) { - if (irq < LM3S_IRQ_INTERRUPTS + 32) + if (irq < LM_IRQ_INTERRUPTS + 32) { *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); + *bit = 1 << (irq - LM_IRQ_INTERRUPTS); } else if (irq < NR_IRQS) { *regaddr = NVIC_IRQ32_63_ENABLE; - *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); + *bit = 1 << (irq - LM_IRQ_INTERRUPTS - 32); } else { @@ -228,19 +228,19 @@ static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) else { *regaddr = NVIC_SYSHCON; - if (irq == LM3S_IRQ_MEMFAULT) + if (irq == LM_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == LM3S_IRQ_BUSFAULT) + else if (irq == LM_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == LM3S_IRQ_USAGEFAULT) + else if (irq == LM_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == LM3S_IRQ_SYSTICK) + else if (irq == LM_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -309,13 +309,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(LM3S_IRQ_SVCALL, up_svcall); - irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); + irq_attach(LM_IRQ_SVCALL, up_svcall); + irq_attach(LM_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO -/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -323,22 +323,22 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); - up_enable_irq(LM3S_IRQ_MEMFAULT); + irq_attach(LM_IRQ_MEMFAULT, up_memfault); + up_enable_irq(LM_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG - irq_attach(LM3S_IRQ_NMI, lm_nmi); + irq_attach(LM_IRQ_NMI, lm_nmi); #ifndef CONFIG_ARMV7M_MPU - irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); + irq_attach(LM_IRQ_MEMFAULT, up_memfault); #endif - irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault); - irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault); - irq_attach(LM3S_IRQ_PENDSV, lm_pendsv); - irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor); - irq_attach(LM3S_IRQ_RESERVED, lm_reserved); + irq_attach(LM_IRQ_BUSFAULT, lm_busfault); + irq_attach(LM_IRQ_USAGEFAULT, lm_usagefault); + irq_attach(LM_IRQ_PENDSV, lm_pendsv); + irq_attach(LM_IRQ_DBGMONITOR, lm_dbgmonitor); + irq_attach(LM_IRQ_RESERVED, lm_reserved); #endif lm_dumpnvic("initial", NR_IRQS); @@ -433,16 +433,16 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < LM3S_IRQ_INTERRUPTS) + if (irq < LM_IRQ_INTERRUPTS) { irq -= 4; regaddr = NVIC_SYSH_PRIORITY(irq); } else { - irq -= LM3S_IRQ_INTERRUPTS; + irq -= LM_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.c b/nuttx/arch/arm/src/lm/lm_lowputc.c index d2c1f5be5..d461cd52e 100644 --- a/nuttx/arch/arm/src/lm/lm_lowputc.c +++ b/nuttx/arch/arm/src/lm/lm_lowputc.c @@ -57,12 +57,12 @@ /* Configuration **********************************************************/ -#if LM3S_NUARTS < 2 +#if LM_NUARTS < 2 # undef CONFIG_LM_UART1 # undef CONFIG_UART1_SERIAL_CONSOLE #endif -#if LM3S_NUARTS < 3 +#if LM_NUARTS < 3 # undef CONFIG_LM_UART2 # undef CONFIG_UART2_SERIAL_CONSOLE #endif @@ -92,52 +92,52 @@ /* Select UART parameters for the selected console */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART0_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP +# define LM_CONSOLE_BASE LM_UART0_BASE +# define LM_CONSOLE_BAUD CONFIG_UART0_BAUD +# define LM_CONSOLE_BITS CONFIG_UART0_BITS +# define LM_CONSOLE_PARITY CONFIG_UART0_PARITY +# define LM_CONSOLE_2STOP CONFIG_UART0_2STOP #elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART1_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP +# define LM_CONSOLE_BASE LM_UART1_BASE +# define LM_CONSOLE_BAUD CONFIG_UART1_BAUD +# define LM_CONSOLE_BITS CONFIG_UART1_BITS +# define LM_CONSOLE_PARITY CONFIG_UART1_PARITY +# define LM_CONSOLE_2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define LM3S_CONSOLE_BASE LM3S_UART2_BASE -# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD -# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS -# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY -# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP +# define LM_CONSOLE_BASE LM_UART2_BASE +# define LM_CONSOLE_BAUD CONFIG_UART2_BAUD +# define LM_CONSOLE_BITS CONFIG_UART2_BITS +# define LM_CONSOLE_PARITY CONFIG_UART2_PARITY +# define LM_CONSOLE_2STOP CONFIG_UART2_2STOP #else # error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" #endif /* Get LCRH settings */ -#if LM3S_CONSOLE_BITS == 5 +#if LM_CONSOLE_BITS == 5 # define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS -#elif LM3S_CONSOLE_BITS == 6 +#elif LM_CONSOLE_BITS == 6 # define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS -#elif LM3S_CONSOLE_BITS == 7 +#elif LM_CONSOLE_BITS == 7 # define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS -#elif LM3S_CONSOLE_BITS == 8 +#elif LM_CONSOLE_BITS == 8 # define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS #else # error "Number of bits not supported" #endif -#if LM3S_CONSOLE_PARITY == 0 +#if LM_CONSOLE_PARITY == 0 # define UART_LCRH_PARITY (0) -#elif LM3S_CONSOLE_PARITY == 1 +#elif LM_CONSOLE_PARITY == 1 # define UART_LCRH_PARITY UART_LCRH_PEN -#elif LM3S_CONSOLE_PARITY == 2 +#elif LM_CONSOLE_PARITY == 2 # define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) #else # error "Invalid parity selection" #endif -#if LM3S_CONSOLE_2STOP != 0 +#if LM_CONSOLE_2STOP != 0 # define UART_LCRH_NSTOP UART_LCRH_STP2 #else # define UART_LCRH_NSTOP (0) @@ -177,17 +177,17 @@ * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." */ -#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) -#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) -#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) -#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) +#define LM_BRDDEN (16 * LM_CONSOLE_BAUD) +#define LM_BRDI (SYSCLK_FREQUENCY / LM_BRDDEN) +#define LM_REMAINDER (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI) +#define LM_DIVFRAC ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN) -/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: +/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: * - * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 - * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 - * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 - * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 + * LM_BRDDEN = (16 * 115,200) = 1,843,200 + * LM_BRDI = 50,000,000 / 1,843,200 = 27 + * LM_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 + * LM_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 * * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 */ @@ -229,11 +229,11 @@ void up_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX FIFO is not full */ - while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); + while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0); /* Then send the character */ - putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); + putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET); #endif } @@ -260,18 +260,18 @@ void up_lowsetup(void) */ #ifdef CONFIG_LM_UART0 - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_UART0; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); lm_configgpio(GPIO_UART0_RX); lm_configgpio(GPIO_UART0_TX); #endif #ifdef CONFIG_LM_UART1 - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_UART1; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); lm_configgpio(GPIO_UART1_RX); lm_configgpio(GPIO_UART1_TX); @@ -282,26 +282,26 @@ void up_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET); ctl &= ~UART_CTL_UARTEN; - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET); /* Write the integer portion of the BRD to the UART IBRD register */ - putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); + putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET); /* Write the fractional portion of the BRD to the UART FBRD register */ - putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); + putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET); /* Write the desired serial parameters to the UART LCRH register */ - putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); + putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET); /* Enable the UART by setting the UARTEN bit in the UART CTL register */ ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET); #endif } diff --git a/nuttx/arch/arm/src/lm/lm_serial.c b/nuttx/arch/arm/src/lm/lm_serial.c index e9f604989..ede47a8ca 100644 --- a/nuttx/arch/arm/src/lm/lm_serial.c +++ b/nuttx/arch/arm/src/lm/lm_serial.c @@ -66,12 +66,12 @@ /* Some sanity checks *******************************************************/ -#if LM3S_NUARTS < 2 +#if LM_NUARTS < 2 # undef CONFIG_LM_UART1 # undef CONFIG_UART1_SERIAL_CONSOLE #endif -#if LM3S_NUARTS < 3 +#if LM_NUARTS < 3 # undef CONFIG_LM_UART2 # undef CONFIG_UART2_SERIAL_CONSOLE #endif @@ -274,14 +274,14 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; #endif -/* This describes the state of the LM3S uart0 port. */ +/* This describes the state of the Stellaris uart0 port. */ #ifdef CONFIG_LM_UART0 static struct up_dev_s g_uart0priv = { - .uartbase = LM3S_UART0_BASE, + .uartbase = LM_UART0_BASE, .baud = CONFIG_UART0_BAUD, - .irq = LM3S_IRQ_UART0, + .irq = LM_IRQ_UART0, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, @@ -304,14 +304,14 @@ static uart_dev_t g_uart0port = }; #endif -/* This describes the state of the LM3S uart1 port. */ +/* This describes the state of the Stellaris uart1 port. */ #ifdef CONFIG_LM_UART1 static struct up_dev_s g_uart1priv = { - .uartbase = LM3S_UART1_BASE, + .uartbase = LM_UART1_BASE, .baud = CONFIG_UART1_BAUD, - .irq = LM3S_IRQ_UART1, + .irq = LM_IRQ_UART1, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, @@ -334,14 +334,14 @@ static uart_dev_t g_uart1port = }; #endif -/* This describes the state of the LM3S uart1 port. */ +/* This describes the state of the Stellaris uart1 port. */ #ifdef CONFIG_LM_UART2 static struct up_dev_s g_uart2priv = { - .uartbase = LM3S_UART2_BASE, + .uartbase = LM_UART2_BASE, .baud = CONFIG_UART2_BAUD, - .irq = LM3S_IRQ_UART2, + .irq = LM_IRQ_UART2, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, @@ -402,7 +402,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) /* Disable all interrupts */ priv->im = 0; - up_serialout(priv, LM3S_UART_IM_OFFSET, 0); + up_serialout(priv, LM_UART_IM_OFFSET, 0); } /**************************************************************************** @@ -412,7 +412,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) { priv->im = im; - up_serialout(priv, LM3S_UART_IM_OFFSET, im); + up_serialout(priv, LM_UART_IM_OFFSET, im); } /**************************************************************************** @@ -430,7 +430,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv) { /* Check Tx FIFO is full */ - if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) + if ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0) { /* The Tx FIFO is not full... return */ @@ -471,9 +471,9 @@ static int up_setup(struct uart_dev_s *dev) /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); + ctl = up_serialin(priv, LM_UART_CTL_OFFSET); ctl &= ~UART_CTL_UARTEN; - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + up_serialout(priv, LM_UART_CTL_OFFSET, ctl); /* Calculate BAUD rate from the SYS clock: * @@ -517,8 +517,8 @@ static int up_setup(struct uart_dev_s *dev) remainder = SYSCLK_FREQUENCY - den * brdi; divfrac = ((remainder << 6) + (den >> 1)) / den; - up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); - up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); + up_serialout(priv, LM_UART_IBRD_OFFSET, brdi); + up_serialout(priv, LM_UART_FBRD_OFFSET, divfrac); /* Set up the LCRH register */ @@ -558,14 +558,14 @@ static int up_setup(struct uart_dev_s *dev) lcrh |= UART_LCRH_STP2; } - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); + up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh); #endif /* Set the UART to interrupt whenever the TX FIFO is almost empty or when * any character is received. */ - up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); + up_serialout(priv, LM_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); /* Flush the Rx and Tx FIFOs -- How do you do that?*/ @@ -575,27 +575,27 @@ static int up_setup(struct uart_dev_s *dev) * yet because the interrupt is still disabled at the interrupt controller. */ - up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); + up_serialout(priv, LM_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); /* Enable the FIFOs */ #ifdef CONFIG_SUPPRESS_UART_CONFIG - lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); + lcrh = up_serialin(priv, LM_UART_LCRH_OFFSET); #endif lcrh |= UART_LCRH_FEN; - up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); + up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh); /* Enable Rx, Tx, and the UART */ #ifdef CONFIG_SUPPRESS_UART_CONFIG - ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); + ctl = up_serialin(priv, LM_UART_CTL_OFFSET); #endif ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); - up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + up_serialout(priv, LM_UART_CTL_OFFSET, ctl); /* Set up the cache IM value */ - priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); + priv->im = up_serialin(priv, LM_UART_IM_OFFSET); return OK; } @@ -716,8 +716,8 @@ static int up_interrupt(int irq, void *context) /* Get the masked UART status and clear the pending interrupts. */ - mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); - up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); + mis = up_serialin(priv, LM_UART_MIS_OFFSET); + up_serialout(priv, LM_UART_ICR_OFFSET, mis); /* Handle incoming, receive bytes (with or without timeout) */ @@ -797,7 +797,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) /* Get the Rx byte + 4 bits of error information. Return those in status */ - rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); + rxd = up_serialin(priv, LM_UART_DR_OFFSET); *status = rxd; /* The lower 8bits of the Rx data is the actual recevied byte */ @@ -830,7 +830,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) { priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); } - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + up_serialout(priv, LM_UART_IM_OFFSET, priv->im); } /**************************************************************************** @@ -844,7 +844,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); + return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_RXFE) == 0); } /**************************************************************************** @@ -858,7 +858,7 @@ static bool up_rxavailable(struct uart_dev_s *dev) static void up_send(struct uart_dev_s *dev, int ch) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); + up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -881,11 +881,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS priv->im |= UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + up_serialout(priv, LM_UART_IM_OFFSET, priv->im); /* The serial driver wants an interrupt here, but will not get get * one unless we "prime the pump." I believe that this is because - * behave like a level interrupt and the LM3S interrupts behave + * behave like a level interrupt and the Stellaris interrupts behave * (at least by default) like edge interrupts. * * In any event, faking a TX interrupt here solves the problem; @@ -901,7 +901,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) /* Disable the TX interrupt */ priv->im &= ~UART_IM_TXIM; - up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + up_serialout(priv, LM_UART_IM_OFFSET, priv->im); } irqrestore(flags); } @@ -917,7 +917,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); + return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0); } /**************************************************************************** @@ -931,7 +931,7 @@ static bool up_txready(struct uart_dev_s *dev) static bool up_txempty(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); + return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFE) != 0); } /**************************************************************************** @@ -1016,7 +1016,7 @@ int up_putc(int ch) up_disableuartint(priv, &im); up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); + up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch); /* Check for LF */ @@ -1025,7 +1025,7 @@ int up_putc(int ch) /* Add CR */ up_waittxnotfull(priv); - up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); + up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)'\r'); } up_waittxnotfull(priv); diff --git a/nuttx/arch/arm/src/lm/lm_ssi.c b/nuttx/arch/arm/src/lm/lm_ssi.c index c6f8dcdb1..dae08e092 100644 --- a/nuttx/arch/arm/src/lm/lm_ssi.c +++ b/nuttx/arch/arm/src/lm/lm_ssi.c @@ -83,12 +83,12 @@ * such case, the following must be expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif @@ -102,15 +102,15 @@ # define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ # else # define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ -# define SSI_BASE LM3S_SSI0_BASE -# define SSI_IRQ LM3S_IRQ_SSI0 +# define SSI_BASE LM_SSI0_BASE +# define SSI_IRQ LM_IRQ_SSI0 # endif #else # ifndef CONFIG_SSI1_DISABLE # define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ # define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ -# define SSI_BASE LM3S_SSI1_BASE -# define SSI_IRQ LM3S_IRQ_SSI1 +# define SSI_BASE LM_SSI1_BASE +# define SSI_IRQ LM_IRQ_SSI1 # else # define NSSI_ENABLED 0 /* No SSI interfaces */ # endif @@ -124,19 +124,19 @@ /* The number of (16-bit) words that will fit in the Tx FIFO */ -#define LM3S_TXFIFO_WORDS 8 +#define LM_TXFIFO_WORDS 8 /* Configuration settings */ #ifndef CONFIG_SSI_TXLIMIT -# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) +# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2) #endif -#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS +#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS # error "Invalid range for CONFIG_SSI_TXLIMIT" #endif -#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) +#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2) # error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" #endif @@ -304,10 +304,10 @@ static struct lm_ssidev_s g_ssidev[] = { .ops = &g_spiops, #if NSSI_ENABLED > 1 - .base = LM3S_SSI0_BASE, + .base = LM_SSI0_BASE, #endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI0, + .irq = LM_IRQ_SSI0, #endif }, #endif @@ -315,10 +315,10 @@ static struct lm_ssidev_s g_ssidev[] = { .ops = &g_spiops, #if NSSI_ENABLED > 1 - .base = LM3S_SSI1_BASE, + .base = LM_SSI1_BASE, #endif #if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 - .irq = LM3S_IRQ_SSI1, + .irq = LM_IRQ_SSI1, #endif }, #endif @@ -404,9 +404,9 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv) uint32_t retval; uint32_t regval; - retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET); regval = (retval & ~SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval); ssivdbg("CR1: %08x\n", regval); return retval; } @@ -430,10 +430,10 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv) static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable) { - uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET); regval &= ~SSI_CR1_SSE; regval |= (enable & SSI_CR1_SSE); - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval); ssivdbg("CR1: %08x\n", regval); } @@ -484,14 +484,14 @@ static void ssi_semtake(sem_t *sem) static void ssi_txnull(struct lm_ssidev_s *priv) { ssivdbg("TX: ->0xffff\n"); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); + ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff); } static void ssi_txuint16(struct lm_ssidev_s *priv) { uint16_t *ptr = (uint16_t*)priv->txbuffer; ssivdbg("TX: %p->%04x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++)); priv->txbuffer = (void*)ptr; } @@ -499,7 +499,7 @@ static void ssi_txuint8(struct lm_ssidev_s *priv) { uint8_t *ptr = (uint8_t*)priv->txbuffer; ssivdbg("TX: %p->%02x\n", ptr, *ptr); - ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++)); priv->txbuffer = (void*)ptr; } @@ -523,17 +523,17 @@ static void ssi_txuint8(struct lm_ssidev_s *priv) static void ssi_rxnull(struct lm_ssidev_s *priv) { #if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) - uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: discard %04x\n", regval); #else - (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + (void)ssi_getreg(priv, LM_SSI_DR_OFFSET); #endif } static void ssi_rxuint16(struct lm_ssidev_s *priv) { uint16_t *ptr = (uint16_t*)priv->rxbuffer; - *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + *ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: %p<-%04x\n", ptr, *ptr); priv->rxbuffer = (void*)(++ptr); } @@ -541,7 +541,7 @@ static void ssi_rxuint16(struct lm_ssidev_s *priv) static void ssi_rxuint8(struct lm_ssidev_s *priv) { uint8_t *ptr = (uint8_t*)priv->rxbuffer; - *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + *ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET); ssivdbg("RX: %p<-%02x\n", ptr, *ptr); priv->rxbuffer = (void*)(++ptr); } @@ -562,7 +562,7 @@ static void ssi_rxuint8(struct lm_ssidev_s *priv) static inline bool ssi_txfifofull(struct lm_ssidev_s *priv) { - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; + return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; } /**************************************************************************** @@ -581,7 +581,7 @@ static inline bool ssi_txfifofull(struct lm_ssidev_s *priv) static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv) { - return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; + return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; } /**************************************************************************** @@ -657,7 +657,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv) /* Check again... Now have all of the Tx words been sent? */ #ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + regval = ssi_getreg(priv, LM_SSI_IM_OFFSET); if (priv->ntxwords > 0) { /* No.. Enable the Tx FIFO interrupt. This interrupt occurs @@ -678,7 +678,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv) regval &= ~(SSI_IM_TX|SSI_RIS_ROR); } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); + ssi_putreg(priv, LM_SSI_IM_OFFSET, regval); #endif /* CONFIG_SSI_POLLWAIT */ } return ntxd; @@ -728,7 +728,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv) */ #ifndef CONFIG_SSI_POLLWAIT - regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + regval = ssi_getreg(priv, LM_SSI_IM_OFFSET); if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) { /* There are no more outgoing words to send, but there are @@ -751,7 +751,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv) regval &= ~(SSI_IM_RX|SSI_IM_RT); } - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); + ssi_putreg(priv, LM_SSI_IM_OFFSET, regval); #endif /* CONFIG_SSI_POLLWAIT */ } @@ -829,7 +829,7 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, flags = irqsave(); ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET)); ntxd = ssi_performtx(priv); @@ -842,8 +842,8 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer, ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET), + ssi_getreg(priv, LM_SSI_IM_OFFSET)); /* Wait for the transfer to complete. Since there is no handshake * with SPI, the following should complete even if there are problems @@ -908,11 +908,11 @@ static inline struct lm_ssidev_s *ssi_mapirq(int irq) switch (irq) { #ifndef CONFIG_SSI0_DISABLE - case LM3S_IRQ_SSI0: + case LM_IRQ_SSI0: return &g_ssidev[SSI0_NDX]; #endif #ifndef CONFIG_SSI1_DISABLE - case LM3S_IRQ_SSI1: + case LM_IRQ_SSI1: return &g_ssidev[SSI1_NDX]; #endif default: @@ -952,8 +952,8 @@ static int ssi_interrupt(int irq, void *context) /* Clear pending interrupts */ - regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); - ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); + regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET); + ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval); /* Check for Rx FIFO overruns */ @@ -966,7 +966,7 @@ static int ssi_interrupt(int irq, void *context) ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET)); /* Handle outgoing Tx FIFO transfers */ @@ -978,8 +978,8 @@ static int ssi_interrupt(int irq, void *context) ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", priv->ntxwords, priv->nrxwords, priv->nwords, - ssi_getreg(priv, LM3S_SSI_SR_OFFSET), - ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + ssi_getreg(priv, LM_SSI_SR_OFFSET), + ssi_getreg(priv, LM_SSI_IM_OFFSET)); /* Check if the transfer is complete */ @@ -987,7 +987,7 @@ static int ssi_interrupt(int irq, void *context) { /* Yes.. Disable all SSI interrupt sources */ - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + ssi_putreg(priv, LM_SSI_IM_OFFSET, 0); /* Wake up the waiting thread */ @@ -1135,14 +1135,14 @@ static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t freq /* Set CPDVSR */ DEBUGASSERT(cpsdvsr < 255); - ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); + ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr); /* Set SCR */ - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~SSI_CR0_SCR_MASK; regval |= (scr << SSI_CR0_SCR_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); /* Calcluate the actual frequency */ @@ -1235,10 +1235,10 @@ static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode) /* Then set the selected mode: Freescale SPI format, mode0-3 */ - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); regval |= modebits; - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x\n", regval); /* Save the mode so that subsequent re-configuratins will be faster */ @@ -1287,10 +1287,10 @@ static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits) DEBUGASSERT(priv); if (nbits != priv->nbits && nbits >=4 && nbits <= 16) { - regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET); regval &= ~SSI_CR0_DSS_MASK; regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval); ssivdbg("CR0: %08x\n", regval); priv->nbits = nbits; @@ -1464,9 +1464,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Enable the SSI0 peripheral */ - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_SSI0; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); ssivdbg("RCGC1: %08x\n", regval); /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the @@ -1488,9 +1488,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Enable the SSI1 peripheral */ - regval = getreg32(LM3S_SYSCON_RCGC1); + regval = getreg32(LM_SYSCON_RCGC1); regval |= SYSCON_RCGC1_SSI1; - putreg32(regval, LM3S_SYSCON_RCGC1); + putreg32(regval, LM_SYSCON_RCGC1); ssivdbg("RCGC1: %08x\n", regval); /* Configure SSI1 GPIOs */ @@ -1518,11 +1518,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port) /* Set all CR1 fields to reset state. This will be master mode. */ - ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); + ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0); /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ - ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); + ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0); /* Set the initial mode to mode 0. The application may override * this initial setting using the setmode() method. @@ -1547,7 +1547,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port) * while there is an SSI transfer in progress. */ - ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + ssi_putreg(priv, LM_SSI_IM_OFFSET, 0); /* Attach the interrupt */ diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.c b/nuttx/arch/arm/src/lm/lm_syscontrol.c index f0d0bd3c9..2ded66c8e 100644 --- a/nuttx/arch/arm/src/lm/lm_syscontrol.c +++ b/nuttx/arch/arm/src/lm/lm_syscontrol.c @@ -159,7 +159,7 @@ static inline void lm_plllock(void) { /* Check if the PLL is locked on */ - if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) + if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) { /* Yes.. return now */ @@ -191,17 +191,17 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) /* Get the current values of the RCC and RCC2 registers */ - rcc = getreg32(LM3S_SYSCON_RCC); - rcc2 = getreg32(LM3S_SYSCON_RCC2); + rcc = getreg32(LM_SYSCON_RCC); + rcc2 = getreg32(LM_SYSCON_RCC2); /* Temporarily bypass the PLL and system clock dividers */ rcc |= SYSCON_RCC_BYPASS; rcc &= ~(SYSCON_RCC_USESYSDIV); - putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc, LM_SYSCON_RCC); rcc2 |= SYSCON_RCC2_BYPASS2; - putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc2, LM_SYSCON_RCC2); /* We are probably using the main oscillator. The main oscillator is disabled on * reset and so probably must be enabled here. The internal oscillator is enabled @@ -214,7 +214,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) /* Enable any selected osciallators (but don't disable any yet) */ rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); - putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc, LM_SYSCON_RCC); /* Wait for the newly selected oscillator(s) to settle. This is tricky because * the time that we wait can be significant and is determined by the previous @@ -234,7 +234,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) /* Clear the PLL lock interrupt */ - putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); + putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC); /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC * is currently enabled. @@ -242,13 +242,13 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) if (rcc2 & SYSCON_RCC2_USERCC2) { - putreg32(rcc2, LM3S_SYSCON_RCC2); - putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM_SYSCON_RCC2); + putreg32(rcc, LM_SYSCON_RCC); } else { - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc, LM_SYSCON_RCC); + putreg32(rcc2, LM_SYSCON_RCC2); } /* Wait for the new crystal value and oscillator source to take effect */ @@ -279,8 +279,8 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2) /* Now we can set the final RCC/RCC2 values */ - putreg32(rcc, LM3S_SYSCON_RCC); - putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc, LM_SYSCON_RCC); + putreg32(rcc2, LM_SYSCON_RCC2); /* Wait for the system divider to be effective */ @@ -303,13 +303,13 @@ void up_clockconfig(void) * around a PLL bug */ - putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); + putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL); #endif /* Set the clocking to run with the default settings provided in the board.h * header file */ - lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); + lm_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE); } diff --git a/nuttx/arch/arm/src/lm/lm_timerisr.c b/nuttx/arch/arm/src/lm/lm_timerisr.c index 0469a473b..49e11e5c5 100644 --- a/nuttx/arch/arm/src/lm/lm_timerisr.c +++ b/nuttx/arch/arm/src/lm/lm_timerisr.c @@ -130,7 +130,7 @@ void up_timerinit(void) /* Attach the timer interrupt vector */ - (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); + (void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr); /* Enable SysTick interrupts */ @@ -138,5 +138,5 @@ void up_timerinit(void) /* And enable the timer interrupt */ - up_enable_irq(LM3S_IRQ_SYSTICK); + up_enable_irq(LM_IRQ_SYSTICK); } diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S index 93350a9ff..fecff0428 100644 --- a/nuttx/arch/arm/src/lm/lm_vectors.S +++ b/nuttx/arch/arm/src/lm/lm_vectors.S @@ -421,214 +421,214 @@ lm_vectors: .type handlers, function .thumb_func handlers: - HANDLER lm_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ - HANDLER lm_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ - HANDLER lm_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ - HANDLER lm_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ - HANDLER lm_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ - HANDLER lm_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ - HANDLER lm_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ - HANDLER lm_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ - HANDLER lm_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ - HANDLER lm_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ + HANDLER lm_reserved, LM_IRQ_RESERVED /* Unexpected/reserved vector */ + HANDLER lm_nmi, LM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ + HANDLER lm_hardfault, LM_IRQ_HARDFAULT /* Vector 3: Hard fault */ + HANDLER lm_mpu, LM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ + HANDLER lm_busfault, LM_IRQ_BUSFAULT /* Vector 5: Bus fault */ + HANDLER lm_usagefault, LM_IRQ_USAGEFAULT /* Vector 6: Usage fault */ + HANDLER lm_svcall, LM_IRQ_SVCALL /* Vector 11: SVC call */ + HANDLER lm_dbgmonitor, LM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ + HANDLER lm_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */ + HANDLER lm_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */ #if defined(CONFIG_ARCH_CHIP_LM3S6918) - HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ - HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ + HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: SSI 1 */ + HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ #elif defined(CONFIG_ARCH_CHIP_LM3S6432) - HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ #elif defined(CONFIG_ARCH_CHIP_LM3S6965) - HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ + HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ #elif defined(CONFIG_ARCH_CHIP_LM3S8962) - HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ + HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ - HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ - HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ - HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ - HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_usb, LM3S_IRQ_USB /* Vector 60: USB */ - HANDLER lm_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ - HANDLER lm_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ - HANDLER lm_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ - HANDLER lm_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ - HANDLER lm_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ - HANDLER lm_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ - HANDLER lm_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ - HANDLER lm_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ - HANDLER lm_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ - HANDLER lm_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ + HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm_cmp2, LM_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ + HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm_uart2, LM_IRQ_UART2 /* Vector 49: UART 2 */ + HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: GPIO Port H */ + HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm_can1, LM_IRQ_CAN1 /* Vector 56: CAN 1 */ + HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm_usb, LM_IRQ_USB /* Vector 60: USB */ + HANDLER lm_pwm3, LM_IRQ_PWM3 /* Vector 61: PWM 3 */ + HANDLER lm_udmasoft, LM_IRQ_UDMASOFT /* Vector 62: uDMA Software */ + HANDLER lm_udmaerror, LM_IRQ_UDMAERROR /* Vector 63: uDMA Error */ + HANDLER lm_adc1_0, LM_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ + HANDLER lm_adc1_1, LM_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ + HANDLER lm_adc1_2, LM_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ + HANDLER lm_adc1_3, LM_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ + HANDLER lm_i2s0, LM_IRQ_I2S0 /* Vector 68: I2S 0 */ + HANDLER lm_epi, LM_IRQ_EPI /* Vector 69: EPI */ + HANDLER lm_gpioj, LM_IRQ_GPIOJ /* Vector 70: GPIO Port J */ #else -# error "Vectors not specified for this LM3S chip" +# error "Vectors not specified for this Stellaris chip" #endif /* Common IRQ handling logic. On entry here, the return stack is on either diff --git a/nuttx/configs/avr32dev1/README.txt b/nuttx/configs/avr32dev1/README.txt index 37e15dc9b..1f52ff0c2 100644 --- a/nuttx/configs/avr32dev1/README.txt +++ b/nuttx/configs/avr32dev1/README.txt @@ -431,14 +431,16 @@ AVR32DEV1 Configuration Options Configurations ^^^^^^^^^^^^^^ -Each Stellaris LM3S6965 Evaluation Kit configuration is maintained in a -sudirectory and can be selected as follow: +Each Atmel AVR32DEV configuration is maintained in a sudirectory and +can be selected as follow: cd tools ./configure.sh avr32dev1/ cd - . ./setenv.sh +(Or configure.bat in a native Windows environment). + Where is one of the following: nsh: diff --git a/nuttx/configs/eagle100/README.txt b/nuttx/configs/eagle100/README.txt index 378f5a25b..8ed581e98 100644 --- a/nuttx/configs/eagle100/README.txt +++ b/nuttx/configs/eagle100/README.txt @@ -344,7 +344,7 @@ Eagle100-specific Configuration Options CONFIG_LM_DISABLE_GPIOH_IRQS=y CONFIG_LM_DISABLE_GPIOJ_IRQS=y - LM3S6818 specific device driver settings + LM3S6918 specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -368,7 +368,7 @@ Eagle100-specific Configuration Options Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) - to build the LM3S Ethernet driver + to build the Stellaris Ethernet driver CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. diff --git a/nuttx/configs/eagle100/include/board.h b/nuttx/configs/eagle100/include/board.h index 597f801ac..e7d9414a0 100644 --- a/nuttx/configs/eagle100/include/board.h +++ b/nuttx/configs/eagle100/include/board.h @@ -63,7 +63,7 @@ * of (400 / 2) / 4 = 50MHz */ -#define LM3S_SYSDIV 4 +#define LM_SYSDIV 4 #define SYSCLK_FREQUENCY 50000000 /* 50MHz */ /* Other RCC settings: @@ -74,7 +74,7 @@ * - No auto-clock gating reset */ -#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV)) /* RCC2 settings -- RCC2 not used. Other RCC2 settings * @@ -83,7 +83,7 @@ * - Not using RCC2 */ -#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV)) /* LED definitions ******************************************************************/ @@ -115,9 +115,9 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. * ************************************************************************************/ diff --git a/nuttx/configs/eagle100/src/eagle100_internal.h b/nuttx/configs/eagle100/src/eagle100_internal.h index 8a76e2eb5..48da6b9f7 100644 --- a/nuttx/configs/eagle100/src/eagle100_internal.h +++ b/nuttx/configs/eagle100/src/eagle100_internal.h @@ -56,12 +56,12 @@ * expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif diff --git a/nuttx/configs/eagle100/src/up_boot.c b/nuttx/configs/eagle100/src/up_boot.c index 8fed389f8..bd46bf288 100644 --- a/nuttx/configs/eagle100/src/up_boot.c +++ b/nuttx/configs/eagle100/src/up_boot.c @@ -63,9 +63,10 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * ************************************************************************************/ void lm_boardinitialize(void) diff --git a/nuttx/configs/eagle100/src/up_ethernet.c b/nuttx/configs/eagle100/src/up_ethernet.c index 42876b3b5..c3cea86e8 100644 --- a/nuttx/configs/eagle100/src/up_ethernet.c +++ b/nuttx/configs/eagle100/src/up_ethernet.c @@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr) /* Get the current value of the user registers */ - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); + user0 = getreg32(LM_FLASH_USERREG0); + user1 = getreg32(LM_FLASH_USERREG1); nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); diff --git a/nuttx/configs/ekk-lm3s9b96/README.txt b/nuttx/configs/ekk-lm3s9b96/README.txt index 78f7f7b8c..01aa1496c 100644 --- a/nuttx/configs/ekk-lm3s9b96/README.txt +++ b/nuttx/configs/ekk-lm3s9b96/README.txt @@ -324,7 +324,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options CONFIG_DRAM_START=0x20000000 - CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization + CONFIG_ARCH_IRQPRIO - The LM3S9B96 supports interrupt prioritization CONFIG_ARCH_IRQPRIO=y @@ -348,7 +348,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options the delay actually is 100 seconds. There are configurations for disabling support for interrupts GPIO ports. - GPIOJ must be disabled because it does not exist on the LM3S6918. + GPIOJ must be disabled because it does not exist on the LM3S9B96. Additional interrupt support can be disabled if desired to reduce memory footprint. @@ -362,7 +362,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options CONFIG_LM_DISABLE_GPIOH_IRQS=n CONFIG_LM_DISABLE_GPIOJ_IRQS=y - LM3S6818 specific device driver settings + LM3S9B96 specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -386,7 +386,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) - to build the LM3S Ethernet driver + to build the Stellaris Ethernet driver CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. diff --git a/nuttx/configs/ekk-lm3s9b96/include/board.h b/nuttx/configs/ekk-lm3s9b96/include/board.h index f5c997539..c2fe521c7 100644 --- a/nuttx/configs/ekk-lm3s9b96/include/board.h +++ b/nuttx/configs/ekk-lm3s9b96/include/board.h @@ -64,7 +64,7 @@ * of (400 / 2) / 4 = 50MHz */ -#define LM3S_SYSDIV 4 +#define LM_SYSDIV 4 #define SYSCLK_FREQUENCY 50000000 /* 50MHz */ /* Other RCC settings: @@ -75,7 +75,7 @@ * - No auto-clock gating reset */ -#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV)) /* RCC2 settings -- RCC2 not used. Other RCC2 settings * @@ -84,7 +84,7 @@ * - Not using RCC2 */ -#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV)) /* LED definitions ******************************************************************/ @@ -116,9 +116,9 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. * ************************************************************************************/ diff --git a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h index d7ab916c8..a353020b8 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h +++ b/nuttx/configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h @@ -57,12 +57,12 @@ * expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c index 16057ccb9..312f63adc 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_boot.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_boot.c @@ -65,9 +65,10 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * ************************************************************************************/ void lm_boardinitialize(void) diff --git a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c index bc4149082..735073803 100644 --- a/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c +++ b/nuttx/configs/ekk-lm3s9b96/src/up_ethernet.c @@ -81,8 +81,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr) /* Get the current value of the user registers */ - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); + user0 = getreg32(LM_FLASH_USERREG0); + user1 = getreg32(LM_FLASH_USERREG1); nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); diff --git a/nuttx/configs/lm3s6432-s2e/README.txt b/nuttx/configs/lm3s6432-s2e/README.txt index 29cf80fae..7241856b0 100644 --- a/nuttx/configs/lm3s6432-s2e/README.txt +++ b/nuttx/configs/lm3s6432-s2e/README.txt @@ -318,7 +318,7 @@ Stellaris MDL-S2E Reference Design Configuration Options CONFIG_DRAM_START=0x20000000 - CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization + CONFIG_ARCH_IRQPRIO - The LM3S6432 supports interrupt prioritization CONFIG_ARCH_IRQPRIO=y @@ -389,7 +389,7 @@ Stellaris MDL-S2E Reference Design Configuration Options Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) - to build the LM3S Ethernet driver + to build the Stellaris Ethernet driver CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM_BOARDMAC - This should be set in order to use the MAC address configured in the flash USER registers. diff --git a/nuttx/configs/lm3s6432-s2e/include/board.h b/nuttx/configs/lm3s6432-s2e/include/board.h index 7fdcabf76..a3d560361 100644 --- a/nuttx/configs/lm3s6432-s2e/include/board.h +++ b/nuttx/configs/lm3s6432-s2e/include/board.h @@ -63,7 +63,7 @@ * of (400 / 2) / 4 = 50MHz */ -#define LM3S_SYSDIV 4 +#define LM_SYSDIV 4 #define SYSCLK_FREQUENCY 50000000 /* 50MHz */ /* Other RCC settings: @@ -74,7 +74,7 @@ * - No auto-clock gating reset */ -#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV)) /* RCC2 settings -- RCC2 not used. Other RCC2 settings * @@ -83,7 +83,7 @@ * - Not using RCC2 */ -#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV)) /* LED definitions ******************************************************************/ @@ -117,9 +117,9 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. * ************************************************************************************/ diff --git a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h index f95b118ad..3f05bdc63 100644 --- a/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h +++ b/nuttx/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h @@ -55,7 +55,7 @@ * expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 #endif diff --git a/nuttx/configs/lm3s6432-s2e/src/up_boot.c b/nuttx/configs/lm3s6432-s2e/src/up_boot.c index da900282f..60be9c3cf 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_boot.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_boot.c @@ -70,9 +70,10 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * ************************************************************************************/ void lm_boardinitialize(void) diff --git a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c index 434ffe2c5..54c88a37b 100644 --- a/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c +++ b/nuttx/configs/lm3s6432-s2e/src/up_ethernet.c @@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr) /* Get the current value of the user registers */ - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); + user0 = getreg32(LM_FLASH_USERREG0); + user1 = getreg32(LM_FLASH_USERREG1); nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index 813e11467..77f034bf5 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -387,7 +387,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options CONFIG_DRAM_START=0x20000000 - CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization + CONFIG_ARCH_IRQPRIO - The LM3S6965 supports interrupt prioritization CONFIG_ARCH_IRQPRIO=y @@ -411,7 +411,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options the delay actually is 100 seconds. There are configurations for disabling support for interrupts GPIO ports. - GPIOJ must be disabled because it does not exist on the LM3S6918. + GPIOJ must be disabled because it does not exist on the LM3S6965. Additional interrupt support can be disabled if desired to reduce memory footprint. @@ -425,7 +425,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options CONFIG_LM_DISABLE_GPIOH_IRQS=n CONFIG_LM_DISABLE_GPIOJ_IRQS=y - LM3S6818 specific device driver settings + LM3S6965 specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -449,7 +449,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) - to build the LM3S Ethernet driver + to build the Stellaris Ethernet driver CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. diff --git a/nuttx/configs/lm3s6965-ek/include/board.h b/nuttx/configs/lm3s6965-ek/include/board.h index 808d009cc..112c40b7a 100644 --- a/nuttx/configs/lm3s6965-ek/include/board.h +++ b/nuttx/configs/lm3s6965-ek/include/board.h @@ -63,7 +63,7 @@ * of (400 / 2) / 4 = 50MHz */ -#define LM3S_SYSDIV 4 +#define LM_SYSDIV 4 #define SYSCLK_FREQUENCY 50000000 /* 50MHz */ /* Other RCC settings: @@ -74,7 +74,7 @@ * - No auto-clock gating reset */ -#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV)) /* RCC2 settings -- RCC2 not used. Other RCC2 settings * @@ -83,7 +83,7 @@ * - Not using RCC2 */ -#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV)) /* LED definitions ******************************************************************/ @@ -115,9 +115,9 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. * ************************************************************************************/ diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 99f2f50ab..5c288f95d 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# LM3S Configuration Options +# Stellaris Configuration Options # # CONFIG_ARCH_CHIP_LM3S6918 is not set # CONFIG_ARCH_CHIP_LM3S9B96 is not set @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y CONFIG_LM_DFU=y # -# Select LM3S Peripheral Support +# Select Stellaris Peripheral Support # CONFIG_LM_UART0=y # CONFIG_LM_UART1 is not set @@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y CONFIG_LM_DISABLE_GPIOJ_IRQS=y # -# LM3S Ethernet Configuration +# Stellaris Ethernet Configuration # # CONFIG_LM_ETHLEDS is not set # CONFIG_LM_BOARDMAC is not set @@ -141,7 +141,7 @@ CONFIG_LM_DISABLE_GPIOJ_IRQS=y # CONFIG_M3S_DUMPPACKET is not set # -# LM3S SSI Configuration +# Stellaris SSI Configuration # CONFIG_SSI_POLLWAIT=y CONFIG_SSI_TXLIMIT=4 diff --git a/nuttx/configs/lm3s6965-ek/nx/defconfig b/nuttx/configs/lm3s6965-ek/nx/defconfig index b86d06dc9..b123800e0 100755 --- a/nuttx/configs/lm3s6965-ek/nx/defconfig +++ b/nuttx/configs/lm3s6965-ek/nx/defconfig @@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# LM3S Configuration Options +# Stellaris Configuration Options # # CONFIG_ARCH_CHIP_LM3S6918 is not set # CONFIG_ARCH_CHIP_LM3S9B96 is not set @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y CONFIG_LM_DFU=y # -# Select LM3S Peripheral Support +# Select Stellaris Peripheral Support # CONFIG_LM_UART0=y # CONFIG_LM_UART1 is not set @@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y CONFIG_LM_DISABLE_GPIOJ_IRQS=y # -# LM3S SSI Configuration +# Stellaris SSI Configuration # CONFIG_SSI_POLLWAIT=y CONFIG_SSI_TXLIMIT=4 diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index bc433e116..67633c916 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# LM3S Configuration Options +# Stellaris Configuration Options # # CONFIG_ARCH_CHIP_LM3S6918 is not set # CONFIG_ARCH_CHIP_LM3S9B96 is not set @@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y CONFIG_LM_DFU=y # -# Select LM3S Peripheral Support +# Select Stellaris Peripheral Support # CONFIG_LM_UART0=y # CONFIG_LM_UART1 is not set @@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y CONFIG_LM_DISABLE_GPIOJ_IRQS=y # -# LM3S SSI Configuration +# Stellaris SSI Configuration # CONFIG_SSI_POLLWAIT=y CONFIG_SSI_TXLIMIT=4 diff --git a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h index c2fc50df1..00d55ed40 100644 --- a/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h +++ b/nuttx/configs/lm3s6965-ek/src/lm3s6965ek_internal.h @@ -56,12 +56,12 @@ * expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif diff --git a/nuttx/configs/lm3s6965-ek/src/up_boot.c b/nuttx/configs/lm3s6965-ek/src/up_boot.c index 7ffd37f17..6229a2a59 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_boot.c +++ b/nuttx/configs/lm3s6965-ek/src/up_boot.c @@ -64,9 +64,10 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * ************************************************************************************/ void lm_boardinitialize(void) diff --git a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c index 2d114baaa..81d6cda26 100644 --- a/nuttx/configs/lm3s6965-ek/src/up_ethernet.c +++ b/nuttx/configs/lm3s6965-ek/src/up_ethernet.c @@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr) /* Get the current value of the user registers */ - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); + user0 = getreg32(LM_FLASH_USERREG0); + user1 = getreg32(LM_FLASH_USERREG1); nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); diff --git a/nuttx/configs/lm3s8962-ek/README.txt b/nuttx/configs/lm3s8962-ek/README.txt index 38ed76aea..e8a0091c6 100644 --- a/nuttx/configs/lm3s8962-ek/README.txt +++ b/nuttx/configs/lm3s8962-ek/README.txt @@ -371,7 +371,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options CONFIG_DRAM_START=0x20000000 - CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization + CONFIG_ARCH_IRQPRIO - The LM3S8962 supports interrupt prioritization CONFIG_ARCH_IRQPRIO=y @@ -395,7 +395,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options the delay actually is 100 seconds. There are configurations for disabling support for interrupts GPIO ports. - GPIOJ must be disabled because it does not exist on the LM3S6918. + GPIOJ must be disabled because it does not exist on the LM3S8962. Additional interrupt support can be disabled if desired to reduce memory footprint. @@ -409,7 +409,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options CONFIG_LM_DISABLE_GPIOH_IRQS=n CONFIG_LM_DISABLE_GPIOJ_IRQS=y - LM3S6818 specific device driver settings + LM3S8962 specific device driver settings CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the console and ttys0 (default is the UART0). @@ -433,7 +433,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options Rx FIFO overrun errors. Default: half of the Tx FIFO size (4). CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET) - to build the LM3S Ethernet driver + to build the Stellaris Ethernet driver CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board. CONFIG_LM_BOARDMAC - If the board-specific logic can provide a MAC address (via lm_ethernetmac()), then this should be selected. diff --git a/nuttx/configs/lm3s8962-ek/include/board.h b/nuttx/configs/lm3s8962-ek/include/board.h index 4d6a0c302..9c4adeaa7 100644 --- a/nuttx/configs/lm3s8962-ek/include/board.h +++ b/nuttx/configs/lm3s8962-ek/include/board.h @@ -63,7 +63,7 @@ * of (400 / 2) / 4 = 50MHz */ -#define LM3S_SYSDIV 4 +#define LM_SYSDIV 4 #define SYSCLK_FREQUENCY 50000000 /* 50MHz */ /* Other RCC settings: @@ -74,7 +74,7 @@ * - No auto-clock gating reset */ -#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV)) /* RCC2 settings -- RCC2 not used. Other RCC2 settings * @@ -83,7 +83,7 @@ * - Not using RCC2 */ -#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV)) +#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV)) /* LED definitions ******************************************************************/ @@ -115,9 +115,9 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. * ************************************************************************************/ diff --git a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h index 7fc8fa331..3f989bc13 100644 --- a/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h +++ b/nuttx/configs/lm3s8962-ek/src/lm3s8962ek_internal.h @@ -56,12 +56,12 @@ * expanded). */ -#if LM3S_NSSI == 0 +#if LM_NSSI == 0 # undef CONFIG_SSI0_DISABLE # define CONFIG_SSI0_DISABLE 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 +#elif LM_NSSI == 1 # undef CONFIG_SSI1_DISABLE # define CONFIG_SSI1_DISABLE 1 #endif diff --git a/nuttx/configs/lm3s8962-ek/src/up_boot.c b/nuttx/configs/lm3s8962-ek/src/up_boot.c index 8dc5b81cc..655aa6993 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_boot.c +++ b/nuttx/configs/lm3s8962-ek/src/up_boot.c @@ -64,9 +64,10 @@ * Name: lm_boardinitialize * * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All Stellaris architectures must provide the following entry point. This entry + * point is called early in the intitialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * ************************************************************************************/ void lm_boardinitialize(void) diff --git a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c index 0d73233a4..63c681af9 100644 --- a/nuttx/configs/lm3s8962-ek/src/up_ethernet.c +++ b/nuttx/configs/lm3s8962-ek/src/up_ethernet.c @@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr) /* Get the current value of the user registers */ - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); + user0 = getreg32(LM_FLASH_USERREG0); + user1 = getreg32(LM_FLASH_USERREG1); nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); diff --git a/nuttx/configs/lpcxpresso-lpc1768/README.txt b/nuttx/configs/lpcxpresso-lpc1768/README.txt index ca0c0fdbd..1d9c0cbc2 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/README.txt +++ b/nuttx/configs/lpcxpresso-lpc1768/README.txt @@ -361,7 +361,7 @@ Code Red IDE crt_emu_cm3_nxp (for LPC17xx parts) crt_emu_a7_nxp (for LPC21/22/23/24 parts) crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts) - crt_emu_cm3_lmi (for TI Stellaris LM3S parts + crt_emu_cm3_lmi (for TI Stellaris parts) wire is one of: diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c index 894404cc2..7b5f02e31 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c +++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c @@ -52,8 +52,6 @@ #include "lpc17_internal.h" #include "lpcxpresso_internal.h" -/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ - #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) /************************************************************************************ @@ -98,7 +96,7 @@ * Name: lpc17_sspinitialize * * Description: - * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. + * Called to configure SPI chip select GPIO pins for the LPCXpresso. * ************************************************************************************/ diff --git a/nuttx/configs/nucleus2g/src/up_ssp.c b/nuttx/configs/nucleus2g/src/up_ssp.c index 5515d4968..13a768130 100644 --- a/nuttx/configs/nucleus2g/src/up_ssp.c +++ b/nuttx/configs/nucleus2g/src/up_ssp.c @@ -52,8 +52,6 @@ #include "lpc17_internal.h" #include "nucleus2g_internal.h" -/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ - #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) /************************************************************************************ @@ -98,7 +96,7 @@ * Name: lpc17_sspinitialize * * Description: - * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. + * Called to configure SPI chip select GPIO pins for the Nucleus 2G. * ************************************************************************************/ diff --git a/nuttx/include/nuttx/net/mii.h b/nuttx/include/nuttx/net/mii.h index 6a5fc6e89..de4dcdfd7 100644 --- a/nuttx/include/nuttx/net/mii.h +++ b/nuttx/include/nuttx/net/mii.h @@ -112,12 +112,12 @@ /* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */ -#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */ -#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */ -#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */ -#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */ -#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */ -#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */ +#define MII_LM_VSPECIFIC 0x10 /* Vendor-Specific */ +#define MII_LM_INTCS 0x11 /* Interrupt control/status */ +#define MII_LM_DIAGNOSTIC 0x12 /* Diagnostic */ +#define MII_LM_XCVRCONTROL 0x13 /* Transceiver Control */ +#define MII_LM_LEDCONFIG 0x17 /* LED Configuration */ +#define MII_LM_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */ /* Micrel KS8721: 0x15, 0x1b, and 0x1f */ @@ -323,79 +323,79 @@ /* LM3S6918-specific register bit settings **********************************/ /* LM3S6918 Vendor-Specific, address 0x10 */ -#define LM3S_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/ -#define LM3S_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */ -#define LM3S_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */ -#define LM3S_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */ -#define LM3S_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */ -#define LM3S_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */ -#define LM3S_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */ -#define LM3S_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/ -#define LM3S_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/ +#define LM_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/ +#define LM_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */ +#define LM_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */ +#define LM_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */ +#define LM_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */ +#define LM_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */ +#define LM_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */ +#define LM_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/ +#define LM_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/ /* LM3S6918 Interrupt Control/Status, address 0x11 */ -#define LM3S_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */ -#define LM3S_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */ -#define LM3S_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */ -#define LM3S_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */ -#define LM3S_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */ -#define LM3S_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */ -#define LM3S_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */ -#define LM3S_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */ -#define LM3S_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */ -#define LM3S_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */ -#define LM3S_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */ -#define LM3S_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */ -#define LM3S_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */ -#define LM3S_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */ -#define LM3S_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */ -#define LM3S_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */ +#define LM_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */ +#define LM_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */ +#define LM_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */ +#define LM_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */ +#define LM_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */ +#define LM_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */ +#define LM_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */ +#define LM_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */ +#define LM_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */ +#define LM_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */ +#define LM_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */ +#define LM_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */ +#define LM_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */ +#define LM_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */ +#define LM_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */ +#define LM_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */ /* LM3S6918 Diagnostic, address 0x12 */ -#define LM3S_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */ -#define LM3S_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */ -#define LM3S_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */ -#define LM3S_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */ -#define LM3S_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */ +#define LM_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */ +#define LM_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */ +#define LM_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */ +#define LM_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */ +#define LM_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */ /* LM3S6918 Transceiver Control, address 0x13 */ -#define LM3S_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */ -#define LM3S_XCVRCONTROL_TXO_MASK (3 << LM3S_XCVRCONTROL_TXO_SHIFT) -#define LM3S_XCVRCONTROL_TXO_00DB (0 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */ -#define LM3S_XCVRCONTROL_TXO_04DB (1 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */ -#define LM3S_XCVRCONTROL_TXO_08DB (2 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */ -#define LM3S_XCVRCONTROL_TXO_12DB (3 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */ +#define LM_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */ +#define LM_XCVRCONTROL_TXO_MASK (3 << LM_XCVRCONTROL_TXO_SHIFT) +#define LM_XCVRCONTROL_TXO_00DB (0 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */ +#define LM_XCVRCONTROL_TXO_04DB (1 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */ +#define LM_XCVRCONTROL_TXO_08DB (2 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */ +#define LM_XCVRCONTROL_TXO_12DB (3 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */ /* LM3S6918 LED Configuration, address 0x17 */ -#define LM3S_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */ -#define LM3S_LEDCONFIG_LED0_MASK (0x0f << LM3S_LEDCONFIG_LED0_SHIFT) -#define LM3S_LEDCONFIG_LED0_LINKOK (0 << LM3S_LEDCONFIG_LED0_SHIFT) /* Link OK */ -#define LM3S_LEDCONFIG_LED0_RXTX (1 << LM3S_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */ -#define LM3S_LEDCONFIG_LED0_100BASET (5 << LM3S_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */ -#define LM3S_LEDCONFIG_LED0_10BASET (6 << LM3S_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */ -#define LM3S_LEDCONFIG_LED0_FDUPLEX (7 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */ -#define LM3S_LEDCONFIG_LED0_OKRXTX (8 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */ -#define LM3S_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */ -#define LM3S_LEDCONFIG_LED1_MASK (0x0f << LM3S_LEDCONFIG_LED1_SHIFT) -#define LM3S_LEDCONFIG_LED1_LINKOK (0 << LM3S_LEDCONFIG_LED1_SHIFT) /* Link OK */ -#define LM3S_LEDCONFIG_LED1_RXTX (1 << LM3S_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */ -#define LM3S_LEDCONFIG_LED1_100BASET (5 << LM3S_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */ -#define LM3S_LEDCONFIG_LED1_10BASET (6 << LM3S_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */ -#define LM3S_LEDCONFIG_LED1_FDUPLEX (7 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */ -#define LM3S_LEDCONFIG_LED1_OKRXTX (8 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */ +#define LM_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */ +#define LM_LEDCONFIG_LED0_MASK (0x0f << LM_LEDCONFIG_LED0_SHIFT) +#define LM_LEDCONFIG_LED0_LINKOK (0 << LM_LEDCONFIG_LED0_SHIFT) /* Link OK */ +#define LM_LEDCONFIG_LED0_RXTX (1 << LM_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */ +#define LM_LEDCONFIG_LED0_100BASET (5 << LM_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */ +#define LM_LEDCONFIG_LED0_10BASET (6 << LM_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */ +#define LM_LEDCONFIG_LED0_FDUPLEX (7 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */ +#define LM_LEDCONFIG_LED0_OKRXTX (8 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */ +#define LM_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */ +#define LM_LEDCONFIG_LED1_MASK (0x0f << LM_LEDCONFIG_LED1_SHIFT) +#define LM_LEDCONFIG_LED1_LINKOK (0 << LM_LEDCONFIG_LED1_SHIFT) /* Link OK */ +#define LM_LEDCONFIG_LED1_RXTX (1 << LM_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */ +#define LM_LEDCONFIG_LED1_100BASET (5 << LM_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */ +#define LM_LEDCONFIG_LED1_10BASET (6 << LM_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */ +#define LM_LEDCONFIG_LED1_FDUPLEX (7 << LM_LEDCONFIG_LED1_SHIFT) /* Full duplex */ +#define LM_LEDCONFIG_LED1_OKRXTX (8 << LM_LEDCONFIG_LED1_SHIFT) /* Full duplex */ /* LM3S6918 MDI/MDIX Control, address 0x18 */ -#define LM3S_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */ -#define LM3S_MDICONTROL_MDIXSD_MASK (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT) -#define LM3S_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */ -#define LM3S_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */ -#define LM3S_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */ -#define LM3S_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */ +#define LM_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */ +#define LM_MDICONTROL_MDIXSD_MASK (0x0f << LM_MDICONTROL_MDIXSD_SHIFT) +#define LM_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */ +#define LM_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */ +#define LM_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */ +#define LM_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */ /* KS8921-specific register bit settings ************************************/ /* KS8921 MII Control register bit definitions (not in 802.3) */ @@ -430,26 +430,26 @@ /* KS8921 10BASE-TX PHY control register */ -#define KS8721_10BTCR_BIT0 (1 << 0) /* Bit 0: xxx */ -#define KS8721_10BTCR_BIT1 (1 << 1) /* Bit 1: xxx */ -#define KS8721_10BTCR_MODE_SHIFT (2) /* Bits 2-4: Operation Mode Indication */ -#define KS8721_10BTCR_MODE_MASK (7 << KS8721_10BTCR_MODE_SHIFT) -# define KS8721_10BTCR_MODE_ANEG (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */ -# define KS8721_10BTCR_MODE_10BTHD (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */ -# define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */ -# define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */ -# define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */ -# define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */ -# define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */ -#define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */ -#define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */ -#define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */ -#define KS8721_10BTCR_JABBERE (1 << 8) /* Bit 8: Enable Jabber */ -#define KS8721_10BTCR_INTLVL (1 << 9) /* Bit 9: Interrupt level */ -#define KS8721_10BTCR_POWER (1 << 10) /* Bit 10: Power saving */ -#define KS8721_10BTCR_FORCE (1 << 11) /* Bit 11: Force link */ -#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */ -#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */ +#define KS8721_10BTCR_BIT0 (1 << 0) /* Bit 0: xxx */ +#define KS8721_10BTCR_BIT1 (1 << 1) /* Bit 1: xxx */ +#define KS8721_10BTCR_MODE_SHIFT (2) /* Bits 2-4: Operation Mode Indication */ +#define KS8721_10BTCR_MODE_MASK (7 << KS8721_10BTCR_MODE_SHIFT) +# define KS8721_10BTCR_MODE_ANEG (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */ +# define KS8721_10BTCR_MODE_10BTHD (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */ +# define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */ +# define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */ +# define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */ +# define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */ +# define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */ +#define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */ +#define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */ +#define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */ +#define KS8721_10BTCR_JABBERE (1 << 8) /* Bit 8: Enable Jabber */ +#define KS8721_10BTCR_INTLVL (1 << 9) /* Bit 9: Interrupt level */ +#define KS8721_10BTCR_POWER (1 << 10) /* Bit 10: Power saving */ +#define KS8721_10BTCR_FORCE (1 << 11) /* Bit 11: Force link */ +#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */ +#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */ /**************************************************************************** * Type Definitions -- cgit v1.2.3 From d844f61f8ad81de5bf2b4353763ca92634fb73f4 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 9 Jan 2013 19:49:16 +0000 Subject: Re-partition Stellaris vector logic git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5499 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lm/irq.h | 281 +---------------- nuttx/arch/arm/include/lm/lm3s_irq.h | 424 +++++++++++++++++++++++++ nuttx/arch/arm/src/lm/chip/lm3s_vectors.h | 439 ++++++++++++++++++++++++++ nuttx/arch/arm/src/lm/chip/lm_memorymap.h | 4 +- nuttx/arch/arm/src/lm/chip/lm_pinmap.h | 4 +- nuttx/arch/arm/src/lm/chip/lm_vectors.h | 64 ++++ nuttx/arch/arm/src/lm/lm_vectors.S | 498 +----------------------------- 7 files changed, 963 insertions(+), 751 deletions(-) create mode 100644 nuttx/arch/arm/include/lm/lm3s_irq.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm3s_vectors.h create mode 100644 nuttx/arch/arm/src/lm/chip/lm_vectors.h diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h index 9a5a3d153..3b984a826 100644 --- a/nuttx/arch/arm/include/lm/irq.h +++ b/nuttx/arch/arm/include/lm/irq.h @@ -33,10 +33,6 @@ * ************************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h - */ - #ifndef __ARCH_ARM_INCLUDE_LM_IRQ_H #define __ARCH_ARM_INCLUDE_LM_IRQ_H @@ -47,263 +43,18 @@ #include #include -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in the IRQ - * to handle mapping tables. - */ - -/* Processor Exceptions (vectors 0-15) */ - -#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - -# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25-29: Reserved */ -# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ - /* Vector 49: Reserved */ -# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ - /* Vectors 54-57: Reserved */ -# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ - /* Vector 25: Reserved */ -# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ - /* Vectors 27-29: Reserved */ -# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vectors 48-57: Reserved */ -# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vectors 59-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ - /* Vector 43: Reserved */ -# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ -# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ - /* Vector 50: Reserved */ -# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ - /* Vectors 55-57: Reserved */ -# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ -# define LM_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ -# define LM_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ -# define LM_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ -# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ -# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ -# define LM_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ -# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ -# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ -# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ -# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ -# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ -# define LM_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ - /* Vector 57: Reserved */ -# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ - /* Vector 59: Reserved */ -# define LM_IRQ_USB (60) /* Vector 60: USB */ -# define LM_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ -# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ -# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ -# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ -# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ -# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ -# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ -# define LM_IRQ_I2S0 (68) /* Vector 68: I2S0 */ -# define LM_IRQ_EPI (69) /* Vector 69: EPI */ -# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ - /* Vector 71: Reserved */ -# define NR_IRQS (71) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ -# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ -# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ -# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ -# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ -# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ -# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ -# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ -# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ -# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ -# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ -# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ -# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ -# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ -# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ -# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ -# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ -# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ -# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ -# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ -# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ -# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ -# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ -# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ -# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ -# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ - /* Vector 42: Reserved */ - /* Vector 43: Reserved */ -# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ -# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ -# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ -# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ - /* Vector 48: Reserved */ - /* Vector 49: Reserved */ - /* Vector 50: Reserved */ -# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ -# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ -# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ -# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ -# define LM_IRQ_CAN0 (54) /* Vector 55: CAN0 */ - /* Vectors 56-57: Reserved */ -# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ -# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ - /* Vectors 60-70: Reserved */ -# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#if defined(CONFIG_ARCH_CHIP_LM3S) +# include +#elif defined(CONFIG_ARCH_CHIP_LM4F) +# include #else -# error "IRQ Numbers not specified for this Stellaris chip" +# error "Unsupported Stellaris IRQ file" #endif +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* GPIO IRQs -- Note that support for individual GPIO ports can * be disabled in order to reduce the size of the implemenation. */ @@ -446,10 +197,8 @@ #ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif /************************************************************************************ @@ -464,7 +213,7 @@ extern "C" { * ****************************************************************************/ -EXTERN int gpio_irqattach(int irq, xcpt_t isr); +int gpio_irqattach(int irq, xcpt_t isr); #define gpio_irqdetach(isr) gpio_irqattach(isr, NULL) /**************************************************************************** @@ -475,7 +224,7 @@ EXTERN int gpio_irqattach(int irq, xcpt_t isr); * ****************************************************************************/ -EXTERN void gpio_irqenable(int irq); +void gpio_irqenable(int irq); /**************************************************************************** * Name: gpio_irqdisable @@ -485,13 +234,11 @@ EXTERN void gpio_irqenable(int irq); * ****************************************************************************/ -EXTERN void gpio_irqdisable(int irq); +void gpio_irqdisable(int irq); -#undef EXTERN #ifdef __cplusplus } #endif #endif #endif /* __ARCH_ARM_INCLUDE_LM_IRQ_H */ - diff --git a/nuttx/arch/arm/include/lm/lm3s_irq.h b/nuttx/arch/arm/include/lm/lm3s_irq.h new file mode 100644 index 000000000..a9d0640d9 --- /dev/null +++ b/nuttx/arch/arm/include/lm/lm3s_irq.h @@ -0,0 +1,424 @@ +/************************************************************************************ + * arch/arm/include/lm/lm3s_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H +#define __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ + +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_RESERVED_25 (25) /* Vector 25: Reserved */ +# define LM_RESERVED_26 (26) /* Vector 26: Reserved */ +# define LM_RESERVED_27 (27) /* Vector 27: Reserved */ +# define LM_RESERVED_28 (28) /* Vector 28: Reserved */ +# define LM_RESERVED_29 (29) /* Vector 29: Reserved */ + +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ + +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM_RESERVED_43 (43) /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ +# define LM_RESERVED_49 (49) /* Vector 49: Reserved */ + +# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_RESERVED_54 (54) /* Vector 54: Reserved */ +# define LM_RESERVED_55 (55) /* Vector 55: Reserved */ +# define LM_RESERVED_56 (56) /* Vector 56: Reserved */ +# define LM_RESERVED_57 (57) /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + +# define LM_RESERVED_60 (60) /* Vector 60: Reserved */ +# define LM_RESERVED_61 (61) /* Vector 61: Reserved */ +# define LM_RESERVED_62 (62) /* Vector 62: Reserved */ +# define LM_RESERVED_63 (63) /* Vector 63: Reserved */ +# define LM_RESERVED_64 (64) /* Vector 64: Reserved */ +# define LM_RESERVED_65 (65) /* Vector 65: Reserved */ +# define LM_RESERVED_66 (66) /* Vector 66: Reserved */ +# define LM_RESERVED_67 (67) /* Vector 67: Reserved */ +# define LM_RESERVED_68 (68) /* Vector 68: Reserved */ +# define LM_RESERVED_69 (69) /* Vector 69: Reserved */ + +# define LM_RESERVED_70 (70) /* Vector 70: Reserved */ + +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ + +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_RESERVED_25 (25) /* Vector 25: Reserved */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_RESERVED_27 (27) /* Vector 27: Reserved */ +# define LM_RESERVED_28 (28) /* Vector 28: Reserved */ +# define LM_RESERVED_29 (29) /* Vector 29: Reserved */ + +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ + +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM_RESERVED_43 (43) /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_RESERVED_48 (48) /* Vector 48: Reserved */ +# define LM_RESERVED_49 (49) /* Vector 49: Reserved */ + +# define LM_RESERVED_50 (50) /* Vector 50: Reserved */ +# define LM_RESERVED_51 (51) /* Vector 51: Reserved */ +# define LM_RESERVED_52 (52) /* Vector 52: Reserved */ +# define LM_RESERVED_53 (53) /* Vector 53: Reserved */ +# define LM_RESERVED_54 (54) /* Vector 54: Reserved */ +# define LM_RESERVED_55 (55) /* Vector 55: Reserved */ +# define LM_RESERVED_56 (56) /* Vector 56: Reserved */ +# define LM_RESERVED_57 (57) /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_RESERVED_59 (59) /* Vector 59: Reserved */ + +# define LM_RESERVED_60 (60) /* Vector 60: Reserved */ +# define LM_RESERVED_61 (61) /* Vector 61: Reserved */ +# define LM_RESERVED_62 (62) /* Vector 62: Reserved */ +# define LM_RESERVED_63 (63) /* Vector 63: Reserved */ +# define LM_RESERVED_64 (64) /* Vector 64: Reserved */ +# define LM_RESERVED_65 (65) /* Vector 65: Reserved */ +# define LM_RESERVED_66 (66) /* Vector 66: Reserved */ +# define LM_RESERVED_67 (67) /* Vector 67: Reserved */ +# define LM_RESERVED_68 (68) /* Vector 68: Reserved */ +# define LM_RESERVED_69 (69) /* Vector 69: Reserved */ + +# define LM_RESERVED_70 (70) /* Vector 70: Reserved */ + +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ + +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ + +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ + +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM_RESERVED_43 (43) /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_RESERVED_48 (48) /* Vector 48: Reserved */ +# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ + +# define LM_RESERVED_50 (50) /* Vector 50: Reserved */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM_RESERVED_55 (55) /* Vector 55: Reserved */ +# define LM_RESERVED_56 (56) /* Vector 56: Reserved */ +# define LM_RESERVED_57 (57) /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + +# define LM_RESERVED_60 (60) /* Vector 60: Reserved */ +# define LM_RESERVED_61 (61) /* Vector 61: Reserved */ +# define LM_RESERVED_62 (62) /* Vector 62: Reserved */ +# define LM_RESERVED_63 (63) /* Vector 63: Reserved */ +# define LM_RESERVED_64 (64) /* Vector 64: Reserved */ +# define LM_RESERVED_65 (65) /* Vector 65: Reserved */ +# define LM_RESERVED_66 (66) /* Vector 66: Reserved */ +# define LM_RESERVED_67 (67) /* Vector 67: Reserved */ +# define LM_RESERVED_68 (68) /* Vector 68: Reserved */ +# define LM_RESERVED_69 (69) /* Vector 69: Reserved */ + +# define LM_RESERVED_70 (70) /* Vector 70: Reserved */ + +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ + +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ + +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ + +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */ +# define LM_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */ +# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */ + +# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 1 */ +# define LM_IRQ_CAN1 (56) /* Vector 56: CAN 2 */ +# define LM_RESERVED_57 (57) /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_RESERVED_59 (59) /* Vector 59: Reserved */ + +# define LM_IRQ_USB (60) /* Vector 60: USB */ +# define LM_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */ +# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */ +# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */ +# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */ +# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */ +# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */ +# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */ +# define LM_IRQ_I2S0 (68) /* Vector 68: I2S0 */ +# define LM_IRQ_EPI (69) /* Vector 69: EPI */ + +# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */ +# define LM_RESERVED_71 (71) /* Vector 71: Reserved */ + +# define NR_IRQS (71) /* (Really less because of reserved vectors) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ +# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ +# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ +# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */ + +# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */ +# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */ +# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */ +# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */ +# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */ +# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */ +# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */ +# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */ +# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */ +# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */ + +# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */ +# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */ +# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */ +# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */ +# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */ +# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */ +# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */ +# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */ +# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */ +# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */ +# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */ + +# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */ +# define LM_RESERVED_42 (42) /* Vector 42: Reserved */ +# define LM_RESERVED_43 (43) /* Vector 43: Reserved */ +# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */ +# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */ +# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */ +# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */ +# define LM_RESERVED_48 (48) /* Vector 48: Reserved */ +# define LM_RESERVED_49 (49) /* Vector 49: Reserved */ + +# define LM_RESERVED_50 (50) /* Vector 50: Reserved */ +# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */ +# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */ +# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */ +# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */ +# define LM_IRQ_CAN0 (54) /* Vector 55: CAN0 */ +# define LM_RESERVED_56 (56) /* Vector 56: Reserved */ +# define LM_RESERVED_57 (57) /* Vector 57: Reserved */ +# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */ +# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */ + +# define LM_RESERVED_60 (60) /* Vector 60: Reserved */ +# define LM_RESERVED_61 (61) /* Vector 61: Reserved */ +# define LM_RESERVED_62 (62) /* Vector 62: Reserved */ +# define LM_RESERVED_63 (63) /* Vector 63: Reserved */ +# define LM_RESERVED_64 (64) /* Vector 64: Reserved */ +# define LM_RESERVED_65 (65) /* Vector 65: Reserved */ +# define LM_RESERVED_66 (66) /* Vector 66: Reserved */ +# define LM_RESERVED_67 (67) /* Vector 67: Reserved */ +# define LM_RESERVED_68 (68) /* Vector 68: Reserved */ +# define LM_RESERVED_69 (69) /* Vector 69: Reserved */ + +# define LM_RESERVED_70 (70) /* Vector 70: Reserved */ + +# define NR_IRQS (60) /* (Really less because of reserved vectors) */ +#else +# error "IRQ Numbers not specified for this Stellaris chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_LM_LM3S_IRQ_H */ + diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h b/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h new file mode 100644 index 000000000..58447793d --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h @@ -0,0 +1,439 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_vectors.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Vectors + ************************************************************************************/ + +/* This file is included by lm_vectors.S. It provides the macro VECTOR that + * supplies ach Stellaris vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/lm/lm3s_irq.h. + * lm_vectors.S will define the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 71 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 71 + +#else + +VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ +VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ +VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ +VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ + +VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ +VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ +VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ +VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ +VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ +UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */ +UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */ +UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */ +UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */ +UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */ + +VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ +VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ +VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ +VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ +VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ +VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ +VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ +VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ +VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ +VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ + +VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ +VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ +VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ +UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ +VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ +VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ +VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ +VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ +VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */ +UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ + +VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */ +VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ +VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ +VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ +UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */ +UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ +UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ +UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ +VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ +VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ + +UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ +UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ +UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ +UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ +UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ +UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ +UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ +UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ +UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ +UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ + +UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ +#endif + +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 71 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 71 + +#else + +VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ +VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ +VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ +VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ + +VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ +VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ +VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ +VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ +VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ +UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */ +VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ +UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */ +UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */ +UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */ + +VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ +VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ +VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ +VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ +VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ +VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ +VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ +VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ +VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ +VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ + +VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ +VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ +VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ +UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ +VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ +VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ +VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ +VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ +UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ +UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ + +UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ +UNUSED(LM_RESERVED_51) /* Vector 51: Reserved */ +UNUSED(LM_RESERVED_52) /* Vector 52: Reserved */ +UNUSED(LM_RESERVED_53) /* Vector 53: Reserved */ +UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */ +UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ +UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ +UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ +VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ +UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */ + +UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ +UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ +UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ +UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ +UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ +UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ +UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ +UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ +UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ +UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ + +UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ +#endif + +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 71 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 71 + +#else + +VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ +VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ +VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ +VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ + +VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ +VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ +VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ +VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ +VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ +VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ +VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ +VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ +VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ +VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ + +VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ +VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ +VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ +VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ +VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ +VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ +VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ +VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ +VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ +VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ + +VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ +VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ +VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ +UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ +VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ +VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ +VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ +VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ +UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ +VECTOR(lm_uart2, LM_IRQ_UART1) /* Vector 49: UART 1 */ + +UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ +VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ +VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ +VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ +VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ +UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ +UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ +UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ +VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ +VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ + +UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ +UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ +UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ +UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ +UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ +UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ +UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ +UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ +UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ +UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ + +UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ +#endif + +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 71 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 71 + +#else + +VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ +VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ +VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ +VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ + +VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ +VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ +VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ +VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ +VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ +VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ +VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ +VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ +VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ +VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ + +VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ +VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ +VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ +VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ +VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ +VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ +VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ +VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ +VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ +VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ + +VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ +VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ +UNUSED(LM_RESERVED_42) /* Vector 42: Reserved */ +UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ +VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ +VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ +VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ +VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ +UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ +UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ + +UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ +VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ +VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ +VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ +VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ +VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */ +UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ +UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ +VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ +VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ + +UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ +UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ +UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ +UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ +UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ +UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ +UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ +UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ +UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ +UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ + +UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ +#endif + +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 72 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 72 + +#else + +VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ +VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ +VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ +VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ +VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ + +VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ +VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ +VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ +VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ +VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ +VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ +VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ +VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ +VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ + +VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ +VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ +VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ +VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ +VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ +VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ +VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ +VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ +VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ +VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ + +VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ +VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ +VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ +VECTOR(lm_cmp2, LM_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */ +VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ +VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ +VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ +VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ +VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */ +VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 49: UART 2 */ + +VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: GPIO Port H */ +VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ +VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ +VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ +VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ +VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */ +VECTOR(lm_can1, LM_IRQ_CAN1) /* Vector 56: CAN 1 */ +UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ +VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ +UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */ + +VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */ +VECTOR(lm_pwm3, LM_IRQ_PWM3) /* Vector 61: PWM 3 */ +VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */ +VECTOR(lm_udmaerror, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */ +VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */ +VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */ +VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */ +VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */ +VECTOR(lm_i2s0, LM_IRQ_I2S0) /* Vector 68: I2S 0 */ +VECTOR(lm_epi, LM_IRQ_EPI) /* Vector 69: EPI */ + +VECTOR(lm_gpioj, LM_IRQ_GPIOJ) /* Vector 70: GPIO Port J */ +UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */ +#endif + +#else +# error "Vectors not specified for this Stellaris chip" +#endif diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h index 530ecdf64..d8257fc02 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h +++ b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h @@ -44,8 +44,10 @@ /* Include the memory map file for the specific Stellaris chip */ -#ifdef CONFIG_ARCH_CHIP_LM3S +#if defined(CONFIG_ARCH_CHIP_LM3S) # include "chip/lm3s_memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_LM4F) +# include "chip/lm4f_memorymap.h" #else # error "Unsupported Stellaris memory map" #endif diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h index 311d6fcdc..00b42e73b 100644 --- a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h +++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h @@ -44,8 +44,10 @@ /* Include the pin mapping file for the specific Stellaris chip */ -#ifdef CONFIG_ARCH_CHIP_LM3S +#if defined(CONFIG_ARCH_CHIP_LM3S) # include "chip/lm3s_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_LM4F) +# include "chip/lm4f_pinmap.h" #else # error "Unsupported Stellaris PIN mapping" #endif diff --git a/nuttx/arch/arm/src/lm/chip/lm_vectors.h b/nuttx/arch/arm/src/lm/chip/lm_vectors.h new file mode 100644 index 000000000..97227bf29 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_vectors.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/* Include the vector file for the specific Stellaris chip */ + +#if defined(CONFIG_ARCH_CHIP_LM3S) +# include "chip/lm3s_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_LM4F) +# include "chip/lm4f_vectors.h" +#else +# error "Unsupported Stellaris vector file" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S index fecff0428..d3798fbb7 100644 --- a/nuttx/arch/arm/src/lm/lm_vectors.S +++ b/nuttx/arch/arm/src/lm/lm_vectors.S @@ -127,290 +127,15 @@ lm_vectors: /* External Interrupts */ -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - .word lm_gpioa /* Vector 16: GPIO Port A */ - .word lm_gpiob /* Vector 17: GPIO Port B */ - .word lm_gpioc /* Vector 18: GPIO Port C */ - .word lm_gpiod /* Vector 19: GPIO Port D */ - .word lm_gpioe /* Vector 20: GPIO Port E */ - .word lm_uart0 /* Vector 21: UART 0 */ - .word lm_uart1 /* Vector 22: UART 1 */ - .word lm_ssi0 /* Vector 23: SSI 0 */ - .word lm_i2c0 /* Vector 24: I2C 0 */ - .word lm_reserved /* Vector 25: Reserved */ - .word lm_reserved /* Vector 26: Reserved */ - .word lm_reserved /* Vector 27: Reserved */ - .word lm_reserved /* Vector 28: Reserved */ - .word lm_reserved /* Vector 29: Reserved */ - .word lm_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm_wdog /* Vector 34: Watchdog Timer */ - .word lm_tmr0a /* Vector 35: Timer 0 A */ - .word lm_tmr0b /* Vector 36: Timer 0 B */ - .word lm_tmr1a /* Vector 37: Timer 1 A */ - .word lm_tmr1b /* Vector 38: Timer 1 B */ - .word lm_tmr2a /* Vector 39: Timer 2 A */ - .word lm_tmr2b /* Vector 40: Timer 3 B */ - .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm_reserved /* Vector 43: Reserved */ - .word lm_syscon /* Vector 44: System Control */ - .word lm_flashcon /* Vector 45: FLASH Control */ - .word lm_gpiof /* Vector 46: GPIO Port F */ - .word lm_gpiog /* Vector 47: GPIO Port G */ - .word lm_gpioh /* Vector 48: GPIO Port H */ - .word lm_reserved /* Vector 49: Reserved */ - .word lm_ssi1 /* Vector 50: SSI 1 */ - .word lm_tmr3a /* Vector 51: Timer 3 A */ - .word lm_tmr3b /* Vector 52: Timer 3 B */ - .word lm_i2c1 /* Vector 53: I2C 1 */ - .word lm_reserved /* Vector 54: Reserved */ - .word lm_reserved /* Vector 55: Reserved */ - .word lm_reserved /* Vector 56: Reserved */ - .word lm_reserved /* Vector 57: Reserved */ - .word lm_eth /* Vector 58: Ethernet Controller */ - .word lm_hib /* Vector 59: Hibernation Module */ - .word lm_reserved /* Vector 60: Reserved */ - .word lm_reserved /* Vector 61: Reserved */ - .word lm_reserved /* Vector 62: Reserved */ - .word lm_reserved /* Vector 63: Reserved */ - .word lm_reserved /* Vector 64: Reserved */ - .word lm_reserved /* Vector 65: Reserved */ - .word lm_reserved /* Vector 66: Reserved */ - .word lm_reserved /* Vector 67: Reserved */ - .word lm_reserved /* Vector 68: Reserved */ - .word lm_reserved /* Vector 69: Reserved */ - .word lm_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - .word lm_gpioa /* Vector 16: GPIO Port A */ - .word lm_gpiob /* Vector 17: GPIO Port B */ - .word lm_gpioc /* Vector 18: GPIO Port C */ - .word lm_gpiod /* Vector 19: GPIO Port D */ - .word lm_gpioe /* Vector 20: GPIO Port E */ - .word lm_uart0 /* Vector 21: UART 0 */ - .word lm_uart1 /* Vector 22: UART 1 */ - .word lm_ssi0 /* Vector 23: SSI 0 */ - .word lm_i2c0 /* Vector 24: I2C 0 */ - .word lm_reserved /* Vector 25: Reserved */ - .word lm_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm_reserved /* Vector 27: Reserved */ - .word lm_reserved /* Vector 28: Reserved */ - .word lm_reserved /* Vector 29: Reserved */ - .word lm_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm_wdog /* Vector 34: Watchdog Timer */ - .word lm_tmr0a /* Vector 35: Timer 0 A */ - .word lm_tmr0b /* Vector 36: Timer 0 B */ - .word lm_tmr1a /* Vector 37: Timer 1 A */ - .word lm_tmr1b /* Vector 38: Timer 1 B */ - .word lm_tmr2a /* Vector 39: Timer 2 A */ - .word lm_tmr2b /* Vector 40: Timer 3 B */ - .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm_reserved /* Vector 43: Reserved */ - .word lm_syscon /* Vector 44: System Control */ - .word lm_flashcon /* Vector 45: FLASH Control */ - .word lm_gpiof /* Vector 46: GPIO Port F */ - .word lm_gpiog /* Vector 47: GPIO Port G */ - .word lm_reserved /* Vector 48: Reserved */ - .word lm_reserved /* Vector 49: Reserved */ - .word lm_reserved /* Vector 50: Reserved */ - .word lm_reserved /* Vector 51: Reserved */ - .word lm_reserved /* Vector 52: Reserved */ - .word lm_reserved /* Vector 53: Reserved */ - .word lm_reserved /* Vector 54: Reserved */ - .word lm_reserved /* Vector 55: Reserved */ - .word lm_reserved /* Vector 56: Reserved */ - .word lm_reserved /* Vector 57: Reserved */ - .word lm_eth /* Vector 58: Ethernet Controller */ - .word lm_reserved /* Vector 59: Reserved */ - .word lm_reserved /* Vector 60: Reserved */ - .word lm_reserved /* Vector 61: Reserved */ - .word lm_reserved /* Vector 62: Reserved */ - .word lm_reserved /* Vector 63: Reserved */ - .word lm_reserved /* Vector 64: Reserved */ - .word lm_reserved /* Vector 65: Reserved */ - .word lm_reserved /* Vector 66: Reserved */ - .word lm_reserved /* Vector 67: Reserved */ - .word lm_reserved /* Vector 68: Reserved */ - .word lm_reserved /* Vector 69: Reserved */ - .word lm_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - .word lm_gpioa /* Vector 16: GPIO Port A */ - .word lm_gpiob /* Vector 17: GPIO Port B */ - .word lm_gpioc /* Vector 18: GPIO Port C */ - .word lm_gpiod /* Vector 19: GPIO Port D */ - .word lm_gpioe /* Vector 20: GPIO Port E */ - .word lm_uart0 /* Vector 21: UART 0 */ - .word lm_uart1 /* Vector 22: UART 1 */ - .word lm_ssi0 /* Vector 23: SSI 0 */ - .word lm_i2c0 /* Vector 24: I2C 0 */ - .word lm_pwmfault /* Vector 25: PWM Fault */ - .word lm_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm_qei0 /* Vector 29: QEI0 */ - .word lm_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm_wdog /* Vector 34: Watchdog Timer */ - .word lm_tmr0a /* Vector 35: Timer 0 A */ - .word lm_tmr0b /* Vector 36: Timer 0 B */ - .word lm_tmr1a /* Vector 37: Timer 1 A */ - .word lm_tmr1b /* Vector 38: Timer 1 B */ - .word lm_tmr2a /* Vector 39: Timer 2 A */ - .word lm_tmr2b /* Vector 40: Timer 3 B */ - .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm_reserved /* Vector 43: Reserved */ - .word lm_syscon /* Vector 44: System Control */ - .word lm_flashcon /* Vector 45: FLASH Control */ - .word lm_gpiof /* Vector 46: GPIO Port F */ - .word lm_gpiog /* Vector 47: GPIO Port G */ - .word lm_reserved /* Vector 48: Reserved */ - .word lm_uart2 /* Vector 49: UART 2 */ - .word lm_reserved /* Vector 50: Reserved */ - .word lm_tmr3a /* Vector 51: Timer 3 A */ - .word lm_tmr3b /* Vector 52: Timer 3 B */ - .word lm_i2c1 /* Vector 53: I2C 1 */ - .word lm_qei1 /* Vector 54: QEI1 */ - .word lm_reserved /* Vector 55: Reserved */ - .word lm_reserved /* Vector 56: Reserved */ - .word lm_reserved /* Vector 57: Reserved */ - .word lm_eth /* Vector 58: Ethernet Controller */ - .word lm_hib /* Vector 59: Hibernation Module */ - .word lm_reserved /* Vector 60: Reserved */ - .word lm_reserved /* Vector 61: Reserved */ - .word lm_reserved /* Vector 62: Reserved */ - .word lm_reserved /* Vector 63: Reserved */ - .word lm_reserved /* Vector 64: Reserved */ - .word lm_reserved /* Vector 65: Reserved */ - .word lm_reserved /* Vector 66: Reserved */ - .word lm_reserved /* Vector 67: Reserved */ - .word lm_reserved /* Vector 68: Reserved */ - .word lm_reserved /* Vector 69: Reserved */ - .word lm_reserved /* Vector 70: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - .word lm_gpioa /* Vector 16: GPIO Port A */ - .word lm_gpiob /* Vector 17: GPIO Port B */ - .word lm_gpioc /* Vector 18: GPIO Port C */ - .word lm_gpiod /* Vector 19: GPIO Port D */ - .word lm_gpioe /* Vector 20: GPIO Port E */ - .word lm_uart0 /* Vector 21: UART 0 */ - .word lm_uart1 /* Vector 22: UART 1 */ - .word lm_ssi0 /* Vector 23: SSI 0 */ - .word lm_i2c0 /* Vector 24: I2C 0 */ - .word lm_pwmfault /* Vector 25: PWM Fault */ - .word lm_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm_qei0 /* Vector 29: QEI0 */ - .word lm_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm_wdog /* Vector 34: Watchdog Timer */ - .word lm_tmr0a /* Vector 35: Timer 0 A */ - .word lm_tmr0b /* Vector 36: Timer 0 B */ - .word lm_tmr1a /* Vector 37: Timer 1 A */ - .word lm_tmr1b /* Vector 38: Timer 1 B */ - .word lm_tmr2a /* Vector 39: Timer 2 A */ - .word lm_tmr2b /* Vector 40: Timer 3 B */ - .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm_cmp1 /* Vector 42: Analog Comparator 1 */ - .word lm_cmp2 /* Vector 43: Reserved */ - .word lm_syscon /* Vector 44: System Control */ - .word lm_flashcon /* Vector 45: FLASH Control */ - .word lm_gpiof /* Vector 46: GPIO Port F */ - .word lm_gpiog /* Vector 47: GPIO Port G */ - .word lm_gpioh /* Vector 48: GPIO Port H */ - .word lm_uart2 /* Vector 49: UART 2 */ - .word lm_ssi1 /* Vector 50: SSI 1 */ - .word lm_tmr3a /* Vector 51: Timer 3 A */ - .word lm_tmr3b /* Vector 52: Timer 3 B */ - .word lm_i2c1 /* Vector 53: I2C 1 */ - .word lm_qei1 /* Vector 54: QEI1 */ - .word lm_can0 /* Vector 55: CAN 0 */ - .word lm_can1 /* Vector 56: CAN 1 */ - .word lm_reserved /* Vector 57: Reserved */ - .word lm_eth /* Vector 58: Ethernet Controller */ - .word lm_reserved /* Vector 59: Reserved */ - .word lm_usb /* Vector 60: USB */ - .word lm_pwm3 /* Vector 61: PWM 3 */ - .word lm_udmasoft /* Vector 62: uDMA Software */ - .word lm_udmaerror /* Vector 63: uDMA Error */ - .word lm_adc1_0 /* Vector 64: ADC1 Sequence 0 */ - .word lm_adc1_1 /* Vector 65: ADC1 Sequence 1 */ - .word lm_adc1_2 /* Vector 66: ADC1 Sequence 2 */ - .word lm_adc1_3 /* Vector 67: ADC1 Sequence 3 */ - .word lm_i2s0 /* Vector 68: I2S 0 */ - .word lm_epi /* Vector 69: Reserved */ - .word lm_gpioj /* Vector 70: GPIO J */ - .word lm_reserved /* Vector 71: Reserved */ - #elif defined(CONFIG_ARCH_CHIP_LM3S8962) - .word lm_gpioa /* Vector 16: GPIO Port A */ - .word lm_gpiob /* Vector 17: GPIO Port B */ - .word lm_gpioc /* Vector 18: GPIO Port C */ - .word lm_gpiod /* Vector 19: GPIO Port D */ - .word lm_gpioe /* Vector 20: GPIO Port E */ - .word lm_uart0 /* Vector 21: UART 0 */ - .word lm_uart1 /* Vector 22: UART 1 */ - .word lm_ssi0 /* Vector 23: SSI 0 */ - .word lm_i2c0 /* Vector 24: I2C 0 */ - .word lm_pwmfault /* Vector 25: PWM Fault */ - .word lm_pwm0 /* Vector 26: PWM Generator 0 */ - .word lm_pwm1 /* Vector 27: PWM Generator 1 */ - .word lm_pwm2 /* Vector 28: PWM Generator 2 */ - .word lm_qei0 /* Vector 29: QEI0 */ - .word lm_adc0 /* Vector 30: ADC Sequence 0 */ - .word lm_adc1 /* Vector 31: ADC Sequence 1 */ - .word lm_adc2 /* Vector 32: ADC Sequence 2 */ - .word lm_adc3 /* Vector 33: ADC Sequence 3 */ - .word lm_wdog /* Vector 34: Watchdog Timer */ - .word lm_tmr0a /* Vector 35: Timer 0 A */ - .word lm_tmr0b /* Vector 36: Timer 0 B */ - .word lm_tmr1a /* Vector 37: Timer 1 A */ - .word lm_tmr1b /* Vector 38: Timer 1 B */ - .word lm_tmr2a /* Vector 39: Timer 2 A */ - .word lm_tmr2b /* Vector 40: Timer 3 B */ - .word lm_cmp0 /* Vector 41: Analog Comparator 0 */ - .word lm_reserved /* Vector 42: Reserved */ - .word lm_reserved /* Vector 43: Reserved */ - .word lm_syscon /* Vector 44: System Control */ - .word lm_flashcon /* Vector 45: FLASH Control */ - .word lm_gpiof /* Vector 46: GPIO Port F */ - .word lm_gpiog /* Vector 47: GPIO Port G */ - .word lm_reserved /* Vector 48: Reserved */ - .word lm_reserved /* Vector 49: Reserved */ - .word lm_reserved /* Vector 50: Reserved */ - .word lm_tmr3a /* Vector 51: Timer 3 A */ - .word lm_tmr3b /* Vector 52: Timer 3 B */ - .word lm_reserved /* Vector 53: Reserved*/ - .word lm_qei1 /* Vector 54: QEI1 */ - .word lm_can0 /* Vector 55: Can Controller */ - .word lm_reserved /* Vector 56: Reserved */ - .word lm_reserved /* Vector 57: Reserved */ - .word lm_eth /* Vector 58: Ethernet Controller */ - .word lm_hib /* Vector 59: Hibernation Module */ - .word lm_reserved /* Vector 60: Reserved */ - .word lm_reserved /* Vector 61: Reserved */ - .word lm_reserved /* Vector 62: Reserved */ - .word lm_reserved /* Vector 63: Reserved */ - .word lm_reserved /* Vector 64: Reserved */ - .word lm_reserved /* Vector 65: Reserved */ - .word lm_reserved /* Vector 66: Reserved */ - .word lm_reserved /* Vector 67: Reserved */ - .word lm_reserved /* Vector 68: Reserved */ - .word lm_reserved /* Vector 69: Reserved */ - .word lm_reserved /* Vector 70: Reserved */ -#else -# error "Vectors not specified for this LM3S chip" -#endif +/* External Interrupts */ + +#undef VECTOR +#define VECTOR(l,i) .word l + +#undef UNUSED +#define UNUSED(i) .word lm_reserved + +#include "chip/chip/lm_vectors.h" .size lm_vectors, .-lm_vectors /************************************************************************************ @@ -432,204 +157,13 @@ handlers: HANDLER lm_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */ HANDLER lm_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */ -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: SSI 1 */ - HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) - HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */ - HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */ - HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */ - HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */ - HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */ - HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */ - HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */ - HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */ - HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */ - HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */ - HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */ - HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ - HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ - HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ - HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */ - HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ - HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ - HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ - HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ - HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */ - HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */ - HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */ - HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */ - HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */ - HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */ - HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */ - HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ - HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ - HANDLER lm_cmp2, LM_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ - HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */ - HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */ - HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */ - HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */ - HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */ - HANDLER lm_uart2, LM_IRQ_UART2 /* Vector 49: UART 2 */ - HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: GPIO Port H */ - HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */ - HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */ - HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */ - HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */ - HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */ - HANDLER lm_can1, LM_IRQ_CAN1 /* Vector 56: CAN 1 */ - HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */ - HANDLER lm_usb, LM_IRQ_USB /* Vector 60: USB */ - HANDLER lm_pwm3, LM_IRQ_PWM3 /* Vector 61: PWM 3 */ - HANDLER lm_udmasoft, LM_IRQ_UDMASOFT /* Vector 62: uDMA Software */ - HANDLER lm_udmaerror, LM_IRQ_UDMAERROR /* Vector 63: uDMA Error */ - HANDLER lm_adc1_0, LM_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ - HANDLER lm_adc1_1, LM_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ - HANDLER lm_adc1_2, LM_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ - HANDLER lm_adc1_3, LM_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ - HANDLER lm_i2s0, LM_IRQ_I2S0 /* Vector 68: I2S 0 */ - HANDLER lm_epi, LM_IRQ_EPI /* Vector 69: EPI */ - HANDLER lm_gpioj, LM_IRQ_GPIOJ /* Vector 70: GPIO Port J */ -#else -# error "Vectors not specified for this Stellaris chip" -#endif +#undef VECTOR +#define VECTOR(l,i) HANDLER l, i + +#undef UNUSED +#define UNUSED(i) + +#include "chip/chip/lm_vectors.h" /* Common IRQ handling logic. On entry here, the return stack is on either * the PSP or the MSP and looks like the following: -- cgit v1.2.3 From 44fdf6fc7a8188577cc968233b3ee123e688ab71 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 9 Jan 2013 21:31:36 +0000 Subject: Add file action logic which will eventually be needed to support posix_spawn() git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5500 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 1 + nuttx/configs/sim/ostest/defconfig | 14 +++- nuttx/include/spawn.h | 28 +++++--- nuttx/libc/spawn/Make.defs | 3 +- nuttx/libc/spawn/lib_psfa_addaction.c | 91 +++++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_addclose.c | 100 ++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_adddup2.c | 104 +++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_addopen.c | 119 +++++++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_destroy.c | 96 +++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_init.c | 70 ++++++++++++++++++++ nuttx/libc/spawn/spawn.h | 121 ++++++++++++++++++++++++++++++++++ 11 files changed, 735 insertions(+), 12 deletions(-) create mode 100644 nuttx/libc/spawn/lib_psfa_addaction.c create mode 100644 nuttx/libc/spawn/lib_psfa_addclose.c create mode 100644 nuttx/libc/spawn/lib_psfa_adddup2.c create mode 100644 nuttx/libc/spawn/lib_psfa_addopen.c create mode 100644 nuttx/libc/spawn/lib_psfa_destroy.c create mode 100644 nuttx/libc/spawn/lib_psfa_init.c create mode 100644 nuttx/libc/spawn/spawn.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 35bf42253..3d124073b 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3896,4 +3896,5 @@ * arch/arm/src/lm: Rename the arch/arm/src/lm3s directory to arch/arm/src/lm so that is can support other members of the Stellaris family. + * libc/spawn: Add file action interfaces needed by posix_spawn(). diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index 55687c366..43d78e6a2 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -90,6 +90,7 @@ CONFIG_BOARD_LOOPSPERMSEC=100 # CONFIG_ARCH_IRQPRIO is not set # CONFIG_CUSTOM_STACK is not set # CONFIG_ADDRENV is not set +# CONFIG_ARCH_HAVE_VFORK is not set # CONFIG_ARCH_STACKDUMP is not set # CONFIG_ENDIAN_BIG is not set @@ -266,6 +267,10 @@ CONFIG_MM_REGIONS=1 # # Library Routines # + +# +# Standard C Library Options +# CONFIG_STDIO_BUFFER_SIZE=1024 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=2 @@ -277,6 +282,7 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y @@ -284,6 +290,11 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + # # Basic CXX Support # @@ -295,7 +306,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # -# Named Applications +# Built-In Applications # # CONFIG_BUILTIN is not set @@ -356,7 +367,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_USBMSC is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WLAN is not set # # Interpreters diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index 3463670b5..d453fb582 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -33,14 +33,16 @@ * ****************************************************************************/ -#ifndef __INCLUDE_LIBGEN_H -#define __INCLUDE_LIBGEN_H +#ifndef __INCLUDE_SPAWN_H +#define __INCLUDE_SPAWN_H /**************************************************************************** * Included Files ****************************************************************************/ #include + +#include #include /**************************************************************************** @@ -67,15 +69,23 @@ struct posix_spawnattr_s { -/* To be provided */ + uint8_t flags; + uint8_t priority; + pid_t group; + sigset_t sigset; }; + typedef struct posix_spawnattr_s posix_spawnattr_t; -struct posix_spawn_file_actions_s -{ -/* To be provided */ -}; -typedef struct posix_spawn_file_actions_s posix_spawn_file_actions_t; +/* posix_spawn_file_actions_addclose(), posix_spawn_file_actions_adddup2(), + * and posix_spawn_file_actions_addopen() will allocate memory and append + * a new file action to an instance of posix_spawn_file_actions_t. The + * internal representation of these structures is not exposed to the user. + * The user need only know that the size sizeof(posix_spawn_file_actions_t) + * will hold a pointer to data. + */ + +typedef FAR void *posix_spawn_file_actions_t; /**************************************************************************** * Public Function Prototypes @@ -134,4 +144,4 @@ int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *, } #endif -#endif /* __INCLUDE_LIBGEN_H */ +#endif /* __INCLUDE_SPAWN_H */ diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 17d9f393a..0952fda47 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -37,7 +37,8 @@ ifeq ($(CONFIG_LIBC_EXECFUNCS),y) -CSRCS += +CSRCS += lib_psfa_addaction.c lib_psfa_addclose.c lib_psfa_adddup2.c +CSRCS += lib_psfa_addopen.c lib_psfa_destroy.c lib_psfa_init.c # Add the spawn directory to the build diff --git a/nuttx/libc/spawn/lib_psfa_addaction.c b/nuttx/libc/spawn/lib_psfa_addaction.c new file mode 100644 index 000000000..3f297d7cf --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_addaction.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * libc/string/lib_psfa_addaction.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: add_file_action + * + * Description: + * Add the file action to the end for the file action list. + * + * Input Parameters: + * file_actions - The head of the file action list. + * entry - The file action to be added + * + * Returned Value: + * None + * + ****************************************************************************/ + +void add_file_action(FAR posix_spawn_file_actions_t *file_actions, + FAR struct spawn_general_file_action_s *entry) +{ + FAR struct spawn_general_file_action_s *prev; + FAR struct spawn_general_file_action_s *next; + + /* Find the end of the list */ + + for (prev = NULL, next = (FAR struct spawn_general_file_action_s *)*file_actions; + next; + prev = next, next = next->flink); + + /* Here next is NULL and prev points to the last entry in the list (or + * is NULL if the list is empty). + */ + + if (prev) + { + prev->flink = entry; + } + else + { + *file_actions = (posix_spawn_file_actions_t)entry; + } + + entry->flink = NULL; +} diff --git a/nuttx/libc/spawn/lib_psfa_addclose.c b/nuttx/libc/spawn/lib_psfa_addclose.c new file mode 100644 index 000000000..225885cb1 --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_addclose.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * libc/string/lib_psfa_addclose.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn_file_actions_addclose + * + * Description: + * The posix_spawn_file_actions_addclose() function adds a close operation + * to the list of operations associated with the object referenced by + * file_actions, for subsequent use in a call to posix_spawn(2) or + * posix_spawnp(2). The descriptor referred to by fd is closed as if + * close() had been called on it prior to the new child process starting + * execution. + * + * Input Parameters: + * file_actions - The posix_spawn_file_actions_t to append the action. + * fd - The file descriptor to be closed. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actions, + int fd) +{ + FAR struct spawn_close_file_action_s *entry; + + DEBUGASSERT(file_actions && fd >= 0 && fd < CONFIG_NFILE_DESCRIPTORS); + + /* Allocate the action list entry */ + + entry = (FAR struct spawn_close_file_action_s *) + zalloc(sizeof(struct spawn_close_file_action_s)); + + if (!entry) + { + return ENOMEM; + } + + /* Initialize the file action entry */ + + entry->action = SPAWN_FILE_ACTION_CLOSE; + entry->fd = fd; + + /* And add it to the file action list */ + + add_file_action(file_actions, (FAR struct spawn_general_file_action_s *)entry); + return OK; +} diff --git a/nuttx/libc/spawn/lib_psfa_adddup2.c b/nuttx/libc/spawn/lib_psfa_adddup2.c new file mode 100644 index 000000000..966f456af --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_adddup2.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * libc/string/lib_psfa_adddup2.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn_file_actions_adddup2 + * + * Description: + * The posix_spawn_file_actions_adddup2() function adds a dup2 operation to + * the list of operations associated with the object referenced by + * file_actions, for subsequent use in a call to posix_spawn(2) or + * posix_spawnp(2). The descriptor referred to by fd2 is created as + * if dup2() had been called on fd1 prior to the new child process + * starting execution. + * + * Input Parameters: + * file_actions - The posix_spawn_file_actions_t to append the action. + * fd1 - The first file descriptor to be argument to dup2. + * fd2 - The first file descriptor to be argument to dup2. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_actions, + int fd1, int fd2) +{ + FAR struct spawn_dup2_file_action_s *entry; + + DEBUGASSERT(file_actions && + fd1 >= 0 && fd1 < CONFIG_NFILE_DESCRIPTORS && + fd2 >= 0 && fd2 < CONFIG_NFILE_DESCRIPTORS); + + /* Allocate the action list entry */ + + entry = (FAR struct spawn_dup2_file_action_s *) + zalloc(sizeof(struct spawn_close_file_action_s)); + + if (!entry) + { + return ENOMEM; + } + + /* Initialize the file action entry */ + + entry->action = SPAWN_FILE_ACTION_DUP2; + entry->fd1 = fd1; + entry->fd2 = fd2; + + /* And add it to the file action list */ + + add_file_action(file_actions, (FAR struct spawn_general_file_action_s *)entry); + return OK; +} diff --git a/nuttx/libc/spawn/lib_psfa_addopen.c b/nuttx/libc/spawn/lib_psfa_addopen.c new file mode 100644 index 000000000..bcb201291 --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_addopen.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * libc/string/lib_psfa_addopen.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn_file_actions_addopen + * + * Description: + * The posix_spawn_file_actions_addopen() function adds an open operation + * to the list of operations associated with the object referenced by + * file_actions, for subsequent use in a call to posix_spawn(2) or + * posix_spawnp(2). The descriptor referred to by fd is opened using + * the path, oflag, and mode arguments as if open() had been called on it + * prior to the new child process starting execution. The string path is + * copied by the posix_spawn_file_actions_addopen() function during this + * process, so storage need not be persistent in the caller. + * + * Input Parameters: + * file_actions - The posix_spawn_file_actions_t to append the action. + * fd - The path to be opened. + * path - The first file descriptor to be argument to dup2. + * oflags - Open flags + * mode - File creation mode + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_actions, + int fd, FAR const char *path, int oflags, + mode_t mode) +{ + FAR struct spawn_open_file_action_s *entry; + size_t len; + size_t alloc; + + DEBUGASSERT(file_actions && path && + fd >= 0 && fd < CONFIG_NFILE_DESCRIPTORS); + + /* Get the size of the action including storage for the path plus its NUL + * terminating character. + */ + + len = strlen(path); + alloc = SIZEOF_OPEN_FILE_ACTION_S(len); + + /* Allocate the action list entry of this size */ + + entry = (FAR struct spawn_open_file_action_s *)zalloc(alloc); + + if (!entry) + { + return ENOMEM; + } + + /* Initialize the file action entry */ + + entry->action = SPAWN_FILE_ACTION_OPEN; + entry->fd = fd; + entry->oflags = oflags; + entry->mode = mode; + strncpy(entry->path, path, len+1); + + /* And add it to the file action list */ + + add_file_action(file_actions, (FAR struct spawn_general_file_action_s *)entry); + return OK; +} diff --git a/nuttx/libc/spawn/lib_psfa_destroy.c b/nuttx/libc/spawn/lib_psfa_destroy.c new file mode 100644 index 000000000..5d0a644d8 --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_destroy.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * libc/string/lib_psfa_destroy.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn_file_actions_destroy + * + * Description: + * The posix_spawn_file_actions_destroy() function destroys the object + * referenced by file_actions which was previously intialized by + * posix_spawn_file_actions_init(), returning any resources obtained at the + * time of initialization to the system for subsequent reuse. A + * posix_spawn_file_actions_t may be reinitialized after having been + * destroyed, but must not be reused after destruction, unless it has been + * reinitialized. + * + * Input Parameters: + * file_actions - The posix_spawn_file_actions_t to be destroyed. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_actions) +{ + FAR struct spawn_general_file_action_s *curr; + FAR struct spawn_general_file_action_s *next; + + DEBUGASSERT(file_actions); + + /* Destroy each file action, one at a time */ + + for (curr = (FAR struct spawn_general_file_action_s *)*file_actions; + curr; + curr = next) + { + /* Get the pointer to the next element before destroying the current one */ + + next = curr->flink; + free(curr); + } + + /* Mark the list empty */ + + *file_actions = NULL; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psfa_init.c b/nuttx/libc/spawn/lib_psfa_init.c new file mode 100644 index 000000000..860045b52 --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_init.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * libc/string/lib_psfa_init.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn_file_actions_init + * + * Description: + * The posix_spawn_file_actions_init() function initializes the object + * referenced by file_actions, to an empty set of file actions for + * subsequent use in a call to posix_spawn(2) or posix_spawnp(2). + * + * Input Parameters: + * file_actions - The address of the posix_spawn_file_actions_t to be + * initialized. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions) +{ + file_actions = NULL; + return OK; +} diff --git a/nuttx/libc/spawn/spawn.h b/nuttx/libc/spawn/spawn.h new file mode 100644 index 000000000..5d0159ff2 --- /dev/null +++ b/nuttx/libc/spawn/spawn.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * libc/spawn/spawn.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __LIBC_SPAWN_SPAWN_H +#define __LIBC_SPAWN_SPAWN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ +/* This enumerator identifies a file action */ + +enum spawn_file_actions_e +{ + SPAWN_FILE_ACTION_NONE = 0, + SPAWN_FILE_ACTION_CLOSE, + SPAWN_FILE_ACTION_DUP2, + SPAWN_FILE_ACTION_OPEN +}; + +/* posix_spawn_file_actions_addclose(), posix_spawn_file_actions_adddup2(), + * and posix_spawn_file_actions_addopen() will allocate memory and append + * a new file action to an instance of posix_spawn_file_actions_t. The + * internal representation of these structures are defined below: + */ + +struct spawn_general_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* A member of enum spawn_file_actions_e */ +}; + +struct spawn_close_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_CLOSE */ + int fd; /* The file descriptor to close */ +}; + +struct spawn_dup2_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_DUP2 */ + int fd1; /* The first file descriptor for dup2() */ + int fd2; /* The second file descriptor for dup2() */ +}; + +struct spawn_open_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_OPEN */ + int fd; /* The file descriptor after opening */ + int oflags; /* Open flags */ + mode_t mode; /* File creation mode */ + char path[1]; /* Start of the path to be + * opened */ +}; + +#define SIZEOF_OPEN_FILE_ACTION_S(n) \ + (sizeof(struct spawn_open_file_action_s) + (n)) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +void add_file_action(FAR posix_spawn_file_actions_t *file_action, + FAR struct spawn_general_file_action_s *entry); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIBC_SPAWN_SPAWN_H */ -- cgit v1.2.3 From 5ac907eb398c40e4aaecf788d6c9e473eac051a0 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 00:45:11 +0000 Subject: Add spawn attribute logic which will eventually be needed to support posix_spawn() git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5501 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/Documentation/NuttX.html | 14 ++-- nuttx/README.txt | 12 ++-- nuttx/configs/stm32f4discovery/README.txt | 4 +- nuttx/include/spawn.h | 37 +++++++++-- nuttx/libc/spawn/Make.defs | 5 ++ nuttx/libc/spawn/lib_psa_getflags.c | 72 +++++++++++++++++++++ nuttx/libc/spawn/lib_psa_getschedparam.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_getschedpolicy.c | 73 +++++++++++++++++++++ nuttx/libc/spawn/lib_psa_getsigdefault.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_getsigmask.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_init.c | 102 ++++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setflags.c | 71 +++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setschedparam.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setschedpolicy.c | 72 +++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setsigdefault.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setsigmask.c | 74 ++++++++++++++++++++++ nuttx/libc/spawn/lib_psfa_addclose.c | 4 +- nuttx/libc/spawn/lib_psfa_adddup2.c | 4 +- nuttx/libc/spawn/lib_psfa_init.c | 2 +- 19 files changed, 891 insertions(+), 25 deletions(-) create mode 100644 nuttx/libc/spawn/lib_psa_getflags.c create mode 100644 nuttx/libc/spawn/lib_psa_getschedparam.c create mode 100644 nuttx/libc/spawn/lib_psa_getschedpolicy.c create mode 100644 nuttx/libc/spawn/lib_psa_getsigdefault.c create mode 100644 nuttx/libc/spawn/lib_psa_getsigmask.c create mode 100644 nuttx/libc/spawn/lib_psa_init.c create mode 100644 nuttx/libc/spawn/lib_psa_setflags.c create mode 100644 nuttx/libc/spawn/lib_psa_setschedparam.c create mode 100644 nuttx/libc/spawn/lib_psa_setschedpolicy.c create mode 100644 nuttx/libc/spawn/lib_psa_setsigdefault.c create mode 100644 nuttx/libc/spawn/lib_psa_setsigmask.c diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 21f732c97..f6e9a41ba 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -1239,8 +1239,8 @@ svn checkout -r5447 http://svn.code.sf.net/p/nuttx/code/trunk nuttx-code

        • New top-level Makefiles: Makefile.unix and Makefile.win (along with numerous changes to other make-related files). - This adds basic support for building NuttX natively under Windows from a CMD.exe window (rather than in a POSIX-like environment). - This build: (1) Uses all Windows style paths, (2) Uses primarily Windows batch commands from CMD.exe, with (3) a few extensions from GNUWin32. + This adds basic support for building NuttX natively under from Windows console (rather than in a POSIX-like environment). + This build: (1) Uses all Windows style paths, (2) Uses primarily standard Windows batch commands with (3) a few additional commands from GNUWin32 (such as GNU make).

          This capability should still be considered a work in progress because: (1) It has not been verfied on all targets and tools, and (2) it still lacks some of the creature-comforts of the more mature environments (like a functional configure.sh script and make menuconfig support). @@ -3202,7 +3202,7 @@ avr, m68k, m68hc11, m68hc12, m9s12, blackfin, m32c, h8, and SuperH ports.

          • - Build support has been added to support building natively in a Windes CMD.exe rather than in a POSIX-like environment. + Build support has been added to support building natively in a Windows console rather than in a POSIX-like environment.

          This build: @@ -3221,10 +3221,10 @@ avr, m68k, m68hc11, m68hc12, m9s12, blackfin, m32c, h8, and SuperH ports.

          • - CMD.exe Shell. - The build must be performed in a Windows CMD.execmd shell that comes with Windows. - I prefer the ConEmu command shell which can be downloaded from: + Windows Console. + The build must be performed in a Windows console window. + This may be using the standard CMD.exe terminal that comes with Windows. + I prefer the ConEmu terminal which can be downloaded from: http://code.google.com/p/conemu-maximus5/
          • diff --git a/nuttx/README.txt b/nuttx/README.txt index 23d0e1a81..2ff473fa0 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -421,7 +421,7 @@ NuttX Configuration Tool under DOS ---------------------------------- Recent versions of NuttX support building NuttX from a native Windows - CMD.exe shell (see "Native Windows Build" below). But kconfig-frontends + console window (see "Native Windows Build" below). But kconfig-frontends is a Linux tool. There have been some successes building a Windows native version of the kconfig-frontends tool, but that is not ready for prime time. @@ -440,8 +440,8 @@ NuttX Configuration Tool under DOS restore CONFIG_WINDOWS_NATIVE=y and the correct CONFIG_APPS_DIR. 2) You can, with some effort, run the the Cygwin kconfig-mconf tool - directly in the CMD.exe shell. In this case, you do not have to - modify the .config file, but there are other complexities: + directly in the Windows console window. In this case, you do not + have to modify the .config file, but there are other complexities: a. You need to temporarily set the Cgywin directories in the PATH variable then run kconfig-mconf manually like: @@ -454,7 +454,7 @@ NuttX Configuration Tool under DOS tools/kconfig menuconfig b. There is an issue with accessing DOS environment variables from - the Cygwin kconfig-mconf running in the CMD.exe shell. The + the Cygwin kconfig-mconf running in the Windows console. The following change to the top-level Kconfig file seems to work around these problems: @@ -680,8 +680,8 @@ Native Windows Build - A few extensions from GNUWin32 In this build, you cannot use a Cygwin or MSYS shell. Rather the build must - be performed in a Windows CMD shell. Here is a better shell than than the - standard issue, CMD shell: ConEmu which can be downloaded from: + be performed in a Windows console window. Here is a better terminal than the + standard issue, CMD.exe terminal: ConEmu which can be downloaded from: http://code.google.com/p/conemu-maximus5/ Build Tools. The build still relies on some Unix-like commands. I use diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index ef61b05e6..c1d484279 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -1468,8 +1468,8 @@ Where is one of the following: - A few extensions from GNUWin32 (or MSYS is you prefer) In this build, you cannot use a Cygwin or MSYS shell. Rather the build must - be performed in a Windows CMD shell. Here is a better shell than than the - standard issue, CMD shell: ConEmu which can be downloaded from: + be performed in a Windows console. Here is a better shell than than the + standard issue, CMD.exe shell: ConEmu which can be downloaded from: http://code.google.com/p/conemu-maximus5/ CONFIG_HOST_WINDOWS=y : Windows diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index d453fb582..24b68585e 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -43,7 +43,10 @@ #include #include + +#include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -65,14 +68,18 @@ ****************************************************************************/ /* "The spawn.h header shall define the posix_spawnattr_t and * posix_spawn_file_actions_t types used in performing spawn operations. + * + * The internal structure underlying the posix_spawnattr_t is exposed here + * because the user will be required to allocate this memory. */ struct posix_spawnattr_s { uint8_t flags; uint8_t priority; - pid_t group; - sigset_t sigset; + uint8_t policy; + sigset_t sigdefault; + sigset_t sigmask; }; typedef struct posix_spawnattr_s posix_spawnattr_t; @@ -99,6 +106,8 @@ extern "C" { #endif +/* posix_spawn[p] interfaces ************************************************/ + int posix_spawn(FAR pid_t *, FAR const char *, FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, FAR char *const [], FAR char *const []); @@ -106,9 +115,14 @@ int posix_spawnp(FAR pid_t *, FAR const char *, FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, FAR char *const [], FAR char *const []); +/* File action interfaces ***************************************************/ +/* File action initialization and destruction */ + int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *); int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *); +/* Add file action interfaces */ + int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *, int); int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *, @@ -116,11 +130,22 @@ int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *, int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *, int, FAR const char *, int, mode_t); +/* Spawn attributes interfaces **********************************************/ +/* Spawn attributes initialization and destruction */ + int posix_spawnattr_init(FAR posix_spawnattr_t *); -int posix_spawnattr_destroy(FAR posix_spawnattr_t *); + +/* int posix_spawnattr_destroy(FAR posix_spawnattr_t *); */ +#ifdef CONFIG_DEBUG +# define posix_spawnattr_destroy(attr) (attr ? 0 : EINVAL) +#else +# define posix_spawnattr_destroy(attr) (0) +#endif + +/* Get spawn attributes interfaces */ int posix_spawnattr_getflags(FAR const posix_spawnattr_t *, FAR short *); -int posix_spawnattr_getpgroup(FAR const posix_spawnattr_t *, FAR pid_t *); +#define posix_spawnattr_getpgroup(attr,group) (ENOSYS) int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *, FAR struct sched_param *); int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *, @@ -130,8 +155,10 @@ int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *, int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *, FAR sigset_t *); +/* Set spawn attributes interfaces */ + int posix_spawnattr_setflags(FAR posix_spawnattr_t *, short); -int posix_spawnattr_setpgroup(FAR posix_spawnattr_t *, pid_t); +#define posix_spawnattr_setpgroup(attr,group) (ENOSYS) int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *, FAR const struct sched_param *); int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *, int); diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 0952fda47..4c59b4487 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -40,6 +40,11 @@ ifeq ($(CONFIG_LIBC_EXECFUNCS),y) CSRCS += lib_psfa_addaction.c lib_psfa_addclose.c lib_psfa_adddup2.c CSRCS += lib_psfa_addopen.c lib_psfa_destroy.c lib_psfa_init.c +CSRCS += lib_psa_getflags.c lib_psa_getschedparam.c lib_psa_getschedpolicy.c +CSRCS += lib_psa_getsigdefault.c lib_psa_getsigmask.c lib_psa_init.c +CSRCS += lib_psa_setflags.c lib_psa_setschedparam.c lib_psa_setschedpolicy.c +CSRCS += lib_psa_setsigdefault.c lib_psa_setsigmask.c + # Add the spawn directory to the build DEPPATH += --dep-path spawn diff --git a/nuttx/libc/spawn/lib_psa_getflags.c b/nuttx/libc/spawn/lib_psa_getflags.c new file mode 100644 index 000000000..f0e07f0c2 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getflags.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * libc/string/lib_psa_getflags.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getflags + * + * Description: + * The posix_spawnattr_getflags() function will obtain the value of the + * spawn-flags attribute from the attributes object referenced by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * flags - The location to return the spawn flags + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, + FAR short *flags) +{ + DEBUGASSERT(attr && flags); + *flags = (short)attr->flags; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_getschedparam.c b/nuttx/libc/spawn/lib_psa_getschedparam.c new file mode 100644 index 000000000..65cec47f1 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getschedparam.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_getschedparam.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getschedparam + * + * Description: + * The posix_spawnattr_getschedparam() function will obtain the value of + * the spawn-schedparam attribute from the attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * flags - The location to return the sched_priority value. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, + FAR struct sched_param *param) +{ + DEBUGASSERT(attr && param); + param->sched_priority = attr->priority; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_getschedpolicy.c b/nuttx/libc/spawn/lib_psa_getschedpolicy.c new file mode 100644 index 000000000..8f3645666 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getschedpolicy.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * libc/string/lib_psa_getschedpolicy.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getschedpolicy + * + * Description: + * The posix_spawnattr_getschedpolicy() function shall obtain the value + * of the spawn-schedpolicy attribute from the attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * policy - The location to return the scheduler policy + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, + FAR int *policy) +{ + DEBUGASSERT(attr && policy); + *policy = (int)attr->policy; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_getsigdefault.c b/nuttx/libc/spawn/lib_psa_getsigdefault.c new file mode 100644 index 000000000..73ebcc737 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getsigdefault.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_getsigdefault.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getsigdefault + * + * Description: + * The posix_spawnattr_getsigdefault() function will obtain the value of + * the spawn-sigdefault attribute from the attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * sigdefault - The location to return the signal set + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *attr, + FAR sigset_t *sigdefault) +{ + DEBUGASSERT(attr && sigdefault); + *sigdefault = attr->sigdefault; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_getsigmask.c b/nuttx/libc/spawn/lib_psa_getsigmask.c new file mode 100644 index 000000000..4ab383e76 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getsigmask.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_getsigmask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getsigmask + * + * Description: + * The posix_spawnattr_getsigdefault() function will obtain the value of + * the spawn-sigmask attribute from the attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * sigmask - The location to return the spawn flags + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, + FAR sigset_t *sigmask) +{ + DEBUGASSERT(attr && sigmask); + *sigmask = attr->sigmask; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_init.c b/nuttx/libc/spawn/lib_psa_init.c new file mode 100644 index 000000000..95f9dad33 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_init.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * libc/string/lib_psa_init.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_init + * + * Description: + * The posix_spawnattr_init() function initializes the object referenced + * by attr, to an empty set of spawn attributes for subsequent use in a + * call to posix_spawn() or posix_spawnp(). + * + * Input Parameters: + * attr - The address spawn attributes to be initialized. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_init(posix_spawnattr_t *attr) +{ + struct sched_param param; + int ret; + + DEBUGASSERT(attr); + + /* Flags: None */ + + attr->flags = 0; + + /* Signal sets. Don't really matter unless flags are set (then the settings + * are not really our responsibility). + */ + + sigemptyset(&attr->sigdefault); + sigemptyset(&attr->sigmask); + + /* Set the default scheduler policy to the policy of this task */ + + attr->policy = sched_getscheduler(0); + + /* Set the default priority to the same priority as this task */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + return errno; + } + + attr->priority = param.sched_priority; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_setflags.c b/nuttx/libc/spawn/lib_psa_setflags.c new file mode 100644 index 000000000..34b71d841 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setflags.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * libc/string/lib_psa_setflags.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setflags + * + * Description: + * The posix_spawnattr_setflags() function will set the spawn-flags + * attribute in an initialized attributes object referenced by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * flags - The new value of the spawn flags + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags) +{ + DEBUGASSERT(attr && (flags & ~0xff) == 0); + attr->flags = (uint8_t)flags; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_setschedparam.c b/nuttx/libc/spawn/lib_psa_setschedparam.c new file mode 100644 index 000000000..8d3356aaf --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setschedparam.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_setschedparam.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setschedparam + * + * Description: + * The posix_spawnattr_setschedparam() function shall set the spawn- + * schedparam attribute in an initialized attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * parm - The new sched_priority to set. + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, + FAR const struct sched_param *param) +{ + DEBUGASSERT(attr && param && (unsigned)param->sched_priority <= 0xff); + attr->priority = (uint8_t)param->sched_priority; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_setschedpolicy.c b/nuttx/libc/spawn/lib_psa_setschedpolicy.c new file mode 100644 index 000000000..136a6f0fd --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setschedpolicy.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * libc/string/lib_psa_setschedpolicy.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setschedpolicy + * + * Description: + * The posix_spawnattr_setschedpolicy() function will set the spawn- + * schedpolicy attribute in an initialized attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * flags - The new value of the spawn flags + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy) +{ + DEBUGASSERT(attr && (policy == SCHED_FIFO || policy == SCHED_RR)); + attr->policy = (uint8_t)policy; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_setsigdefault.c b/nuttx/libc/spawn/lib_psa_setsigdefault.c new file mode 100644 index 000000000..c927c6695 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setsigdefault.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_setsigdefault.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setsigdefault + * + * Description: + * The posix_spawnattr_setsigdefault() function will set the spawn- + * sigdefault attribute in an initialized attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * flags - The new value of the default signal set + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setsigdefault(FAR posix_spawnattr_t *attr, + FAR const sigset_t *sigdefault) +{ + DEBUGASSERT(attr && sigdefault); + attr->sigdefault = *sigdefault; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_setsigmask.c b/nuttx/libc/spawn/lib_psa_setsigmask.c new file mode 100644 index 000000000..d3ddff4e3 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setsigmask.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/string/lib_psa_setsigmask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setsigmask + * + * Description: + * The posix_spawnattr_setsigmask() function will set the spawn- + * sigmask attribute in an initialized attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * flags - The new value of the default signal set + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, + FAR const sigset_t *sigmask) +{ + DEBUGASSERT(attr && sigmask); + attr->sigmask = *sigmask; + return OK; +} diff --git a/nuttx/libc/spawn/lib_psfa_addclose.c b/nuttx/libc/spawn/lib_psfa_addclose.c index 225885cb1..bf22a153a 100644 --- a/nuttx/libc/spawn/lib_psfa_addclose.c +++ b/nuttx/libc/spawn/lib_psfa_addclose.c @@ -56,8 +56,8 @@ * Description: * The posix_spawn_file_actions_addclose() function adds a close operation * to the list of operations associated with the object referenced by - * file_actions, for subsequent use in a call to posix_spawn(2) or - * posix_spawnp(2). The descriptor referred to by fd is closed as if + * file_actions, for subsequent use in a call to posix_spawn() or + * posix_spawnp(). The descriptor referred to by fd is closed as if * close() had been called on it prior to the new child process starting * execution. * diff --git a/nuttx/libc/spawn/lib_psfa_adddup2.c b/nuttx/libc/spawn/lib_psfa_adddup2.c index 966f456af..fc788a4e9 100644 --- a/nuttx/libc/spawn/lib_psfa_adddup2.c +++ b/nuttx/libc/spawn/lib_psfa_adddup2.c @@ -56,8 +56,8 @@ * Description: * The posix_spawn_file_actions_adddup2() function adds a dup2 operation to * the list of operations associated with the object referenced by - * file_actions, for subsequent use in a call to posix_spawn(2) or - * posix_spawnp(2). The descriptor referred to by fd2 is created as + * file_actions, for subsequent use in a call to posix_spawn() or + * posix_spawnp(). The descriptor referred to by fd2 is created as * if dup2() had been called on fd1 prior to the new child process * starting execution. * diff --git a/nuttx/libc/spawn/lib_psfa_init.c b/nuttx/libc/spawn/lib_psfa_init.c index 860045b52..cb638d6e7 100644 --- a/nuttx/libc/spawn/lib_psfa_init.c +++ b/nuttx/libc/spawn/lib_psfa_init.c @@ -51,7 +51,7 @@ * Description: * The posix_spawn_file_actions_init() function initializes the object * referenced by file_actions, to an empty set of file actions for - * subsequent use in a call to posix_spawn(2) or posix_spawnp(2). + * subsequent use in a call to posix_spawn() or posix_spawnp(). * * Input Parameters: * file_actions - The address of the posix_spawn_file_actions_t to be -- cgit v1.2.3 From 35c5bb8e0f177643ec8d182d5a8fe2a813a3a2ad Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 14:07:30 +0000 Subject: Fix rounding in clock_time2ticks(). From Mike Smith. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5502 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 ++ nuttx/sched/clock_time2ticks.c | 42 ++++++++++++++++++++++++++++++++++++++---- 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 3d124073b..758e8c862 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3897,4 +3897,6 @@ arch/arm/src/lm so that is can support other members of the Stellaris family. * libc/spawn: Add file action interfaces needed by posix_spawn(). + * sched/clock_time2ticks.c: Another case where time was being + rounded down instead of up (from Mikek Smith). diff --git a/nuttx/sched/clock_time2ticks.c b/nuttx/sched/clock_time2ticks.c index 383264d51..012f4e4f1 100644 --- a/nuttx/sched/clock_time2ticks.c +++ b/nuttx/sched/clock_time2ticks.c @@ -89,14 +89,48 @@ int clock_time2ticks(FAR const struct timespec *reltime, FAR int *ticks) { +#ifdef CONFIG_HAVE_LONG_LONG + int64_t relnsec; + + /* Convert the relative time into nanoseconds. The range of the int64_t is + * sufficiently large that there is no real need for range checking. + */ + + relnsec = (int64_t)reltime->tv_sec * NSEC_PER_SEC + + (int64_t)reltime->tv_nsec; + + /* Convert nanoseconds to clock ticks, rounding up to the smallest integer + * that is greater than or equal to the exact number of tick. + */ + + *ticks = (int)((relnsec + NSEC_PER_TICK - 1) / NSEC_PER_TICK); + return OK; +#else int32_t relusec; - /* Convert the relative time into microseconds.*/ + /* This function uses an int32_t to only the relative time in microseconds. + * that means that the maximum supported relative time is 2,147,487.647 + * seconds + */ + +#if 0 // overkill + DEBUGASSERT(reltime->tv_sec < 2147487 || + reltime->tv_sec == 2147487 && + reltime->tv_nsec <= 647 * NSEC_PER_MSEC); +#endif + + /* Convert the relative time into microseconds, rounding up to the smallest + * value that is greater than or equal to the exact number of microseconds. + */ - relusec = reltime->tv_sec * USEC_PER_SEC + reltime->tv_nsec / NSEC_PER_USEC; + relusec = reltime->tv_sec * USEC_PER_SEC + + (reltime->tv_nsec + NSEC_PER_USEC - 1) / NSEC_PER_USEC; - /* Convert microseconds to clock ticks */ + /* Convert microseconds to clock ticks, rounding up to the smallest integer + * that is greater than or equal to the exact number of tick. + */ - *ticks = relusec / USEC_PER_TICK; + *ticks = (int)((relusec + USEC_PER_TICK - 1) / USEC_PER_TICK); return OK; +#endif } -- cgit v1.2.3 From 91cfebc978d02d83323ce3f95e02d819c5eded0e Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 15:26:09 +0000 Subject: Removed posix_spawn signal masks - they cannot be supported in NuttX; Add skeleton for posix_spawn proposer - still incomplete git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5503 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 2 +- nuttx/include/spawn.h | 84 ++++++++-------- nuttx/libc/spawn/Make.defs | 7 +- nuttx/libc/spawn/lib_ps.c | 158 +++++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_getsigdefault.c | 74 --------------- nuttx/libc/spawn/lib_psa_getsigmask.c | 74 --------------- nuttx/libc/spawn/lib_psa_init.c | 8 -- nuttx/libc/spawn/lib_psa_setsigdefault.c | 74 --------------- nuttx/libc/spawn/lib_psa_setsigmask.c | 74 --------------- 9 files changed, 205 insertions(+), 350 deletions(-) create mode 100644 nuttx/libc/spawn/lib_ps.c delete mode 100644 nuttx/libc/spawn/lib_psa_getsigdefault.c delete mode 100644 nuttx/libc/spawn/lib_psa_getsigmask.c delete mode 100644 nuttx/libc/spawn/lib_psa_setsigdefault.c delete mode 100644 nuttx/libc/spawn/lib_psa_setsigmask.c diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 758e8c862..92fbb56df 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3898,5 +3898,5 @@ Stellaris family. * libc/spawn: Add file action interfaces needed by posix_spawn(). * sched/clock_time2ticks.c: Another case where time was being - rounded down instead of up (from Mikek Smith). + rounded down instead of up (from Mike Smith). diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index 24b68585e..91092eeb0 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/spawn.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,7 +45,6 @@ #include #include -#include #include /**************************************************************************** @@ -56,12 +55,12 @@ * posix_spawnattr_t object using the posix_spawnattr_setflags() function:" */ -#define POSIX_SPAWN_RESETIDS (1 << 0) -#define POSIX_SPAWN_SETPGROUP (1 << 1) -#define POSIX_SPAWN_SETSCHEDPARAM (1 << 2) -#define POSIX_SPAWN_SETSCHEDULER (1 << 3) -#define POSIX_SPAWN_SETSIGDEF (1 << 4) -#define POSIX_SPAWN_SETSIGMASK (1 << 5) +#define POSIX_SPAWN_RESETIDS (1 << 0) /* 1: Reset effective user ID */ +#define POSIX_SPAWN_SETPGROUP (1 << 1) /* 1: Set process group */ +#define POSIX_SPAWN_SETSCHEDPARAM (1 << 2) /* 1: Set task's priority */ +#define POSIX_SPAWN_SETSCHEDULER (1 << 3) /* 1: Set task's scheduler policy */ +#define POSIX_SPAWN_SETSIGDEF (1 << 4) /* 1: Set default signal actions */ +#define POSIX_SPAWN_SETSIGMASK (1 << 5) /* 1: Set sigmask *./ /**************************************************************************** * Type Definitions @@ -78,8 +77,6 @@ struct posix_spawnattr_s uint8_t flags; uint8_t priority; uint8_t policy; - sigset_t sigdefault; - sigset_t sigmask; }; typedef struct posix_spawnattr_s posix_spawnattr_t; @@ -108,32 +105,39 @@ extern "C" /* posix_spawn[p] interfaces ************************************************/ -int posix_spawn(FAR pid_t *, FAR const char *, - FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, - FAR char *const [], FAR char *const []); -int posix_spawnp(FAR pid_t *, FAR const char *, - FAR const posix_spawn_file_actions_t *, FAR const posix_spawnattr_t *, - FAR char *const [], FAR char *const []); +#ifdef CONFIG_BINFMT_EXEPATH +int posix_spawnp(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t * attr, + FAR char *const argv[], FAR char *const envp[]); +#define posix_spawn(pid,path,file_actions,attr,argv,envp) \ + posix_spawnp(pid,path,file_actions,attr,argv,envp) +#else +int posix_spawn(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[], FAR char *const envp[]); +#endif /* File action interfaces ***************************************************/ /* File action initialization and destruction */ -int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *); -int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *); +int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions); +int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_actions); /* Add file action interfaces */ -int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *, - int); -int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *, - int, int); -int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *, - int, FAR const char *, int, mode_t); +int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actions, + int fd); +int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_actions, + int fd1, int fd2); +int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_actions, + int fd, FAR const char *path, int oflags, mode_t mode); /* Spawn attributes interfaces **********************************************/ /* Spawn attributes initialization and destruction */ -int posix_spawnattr_init(FAR posix_spawnattr_t *); +int posix_spawnattr_init(FAR posix_spawnattr_t *attr); /* int posix_spawnattr_destroy(FAR posix_spawnattr_t *); */ #ifdef CONFIG_DEBUG @@ -144,28 +148,24 @@ int posix_spawnattr_init(FAR posix_spawnattr_t *); /* Get spawn attributes interfaces */ -int posix_spawnattr_getflags(FAR const posix_spawnattr_t *, FAR short *); +int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, FAR short *flags); #define posix_spawnattr_getpgroup(attr,group) (ENOSYS) -int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *, - FAR struct sched_param *); -int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *, - FAR int *); -int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *, - FAR sigset_t *); -int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *, - FAR sigset_t *); +int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, + FAR struct sched_param *param); +int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, + FAR int *policy); +#define posix_spawnattr_getsigdefault(attr,sigdefault) (ENOSYS) +#define posix_spawnattr_getsigmask(attr,sigmask) (ENOSYS) /* Set spawn attributes interfaces */ -int posix_spawnattr_setflags(FAR posix_spawnattr_t *, short); +int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags); #define posix_spawnattr_setpgroup(attr,group) (ENOSYS) -int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *, - FAR const struct sched_param *); -int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *, int); -int posix_spawnattr_setsigdefault(FAR posix_spawnattr_t *, - FAR const sigset_t *); -int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *, - FAR const sigset_t *); +int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, + FAR const struct sched_param *param); +int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy); +#define posix_spawnattr_setsigdefault(attr,sigdefault) (ENOSYS) +#define posix_spawnattr_setsigmask(attr,sigmask) (ENOSYS) #ifdef __cplusplus } diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 4c59b4487..21bc316fa 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -37,13 +37,14 @@ ifeq ($(CONFIG_LIBC_EXECFUNCS),y) +CSRCS += lib_ps.c + CSRCS += lib_psfa_addaction.c lib_psfa_addclose.c lib_psfa_adddup2.c CSRCS += lib_psfa_addopen.c lib_psfa_destroy.c lib_psfa_init.c CSRCS += lib_psa_getflags.c lib_psa_getschedparam.c lib_psa_getschedpolicy.c -CSRCS += lib_psa_getsigdefault.c lib_psa_getsigmask.c lib_psa_init.c -CSRCS += lib_psa_setflags.c lib_psa_setschedparam.c lib_psa_setschedpolicy.c -CSRCS += lib_psa_setsigdefault.c lib_psa_setsigmask.c +CSRCS += lib_psa_init.c lib_psa_setflags.c lib_psa_setschedparam.c +CSRCS += lib_psa_setschedpolicy.c # Add the spawn directory to the build diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c new file mode 100644 index 000000000..e04ed77ad --- /dev/null +++ b/nuttx/libc/spawn/lib_ps.c @@ -0,0 +1,158 @@ +/**************************************************************************** + * libc/string/lib_ps.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn + * + * Description: + * The posix_spawn() and posix_spawnp() functions will create a new, + * child task, constructed a regular executable file. + * + * Input Parameters: + * + * pid - Upon successful completion, posix_spawn() and posix_spawnp() will + * return the task ID of the child task to the parent task, in the + * variable pointed to by a non-NULL 'pid' argument. If the 'pid' + * argument is a null pointer, the process ID of the child is not + * returned to the caller. + * + * path - The 'path' argument to posix_spawn() is the absolute path that + * identifies the file to execute. The 'path' argument to posix_spawnp() + * may also be a relative path and will be used to construct a pathname + * that identifies the file to execute. In the case of a relative path, + * the path prefix for the file will be obtained by a search of the + * directories passed as the environment variable PATH. + * + * NOTE: NuttX provides only one implementation: If + * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior + * is supported; otherwise, only posix_spawn behavior is supported. + * + * file_actions - If 'file_actions' is a null pointer, then file + * descriptors open in the calling process will remain open in the + * child process (unless CONFIG_FDCLONE_STDIO is defined). If + * 'file_actions' is not NULL, then the file descriptors open in the + * child process will be those open in the calling process as modified + * by the spawn file actions object pointed to by file_actions. + * + * attr - If the value of the 'attr' parameter is NULL, the all default + * values for the POSIX spawn attributes will be used. Otherwise, the + * attributes will be set according to the spawn flags. The + * posix_spawnattr_t spawn attributes object type is defined in spawn.h. + * It will contains these attributes, not all of which are supported by + * NuttX: + * + * - POSIX_SPAWN_SETPGROUP: Setting of the new tasks process group is + * not supported. NuttX does not support process groups. + * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param + * value. + * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to + * the sched_policy value. + * - POSIX_SPAWN_RESETIDS: Resetting of effective user ID of the child + * process is not supported. NuttX does not support effective user + * IDs. + * - POSIX_SPAWN_SETSIGMASK: Setting the initial signal mask of the new + * task is not supported. NuttX does support signal masks, but there + * is no mechanism in place now to do this. + * - POSIX_SPAWN_SETSIGDEF: Resetting signal default actions is not + * supported. NuttX does not support default signal actions. + * + * argv - argv[] is the argument list for the new task. argv[] is an + * array of pointers to null-terminated strings. The list is terminated + * with a null pointer. The value in argv[0] should point to a filename + * that is associated with the process image being started by the + * posix_spawn() or posix_spawnp() functions. + * + * envp - The envp[] argument is not used by NuttX and may be NULL. In + * standard implementations, envp[] is an array of character pointers to + * null-terminated strings that provide the environment for the new + * process image. The environment array is terminated by a null pointer. + * In NuttX, the envp[] argument is ignored and the new task will simply + * inherit the environment of the parent task. + * + * Returned Value: + * posix_spawn() and posix_spawnp() will return zero on success. + * Otherwise, an error number will be returned as the function return + * value to indicate the error: + * + * - EINVAL: The value specified by 'file_actions' or 'attr' is invalid. + * - Any errors that might have been return if vfork() and excec[l|v]() + * had been called. + * + * Assumptions/Limitations: + * - NuttX provides only posix_spawn() or posix_spawnp() behavior + * depending upon the setting of CONFIG_BINFMT_EXEPATH: If + * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior + * is supported; otherwise, only posix_spawn behavior is supported. + * - The 'envp' argument is not used and the 'environ' variable is not + * altered (NuttX does not support the 'environ' variable. + * - Process groups are not supported (POSIX_SPAWN_SETPGROUP). + * - Effective user IDs are not supported (POSIX_SPAWN_RESETIDS). + * - Signal masks and signal default actions cannot be modified in the + * newly executed task (POSIX_SPAWN_SETSIGDEF and POSIX_SPAWN_SETSIGMASK). + * + * POSIX Compatibility + * - The value of the argv[0] received by the child task is assigned by + * NuttX. For the caller of posix_spawn(), the provided argv[0] will + * correspond to argv[1] received by the new task. + * + ****************************************************************************/ + +#ifdef CONFIG_BINFMT_EXEPATH +int posix_spawnp(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[], FAR char *const envp[]) +#else +int posix_spawn(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[], FAR char *const envp[]) +#endif +{ +#warning "Missing Logic" + return OK; +} diff --git a/nuttx/libc/spawn/lib_psa_getsigdefault.c b/nuttx/libc/spawn/lib_psa_getsigdefault.c deleted file mode 100644 index 73ebcc737..000000000 --- a/nuttx/libc/spawn/lib_psa_getsigdefault.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * libc/string/lib_psa_getsigdefault.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: posix_spawnattr_getsigdefault - * - * Description: - * The posix_spawnattr_getsigdefault() function will obtain the value of - * the spawn-sigdefault attribute from the attributes object referenced - * by attr. - * - * Input Parameters: - * attr - The address spawn attributes to be queried. - * sigdefault - The location to return the signal set - * - * Returned Value: - * On success, these functions return 0; on failure they return an error - * number from . - * - ****************************************************************************/ - -int posix_spawnattr_getsigdefault(FAR const posix_spawnattr_t *attr, - FAR sigset_t *sigdefault) -{ - DEBUGASSERT(attr && sigdefault); - *sigdefault = attr->sigdefault; - return OK; -} diff --git a/nuttx/libc/spawn/lib_psa_getsigmask.c b/nuttx/libc/spawn/lib_psa_getsigmask.c deleted file mode 100644 index 4ab383e76..000000000 --- a/nuttx/libc/spawn/lib_psa_getsigmask.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * libc/string/lib_psa_getsigmask.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: posix_spawnattr_getsigmask - * - * Description: - * The posix_spawnattr_getsigdefault() function will obtain the value of - * the spawn-sigmask attribute from the attributes object referenced - * by attr. - * - * Input Parameters: - * attr - The address spawn attributes to be queried. - * sigmask - The location to return the spawn flags - * - * Returned Value: - * On success, these functions return 0; on failure they return an error - * number from . - * - ****************************************************************************/ - -int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, - FAR sigset_t *sigmask) -{ - DEBUGASSERT(attr && sigmask); - *sigmask = attr->sigmask; - return OK; -} diff --git a/nuttx/libc/spawn/lib_psa_init.c b/nuttx/libc/spawn/lib_psa_init.c index 95f9dad33..8aabfd090 100644 --- a/nuttx/libc/spawn/lib_psa_init.c +++ b/nuttx/libc/spawn/lib_psa_init.c @@ -40,7 +40,6 @@ #include #include -#include #include #include #include @@ -78,13 +77,6 @@ int posix_spawnattr_init(posix_spawnattr_t *attr) attr->flags = 0; - /* Signal sets. Don't really matter unless flags are set (then the settings - * are not really our responsibility). - */ - - sigemptyset(&attr->sigdefault); - sigemptyset(&attr->sigmask); - /* Set the default scheduler policy to the policy of this task */ attr->policy = sched_getscheduler(0); diff --git a/nuttx/libc/spawn/lib_psa_setsigdefault.c b/nuttx/libc/spawn/lib_psa_setsigdefault.c deleted file mode 100644 index c927c6695..000000000 --- a/nuttx/libc/spawn/lib_psa_setsigdefault.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * libc/string/lib_psa_setsigdefault.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: posix_spawnattr_setsigdefault - * - * Description: - * The posix_spawnattr_setsigdefault() function will set the spawn- - * sigdefault attribute in an initialized attributes object referenced - * by attr. - * - * Input Parameters: - * attr - The address spawn attributes to be used. - * flags - The new value of the default signal set - * - * Returned Value: - * On success, these functions return 0; on failure they return an error - * number from . - * - ****************************************************************************/ - -int posix_spawnattr_setsigdefault(FAR posix_spawnattr_t *attr, - FAR const sigset_t *sigdefault) -{ - DEBUGASSERT(attr && sigdefault); - attr->sigdefault = *sigdefault; - return OK; -} diff --git a/nuttx/libc/spawn/lib_psa_setsigmask.c b/nuttx/libc/spawn/lib_psa_setsigmask.c deleted file mode 100644 index d3ddff4e3..000000000 --- a/nuttx/libc/spawn/lib_psa_setsigmask.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * libc/string/lib_psa_setsigmask.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: posix_spawnattr_setsigmask - * - * Description: - * The posix_spawnattr_setsigmask() function will set the spawn- - * sigmask attribute in an initialized attributes object referenced - * by attr. - * - * Input Parameters: - * attr - The address spawn attributes to be used. - * flags - The new value of the default signal set - * - * Returned Value: - * On success, these functions return 0; on failure they return an error - * number from . - * - ****************************************************************************/ - -int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, - FAR const sigset_t *sigmask) -{ - DEBUGASSERT(attr && sigmask); - attr->sigmask = *sigmask; - return OK; -} -- cgit v1.2.3 From 322e9d18c7371f9fb27cd57ca894191d564b75c3 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 17:37:29 +0000 Subject: Completes implementation of posix_spawn. Still untested and undocumented git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5504 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 4 + nuttx/TODO | 13 +- nuttx/drivers/usbdev/pl2303.c | 20 +- nuttx/libc/Kconfig | 8 + nuttx/libc/spawn/lib_ps.c | 415 +++++++++++++++++++++++++++++++++++++++++- nuttx/libc/unistd/lib_execv.c | 4 +- 6 files changed, 445 insertions(+), 19 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 92fbb56df..421b1ca60 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3899,4 +3899,8 @@ * libc/spawn: Add file action interfaces needed by posix_spawn(). * sched/clock_time2ticks.c: Another case where time was being rounded down instead of up (from Mike Smith). + * libc/spawn: Implementation of posix_spawn() is complete but + untested and undocumented. + * drivers/usbdev/pl2303.c: Fix typols in the PL2303 driver + (from Max Holtzberg). diff --git a/nuttx/TODO b/nuttx/TODO index 72eb845bc..c10b101cc 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (11) Task/Scheduler (sched/) + (12) Task/Scheduler (sched/) (1) Memory Managment (mm/) (2) Signals (sched/, arch/) (2) pthreads (sched/) @@ -189,6 +189,17 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium Low for now + Title: INHERITANCE of sigmask + Description: New tasks/threads do not inherit the parent's signal mask. + This behavior is required under POSIX. + + Also, related: Setting of the initial sigmask was not + implemented in posix_spawn (libc/spawn) because of this. + Status: Open + Priority: Low, make medium-low. These kinds of behaviors are not + common in tiny embedded RTOSs. And it has always been + like this and no one has complained so far. + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/drivers/usbdev/pl2303.c b/nuttx/drivers/usbdev/pl2303.c index 95f26c185..d10539fa7 100644 --- a/nuttx/drivers/usbdev/pl2303.c +++ b/nuttx/drivers/usbdev/pl2303.c @@ -333,7 +333,7 @@ static void usbclass_wrcomplete(FAR struct usbdev_ep_s *ep, /* USB class device ********************************************************/ -static int usbclass_bind(FAR struct usbdevclass_driver_s *driver, +static int usbclass_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); static void usbclass_unbind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_s *dev); @@ -1295,7 +1295,7 @@ static int usbclass_bind(FAR struct usbdevclass_driver_s *driver, priv->usbdev = dev; /* Save the reference to our private data structure in EP0 so that it - * can be recovered in ep0 completion events (Unless we are part of + * can be recovered in ep0 completion events (Unless we are part of * a composite device and, in that case, the composite device owns * EP0). */ @@ -1859,7 +1859,7 @@ static void usbclass_disconnect(FAR struct usbdevclass_driver_s *driver, * re-enumerated. */ - DEV_CONNECT(dev); + DEV_CONNECT(dev); } /**************************************************************************** @@ -1878,7 +1878,7 @@ static int usbser_setup(FAR struct uart_dev_s *dev) { FAR struct pl2303_dev_s *priv; - usbtrace(PL2303_CLASSASPI_SETUP, 0); + usbtrace(PL2303_CLASSAPI_SETUP, 0); /* Sanity check */ @@ -1919,7 +1919,7 @@ static int usbser_setup(FAR struct uart_dev_s *dev) static void usbser_shutdown(FAR struct uart_dev_s *dev) { - usbtrace(PL2303_CLASSASPI_SHUTDOWN, 0); + usbtrace(PL2303_CLASSAPI_SHUTDOWN, 0); /* Sanity check */ @@ -1941,7 +1941,7 @@ static void usbser_shutdown(FAR struct uart_dev_s *dev) static int usbser_attach(FAR struct uart_dev_s *dev) { - usbtrace(PL2303_CLASSASPI_ATTACH, 0); + usbtrace(PL2303_CLASSAPI_ATTACH, 0); return OK; } @@ -1955,7 +1955,7 @@ static int usbser_attach(FAR struct uart_dev_s *dev) static void usbser_detach(FAR struct uart_dev_s *dev) { - usbtrace(PL2303_CLASSASPI_DETACH, 0); + usbtrace(PL2303_CLASSAPI_DETACH, 0); } /**************************************************************************** @@ -1981,7 +1981,7 @@ static void usbser_rxint(FAR struct uart_dev_s *dev, bool enable) FAR uart_dev_t *serdev; irqstate_t flags; - usbtrace(PL2303_CLASSASPI_RXINT, (uint16_t)enable); + usbtrace(PL2303_CLASSAPI_RXINT, (uint16_t)enable); /* Sanity check */ @@ -2072,7 +2072,7 @@ static void usbser_txint(FAR struct uart_dev_s *dev, bool enable) { FAR struct pl2303_dev_s *priv; - usbtrace(PL2303_CLASSASPI_TXINT, (uint16_t)enable); + usbtrace(PL2303_CLASSAPI_TXINT, (uint16_t)enable); /* Sanity checks */ @@ -2117,7 +2117,7 @@ static bool usbser_txempty(FAR struct uart_dev_s *dev) { FAR struct pl2303_dev_s *priv = (FAR struct pl2303_dev_s*)dev->priv; - usbtrace(PL2303_CLASSASPI_TXEMPTY, 0); + usbtrace(PL2303_CLASSAPI_TXEMPTY, 0); #if CONFIG_DEBUG if (!priv) diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index d739b6351..2f091f1c7 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -121,6 +121,14 @@ config EXECFUNCS_NSYMBOLS symbols in that table. This selection provides the number of symbols in the symbol table. +config POSIX_SPAWN_STACKSIZE + int "posix_spawn Stack Size" + default 768 + ---help--- + If posix_spawn[p] uses I/O redirection options, then it will require + an intermediary/proxy task to muck with the file descriptors. This + configuration item specifies the stack size used for the proxy. + endif config LIBC_STRERROR diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index e04ed77ad..e73d1eef0 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -39,10 +39,349 @@ #include +#include +#include +#include #include +#include +#include +#include + +#include + +#include "spawn/spawn.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct spawn_parms_s +{ + int result; + FAR pid_t *pid; + FAR const char *path; + FAR const posix_spawn_file_actions_t *file_actions; + FAR const posix_spawnattr_t *attr; + FAR char *const *argv; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static sem_t g_ps_parmsem = SEM_INITIALIZER(1); +static sem_t g_ps_execsem = SEM_INITIALIZER(0); +static struct spawn_parms_s g_ps_parms; /**************************************************************************** - * Global Functions + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ps_semtake and ps_semgive + * + * Description: + * Give and take semaphores + * + * Input Parameters: + * + * sem - The semaphore to act on. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ps_semtake(FAR sem_t *sem) +{ + int ret; + + do + { + ret = sem_wait(sem); + ASSERT(ret == 0 || errno == EINTR); + } + while (ret != 0); +} + +#define ps_semgive(sem) sem_post(sem) + +/**************************************************************************** + * Name: ps_exec + * + * Description: + * Execute the task from the file system. + * + * Input Parameters: + * + * pidp - Upon successful completion, this will return the task ID of the + * child task in the variable pointed to by a non-NULL 'pid' argument.| + * + * path - The 'path' argument identifies the file to execute. If + * CONFIG_BINFMT_EXEPATH is defined, this may be either a relative or + * or an absolute path. Otherwise, it must be an absolute path. + * + * attr - If the value of the 'attr' parameter is NULL, the all default + * values for the POSIX spawn attributes will be used. Otherwise, the + * attributes will be set according to the spawn flags. The + * following spawn flags are supported: + * + * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param + * value. + * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to + * the sched_policy value. + * + * argv - argv[] is the argument list for the new task. argv[] is an + * array of pointers to null-terminated strings. The list is terminated + * with a null pointer. + * + * Returned Value: + * This function will return zero on success. Otherwise, an error number + * will be returned as the function return value to indicate the error. + * This errno value may be that set by execv(), sched_setpolicy(), or + * sched_setparam(). + * + ****************************************************************************/ + +static int ps_exec(FAR pid_t *pidp, FAR const char *path, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[]) +{ + struct sched_param param; + int pid; + int ret = OK; + + DEBUGASSERT(path); + + /* Disable pre-emption so that we can modify the task parameters after + * we start the new task; the new task will not actually begin execution + * until we re-enable pre-emption. + */ + + sched_lock(); + + /* Start the task */ + + pid = exec(path, (FAR const char **)argv, &CONFIG_EXECFUNCS_SYMTAB, + CONFIG_EXECFUNCS_NSYMBOLS); + + if (pid < 0) + { + ret = errno; + sdbg("exec failed: %d\n", ret); + goto errout; + } + + /* Return the task ID to the caller */ + + if (pid) + { + *pidp = pid; + } + + /* Now set the attributes. Note that we ignore all of the return values + * here because we have already successfully started the task. If we + * return an error value, then we would also have to stop the task. + */ + + if (attr) + { + /* If we are only setting the priority, then call sched_setparm() + * to set the priority of the of the new task. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDPARAM) != 0) + { + /* Get the priority from the attrributes */ + + param.sched_priority = attr->priority; + + /* If we are setting *both* the priority and the scheduler, + * then we will call sched_setscheduler() below. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) == 0) + { + (void)sched_setparam(pid, ¶m); + } + } + + /* If we are only changing the scheduling policy, then reset + * the priority to the default value (the same as this thread) in + * preparation for the sched_setscheduler() call below. + */ + + else if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) + { + (void)sched_getparam(0, ¶m); + } + + /* Are we setting the scheduling policy? If so, use the priority + * setting determined above. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) + { + (void)sched_setscheduler(pid, attr->policy, ¶m); + } + } + + /* Re-enable pre-emption and return */ + +errout: + sched_unlock(); + return OK; +} + +/**************************************************************************** + * Name: spawn_close, spawn_dup2, and spawn_open + * + * Description: + * Implement individual file actions + * + * Input Parameters: + * action - describes the action to be performed + * + * Returned Value: + * posix_spawn() and posix_spawnp() will return zero on success. + * Otherwise, an error number will be returned as the function return + * value to indicate the error. + * + ****************************************************************************/ + +static inline int spawn_close(FAR struct spawn_close_file_action_s *action) +{ + /* The return value from close() is ignored */ + + (void)close(action->fd); + return OK; +} + +static inline int spawn_dup2(FAR struct spawn_dup2_file_action_s *action) +{ + /* Perform the dup */ + + int ret = dup2(action->fd1, action->fd2); + if (ret < 0) + { + return errno; + } + + return OK; +} + +static inline int spawn_open(FAR struct spawn_open_file_action_s *action) +{ + int fd; + int ret = OK; + + /* Open the file */ + + fd = open(action->path, action->oflags, action->mode); + if (fd < 0) + { + ret = errno; + } + + /* Does the return file descriptor happen to match the required file + * desciptor number? + */ + + else if (fd != action->fd) + { + /* No.. dup2 to get the correct file number */ + + ret = dup2(fd, action->fd); + if (ret < 0) + { + ret = errno; + } + + close(fd); + } + + return ret; +} + +/**************************************************************************** + * Name: spawn_proxy + * + * Description: + * Perform file_actions, then execute the task from the file system. + * + * Input Parameters: + * Standard task start-up parameters + * + * Returned Value: + * Standard task return value. + * + ****************************************************************************/ + +static int spawn_proxy(int argc, char *argv[]) +{ + FAR struct spawn_general_file_action_s *entry; + int ret; + + /* Perform I/O redirection. We get here only if the file_actions parameter + * to posix_spawn[p] was non-NULL. + */ + + DEBUGASSERT(g_ps_parms.file_actions); + + /* Execute each file action */ + + for (entry = (FAR struct spawn_general_file_action_s *)*g_ps_parms.file_actions; + entry && ret == OK; + entry = entry->flink) + { + switch (entry->action) + { + case SPAWN_FILE_ACTION_CLOSE: + ret = spawn_close((FAR struct spawn_close_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_DUP2: + ret = spawn_dup2((FAR struct spawn_dup2_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_OPEN: + ret = spawn_open((FAR struct spawn_open_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_NONE: + default: + ret = EINVAL; + break; + } + } + + /* Check for failures */ + + if (ret == OK) + { + /* Start the task */ + + ret = ps_exec(g_ps_parms.pid, g_ps_parms.path, g_ps_parms.attr, + g_ps_parms.argv); + } + + /* Post the semaphore to inform the parent task that we have completed + * what we need to do. + */ + + g_ps_parms.result = ret; + ps_semgive(&g_ps_execsem); + return 0; +} + +/**************************************************************************** + * Public Functions ****************************************************************************/ /**************************************************************************** @@ -102,9 +441,7 @@ * * argv - argv[] is the argument list for the new task. argv[] is an * array of pointers to null-terminated strings. The list is terminated - * with a null pointer. The value in argv[0] should point to a filename - * that is associated with the process image being started by the - * posix_spawn() or posix_spawnp() functions. + * with a null pointer. * * envp - The envp[] argument is not used by NuttX and may be NULL. In * standard implementations, envp[] is an array of character pointers to @@ -153,6 +490,72 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, FAR char *const argv[], FAR char *const envp[]) #endif { -#warning "Missing Logic" - return OK; + struct sched_param param; + pid_t proxy; + int ret; + + DEBUGASSERT(path); + + /* If there are no file actions to be performed, then start the new child + * task directory form the parent task. + */ + + if (!file_actions) + { + return ps_exec(pid, path, attr, argv); + } + + /* Otherwise, we will have to go through an intermediary/proxy task in order + * to perform the I/O redirection. This would be a natural place to fork(). + * However, true fork() behavior requires an MMU and most implementations + * of vfork() are not capable of these operations. + * + * Even without fork(), we can still do the job, but parameter passing is + * messier. Unfortunately, there is no (clean) way to pass binary values + * as a task parameter, so we will use a semaphore-protected global + * structure. + */ + + /* Get exclusive access to the global parameter structure */ + + ps_semtake(&g_ps_parmsem); + + /* Populate the parameter structure */ + + g_ps_parms.result = ENOSYS; + g_ps_parms.pid = pid; + g_ps_parms.path = path; + g_ps_parms.file_actions = file_actions; + g_ps_parms.attr = attr; + g_ps_parms.argv = argv; + + /* Get the priority of this (parent) task */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + ps_semgive(&g_ps_parmsem); + return errno; + } + + /* Start the intermediary/proxy task at the same priority as the parent task. */ + + proxy = TASK_CREATE("spawn_proxy", param.sched_priority, + CONFIG_POSIX_SPAWN_STACKSIZE, (main_t)spawn_proxy, + (const char **)NULL); + if (proxy < 0) + { + ps_semgive(&g_ps_parmsem); + return errno; + } + + /* Wait for the proxy to complete its job */ + + ps_semtake(&g_ps_execsem); + + /* Get the result and relinquish our access to the parameter structure */ + + ret = g_ps_parms.result; + ps_semgive(&g_ps_parmsem); + return ret; } diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c index b0f4136f1..6d09bf481 100644 --- a/nuttx/libc/unistd/lib_execv.c +++ b/nuttx/libc/unistd/lib_execv.c @@ -68,7 +68,7 @@ #endif /**************************************************************************** - * Global Variables + * Public Variables ****************************************************************************/ extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; @@ -78,7 +78,7 @@ extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; ****************************************************************************/ /**************************************************************************** - * Global Functions + * Public Functions ****************************************************************************/ /**************************************************************************** -- cgit v1.2.3 From 9f8f8fc6dc5c2057f61fe04bf1109a8590ef93d0 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 18:31:08 +0000 Subject: Add missing support for signal masks to posix_spawn. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5505 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/TODO | 15 +----- nuttx/include/spawn.h | 18 ++++++- nuttx/libc/spawn/Make.defs | 4 ++ nuttx/libc/spawn/lib_ps.c | 89 ++++++++++++++++++++++------------- nuttx/libc/spawn/lib_psa_getsigmask.c | 78 ++++++++++++++++++++++++++++++ nuttx/libc/spawn/lib_psa_setsigmask.c | 79 +++++++++++++++++++++++++++++++ nuttx/sched/task_setup.c | 4 +- 7 files changed, 238 insertions(+), 49 deletions(-) create mode 100644 nuttx/libc/spawn/lib_psa_getsigmask.c create mode 100644 nuttx/libc/spawn/lib_psa_setsigmask.c diff --git a/nuttx/TODO b/nuttx/TODO index c10b101cc..9295f6206 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 8, 2013) +NuttX TODO List (Last updated January 10, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (12) Task/Scheduler (sched/) + (11) Task/Scheduler (sched/) (1) Memory Managment (mm/) (2) Signals (sched/, arch/) (2) pthreads (sched/) @@ -189,17 +189,6 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium Low for now - Title: INHERITANCE of sigmask - Description: New tasks/threads do not inherit the parent's signal mask. - This behavior is required under POSIX. - - Also, related: Setting of the initial sigmask was not - implemented in posix_spawn (libc/spawn) because of this. - Status: Open - Priority: Low, make medium-low. These kinds of behaviors are not - common in tiny embedded RTOSs. And it has always been - like this and no one has complained so far. - o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index 91092eeb0..3978424fb 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -45,6 +45,7 @@ #include #include +#include #include /**************************************************************************** @@ -77,6 +78,9 @@ struct posix_spawnattr_s uint8_t flags; uint8_t priority; uint8_t policy; +#ifndef CONFIG_DISABLE_SIGNALS + sigset_t sigmask; +#endif }; typedef struct posix_spawnattr_s posix_spawnattr_t; @@ -155,7 +159,12 @@ int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *policy); #define posix_spawnattr_getsigdefault(attr,sigdefault) (ENOSYS) -#define posix_spawnattr_getsigmask(attr,sigmask) (ENOSYS) +#ifndef CONFIG_DISABLE_SIGNALS +int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, + FAR sigset_t *sigmask); +#else +# define posix_spawnattr_getsigmask(attr,sigmask) (ENOSYS) +#endif /* Set spawn attributes interfaces */ @@ -165,7 +174,12 @@ int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, FAR const struct sched_param *param); int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy); #define posix_spawnattr_setsigdefault(attr,sigdefault) (ENOSYS) -#define posix_spawnattr_setsigmask(attr,sigmask) (ENOSYS) +#ifndef CONFIG_DISABLE_SIGNALS +int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, + FAR const sigset_t *sigmask); +#else +# define posix_spawnattr_setsigmask(attr,sigmask) (ENOSYS) +#endif #ifdef __cplusplus } diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 21bc316fa..2cf75c410 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -46,6 +46,10 @@ CSRCS += lib_psa_getflags.c lib_psa_getschedparam.c lib_psa_getschedpolicy.c CSRCS += lib_psa_init.c lib_psa_setflags.c lib_psa_setschedparam.c CSRCS += lib_psa_setschedpolicy.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CSRCS += lib_psa_getsigmask.c lib_psa_setsigmask.c +endif + # Add the spawn directory to the build DEPPATH += --dep-path spawn diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index e73d1eef0..b0f6e1b07 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -137,6 +138,8 @@ static void ps_semtake(FAR sem_t *sem) * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to * the sched_policy value. * + * NOTE: POSIX_SPAWN_SETSIGMASK is handled in ps_proxy(). + * * argv - argv[] is the argument list for the new task. argv[] is an * array of pointers to null-terminated strings. The list is terminated * with a null pointer. @@ -326,38 +329,59 @@ static inline int spawn_open(FAR struct spawn_open_file_action_s *action) static int spawn_proxy(int argc, char *argv[]) { FAR struct spawn_general_file_action_s *entry; + FAR const posix_spawnattr_t *attr = g_ps_parms.attr; int ret; - /* Perform I/O redirection. We get here only if the file_actions parameter - * to posix_spawn[p] was non-NULL. + /* Perform file actions and/or set a custom signal mask. We get here only + * if the file_actions parameter to posix_spawn[p] was non-NULL and/or the + * option to change the signal mask was selected. */ +#ifndef CONFIG_DISABLE_SIGNALS + DEBUGASSERT(g_ps_parms.file_actions || + (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0)); +#else DEBUGASSERT(g_ps_parms.file_actions); +#endif + + /* Check if we need to change the signal mask */ + +#ifndef CONFIG_DISABLE_SIGNALS + if (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0) + { + (void)sigprocmask(SIG_SETMASK, &attr->sigmask, NULL); + } - /* Execute each file action */ + /* Were we also requested to perform file actions? */ - for (entry = (FAR struct spawn_general_file_action_s *)*g_ps_parms.file_actions; - entry && ret == OK; - entry = entry->flink) + if (g_ps_parms.file_actions) +#endif { - switch (entry->action) + /* Execute each file action */ + + for (entry = (FAR struct spawn_general_file_action_s *)*g_ps_parms.file_actions; + entry && ret == OK; + entry = entry->flink) { - case SPAWN_FILE_ACTION_CLOSE: - ret = spawn_close((FAR struct spawn_close_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_DUP2: - ret = spawn_dup2((FAR struct spawn_dup2_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_OPEN: - ret = spawn_open((FAR struct spawn_open_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_NONE: - default: - ret = EINVAL; - break; + switch (entry->action) + { + case SPAWN_FILE_ACTION_CLOSE: + ret = spawn_close((FAR struct spawn_close_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_DUP2: + ret = spawn_dup2((FAR struct spawn_dup2_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_OPEN: + ret = spawn_open((FAR struct spawn_open_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_NONE: + default: + ret = EINVAL; + break; + } } } @@ -367,8 +391,7 @@ static int spawn_proxy(int argc, char *argv[]) { /* Start the task */ - ret = ps_exec(g_ps_parms.pid, g_ps_parms.path, g_ps_parms.attr, - g_ps_parms.argv); + ret = ps_exec(g_ps_parms.pid, g_ps_parms.path, attr, g_ps_parms.argv); } /* Post the semaphore to inform the parent task that we have completed @@ -424,18 +447,16 @@ static int spawn_proxy(int argc, char *argv[]) * It will contains these attributes, not all of which are supported by * NuttX: * - * - POSIX_SPAWN_SETPGROUP: Setting of the new tasks process group is + * - POSIX_SPAWN_SETPGROUP: Setting of the new task's process group is * not supported. NuttX does not support process groups. * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param * value. - * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to + * - POSIX_SPAWN_SETSCHEDULER: Set the new task's scheduler priority to * the sched_policy value. * - POSIX_SPAWN_RESETIDS: Resetting of effective user ID of the child * process is not supported. NuttX does not support effective user * IDs. - * - POSIX_SPAWN_SETSIGMASK: Setting the initial signal mask of the new - * task is not supported. NuttX does support signal masks, but there - * is no mechanism in place now to do this. + * - POSIX_SPAWN_SETSIGMASK: Set the new task's signal mask. * - POSIX_SPAWN_SETSIGDEF: Resetting signal default actions is not * supported. NuttX does not support default signal actions. * @@ -496,11 +517,15 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, DEBUGASSERT(path); - /* If there are no file actions to be performed, then start the new child - * task directory form the parent task. + /* If there are no file actions to be performed and there is no change to + * the signal mask, then start the new child task directly from the parent task. */ +#ifndef CONFIG_DISABLE_SIGNALS + if (!file_actions && (attr->flags & POSIX_SPAWN_SETSIGMASK) == 0) +#else if (!file_actions) +#endif { return ps_exec(pid, path, attr, argv); } diff --git a/nuttx/libc/spawn/lib_psa_getsigmask.c b/nuttx/libc/spawn/lib_psa_getsigmask.c new file mode 100644 index 000000000..3c831075e --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_getsigmask.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * libc/string/lib_psa_getsigmask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_getsigmask + * + * Description: + * The posix_spawnattr_getsigdefault() function will obtain the value of + * the spawn-sigmask attribute from the attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be queried. + * sigmask - The location to return the spawn flags + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, + FAR sigset_t *sigmask) +{ + DEBUGASSERT(attr && sigmask); + *sigmask = attr->sigmask; + return OK; +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/nuttx/libc/spawn/lib_psa_setsigmask.c b/nuttx/libc/spawn/lib_psa_setsigmask.c new file mode 100644 index 000000000..28b7daf77 --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_setsigmask.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * libc/string/lib_psa_setsigmask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_setsigmask + * + * Description: + * The posix_spawnattr_setsigmask() function will set the spawn- + * sigmask attribute in an initialized attributes object referenced + * by attr. + * + * Input Parameters: + * attr - The address spawn attributes to be used. + * flags - The new value of the default signal set + * + * Returned Value: + * On success, these functions return 0; on failure they return an error + * number from . + * + ****************************************************************************/ + +int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, + FAR const sigset_t *sigmask) +{ + DEBUGASSERT(attr && sigmask); + attr->sigmask = *sigmask; + return OK; +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ + diff --git a/nuttx/sched/task_setup.c b/nuttx/sched/task_setup.c index a37fb165a..8721b39ec 100644 --- a/nuttx/sched/task_setup.c +++ b/nuttx/sched/task_setup.c @@ -231,8 +231,8 @@ int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main) tcb->start = start; tcb->entry.main = main; - /* exec() and pthread_create() inherit the signal mask of the - * parent thread. I suppose that task_create() should as well. + /* exec(), pthread_create(), task_create(), and vfork() all + * inherit the signal mask of the parent thread. */ #ifndef CONFIG_DISABLE_SIGNALS -- cgit v1.2.3 From 6f241ed0443cc265d7a079f4bbf8d2d67be939ff Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 20:00:08 +0000 Subject: Add interfaces to dynamically change symbol tables used by posix_spawn, execv, and execl. This is needed for testing. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5506 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/Make.defs | 4 + apps/examples/Makefile | 4 +- apps/examples/README.txt | 84 +++++++++++++++++++-- nuttx/include/unistd.h | 6 ++ nuttx/libc/spawn/lib_ps.c | 53 +++++++++++-- nuttx/libc/spawn/spawn.h | 2 +- nuttx/libc/unistd/Make.defs | 2 +- nuttx/libc/unistd/lib_execsymtab.c | 147 +++++++++++++++++++++++++++++++++++++ nuttx/libc/unistd/lib_execv.c | 31 ++------ 9 files changed, 292 insertions(+), 41 deletions(-) create mode 100644 nuttx/libc/unistd/lib_execsymtab.c diff --git a/apps/examples/Make.defs b/apps/examples/Make.defs index de2b8939f..68d4d4340 100644 --- a/apps/examples/Make.defs +++ b/apps/examples/Make.defs @@ -182,6 +182,10 @@ ifeq ($(CONFIG_EXAMPLES_PWM),y) CONFIGURED_APPS += examples/pwm endif +ifeq ($(CONFIG_EXAMPLES_POSIXSPAWN),y) +CONFIGURED_APPS += examples/posix_spawn +endif + ifeq ($(CONFIG_EXAMPLES_QENCODER),y) CONFIGURED_APPS += examples/qencoder endif diff --git a/apps/examples/Makefile b/apps/examples/Makefile index 99312af7a..a11dbf240 100644 --- a/apps/examples/Makefile +++ b/apps/examples/Makefile @@ -40,8 +40,8 @@ SUBDIRS = adc buttons can cdcacm composite cxxtest dhcpd discover elf ftpc SUBDIRS += ftpd hello helloxx hidkbd igmp json keypadtest lcdrw mm modbus mount SUBDIRS += nettest nsh null nx nxconsole nxffs nxflat nxhello nximage -SUBDIRS += nxlines nxtext ostest pashello pipe poll pwm qencoder relays -SUBDIRS += rgmp romfs serloop telnetd thttpd tiff touchscreen udp uip +SUBDIRS += nxlines nxtext ostest pashello pipe poll pwm posix_spawn qencoder +SUBDIRS += relays rgmp romfs serloop telnetd thttpd tiff touchscreen udp uip SUBDIRS += usbserial sendmail usbstorage usbterm watchdog wget wgetjson # Sub-directories that might need context setup. Directories may need diff --git a/apps/examples/README.txt b/apps/examples/README.txt index 7bfba721a..5c6332ee3 100644 --- a/apps/examples/README.txt +++ b/apps/examples/README.txt @@ -329,10 +329,10 @@ examples/elf each program in the ROMFS file system is executed. Requires CONFIG_ELF. Other configuration options: - CONFIG_EXAMPLES_ELF_DEVMINOR - The minor device number of the ROMFS block. - For example, the N in /dev/ramN. Used for registering the RAM block driver - that will hold the ROMFS file system containing the ELF executables to be - tested. Default: 0 + CONFIG_EXAMPLES_ELF_DEVMINOR - The minor device number of the ROMFS block + driver. For example, the N in /dev/ramN. Used for registering the RAM + block driver that will hold the ROMFS file system containing the ELF + executables to be tested. Default: 0 CONFIG_EXAMPLES_ELF_DEVPATH - The path to the ROMFS block driver device. This must match EXAMPLES_ELF_DEVMINOR. Used for registering the RAM block driver @@ -348,7 +348,7 @@ examples/elf Similarly for C++ flags which must be provided in CXXELFFLAGS. - 2. Your top-level nuttx/Make.defs file must alos include an approproate definition, + 2. Your top-level nuttx/Make.defs file must also include an approproate definition, LDELFFLAGS, to generate a relocatable ELF object. With GNU LD, this should include '-r' and '-e main' (or _main on some platforms). @@ -1202,6 +1202,80 @@ examples/poll CONFIGURED_APPS += uiplib +examples/posix_spawn +^^^^^^^^^^^^^^^^^^^^ + + This is a simple test of the posix_spawn() API. The example derives from + examples/elf. As a result, these tests are built using the relocatable + ELF format installed in a ROMFS file system. At run time, the test program + in the ROMFS file system is spawned using posix_spawn(). + + Requires: + + CONFIG_BINFMT_DISABLE=n - Don't disable the binary loader + CONFIG_ELF=y - Enable ELF binary loader + CONFIG_LIBC_EXECFUNCS=y - Enable support for posix_spawn + CONFIG_EXECFUNCS_SYMTAB="exports" - The name of the symbol table + created by the test. + CONFIG_EXECFUNCS_NSYMBOLS=10 - Value does not matter, it will be + corrected at runtime. + CONFIG_POSIX_SPAWN_STACKSIZE=768 - This default setting. + + Test-specific configuration options: + + CONFIG_EXAMPLES_POSIXSPAWN_DEVMINOR - The minor device number of the ROMFS + block. driver. For example, the N in /dev/ramN. Used for registering the + RAM block driver that will hold the ROMFS file system containing the ELF + executables to be tested. Default: 0 + + CONFIG_EXAMPLES_POSIXSPAWN_DEVPATH - The path to the ROMFS block driver + device. This must match EXAMPLES_POSIXSPAWN_DEVMINOR. Used for + registering the RAM block driver that will hold the ROMFS file system + containing the ELF executables to be tested. Default: "/dev/ram0" + + NOTES: + + 1. CFLAGS should be provided in CELFFLAGS. RAM and FLASH memory regions + may require long allcs. For ARM, this might be: + + CELFFLAGS = $(CFLAGS) -mlong-calls + + Similarly for C++ flags which must be provided in CXXELFFLAGS. + + 2. Your top-level nuttx/Make.defs file must also include an approproate + definition, LDELFFLAGS, to generate a relocatable ELF object. With GNU + LD, this should include '-r' and '-e main' (or _main on some platforms). + + LDELFFLAGS = -r -e main + + If you use GCC to link, you make also need to include '-nostdlib' or + '-nostartfiles' and '-nodefaultlibs'. + + 3. This example also requires genromfs. genromfs can be build as part of the + nuttx toolchain. Or can built from the genromfs sources that can be found + at misc/tools/genromfs-0.5.2.tar.gz. In any event, the PATH variable must + include the path to the genromfs executable. + + 4. ELF size: The ELF files in this example are, be default, quite large + because they include a lot of "build garbage". You can greatly reduce the + size of the ELF binaries are using the 'objcopy --strip-unneeded' command to + remove un-necessary information from the ELF files. + + 5. Simulator. You cannot use this example with the the NuttX simulator on + Cygwin. That is because the Cygwin GCC does not generate ELF file but + rather some Windows-native binary format. + + If you really want to do this, you can create a NuttX x86 buildroot toolchain + and use that be build the ELF executables for the ROMFS file system. + + 6. Linker scripts. You might also want to use a linker scripts to combine + sections better. An example linker script is at nuttx/binfmt/libelf/gnu-elf.ld. + That example might have to be tuned for your particular linker output to + position additional sections correctly. The GNU LD LDELFFLAGS then might + be: + + LDELFFLAGS = -r -e main -T$(TOPDIR)/binfmt/libelf/gnu-elf.ld + examples/pwm ^^^^^^^^^^^^ diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h index d2ace79fa..c5289624b 100644 --- a/nuttx/include/unistd.h +++ b/nuttx/include/unistd.h @@ -165,6 +165,12 @@ EXTERN int rmdir(FAR const char *pathname); #ifdef CONFIG_LIBC_EXECFUNCS EXTERN int execl(FAR const char *path, ...); EXTERN int execv(FAR const char *path, FAR char *const argv[]); + +/* Non-standard functions to manage symbol tables */ + +struct symtab_s; /* See include/nuttx/binfmt/symtab.h */ +EXTERN void exec_getsymtab(FAR struct symtab_s **symtab, FAR int *nsymbols); +EXTERN void exec_setsymtab(FAR const struct symtab_s *symtab, int nsymbols); #endif /* Other */ diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index b0f6e1b07..7509d6737 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -157,11 +157,17 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, FAR char *const argv[]) { struct sched_param param; + FAR struct symtab_s *symtab; + int nsymbols; int pid; int ret = OK; DEBUGASSERT(path); + /* Get the current symbol table selection */ + + exec_getsymtab(&symtab, &nsymbols); + /* Disable pre-emption so that we can modify the task parameters after * we start the new task; the new task will not actually begin execution * until we re-enable pre-emption. @@ -171,13 +177,11 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, /* Start the task */ - pid = exec(path, (FAR const char **)argv, &CONFIG_EXECFUNCS_SYMTAB, - CONFIG_EXECFUNCS_NSYMBOLS); - + pid = exec(path, (FAR const char **)argv, symtab, nsymbols); if (pid < 0) { ret = errno; - sdbg("exec failed: %d\n", ret); + sdbg("ERROR: exec failed: %d\n", ret); goto errout; } @@ -211,6 +215,9 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) == 0) { + svdbg("Setting priority=%d for pid=%d\n", + param.sched_priority, pid); + (void)sched_setparam(pid, ¶m); } } @@ -231,6 +238,9 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) { + svdbg("Setting policy=%d priority=%d for pid=%d\n", + attr->policy, param.sched_priority, pid); + (void)sched_setscheduler(pid, attr->policy, ¶m); } } @@ -262,18 +272,27 @@ static inline int spawn_close(FAR struct spawn_close_file_action_s *action) { /* The return value from close() is ignored */ + svdbg("Closing fd=%d\n", action->fd); + (void)close(action->fd); return OK; } static inline int spawn_dup2(FAR struct spawn_dup2_file_action_s *action) { + int ret; + /* Perform the dup */ - int ret = dup2(action->fd1, action->fd2); + svdbg("Dup'ing %d->%d\n", action->fd1, action->fd2); + + ret = dup2(action->fd1, action->fd2); if (ret < 0) { - return errno; + int errcode = errno; + + sdbg("ERROR: dup2 failed: %d\n", errcode); + return errcode; } return OK; @@ -286,10 +305,14 @@ static inline int spawn_open(FAR struct spawn_open_file_action_s *action) /* Open the file */ + svdbg("Open'ing path=%s oflags=%04x mode=%04x\n", + action->path, action->oflags, action->mode); + fd = open(action->path, action->oflags, action->mode); if (fd < 0) { ret = errno; + sdbg("ERROR: open failed: %d\n", ret); } /* Does the return file descriptor happen to match the required file @@ -300,12 +323,16 @@ static inline int spawn_open(FAR struct spawn_open_file_action_s *action) { /* No.. dup2 to get the correct file number */ + svdbg("Dup'ing %d->%d\n", fd, action->fd); + ret = dup2(fd, action->fd); if (ret < 0) { ret = errno; + sdbg("ERROR: dup2 failed: %d\n", ret); } + svdbg("Closing fd=%d\n", fd); close(fd); } @@ -379,6 +406,7 @@ static int spawn_proxy(int argc, char *argv[]) case SPAWN_FILE_ACTION_NONE: default: + sdbg("ERROR: Unknown action: %d\n", entry->action); ret = EINVAL; break; } @@ -517,6 +545,9 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, DEBUGASSERT(path); + svdbg("pid=%p path=%s file_actions=%p attr=%p argv=%p\n", + pid, path, file_actions, attr, argv); + /* If there are no file actions to be performed and there is no change to * the signal mask, then start the new child task directly from the parent task. */ @@ -559,8 +590,11 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, ret = sched_getparam(0, ¶m); if (ret < 0) { + int errcode = errno; + + sdbg("ERROR: sched_getparam failed: %d\n", errcode); ps_semgive(&g_ps_parmsem); - return errno; + return errcode; } /* Start the intermediary/proxy task at the same priority as the parent task. */ @@ -570,8 +604,11 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, (const char **)NULL); if (proxy < 0) { + int errcode = errno; + + sdbg("ERROR: Failed to start spawn_proxy: %d\n", errcode); ps_semgive(&g_ps_parmsem); - return errno; + return errcode; } /* Wait for the proxy to complete its job */ diff --git a/nuttx/libc/spawn/spawn.h b/nuttx/libc/spawn/spawn.h index 5d0159ff2..3f4e195cc 100644 --- a/nuttx/libc/spawn/spawn.h +++ b/nuttx/libc/spawn/spawn.h @@ -1,7 +1,7 @@ /**************************************************************************** * libc/spawn/spawn.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/libc/unistd/Make.defs b/nuttx/libc/unistd/Make.defs index 3811673bf..ee3ac0fc9 100644 --- a/nuttx/libc/unistd/Make.defs +++ b/nuttx/libc/unistd/Make.defs @@ -43,7 +43,7 @@ CSRCS += lib_chdir.c lib_getcwd.c endif ifeq ($(CONFIG_LIBC_EXECFUNCS),y) -CSRCS += lib_execl.c lib_execv.c +CSRCS += lib_execl.c lib_execv.c lib_execsymtab.c endif endif diff --git a/nuttx/libc/unistd/lib_execsymtab.c b/nuttx/libc/unistd/lib_execsymtab.c new file mode 100644 index 000000000..e95107d15 --- /dev/null +++ b/nuttx/libc/unistd/lib_execsymtab.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * libc/unistd/lib_execsymtab.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#ifdef CONFIG_LIBC_EXECFUNCS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* If CONFIG_LIBC_EXECFUNCS is defined in the configuration, then the + * following must also be defined: + */ + +/* Symbol table used by exec[l|v] */ + +#ifndef CONFIG_EXECFUNCS_SYMTAB +# error "CONFIG_EXECFUNCS_SYMTAB must be defined" +#endif + +/* Number of Symbols in the Table */ + +#ifndef CONFIG_EXECFUNCS_NSYMBOLS +# error "CONFIG_EXECFUNCS_NSYMBOLS must be defined" +#endif + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct symtab_s *g_exec_symtab = &CONFIG_EXECFUNCS_SYMTAB; +static int g_exec_nsymbols = CONFIG_EXECFUNCS_NSYMBOLS; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: exec_getsymtab + * + * Description: + * Get the current symbol table selection as an atomic operation. + * + * Input Parameters: + * symtab - The location to store the symbol table. + * nsymbols - The location to store the number of symbols in the symbol table. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void exec_getsymtab(FAR struct symtab_s **symtab, FAR int *nsymbols) +{ + irqstate_t flags; + + DEBUGASSERT(symtab && nsymbols); + + /* Disable interrupts very briefly so that both the symbol table and its + * size are returned as a single atomic operation. + */ + + flags = irqsave(); + *symtab = g_exec_symtab; + *nsymbols = g_exec_nsymbols; + irqrestore(flags); +} + +/**************************************************************************** + * Name: exec_setsymtab + * + * Description: + * Select a new symbol table selection as an atomic operation. + * + * Input Parameters: + * symtab - The new symbol table. + * nsymbols - The number of symbols in the symbol table. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void exec_setsymtab(FAR const struct symtab_s *symtab, int nsymbols) +{ + irqstate_t flags; + + DEBUGASSERT(symtab); + + /* Disable interrupts very briefly so that both the symbol table and its + * size are set as a single atomic operation. + */ + + flags = irqsave(); + g_exec_symtab = symtab; + g_exec_nsymbols = nsymbols; + irqrestore(flags); +} + +#endif /* CONFIG_LIBC_EXECFUNCS */ \ No newline at end of file diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c index 6d09bf481..e35138be5 100644 --- a/nuttx/libc/unistd/lib_execv.c +++ b/nuttx/libc/unistd/lib_execv.c @@ -51,27 +51,6 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* If CONFIG_LIBC_EXECFUNCS is defined in the configuration, then the - * following must also be defined: - */ - -/* Symbol table used by exec[l|v] */ - -#ifndef CONFIG_EXECFUNCS_SYMTAB -# error "CONFIG_EXECFUNCS_SYMTAB must be defined" -#endif - -/* Number of Symbols in the Table */ - -#ifndef CONFIG_EXECFUNCS_NSYMBOLS -# error "CONFIG_EXECFUNCS_NSYMBOLS must be defined" -#endif - -/**************************************************************************** - * Public Variables - ****************************************************************************/ - -extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; /**************************************************************************** * Private Variables @@ -140,13 +119,17 @@ extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; int execv(FAR const char *path, FAR char *const argv[]) { + FAR struct symtab_s *symtab; + int nsymbols; int ret; - /* Start the task */ + /* Get the current symbol table selection */ - ret = exec(path, (FAR const char **)argv, - &CONFIG_EXECFUNCS_SYMTAB, CONFIG_EXECFUNCS_NSYMBOLS); + exec_getsymtab(&symtab, &nsymbols); + + /* Start the task */ + ret = exec(path, (FAR const char **)argv, symtab, nsymbols); if (ret < 0) { sdbg("exec failed: %d\n", errno); -- cgit v1.2.3 From f011bd7ef6f91261969ae08655016b8a7b41a796 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 21:39:57 +0000 Subject: Added a test of posix_spawn() git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5507 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 1 + apps/examples/Kconfig | 1 + apps/examples/elf/tests/Makefile | 18 +- apps/examples/elf/tests/mksymtab.sh | 18 +- apps/examples/nxflat/tests/Makefile | 4 +- apps/examples/posix_spawn/Kconfig | 29 + apps/examples/posix_spawn/Makefile | 110 ++++ apps/examples/posix_spawn/filesystem/Makefile | 85 +++ apps/examples/posix_spawn/filesystem/mksymtab.sh | 51 ++ .../posix_spawn/filesystem/program/Makefile | 59 ++ .../posix_spawn/filesystem/program/program.c | 60 ++ apps/examples/posix_spawn/filesystem/testdata.txt | 2 + apps/examples/posix_spawn/spawn_main.c | 356 ++++++++++++ nuttx/ChangeLog | 2 + .../configs/stm32f4discovery/posix_spawn/Make.defs | 130 +++++ .../configs/stm32f4discovery/posix_spawn/defconfig | 625 +++++++++++++++++++++ .../configs/stm32f4discovery/posix_spawn/setenv.sh | 79 +++ nuttx/libc/unistd/lib_execsymtab.c | 6 +- 18 files changed, 1605 insertions(+), 31 deletions(-) create mode 100644 apps/examples/posix_spawn/Kconfig create mode 100644 apps/examples/posix_spawn/Makefile create mode 100644 apps/examples/posix_spawn/filesystem/Makefile create mode 100755 apps/examples/posix_spawn/filesystem/mksymtab.sh create mode 100644 apps/examples/posix_spawn/filesystem/program/Makefile create mode 100644 apps/examples/posix_spawn/filesystem/program/program.c create mode 100644 apps/examples/posix_spawn/filesystem/testdata.txt create mode 100644 apps/examples/posix_spawn/spawn_main.c create mode 100644 nuttx/configs/stm32f4discovery/posix_spawn/Make.defs create mode 100644 nuttx/configs/stm32f4discovery/posix_spawn/defconfig create mode 100755 nuttx/configs/stm32f4discovery/posix_spawn/setenv.sh diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index cd15b430d..6b63527a7 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -461,4 +461,5 @@ the USB HID keyboard report data. * apps/examples/wlan: Remove non-functional example. * apps/examples/ostest/vfork.c: Added a test of vfork(). + * apps/exampes/posix_spawn: Added a test of poxis_spawn(). diff --git a/apps/examples/Kconfig b/apps/examples/Kconfig index b0cbd7088..ec0a97dd4 100644 --- a/apps/examples/Kconfig +++ b/apps/examples/Kconfig @@ -39,6 +39,7 @@ source "$APPSDIR/examples/pashello/Kconfig" source "$APPSDIR/examples/pipe/Kconfig" source "$APPSDIR/examples/poll/Kconfig" source "$APPSDIR/examples/pwm/Kconfig" +source "$APPSDIR/examples/posix_spawn/Kconfig" source "$APPSDIR/examples/qencoder/Kconfig" source "$APPSDIR/examples/relays/Kconfig" source "$APPSDIR/examples/rgmp/Kconfig" diff --git a/apps/examples/elf/tests/Makefile b/apps/examples/elf/tests/Makefile index 778dd6480..755199506 100644 --- a/apps/examples/elf/tests/Makefile +++ b/apps/examples/elf/tests/Makefile @@ -66,7 +66,7 @@ SYMTAB_SRC = $(TESTS_DIR)/symtab.c define DIR_template $(1)_$(2): - @$(MAKE) -C $(1) $(3) TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" CROSSDEV=$(CROSSDEV) + $(Q) $(MAKE) -C $(1) $(3) TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" CROSSDEV=$(CROSSDEV) endef all: $(ROMFS_HDR) $(DIRLIST_HDR) $(SYMTAB_SRC) @@ -87,7 +87,7 @@ install: $(foreach DIR, $(BUILD_SUBDIRS), $(DIR)_install) # Create the romfs directory $(ROMFS_DIR): - @mkdir $(ROMFS_DIR) + $(Q) mkdir $(ROMFS_DIR) # Populate the romfs directory @@ -96,25 +96,25 @@ populate: $(ROMFS_DIR) build install # Create the romfs.img file from the populated romfs directory $(ROMFS_IMG): populate - @genromfs -f $@ -d $(ROMFS_DIR) -V "ELFTEST" + $(Q) genromfs -f $@ -d $(ROMFS_DIR) -V "ELFTEST" # Create the romfs.h header file from the romfs.img file $(ROMFS_HDR) : $(ROMFS_IMG) - @(cd $(TESTS_DIR); xxd -i romfs.img | sed -e "s/^unsigned/static const unsigned/g" >$@) + $(Q) (cd $(TESTS_DIR); xxd -i romfs.img | sed -e "s/^unsigned/static const unsigned/g" >$@) # Create the dirlist.h header file from the romfs directory $(DIRLIST_HDR) : populate - @$(TESTS_DIR)/mkdirlist.sh $(ROMFS_DIR) >$@ + $(Q) $(TESTS_DIR)/mkdirlist.sh $(ROMFS_DIR) >$@ -# Create the exported symbol table list from the derived *-thunk.S files +# Create the exported symbol table $(SYMTAB_SRC): build - @$(TESTS_DIR)/mksymtab.sh -t varlist.tmp $(ROMFS_DIR) >$@ + $(Q) $(TESTS_DIR)/mksymtab.sh $(ROMFS_DIR) >$@ # Clean each subdirectory clean: $(foreach DIR, $(ALL_SUBDIRS), $(DIR)_clean) - @rm -f $(ROMFS_HDR) $(ROMFS_IMG) $(SYMTAB_SRC) varlist.tmp - @rm -rf $(ROMFS_DIR) $(DIRLIST_HDR) + $(Q) rm -f $(ROMFS_HDR) $(DIRLIST_HDR) $(ROMFS_IMG) $(SYMTAB_SRC) + $(Q) rm -rf $(ROMFS_DIR) diff --git a/apps/examples/elf/tests/mksymtab.sh b/apps/examples/elf/tests/mksymtab.sh index 56be10f73..51408a89c 100755 --- a/apps/examples/elf/tests/mksymtab.sh +++ b/apps/examples/elf/tests/mksymtab.sh @@ -1,22 +1,6 @@ #!/bin/bash -usage="Usage: $0 [-t ] " - -# Check for the optional tempory file name - -tmpfile=varlist.tmp -if [ "X${1}" = "X-t" ]; then - shift - tmpfile=$1 - shift - - if [ -z "$tmpfile" ]; then - echo "ERROR: Missing " - echo "" - echo $usage - exit 1 - fi -fi +usage="Usage: $0 " # Check for the required ROMFS directory path diff --git a/apps/examples/nxflat/tests/Makefile b/apps/examples/nxflat/tests/Makefile index 4979c7fd4..53e43288f 100644 --- a/apps/examples/nxflat/tests/Makefile +++ b/apps/examples/nxflat/tests/Makefile @@ -97,7 +97,7 @@ $(SYMTAB): build # Clean each subdirectory clean: $(foreach DIR, $(SUBDIRS), $(DIR)_clean) - @rm -f $(ROMFS_HDR) $(ROMFS_IMG) $(SYMTAB) - @rm -rf $(ROMFS_DIR) $(ROMFS_DIRLIST) + @rm -f $(ROMFS_HDR) $(ROMFS_DIRLIST) $(ROMFS_IMG) $(SYMTAB) + @rm -rf $(ROMFS_DIR) diff --git a/apps/examples/posix_spawn/Kconfig b/apps/examples/posix_spawn/Kconfig new file mode 100644 index 000000000..508065913 --- /dev/null +++ b/apps/examples/posix_spawn/Kconfig @@ -0,0 +1,29 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +config EXAMPLES_POSIXSPAWN + bool "posix_spawn Unit Test" + default n + ---help--- + Enable the posix_spawn() unit test + +if EXAMPLES_POSIXSPAWN +config EXAMPLES_POSIXSPAWN_DEVMINOR + int "ROMFS Minor Device Number" + default 0 + ---help--- + The minor device number of the ROMFS block. For example, the N in /dev/ramN. + Used for registering the RAM block driver that will hold the ROMFS file system + containing the ELF executables to be tested. Default: 0 + +config EXAMPLES_POSIXSPAWN_DEVPATH + string "ROMFS Devie Path" + default "/dev/ram0" + ---help--- + The path to the ROMFS block driver device. This must match EXAMPLES_POSIXSPAWN_DEVMINOR. + Used for registering the RAM block driver that will hold the ROMFS file system + containing the ELF executables to be tested. Default: "/dev/ram0" + +endif diff --git a/apps/examples/posix_spawn/Makefile b/apps/examples/posix_spawn/Makefile new file mode 100644 index 000000000..d21c8f856 --- /dev/null +++ b/apps/examples/posix_spawn/Makefile @@ -0,0 +1,110 @@ +############################################################################ +# apps/examples/posix_spawn/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/.config +-include $(TOPDIR)/Make.defs +include $(APPDIR)/Make.defs + +# ELF Example + +ASRCS = +CSRCS = spawn_main.c symtab.c + +AOBJS = $(ASRCS:.S=$(OBJEXT)) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BIN = ..\..\libapps$(LIBEXT) +else +ifeq ($(WINTOOL),y) + BIN = ..\\..\\libapps$(LIBEXT) +else + BIN = ../../libapps$(LIBEXT) +endif +endif + +ROOTDEPPATH = --dep-path . --dep-path filesystem + +# Build targets + +VPATH = filesystem + +all: .built +.PHONY: really_build clean_filesystem clean depend distclean + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# This is a little messy. The build is broken into two pieces: (1) the +# filesystem/ subdir build that auto-generates several files, and (2) the real +# build. This is done because we need a fresh build context after auto- +# generating the source files. + +really_build: $(OBJS) + $(call ARCHIVE, $(BIN), $(OBJS)) + @touch .built + +.built: + @$(MAKE) -C filesystem TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" CROSSDEV=$(CROSSDEV) + @$(MAKE) TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" really_build + +context: + +# We can't make dependencies in this directory because the required +# header files may not yet exist. + +.depend: + @touch $@ + +depend: .depend + +clean_filesystem: + @$(MAKE) -C filesystem TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" CROSSDEV=$(CROSSDEV) clean + +clean: clean_filesystem + $(call DELFILE, .built) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/apps/examples/posix_spawn/filesystem/Makefile b/apps/examples/posix_spawn/filesystem/Makefile new file mode 100644 index 000000000..19a02bb80 --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/Makefile @@ -0,0 +1,85 @@ +############################################################################ +# apps/examples/posix_spawn/filesystem/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +include $(APPDIR)$(DELIM)Make.defs + +SPAWN_DIR = $(APPDIR)$(DELIM)examples$(DELIM)posix_spawn +FILESYSTEM_DIR = $(SPAWN_DIR)$(DELIM)filesystem +ROMFS_DIR = $(FILESYSTEM_DIR)$(DELIM)romfs +ROMFS_IMG = $(FILESYSTEM_DIR)$(DELIM)romfs.img +ROMFS_HDR = $(FILESYSTEM_DIR)$(DELIM)romfs.h +SYMTAB_SRC = $(FILESYSTEM_DIR)$(DELIM)symtab.c + +all: $(ROMFS_HDR) $(SYMTAB_SRC) +.PHONY: all program clean install populate + +# Create the romfs directory + +$(ROMFS_DIR): + $(Q) mkdir $(ROMFS_DIR) + +# Build the test program + +program: $(ROMFS_DIR) + $(Q) $(MAKE) -C program program TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + +# Install the test program in the romfs directory + +install: program testdata.txt + $(Q) $(MAKE) -C program install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + $(Q) install --mode=0644 testdata.txt $(ROMFS_DIR)/testdata.txt + +# Create the romfs.img file from the romfs directory + +$(ROMFS_IMG): install + $(Q) genromfs -f $@ -d $(ROMFS_DIR) -V "POSIXSPAWN" + +# Create the romfs.h header file from the romfs.img file + +$(ROMFS_HDR) : $(ROMFS_IMG) + $(Q) (cd $(FILESYSTEM_DIR); xxd -i romfs.img | sed -e "s/^unsigned/static const unsigned/g" >$@) + +# Create the exported symbol table + +$(SYMTAB_SRC): program + $(Q) $(FILESYSTEM_DIR)$(DELIM)mksymtab.sh $(ROMFS_DIR) >$@ + +# Clean each subdirectory + +clean: + $(Q) $(MAKE) -C program clean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + $(Q) rm -f $(ROMFS_HDR) $(ROMFS_IMG) $(SYMTAB_SRC) + $(Q) rm -rf $(ROMFS_DIR) diff --git a/apps/examples/posix_spawn/filesystem/mksymtab.sh b/apps/examples/posix_spawn/filesystem/mksymtab.sh new file mode 100755 index 000000000..51408a89c --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/mksymtab.sh @@ -0,0 +1,51 @@ +#!/bin/bash + +usage="Usage: $0 " + +# Check for the required ROMFS directory path + +dir=$1 +if [ -z "$dir" ]; then + echo "ERROR: Missing " + echo "" + echo $usage + exit 1 +fi + +if [ ! -d "$dir" ]; then + echo "ERROR: Directory $dir does not exist" + echo "" + echo $usage + exit 1 +fi + +# Extract all of the undefined symbols from the ELF files and create a +# list of sorted, unique undefined variable names. + +varlist=`find ${dir} -executable -type f | xargs nm | fgrep ' U ' | sed -e "s/^[ ]*//g" | cut -d' ' -f2 | sort | uniq` + +# Now output the symbol table as a structure in a C source file. All +# undefined symbols are declared as void* types. If the toolchain does +# any kind of checking for function vs. data objects, then this could +# faile + +echo "#include " +echo "#include " +echo "" + +for var in $varlist; do + echo "extern void *${var};" +done + +echo "" +echo "const struct symtab_s exports[] = " +echo "{" + +for var in $varlist; do + echo " {\"${var}\", &${var}}," +done + +echo "};" +echo "" +echo "const int nexports = sizeof(exports) / sizeof(struct symtab_s);" + diff --git a/apps/examples/posix_spawn/filesystem/program/Makefile b/apps/examples/posix_spawn/filesystem/program/Makefile new file mode 100644 index 000000000..cf55797b2 --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/program/Makefile @@ -0,0 +1,59 @@ +############################################################################ +# examples/posix_spawn/filesystem/program/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +BIN = program + +SRCS = $(BIN).c +OBJS = $(SRCS:.c=.o) + +all: $(BIN) + +$(OBJS): %.o: %.c + @echo "CC: $<" + $(Q) $(CC) -c $(CELFFLAGS) $< -o $@ + +$(BIN): $(OBJS) + @echo "LD: $<" + $(Q) $(LD) $(LDELFFLAGS) -o $@ $^ + +clean: + $(call DELFILE, $(BIN)) + $(call CLEAN) + +install: + $(Q) mkdir -p $(ROMFS_DIR) + $(Q) install --mode=0755 $(BIN) $(ROMFS_DIR)/$(BIN) diff --git a/apps/examples/posix_spawn/filesystem/program/program.c b/apps/examples/posix_spawn/filesystem/program/program.c new file mode 100644 index 000000000..f63b559c8 --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/program/program.c @@ -0,0 +1,60 @@ +/**************************************************************************** + * examples/posix_spawn/filesystem/program/program.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int main(int argc, char **argv) +{ + int ch; + + /* stdin should have been redirected to testdata.txt. Read and print until + * we hit the end of file. + */ + + while ((ch = getchar()) != EOF) + { + putchar(ch); + } + + return 0; +} diff --git a/apps/examples/posix_spawn/filesystem/testdata.txt b/apps/examples/posix_spawn/filesystem/testdata.txt new file mode 100644 index 000000000..bb581fbb5 --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/testdata.txt @@ -0,0 +1,2 @@ +Now is the time for all good men to come to the aid of their party. + diff --git a/apps/examples/posix_spawn/spawn_main.c b/apps/examples/posix_spawn/spawn_main.c new file mode 100644 index 000000000..3e3a7b1b1 --- /dev/null +++ b/apps/examples/posix_spawn/spawn_main.c @@ -0,0 +1,356 @@ +/**************************************************************************** + * examples/posix_spawn/spawn_main.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "filesystem/romfs.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Check configuration. This is not all of the configuration settings that + * are required -- only the more obvious. + */ + +#if CONFIG_NFILE_DESCRIPTORS < 1 +# error "You must provide file descriptors via CONFIG_NFILE_DESCRIPTORS in your configuration file" +#endif + +#ifdef CONFIG_BINFMT_DISABLE +# error "The binary loader is disabled (CONFIG_BINFMT_DISABLE)!" +#endif + +#ifndef CONFIG_ELF +# error "You must select CONFIG_ELF in your configuration file" +#endif + +#ifndef CONFIG_FS_ROMFS +# error "You must select CONFIG_FS_ROMFS in your configuration file" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "You must not disable mountpoints via CONFIG_DISABLE_MOUNTPOINT in your configuration file" +#endif + +#ifdef CONFIG_BINFMT_DISABLE +# error "You must not disable loadable modules via CONFIG_BINFMT_DISABLE in your configuration file" +#endif + +/* Describe the ROMFS file system */ + +#define SECTORSIZE 512 +#define NSECTORS(b) (((b)+SECTORSIZE-1)/SECTORSIZE) +#define MOUNTPT "/mnt/romfs" + +#ifndef CONFIG_EXAMPLES_ELF_DEVMINOR +# define CONFIG_EXAMPLES_ELF_DEVMINOR 0 +#endif + +#ifndef CONFIG_EXAMPLES_ELF_DEVPATH +# define CONFIG_EXAMPLES_ELF_DEVPATH "/dev/ram0" +#endif + +/* If CONFIG_DEBUG is enabled, use dbg instead of printf so that the + * output will be synchronous with the debug output. + */ + +#ifdef CONFIG_CPP_HAVE_VARARGS +# ifdef CONFIG_DEBUG +# define message(format, arg...) dbg(format, ##arg) +# define err(format, arg...) dbg(format, ##arg) +# else +# define message(format, arg...) printf(format, ##arg) +# define err(format, arg...) fprintf(stderr, format, ##arg) +# endif +#else +# ifdef CONFIG_DEBUG +# define message dbg +# define err dbg +# else +# define message printf +# define err printf +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static unsigned int g_mminitial; /* Initial memory usage */ +static unsigned int g_mmstep; /* Memory Usage at beginning of test step */ + +static const char delimiter[] = + "****************************************************************************"; +static const char program[] = "program"; +static const char data[] = "testdata.txt"; + +static char fullpath[128]; + +/**************************************************************************** + * Symbols from Auto-Generated Code + ****************************************************************************/ + +extern const struct symtab_s exports[]; +extern const int nexports; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mm_update + ****************************************************************************/ + +static void mm_update(FAR unsigned int *previous, FAR const char *msg) +{ + struct mallinfo mmcurrent; + + /* Get the current memory usage */ + +#ifdef CONFIG_CAN_PASS_STRUCTS + mmcurrent = mallinfo(); +#else + (void)mallinfo(&mmcurrent); +#endif + + /* Show the change from the previous time */ + + printf("\nMemory Usage %s:\n", msg); + printf(" Before: %8u After: %8u Change: %8d\n", + *previous, mmcurrent.uordblks, (int)mmcurrent.uordblks - (int)*previous); + + /* Set up for the next test */ + + *previous = mmcurrent.uordblks; +} + +/**************************************************************************** + * Name: mm_initmonitor + ****************************************************************************/ + +static void mm_initmonitor(void) +{ + struct mallinfo mmcurrent; + +#ifdef CONFIG_CAN_PASS_STRUCTS + mmcurrent = mallinfo(); +#else + (void)mallinfo(&mmcurrent); +#endif + + g_mminitial = mmcurrent.uordblks; + g_mmstep = mmcurrent.uordblks; + + printf("Initial memory usage: %d\n", mmcurrent.uordblks); +} + +/**************************************************************************** + * Name: testheader + ****************************************************************************/ + +static inline void testheader(FAR const char *progname) +{ + message("\n%s\n* Executing %s\n%s\n\n", delimiter, progname, delimiter); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spawn_main + ****************************************************************************/ + +int spawn_main(int argc, char *argv[]) +{ + posix_spawn_file_actions_t file_actions; + posix_spawnattr_t attr; + FAR const char *filepath; + pid_t pid; + int ret; + + /* Initialize the memory monitor */ + + mm_initmonitor(); + + /* Initialize the ELF binary loader */ + + message("Initializing the ELF binary loader\n"); + ret = elf_initialize(); + if (ret < 0) + { + err("ERROR: Initialization of the ELF loader failed: %d\n", ret); + exit(1); + } + + mm_update(&g_mmstep, "after elf_initialize"); + + /* Create a ROM disk for the ROMFS filesystem */ + + message("Registering romdisk at /dev/ram%d\n", CONFIG_EXAMPLES_ELF_DEVMINOR); + ret = romdisk_register(CONFIG_EXAMPLES_ELF_DEVMINOR, (FAR uint8_t *)romfs_img, + NSECTORS(romfs_img_len), SECTORSIZE); + if (ret < 0) + { + err("ERROR: romdisk_register failed: %d\n", ret); + elf_uninitialize(); + exit(1); + } + + mm_update(&g_mmstep, "after romdisk_register"); + + /* Mount the file system */ + + message("Mounting ROMFS filesystem at target=%s with source=%s\n", + MOUNTPT, CONFIG_EXAMPLES_ELF_DEVPATH); + + ret = mount(CONFIG_EXAMPLES_ELF_DEVPATH, MOUNTPT, "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + err("ERROR: mount(%s,%s,romfs) failed: %s\n", + CONFIG_EXAMPLES_ELF_DEVPATH, MOUNTPT, errno); + elf_uninitialize(); + } + + mm_update(&g_mmstep, "after mount"); + + /* Does the system support the PATH variable? Has the PATH variable + * already been set? If YES and NO, then set the PATH variable to + * the ROMFS mountpoint. + */ + +#if defined(CONFIG_BINFMT_EXEPATH) && !defined(CONFIG_PATH_INITIAL) + (void)setenv("PATH", MOUNTPT, 1); +#endif + + /* Make sure that we are using our symbol take */ + + exec_setsymtab(exports, nexports); + + /* Output a seperated so that we can clearly discriminate the output of + * this program from the others. + */ + + testheader(program); + + /* Initialize the attributes file actions structure */ + + ret = posix_spawn_file_actions_init(&file_actions); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_init failed: %d\n", ret); + } + + ret = posix_spawnattr_init(&attr); + if (ret != 0) + { + err("ERROR: posix_spawnattr_init failed: %d\n", ret); + } + + /* Set up to close stdin (0) and open testdata.txt as the program input */ + + ret = posix_spawn_file_actions_addclose(&file_actions, 0); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_addclose failed: %d\n", ret); + } + + snprintf(fullpath, 128, "%s/%s", MOUNTPT, data); + ret = posix_spawn_file_actions_addopen(&file_actions, 0, fullpath, O_RDONLY, 0644); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_addopen failed: %d\n", ret); + } + + /* If the binary loader does not support the PATH variable, then + * create the full path to the executable program. Otherwise, + * use the relative path so that the binary loader will have to + * search the PATH variable to find the executable. + */ + +#ifdef CONFIG_BINFMT_EXEPATH + filepath = program; +#else + snprintf(fullpath, 128, "%s/%s", MOUNTPT, program); + filepath = fullpath; +#endif + + /* Execute the program */ + + mm_update(&g_mmstep, "before posix_spawn"); + + ret = posix_spawn(&pid, filepath, &file_actions, &attr, NULL, NULL); + if (ret != 0) + { + err("ERROR: posix_spawn failed: %d\n", ret); + } + + sleep(1); + mm_update(&g_mmstep, "after posix_spawn"); + + /* Clean-up */ + + (void)posix_spawn_file_actions_destroy(&file_actions); + (void)posix_spawnattr_destroy(&attr); + elf_uninitialize(); + + mm_update(&g_mmstep, "End-of-Test"); + return 0; +} diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 421b1ca60..7ddc4901e 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3903,4 +3903,6 @@ untested and undocumented. * drivers/usbdev/pl2303.c: Fix typols in the PL2303 driver (from Max Holtzberg). + * configs/stm32f4discovery/posix_spawn: Added a configuration + that can be used for testing posix_spawn(). diff --git a/nuttx/configs/stm32f4discovery/posix_spawn/Make.defs b/nuttx/configs/stm32f4discovery/posix_spawn/Make.defs new file mode 100644 index 000000000..34b9f7feb --- /dev/null +++ b/nuttx/configs/stm32f4discovery/posix_spawn/Make.defs @@ -0,0 +1,130 @@ +############################################################################ +# configs/stm32f4discovery/posix_spawn/Make.defs +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +ifeq ($(WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld}" +else + LDELFFLAGS += -T $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld +endif + +# File extensions + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +# Linker flags + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +# Host tools + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/stm32f4discovery/posix_spawn/defconfig b/nuttx/configs/stm32f4discovery/posix_spawn/defconfig new file mode 100644 index 000000000..b908393d8 --- /dev/null +++ b/nuttx/configs/stm32f4discovery/posix_spawn/defconfig @@ -0,0 +1,625 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM4=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F103RET6 is not set +# CONFIG_ARCH_CHIP_STM32F103VCT6 is not set +# CONFIG_ARCH_CHIP_STM32F103VET6 is not set +# CONFIG_ARCH_CHIP_STM32F103ZET6 is not set +# CONFIG_ARCH_CHIP_STM32F105VBT7 is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +CONFIG_ARCH_CHIP_STM32F407VG=y +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_WWDG is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_STM32_CCMEXCLUDE=y + +# +# U[S]ART Configuration +# +# CONFIG_USART2_RS485 is not set + +# +# USB Host Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x20000000 +CONFIG_DRAM_SIZE=114688 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f4discovery" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=10 +CONFIG_START_DAY=26 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="spawn_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_POLL is not set + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_USART2=y +CONFIG_MCU_SERIAL=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_FS_FAT is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_NXFFS is not set +CONFIG_FS_ROMFS=y + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +CONFIG_BINFMT_EXEPATH=y +CONFIG_PATH_INITIAL="/mnt/romfs" +# CONFIG_NXFLAT is not set +CONFIG_ELF=y +CONFIG_ELF_ALIGN_LOG2=2 +CONFIG_ELF_STACKSIZE=2048 +CONFIG_ELF_BUFFERSIZE=128 +CONFIG_ELF_BUFFERINCR=32 +# CONFIG_PIC is not set +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_EXECFUNCS_SYMTAB="exports" +CONFIG_EXECFUNCS_NSYMBOLS=10 +CONFIG_POSIX_SPAWN_STACKSIZE=768 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +# CONFIG_HAVE_CXXINITIALIZE is not set +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +CONFIG_EXAMPLES_POSIXSPAWN=y +CONFIG_EXAMPLES_POSIXSPAWN_DEVMINOR=0 +CONFIG_EXAMPLES_POSIXSPAWN_DEVPATH="/dev/ram0" +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/stm32f4discovery/posix_spawn/setenv.sh b/nuttx/configs/stm32f4discovery/posix_spawn/setenv.sh new file mode 100755 index 000000000..c06a15c9c --- /dev/null +++ b/nuttx/configs/stm32f4discovery/posix_spawn/setenv.sh @@ -0,0 +1,79 @@ +#!/bin/bash +# configs/stm32f4discovery/posix_spawn/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# This the the Cygwin path to the location where I built genromfs. If you use +# the buildroot toolchain, then genromfs can probably be found in TOOLCHAIN_DIR +export GENROMFS_PATH="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${GENROMFS_PATH}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/libc/unistd/lib_execsymtab.c b/nuttx/libc/unistd/lib_execsymtab.c index e95107d15..7abb2d74e 100644 --- a/nuttx/libc/unistd/lib_execsymtab.c +++ b/nuttx/libc/unistd/lib_execsymtab.c @@ -107,7 +107,7 @@ void exec_getsymtab(FAR struct symtab_s **symtab, FAR int *nsymbols) * size are returned as a single atomic operation. */ - flags = irqsave(); + flags = irqsave(); *symtab = g_exec_symtab; *nsymbols = g_exec_nsymbols; irqrestore(flags); @@ -138,8 +138,8 @@ void exec_setsymtab(FAR const struct symtab_s *symtab, int nsymbols) * size are set as a single atomic operation. */ - flags = irqsave(); - g_exec_symtab = symtab; + flags = irqsave(); + g_exec_symtab = symtab; g_exec_nsymbols = nsymbols; irqrestore(flags); } -- cgit v1.2.3 From 7609c9a19206ff0c19ef2e6cba4d6a5207d5cf30 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 10 Jan 2013 23:06:23 +0000 Subject: Fix problem with initialization of file actions git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5508 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/posix_spawn/spawn_main.c | 4 ++++ nuttx/libc/spawn/lib_psfa_init.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/apps/examples/posix_spawn/spawn_main.c b/apps/examples/posix_spawn/spawn_main.c index 3e3a7b1b1..608145232 100644 --- a/apps/examples/posix_spawn/spawn_main.c +++ b/apps/examples/posix_spawn/spawn_main.c @@ -304,6 +304,8 @@ int spawn_main(int argc, char *argv[]) err("ERROR: posix_spawnattr_init failed: %d\n", ret); } + mm_update(&g_mmstep, "after file_action/attr init"); + /* Set up to close stdin (0) and open testdata.txt as the program input */ ret = posix_spawn_file_actions_addclose(&file_actions, 0); @@ -319,6 +321,8 @@ int spawn_main(int argc, char *argv[]) err("ERROR: posix_spawn_file_actions_addopen failed: %d\n", ret); } + mm_update(&g_mmstep, "after adding file_actions"); + /* If the binary loader does not support the PATH variable, then * create the full path to the executable program. Otherwise, * use the relative path so that the binary loader will have to diff --git a/nuttx/libc/spawn/lib_psfa_init.c b/nuttx/libc/spawn/lib_psfa_init.c index cb638d6e7..4e23703ae 100644 --- a/nuttx/libc/spawn/lib_psfa_init.c +++ b/nuttx/libc/spawn/lib_psfa_init.c @@ -65,6 +65,6 @@ int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions) { - file_actions = NULL; + *file_actions = NULL; return OK; } -- cgit v1.2.3 From b26d1e14537568d79c5d805939408ecfca966072 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 11 Jan 2013 13:30:23 +0000 Subject: Update STM32 F1 DMA to parity with F2/F4 git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5509 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/stm32_serial.c | 121 +++++++++++++++++++---------- nuttx/arch/arm/src/stm32/stm32_uart.h | 7 +- nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c | 56 ++++++++++--- nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c | 11 ++- 4 files changed, 137 insertions(+), 58 deletions(-) diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index c7f97b25a..e86fbcf6f 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -79,22 +79,22 @@ #if SERIAL_HAVE_DMA -/* Verify that DMA has been enabled an the DMA channel has been defined. - * NOTE: These assignments may only be true for the F4. +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +/* Verify that DMA has been enabled and the DMA channel has been defined. */ -# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# endif # endif -# endif -# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ +# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1 +# endif # endif -# endif /* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack * of testing - RS-485 support was developed on STM32F1x @@ -114,28 +114,52 @@ * the following in the board.h file. */ -# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" -# endif +# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif -# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) -# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" -# endif +# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" +# endif -# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) -# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" -# endif +# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" +# endif -# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) -# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" -# endif +# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) +# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" +# endif -# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) -# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" -# endif +# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) +# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" +# endif + +# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) +# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" +# endif + +# elif defined(CONFIG_STM32_STM32F10XX) + +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ + defined(CONFIG_USART3_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +# if defined(CONFIG_UART4_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART4 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +/* There are no optional DMA channel assignments for the F1 */ + +# define DMAMAP_USART1_RX DMACHAN_USART1_RX +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX +# define DMAMAP_UART4_RX DMACHAN_USART4_RX -# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) -# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" # endif /* The DMA buffer size when using RX DMA to emulate a FIFO. @@ -169,6 +193,27 @@ # error "Unknown STM32 DMA" # endif +/* DMA control word */ + +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_SCR_DIR_P2M | \ + DMA_SCR_CIRC | \ + DMA_SCR_MINC | \ + DMA_SCR_PSIZE_8BITS | \ + DMA_SCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO | \ + DMA_SCR_PBURST_SINGLE | \ + DMA_SCR_MBURST_SINGLE) +# else +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO) +# endif + #endif /* Power management definitions */ @@ -1056,12 +1101,15 @@ static int up_dma_setup(struct uart_dev_s *dev) int result; uint32_t regval; - /* Do the basic UART setup first */ + /* Do the basic UART setup first, unless we are the console */ - result = up_setup(dev); - if (result != OK) - { - return result; + if (!dev->isconsole) + { + result = up_setup(dev); + if (result != OK) + { + return result; + } } /* Acquire the DMA channel. This should always succeed. */ @@ -1074,14 +1122,7 @@ static int up_dma_setup(struct uart_dev_s *dev) priv->usartbase + STM32_USART_DR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, - DMA_SCR_DIR_P2M | - DMA_SCR_CIRC | - DMA_SCR_MINC | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MSIZE_8BITS | - CONFIG_USART_DMAPRIO | - DMA_SCR_PBURST_SINGLE | - DMA_SCR_MBURST_SINGLE); + SERIAL_DMA_CONTROL_WORD); /* Reset our DMA shadow pointer to match the address just * programmed above. diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h index 8ff6a9975..a26ea2009 100644 --- a/nuttx/arch/arm/src/stm32/stm32_uart.h +++ b/nuttx/arch/arm/src/stm32/stm32_uart.h @@ -140,12 +140,9 @@ # undef HAVE_CONSOLE #endif -/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration. - * Furthermore, DMA support is currently only implemented for the F4 (but could be - * extended to the F1 and F2 with a little effort in the DMA code. - */ +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */ -#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) || !defined(CONFIG_STM32_STM32F40XX) +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) # undef CONFIG_USART1_RXDMA # undef CONFIG_USART2_RXDMA # undef CONFIG_USART3_RXDMA diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c index 89b279bea..13324b8ac 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -303,13 +303,13 @@ static int stm32_dmainterrupt(int irq, void *context) } dmach = &g_dma[chndx]; - /* Get the interrupt status (for this channel only) -- not currently used */ + /* Get the interrupt status (for this channel only) */ isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); - /* Disable the DMA channel */ + /* Clear the interrupts we are handling */ - stm32_dmachandisable(dmach); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); /* Invoke the callback */ @@ -528,14 +528,34 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; - /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is - * set and an interrupt is generated if the Half-Transfer Interrupt Enable - * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag - * (TCIF) is set and an interrupt is generated if the Transfer Complete - * Interrupt Enable bit (TCIE) is set. + /* In normal mode, interrupt at either half or full completion. In circular mode, + * always interrupt on buffer wrap, and optionally interrupt at the halfway point. */ - ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE)); + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is + * set and an interrupt is generated if the Half-Transfer Interrupt Enable + * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag + * (TCIF) is set and an interrupt is generated if the Transfer Complete + * Interrupt Enable bit (TCIE) is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE)); + + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full, or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } @@ -558,6 +578,24 @@ void stm32_dmastop(DMA_HANDLE handle) stm32_dmachandisable(dmach); } +/**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); +} + /**************************************************************************** * Name: stm32_dmasample * diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c index dcbbf1856..40fce8cb5 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -94,7 +94,6 @@ struct stm32_dma_s uint8_t irq; /* DMA stream IRQ number */ uint8_t shift; /* ISR/IFCR bit shift value */ uint8_t channel; /* DMA channel number (0-7) */ - bool nonstop; /* Stream is configured in a non-stopping mode. */ sem_t sem; /* Used to wait for DMA channel to become available */ uint32_t base; /* DMA register channel base address */ dma_callback_t callback; /* Callback invoked when the DMA completes */ @@ -728,7 +727,6 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_SCR_DBM|DMA_SCR_CIRC| DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); regval |= scr; - dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0; dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); } @@ -764,7 +762,12 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); scr |= DMA_SCR_EN; - if (!dmast->nonstop) + /* In normal mode, interrupt at either half or full completion. In circular + * and double-buffered modes, always interrupt on buffer wrap, and optionally + * interrupt at the halfway point. + */ + + if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0) { /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is * set and an interrupt is generated if the Half-Transfer Interrupt Enable @@ -777,7 +780,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool } else { - /* In nonstop mode, when the transfer completes it immediately resets + /* In non-stop modes, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always * enabled, and the half-complete interrupt can be used in circular * mode to determine when the buffer is half-full, or in double-buffered -- cgit v1.2.3 From e7a5090e55f7db78164fda2696af414c3e083806 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 11 Jan 2013 16:53:44 +0000 Subject: Various changes while debugging posix_spawn git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5510 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/elf/tests/hello/hello.c | 12 +- apps/examples/posix_spawn/Makefile | 17 +-- apps/examples/posix_spawn/filesystem/Makefile | 25 ++-- .../examples/posix_spawn/filesystem/hello/Makefile | 59 ++++++++++ apps/examples/posix_spawn/filesystem/hello/hello.c | 78 +++++++++++++ .../posix_spawn/filesystem/program/Makefile | 59 ---------- .../posix_spawn/filesystem/program/program.c | 60 ---------- .../posix_spawn/filesystem/redirect/Makefile | 59 ++++++++++ .../posix_spawn/filesystem/redirect/redirect.c | 63 ++++++++++ apps/examples/posix_spawn/spawn_main.c | 118 +++++++++++++++++-- nuttx/ChangeLog | 2 + nuttx/include/spawn.h | 12 +- nuttx/libc/spawn/Make.defs | 8 ++ nuttx/libc/spawn/lib_ps.c | 13 ++- nuttx/libc/spawn/lib_psa_dump.c | 127 ++++++++++++++++++++ nuttx/libc/spawn/lib_psa_init.c | 3 +- nuttx/libc/spawn/lib_psfa_dump.c | 129 +++++++++++++++++++++ nuttx/sched/task_vfork.c | 61 ++++++++++ 18 files changed, 745 insertions(+), 160 deletions(-) create mode 100644 apps/examples/posix_spawn/filesystem/hello/Makefile create mode 100644 apps/examples/posix_spawn/filesystem/hello/hello.c delete mode 100644 apps/examples/posix_spawn/filesystem/program/Makefile delete mode 100644 apps/examples/posix_spawn/filesystem/program/program.c create mode 100644 apps/examples/posix_spawn/filesystem/redirect/Makefile create mode 100644 apps/examples/posix_spawn/filesystem/redirect/redirect.c create mode 100644 nuttx/libc/spawn/lib_psa_dump.c create mode 100644 nuttx/libc/spawn/lib_psfa_dump.c diff --git a/apps/examples/elf/tests/hello/hello.c b/apps/examples/elf/tests/hello/hello.c index 6b1d079d8..bc4953e12 100644 --- a/apps/examples/elf/tests/hello/hello.c +++ b/apps/examples/elf/tests/hello/hello.c @@ -63,13 +63,13 @@ int main(int argc, char **argv) { printf("argv[%d]\t= ", i); if (argv[i]) - { - printf("(0x%p) \"%s\"\n", argv[i], argv[i]); - } + { + printf("(0x%p) \"%s\"\n", argv[i], argv[i]); + } else - { - printf("NULL?\n"); - } + { + printf("NULL?\n"); + } } printf("argv[%d]\t= 0x%p\n", argc, argv[argc]); diff --git a/apps/examples/posix_spawn/Makefile b/apps/examples/posix_spawn/Makefile index d21c8f856..bda3376d2 100644 --- a/apps/examples/posix_spawn/Makefile +++ b/apps/examples/posix_spawn/Makefile @@ -64,8 +64,8 @@ ROOTDEPPATH = --dep-path . --dep-path filesystem VPATH = filesystem -all: .built -.PHONY: really_build clean_filesystem clean depend distclean +all: build +.PHONY: build clean_filesystem clean depend distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -74,17 +74,16 @@ $(COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) # This is a little messy. The build is broken into two pieces: (1) the -# filesystem/ subdir build that auto-generates several files, and (2) the real +# filesystem/ subdir build that auto-generates several files, and (2) the library # build. This is done because we need a fresh build context after auto- # generating the source files. -really_build: $(OBJS) +build_lib: $(OBJS) $(call ARCHIVE, $(BIN), $(OBJS)) - @touch .built -.built: +build: @$(MAKE) -C filesystem TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" CROSSDEV=$(CROSSDEV) - @$(MAKE) TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" really_build + @$(MAKE) TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" build_lib context: @@ -100,11 +99,13 @@ clean_filesystem: @$(MAKE) -C filesystem TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" CROSSDEV=$(CROSSDEV) clean clean: clean_filesystem - $(call DELFILE, .built) $(call CLEAN) distclean: clean $(call DELFILE, Make.dep) $(call DELFILE, .depend) +# There are no dependencies in this directory. We should are code some of +# more important dependencies here: + -include Make.dep diff --git a/apps/examples/posix_spawn/filesystem/Makefile b/apps/examples/posix_spawn/filesystem/Makefile index 19a02bb80..2005d060f 100644 --- a/apps/examples/posix_spawn/filesystem/Makefile +++ b/apps/examples/posix_spawn/filesystem/Makefile @@ -44,22 +44,28 @@ ROMFS_HDR = $(FILESYSTEM_DIR)$(DELIM)romfs.h SYMTAB_SRC = $(FILESYSTEM_DIR)$(DELIM)symtab.c all: $(ROMFS_HDR) $(SYMTAB_SRC) -.PHONY: all program clean install populate +.PHONY: all hello redirect clean install populate # Create the romfs directory $(ROMFS_DIR): $(Q) mkdir $(ROMFS_DIR) -# Build the test program +# Build the hello test program -program: $(ROMFS_DIR) - $(Q) $(MAKE) -C program program TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" +hello: $(ROMFS_DIR) + $(Q) $(MAKE) -C hello hello TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" -# Install the test program in the romfs directory +# Build the redirection test program -install: program testdata.txt - $(Q) $(MAKE) -C program install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" +redirect: $(ROMFS_DIR) + $(Q) $(MAKE) -C redirect redirect TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + +# Install the test programs in the romfs directory + +install: hello redirect testdata.txt + $(Q) $(MAKE) -C hello install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + $(Q) $(MAKE) -C redirect install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" $(Q) install --mode=0644 testdata.txt $(ROMFS_DIR)/testdata.txt # Create the romfs.img file from the romfs directory @@ -74,12 +80,13 @@ $(ROMFS_HDR) : $(ROMFS_IMG) # Create the exported symbol table -$(SYMTAB_SRC): program +$(SYMTAB_SRC): hello/hello redirect/redirect testdata.txt $(Q) $(FILESYSTEM_DIR)$(DELIM)mksymtab.sh $(ROMFS_DIR) >$@ # Clean each subdirectory clean: - $(Q) $(MAKE) -C program clean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + $(Q) $(MAKE) -C hello clean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" + $(Q) $(MAKE) -C redirect clean TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" $(Q) rm -f $(ROMFS_HDR) $(ROMFS_IMG) $(SYMTAB_SRC) $(Q) rm -rf $(ROMFS_DIR) diff --git a/apps/examples/posix_spawn/filesystem/hello/Makefile b/apps/examples/posix_spawn/filesystem/hello/Makefile new file mode 100644 index 000000000..5cd80411b --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/hello/Makefile @@ -0,0 +1,59 @@ +############################################################################ +# examples/elf/tests/hello/Makefile +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +BIN = hello + +SRCS = $(BIN).c +OBJS = $(SRCS:.c=.o) + +all: $(BIN) + +$(OBJS): %.o: %.c + @echo "CC: $<" + $(Q) $(CC) -c $(CELFFLAGS) $< -o $@ + +$(BIN): $(OBJS) + @echo "LD: $<" + $(Q) $(LD) $(LDELFFLAGS) -o $@ $^ + +clean: + $(call DELFILE, $(BIN)) + $(call CLEAN) + +install: + $(Q) mkdir -p $(ROMFS_DIR) + $(Q) install $(BIN) $(ROMFS_DIR)/$(BIN) diff --git a/apps/examples/posix_spawn/filesystem/hello/hello.c b/apps/examples/posix_spawn/filesystem/hello/hello.c new file mode 100644 index 000000000..1b269d85f --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/hello/hello.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * examples/posix_spawn/filesystem/hello/hello.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int main(int argc, char **argv) +{ + int i; + + /* Mandatory "Hello, world!" */ + + puts("Getting ready to say \"Hello, world\"\n"); + printf("Hello, world!\n"); + puts("It has been said.\n"); + + /* Print arguments */ + + printf("argc\t= %d\n", argc); + printf("argv\t= 0x%p\n", argv); + + for (i = 0; i < argc; i++) + { + printf("argv[%d]\t= ", i); + if (argv[i]) + { + printf("(0x%p) \"%s\"\n", argv[i], argv[i]); + } + else + { + printf("NULL?\n"); + } + } + + printf("argv[%d]\t= 0x%p\n", argc, argv[argc]); + printf("Goodbye, world!\n"); + return 0; +} diff --git a/apps/examples/posix_spawn/filesystem/program/Makefile b/apps/examples/posix_spawn/filesystem/program/Makefile deleted file mode 100644 index cf55797b2..000000000 --- a/apps/examples/posix_spawn/filesystem/program/Makefile +++ /dev/null @@ -1,59 +0,0 @@ -############################################################################ -# examples/posix_spawn/filesystem/program/Makefile -# -# Copyright (C) 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -BIN = program - -SRCS = $(BIN).c -OBJS = $(SRCS:.c=.o) - -all: $(BIN) - -$(OBJS): %.o: %.c - @echo "CC: $<" - $(Q) $(CC) -c $(CELFFLAGS) $< -o $@ - -$(BIN): $(OBJS) - @echo "LD: $<" - $(Q) $(LD) $(LDELFFLAGS) -o $@ $^ - -clean: - $(call DELFILE, $(BIN)) - $(call CLEAN) - -install: - $(Q) mkdir -p $(ROMFS_DIR) - $(Q) install --mode=0755 $(BIN) $(ROMFS_DIR)/$(BIN) diff --git a/apps/examples/posix_spawn/filesystem/program/program.c b/apps/examples/posix_spawn/filesystem/program/program.c deleted file mode 100644 index f63b559c8..000000000 --- a/apps/examples/posix_spawn/filesystem/program/program.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * examples/posix_spawn/filesystem/program/program.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int main(int argc, char **argv) -{ - int ch; - - /* stdin should have been redirected to testdata.txt. Read and print until - * we hit the end of file. - */ - - while ((ch = getchar()) != EOF) - { - putchar(ch); - } - - return 0; -} diff --git a/apps/examples/posix_spawn/filesystem/redirect/Makefile b/apps/examples/posix_spawn/filesystem/redirect/Makefile new file mode 100644 index 000000000..421ff014a --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/redirect/Makefile @@ -0,0 +1,59 @@ +############################################################################ +# examples/posix_spawn/filesystem/redirect/Makefile +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +BIN = redirect + +SRCS = $(BIN).c +OBJS = $(SRCS:.c=.o) + +all: $(BIN) + +$(OBJS): %.o: %.c + @echo "CC: $<" + $(Q) $(CC) -c $(CELFFLAGS) $< -o $@ + +$(BIN): $(OBJS) + @echo "LD: $<" + $(Q) $(LD) $(LDELFFLAGS) -o $@ $^ + +clean: + $(call DELFILE, $(BIN)) + $(call CLEAN) + +install: + $(Q) mkdir -p $(ROMFS_DIR) + $(Q) install --mode=0755 $(BIN) $(ROMFS_DIR)/$(BIN) diff --git a/apps/examples/posix_spawn/filesystem/redirect/redirect.c b/apps/examples/posix_spawn/filesystem/redirect/redirect.c new file mode 100644 index 000000000..61638df79 --- /dev/null +++ b/apps/examples/posix_spawn/filesystem/redirect/redirect.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * examples/posix_spawn/filesystem/redirect/redirect.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int main(int argc, char **argv) +{ + int ch; + + printf("Entering the stdin redirection test\n"); + + /* stdin should have been redirected to testdata.txt. Read and print until + * we hit the end of file. + */ + + while ((ch = getchar()) != EOF) + { + putchar(ch); + } + + printf("Exit-ing the stdin redirection test\n"); + return 0; +} diff --git a/apps/examples/posix_spawn/spawn_main.c b/apps/examples/posix_spawn/spawn_main.c index 608145232..6f8859516 100644 --- a/apps/examples/posix_spawn/spawn_main.c +++ b/apps/examples/posix_spawn/spawn_main.c @@ -138,11 +138,15 @@ static unsigned int g_mmstep; /* Memory Usage at beginning of test step */ static const char delimiter[] = "****************************************************************************"; -static const char program[] = "program"; -static const char data[] = "testdata.txt"; +static const char g_redirect[] = "redirect"; +static const char g_hello[] = "hello"; +static const char g_data[] = "testdata.txt"; static char fullpath[128]; +static char * const g_argv[4] = + { "Argument 1", "Argument 2", "Argument 3", NULL }; + /**************************************************************************** * Symbols from Auto-Generated Code ****************************************************************************/ @@ -284,11 +288,87 @@ int spawn_main(int argc, char *argv[]) exec_setsymtab(exports, nexports); + /************************************************************************* + * Case 1: Simple program with arguments + *************************************************************************/ + + /* Output a seperated so that we can clearly discriminate the output of + * this program from the others. + */ + + testheader(g_hello); + + /* Initialize the attributes file actions structure */ + + ret = posix_spawn_file_actions_init(&file_actions); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_init failed: %d\n", ret); + } + posix_spawn_file_actions_dump(&file_actions); + + ret = posix_spawnattr_init(&attr); + if (ret != 0) + { + err("ERROR: posix_spawnattr_init failed: %d\n", ret); + } + posix_spawnattr_dump(&attr); + + mm_update(&g_mmstep, "after file_action/attr init"); + + /* If the binary loader does not support the PATH variable, then + * create the full path to the executable program. Otherwise, + * use the relative path so that the binary loader will have to + * search the PATH variable to find the executable. + */ + +#ifdef CONFIG_BINFMT_EXEPATH + filepath = g_hello; +#else + snprintf(fullpath, 128, "%s/%s", MOUNTPT, g_hello); + filepath = fullpath; +#endif + + /* Execute the program */ + + mm_update(&g_mmstep, "before posix_spawn"); + + ret = posix_spawn(&pid, filepath, &file_actions, &attr, NULL, (FAR char * const*)&g_argv); + if (ret != 0) + { + err("ERROR: posix_spawn failed: %d\n", ret); + } + + sleep(4); + mm_update(&g_mmstep, "after posix_spawn"); + + /* Free attibutes and file actions */ + + ret = posix_spawn_file_actions_destroy(&file_actions); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_destroy failed: %d\n", ret); + } + posix_spawn_file_actions_dump(&file_actions); + + ret = posix_spawnattr_destroy(&attr); + if (ret != 0) + { + err("ERROR: posix_spawnattr_destroy failed: %d\n", ret); + } + posix_spawnattr_dump(&attr); + + mm_update(&g_mmstep, "after file_action/attr destruction"); + + /************************************************************************* + * Case 2: Simple program with redirection of stdin + *************************************************************************/ + /* Output a seperated so that we can clearly discriminate the output of * this program from the others. */ - testheader(program); + testheader(g_redirect); /* Initialize the attributes file actions structure */ @@ -297,12 +377,14 @@ int spawn_main(int argc, char *argv[]) { err("ERROR: posix_spawn_file_actions_init failed: %d\n", ret); } + posix_spawn_file_actions_dump(&file_actions); ret = posix_spawnattr_init(&attr); if (ret != 0) { err("ERROR: posix_spawnattr_init failed: %d\n", ret); } + posix_spawnattr_dump(&attr); mm_update(&g_mmstep, "after file_action/attr init"); @@ -313,13 +395,15 @@ int spawn_main(int argc, char *argv[]) { err("ERROR: posix_spawn_file_actions_addclose failed: %d\n", ret); } + posix_spawn_file_actions_dump(&file_actions); - snprintf(fullpath, 128, "%s/%s", MOUNTPT, data); + snprintf(fullpath, 128, "%s/%s", MOUNTPT, g_data); ret = posix_spawn_file_actions_addopen(&file_actions, 0, fullpath, O_RDONLY, 0644); if (ret != 0) { err("ERROR: posix_spawn_file_actions_addopen failed: %d\n", ret); } + posix_spawn_file_actions_dump(&file_actions); mm_update(&g_mmstep, "after adding file_actions"); @@ -330,9 +414,9 @@ int spawn_main(int argc, char *argv[]) */ #ifdef CONFIG_BINFMT_EXEPATH - filepath = program; + filepath = g_redirect; #else - snprintf(fullpath, 128, "%s/%s", MOUNTPT, program); + snprintf(fullpath, 128, "%s/%s", MOUNTPT, g_redirect); filepath = fullpath; #endif @@ -346,13 +430,29 @@ int spawn_main(int argc, char *argv[]) err("ERROR: posix_spawn failed: %d\n", ret); } - sleep(1); + sleep(2); mm_update(&g_mmstep, "after posix_spawn"); + /* Free attibutes and file actions */ + + ret = posix_spawn_file_actions_destroy(&file_actions); + if (ret != 0) + { + err("ERROR: posix_spawn_file_actions_destroy failed: %d\n", ret); + } + posix_spawn_file_actions_dump(&file_actions); + + ret = posix_spawnattr_destroy(&attr); + if (ret != 0) + { + err("ERROR: posix_spawnattr_destroy failed: %d\n", ret); + } + posix_spawnattr_dump(&attr); + + mm_update(&g_mmstep, "after file_action/attr destruction"); + /* Clean-up */ - (void)posix_spawn_file_actions_destroy(&file_actions); - (void)posix_spawnattr_destroy(&attr); elf_uninitialize(); mm_update(&g_mmstep, "End-of-Test"); diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7ddc4901e..63aac89f5 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3905,4 +3905,6 @@ (from Max Holtzberg). * configs/stm32f4discovery/posix_spawn: Added a configuration that can be used for testing posix_spawn(). + * arch/arm/src/stm32: Bring F1 support for general DMA and serial + DMA in paricular up to parity with F2/F4 (from Mike Smith). diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index 3978424fb..39ed9be15 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -61,7 +61,7 @@ #define POSIX_SPAWN_SETSCHEDPARAM (1 << 2) /* 1: Set task's priority */ #define POSIX_SPAWN_SETSCHEDULER (1 << 3) /* 1: Set task's scheduler policy */ #define POSIX_SPAWN_SETSIGDEF (1 << 4) /* 1: Set default signal actions */ -#define POSIX_SPAWN_SETSIGMASK (1 << 5) /* 1: Set sigmask *./ +#define POSIX_SPAWN_SETSIGMASK (1 << 5) /* 1: Set sigmask */ /**************************************************************************** * Type Definitions @@ -181,6 +181,16 @@ int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, # define posix_spawnattr_setsigmask(attr,sigmask) (ENOSYS) #endif +/* Non standard debug functions */ + +#ifdef CONFIG_DEBUG +void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions); +void posix_spawnattr_dump(FAR posix_spawnattr_t *attr); +#else +# define posix_spawn_file_actions_dump(fa) +# define posix_spawnattr_dump(a) +#endif + #ifdef __cplusplus } #endif diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 2cf75c410..99ee781ce 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -42,6 +42,10 @@ CSRCS += lib_ps.c CSRCS += lib_psfa_addaction.c lib_psfa_addclose.c lib_psfa_adddup2.c CSRCS += lib_psfa_addopen.c lib_psfa_destroy.c lib_psfa_init.c +ifeq ($(CONFIG_DEBUG),y) +CSRCS += lib_psfa_dump.c +endif + CSRCS += lib_psa_getflags.c lib_psa_getschedparam.c lib_psa_getschedpolicy.c CSRCS += lib_psa_init.c lib_psa_setflags.c lib_psa_setschedparam.c CSRCS += lib_psa_setschedpolicy.c @@ -50,6 +54,10 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y) CSRCS += lib_psa_getsigmask.c lib_psa_setsigmask.c endif +ifeq ($(CONFIG_DEBUG),y) +CSRCS += lib_psa_dump.c +endif + # Add the spawn directory to the build DEPPATH += --dep-path spawn diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index 7509d6737..a6a0590d4 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -357,7 +357,7 @@ static int spawn_proxy(int argc, char *argv[]) { FAR struct spawn_general_file_action_s *entry; FAR const posix_spawnattr_t *attr = g_ps_parms.attr; - int ret; + int ret = OK; /* Perform file actions and/or set a custom signal mask. We get here only * if the file_actions parameter to posix_spawn[p] was non-NULL and/or the @@ -365,10 +365,10 @@ static int spawn_proxy(int argc, char *argv[]) */ #ifndef CONFIG_DISABLE_SIGNALS - DEBUGASSERT(g_ps_parms.file_actions || + DEBUGASSERT((g_ps_parms.file_actions && *g_ps_parms.file_actions) || (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0)); #else - DEBUGASSERT(g_ps_parms.file_actions); + DEBUGASSERT(g_ps_parms.file_actions && *g_ps_parms.file_actions); #endif /* Check if we need to change the signal mask */ @@ -553,9 +553,10 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, */ #ifndef CONFIG_DISABLE_SIGNALS - if (!file_actions && (attr->flags & POSIX_SPAWN_SETSIGMASK) == 0) + if ((file_actions == NULL || *file_actions == NULL) && + (attr == NULL || (attr->flags & POSIX_SPAWN_SETSIGMASK) == 0)) #else - if (!file_actions) + if (file_actions == NULL || *file_actions == NULL) #endif { return ps_exec(pid, path, attr, argv); @@ -601,7 +602,7 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, proxy = TASK_CREATE("spawn_proxy", param.sched_priority, CONFIG_POSIX_SPAWN_STACKSIZE, (main_t)spawn_proxy, - (const char **)NULL); + (FAR const char **)NULL); if (proxy < 0) { int errcode = errno; diff --git a/nuttx/libc/spawn/lib_psa_dump.c b/nuttx/libc/spawn/lib_psa_dump.c new file mode 100644 index 000000000..03770c6ff --- /dev/null +++ b/nuttx/libc/spawn/lib_psa_dump.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * libc/string/lib_psa_dump.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_DEBUG + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawnattr_dump + * + * Description: + * Show the current attributes. + * + * Input Parameters: + * attr - The address of the spawn attributes to be dumped. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void posix_spawnattr_dump(posix_spawnattr_t *attr) +{ + dbg("attr[%p]:\n", attr); + dbg(" flags: %04x\n", attr->flags); + if (attr->flags == 0) + { + dbg(" None\n"); + } + else + { + if ((attr->flags & POSIX_SPAWN_RESETIDS) != 0) + { + dbg(" POSIX_SPAWN_RESETIDS\n"); + } + + if ((attr->flags & POSIX_SPAWN_SETPGROUP) != 0) + { + dbg(" POSIX_SPAWN_SETPGROUP\n"); + } + + if ((attr->flags & POSIX_SPAWN_SETSCHEDPARAM) != 0) + { + dbg(" POSIX_SPAWN_SETSCHEDPARAM\n"); + } + + if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) + { + dbg(" POSIX_SPAWN_SETSCHEDULER\n"); + } + + if ((attr->flags & POSIX_SPAWN_SETSIGDEF) != 0) + { + dbg(" POSIX_SPAWN_SETSIGDEF\n"); + } + + if ((attr->flags & POSIX_SPAWN_SETSIGMASK) != 0) + { + dbg(" POSIX_SPAWN_SETSIGMASK\n"); + } + } + + dbg(" priority: %d\n", attr->priority); + + dbg(" policy: %d\n", attr->policy); + if (attr->policy == SCHED_FIFO) + { + dbg(" SCHED_FIFO\n"); + } + else if (attr->policy == SCHED_RR) + { + dbg(" SCHED_RR\n"); + } + else + { + dbg(" Unrecognized\n"); + } + +#ifndef CONFIG_DISABLE_SIGNALS + dbg(" sigmask: %08x\n", attr->sigmask); +#endif +}; + +#endif /* CONFIG_DEBUG */ \ No newline at end of file diff --git a/nuttx/libc/spawn/lib_psa_init.c b/nuttx/libc/spawn/lib_psa_init.c index 8aabfd090..f76188c52 100644 --- a/nuttx/libc/spawn/lib_psa_init.c +++ b/nuttx/libc/spawn/lib_psa_init.c @@ -43,7 +43,6 @@ #include #include #include -#include /**************************************************************************** * Global Functions @@ -58,7 +57,7 @@ * call to posix_spawn() or posix_spawnp(). * * Input Parameters: - * attr - The address spawn attributes to be initialized. + * attr - The address of the spawn attributes to be initialized. * * Returned Value: * On success, these functions return 0; on failure they return an error diff --git a/nuttx/libc/spawn/lib_psfa_dump.c b/nuttx/libc/spawn/lib_psfa_dump.c new file mode 100644 index 000000000..d7bf1576d --- /dev/null +++ b/nuttx/libc/spawn/lib_psfa_dump.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * libc/string/lib_psfa_dump.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "spawn/spawn.h" + +#ifdef CONFIG_DEBUG + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lib_psfa_dump + * + * Description: + * Show the entryent file actions. + * + * Input Parameters: + * file_actions - The address of the file_actions to be dumped. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions) +{ + FAR struct spawn_general_file_action_s *entry; + + DEBUGASSERT(file_actions); + + dbg("File Actions[%p->%p]:\n", file_actions, *file_actions); + if (!*file_actions) + { + dbg(" NONE\n"); + return; + } + + /* Destroy each file action, one at a time */ + + for (entry = (FAR struct spawn_general_file_action_s *)*file_actions; + entry; + entry = entry->flink) + { + switch (entry->action) + { + case SPAWN_FILE_ACTION_CLOSE: + { + FAR struct spawn_close_file_action_s *action = + (FAR struct spawn_close_file_action_s *)entry; + + dbg(" CLOSE: fd=%d\n", action->fd); + } + break; + + case SPAWN_FILE_ACTION_DUP2: + { + FAR struct spawn_dup2_file_action_s *action = + (FAR struct spawn_dup2_file_action_s *)entry; + + dbg(" DUP2: %d->%d\n", action->fd1, action->fd2); + } + break; + + case SPAWN_FILE_ACTION_OPEN: + { + FAR struct spawn_open_file_action_s *action = + (FAR struct spawn_open_file_action_s *)entry; + + svdbg(" OPEN: path=%s oflags=%04x mode=%04x fd=%d\n", + action->path, action->oflags, action->mode, action->fd); + } + break; + + case SPAWN_FILE_ACTION_NONE: + default: + dbg(" ERROR: Unknown action: %d\n", entry->action); + break; + } + } +} + +#endif /* CONFIG_DEBUG */ \ No newline at end of file diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c index 64f6f0636..0ea09b048 100644 --- a/nuttx/sched/task_vfork.c +++ b/nuttx/sched/task_vfork.c @@ -218,6 +218,9 @@ pid_t task_vforkstart(FAR _TCB *child) #endif FAR const char *name; pid_t pid; +#ifdef CONFIG_SCHED_WAITPID + int rc; +#endif int ret; svdbg("Starting Child TCB=%p, parent=%p\n", child, g_readytorun.head); @@ -246,6 +249,64 @@ pid_t task_vforkstart(FAR _TCB *child) return ERROR; } + /* Since the child task has the same priority as the parent task, it is + * now ready to run, but has not yet ran. It is a requirement that + * the parent enivornment be stable while vfork runs; the child thread + * is still dependent on things in the parent thread... like the pointers + * into parent thread's stack which will still appear in the child's + * registers and environment. + * + * We do not have SIG_CHILD, so we have to do some silly things here. + * The simplest way to make sure that the child thread runs to completion + * is simply to yield here. Since the child can only do exit() or + * execv/l(), that should be all that is needed. + * + * Hmmm.. this is probably not sufficient. What if we are running + * SCHED_RR? What if the child thread is suspeneded and rescheduled + * after the parent thread again? + */ + +#ifdef CONFIG_SCHED_WAITPID + + /* We can also exploit a bug in the execv() implementation: The PID + * of the task exec'ed by the child will not be the same as the PID of + * the child task. Therefore, waitpid() on the child task's PID will + * accomplish what we need to do. + */ + + rc = 0; + +#ifdef CONFIG_DEBUG + ret = waitpid(pid, &rc, 0); + if (ret < 0) + { + sdbg("ERROR: waitpid failed: %d\n", errno); + } +#else + (void)waitpid(pid, &rc, 0); +#endif + +#else + /* Again exploiting that execv() bug: Check if the child thread is + * still running. + */ + + while ((ret = kill(pid, 0)) == OK) + { + /* Yes.. then we can yield to it -- assuming that it has not lowered + * its priority. sleep(0) might be a safer thing to do since it does + * not depend on prioirities: It will halt the parent thread for one + * system clock tick. This will delay the return to the parent thread. + */ + +#ifndef CONFIG_DISABLE_SIGNALS + sleep(0); +#else + sched_yield(); +#endif + } +#endif + return pid; } -- cgit v1.2.3 From 43e22b2b98bacc15438133b5823d545806c8d092 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 11 Jan 2013 19:08:51 +0000 Subject: Fix an error handling bug in the fread logic git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5511 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/posix_spawn/Makefile | 27 +++++++++++++++++++++++---- apps/examples/posix_spawn/filesystem/Makefile | 16 ++++++---------- apps/examples/posix_spawn/spawn_main.c | 16 +++++++++++++++- nuttx/ChangeLog | 5 ++++- nuttx/TODO | 14 ++++++++++++-- nuttx/libc/misc/lib_filesem.c | 16 ++++++++-------- nuttx/libc/misc/lib_streamsem.c | 2 -- nuttx/libc/stdio/lib_libfread.c | 3 ++- 8 files changed, 70 insertions(+), 29 deletions(-) diff --git a/apps/examples/posix_spawn/Makefile b/apps/examples/posix_spawn/Makefile index bda3376d2..0bfa36e55 100644 --- a/apps/examples/posix_spawn/Makefile +++ b/apps/examples/posix_spawn/Makefile @@ -105,7 +105,26 @@ distclean: clean $(call DELFILE, Make.dep) $(call DELFILE, .depend) -# There are no dependencies in this directory. We should are code some of -# more important dependencies here: - --include Make.dep +# There are no dependencies in this directory. Some of more important +# and more obvious dependencies are hard-coded here: + +spawn_main.o: spawn_main.c \ + $(TOPDIR)/include/nuttx/config.h \ + $(TOPDIR)/include/nuttx/compiler.h \ + $(TOPDIR)/include/sys/mount.h \ + $(TOPDIR)/include/stdio.h \ + $(TOPDIR)/include/stdlib.h \ + $(TOPDIR)/include/unistd.h \ + $(TOPDIR)/include/string.h \ + $(TOPDIR)/include/fcntl.h \ + $(TOPDIR)/include/spawn.h \ + $(TOPDIR)/include/debug.h \ + $(TOPDIR)/include/errno.h \ + $(TOPDIR)/include/nuttx/ramdisk.h \ + $(TOPDIR)/include/nuttx/binfmt/elf.h \ + $(TOPDIR)/include/nuttx/binfmt/symtab.h \ + filesystem/romfs.h + +symtab.o: filesystem/symtab.c \ + $(TOPDIR)/include/nuttx/compiler.h \ + $(TOPDIR)/include/nuttx/binfmt/symtab.h diff --git a/apps/examples/posix_spawn/filesystem/Makefile b/apps/examples/posix_spawn/filesystem/Makefile index 2005d060f..26897426c 100644 --- a/apps/examples/posix_spawn/filesystem/Makefile +++ b/apps/examples/posix_spawn/filesystem/Makefile @@ -44,7 +44,7 @@ ROMFS_HDR = $(FILESYSTEM_DIR)$(DELIM)romfs.h SYMTAB_SRC = $(FILESYSTEM_DIR)$(DELIM)symtab.c all: $(ROMFS_HDR) $(SYMTAB_SRC) -.PHONY: all hello redirect clean install populate +.PHONY: all hello/hello redirect/redirect clean populate # Create the romfs directory @@ -53,24 +53,20 @@ $(ROMFS_DIR): # Build the hello test program -hello: $(ROMFS_DIR) +hello/hello: $(Q) $(MAKE) -C hello hello TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" # Build the redirection test program -redirect: $(ROMFS_DIR) +redirect/redirect: $(Q) $(MAKE) -C redirect redirect TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" -# Install the test programs in the romfs directory +# Create the romfs.img file from the romfs directory -install: hello redirect testdata.txt +$(ROMFS_IMG): hello/hello redirect/redirect testdata.txt $(ROMFS_DIR) $(Q) $(MAKE) -C hello install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" $(Q) $(MAKE) -C redirect install TOPDIR="$(TOPDIR)" APPDIR="$(APPDIR)" ROMFS_DIR="$(ROMFS_DIR)" $(Q) install --mode=0644 testdata.txt $(ROMFS_DIR)/testdata.txt - -# Create the romfs.img file from the romfs directory - -$(ROMFS_IMG): install $(Q) genromfs -f $@ -d $(ROMFS_DIR) -V "POSIXSPAWN" # Create the romfs.h header file from the romfs.img file @@ -80,7 +76,7 @@ $(ROMFS_HDR) : $(ROMFS_IMG) # Create the exported symbol table -$(SYMTAB_SRC): hello/hello redirect/redirect testdata.txt +$(SYMTAB_SRC): $(ROMFS_DIR)/hello $(ROMFS_DIR)/redirect $(ROMFS_DIR)/testdata.txt $(Q) $(FILESYSTEM_DIR)$(DELIM)mksymtab.sh $(ROMFS_DIR) >$@ # Clean each subdirectory diff --git a/apps/examples/posix_spawn/spawn_main.c b/apps/examples/posix_spawn/spawn_main.c index 6f8859516..1506fe499 100644 --- a/apps/examples/posix_spawn/spawn_main.c +++ b/apps/examples/posix_spawn/spawn_main.c @@ -89,6 +89,15 @@ # error "You must not disable loadable modules via CONFIG_BINFMT_DISABLE in your configuration file" #endif +/* The redirection test does not work. This is because it tries to redirect + * file as stdin. That won't work now because (1) the file descriptors must + * be dup'ed when the new task is created, and (2) there is no support in + * place for dup'ing file descriptors for anything other than sockets and + * character drivers. This is a bug! + */ + +#define FILE_DUP_BUG 1 + /* Describe the ROMFS file system */ #define SECTORSIZE 512 @@ -138,7 +147,9 @@ static unsigned int g_mmstep; /* Memory Usage at beginning of test step */ static const char delimiter[] = "****************************************************************************"; +#ifndef FILE_DUP_BUG static const char g_redirect[] = "redirect"; +#endif static const char g_hello[] = "hello"; static const char g_data[] = "testdata.txt"; @@ -361,9 +372,11 @@ int spawn_main(int argc, char *argv[]) mm_update(&g_mmstep, "after file_action/attr destruction"); /************************************************************************* - * Case 2: Simple program with redirection of stdin + * Case 2: Simple program with redirection of stdin to a file input *************************************************************************/ +#ifndef FILE_DUP_BUG + /* Output a seperated so that we can clearly discriminate the output of * this program from the others. */ @@ -450,6 +463,7 @@ int spawn_main(int argc, char *argv[]) posix_spawnattr_dump(&attr); mm_update(&g_mmstep, "after file_action/attr destruction"); +#endif /* Clean-up */ diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 63aac89f5..40a24d8f1 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3907,4 +3907,7 @@ that can be used for testing posix_spawn(). * arch/arm/src/stm32: Bring F1 support for general DMA and serial DMA in paricular up to parity with F2/F4 (from Mike Smith). - + * libc/stdio/lib_libfread.c: Correct some error handling when + lib_fread() was passed a bad stream. Needed to move the + releasing of a semaphore inside of some conditional logic + (cosmetic). diff --git a/nuttx/TODO b/nuttx/TODO index 9295f6206..e257cef79 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 10, 2013) +NuttX TODO List (Last updated January 11, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -15,7 +15,7 @@ nuttx/ (17) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (12) Libraries (libc/, ) - (9) File system/Generic drivers (fs/, drivers/) + (10) File system/Generic drivers (fs/, drivers/) (5) Graphics subystem (graphics/) (1) Pascal add-on (pcode/) (1) Documentation (Documentation/) @@ -863,6 +863,16 @@ o File system / Generic drivers (fs/, drivers/) Status: Open Priority: Medium + Title: dup AND dup2 WILL NOT WORK ON FILES IN A MOUNTED VOLUME + Description: The current implementation of dup() and dup2() will only + work with open device drivers and sockets. It will not + work with open files in a file system. + + A limitation that results from this is that you cannot + redirect I/O to an from and file. + Status: Open + Priority: High + o Graphics subystem (graphics/) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/libc/misc/lib_filesem.c b/nuttx/libc/misc/lib_filesem.c index 5cc4624ec..f38ff5f23 100644 --- a/nuttx/libc/misc/lib_filesem.c +++ b/nuttx/libc/misc/lib_filesem.c @@ -67,8 +67,8 @@ void lib_sem_initialize(FAR struct file_struct *stream) { - /* Initialize the LIB semaphore to one (to support one-at- - * a-time access to private data sets. + /* Initialize the LIB semaphore to one (to support one-at-a-time access + * to private data sets. */ (void)sem_init(&stream->fs_sem, 0, 1); @@ -98,13 +98,13 @@ void lib_take_semaphore(FAR struct file_struct *stream) /* Take the semaphore (perhaps waiting) */ while (sem_wait(&stream->fs_sem) != 0) - { - /* The only case that an error should occr here is if - * the wait was awakened by a signal. - */ + { + /* The only case that an error should occr here is if the wait + * was awakened by a signal. + */ - ASSERT(get_errno() == EINTR); - } + ASSERT(get_errno() == EINTR); + } /* We have it. Claim the stak and return */ diff --git a/nuttx/libc/misc/lib_streamsem.c b/nuttx/libc/misc/lib_streamsem.c index e38298bdb..3397f9907 100644 --- a/nuttx/libc/misc/lib_streamsem.c +++ b/nuttx/libc/misc/lib_streamsem.c @@ -86,5 +86,3 @@ void stream_semgive(FAR struct streamlist *list) { sem_post(&list->sl_sem); } - - diff --git a/nuttx/libc/stdio/lib_libfread.c b/nuttx/libc/stdio/lib_libfread.c index bc6479037..3e851bf17 100644 --- a/nuttx/libc/stdio/lib_libfread.c +++ b/nuttx/libc/stdio/lib_libfread.c @@ -301,9 +301,10 @@ ssize_t lib_fread(FAR void *ptr, size_t count, FAR FILE *stream) { stream->fs_flags |= __FS_FLAG_EOF; } + + lib_give_semaphore(stream); } - lib_give_semaphore(stream); return bytes_read; /* Error exits */ -- cgit v1.2.3 From db161f73bc2608dbb8ad8c022609198f7f0b3f95 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 11 Jan 2013 21:51:54 +0000 Subject: Documentation update git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5512 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/Documentation/NuttxUserGuide.html | 748 ++++++++++++++++++++++++++++--- nuttx/TODO | 12 +- nuttx/include/spawn.h | 2 +- nuttx/libc/spawn/lib_ps.c | 13 +- nuttx/libc/spawn/lib_psa_getschedparam.c | 2 +- nuttx/libc/spawn/lib_psa_getsigmask.c | 2 +- nuttx/libc/spawn/lib_psa_setschedparam.c | 4 +- nuttx/libc/spawn/lib_psfa_addopen.c | 8 +- nuttx/libc/spawn/lib_psfa_init.c | 2 +- 9 files changed, 722 insertions(+), 71 deletions(-) diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index 89bc08942..c6eabd29a 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

            NuttX Operating System

            User's Manual

            by

            Gregory Nutt

            -

            Last Updated: January 8, 2013

            +

            Last Updated: January 11, 2013
          @@ -193,18 +193,52 @@ paragraphs.

          Task Control Interfaces. The following task control interfaces are provided by NuttX:

          +

          + Non-standard task control interfaces inspired by VxWorks interfaces: +

          +

          + Standard interfaces +

          + +

          + Standard vfork and exec[v|l] interfaces: +

          + +

          + Standard posix_spawn interfaces: +

          + +

          2.1.1 task_create

          @@ -472,53 +506,7 @@ STATUS taskDelete(int tid);
        • Deletion of self is supported, but only because task_delete() will re-direct processing to exit(). -

          2.1.5 exit

          - -

          -Function Prototype: -

          -    #include <sched.h>
-    void exit(int code);
-
-    #include <nuttx/unistd.h>
-    void _exit(int code);
-
          - -

          -Description: This function causes the calling task to cease -to exist -- its stack and TCB will be deallocated. exit differs from -_exit in that it flushes streams, closes file descriptors and will -execute any function registered with atexit() or on_exit(). -

          -Input Parameters: -

            -
          • code. (ignored) -
          - -

          -Returned Value: None. - -

          -Assumptions/Limitations: - -

          -POSIX Compatibility: This is equivalent to the ANSI interface: -

          -    void exit(int code);
-
          -And the UNIX interface: -
          -    void _exit(int code);
-
          - -

          - The NuttX exit() differs from ANSI exit() in the following ways: -

          -
            -
          • The code parameter is ignored. -
          - -

          2.1.6 task_restart

          +

          2.1.5 task_restart

          Function Prototype: 

            @@ -588,6 +576,52 @@ VxWorks provides the following similar interface:
          +

          2.1.6 exit

          + +

          +Function Prototype: +

          +    #include <sched.h>
+    void exit(int code);
+
+    #include <nuttx/unistd.h>
+    void _exit(int code);
+
          + +

          +Description: This function causes the calling task to cease +to exist -- its stack and TCB will be deallocated. exit differs from +_exit in that it flushes streams, closes file descriptors and will +execute any function registered with atexit() or on_exit(). +

          +Input Parameters: +

            +
          • code. (ignored) +
          + +

          +Returned Value: None. + +

          +Assumptions/Limitations: + +

          +POSIX Compatibility: This is equivalent to the ANSI interface: +

          +    void exit(int code);
+
          +And the UNIX interface: +
          +    void _exit(int code);
+
          + +

          + The NuttX exit() differs from ANSI exit() in the following ways: +

          +
            +
          • The code parameter is ignored. +
          +

          2.1.7 getpid

          @@ -780,6 +814,595 @@ int execl(FAR const char *path, ...); There are, however, several compatibility issues as detailed in the description of execv().

          +

          2.1.11 posix_spawn and posix_spawnp

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn(FAR pid_t *pid, FAR const char *path,
+      FAR const posix_spawn_file_actions_t *file_actions,
+      FAR const posix_spawnattr_t *attr,
+      FAR char *const argv[], FAR char *const envp[]);
+int posix_spawnp(FAR pid_t *pid, FAR const char *file,
+      FAR const posix_spawn_file_actions_t *file_actions,
+      FAR const posix_spawnattr_t *attr,
+      FAR char *const argv[], FAR char *const envp[]);
+
          +

          + Description: + The posix_spawn() and posix_spawnp() functions will create a new, child task, constructed from a regular executable file.

          +

          +

          + Input Parameters: +

          +
            +
          • +

            + pid: + Upon successful completion, posix_spawn() and posix_spawnp() will return the task ID of the child task to the parent task, in the variable pointed to by a non-NULL pid argument. + If the pid argument is a null pointer, the process ID of the child is not returned to the caller. +

            +
            • +
          • +

            + path or file: + The path argument to posix_spawn() is the absolute path that identifies the file to execute. + The file argument to posix_spawnp() may also be a relative path and will be used to construct a pathname that identifies the file to execute. + In the case of a relative path, the path prefix for the file will be obtained by a search of the directories passed as the environment variable PATH. +

            +

            + NOTE: NuttX provides only one implementation: + If CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior is supported; otherwise, only posix_spawn behavior is supported. +

            • +
          • +

            + file_actions: + If file_actions is a null pointer, then file descriptors open in the calling process will remain open in the child process (unless CONFIG_FDCLONE_STDIO is defined). + If file_actions is not NULL, then the file descriptors open in the child process will be those open in the calling process as modified by the spawn file actions object pointed to by file_actions. +

            +
            • +
          • +

            + attr: + If the value of the attr parameter is NULL, the all default values for the POSIX spawn attributes will be used. + Otherwise, the attributes will be set according to the spawn flags. + The posix_spawnattr_t spawn attributes object type is defined in spawn.h. + It will contains these attributes, not all of which are supported by NuttX: +

            +
              +
            • + POSIX_SPAWN_SETPGROUP: + Setting of the new task's process group is not supported. + NuttX does not support process groups. +
              • +
            • + POSIX_SPAWN_SETSCHEDPARAM: + Set new tasks priority to the sched_param value. +
              • +
            • + POSIX_SPAWN_SETSCHEDULER: + Set the new task's scheduler policy to the sched_policy value. +
              • +
            • + POSIX_SPAWN_RESETIDS + Resetting of the effective user ID of the child process is not supported. + NuttX does not support effective user IDs. +
              • +
            • + POSIX_SPAWN_SETSIGMASK: + Set the new task's signal mask. +
              • +
            • + POSIX_SPAWN_SETSIGDEF: + Resetting signal default actions is not supported. + NuttX does not support default signal actions. +
              • +
            +
            • +
          • +

            + argv: + argv[] is the argument list for the new task. argv[] is an array of pointers to null-terminated strings. + The list is terminated with a null pointer. +

            +
            • +
          • +

            + envp: + The envp[] argument is not used by NuttX and may be NULL. + In standard implementations, envp[] is an array of character pointers to null-terminated strings that provide the environment for the new process image. + The environment array is terminated by a null pointer. + In NuttX, the envp[] argument is ignored and the new task will inherit the environment of the parent task unconditionally.

            +
            • +
          +

          + Returned Value: + posix_spawn() and posix_spawnp() will return zero on success. + Otherwise, an error number will be returned as the function return value to indicate the error: +

          +
            +
          • + EINVAL: + The value specified by file_actions or attr is invalid. +
            • +
          • + Any errors that might have been return if vfork() and excec[l|v]() had been called. +
            • +
          +

          + Assumptions/Limitations: +

          +
            +
          • + NuttX provides only posix_spawn() or posix_spawnp() behavior depending upon the setting of CONFIG_BINFMT_EXEPATH: + If CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior is supported; otherwise, only posix_spawn() behavior is supported. +
            • +
          • + The envp argument is not used and the environ variable is not altered (NuttX does not support the environ variable). +
            • +
          • + Process groups are not supported (See POSIX_SPAWN_SETPGROUP above). +
            • +
          • + Effective user IDs are not supported (See POSIX_SPAWN_RESETIDS above). +
            • +
          • + Signal default actions cannot be modified in the newly task executed because NuttX does not support default signal actions (See POSIX_SPAWN_SETSIGDEF). +
            • +
          +

          + POSIX Compatibility: + The value of the argv[0] received by the child task is assigned by NuttX. + For the caller of posix_spawn(), the provided argv[0] will correspond to argv[1] received by the new task. +

          + +

          2.1.12 posix_spawn_file_actions_init

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions);
+
          +

          + Description: + The posix_spawn_file_actions_init() function initializes the object referenced by file_actions to an empty set of file actions for subsequent use in a call to posix_spawn() or posix_spawnp(). +

          +

          + Input Parameters: +

          +
            +
          • + file_actions: + The address of the posix_spawn_file_actions_t to be initialized. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h>. +

          + +

          2.1.13 posix_spawn_file_actions_destroy

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_actions);
+
          +

          + Description: + The posix_spawn_file_actions_destroy() function destroys the object referenced by file_actions which was previously intialized by posix_spawn_file_actions_init(), returning any resources obtained at the time of initialization to the system for subsequent reuse. + A posix_spawn_file_actions_t may be reinitialized after having been destroyed, but must not be reused after destruction, unless it has been reinitialized. +

          +

          + Input Parameters: +

          +
            +
          • + file_actions: + The address of the posix_spawn_file_actions_t to be destroyed. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.14 posix_spawn_file_actions_addclose

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actions, int fd);
+
          +

          + Description: + The posix_spawn_file_actions_addclose() function adds a close operation to the list of operations associated with the object referenced by file_actions, for subsequent use in a call to posix_spawn() or posix_spawnp(). + The descriptor referred to by fd is closed as if close() had been called on it prior to the new child process starting execution. +

          +

          + Input Parameters: +

          +
            +
          • + file_actions: + The address of the posix_spawn_file_actions_t object to which the close operation will be appended. +
            • +
          • + fd: + The file descriptor to be closed. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.15 posix_spawn_file_actions_adddup2

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_actions, int fd1, int fd2);
+
          +

          + Description: + The posix_spawn_file_actions_adddup2() function adds a dup2 operation to the list of operations associated with the object referenced by file_actions, for subsequent use in a call to posix_spawn() or posix_spawnp(). + The descriptor referred to by fd2 is created as if dup2() had been called on fd1 prior to the new child process starting execution. +

          +

          + Input Parameters: +

          +
            +
          • + file_actions: + The address of the posix_spawn_file_actions_t object to which the dup2 operation will be appended. +
            • +
          • + fd1: + The file descriptor to be be duplicated. + The first file descriptor to be argument to dup2(). +
            • +
          • + fd2: + The file descriptor to be be created. + The second file descriptor to be argument to dup2(). +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.16 posix_spawn_file_actions_addopen

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_actions,
+      int fd, FAR const char *path, int oflags, mode_t mode);
+
          +

          + Description: + The posix_spawn_file_actions_addopen() function adds an open operation to the list of operations associated with the object referenced by file_actions, for subsequent use in a call to posix_spawn() or posix_spawnp(). + The descriptor referred to by fd is opened using the path, oflag, and mode arguments as if open() had been called on it prior to the new child process starting execution. + The string path is copied by the posix_spawn_file_actions_addopen() function during this process, so storage need not be persistent in the caller. +

          +

          + Input Parameters: +

          +
            +
          • + file_actions: + The address of the posix_spawn_file_actions_t object to which the open operation will be appended. +
            • +
          • + fd: + The file descriptor to be opened. +
            • +
          • + path: + The path to be opened. +
            • +
          • + oflags: + Open flags. +
            • +
          • + mode: + File creation mode/ +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.17 posix_spawnattr_init

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_init(FAR posix_spawnattr_t *attr);
+
          +

          + Description: + The posix_spawnattr_init() function initializes the object referenced by attr, to an empty set of spawn attributes for subsequent use in a call to posix_spawn() or posix_spawnp(). +

          +

          + Then the spawn attributes are no longer needed, they should be destroyed by calling posix_spawnattr_destroyed(). + In NuttX, however, posix_spawnattr_destroyed() is just stub: +

          +
            +#define posix_spawnattr_destroy(attr) (0)
+
          +

          + For portability, the convention of calling posix_spawnattr_destroyed() when the attributes are not longer needed should still be followed. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address of the spawn attributes to be initialized. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.18 posix_spawnattr_getflags

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, FAR short *flags);
+
          +

          + Description: + The posix_spawnattr_getflags() function will obtain the value of the spawn-flags attribute from the attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be queried. +
            • +
          • + flags: + The location to return the spawn flags +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.19 posix_spawnattr_getschedparam

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, FAR struct sched_param *param);
+
          +

          + Description: + The posix_spawnattr_getschedparam() function will obtain the value of the spawn-schedparam attribute from the attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be queried. +
            • +
          • + param: + The location to return the spawn-schedparam value. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.20 posix_spawnattr_getschedpolicy

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *policy);
+
          +

          + Description: + The posix_spawnattr_getschedpolicy() function will obtain the value of the spawn-schedpolicy attribute from the attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be queried. +
            • +
          • + policy: + The location to return the spawn-schedpolicy value. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.21 posix_spawnattr_getsigmask

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+#ifndef CONFIG_DISABLE_SIGNALS
+int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t *sigmask);
+#endif
+
          +

          + Description: + The posix_spawnattr_getsigdefault() function will obtain the value of the spawn-sigmask attribute from the attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be queried. +
            • +
          • + sigmask: + The location to return the spawn-sigmask value. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.22 posix_spawnattr_setflags

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags);
+
          +

          + Description: + The posix_spawnattr_setflags() function will set the spawn-flags attribute in an initialized attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be used. +
            • +
          • + flags: + The new value of the spawn-flags attribute. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.23 posix_spawnattr_setschedparam

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, FAR const struct sched_param *param);
+
          +

          + Description: + The posix_spawnattr_setschedparam() function will set the spawn-schedparam attribute in an initialized attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be used. +
            • +
          • + param: + The new value of the spawn-schedparam attribute. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.24 posix_spawnattr_setschedpolicy

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy);
+
          +

          + Description: + The posix_spawnattr_setschedpolicy() function will set the spawn-schedpolicy attribute in an initialized attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be used. +
            • +
          • + policy: + The new value of the spawn-schedpolicy attribute. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + +

          2.1.25 posix_spawnattr_setsigmask

          +

          + Function Prototype: +

          + 
            +#include <spawn.h>
+#ifndef CONFIG_DISABLE_SIGNALS
+int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t *sigmask);
+#endif
+
          +

          + Description: + The posix_spawnattr_setsigmask() function will set the spawn-sigmask attribute in an initialized attributes object referenced by attr. +

          +

          + Input Parameters: +

          +
            +
          • + attr: + The address spawn attributes to be used. +
            • +
          • + sigmask: + The new value of the spawn-sigmask attribute. +
            • +
          +

          + Returned Value: + On success, this function returns 0; on failure it will return an error number from <errno.h> +

          + - + + -
          @@ -8395,13 +9018,30 @@ notify a task when a message is available on a queue.
        • on_exit
        • open
        • opendir
          • -
        • OS Interfaces
        • pause
        • pipe
        • poll
        • poll.h
          • +          		 +
        • posix_spawn
          • +
        • posix_spawn_file_actions_addclose
          • +
        • posix_spawn_file_actions_adddup2
          • +
        • posix_spawn_file_actions_addopen
          • +
        • posix_spawn_file_actions_destroy
          • +
        • posix_spawn_file_actions_init
          • +
        • posix_spawnattr_init
          • +
        • posix_spawnattr_destroy
          • +
        • posix_spawnattr_getflags
          • +
        • posix_spawnattr_getschedparam
          • +
        • posix_spawnattr_getschedpolicy
          • +
        • posix_spawnattr_getsigmask
          • +
        • posix_spawnattr_setflags
          • +
        • posix_spawnattr_setschedparam
          • +
        • posix_spawnattr_setschedpolicy
          • +
        • posix_spawnattr_setsigmask
          • +
        • posix_spawnp
        • printf
        • Pthread Interfaces
        • pthread_attr_destroy
          • @@ -8467,6 +9107,8 @@ notify a task when a message is available on a queue.
        • recv
        • recvfrom
        • rename
          • +
        • rmdir
        • rewinddir
        • ROM disk driver
          • @@ -8474,8 +9116,6 @@ notify a task when a message is available on a queue.
        • sched_getparam
        • sched_get_priority_max
        • sched_get_priority_min
          • -
        • sched_get_rr_interval
        • sched_lockcount
        • sched_lock
          • diff --git a/nuttx/TODO b/nuttx/TODO index e257cef79..92b7ab4f5 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -866,7 +866,17 @@ o File system / Generic drivers (fs/, drivers/) Title: dup AND dup2 WILL NOT WORK ON FILES IN A MOUNTED VOLUME Description: The current implementation of dup() and dup2() will only work with open device drivers and sockets. It will not - work with open files in a file system. + work with open files in a file system. Support for dup'ing + open files on a mounted volume has not been implemented yet. + + There is a stubbed out, partial implemenation in fs/fs_files.c. + In would perform the dup2() operation by re-opening the file + and setting the file pointer. The logic, however, would require + that we remember the (relative) path to the file in the mounted + volume for each open file. + + An option might to add a dup() method to the file system + mountpoint interface. A limitation that results from this is that you cannot redirect I/O to an from and file. diff --git a/nuttx/include/spawn.h b/nuttx/include/spawn.h index 39ed9be15..5e0ce3416 100644 --- a/nuttx/include/spawn.h +++ b/nuttx/include/spawn.h @@ -112,7 +112,7 @@ extern "C" #ifdef CONFIG_BINFMT_EXEPATH int posix_spawnp(FAR pid_t *pid, FAR const char *path, FAR const posix_spawn_file_actions_t *file_actions, - FAR const posix_spawnattr_t * attr, + FAR const posix_spawnattr_t *attr, FAR char *const argv[], FAR char *const envp[]); #define posix_spawn(pid,path,file_actions,attr,argv,envp) \ posix_spawnp(pid,path,file_actions,attr,argv,envp) diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index a6a0590d4..dfe57089e 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -440,7 +440,7 @@ static int spawn_proxy(int argc, char *argv[]) * * Description: * The posix_spawn() and posix_spawnp() functions will create a new, - * child task, constructed a regular executable file. + * child task, constructed from a regular executable file. * * Input Parameters: * @@ -479,9 +479,9 @@ static int spawn_proxy(int argc, char *argv[]) * not supported. NuttX does not support process groups. * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param * value. - * - POSIX_SPAWN_SETSCHEDULER: Set the new task's scheduler priority to + * - POSIX_SPAWN_SETSCHEDULER: Set the new task's scheduler policy to * the sched_policy value. - * - POSIX_SPAWN_RESETIDS: Resetting of effective user ID of the child + * - POSIX_SPAWN_RESETIDS: Resetting of the effective user ID of the child * process is not supported. NuttX does not support effective user * IDs. * - POSIX_SPAWN_SETSIGMASK: Set the new task's signal mask. @@ -514,11 +514,12 @@ static int spawn_proxy(int argc, char *argv[]) * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior * is supported; otherwise, only posix_spawn behavior is supported. * - The 'envp' argument is not used and the 'environ' variable is not - * altered (NuttX does not support the 'environ' variable. + * altered (NuttX does not support the 'environ' variable). * - Process groups are not supported (POSIX_SPAWN_SETPGROUP). * - Effective user IDs are not supported (POSIX_SPAWN_RESETIDS). - * - Signal masks and signal default actions cannot be modified in the - * newly executed task (POSIX_SPAWN_SETSIGDEF and POSIX_SPAWN_SETSIGMASK). + * - Signal default actions cannot be modified in the newly task executed + * because NuttX does not support default signal actions + * (POSIX_SPAWN_SETSIGDEF). * * POSIX Compatibility * - The value of the argv[0] received by the child task is assigned by diff --git a/nuttx/libc/spawn/lib_psa_getschedparam.c b/nuttx/libc/spawn/lib_psa_getschedparam.c index 65cec47f1..ed8cb1f70 100644 --- a/nuttx/libc/spawn/lib_psa_getschedparam.c +++ b/nuttx/libc/spawn/lib_psa_getschedparam.c @@ -57,7 +57,7 @@ * * Input Parameters: * attr - The address spawn attributes to be queried. - * flags - The location to return the sched_priority value. + * flags - The location to return the spawn-schedparam value. * * Returned Value: * On success, these functions return 0; on failure they return an error diff --git a/nuttx/libc/spawn/lib_psa_getsigmask.c b/nuttx/libc/spawn/lib_psa_getsigmask.c index 3c831075e..dd3495b4d 100644 --- a/nuttx/libc/spawn/lib_psa_getsigmask.c +++ b/nuttx/libc/spawn/lib_psa_getsigmask.c @@ -59,7 +59,7 @@ * * Input Parameters: * attr - The address spawn attributes to be queried. - * sigmask - The location to return the spawn flags + * sigmask - The location to return the signal mask * * Returned Value: * On success, these functions return 0; on failure they return an error diff --git a/nuttx/libc/spawn/lib_psa_setschedparam.c b/nuttx/libc/spawn/lib_psa_setschedparam.c index 8d3356aaf..5e992e8a9 100644 --- a/nuttx/libc/spawn/lib_psa_setschedparam.c +++ b/nuttx/libc/spawn/lib_psa_setschedparam.c @@ -56,8 +56,8 @@ * by attr. * * Input Parameters: - * attr - The address spawn attributes to be used. - * parm - The new sched_priority to set. + * attr - The address spawn attributes to be used. + * param - The new sched_priority to set. * * Returned Value: * On success, these functions return 0; on failure they return an error diff --git a/nuttx/libc/spawn/lib_psfa_addopen.c b/nuttx/libc/spawn/lib_psfa_addopen.c index bcb201291..385e1cfc3 100644 --- a/nuttx/libc/spawn/lib_psfa_addopen.c +++ b/nuttx/libc/spawn/lib_psfa_addopen.c @@ -57,8 +57,8 @@ * Description: * The posix_spawn_file_actions_addopen() function adds an open operation * to the list of operations associated with the object referenced by - * file_actions, for subsequent use in a call to posix_spawn(2) or - * posix_spawnp(2). The descriptor referred to by fd is opened using + * file_actions, for subsequent use in a call to posix_spawn() or + * posix_spawnp(). The descriptor referred to by fd is opened using * the path, oflag, and mode arguments as if open() had been called on it * prior to the new child process starting execution. The string path is * copied by the posix_spawn_file_actions_addopen() function during this @@ -66,8 +66,8 @@ * * Input Parameters: * file_actions - The posix_spawn_file_actions_t to append the action. - * fd - The path to be opened. - * path - The first file descriptor to be argument to dup2. + * fd - The file descriptor to be opened. + * path - The path to be opened. * oflags - Open flags * mode - File creation mode * diff --git a/nuttx/libc/spawn/lib_psfa_init.c b/nuttx/libc/spawn/lib_psfa_init.c index 4e23703ae..5c902125a 100644 --- a/nuttx/libc/spawn/lib_psfa_init.c +++ b/nuttx/libc/spawn/lib_psfa_init.c @@ -50,7 +50,7 @@ * * Description: * The posix_spawn_file_actions_init() function initializes the object - * referenced by file_actions, to an empty set of file actions for + * referenced by file_actions to an empty set of file actions for * subsequent use in a call to posix_spawn() or posix_spawnp(). * * Input Parameters: -- cgit v1.2.3 From b58281cab8add0af82167282126132b069170dd6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 12 Jan 2013 19:58:45 +0000 Subject: Fix a *critical* bug in the task exit logic. Implements SIGCHILD git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5513 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/examples/ostest/sighand.c | 58 ++++++++++++++++++ nuttx/ChangeLog | 11 ++++ nuttx/Documentation/NuttxPortingGuide.html | 50 ++++++++++++++-- nuttx/configs/README.txt | 24 +++++++- nuttx/configs/amber/hello/defconfig | 2 +- nuttx/configs/avr32dev1/nsh/defconfig | 2 +- nuttx/configs/avr32dev1/ostest/defconfig | 2 +- nuttx/configs/cloudctrl/nsh/defconfig | 2 +- nuttx/configs/demo9s12ne64/ostest/defconfig | 2 +- nuttx/configs/ea3131/nsh/defconfig | 2 +- nuttx/configs/ea3131/ostest/defconfig | 2 +- nuttx/configs/ea3131/pgnsh/defconfig | 2 +- nuttx/configs/ea3131/usbserial/defconfig | 2 +- nuttx/configs/ea3131/usbstorage/defconfig | 2 +- nuttx/configs/ea3152/ostest/defconfig | 2 +- nuttx/configs/fire-stm32v2/nsh/defconfig | 2 +- nuttx/configs/hymini-stm32v/buttons/defconfig | 2 +- nuttx/configs/hymini-stm32v/nsh/defconfig | 2 +- nuttx/configs/hymini-stm32v/nsh2/defconfig | 2 +- nuttx/configs/hymini-stm32v/nx/defconfig | 2 +- nuttx/configs/hymini-stm32v/nxlines/defconfig | 2 +- nuttx/configs/hymini-stm32v/usbserial/defconfig | 2 +- nuttx/configs/hymini-stm32v/usbstorage/defconfig | 2 +- nuttx/configs/kwikstik-k40/ostest/defconfig | 2 +- nuttx/configs/lincoln60/nsh/defconfig | 2 +- nuttx/configs/lincoln60/ostest/defconfig | 2 +- nuttx/configs/lpc4330-xplorer/nsh/defconfig | 2 +- nuttx/configs/lpc4330-xplorer/ostest/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/nx/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig | 2 +- .../lpcxpresso-lpc1768/usbstorage/defconfig | 2 +- nuttx/configs/mbed/hidkbd/defconfig | 2 +- nuttx/configs/mbed/nsh/defconfig | 2 +- nuttx/configs/micropendous3/hello/defconfig | 2 +- nuttx/configs/mirtoo/nsh/defconfig | 2 +- nuttx/configs/mirtoo/nxffs/defconfig | 2 +- nuttx/configs/mirtoo/ostest/defconfig | 2 +- nuttx/configs/ne64badge/ostest/defconfig | 2 +- nuttx/configs/nucleus2g/nsh/defconfig | 2 +- nuttx/configs/nucleus2g/ostest/defconfig | 2 +- nuttx/configs/nucleus2g/usbserial/defconfig | 2 +- nuttx/configs/nucleus2g/usbstorage/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/ftpc/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nettest/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nx/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/ostest/defconfig | 2 +- .../configs/olimex-lpc1766stk/slip-httpd/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/thttpd/defconfig | 2 +- .../configs/olimex-lpc1766stk/usbserial/defconfig | 2 +- .../configs/olimex-lpc1766stk/usbstorage/defconfig | 2 +- nuttx/configs/olimex-stm32-p107/nsh/defconfig | 2 +- nuttx/configs/olimex-stm32-p107/ostest/defconfig | 2 +- nuttx/configs/olimex-strp711/nettest/defconfig | 2 +- nuttx/configs/pcblogic-pic32mx/nsh/defconfig | 2 +- nuttx/configs/pcblogic-pic32mx/ostest/defconfig | 2 +- nuttx/configs/pic32-starterkit/nsh/defconfig | 2 +- nuttx/configs/pic32-starterkit/nsh2/defconfig | 2 +- nuttx/configs/pic32-starterkit/ostest/defconfig | 2 +- nuttx/configs/pic32mx7mmb/nsh/defconfig | 2 +- nuttx/configs/pic32mx7mmb/ostest/defconfig | 2 +- nuttx/configs/sam3u-ek/knsh/defconfig | 2 +- nuttx/configs/sam3u-ek/nsh/defconfig | 2 +- nuttx/configs/sam3u-ek/nx/defconfig | 2 +- nuttx/configs/sam3u-ek/ostest/defconfig | 2 +- nuttx/configs/sam3u-ek/touchscreen/defconfig | 2 +- nuttx/configs/shenzhou/nsh/defconfig | 2 +- nuttx/configs/shenzhou/nxwm/defconfig | 2 +- nuttx/configs/shenzhou/thttpd/defconfig | 2 +- nuttx/configs/sim/nsh/defconfig | 2 +- nuttx/configs/sim/nsh2/defconfig | 2 +- nuttx/configs/sim/ostest/defconfig | 13 +++- nuttx/configs/stm3210e-eval/RIDE/defconfig | 2 +- nuttx/configs/stm3210e-eval/buttons/defconfig | 2 +- nuttx/configs/stm3210e-eval/composite/defconfig | 2 +- nuttx/configs/stm3210e-eval/nsh/defconfig | 2 +- nuttx/configs/stm3210e-eval/nsh2/defconfig | 2 +- nuttx/configs/stm3210e-eval/nx/defconfig | 2 +- nuttx/configs/stm3210e-eval/nxconsole/defconfig | 2 +- nuttx/configs/stm3210e-eval/nxlines/defconfig | 2 +- nuttx/configs/stm3210e-eval/nxtext/defconfig | 2 +- nuttx/configs/stm3210e-eval/ostest/defconfig | 2 +- nuttx/configs/stm3210e-eval/pm/defconfig | 2 +- nuttx/configs/stm3210e-eval/usbserial/defconfig | 2 +- nuttx/configs/stm3210e-eval/usbstorage/defconfig | 2 +- nuttx/configs/stm3220g-eval/dhcpd/defconfig | 2 +- nuttx/configs/stm3220g-eval/nettest/defconfig | 2 +- nuttx/configs/stm3220g-eval/nsh/defconfig | 2 +- nuttx/configs/stm3220g-eval/nsh2/defconfig | 2 +- nuttx/configs/stm3220g-eval/nxwm/defconfig | 2 +- nuttx/configs/stm3220g-eval/ostest/defconfig | 2 +- nuttx/configs/stm3220g-eval/telnetd/defconfig | 2 +- nuttx/configs/stm3240g-eval/dhcpd/defconfig | 2 +- nuttx/configs/stm3240g-eval/nettest/defconfig | 2 +- nuttx/configs/stm3240g-eval/nsh/defconfig | 2 +- nuttx/configs/stm3240g-eval/nsh2/defconfig | 2 +- nuttx/configs/stm3240g-eval/nxconsole/defconfig | 2 +- nuttx/configs/stm3240g-eval/nxwm/defconfig | 2 +- nuttx/configs/stm3240g-eval/ostest/defconfig | 2 +- nuttx/configs/stm3240g-eval/telnetd/defconfig | 2 +- nuttx/configs/stm3240g-eval/webserver/defconfig | 2 +- nuttx/configs/stm32f100rc_generic/nsh/defconfig | 2 +- nuttx/configs/stm32f4discovery/README.txt | 26 ++++++++ nuttx/configs/stm32f4discovery/nsh/defconfig | 2 +- nuttx/configs/stm32f4discovery/pm/defconfig | 2 +- .../configs/stm32f4discovery/posix_spawn/defconfig | 2 +- nuttx/configs/sure-pic32mx/nsh/defconfig | 2 +- nuttx/configs/sure-pic32mx/ostest/defconfig | 2 +- nuttx/configs/sure-pic32mx/usbnsh/defconfig | 2 +- nuttx/configs/teensy/hello/defconfig | 2 +- nuttx/configs/teensy/nsh/defconfig | 2 +- nuttx/configs/teensy/usbstorage/defconfig | 2 +- nuttx/configs/twr-k60n512/nsh/defconfig | 2 +- nuttx/configs/twr-k60n512/ostest/defconfig | 2 +- nuttx/configs/ubw32/nsh/defconfig | 2 +- nuttx/configs/ubw32/ostest/defconfig | 2 +- nuttx/configs/vsn/nsh/defconfig | 2 +- nuttx/include/nuttx/sched.h | 3 + nuttx/include/nuttx/wqueue.h | 2 +- nuttx/include/signal.h | 68 +++++++++++++-------- nuttx/libc/Kconfig | 5 +- nuttx/sched/Kconfig | 69 +++++++++++++++++++--- nuttx/sched/sched_unlock.c | 1 + nuttx/sched/sig_kill.c | 7 +++ nuttx/sched/sig_mqnotempty.c | 7 +++ nuttx/sched/sig_queue.c | 13 +++- nuttx/sched/sig_timedwait.c | 4 ++ nuttx/sched/task_deletecurrent.c | 16 ++++- nuttx/sched/task_exithook.c | 55 +++++++++++++++++ nuttx/sched/task_setup.c | 36 ++++++++++- nuttx/sched/timer_settime.c | 4 ++ 136 files changed, 540 insertions(+), 164 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 6b63527a7..65d4d6134 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -462,4 +462,6 @@ * apps/examples/wlan: Remove non-functional example. * apps/examples/ostest/vfork.c: Added a test of vfork(). * apps/exampes/posix_spawn: Added a test of poxis_spawn(). + * apps/examples/ostest: Extend signal handler test to catch + death-of-child signals (SIGCHLD). diff --git a/apps/examples/ostest/sighand.c b/apps/examples/ostest/sighand.c index eabfe5646..63d9590d9 100644 --- a/apps/examples/ostest/sighand.c +++ b/apps/examples/ostest/sighand.c @@ -54,12 +54,32 @@ static sem_t sem; static bool sigreceived = false; static bool threadexited = false; +#ifdef CONFIG_SCHED_HAVE_PARENT +static void death_of_child(int signo, siginfo_t *info, void *ucontext) +{ + /* Use of printf in a signal handler is NOT safe! It can cause deadlocks! */ + + if (info) + { + printf("death_of_child: PID %d received signal=%d code=%d pid=%d status=%d\n", + getpid(), signo, info->si_code, info->si_pid, info->si_status); + } + else + { + printf("death_of_child: PID %d received signal=%d (no info?)\n", + getpid(), signo); + } +} +#endif + static void wakeup_action(int signo, siginfo_t *info, void *ucontext) { sigset_t oldset; sigset_t allsigs; int status; + /* Use of printf in a signal handler is NOT safe! It can cause deadlocks! */ + printf("wakeup_action: Received signal %d\n" , signo); sigreceived = true; @@ -186,6 +206,11 @@ static int waiter_main(int argc, char *argv[]) void sighand_test(void) { +#ifdef CONFIG_SCHED_HAVE_PARENT + struct sigaction act; + struct sigaction oact; + sigset_t sigset; +#endif struct sched_param param; union sigval sigvalue; pid_t waiterpid; @@ -195,6 +220,32 @@ void sighand_test(void) printf("sighand_test: Initializing semaphore to 0\n" ); sem_init(&sem, 0, 0); +#ifdef CONFIG_SCHED_HAVE_PARENT + printf("sighand_test: Unmasking SIGCHLD\n"); + + (void)sigemptyset(&sigset); + (void)sigaddset(&sigset, SIGCHLD); + status = sigprocmask(SIG_UNBLOCK, &sigset, NULL); + if (status != OK) + { + printf("sighand_test: ERROR sigprocmask failed, status=%d\n", + status); + } + + printf("sighand_test: Registering SIGCHLD handler\n" ); + act.sa_sigaction = death_of_child; + act.sa_flags = SA_SIGINFO; + + (void)sigfillset(&act.sa_mask); + (void)sigdelset(&act.sa_mask, SIGCHLD); + + status = sigaction(SIGCHLD, &act, &oact); + if (status != OK) + { + printf("waiter_main: ERROR sigaction failed, status=%d\n" , status); + } +#endif + /* Start waiter thread */ printf("sighand_test: Starting waiter task\n" ); @@ -262,6 +313,13 @@ void sighand_test(void) printf("sighand_test: ERROR signal handler did not run\n" ); } + /* Detach the signal handler */ + +#ifdef CONFIG_SCHED_HAVE_PARENT + act.sa_sigaction = SIG_DFL; + status = sigaction(SIGCHLD, &act, &oact); +#endif + printf("sighand_test: done\n" ); FFLUSH(); } diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 40a24d8f1..921b7014b 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3911,3 +3911,14 @@ lib_fread() was passed a bad stream. Needed to move the releasing of a semaphore inside of some conditional logic (cosmetic). + * include/nuttx/sched.h, sched/task_setup.c, and sched/task_exithook.c: + Add support for remembering the parent task and sending + SIGCHLD to the parent when the task exists. + * sched/task_exithook.c: Fixed a *critical* bug. Here is + the scenario: (1) sched_lock() is called increments the lockcount + on the current TCB (i.e., the one at the head of the ready to run + list), (2) sched_mergepending is called which may change the task + at the head of the readytorun list, then (2) sched_lock() is called + which decrements the lockcount on the wrong TCB. The failure case + that I saw was that pre-emption got disabled in the IDLE thread, + locking up the whole system. diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index b1664f3f0..0b67eddb7 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

          NuttX RTOS Porting Guide

          -

          Last Updated: January 4, 2013

          +

          Last Updated: January 12, 2013
          @@ -4480,6 +4480,11 @@ build task name to save in the TCB. Useful if scheduler instrumentation is selected. Set to zero to disable.
          • +
        • + CONFIG_SCHED_HAVE_PARENT: Remember the ID of the parent thread when a new child thread is created. + This support enables a few minor features (such as SIGCHLD) and slightly increases the size of the Task Control Block (TCB) of every task to hold the ID of the parent thread. + Default: disabled. +
        • CONFIG_SYSTEM_TIME16: The range of system time is, by default, 32-bits. @@ -4582,7 +4587,7 @@ build
        • CONFIG_SIG_SIGWORK: The signal number that will be used to wake-up - the worker thread. Default: 4 + the worker thread. Default: 17
        • CONFIG_SCHED_LPWORK: If CONFIG_SCHED_WORKQUEUE is defined, then a single work queue is created by default. @@ -4624,9 +4629,41 @@ build user_start.
          • +

          + Signal Numbers: +

          +
            +
          • + CONFIG_SIG_SIGUSR1: + Value of standard user signal 1 (SIGUSR1). Default: 1 +
            • +
          • + CONFIG_SIG_SIGUSR2: + Value of standard user signal 2 (SIGUSR2). Default: 2 +
            • +
          • + CONFIG_SIG_SIGALARM: + Default the standard signal used with POSIX timers (SIGALRM). Default: 3 +
            • +
          • + CONFIG_SIG_SIGCHLD: + The SIGCHLD signal is sent to the parent of a child process when it exits, is interrupted (stopped), or resumes after being interrupted. + Default: 4 +
            • +
          • + CONFIG_SIG_SIGCONDTIMEDOUT: + This non-standard signal number is used in the implementation of pthread_cond_timedwait(). + Default 16. +
            • +
          • + CONFIG_SIG_SIGWORK: + SIGWORK is a non-standard signal used to wake up the internal NuttX worker thread. + Default: 17. +
            • +

          - Binary Loaders: + Binary Loaders:

          • @@ -4680,7 +4717,7 @@ build

          - System Logging: + System Logging:

          • @@ -4737,7 +4774,7 @@ build

          - Kernel build options: + Kernel build options:

          • @@ -4748,7 +4785,7 @@ build

          - OS setup related to on-demand paging: + OS setup related to on-demand paging:

          • @@ -4906,6 +4943,7 @@ build

          + Disabling OS Features. The following can be used to disable categories of APIs supported by the OS. If the compiler supports weak functions, then it should not be necessary to disable functions unless you want to diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 6e7526ed0..2724cf5a3 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -334,6 +334,11 @@ defconfig -- This is a configuration file similar to the Linux CONFIG_TASK_NAME_SIZE - Specifies that maximum size of a task name to save in the TCB. Useful if scheduler instrumentation is selected. Set to zero to disable. + CONFIG_SCHED_HAVE_PARENT - Remember the ID of the parent thread + when a new child thread is created. This support enables a + few minor features (such as SIGCHLD) and slightly increases + the size of the Task Control Block (TCB) of every task to hold + the ID of the parent thread. Default: disabled. CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - Used to initialize the internal time logic. CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. @@ -400,7 +405,7 @@ defconfig -- This is a configuration file similar to the Linux CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker thread. Default: CONFIG_IDLETHREAD_STACKSIZE. CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up - the worker thread. Default: 4 + the worker thread. Default: 17 CONFIG_SCHED_LPWORK. If CONFIG_SCHED_WORKQUEUE is defined, then a single work queue is created by default. If CONFIG_SCHED_LPWORK is also defined then an additional, lower-priority work queue will also be created. This @@ -426,6 +431,23 @@ defconfig -- This is a configuration file similar to the Linux where 'app' is the application name. If not defined, CONFIG_USER_ENTRYPOINT defaults to user_start. + Signal Numbers: + + CONFIG_SIG_SIGUSR1 - Value of standard user signal 1 (SIGUSR1). + Default: 1 + CONFIG_SIG_SIGUSR2 - Value of standard user signal 2 (SIGUSR2). + Default: 2 + CONFIG_SIG_SIGALARM - Default the standard signal used with POSIX + timers (SIGALRM). Default: 3 + CONFIG_SIG_SIGCHLD - The SIGCHLD signal is sent to the parent of a child + process when it exits, is interrupted (stopped), or resumes after being + interrupted. Default: 4 + + CONFIG_SIG_SIGCONDTIMEDOUT - This non-standard signal number is used in + the implementation of pthread_cond_timedwait(). Default 16. + CONFIG_SIG_SIGWORK - SIGWORK is a non-standard signal used to wake up + the internal NuttX worker thread. Default: 17. + Binary Loaders: CONFIG_BINFMT_DISABLE - By default, support for loadable binary formats is built. diff --git a/nuttx/configs/amber/hello/defconfig b/nuttx/configs/amber/hello/defconfig index 5d028e321..7e3d4ad70 100644 --- a/nuttx/configs/amber/hello/defconfig +++ b/nuttx/configs/amber/hello/defconfig @@ -142,7 +142,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/avr32dev1/nsh/defconfig b/nuttx/configs/avr32dev1/nsh/defconfig index 2b66316c3..acca1fbac 100755 --- a/nuttx/configs/avr32dev1/nsh/defconfig +++ b/nuttx/configs/avr32dev1/nsh/defconfig @@ -168,7 +168,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/avr32dev1/ostest/defconfig b/nuttx/configs/avr32dev1/ostest/defconfig index 9b67be09e..084c66233 100755 --- a/nuttx/configs/avr32dev1/ostest/defconfig +++ b/nuttx/configs/avr32dev1/ostest/defconfig @@ -168,7 +168,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/cloudctrl/nsh/defconfig b/nuttx/configs/cloudctrl/nsh/defconfig index 99c7eb790..8f145d3ab 100644 --- a/nuttx/configs/cloudctrl/nsh/defconfig +++ b/nuttx/configs/cloudctrl/nsh/defconfig @@ -273,7 +273,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/demo9s12ne64/ostest/defconfig b/nuttx/configs/demo9s12ne64/ostest/defconfig index 9c9668aac..79224989f 100755 --- a/nuttx/configs/demo9s12ne64/ostest/defconfig +++ b/nuttx/configs/demo9s12ne64/ostest/defconfig @@ -142,7 +142,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=256 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3131/nsh/defconfig b/nuttx/configs/ea3131/nsh/defconfig index 735af431b..8c7b351af 100644 --- a/nuttx/configs/ea3131/nsh/defconfig +++ b/nuttx/configs/ea3131/nsh/defconfig @@ -141,7 +141,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3131/ostest/defconfig b/nuttx/configs/ea3131/ostest/defconfig index 2f73ad5c9..19838ceab 100644 --- a/nuttx/configs/ea3131/ostest/defconfig +++ b/nuttx/configs/ea3131/ostest/defconfig @@ -141,7 +141,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3131/pgnsh/defconfig b/nuttx/configs/ea3131/pgnsh/defconfig index 32f89c500..1cc2bec7e 100644 --- a/nuttx/configs/ea3131/pgnsh/defconfig +++ b/nuttx/configs/ea3131/pgnsh/defconfig @@ -156,7 +156,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # OS setup related to on-demand paging: diff --git a/nuttx/configs/ea3131/usbserial/defconfig b/nuttx/configs/ea3131/usbserial/defconfig index 3d33a1b67..a82f69877 100644 --- a/nuttx/configs/ea3131/usbserial/defconfig +++ b/nuttx/configs/ea3131/usbserial/defconfig @@ -143,7 +143,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3131/usbstorage/defconfig b/nuttx/configs/ea3131/usbstorage/defconfig index 8d9933f55..a957fb3ab 100644 --- a/nuttx/configs/ea3131/usbstorage/defconfig +++ b/nuttx/configs/ea3131/usbstorage/defconfig @@ -144,7 +144,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ea3152/ostest/defconfig b/nuttx/configs/ea3152/ostest/defconfig index d85fd5821..6d0bb63f0 100644 --- a/nuttx/configs/ea3152/ostest/defconfig +++ b/nuttx/configs/ea3152/ostest/defconfig @@ -142,7 +142,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/fire-stm32v2/nsh/defconfig b/nuttx/configs/fire-stm32v2/nsh/defconfig index c42bb1569..266098496 100644 --- a/nuttx/configs/fire-stm32v2/nsh/defconfig +++ b/nuttx/configs/fire-stm32v2/nsh/defconfig @@ -266,7 +266,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/hymini-stm32v/buttons/defconfig b/nuttx/configs/hymini-stm32v/buttons/defconfig index bbd6c2319..e90ded32a 100644 --- a/nuttx/configs/hymini-stm32v/buttons/defconfig +++ b/nuttx/configs/hymini-stm32v/buttons/defconfig @@ -194,7 +194,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/hymini-stm32v/nsh/defconfig b/nuttx/configs/hymini-stm32v/nsh/defconfig index ca589278a..eeb3b09ff 100755 --- a/nuttx/configs/hymini-stm32v/nsh/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh/defconfig @@ -192,7 +192,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/hymini-stm32v/nsh2/defconfig b/nuttx/configs/hymini-stm32v/nsh2/defconfig index 5a8c0bea2..ecf4c3a3d 100644 --- a/nuttx/configs/hymini-stm32v/nsh2/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh2/defconfig @@ -202,7 +202,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/hymini-stm32v/nx/defconfig b/nuttx/configs/hymini-stm32v/nx/defconfig index 28b08582c..c6e049142 100644 --- a/nuttx/configs/hymini-stm32v/nx/defconfig +++ b/nuttx/configs/hymini-stm32v/nx/defconfig @@ -193,7 +193,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/hymini-stm32v/nxlines/defconfig b/nuttx/configs/hymini-stm32v/nxlines/defconfig index 880efb7d8..fb968c483 100644 --- a/nuttx/configs/hymini-stm32v/nxlines/defconfig +++ b/nuttx/configs/hymini-stm32v/nxlines/defconfig @@ -197,7 +197,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/hymini-stm32v/usbserial/defconfig b/nuttx/configs/hymini-stm32v/usbserial/defconfig index 732c1e8b6..0c7317a00 100755 --- a/nuttx/configs/hymini-stm32v/usbserial/defconfig +++ b/nuttx/configs/hymini-stm32v/usbserial/defconfig @@ -195,7 +195,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/hymini-stm32v/usbstorage/defconfig b/nuttx/configs/hymini-stm32v/usbstorage/defconfig index 7e49de0e8..16f43a1ce 100755 --- a/nuttx/configs/hymini-stm32v/usbstorage/defconfig +++ b/nuttx/configs/hymini-stm32v/usbstorage/defconfig @@ -195,7 +195,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/kwikstik-k40/ostest/defconfig b/nuttx/configs/kwikstik-k40/ostest/defconfig index 759cff20b..5f0291ced 100755 --- a/nuttx/configs/kwikstik-k40/ostest/defconfig +++ b/nuttx/configs/kwikstik-k40/ostest/defconfig @@ -204,7 +204,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/lincoln60/nsh/defconfig b/nuttx/configs/lincoln60/nsh/defconfig index e5009f8d6..908b01e3a 100644 --- a/nuttx/configs/lincoln60/nsh/defconfig +++ b/nuttx/configs/lincoln60/nsh/defconfig @@ -181,7 +181,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/lincoln60/ostest/defconfig b/nuttx/configs/lincoln60/ostest/defconfig index 986f9bf43..ea42f5763 100644 --- a/nuttx/configs/lincoln60/ostest/defconfig +++ b/nuttx/configs/lincoln60/ostest/defconfig @@ -187,7 +187,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/lpc4330-xplorer/nsh/defconfig b/nuttx/configs/lpc4330-xplorer/nsh/defconfig index 0afcbae89..78b9e3f71 100644 --- a/nuttx/configs/lpc4330-xplorer/nsh/defconfig +++ b/nuttx/configs/lpc4330-xplorer/nsh/defconfig @@ -227,7 +227,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig index 76d3f11e9..342fe04a0 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig +++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig @@ -224,7 +224,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig index f56dfca1b..2e0d2eea6 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -186,7 +186,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig index ef70b5508..23f375a47 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -189,7 +189,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig b/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig index a0d3cd283..3f8474103 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig @@ -191,7 +191,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig index 660bd6c8b..10b63eb2d 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig @@ -184,7 +184,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig b/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig index 755869156..b6ea25948 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -186,7 +186,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig index 004d92cb3..9e4bcb15d 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig @@ -187,7 +187,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/mbed/hidkbd/defconfig b/nuttx/configs/mbed/hidkbd/defconfig index ba0af97ca..b4bf00872 100644 --- a/nuttx/configs/mbed/hidkbd/defconfig +++ b/nuttx/configs/mbed/hidkbd/defconfig @@ -186,7 +186,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/mbed/nsh/defconfig b/nuttx/configs/mbed/nsh/defconfig index a1168dd19..2156af80e 100755 --- a/nuttx/configs/mbed/nsh/defconfig +++ b/nuttx/configs/mbed/nsh/defconfig @@ -181,7 +181,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/micropendous3/hello/defconfig b/nuttx/configs/micropendous3/hello/defconfig index ea8faf8f5..ebc755abc 100644 --- a/nuttx/configs/micropendous3/hello/defconfig +++ b/nuttx/configs/micropendous3/hello/defconfig @@ -137,7 +137,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/mirtoo/nsh/defconfig b/nuttx/configs/mirtoo/nsh/defconfig index f2e2b8991..94a6b8b17 100644 --- a/nuttx/configs/mirtoo/nsh/defconfig +++ b/nuttx/configs/mirtoo/nsh/defconfig @@ -200,7 +200,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/mirtoo/nxffs/defconfig b/nuttx/configs/mirtoo/nxffs/defconfig index 29de6f1e7..d633e56d9 100644 --- a/nuttx/configs/mirtoo/nxffs/defconfig +++ b/nuttx/configs/mirtoo/nxffs/defconfig @@ -200,7 +200,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/mirtoo/ostest/defconfig b/nuttx/configs/mirtoo/ostest/defconfig index dfe7a25c5..471dab444 100644 --- a/nuttx/configs/mirtoo/ostest/defconfig +++ b/nuttx/configs/mirtoo/ostest/defconfig @@ -190,7 +190,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/ne64badge/ostest/defconfig b/nuttx/configs/ne64badge/ostest/defconfig index 78e10f87c..e6e0df700 100755 --- a/nuttx/configs/ne64badge/ostest/defconfig +++ b/nuttx/configs/ne64badge/ostest/defconfig @@ -148,7 +148,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=256 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/nucleus2g/nsh/defconfig b/nuttx/configs/nucleus2g/nsh/defconfig index cc747e0c8..2c440bc7f 100755 --- a/nuttx/configs/nucleus2g/nsh/defconfig +++ b/nuttx/configs/nucleus2g/nsh/defconfig @@ -182,7 +182,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/nucleus2g/ostest/defconfig b/nuttx/configs/nucleus2g/ostest/defconfig index 3d777de9c..c32b1e715 100755 --- a/nuttx/configs/nucleus2g/ostest/defconfig +++ b/nuttx/configs/nucleus2g/ostest/defconfig @@ -181,7 +181,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/nucleus2g/usbserial/defconfig b/nuttx/configs/nucleus2g/usbserial/defconfig index e5762e8bc..abe9ac020 100755 --- a/nuttx/configs/nucleus2g/usbserial/defconfig +++ b/nuttx/configs/nucleus2g/usbserial/defconfig @@ -182,7 +182,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/nucleus2g/usbstorage/defconfig b/nuttx/configs/nucleus2g/usbstorage/defconfig index 88c54bccc..adab8f4f0 100755 --- a/nuttx/configs/nucleus2g/usbstorage/defconfig +++ b/nuttx/configs/nucleus2g/usbstorage/defconfig @@ -183,7 +183,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig index 36c5eefc4..8ff0d95aa 100755 --- a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig @@ -192,7 +192,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y # diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig index 35a7bfc3d..634601187 100755 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -262,7 +262,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set # CONFIG_SCHED_WAITPID is not set # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/olimex-lpc1766stk/nettest/defconfig b/nuttx/configs/olimex-lpc1766stk/nettest/defconfig index f89d265b0..4ab823b8c 100755 --- a/nuttx/configs/olimex-lpc1766stk/nettest/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nettest/defconfig @@ -192,7 +192,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index 0d82b458b..096f08a8a 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -194,7 +194,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/olimex-lpc1766stk/nx/defconfig b/nuttx/configs/olimex-lpc1766stk/nx/defconfig index 55c480fe3..28ad229d6 100755 --- a/nuttx/configs/olimex-lpc1766stk/nx/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nx/defconfig @@ -197,7 +197,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-lpc1766stk/ostest/defconfig b/nuttx/configs/olimex-lpc1766stk/ostest/defconfig index 32e2cacc5..02732e74a 100755 --- a/nuttx/configs/olimex-lpc1766stk/ostest/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/ostest/defconfig @@ -187,7 +187,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig b/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig index ff2674c79..9becdee04 100755 --- a/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -190,7 +190,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig b/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig index 936dba359..fe42a861f 100755 --- a/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig @@ -188,7 +188,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig b/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig index 603a1562a..995cbad59 100755 --- a/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig @@ -188,7 +188,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig b/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig index 2c29d2ffd..e11c2c404 100755 --- a/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig @@ -189,7 +189,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-stm32-p107/nsh/defconfig b/nuttx/configs/olimex-stm32-p107/nsh/defconfig index 7aaae2514..0a831ce9f 100644 --- a/nuttx/configs/olimex-stm32-p107/nsh/defconfig +++ b/nuttx/configs/olimex-stm32-p107/nsh/defconfig @@ -234,7 +234,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-stm32-p107/ostest/defconfig b/nuttx/configs/olimex-stm32-p107/ostest/defconfig index d4bba38fb..272832381 100644 --- a/nuttx/configs/olimex-stm32-p107/ostest/defconfig +++ b/nuttx/configs/olimex-stm32-p107/ostest/defconfig @@ -242,7 +242,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/olimex-strp711/nettest/defconfig b/nuttx/configs/olimex-strp711/nettest/defconfig index 4d73540b8..a8767c7be 100755 --- a/nuttx/configs/olimex-strp711/nettest/defconfig +++ b/nuttx/configs/olimex-strp711/nettest/defconfig @@ -160,7 +160,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig index b4bd30ae8..7bce554ac 100644 --- a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig @@ -189,7 +189,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig index 08bdccddd..730b8134a 100644 --- a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig @@ -187,7 +187,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index f2cd27560..32220d89b 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -253,7 +253,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig index 6f227f638..a7a1ff18a 100644 --- a/nuttx/configs/pic32-starterkit/nsh2/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig @@ -252,7 +252,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig index 922cb8901..3a55de491 100644 --- a/nuttx/configs/pic32-starterkit/ostest/defconfig +++ b/nuttx/configs/pic32-starterkit/ostest/defconfig @@ -250,7 +250,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig index aa7fc23df..d39f8bc40 100644 --- a/nuttx/configs/pic32mx7mmb/nsh/defconfig +++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig @@ -259,7 +259,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/pic32mx7mmb/ostest/defconfig b/nuttx/configs/pic32mx7mmb/ostest/defconfig index 1d656380d..b3cecf98d 100644 --- a/nuttx/configs/pic32mx7mmb/ostest/defconfig +++ b/nuttx/configs/pic32mx7mmb/ostest/defconfig @@ -250,7 +250,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/sam3u-ek/knsh/defconfig b/nuttx/configs/sam3u-ek/knsh/defconfig index e61180407..30f60f0e3 100755 --- a/nuttx/configs/sam3u-ek/knsh/defconfig +++ b/nuttx/configs/sam3u-ek/knsh/defconfig @@ -186,7 +186,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # These NSH commands are (temporarily) disable because more support is needed diff --git a/nuttx/configs/sam3u-ek/nsh/defconfig b/nuttx/configs/sam3u-ek/nsh/defconfig index 288df5957..971598464 100755 --- a/nuttx/configs/sam3u-ek/nsh/defconfig +++ b/nuttx/configs/sam3u-ek/nsh/defconfig @@ -171,7 +171,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/sam3u-ek/nx/defconfig b/nuttx/configs/sam3u-ek/nx/defconfig index 7b56b9d41..dd55d9c93 100755 --- a/nuttx/configs/sam3u-ek/nx/defconfig +++ b/nuttx/configs/sam3u-ek/nx/defconfig @@ -172,7 +172,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/sam3u-ek/ostest/defconfig b/nuttx/configs/sam3u-ek/ostest/defconfig index b2e9a5184..bf15cb1a5 100755 --- a/nuttx/configs/sam3u-ek/ostest/defconfig +++ b/nuttx/configs/sam3u-ek/ostest/defconfig @@ -172,7 +172,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/sam3u-ek/touchscreen/defconfig b/nuttx/configs/sam3u-ek/touchscreen/defconfig index e89db8c4b..414eadb6e 100755 --- a/nuttx/configs/sam3u-ek/touchscreen/defconfig +++ b/nuttx/configs/sam3u-ek/touchscreen/defconfig @@ -180,7 +180,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/shenzhou/nsh/defconfig b/nuttx/configs/shenzhou/nsh/defconfig index c54d714d0..383522b6f 100644 --- a/nuttx/configs/shenzhou/nsh/defconfig +++ b/nuttx/configs/shenzhou/nsh/defconfig @@ -273,7 +273,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/shenzhou/nxwm/defconfig b/nuttx/configs/shenzhou/nxwm/defconfig index 975327747..b9bf72aeb 100644 --- a/nuttx/configs/shenzhou/nxwm/defconfig +++ b/nuttx/configs/shenzhou/nxwm/defconfig @@ -309,7 +309,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set # CONFIG_SCHED_WAITPID is not set # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/shenzhou/thttpd/defconfig b/nuttx/configs/shenzhou/thttpd/defconfig index 958ab02ed..d7af34821 100644 --- a/nuttx/configs/shenzhou/thttpd/defconfig +++ b/nuttx/configs/shenzhou/thttpd/defconfig @@ -260,7 +260,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index a60edd4ac..2d627a66d 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -72,7 +72,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n CONFIG_SCHED_ONEXIT=n diff --git a/nuttx/configs/sim/nsh2/defconfig b/nuttx/configs/sim/nsh2/defconfig index e5dcce322..c9e5b343f 100644 --- a/nuttx/configs/sim/nsh2/defconfig +++ b/nuttx/configs/sim/nsh2/defconfig @@ -91,7 +91,7 @@ CONFIG_PRIORITY_INHERITANCE=n CONFIG_SEM_PREALLOCHOLDERS=0 CONFIG_SEM_NNESTPRIO=0 CONFIG_FDCLONE_DISABLE=n -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_FDCLONE_STDIO=n CONFIG_SDCLONE_DISABLE=y CONFIG_SCHED_WORKQUEUE=n diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index 43d78e6a2..5cea9a6d4 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -57,7 +57,7 @@ CONFIG_DEBUG_VERBOSE=y # # CONFIG_DEBUG_ANALOG is not set # CONFIG_DEBUG_DMA is not set -# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_DEBUG_SYMBOLS=y # # System Type @@ -131,6 +131,7 @@ CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=0 # CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=32 +CONFIG_SCHED_HAVE_PARENT=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -156,6 +157,15 @@ CONFIG_DISABLE_OS_API=y # CONFIG_DISABLE_ENVIRON is not set CONFIG_DISABLE_POLL=y +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCHLD=4 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + # # Sizes of configurable things (0 disables) # @@ -352,6 +362,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PASHELLO is not set # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set diff --git a/nuttx/configs/stm3210e-eval/RIDE/defconfig b/nuttx/configs/stm3210e-eval/RIDE/defconfig index e71540c24..6d84e7c36 100755 --- a/nuttx/configs/stm3210e-eval/RIDE/defconfig +++ b/nuttx/configs/stm3210e-eval/RIDE/defconfig @@ -200,7 +200,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/stm3210e-eval/buttons/defconfig b/nuttx/configs/stm3210e-eval/buttons/defconfig index 0d6882b5d..37e19171f 100644 --- a/nuttx/configs/stm3210e-eval/buttons/defconfig +++ b/nuttx/configs/stm3210e-eval/buttons/defconfig @@ -210,7 +210,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/stm3210e-eval/composite/defconfig b/nuttx/configs/stm3210e-eval/composite/defconfig index 2db58aee5..7fee33794 100755 --- a/nuttx/configs/stm3210e-eval/composite/defconfig +++ b/nuttx/configs/stm3210e-eval/composite/defconfig @@ -210,7 +210,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3210e-eval/nsh/defconfig b/nuttx/configs/stm3210e-eval/nsh/defconfig index 52fdd777f..b5e52e494 100755 --- a/nuttx/configs/stm3210e-eval/nsh/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh/defconfig @@ -208,7 +208,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/stm3210e-eval/nsh2/defconfig b/nuttx/configs/stm3210e-eval/nsh2/defconfig index 18e42d539..30a0bb327 100644 --- a/nuttx/configs/stm3210e-eval/nsh2/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh2/defconfig @@ -255,7 +255,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3210e-eval/nx/defconfig b/nuttx/configs/stm3210e-eval/nx/defconfig index 68a3ad9b5..0ad42dfbe 100644 --- a/nuttx/configs/stm3210e-eval/nx/defconfig +++ b/nuttx/configs/stm3210e-eval/nx/defconfig @@ -209,7 +209,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3210e-eval/nxconsole/defconfig b/nuttx/configs/stm3210e-eval/nxconsole/defconfig index 9cb8689c6..7dd5878bf 100644 --- a/nuttx/configs/stm3210e-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3210e-eval/nxconsole/defconfig @@ -209,7 +209,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3210e-eval/nxlines/defconfig b/nuttx/configs/stm3210e-eval/nxlines/defconfig index ab42612f3..068a17acb 100644 --- a/nuttx/configs/stm3210e-eval/nxlines/defconfig +++ b/nuttx/configs/stm3210e-eval/nxlines/defconfig @@ -209,7 +209,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3210e-eval/nxtext/defconfig b/nuttx/configs/stm3210e-eval/nxtext/defconfig index c00e9b1e8..b6f88a3ca 100644 --- a/nuttx/configs/stm3210e-eval/nxtext/defconfig +++ b/nuttx/configs/stm3210e-eval/nxtext/defconfig @@ -209,7 +209,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3210e-eval/ostest/defconfig b/nuttx/configs/stm3210e-eval/ostest/defconfig index 8ed1795a6..0553b1a98 100755 --- a/nuttx/configs/stm3210e-eval/ostest/defconfig +++ b/nuttx/configs/stm3210e-eval/ostest/defconfig @@ -220,7 +220,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/stm3210e-eval/pm/defconfig b/nuttx/configs/stm3210e-eval/pm/defconfig index 7babce8f6..61bd995c8 100644 --- a/nuttx/configs/stm3210e-eval/pm/defconfig +++ b/nuttx/configs/stm3210e-eval/pm/defconfig @@ -265,7 +265,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3210e-eval/usbserial/defconfig b/nuttx/configs/stm3210e-eval/usbserial/defconfig index b41b41f50..94059c07c 100755 --- a/nuttx/configs/stm3210e-eval/usbserial/defconfig +++ b/nuttx/configs/stm3210e-eval/usbserial/defconfig @@ -210,7 +210,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/stm3210e-eval/usbstorage/defconfig b/nuttx/configs/stm3210e-eval/usbstorage/defconfig index 9f927d7e3..5c1ed5fb2 100755 --- a/nuttx/configs/stm3210e-eval/usbstorage/defconfig +++ b/nuttx/configs/stm3210e-eval/usbstorage/defconfig @@ -210,7 +210,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/stm3220g-eval/dhcpd/defconfig b/nuttx/configs/stm3220g-eval/dhcpd/defconfig index 04f243d71..29baf9af0 100644 --- a/nuttx/configs/stm3220g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3220g-eval/dhcpd/defconfig @@ -262,7 +262,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3220g-eval/nettest/defconfig b/nuttx/configs/stm3220g-eval/nettest/defconfig index 201df86b0..08e04ad0e 100644 --- a/nuttx/configs/stm3220g-eval/nettest/defconfig +++ b/nuttx/configs/stm3220g-eval/nettest/defconfig @@ -262,7 +262,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3220g-eval/nsh/defconfig b/nuttx/configs/stm3220g-eval/nsh/defconfig index 8baf52f7e..bd9d02860 100644 --- a/nuttx/configs/stm3220g-eval/nsh/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh/defconfig @@ -297,7 +297,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3220g-eval/nsh2/defconfig b/nuttx/configs/stm3220g-eval/nsh2/defconfig index c273ce60f..b5fe843bc 100644 --- a/nuttx/configs/stm3220g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh2/defconfig @@ -296,7 +296,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3220g-eval/nxwm/defconfig b/nuttx/configs/stm3220g-eval/nxwm/defconfig index ab061f07a..145792ddb 100644 --- a/nuttx/configs/stm3220g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3220g-eval/nxwm/defconfig @@ -316,7 +316,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/stm3220g-eval/ostest/defconfig b/nuttx/configs/stm3220g-eval/ostest/defconfig index 2393d0a69..f63f96c9a 100644 --- a/nuttx/configs/stm3220g-eval/ostest/defconfig +++ b/nuttx/configs/stm3220g-eval/ostest/defconfig @@ -261,7 +261,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3220g-eval/telnetd/defconfig b/nuttx/configs/stm3220g-eval/telnetd/defconfig index 1401dc6e7..f529198f1 100644 --- a/nuttx/configs/stm3220g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3220g-eval/telnetd/defconfig @@ -262,7 +262,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/dhcpd/defconfig b/nuttx/configs/stm3240g-eval/dhcpd/defconfig index 80293f66a..5199cf85c 100644 --- a/nuttx/configs/stm3240g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3240g-eval/dhcpd/defconfig @@ -268,7 +268,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/nettest/defconfig b/nuttx/configs/stm3240g-eval/nettest/defconfig index 81a53bd68..c5e0da795 100644 --- a/nuttx/configs/stm3240g-eval/nettest/defconfig +++ b/nuttx/configs/stm3240g-eval/nettest/defconfig @@ -268,7 +268,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig index 54eb1d56f..6c19ed531 100644 --- a/nuttx/configs/stm3240g-eval/nsh/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh/defconfig @@ -301,7 +301,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n CONFIG_DEV_RANDOM=y diff --git a/nuttx/configs/stm3240g-eval/nsh2/defconfig b/nuttx/configs/stm3240g-eval/nsh2/defconfig index ba6445615..08690ade3 100644 --- a/nuttx/configs/stm3240g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh2/defconfig @@ -302,7 +302,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/nxconsole/defconfig b/nuttx/configs/stm3240g-eval/nxconsole/defconfig index f8a1fb7d5..202fa4378 100644 --- a/nuttx/configs/stm3240g-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3240g-eval/nxconsole/defconfig @@ -301,7 +301,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/nxwm/defconfig b/nuttx/configs/stm3240g-eval/nxwm/defconfig index 5dfdb28fc..a220af2d1 100644 --- a/nuttx/configs/stm3240g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3240g-eval/nxwm/defconfig @@ -302,7 +302,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n CONFIG_SCHED_ONEXIT=y diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig index 38b51e84b..fcc54aa4b 100644 --- a/nuttx/configs/stm3240g-eval/ostest/defconfig +++ b/nuttx/configs/stm3240g-eval/ostest/defconfig @@ -266,7 +266,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/telnetd/defconfig b/nuttx/configs/stm3240g-eval/telnetd/defconfig index 471845c14..5aef41c27 100644 --- a/nuttx/configs/stm3240g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3240g-eval/telnetd/defconfig @@ -268,7 +268,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm3240g-eval/webserver/defconfig b/nuttx/configs/stm3240g-eval/webserver/defconfig index e9cbbf93d..6d09968e9 100644 --- a/nuttx/configs/stm3240g-eval/webserver/defconfig +++ b/nuttx/configs/stm3240g-eval/webserver/defconfig @@ -302,7 +302,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=2048 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm32f100rc_generic/nsh/defconfig b/nuttx/configs/stm32f100rc_generic/nsh/defconfig index 65ac9a73d..12193e7ed 100644 --- a/nuttx/configs/stm32f100rc_generic/nsh/defconfig +++ b/nuttx/configs/stm32f100rc_generic/nsh/defconfig @@ -249,7 +249,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # CONFIG_SCHED_LPWORK is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt index c1d484279..39fb41d78 100644 --- a/nuttx/configs/stm32f4discovery/README.txt +++ b/nuttx/configs/stm32f4discovery/README.txt @@ -1447,6 +1447,32 @@ Where is one of the following: STANDBY mode. This used of the RTC alarm could conflict with other uses of the RTC alarm in your application. + + posix_spawn: + ------------ + This configuration directory, performs a simple test os the posix_spawn + interface using apps/examples/posix_spawn. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default toolchain: + + CONFIG_HOST_WINDOWS=y : Builds under windows + CONFIG_WINDOWS_CYGWIN=y : Using Cygwin and + CONFIG_STM32_CODESOURCERYW=y : The native Windows CodeSourcery toolchain + + 3. By default, this project assumes that you are *NOT* using the DFU + bootloader. + winbuild: -------- diff --git a/nuttx/configs/stm32f4discovery/nsh/defconfig b/nuttx/configs/stm32f4discovery/nsh/defconfig index 8967fd01c..98034e22e 100644 --- a/nuttx/configs/stm32f4discovery/nsh/defconfig +++ b/nuttx/configs/stm32f4discovery/nsh/defconfig @@ -282,7 +282,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm32f4discovery/pm/defconfig b/nuttx/configs/stm32f4discovery/pm/defconfig index 105eb4d37..3e24168cd 100644 --- a/nuttx/configs/stm32f4discovery/pm/defconfig +++ b/nuttx/configs/stm32f4discovery/pm/defconfig @@ -283,7 +283,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/stm32f4discovery/posix_spawn/defconfig b/nuttx/configs/stm32f4discovery/posix_spawn/defconfig index b908393d8..9e30ada8a 100644 --- a/nuttx/configs/stm32f4discovery/posix_spawn/defconfig +++ b/nuttx/configs/stm32f4discovery/posix_spawn/defconfig @@ -441,7 +441,7 @@ CONFIG_EOL_IS_EITHER_CRLF=y CONFIG_LIBC_EXECFUNCS=y CONFIG_EXECFUNCS_SYMTAB="exports" CONFIG_EXECFUNCS_NSYMBOLS=10 -CONFIG_POSIX_SPAWN_STACKSIZE=768 +CONFIG_POSIX_SPAWN_STACKSIZE=1024 # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y diff --git a/nuttx/configs/sure-pic32mx/nsh/defconfig b/nuttx/configs/sure-pic32mx/nsh/defconfig index 050f30247..60c4dc53d 100644 --- a/nuttx/configs/sure-pic32mx/nsh/defconfig +++ b/nuttx/configs/sure-pic32mx/nsh/defconfig @@ -202,7 +202,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/sure-pic32mx/ostest/defconfig b/nuttx/configs/sure-pic32mx/ostest/defconfig index eb386e232..1bca11c47 100644 --- a/nuttx/configs/sure-pic32mx/ostest/defconfig +++ b/nuttx/configs/sure-pic32mx/ostest/defconfig @@ -188,7 +188,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/sure-pic32mx/usbnsh/defconfig b/nuttx/configs/sure-pic32mx/usbnsh/defconfig index 2b28b94c7..978e16541 100644 --- a/nuttx/configs/sure-pic32mx/usbnsh/defconfig +++ b/nuttx/configs/sure-pic32mx/usbnsh/defconfig @@ -199,7 +199,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/teensy/hello/defconfig b/nuttx/configs/teensy/hello/defconfig index 93376ac57..8fafe1a10 100644 --- a/nuttx/configs/teensy/hello/defconfig +++ b/nuttx/configs/teensy/hello/defconfig @@ -137,7 +137,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for nxflat diff --git a/nuttx/configs/teensy/nsh/defconfig b/nuttx/configs/teensy/nsh/defconfig index ffcd94c1d..faeb0b103 100755 --- a/nuttx/configs/teensy/nsh/defconfig +++ b/nuttx/configs/teensy/nsh/defconfig @@ -137,7 +137,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/teensy/usbstorage/defconfig b/nuttx/configs/teensy/usbstorage/defconfig index dba45073f..1f0186897 100755 --- a/nuttx/configs/teensy/usbstorage/defconfig +++ b/nuttx/configs/teensy/usbstorage/defconfig @@ -138,7 +138,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # Settings for NXFLAT diff --git a/nuttx/configs/twr-k60n512/nsh/defconfig b/nuttx/configs/twr-k60n512/nsh/defconfig index aeb0c5359..7a4bb3b3a 100644 --- a/nuttx/configs/twr-k60n512/nsh/defconfig +++ b/nuttx/configs/twr-k60n512/nsh/defconfig @@ -204,7 +204,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/twr-k60n512/ostest/defconfig b/nuttx/configs/twr-k60n512/ostest/defconfig index 9cf37c763..355e5773b 100644 --- a/nuttx/configs/twr-k60n512/ostest/defconfig +++ b/nuttx/configs/twr-k60n512/ostest/defconfig @@ -203,7 +203,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 # # The following can be used to disable categories of diff --git a/nuttx/configs/ubw32/nsh/defconfig b/nuttx/configs/ubw32/nsh/defconfig index 320b7e266..ad18c12b6 100644 --- a/nuttx/configs/ubw32/nsh/defconfig +++ b/nuttx/configs/ubw32/nsh/defconfig @@ -189,7 +189,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig index 71f286700..60322d4f6 100644 --- a/nuttx/configs/ubw32/ostest/defconfig +++ b/nuttx/configs/ubw32/ostest/defconfig @@ -188,7 +188,7 @@ CONFIG_SCHED_WORKQUEUE=n CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=n CONFIG_SCHED_ATEXIT=n diff --git a/nuttx/configs/vsn/nsh/defconfig b/nuttx/configs/vsn/nsh/defconfig index fa5570596..2b7d8a20c 100755 --- a/nuttx/configs/vsn/nsh/defconfig +++ b/nuttx/configs/vsn/nsh/defconfig @@ -247,7 +247,7 @@ CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=4 +CONFIG_SIG_SIGWORK=17 CONFIG_SCHED_WAITPID=y # # The following can be used to disable categories of diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h index 940bf1f1b..6c67e1500 100644 --- a/nuttx/include/nuttx/sched.h +++ b/nuttx/include/nuttx/sched.h @@ -202,6 +202,9 @@ struct _TCB /* Task Management Fields *****************************************************/ pid_t pid; /* This is the ID of the thread */ +#ifdef CONFIG_SCHED_HAVE_PARENT + pid_t parent; /* This is the ID of the parent thread */ +#endif start_t start; /* Thread start function */ entry_t entry; /* Entry Point into the thread */ diff --git a/nuttx/include/nuttx/wqueue.h b/nuttx/include/nuttx/wqueue.h index c509bf197..d56901d89 100644 --- a/nuttx/include/nuttx/wqueue.h +++ b/nuttx/include/nuttx/wqueue.h @@ -68,7 +68,7 @@ * CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker * thread. Default: CONFIG_IDLETHREAD_STACKSIZE. * CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up - * the worker thread. Default: 4 + * the worker thread. Default: 17 * * CONFIG_SCHED_LPWORK. If CONFIG_SCHED_WORKQUEUE is defined, then a single * work queue is created by default. If CONFIG_SCHED_LPWORK is also defined diff --git a/nuttx/include/signal.h b/nuttx/include/signal.h index 02b222343..30726105b 100644 --- a/nuttx/include/signal.h +++ b/nuttx/include/signal.h @@ -66,44 +66,56 @@ /* A few of the real time signals are used within the OS. They have * default values that can be overridden from the configuration file. The - * rest are all user signals: + * rest are all user signals. + * + * These are semi-standard signal definitions: */ #ifndef CONFIG_SIG_SIGUSR1 -#define SIGUSR1 0 /* User signal 1 */ +# define SIGUSR1 1 /* User signal 1 */ #else -#define SIGUSR1 CONFIG_SIG_SIGUSR1 +# define SIGUSR1 CONFIG_SIG_SIGUSR1 #endif #ifndef CONFIG_SIG_SIGUSR2 -#define SIGUSR2 1 /* User signal 2 */ +# define SIGUSR2 2 /* User signal 2 */ #else -#define SIGUSR2 CONFIG_SIG_SIGUSR2 +# define SIGUSR2 CONFIG_SIG_SIGUSR2 #endif #ifndef CONFIG_SIG_SIGALARM -#define SIGALRM 2 /* Default signal used with POSIX timers (used only */ +# define SIGALRM 3 /* Default signal used with POSIX timers (used only */ /* no other signal is provided) */ #else -#define SIGALRM CONFIG_SIG_SIGALARM +# define SIGALRM CONFIG_SIG_SIGALARM #endif -#ifndef CONFIG_DISABLE_PTHREAD -#ifndef CONFIG_SIG_SIGCONDTIMEDOUT -#define SIGCONDTIMEDOUT 3 /* Used in the implementation of pthread_cond_timedwait */ -#else -#define SIGCONDTIMEDOUT CONFIG_SIG_SIGCONDTIMEDOUT +#ifdef CONFIG_SCHED_HAVE_PARENT +# ifndef CONFIG_SIG_SIGCHLD +# define SIGCHLD 4 /* Used by child threads to signal parent thread */ +# else +# define SIGCHLD CONFIG_SIG_SIGCHLD +# endif #endif + +/* The following are non-standard signal definitions */ + +#ifndef CONFIG_DISABLE_PTHREAD +# ifndef CONFIG_SIG_SIGCONDTIMEDOUT +# define SIGCONDTIMEDOUT 16 /* Used in the implementation of pthread_cond_timedwait */ +# else +# define SIGCONDTIMEDOUT CONFIG_SIG_SIGCONDTIMEDOUT +# endif #endif /* SIGWORK is used to wake up various internal, NuttX worker thread */ #if defined(CONFIG_SCHED_WORKQUEUE) || defined(CONFIG_PAGING) -#ifndef CONFIG_SIG_SIGWORK -#define SIGWORK 4 /* Used to wake up the work queue */ -#else -#define SIGWORK CONFIG_SIG_SIGWORK -#endif +# ifndef CONFIG_SIG_SIGWORK +# define SIGWORK 17 /* Used to wake up the work queue */ +# else +# define SIGWORK CONFIG_SIG_SIGWORK +# endif #endif /* sigprocmask() "how" definitions. Only one of the following can be specified: */ @@ -122,12 +134,18 @@ /* These are the possible values of the signfo si_code field */ -#define SI_USER 0 /* Signal sent from kill, raise, or abort */ -#define SI_QUEUE 1 /* Signal sent from sigqueue */ -#define SI_TIMER 2 /* Signal is result of timer expiration */ -#define SI_ASYNCIO 3 /* Signal is the result of asynch IO completion */ -#define SI_MESGQ 4 /* Signal generated by arrival of a message on an */ - /* empty message queue */ +#define SI_USER 0 /* Signal sent from kill, raise, or abort */ +#define SI_QUEUE 1 /* Signal sent from sigqueue */ +#define SI_TIMER 2 /* Signal is result of timer expiration */ +#define SI_ASYNCIO 3 /* Signal is the result of asynch IO completion */ +#define SI_MESGQ 4 /* Signal generated by arrival of a message on an */ + /* empty message queue */ +#define CLD_EXITED 5 /* Child has exited (SIGCHLD only) */ +#define CLD_KILLED 6 /* Child was killed (SIGCHLD only) */ +#define CLD_DUMPED 7 /* Child terminated abnormally (SIGCHLD only) */ +#define CLD_TRAPPED 8 /* Traced child has trapped (SIGCHLD only) */ +#define CLD_STOPPED 9 /* Child has stopped (SIGCHLD only) */ +#define CLD_CONTINUED 10 /* Stopped child had continued (SIGCHLD only) */ /* Values for the sigev_notify field of struct sigevent */ @@ -175,6 +193,10 @@ struct siginfo uint8_t si_signo; /* Identifies signal */ uint8_t si_code; /* Source: SI_USER, SI_QUEUE, SI_TIMER, SI_ASYNCIO, or SI_MESGQ */ union sigval si_value; /* Data passed with signal */ +#ifdef CONFIG_SCHED_HAVE_PARENT + pid_t si_pid; /* Sending task ID */ + int si_status; /* Exit value or signal (SIGCHLD only). */ +#endif }; typedef struct siginfo siginfo_t; diff --git a/nuttx/libc/Kconfig b/nuttx/libc/Kconfig index 2f091f1c7..72a6a5346 100644 --- a/nuttx/libc/Kconfig +++ b/nuttx/libc/Kconfig @@ -123,11 +123,12 @@ config EXECFUNCS_NSYMBOLS config POSIX_SPAWN_STACKSIZE int "posix_spawn Stack Size" - default 768 + default 1024 ---help--- If posix_spawn[p] uses I/O redirection options, then it will require an intermediary/proxy task to muck with the file descriptors. This - configuration item specifies the stack size used for the proxy. + configuration item specifies the stack size used for the proxy. Default: + 1024 bytes. endif diff --git a/nuttx/sched/Kconfig b/nuttx/sched/Kconfig index bfaec3b5d..69621a1fa 100644 --- a/nuttx/sched/Kconfig +++ b/nuttx/sched/Kconfig @@ -38,6 +38,16 @@ config TASK_NAME_SIZE Useful if scheduler instrumentation is selected. Set to zero to disable. +config SCHED_HAVE_PARENT + bool "Remember Parent" + default n + ---help--- + Remember the ID of the parent thread when a new child thread is + created. This support enables a few minor features (such as + SIGCHLD) and slightly increases the size of the Task Control Block + (TCB) of every task to hold the ID of the parent thread. Default: + disabled. + config JULIAN_TIME bool "Enables Julian time conversions" default n @@ -127,6 +137,7 @@ config SDCLONE_DISABLE config SCHED_WORKQUEUE bool "Enable worker thread" default n + depends on !DISABLE_SIGNALS ---help--- Create a dedicated "worker" thread to handle delayed processing from interrupt handlers. This feature is required for some drivers but, if there are no @@ -158,14 +169,6 @@ config SCHED_WORKSTACKSIZE ---help--- The stack size allocated for the worker thread. Default: 2K. -config SIG_SIGWORK - int "Worker thread wakeup signal" - default 4 - depends on SCHED_WORKQUEUE - ---help--- - The signal number that will be used to wake-up the worker thread. - Default: 4 - config SCHED_LPWORK bool "Enable a lower priority worker thread" default n @@ -310,6 +313,56 @@ config DISABLE_POLL depends on DISABLE_OS_API default n +if !DISABLE_SIGNALS +comment "Signal Numbers" + +config SIG_SIGUSR1 + int "SIGUSR1" + default 1 + ---help--- + Value of standard user signal 1 (SIGUSR1). Default: 1 + +config SIG_SIGUSR2 + int "SIGUSR2" + default 2 + ---help--- + Value of standard user signal 2 (SIGUSR2). Default: 2 + +config SIG_SIGALARM + int "SIGALRM" + default 3 + ---help--- + Default the signal number used with POSIX timers (SIGALRM). + Default: 3 + +config SIG_SIGCHLD + int "SIGCHLD" + default 4 + depends on SCHED_HAVE_PARENT + ---help--- + The SIGCHLD signal is sent to the parent of a child process when it + exits, is interrupted (stopped), or resumes after being interrupted. + Default: 4 + +config SIG_SIGCONDTIMEDOUT + int "SIGCONDTIMEDOUT" + default 16 + depends on !DISABLE_PTHREAD + ---help--- + This non-standard signal number is used the implementation of + pthread_cond_timedwait(). Default 16. + +config SIG_SIGWORK + int "SIGWORK" + default 17 + depends on SCHED_WORKQUEUE + ---help--- + SIGWORK is a non-standard signal used to wake up the internal NuttX + worker thread. This setting specifies the signal number that will be + used for SIGWORK. Default: 17 + +endif + comment "Sizes of configurable things (0 disables)" config MAX_TASKS diff --git a/nuttx/sched/sched_unlock.c b/nuttx/sched/sched_unlock.c index 9a52e8358..5eafcfc9e 100644 --- a/nuttx/sched/sched_unlock.c +++ b/nuttx/sched/sched_unlock.c @@ -126,5 +126,6 @@ int sched_unlock(void) irqrestore(flags); } + return OK; } diff --git a/nuttx/sched/sig_kill.c b/nuttx/sched/sig_kill.c index 17921015f..b3d74d8a1 100644 --- a/nuttx/sched/sig_kill.c +++ b/nuttx/sched/sig_kill.c @@ -84,6 +84,9 @@ int kill(pid_t pid, int signo) { +#ifdef CONFIG_SCHED_HAVE_PARENT + FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; +#endif FAR _TCB *stcb; siginfo_t info; int ret = ERROR; @@ -124,6 +127,10 @@ int kill(pid_t pid, int signo) info.si_signo = signo; info.si_code = SI_USER; info.si_value.sival_ptr = NULL; +#ifdef CONFIG_SCHED_HAVE_PARENT + info.si_pid = rtcb->pid; + info.si_status = OK; +#endif /* Send the signal */ diff --git a/nuttx/sched/sig_mqnotempty.c b/nuttx/sched/sig_mqnotempty.c index 9a1fd7243..f7ae6fd0d 100644 --- a/nuttx/sched/sig_mqnotempty.c +++ b/nuttx/sched/sig_mqnotempty.c @@ -88,6 +88,9 @@ int sig_mqnotempty (int pid, int signo, union sigval value) int sig_mqnotempty (int pid, int signo, void *sival_ptr) #endif { +#ifdef CONFIG_SCHED_HAVE_PARENT + FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; +#endif FAR _TCB *stcb; siginfo_t info; int ret = ERROR; @@ -113,6 +116,10 @@ int sig_mqnotempty (int pid, int signo, void *sival_ptr) #else info.si_value.sival_ptr = sival_ptr; #endif +#ifdef CONFIG_SCHED_HAVE_PARENT + info.si_pid = rtcb->pid; + info.si_status = OK; +#endif /* Verify that we can perform the signalling operation */ diff --git a/nuttx/sched/sig_queue.c b/nuttx/sched/sig_queue.c index dee1c798a..db404238e 100644 --- a/nuttx/sched/sig_queue.c +++ b/nuttx/sched/sig_queue.c @@ -111,6 +111,9 @@ int sigqueue (int pid, int signo, union sigval value) int sigqueue(int pid, int signo, void *sival_ptr) #endif { +#ifdef CONFIG_SCHED_HAVE_PARENT + FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; +#endif FAR _TCB *stcb; siginfo_t info; int ret = ERROR; @@ -142,13 +145,17 @@ int sigqueue(int pid, int signo, void *sival_ptr) /* Create the siginfo structure */ - info.si_signo = signo; - info.si_code = SI_QUEUE; + info.si_signo = signo; + info.si_code = SI_QUEUE; #ifdef CONFIG_CAN_PASS_STRUCTS - info.si_value = value; + info.si_value = value; #else info.si_value.sival_ptr = sival_ptr; #endif +#ifdef CONFIG_SCHED_HAVE_PARENT + info.si_pid = rtcb->pid; + info.si_status = OK; +#endif /* Send the signal */ diff --git a/nuttx/sched/sig_timedwait.c b/nuttx/sched/sig_timedwait.c index d7610cd49..b07b8f2a1 100644 --- a/nuttx/sched/sig_timedwait.c +++ b/nuttx/sched/sig_timedwait.c @@ -120,6 +120,10 @@ static void sig_timeout(int argc, uint32_t itcb) u.wtcb->sigunbinfo.si_signo = SIG_WAIT_TIMEOUT; u.wtcb->sigunbinfo.si_code = SI_TIMER; u.wtcb->sigunbinfo.si_value.sival_int = 0; +#ifdef CONFIG_SCHED_HAVE_PARENT + u.wtcb->sigunbinfo.si_pid = 0; /* Not applicable */ + u.wtcb->sigunbinfo.si_status = OK; +#endif up_unblock_task(u.wtcb); } } diff --git a/nuttx/sched/task_deletecurrent.c b/nuttx/sched/task_deletecurrent.c index 77025f5e0..7ecfb26cc 100644 --- a/nuttx/sched/task_deletecurrent.c +++ b/nuttx/sched/task_deletecurrent.c @@ -90,6 +90,9 @@ * Return Value: * OK on success; or ERROR on failure * + * Assumeptions: + * Interrupts are disabled. + * ****************************************************************************/ int task_deletecurrent(void) @@ -108,7 +111,7 @@ int task_deletecurrent(void) (void)sched_removereadytorun(dtcb); rtcb = (FAR _TCB*)g_readytorun.head; - /* We are not in a bad state -- the head of the ready to run task list + /* We are now in a bad state -- the head of the ready to run task list * does not correspond to the thread that is running. Disabling pre- * emption on this TCB and marking the new ready-to-run task as not * running (see, for example, get_errno_ptr()). @@ -132,9 +135,16 @@ int task_deletecurrent(void) (void)sched_mergepending(); } - /* Now calling sched_unlock() should have no effect */ + /* We can't use sched_unlock() to decrement the lock count because the + * sched_mergepending() call above might have changed the task at the + * head of the ready-to-run list. Furthermore, we should not need to + * perform the unlock action anyway because we know that the pending + * task list is empty. So all we really need to do is to decrement + * the lockcount on rctb. + */ - sched_unlock(); + DEBUGASSERT(rtcb->lockcount > 0); + rtcb->lockcount--; return OK; } diff --git a/nuttx/sched/task_exithook.c b/nuttx/sched/task_exithook.c index 3bde8fb7a..9ce2e5899 100644 --- a/nuttx/sched/task_exithook.c +++ b/nuttx/sched/task_exithook.c @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -187,6 +188,56 @@ static inline void task_onexit(FAR _TCB *tcb, int status) # define task_onexit(tcb,status) #endif +/**************************************************************************** + * Name: task_sigchild + * + * Description: + * Send the SIGCHILD signal to the parent thread + * + ****************************************************************************/ + +#ifdef CONFIG_SCHED_HAVE_PARENT +static inline void task_sigchild(FAR _TCB *tcb, int status) +{ + FAR _TCB *ptcb; + siginfo_t info; + + /* Keep things stationary through the following */ + + sched_lock(); + + /* Get the TCB of the receiving task */ + + ptcb = sched_gettcb(tcb->parent); + if (!ptcb) + { + /* The parent no longer exists... bail */ + + sched_unlock(); + return; + } + + /* Create the siginfo structure. We don't actually know the cause. That + * is a bug. Let's just say that the child task just exit-ted for now. + */ + + info.si_signo = SIGCHLD; + info.si_code = CLD_EXITED; + info.si_value.sival_ptr = NULL; + info.si_pid = tcb->pid; + info.si_status = status; + + /* Send the signal. We need to use this internal interface so that we can + * provide the correct si_code value with the signal. + */ + + (void)sig_received(ptcb, &info); + sched_unlock(); +} +#else +# define task_sigchild(tcb,status) +#endif + /**************************************************************************** * Name: task_exitwakeup * @@ -259,6 +310,10 @@ void task_exithook(FAR _TCB *tcb, int status) task_atexit(tcb); + /* Send SIGCHLD to the parent of the exiting task */ + + task_sigchild(tcb, status); + /* Call any registered on_exit function(s) */ task_onexit(tcb, status); diff --git a/nuttx/sched/task_setup.c b/nuttx/sched/task_setup.c index 8721b39ec..c5dd8ca3a 100644 --- a/nuttx/sched/task_setup.c +++ b/nuttx/sched/task_setup.c @@ -146,6 +146,34 @@ static int task_assignpid(FAR _TCB *tcb) return ERROR; } +/**************************************************************************** + * Name: task_saveparent + * + * Description: + * Save the task ID of the parent task in the child task's TCB. + * + * Parameters: + * tcb - The TCB of the new, child task. + * + * Returned Value: + * None + * + * Assumptions: + * The parent of the new task is the task at the head of the ready-to-run + * list. + * + ****************************************************************************/ + +#ifdef CONFIG_SCHED_HAVE_PARENT +static inline void task_saveparent(FAR _TCB *tcb) +{ + FAR _TCB *rtcb = (FAR _TCB*)g_readytorun.head; + tcb->parent = rtcb->pid; +} +#else +# define task_saveparent(tcb) +#endif + /**************************************************************************** * Name: task_dupdspace * @@ -161,6 +189,8 @@ static int task_assignpid(FAR _TCB *tcb) * None * * Assumptions: + * The parent of the new task is the task at the head of the ready-to-run + * list. * ****************************************************************************/ @@ -231,6 +261,10 @@ int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main) tcb->start = start; tcb->entry.main = main; + /* Save the task ID of the parent task in the TCB */ + + task_saveparent(tcb); + /* exec(), pthread_create(), task_create(), and vfork() all * inherit the signal mask of the parent thread. */ @@ -243,7 +277,7 @@ int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main) * until it is activated. */ - tcb->task_state = TSTATE_TASK_INVALID; + tcb->task_state = TSTATE_TASK_INVALID; /* Clone the parent tasks D-Space (if it was running PIC). This * must be done before calling up_initial_state() so that the diff --git a/nuttx/sched/timer_settime.c b/nuttx/sched/timer_settime.c index 1814ba898..f09842ad4 100644 --- a/nuttx/sched/timer_settime.c +++ b/nuttx/sched/timer_settime.c @@ -113,6 +113,10 @@ static void inline timer_sigqueue(FAR struct posix_timer_s *timer) #else info.si_value.sival_ptr = timer->pt_value.sival_ptr; #endif +#ifdef CONFIG_SCHED_HAVE_PARENT + info.si_pid = 0; /* Not applicable */ + info.si_status = OK; +#endif /* Send the signal */ -- cgit v1.2.3 From ffda55b34a9a8a4a84f4cbc1da3836b944baec46 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 13 Jan 2013 00:35:47 +0000 Subject: Cosmetic cleanup from SIGCHLD changes git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5514 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/ostest/sighand.c | 7 ++++++- nuttx/ChangeLog | 2 +- nuttx/sched/task_deletecurrent.c | 6 ++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/apps/examples/ostest/sighand.c b/apps/examples/ostest/sighand.c index 63d9590d9..32b182c21 100644 --- a/apps/examples/ostest/sighand.c +++ b/apps/examples/ostest/sighand.c @@ -57,7 +57,12 @@ static bool threadexited = false; #ifdef CONFIG_SCHED_HAVE_PARENT static void death_of_child(int signo, siginfo_t *info, void *ucontext) { - /* Use of printf in a signal handler is NOT safe! It can cause deadlocks! */ + /* Use of printf in a signal handler is NOT safe! It can cause deadlocks! + * Also, signals are not queued by NuttX. As a consequence, some + * notifications will get lost (or the info data can be overwrittedn)! + * Because POSIX does not require signals to be queued, I do not think + * that this is a bug (the overwriting is a bug, however). + */ if (info) { diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 921b7014b..7deb9fa94 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3918,7 +3918,7 @@ the scenario: (1) sched_lock() is called increments the lockcount on the current TCB (i.e., the one at the head of the ready to run list), (2) sched_mergepending is called which may change the task - at the head of the readytorun list, then (2) sched_lock() is called + at the head of the readytorun list, then (2) sched_unlock() is called which decrements the lockcount on the wrong TCB. The failure case that I saw was that pre-emption got disabled in the IDLE thread, locking up the whole system. diff --git a/nuttx/sched/task_deletecurrent.c b/nuttx/sched/task_deletecurrent.c index 7ecfb26cc..e1e06acf6 100644 --- a/nuttx/sched/task_deletecurrent.c +++ b/nuttx/sched/task_deletecurrent.c @@ -115,9 +115,12 @@ int task_deletecurrent(void) * does not correspond to the thread that is running. Disabling pre- * emption on this TCB and marking the new ready-to-run task as not * running (see, for example, get_errno_ptr()). + * + * We disable pre-emption here by directly incrementing the lockcount + * (vs. calling sched_lock()). */ - sched_lock(); + rtcb->lockcount++; rtcb->task_state = TSTATE_TASK_READYTORUN; /* Move the TCB to the specified blocked task list and delete it */ @@ -143,7 +146,6 @@ int task_deletecurrent(void) * the lockcount on rctb. */ - DEBUGASSERT(rtcb->lockcount > 0); rtcb->lockcount--; return OK; } -- cgit v1.2.3 From b3f3dd123c181fe851f0a9756bed7acd4ba4ef7d Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 13 Jan 2013 18:53:00 +0000 Subject: Use SIGCHLD with waitpid(); implemented wait() and waitid() git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5515 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 3 +- apps/examples/ostest/Makefile | 4 + apps/examples/ostest/ostest.h | 42 +++-- apps/examples/ostest/ostest_main.c | 8 + apps/examples/ostest/waitpid.c | 269 +++++++++++++++++++++++++++++ nuttx/ChangeLog | 7 + nuttx/Documentation/NuttX.html | 8 +- nuttx/Documentation/NuttxPortingGuide.html | 10 +- nuttx/Documentation/NuttxUserGuide.html | 181 +++++++++++++++++-- nuttx/TODO | 13 +- nuttx/configs/README.txt | 16 +- nuttx/configs/sim/ostest/defconfig | 2 +- nuttx/include/nuttx/sched.h | 5 +- nuttx/include/sys/types.h | 4 +- nuttx/include/sys/wait.h | 10 +- nuttx/sched/Kconfig | 14 +- nuttx/sched/Makefile | 5 +- nuttx/sched/os_internal.h | 6 +- nuttx/sched/sched_wait.c | 90 ++++++++++ nuttx/sched/sched_waitid.c | 256 +++++++++++++++++++++++++++ nuttx/sched/sched_waitpid.c | 192 ++++++++++++++++++-- nuttx/sched/task_exithook.c | 24 ++- nuttx/sched/task_setup.c | 3 + 23 files changed, 1078 insertions(+), 94 deletions(-) create mode 100644 apps/examples/ostest/waitpid.c create mode 100644 nuttx/sched/sched_wait.c create mode 100644 nuttx/sched/sched_waitid.c diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 65d4d6134..70381a79d 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -464,4 +464,5 @@ * apps/exampes/posix_spawn: Added a test of poxis_spawn(). * apps/examples/ostest: Extend signal handler test to catch death-of-child signals (SIGCHLD). - + * apps/examples/ostest/waitpid.c: Add a test for waitpid(), waitid(), + and wait(). diff --git a/apps/examples/ostest/Makefile b/apps/examples/ostest/Makefile index b7ba9a9a8..5a8ff7293 100644 --- a/apps/examples/ostest/Makefile +++ b/apps/examples/ostest/Makefile @@ -52,6 +52,10 @@ ifeq ($(CONFIG_ARCH_FPU),y) CSRCS += fpu.c endif +ifeq ($(CONFIG_SCHED_WAITPID),y) +CSRCS += waitpid.c +endif + ifneq ($(CONFIG_DISABLE_PTHREAD),y) CSRCS += cancel.c cond.c mutex.c sem.c barrier.c ifneq ($(CONFIG_RR_INTERVAL),0) diff --git a/apps/examples/ostest/ostest.h b/apps/examples/ostest/ostest.h index bc46a3860..5217f0a0c 100644 --- a/apps/examples/ostest/ostest.h +++ b/apps/examples/ostest/ostest.h @@ -105,68 +105,74 @@ /* dev_null.c ***************************************************************/ -extern int dev_null(void); +int dev_null(void); /* fpu.c ********************************************************************/ -extern void fpu_test(void); +void fpu_test(void); + +/* waitpid.c ****************************************************************/ + +#ifdef CONFIG_SCHED_WAITPID +int waitpid_test(void); +#endif /* mutex.c ******************************************************************/ -extern void mutex_test(void); +void mutex_test(void); /* rmutex.c ******************************************************************/ -extern void recursive_mutex_test(void); +void recursive_mutex_test(void); /* sem.c ********************************************************************/ -extern void sem_test(void); +void sem_test(void); /* cond.c *******************************************************************/ -extern void cond_test(void); +void cond_test(void); /* mqueue.c *****************************************************************/ -extern void mqueue_test(void); +void mqueue_test(void); /* timedmqueue.c ************************************************************/ -extern void timedmqueue_test(void); +void timedmqueue_test(void); /* cancel.c *****************************************************************/ -extern void cancel_test(void); +void cancel_test(void); /* timedwait.c **************************************************************/ -extern void timedwait_test(void); +void timedwait_test(void); /* sighand.c ****************************************************************/ -extern void sighand_test(void); +void sighand_test(void); /* posixtimers.c ************************************************************/ -extern void timer_test(void); +void timer_test(void); /* roundrobin.c *************************************************************/ -extern void rr_test(void); +void rr_test(void); /* barrier.c ****************************************************************/ -extern void barrier_test(void); +void barrier_test(void); /* prioinherit.c ************************************************************/ -extern void priority_inheritance(void); +void priority_inheritance(void); /* vfork.c ******************************************************************/ #ifdef CONFIG_ARCH_HAVE_VFORK -extern int vfork_test(void); +int vfork_test(void); #endif /* APIs exported (conditionally) by the OS specifically for testing of @@ -174,8 +180,8 @@ extern int vfork_test(void); */ #if defined(CONFIG_DEBUG) && defined(CONFIG_PRIORITY_INHERITANCE) && defined(CONFIG_SEM_PHDEBUG) -extern void sem_enumholders(FAR sem_t *sem); -extern int sem_nfreeholders(void); +void sem_enumholders(FAR sem_t *sem); +int sem_nfreeholders(void); #else # define sem_enumholders(sem) # define sem_nfreeholders() diff --git a/apps/examples/ostest/ostest_main.c b/apps/examples/ostest/ostest_main.c index ca44353c3..aab1ff045 100644 --- a/apps/examples/ostest/ostest_main.c +++ b/apps/examples/ostest/ostest_main.c @@ -301,6 +301,14 @@ static int user_main(int argc, char *argv[]) check_test_memory_usage(); #endif +#ifdef CONFIG_SCHED_WAITPID + /* Check waitpid() and friends */ + + printf("\nuser_main: waitpid test\n"); + waitpid_test(); + check_test_memory_usage(); +#endif + #ifndef CONFIG_DISABLE_PTHREAD /* Verify pthreads and pthread mutex */ diff --git a/apps/examples/ostest/waitpid.c b/apps/examples/ostest/waitpid.c new file mode 100644 index 000000000..e53b49213 --- /dev/null +++ b/apps/examples/ostest/waitpid.c @@ -0,0 +1,269 @@ +/**************************************************************************** + * examples/ostest/waitpid.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "ostest.h" + +#ifdef CONFIG_SCHED_WAITPID + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RETURN_STATUS 14 +#define NCHILDREN 3 +#define PRIORITY 100 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static int g_waitpids[NCHILDREN]; + +/**************************************************************************** + * Priviate Functions + ****************************************************************************/ + +static int waitpid_main(int argc, char *argv[]) +{ + pid_t me = getpid(); + + printf("waitpid_main: PID %d Started\n", me); + sleep(3); + printf("waitpid_main: PID %d exitting with result=%d\n", me, RETURN_STATUS); + return RETURN_STATUS; +} + +static void waitpid_start_children(void) +{ + int ret; + int i; + + for (i = 0; i < NCHILDREN; i++) + { + ret = TASK_CREATE("waitpid", PRIORITY, STACKSIZE, waitpid_main, NULL); + if (ret < 0) + { + printf("waitpid_start_child: ERROR Failed to start user_main\n"); + } + else + { + printf("waitpid_start_child: Started waitpid_main at PID=%d\n", ret); + } + + g_waitpids[i] = ret; + } +} + +static void waitpid_last(void) +{ + int stat_loc; + int ret; + + printf("waitpid_last: Waiting for PID=%d with waitpid()\n", + g_waitpids[NCHILDREN-1]); + + ret = (int)waitpid(g_waitpids[NCHILDREN-1], &stat_loc, 0); + if (ret < 0) + { + int errcode = errno; + printf("waitpid_last: ERROR: PID %d waitpid failed: %d\n", + g_waitpids[NCHILDREN-1], errcode); + } + else if (stat_loc != RETURN_STATUS) + { + printf("waitpid_last: ERROR: PID %d return status is %d, expected %d\n", + g_waitpids[NCHILDREN-1], stat_loc, RETURN_STATUS); + } + else + { + printf("waitpid_last: PID %d waitpid succeeded with stat_loc=%d\n", + g_waitpids[NCHILDREN-1], stat_loc); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int waitpid_test(void) +{ +#ifdef CONFIG_SCHED_HAVE_PARENT + siginfo_t info; +#endif + int stat_loc; + int ret; + + /* Start the children and wait for first one to complete */ + + printf("\nTest waitpid()\n"); + waitpid_start_children(); + + printf("waitpid_test: Waiting for PID=%d with waitpid()\n", g_waitpids[0]); + ret = (int)waitpid(g_waitpids[0], &stat_loc, 0); + if (ret < 0) + { + int errcode = errno; + printf("waitpid_test: ERROR: PID %d waitpid failed: %d\n", + g_waitpids[0], errcode); + } + else if (ret != g_waitpids[0]) + { + printf("waitpid_test: ERROR: PID %d wait returned PID %d\n", + g_waitpids[0], ret); + } + else if (stat_loc != RETURN_STATUS) + { + printf("waitpid_test: ERROR: PID %d return status is %d, expected %d\n", + g_waitpids[0], stat_loc, RETURN_STATUS); + } + else + { + printf("waitpid_test: PID %d waitpid succeeded with stat_loc=%d\n", + g_waitpids[0], stat_loc); + } + + /* Wait a big to make sure that the other threads complete */ + + waitpid_last(); + sleep(1); + +#ifdef CONFIG_SCHED_HAVE_PARENT + /* Start the children and wait for first one to complete */ + + printf("\nTest waitid(P_PID)\n"); + waitpid_start_children(); + + printf("waitpid_test: Waiting for PID=%d with waitid()\n", g_waitpids[0]); + ret = waitid(P_PID, (id_t)g_waitpids[0], &info, WEXITED); + if (ret < 0) + { + int errcode = errno; + printf("waitpid_test: ERROR: PID %d waitid failed: %d\n", + g_waitpids[0], errcode); + } + else if (info.si_pid != g_waitpids[0]) + { + printf("waitpid_test: ERROR: PID %d waitid returned PID %d\n", + g_waitpids[0], info.si_pid); + } + else if (info.si_status != RETURN_STATUS) + { + printf("waitpid_test: ERROR: PID %d return status is %d, expected %d\n", + info.si_pid, info.si_status, RETURN_STATUS); + } + else + { + printf("waitpid_test: waitid PID %d succeeded with si_status=%d\n", + info.si_pid, info.si_status); + } + + /* Wait a big to make sure that the other threads complete */ + + waitpid_last(); + sleep(1); + + /* Start the children and wait for any one to complete */ + + printf("\nTest waitid(P_ALL)\n"); + waitpid_start_children(); + + printf("waitpid_test: Waiting for any child with waitid()\n"); + ret = waitid(P_ALL, 0, &info, WEXITED); + if (ret < 0) + { + int errcode = errno; + printf("waitpid_test: ERROR: waitid failed: %d\n", errcode); + } + else if (info.si_status != RETURN_STATUS) + { + printf("waitpid_test: ERROR: PID %d return status is %d, expected %d\n", + info.si_pid, info.si_status, RETURN_STATUS); + } + else + { + printf("waitpid_test: PID %d waitid succeeded with si_status=%d\n", + info.si_pid, info.si_status); + } + + /* Wait a big to make sure that the other threads complete */ + + waitpid_last(); + sleep(1); + + /* Start the children and wait for first one to complete */ + + printf("\nTest wait()\n"); + waitpid_start_children(); + + printf("waitpid_test: Waiting for any child with wait()\n"); + ret = (int)wait(&stat_loc); + if (ret < 0) + { + int errcode = errno; + printf("waitpid_test: ERROR: wait failed: %d\n", errcode); + } + else if (stat_loc != RETURN_STATUS) + { + printf("waitpid_test: ERROR: PID %d return status is %d, expected %d\n", + ret, stat_loc, RETURN_STATUS); + } + else + { + printf("waitpid_test: PID %d wait succeeded with stat_loc=%d\n", + ret, stat_loc); + } + + /* Wait a big to make sure that the other threads complete */ + + waitpid_last(); + sleep(1); +#endif + + return 0; +} + +#endif /* CONFIG_SCHED_WAITPID */ diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7deb9fa94..e8d4f7309 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3922,3 +3922,10 @@ which decrements the lockcount on the wrong TCB. The failure case that I saw was that pre-emption got disabled in the IDLE thread, locking up the whole system. + * sched/sched_waitpid.c: Use SIGCHLD instead of a semaphore. This + is a much more spec-compliant implemenation. However, there are + some issues with overruning signals because NuttX does not support + queueing of signals (POSIX does not require it). I think it may + need to. + * sched/sched_waitid.c and sched_wait.c: Add support for waitid() + and wait(). See issues with waitpid() above. diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index f6e9a41ba..22651de79 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -286,7 +286,7 @@

        • Easily extensible to new processor architectures, SoC architecture, or board architectures. - A Porting Guide is available. + A Porting Guide is available.


          • -

        • Power management sub-system.
          • +
        • Power management sub-system.

          		•
          Porting GuidePorting Guide
          @@ -4482,7 +4482,8 @@ build
        • CONFIG_SCHED_HAVE_PARENT: Remember the ID of the parent thread when a new child thread is created. - This support enables a few minor features (such as SIGCHLD) and slightly increases the size of the Task Control Block (TCB) of every task to hold the ID of the parent thread. + This support enables some additional features (such as SIGCHLD) and modifies the behavior of other interfaces. + For example, it makes waitpid() more standards complete by restricting the waited-for tasks to the children of the caller. Default: disabled.
        • @@ -4601,10 +4602,11 @@ build CONFIG_SCHED_LPWORKPERIOD: How often the lower priority worker thread checks for work in units of microseconds. Default: 50*1000 (50 MS).
        • - CONFIG_SCHED_LPWORKSTACKSIZE - The stack size allocated for the lower priority worker thread. Default: CONFIG_IDLETHREAD_STACKSIZE. + CONFIG_SCHED_LPWORKSTACKSIZE: The stack size allocated for the lower priority worker thread. Default: CONFIG_IDLETHREAD_STACKSIZE.
        • - CONFIG_SCHED_WAITPID: Enables the waitpid() API + CONFIG_SCHED_WAITPID: Enables the waitpid() interface in a default, non-standard mode (non-standard in the sense that the waited for PID need not be child of the caller). + If SCHED_HAVE_PARENT is also defined, then this setting will modify the behavior or waitpid() (making more spec compliant) and will enable the waitid() and waitp() interfaces as well.
        • CONFIG_SCHED_ATEXIT: Enables the atexit() API diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index c6eabd29a..3cfb63f11 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

          NuttX Operating System

          User's Manual

          by

          Gregory Nutt

          -

          Last Updated: January 11, 2013

          +

          Last Updated: January 13, 2013

          @@ -1776,8 +1776,10 @@ priority of the calling task is returned.

          Task synchronization interfaces

          2.3.1 sched_lock

          @@ -1886,10 +1888,12 @@ on this thread of execution. Description:

          - The following discussion is a general description of the waitpid() interface. - However, as of this writing, the implementation of waitpid() is fragmentary (but usable). - It simply supports waiting for any task to complete execution. - NuttX does not support any concept of parent/child processes or of process groups nor signals related to child processes (SIGCHLD). + The following discussion is a general description of the waitpid() interface. + However, as of this writing, the implementation of waitpid() is incomplete (but usable). + If CONFIG_SCHED_HAVE_PARENT is defined, waitpid() will be a little more compliant to specifications. + Without CONFIG_SCHED_HAVE_PARENT, waitpid() simply supports waiting for any task to complete execution. + With CONFIG_SCHED_HAVE_PARENT, waitpid() will use SIGCHLD and can, therefore, wait for any child of the parent to complete. + The implementation is incomplete in either case, however: NuttX does not support any concept of process groups. Nor does NuttX retain the status of exited tasks so if waitpid() is called after a task has exited, then no status will be available. The options argument is currently ignored.
          @@ -2038,7 +2042,158 @@ on this thread of execution. Comparable to the POSIX interface of the same name, but the implementation is incomplete (as detailed above).

          -

          2.3.5 atexit

          +

          2.3.5 waitid

          • +

          +Function Prototype: +

          +    #include <sys/wait.h>
+    #ifdef CONFIG_SCHED_HAVE_PARENT
+    int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options);
+    #endif
+
          +

          + Description: +

          +
          + The following discussion is a general description of the waitid() interface. + However, as of this writing, the implementation of waitid() is incomplete (but usable). + If CONFIG_SCHED_HAVE_PARENT is defined, waitid() will be a little more compliant to specifications. + waitpid() simply supports waiting a specific child task (P_PID or for any child task P_ALL to complete execution. + SIGCHLD is used. + The implementation is incomplete in either case, however: NuttX does not support any concept of process groups. + Nor does NuttX retain the status of exited tasks so if waitpid() is called after a task has exited, then no status will be available. + The options argument is currently ignored. +
          +

          + The waitid() function suspends the calling thread until one child of the process containing the calling thread changes state. + It records the current state of a child in the structure pointed to by info. + If a child process changed state prior to the call to waitid(), waitid() returns immediately. + If more than one thread is suspended in wait() or waitpid() waiting termination of the same process, exactly one thread will return the process status at the time of the target process termination +

          +

          + The idtype and id arguments are used to specify which children waitid() will wait for. +

          +

          +

            +
          • + If idtype is P_PID, waitid() will wait for the child with a process ID equal to (pid_t)id. +
            • +
          • + If idtype is P_PGID, waitid() will wait for any child with a process group ID equal to (pid_t)id. +
            • +
          • + If idtype is P_ALL, waitid() will wait for any children and id is ignored. +
          +

          + The options argument is used to specify which state changes waitid() will will wait for. + It is formed by OR-ing together one or more of the following flags: +

          +
            +
          • + WEXITED: + Wait for processes that have exited. +
            • +
          • + WSTOPPED: + Status will be returned for any child that has stopped upon receipt of a signal. +
            • +
          • + WCONTINUES: + Status will be returned for any child that was stopped and has been continued. +
            • +
          • + WNOHANG: + Return immediately if there are no children to wait for. +
            • +
          • + WNOWAIT: + Keep the process whose status is returned in info in a waitable state. + This will not affect the state of the process; + the process may be waited for again after this call completes. +
            • +
          + The info argument must point to a siginfo_t structure. + If waitid() returns because a child process was found that satisfied the conditions indicated by the arguments idtype and options, then the structure pointed to by info will be filled in by the system with the status of the process. + The si_signo member will always be equal to SIGCHLD. +

          +

          + Input Parameters: + See the description above. +

          +

          + Returned Value: + If waitid() returns due to the change of state of one of its children, 0 is returned. + Otherwise, -1 is returned and errno is set to indicate the error. +

          +

          + The waitid() function will fail if: +

          +
            +
          • + ECHILD: +
            • + The calling process has no existing unwaited-for child processes. +
          • + EINTR: +
            • + The waitid() function was interrupted by a signal. +
          • + EINVAL: + An invalid value was specified for options, or idtype and id specify an invalid set of processes. +
            • +
          +

          + Assumptions/Limitations: +

          + POSIX Compatibility: + Comparable to the POSIX interface of the same name, but the implementation is incomplete (as detailed in the description above). +

          + +

          2.3.6 wait

          +

          +Function Prototype: +

          +    #include <sys/wait.h>
+    #ifdef CONFIG_SCHED_HAVE_PARENT
+    pid_t wait(FAR int *stat_loc);
+    #endif
+
          +

          + Description: +

          +
          + The following discussion is a general description of the wait() interface. + However, as of this writing, the implementation of wait() is incomplete (but usable). + wait() is based on waitpaid(). + See the description of waitpaid() for further information. +
          +

          + The wait() function will suspend execution of the calling thread until status information for one of its terminated child processes is available, or until delivery of a signal whose action is either to execute a signal-catching function or to terminate the process. + If more than one thread is suspended in wait() awaiting termination of the same process, exactly one thread will return the process status at the time of the target process termination. + If status information is available prior to the call towait(), return will be immediate. +

          +

          + The waitpid() function will behave identically to wait(), if its pid argument is (pid_t)-1 and the options argument is 0. + Otherwise, its behavior will be modified by the values of the pid and options arguments. +

          +

          + Input Parameters: +

          +
            +
          • stat_loc. The location to return the exit status
            • +
          +

          + Returned Value: + See the values returned by waitpaid(). +

          +

          + Assumptions/Limitations: +

          + POSIX Compatibility: + Comparable to the POSIX interface of the same name, but the implementation is incomplete (as detailed in the description waitpaid()). +

          + +

          2.3.7 atexit

          Function Prototype: @@ -2077,7 +2232,7 @@ on this thread of execution.

        • atexit() functions are not inherited when a new task is created.
          • -

          2.3.6 on_exit

          +

          2.3.8 on_exit

          Function Prototype: @@ -9023,9 +9178,9 @@ notify a task when a message is available on a queue.

        • pipe
        • poll
        • poll.h
          • +
        • posix_spawn
          • -
        • posix_spawn
        • posix_spawn_file_actions_addclose
        • posix_spawn_file_actions_adddup2
        • posix_spawn_file_actions_addopen
          • @@ -9107,10 +9262,10 @@ notify a task when a message is available on a queue.
        • recv
        • recvfrom
        • rename
          • - -
        • rmdir
        • rewinddir
          • + +
        • ROM disk driver
        • ROMFS
        • sched_getparam
          • @@ -9183,6 +9338,8 @@ notify a task when a message is available on a queue.
        • vfprintf
        • vprintf
        • vsprintf
          • +
        • wait
          • +
        • waitid
        • waitpid
        • Watchdog Timer Interfaces
        • wd_cancel
          • diff --git a/nuttx/TODO b/nuttx/TODO index 92b7ab4f5..88324c06b 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (11) Task/Scheduler (sched/) + (10) Task/Scheduler (sched/) (1) Memory Managment (mm/) (2) Signals (sched/, arch/) (2) pthreads (sched/) @@ -58,17 +58,6 @@ o Task/Scheduler (sched/) Status: Closed. No, this behavior will not be implemented. Priority: Medium, required for good emulation of process/pthread model. - Title: WAIT.H - Description: Implement sys/wait.h and functions. Consider implementing wait, - waitpid, waitid. At present, a parent has no information about - child tasks. - - Update: A simple but usable version of waitpid() has been included. - This version is not compliant with all specifications and can be - enabled with CONFIG_SCHED_WAITPID. - Status: Open, however no further work is planned. - Priority: Low - Title: MISSING ERRNO SETTINGS Description: Several APIs do not set errno. Need to review all APIs. Update: These are being fixed as they are encountered. There is diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 2724cf5a3..4800f02ee 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -335,10 +335,11 @@ defconfig -- This is a configuration file similar to the Linux task name to save in the TCB. Useful if scheduler instrumentation is selected. Set to zero to disable. CONFIG_SCHED_HAVE_PARENT - Remember the ID of the parent thread - when a new child thread is created. This support enables a - few minor features (such as SIGCHLD) and slightly increases - the size of the Task Control Block (TCB) of every task to hold - the ID of the parent thread. Default: disabled. + when a new child thread is created. This support enables some + additional features (such as SIGCHLD) and modifies the behavior + of other interfaces. For example, it makes waitpid() more + standards complete by restricting the waited-for tasks to the + children of the caller. Default: disabled. CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - Used to initialize the internal time logic. CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. @@ -417,7 +418,12 @@ defconfig -- This is a configuration file similar to the Linux checks for work in units of microseconds. Default: 50*1000 (50 MS). CONFIG_SCHED_LPWORKSTACKSIZE - The stack size allocated for the lower priority worker thread. Default: CONFIG_IDLETHREAD_STACKSIZE. - CONFIG_SCHED_WAITPID - Enables the waitpid() API + CONFIG_SCHED_WAITPID - Enables the waitpid() interface in a default, + non-standard mode (non-standard in the sense that the waited for + PID need not be child of the caller). If SCHED_HAVE_PARENT is + also defined, then this setting will modify the behavior or + waitpid() (making more spec compliant) and will enable the + waitid() and wait() interfaces as well. CONFIG_SCHED_ATEXIT - Enables the atexit() API CONFIG_SCHED_ATEXIT_MAX - By default if CONFIG_SCHED_ATEXIT is selected, only a single atexit() function is supported. That number diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index 5cea9a6d4..c8d5c501d 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -143,7 +143,7 @@ CONFIG_MUTEX_TYPES=y # CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y # CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_WAITPID is not set +CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set CONFIG_USER_ENTRYPOINT="ostest_main" diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h index 6c67e1500..b2ec1cee4 100644 --- a/nuttx/include/nuttx/sched.h +++ b/nuttx/include/nuttx/sched.h @@ -1,7 +1,7 @@ /******************************************************************************** * include/nuttx/sched.h * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -204,6 +204,7 @@ struct _TCB pid_t pid; /* This is the ID of the thread */ #ifdef CONFIG_SCHED_HAVE_PARENT pid_t parent; /* This is the ID of the parent thread */ + uint16_t nchildren; /* This is the number active children */ #endif start_t start; /* Thread start function */ entry_t entry; /* Entry Point into the thread */ @@ -226,7 +227,7 @@ struct _TCB # endif #endif -#ifdef CONFIG_SCHED_WAITPID +#if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) sem_t exitsem; /* Support for waitpid */ int *stat_loc; /* Location to return exit status */ #endif diff --git a/nuttx/include/sys/types.h b/nuttx/include/sys/types.h index 2ae69d4a7..95feee72e 100644 --- a/nuttx/include/sys/types.h +++ b/nuttx/include/sys/types.h @@ -154,7 +154,9 @@ typedef uint16_t dev_t; typedef uint16_t ino_t; -/* pid_t is used for process IDs and process group IDs */ +/* pid_t is used for process IDs and process group IDs. It must be signed because + * negative PID values are used to represent invalid PIDs. + */ typedef int pid_t; diff --git a/nuttx/include/sys/wait.h b/nuttx/include/sys/wait.h index 6af1e971e..2476adef9 100644 --- a/nuttx/include/sys/wait.h +++ b/nuttx/include/sys/wait.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/sys/wait.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,7 +66,7 @@ #define WTERMSIG(s) (false) /* Return signal number that caused process to terminate */ /* The following symbolic constants are possible values for the options - * argument to waitpi(1) (1) and/or waitid() (2), + * argument to waitpid() (1) and/or waitid() (2), */ #define WCONTINUED (1 << 0) /* Status for child that has been continued (1)(2) */ @@ -104,9 +104,9 @@ extern "C" { #define EXTERN extern #endif -EXTERN pid_t wait(int *stat_loc); -EXTERN int waitid(idtype_t idtype, id_t id, siginfo_t *siginfo, int options); -EXTERN pid_t waitpid(pid_t pid, int *stat_loc, int options); +EXTERN pid_t wait(FAR int *stat_loc); +EXTERN int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options); +EXTERN pid_t waitpid(pid_t pid, FAR int *stat_loc, int options); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/sched/Kconfig b/nuttx/sched/Kconfig index 69621a1fa..6d53a03aa 100644 --- a/nuttx/sched/Kconfig +++ b/nuttx/sched/Kconfig @@ -43,9 +43,10 @@ config SCHED_HAVE_PARENT default n ---help--- Remember the ID of the parent thread when a new child thread is - created. This support enables a few minor features (such as - SIGCHLD) and slightly increases the size of the Task Control Block - (TCB) of every task to hold the ID of the parent thread. Default: + created. This support enables some additional features (such as + SIGCHLD) and modifies the behavior of other interfaces. For + example, it makes waitpid() more standards complete by restricting + the waited-for tasks to the children of the caller. Default: disabled. config JULIAN_TIME @@ -206,7 +207,12 @@ config SCHED_WAITPID bool "Enable waitpid() API" default n ---help--- - Enables the waitpid() API + Enables the waitpid() interface in a default, non-standard mode + (non-standard in the sense that the waited for PID need not be child + of the caller). If SCHED_HAVE_PARENT is also defined, then this + setting will modify the behavior or waitpid() (making more spec + compliant) and will enable the waitid() and wait() interfaces as + well. config SCHED_ATEXIT bool "Enable atexit() API" diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile index 23d1e9938..3d6b58bac 100644 --- a/nuttx/sched/Makefile +++ b/nuttx/sched/Makefile @@ -1,7 +1,7 @@ ############################################################################ # sched/Makefile # -# Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -69,6 +69,9 @@ endif ifeq ($(CONFIG_SCHED_WAITPID),y) SCHED_SRCS += sched_waitpid.c +ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) +SCHED_SRCS += sched_waitid.c sched_wait.c +endif endif ENV_SRCS = env_getenvironptr.c env_dup.c env_share.c env_release.c \ diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h index 13b8083cf..32d9fb4ac 100644 --- a/nuttx/sched/os_internal.h +++ b/nuttx/sched/os_internal.h @@ -83,10 +83,10 @@ enum os_crash_codes_e OSERR_BADREPRIORITIZESTATE /* Attempt to reprioritize in bad state or priority */ }; -/* Special task IDS */ +/* Special task IDS. Any negative PID is invalid. */ -#define NULL_TASK_PROCESS_ID 0 -#define INVALID_PROCESS_ID 0 +#define NULL_TASK_PROCESS_ID (pid_t)0 +#define INVALID_PROCESS_ID (pid_t)-1 /* Although task IDs can take the (positive, non-zero) * range of pid_t, the number of tasks that will be supported diff --git a/nuttx/sched/sched_wait.c b/nuttx/sched/sched_wait.c new file mode 100644 index 000000000..813d4f842 --- /dev/null +++ b/nuttx/sched/sched_wait.c @@ -0,0 +1,90 @@ +/***************************************************************************** + * sched/sched_wait.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "os_internal.h" + +#if defined(CONFIG_SCHED_WAITPID) && defined(CONFIG_SCHED_HAVE_PARENT) + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: wait + * + * Description: + * The wait() function will suspend execution of the calling thread until + * status information for one of its terminated child processes is + * available, or until delivery of a signal whose action is either to + * execute a signal-catching function or to terminate the process. If more + * than one thread is suspended in wait() or waitpid() awaiting termination + * of the same process, exactly one thread will return the process status + * at the time of the target process termination. If status information is + * available prior to the call to wait(), return will be immediate. + * + * The waitpid() function will behave identically to wait(), if the pid + * argument is (pid_t)-1 and the options argument is 0. Otherwise, its + * behaviour will be modified by the values of the pid and options arguments. + * + * Input Parameters: + * stat_loc - The location to return the exit status + * + * Returned Value: + * See waitpid(); + * + *****************************************************************************/ + +pid_t wait(FAR int *stat_loc) +{ + return waitpid((pid_t)-1, stat_loc, 0); +} + +#endif /* CONFIG_SCHED_WAITPID && CONFIG_SCHED_HAVE_PARENT*/ diff --git a/nuttx/sched/sched_waitid.c b/nuttx/sched/sched_waitid.c new file mode 100644 index 000000000..eabc69afe --- /dev/null +++ b/nuttx/sched/sched_waitid.c @@ -0,0 +1,256 @@ +/***************************************************************************** + * sched/sched_waitid.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "os_internal.h" + +#if defined(CONFIG_SCHED_WAITPID) && defined(CONFIG_SCHED_HAVE_PARENT) + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: waitid + * + * Description: + * The waitid() function suspends the calling thread until one child of + * the process containing the calling thread changes state. It records the + * current state of a child in the structure pointed to by 'info'. If a + * child process changed state prior to the call to waitid(), waitid() + * returns immediately. If more than one thread is suspended in wait() or + * waitpid() waiting termination of the same process, exactly one thread + * will return the process status at the time of the target process + * termination + * + * The idtype and id arguments are used to specify which children waitid() + * will wait for. + * + * If idtype is P_PID, waitid() will wait for the child with a process + * ID equal to (pid_t)id. + * + * If idtype is P_PGID, waitid() will wait for any child with a process + * group ID equal to (pid_t)id. + * + * If idtype is P_ALL, waitid() will wait for any children and id is + * ignored. + * + * The options argument is used to specify which state changes waitid() + * will will wait for. It is formed by OR-ing together one or more of the + * following flags: + * + * WEXITED - Wait for processes that have exited. + * WSTOPPED - Status will be returned for any child that has stopped + * upon receipt of a signal. + * WCONTINUED - Status will be returned for any child that was stopped + * and has been continued. + * WNOHANG - Return immediately if there are no children to wait for. + * WNOWAIT - Keep the process whose status is returned in 'info' in a + * waitable state. This will not affect the state of the process; the + * process may be waited for again after this call completes. + * + * The 'info' argument must point to a siginfo_t structure. If waitid() + * returns because a child process was found that satisfied the conditions + * indicated by the arguments idtype and options, then the structure pointed + * to by 'info' will be filled in by the system with the status of the + * process. The si_signo member will always be equal to SIGCHLD. + * + * Input Parameters: + * See description. + * + * Returned Value: + * If waitid() returns due to the change of state of one of its children, + * 0 is returned. Otherwise, -1 is returned and errno is set to indicate + * the error. + * + * The waitid() function will fail if: + * + * ECHILD - The calling process has no existing unwaited-for child + * processes. + * EINTR - The waitid() function was interrupted by a signal. + * EINVAL - An invalid value was specified for options, or idtype and id + * specify an invalid set of processes. + * + *****************************************************************************/ + +int waitid(idtype_t idtype, id_t id, siginfo_t *info, int options) +{ + FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; + sigset_t sigset; + int err; + int ret; + + /* MISSING LOGIC: If WNOHANG is provided in the options, then this function + * should returned immediately. However, there is no mechanism available now + * know if the thread has child: The children remember their parents (if + * CONFIG_SCHED_HAVE_PARENT) but the parents do not remember their children. + */ + + /* None of the options are supported except for WEXITED (which must be + * provided. Currently SIGCHILD always reports CLD_EXITED so we cannot + * distinguish any other events. + */ + +#ifdef CONFIG_DEBUG + if (options != WEXITED) + { + set_errno(ENOSYS); + return ERROR; + } +#endif + + /* Create a signal set that contains only SIGCHLD */ + + (void)sigemptyset(&sigset); + (void)sigaddset(&sigset, SIGCHLD); + + /* Disable pre-emption so that nothing changes while the loop executes */ + + sched_lock(); + + /* Verify that this task actually has children and that the the requeste + * TCB is actually a child of this task. + */ + + if (rtcb->nchildren == 0) + { + err = ECHILD; + goto errout_with_errno; + } + else if (idtype == P_PID) + { + /* Get the TCB corresponding to this PID and make sure it is our child. */ + + FAR _TCB *ctcb = sched_gettcb((pid_t)id); + if (!ctcb || ctcb->parent != rtcb->pid) + { + err = ECHILD; + goto errout_with_errno; + } + } + + /* Loop until the child that we are waiting for dies */ + + for (;;) + { + /* Check if the task has already died. Signals are not queued in + * NuttX. So a possibility is that the child has died and we + * missed the death of child signal (we got some other signal + * instead). + */ + + if (rtcb->nchildren == 0 || + (idtype == P_PID && (ret = kill((pid_t)id, 0)) < 0)) + { + /* We know that the child task was running okay we stared, + * so we must have lost the signal. What can we do? + * Let's claim we were interrupted by a signal. + */ + + err = EINTR; + goto errout_with_errno; + } + + /* Wait for any death-of-child signal */ + + ret = sigwaitinfo(&sigset, info); + if (ret < 0) + { + goto errout; + } + + /* Make there this was SIGCHLD */ + + if (info->si_signo == SIGCHLD) + { + /* Yes.. Are we waiting for the death of a specific child? */ + + if (idtype == P_PID) + { + /* Was this the death of the thread we were waiting for? */ + + if (info->si_pid == (pid_t)id) + { + /* Yes... return success */ + + break; + } + } + + /* Are we waiting for any child to change state? */ + + else if (idtype == P_ALL) + { + /* Return success */ + + break; + } + + /* Other ID types are not supported */ + + else /* if (idtype == P_PGID) */ + { + set_errno(ENOSYS); + goto errout; + } + } + } + + sched_unlock(); + return OK; + +errout_with_errno: + set_errno(err); +errout: + sched_unlock(); + return ERROR; +} + +#endif /* CONFIG_SCHED_WAITPID && CONFIG_SCHED_HAVE_PARENT*/ diff --git a/nuttx/sched/sched_waitpid.c b/nuttx/sched/sched_waitpid.c index 692ef6410..dc715b2e9 100644 --- a/nuttx/sched/sched_waitpid.c +++ b/nuttx/sched/sched_waitpid.c @@ -1,7 +1,7 @@ /***************************************************************************** * sched/sched_waitpid.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,13 +41,14 @@ #include #include +#include #include #include #include "os_internal.h" -#ifdef CONFIG_SCHED_WAITPID /* Experimental */ +#ifdef CONFIG_SCHED_WAITPID /***************************************************************************** * Private Functions @@ -58,7 +59,7 @@ *****************************************************************************/ /***************************************************************************** - * Name: sched_waitpid + * Name: waitpid * * Description: * @@ -172,10 +173,16 @@ * *****************************************************************************/ -/***************************************************************************/ -/* NOTE: This is a partially functional, experimental version of waitpid() */ -/***************************************************************************/ +/*************************************************************************** + * NOTE: This is a partially functional, experimental version of waitpid() + * + * If there is no SIGCHLD signal supported (CONFIG_SCHED_HAVE_PARENT not + * defined), then waitpid() is still available, but does not obey the + * restriction that the pid be a child of the caller. + * + ***************************************************************************/ +#ifndef CONFIG_SCHED_HAVE_PARENT pid_t waitpid(pid_t pid, int *stat_loc, int options) { _TCB *tcb; @@ -183,9 +190,24 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) int err; int ret; + DEBUGASSERT(stat_loc); + + /* None of the options are supported */ + +#ifdef CONFIG_DEBUG + if (options != 0) + { + set_errno(ENOSYS); + return ERROR; + } +#endif + /* Disable pre-emption so that nothing changes in the following tests */ sched_lock(); + + /* Get the TCB corresponding to this PID */ + tcb = sched_gettcb(pid); if (!tcb) { @@ -193,16 +215,6 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) goto errout_with_errno; } - /* None of the options are supported */ - -#ifdef CONFIG_DEBUG - if (options != 0) - { - err = ENOSYS; - goto errout_with_errno; - } -#endif - /* "If more than one thread is suspended in waitpid() awaiting termination of * the same process, exactly one thread will return the process status at the * time of the target process termination." Hmmm.. what do we return to the @@ -245,4 +257,152 @@ errout: return ERROR; } +/*************************************************************************** + * + * If CONFIG_SCHED_HAVE_PARENT is defined, then waitpid will use the SIGHCLD + * signal. It can also handle the pid == (pid_t)-1 arguement. This is + * slightly more spec-compliant. + * + * But then I have to be concerned about the fact that NuttX does not queue + * signals. This means that a flurry of signals can cause signals to be + * lost (or to have the data in the struct siginfo to be overwritten by + * the next signal). + * + ***************************************************************************/ + +#else +pid_t waitpid(pid_t pid, int *stat_loc, int options) +{ + FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; + FAR struct siginfo info; + sigset_t sigset; + int err; + int ret; + + DEBUGASSERT(stat_loc); + + /* None of the options are supported */ + +#ifdef CONFIG_DEBUG + if (options != 0) + { + set_errno(ENOSYS); + return ERROR; + } +#endif + + /* Create a signal set that contains only SIGCHLD */ + + (void)sigemptyset(&sigset); + (void)sigaddset(&sigset, SIGCHLD); + + /* Disable pre-emption so that nothing changes while the loop executes */ + + sched_lock(); + + /* Verify that this task actually has children and that the the requeste + * TCB is actually a child of this task. + */ + + if (rtcb->nchildren == 0) + { + err = ECHILD; + goto errout_with_errno; + } + else if (pid != (pid_t)-1) + { + /* Get the TCB corresponding to this PID and make sure it is our child. */ + + FAR _TCB *ctcb = sched_gettcb(pid); + if (!ctcb || ctcb->parent != rtcb->pid) + { + err = ECHILD; + goto errout_with_errno; + } + } + + /* Loop until the child that we are waiting for dies */ + + for (;;) + { + /* Check if the task has already died. Signals are not queued in + * NuttX. So a possibility is that the child has died and we + * missed the death of child signal (we got some other signal + * instead). + */ + + if (pid == (pid_t)-1) + { + /* We are waiting for any child, check if there are still + * chilren. + */ + + if (rtcb->nchildren == 0) + { + /* There were one or more children when we started so they + * must have exit'ed. There are just no bread crumbs left + * behind to tell us the PID(s) of the existed children. + * Reporting ECHLD is about all we can do in this case. + */ + + err = ECHILD; + goto errout_with_errno; + } + } + else + { + /* We are waiting for a specific PID. We can use kill() with + * signal number 0 to determine if that task is still alive. + */ + + ret = kill(pid, 0); + if (ret < 0) + { + /* It is no longer running. We know that the child task was + * running okay when we started, so we must have lost the + * signal. In this case, we know that the task exit'ed, but + * we do not know its exit status. It would be better to + * reported ECHILD that bogus status. + */ + + err = ECHILD; + goto errout_with_errno; + } + } + + /* Wait for any death-of-child signal */ + + ret = sigwaitinfo(&sigset, &info); + if (ret < 0) + { + goto errout_with_lock; + } + + /* Was this the death of the thread we were waiting for? In the of + * pid == (pid_t)-1, we are waiting for any child thread. + */ + + if (info.si_signo == SIGCHLD && + (pid == (pid_t)-1 || info.si_pid == pid)) + { + /* Yes... return the status and PID (in the event it was -1) */ + + *stat_loc = info.si_status; + pid = info.si_pid; + break; + } + } + + sched_unlock(); + return (int)pid; + +errout_with_errno: + set_errno(err); + +errout_with_lock: + sched_unlock(); + return ERROR; +} +#endif /* CONFIG_SCHED_HAVE_PARENT */ + #endif /* CONFIG_SCHED_WAITPID */ diff --git a/nuttx/sched/task_exithook.c b/nuttx/sched/task_exithook.c index 9ce2e5899..1106f2885 100644 --- a/nuttx/sched/task_exithook.c +++ b/nuttx/sched/task_exithook.c @@ -217,6 +217,20 @@ static inline void task_sigchild(FAR _TCB *tcb, int status) return; } + /* Decrement the number of children from this parent */ + + DEBUGASSERT(ptcb->nchildren > 0); + ptcb->nchildren--; + + /* Set the parent to an impossible PID. We do this because under certain + * conditions, task_exithook() can be called multiple times. If this + * function is called again, sched_gettcb() will fail on the invalid + * parent PID above, nchildren will be decremented once and all will be + * well. + */ + + tcb->parent = INVALID_PROCESS_ID; + /* Create the siginfo structure. We don't actually know the cause. That * is a bug. Let's just say that the child task just exit-ted for now. */ @@ -246,7 +260,7 @@ static inline void task_sigchild(FAR _TCB *tcb, int status) * ****************************************************************************/ -#ifdef CONFIG_SCHED_WAITPID +#if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) static inline void task_exitwakeup(FAR _TCB *tcb, int status) { /* Wakeup any tasks waiting for this task to exit */ @@ -310,14 +324,14 @@ void task_exithook(FAR _TCB *tcb, int status) task_atexit(tcb); - /* Send SIGCHLD to the parent of the exiting task */ - - task_sigchild(tcb, status); - /* Call any registered on_exit function(s) */ task_onexit(tcb, status); + /* Send SIGCHLD to the parent of the exit-ing task */ + + task_sigchild(tcb, status); + /* Wakeup any tasks waiting for this task to exit */ task_exitwakeup(tcb, status); diff --git a/nuttx/sched/task_setup.c b/nuttx/sched/task_setup.c index c5dd8ca3a..92897f0ae 100644 --- a/nuttx/sched/task_setup.c +++ b/nuttx/sched/task_setup.c @@ -168,7 +168,10 @@ static int task_assignpid(FAR _TCB *tcb) static inline void task_saveparent(FAR _TCB *tcb) { FAR _TCB *rtcb = (FAR _TCB*)g_readytorun.head; + + DEBUGASSERT(rtcb->nchildren < UINT16_MAX); tcb->parent = rtcb->pid; + rtcb->nchildren++; } #else # define task_saveparent(tcb) -- cgit v1.2.3 From 930f9a13511a6d9bc2e44fadef42f6345d921667 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 14 Jan 2013 15:42:03 +0000 Subject: Add support for dup2'ing files. Infrastructure and ROMFS done. Still need FAT, BINFS, NXFFS, and NFS git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5516 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 1 + apps/builtin/binfs.c | 4 +- apps/examples/posix_spawn/spawn_main.c | 14 -- nuttx/ChangeLog | 11 ++ nuttx/TODO | 47 +++++-- nuttx/fs/fat/fs_fat32.c | 46 ++++--- nuttx/fs/fs_files.c | 18 +-- nuttx/fs/nfs/nfs_vfsops.c | 2 + nuttx/fs/nxffs/nxffs_initialize.c | 2 + nuttx/fs/romfs/fs_romfs.c | 245 +++++++++++++++++++++++---------- nuttx/fs/romfs/fs_romfs.h | 1 - nuttx/fs/romfs/fs_romfsutil.c | 12 +- nuttx/include/nuttx/fs/fs.h | 1 + nuttx/include/unistd.h | 2 +- nuttx/libc/spawn/lib_ps.c | 4 +- nuttx/libc/unistd/lib_execsymtab.c | 6 +- nuttx/libc/unistd/lib_execv.c | 4 +- 17 files changed, 269 insertions(+), 151 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 70381a79d..bf329a40d 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -466,3 +466,4 @@ death-of-child signals (SIGCHLD). * apps/examples/ostest/waitpid.c: Add a test for waitpid(), waitid(), and wait(). + * builtin/binfs.c: Add hooks for dup() method (not implemented). diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c index 501f0a4b9..4159c9663 100644 --- a/apps/builtin/binfs.c +++ b/apps/builtin/binfs.c @@ -1,7 +1,7 @@ /**************************************************************************** * apps/builtin/binfs.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -118,7 +118,9 @@ const struct mountpt_operations binfs_operations = NULL, /* write */ NULL, /* seek */ binfs_ioctl, /* ioctl */ + NULL, /* sync */ + NULL, /* dup */ binfs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/apps/examples/posix_spawn/spawn_main.c b/apps/examples/posix_spawn/spawn_main.c index 1506fe499..0ca5f9107 100644 --- a/apps/examples/posix_spawn/spawn_main.c +++ b/apps/examples/posix_spawn/spawn_main.c @@ -89,15 +89,6 @@ # error "You must not disable loadable modules via CONFIG_BINFMT_DISABLE in your configuration file" #endif -/* The redirection test does not work. This is because it tries to redirect - * file as stdin. That won't work now because (1) the file descriptors must - * be dup'ed when the new task is created, and (2) there is no support in - * place for dup'ing file descriptors for anything other than sockets and - * character drivers. This is a bug! - */ - -#define FILE_DUP_BUG 1 - /* Describe the ROMFS file system */ #define SECTORSIZE 512 @@ -147,9 +138,7 @@ static unsigned int g_mmstep; /* Memory Usage at beginning of test step */ static const char delimiter[] = "****************************************************************************"; -#ifndef FILE_DUP_BUG static const char g_redirect[] = "redirect"; -#endif static const char g_hello[] = "hello"; static const char g_data[] = "testdata.txt"; @@ -375,8 +364,6 @@ int spawn_main(int argc, char *argv[]) * Case 2: Simple program with redirection of stdin to a file input *************************************************************************/ -#ifndef FILE_DUP_BUG - /* Output a seperated so that we can clearly discriminate the output of * this program from the others. */ @@ -463,7 +450,6 @@ int spawn_main(int argc, char *argv[]) posix_spawnattr_dump(&attr); mm_update(&g_mmstep, "after file_action/attr destruction"); -#endif /* Clean-up */ diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index e8d4f7309..cb0244e20 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3929,3 +3929,14 @@ need to. * sched/sched_waitid.c and sched_wait.c: Add support for waitid() and wait(). See issues with waitpid() above. + * include/nuttx/fs/fs.h and fs/fs_files.c: Add a dup() method to + the struct mountpt_operations. When dup'ing a file that resides + on a mounted volume, let the file system's dup() method do the + work. + * fs/romfs/fs_romfs.c: Implemented the dup() method for the ROMFS + file system. + * fs/fat/fs_fat32.c, fs/nxffs/nxffs_initialize, and + fs/nfs/nfs_vfsops.c: Add hooks for dup() method (not yet + implemented). + * fs/romfs: Remove the rf_open flag. It looks good, but actually + does nothing. diff --git a/nuttx/TODO b/nuttx/TODO index 88324c06b..28a9ce68b 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 11, 2013) +NuttX TODO List (Last updated January 13, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -8,7 +8,7 @@ nuttx/ (10) Task/Scheduler (sched/) (1) Memory Managment (mm/) - (2) Signals (sched/, arch/) + (3) Signals (sched/, arch/) (2) pthreads (sched/) (2) C++ Support (6) Binary loaders (binfmt/) @@ -99,13 +99,6 @@ o Task/Scheduler (sched/) someone gets motivated and drives the change. Priority: Low - Title: posix_spawn() - Description: This would be a good interface to add to NuttX. It is really - just a re-packaging of the existing, non-standard NuttX exec() - function. - Status: Open. There are no plans to implement this capabilitiey now. - Priority: Medium low. - Title: pause() NON-COMPLIANCE Description: In the POSIX description of this function is the pause() function will suspend the calling thread until delivery of a signal whose @@ -178,6 +171,30 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium Low for now + Title: RETAINING TASK EXIT STATUS + Description: When a task exists, its exit status should be retained in + so data structure until it is reaped (via waitpid(), or + similar interface) or until the parent thread exists. + + You would think that this should be a clone of the existing + pthread join logic. Howver there is no need for zombies + in NuttX so, the status if the parent has already exit'ed. + + At present, exit status is not retained. If waitpid() + is called after the child task has exit'ed it simpley + returns with the ECHLD error. That is not too bad, but + does not tell you what the exit status was. + + A work-around is to: + 1) Call sched_lock() to disable pre-emption. + 2) Start the task (it cannot run because pre-emption is + disbled. + 3) Call waitpid(); + 4) Call sched_unlock() to re-enable pre-emption. + + Status: Open + Priority: Low + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ @@ -249,7 +266,9 @@ o Signals (sched/, arch/) Title: STANDARD SIGNALS Description: 'Standard' signals and signal actions are not supported. - (e.g., SIGINT, SIGCHLD, SIGSEGV, etc). + (e.g., SIGINT, SIGSEGV, etc). + + Update: SIG_CHLD is support if configured. Status: Open. No changes are planned. Priority: Low, required by standards but not so critical for an embedded system. @@ -262,6 +281,14 @@ o Signals (sched/, arch/) are required by the POSIX standard. Priority: Low for now + Title: SIGNAL NUMBERING + Description: In signal.h, the range of valid signals is listed as 0-31. However, + in many interfaces, 0 is not a valid signal number. The valid + signal number should be 1-32. The signal set operations would need + to map bits appropriately. + Status: Open + Priority: Low. Even if there are only 31 usable signals, that is still a lot. + o pthreads (sched/) ^^^^^^^^^^^^^^^^^ diff --git a/nuttx/fs/fat/fs_fat32.c b/nuttx/fs/fat/fs_fat32.c index 0c28cea67..788e6bebc 100644 --- a/nuttx/fs/fat/fs_fat32.c +++ b/nuttx/fs/fat/fs_fat32.c @@ -121,28 +121,30 @@ static int fat_stat(struct inode *mountpt, const char *relpath, struct stat const struct mountpt_operations fat_operations = { - fat_open, - fat_close, - fat_read, - fat_write, - fat_seek, - fat_ioctl, - fat_sync, - - fat_opendir, - NULL, - fat_readdir, - fat_rewinddir, - - fat_bind, - fat_unbind, - fat_statfs, - - fat_unlink, - fat_mkdir, - fat_rmdir, - fat_rename, - fat_stat + fat_open, /* open */ + fat_close, /* close */ + fat_read, /* read */ + fat_write, /* write */ + fat_seek, /* seek */ + fat_ioctl, /* ioctl */ + + fat_sync, /* sync */ + NULL, /* dup */ + + fat_opendir, /* opendir */ + NULL, /* closedir */ + fat_readdir, /* readdir */ + fat_rewinddir, /* rewinddir */ + + fat_bind, /* bind */ + fat_unbind, /* unbind */ + fat_statfs, /* statfs */ + + fat_unlink, /* unlinke */ + fat_mkdir, /* mkdir */ + fat_rmdir, /* rmdir */ + fat_rename, /* rename */ + fat_stat /* stat */ }; /**************************************************************************** diff --git a/nuttx/fs/fs_files.c b/nuttx/fs/fs_files.c index 4da2d28a5..06addb1ef 100644 --- a/nuttx/fs/fs_files.c +++ b/nuttx/fs/fs_files.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/fs_files.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -284,14 +284,6 @@ int files_dup(FAR struct file *filep1, FAR struct file *filep2) goto errout; } -#ifndef CONFIG_DISABLE_MOUNTPOINT - if (INODE_IS_MOUNTPT(filep1->f_inode)) - { - err = ENOSYS; /* Not yet supported */ - goto errout; - } -#endif - list = sched_getfiles(); if (!list) { @@ -331,18 +323,16 @@ int files_dup(FAR struct file *filep1, FAR struct file *filep2) if (inode->u.i_ops && inode->u.i_ops->open) { #ifndef CONFIG_DISABLE_MOUNTPOINT -#if 0 /* Not implemented */ if (INODE_IS_MOUNTPT(inode)) { - /* Open a file on the mountpoint */ + /* Dup the open file on the in the new file structure */ - ret = inode->u.i_mops->open(filep2, ?, filep2->f_oflags, ?); + ret = inode->u.i_mops->dup(filep1, filep2); } else -#endif #endif { - /* Open the pseudo file or device driver */ + /* (Re-)open the pseudo file or device driver */ ret = inode->u.i_ops->open(filep2); } diff --git a/nuttx/fs/nfs/nfs_vfsops.c b/nuttx/fs/nfs/nfs_vfsops.c index 3cd5a47dc..efb026c7f 100644 --- a/nuttx/fs/nfs/nfs_vfsops.c +++ b/nuttx/fs/nfs/nfs_vfsops.c @@ -166,7 +166,9 @@ const struct mountpt_operations nfs_operations = nfs_write, /* write */ NULL, /* seek */ NULL, /* ioctl */ + NULL, /* sync */ + NULL, /* dup */ nfs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/nuttx/fs/nxffs/nxffs_initialize.c b/nuttx/fs/nxffs/nxffs_initialize.c index 6d93a318a..0aa424869 100644 --- a/nuttx/fs/nxffs/nxffs_initialize.c +++ b/nuttx/fs/nxffs/nxffs_initialize.c @@ -82,7 +82,9 @@ const struct mountpt_operations nxffs_operations = nxffs_write, /* write */ NULL, /* seek -- Use f_pos in struct file */ nxffs_ioctl, /* ioctl */ + NULL, /* sync -- No buffered data */ + NULL, /* dup -- not implemented */ nxffs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/nuttx/fs/romfs/fs_romfs.c b/nuttx/fs/romfs/fs_romfs.c index b95619d75..de87c7fec 100644 --- a/nuttx/fs/romfs/fs_romfs.c +++ b/nuttx/fs/romfs/fs_romfs.c @@ -70,24 +70,33 @@ * Private Function Prototypes ****************************************************************************/ -static int romfs_open(FAR struct file *filep, const char *relpath, +static int romfs_open(FAR struct file *filep, FAR const char *relpath, int oflags, mode_t mode); static int romfs_close(FAR struct file *filep); -static ssize_t romfs_read(FAR struct file *filep, char *buffer, size_t buflen); +static ssize_t romfs_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); static off_t romfs_seek(FAR struct file *filep, off_t offset, int whence); -static int romfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int romfs_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); -static int romfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir); -static int romfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); -static int romfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir); +static int romfs_dup(FAR const struct file *oldp, FAR struct file *newp); -static int romfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle); -static int romfs_unbind(void *handle, FAR struct inode **blkdriver); -static int romfs_statfs(struct inode *mountpt, struct statfs *buf); +static int romfs_opendir(FAR struct inode *mountpt, + FAR const char *relpath, + FAR struct fs_dirent_s *dir); +static int romfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); +static int romfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); -static int romfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf); +static int romfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle); +static int romfs_unbind(FAR void *handle, FAR struct inode **blkdriver); +static int romfs_statfs(FAR struct inode *mountpt, + FAR struct statfs *buf); + +static int romfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf); /**************************************************************************** * Private Variables @@ -110,7 +119,9 @@ const struct mountpt_operations romfs_operations = NULL, /* write */ romfs_seek, /* seek */ romfs_ioctl, /* ioctl */ + NULL, /* sync */ + romfs_dup, /* dup */ romfs_opendir, /* opendir */ NULL, /* closedir */ @@ -136,13 +147,13 @@ const struct mountpt_operations romfs_operations = * Name: romfs_open ****************************************************************************/ -static int romfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode) +static int romfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode) { - struct romfs_dirinfo_s dirinfo; - struct romfs_mountpt_s *rm; - struct romfs_file_s *rf; - int ret; + struct romfs_dirinfo_s dirinfo; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *rf; + int ret; fvdbg("Open '%s'\n", relpath); @@ -150,11 +161,11 @@ static int romfs_open(FAR struct file *filep, const char *relpath, DEBUGASSERT(filep->f_priv == NULL && filep->f_inode != NULL); - /* mountpoint private data from the inode reference from the file + /* Get mountpoint private data from the inode reference from the file * structure */ - rm = (struct romfs_mountpt_s*)filep->f_inode->i_private; + rm = (FAR struct romfs_mountpt_s*)filep->f_inode->i_private; DEBUGASSERT(rm != NULL); @@ -214,7 +225,7 @@ static int romfs_open(FAR struct file *filep, const char *relpath, * file. */ - rf = (struct romfs_file_s *)zalloc(sizeof(struct romfs_file_s)); + rf = (FAR struct romfs_file_s *)zalloc(sizeof(struct romfs_file_s)); if (!rf) { fdbg("Failed to allocate private data\n", ret); @@ -226,8 +237,7 @@ static int romfs_open(FAR struct file *filep, const char *relpath, * non-zero elements) */ - rf->rf_open = true; - rf->rf_size = dirinfo.rd_size; + rf->rf_size = dirinfo.rd_size; /* Get the start of the file data */ @@ -277,9 +287,9 @@ errout_with_semaphore: static int romfs_close(FAR struct file *filep) { - struct romfs_mountpt_s *rm; - struct romfs_file_s *rf; - int ret = OK; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *rf; + int ret = OK; fvdbg("Closing\n"); @@ -321,19 +331,20 @@ static int romfs_close(FAR struct file *filep) * Name: romfs_read ****************************************************************************/ -static ssize_t romfs_read(FAR struct file *filep, char *buffer, size_t buflen) +static ssize_t romfs_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) { - struct romfs_mountpt_s *rm; - struct romfs_file_s *rf; - unsigned int bytesread; - unsigned int readsize; - unsigned int nsectors; - uint32_t offset; - size_t bytesleft; - off_t sector; - uint8_t *userbuffer = (uint8_t*)buffer; - int sectorndx; - int ret; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *rf; + unsigned int bytesread; + unsigned int readsize; + unsigned int nsectors; + uint32_t offset; + size_t bytesleft; + off_t sector; + FAR uint8_t *userbuffer = (FAR uint8_t*)buffer; + int sectorndx; + int ret; fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); @@ -467,10 +478,10 @@ errout_with_semaphore: static off_t romfs_seek(FAR struct file *filep, off_t offset, int whence) { - struct romfs_mountpt_s *rm; - struct romfs_file_s *rf; - off_t position; - int ret; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *rf; + off_t position; + int ret; fvdbg("Seek to offset: %d whence: %d\n", offset, whence); @@ -548,9 +559,9 @@ errout_with_semaphore: static int romfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { - struct romfs_mountpt_s *rm; - struct romfs_file_s *rf; - FAR void **ppv = (FAR void**)arg; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *rf; + FAR void **ppv = (FAR void**)arg; fvdbg("cmd: %d arg: %08lx\n", cmd, arg); @@ -581,6 +592,95 @@ static int romfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return -ENOTTY; } +/**************************************************************************** + * Name: romfs_dup + ****************************************************************************/ + +static int romfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_file_s *oldrf; + FAR struct romfs_file_s *newrf; + int ret; + + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Sanity checks */ + + DEBUGASSERT(oldp->f_priv != NULL && + newp->f_priv == NULL && + newp->f_inode != NULL); + + /* Get mountpoint private data from the inode reference from the file + * structure + */ + + rm = (FAR struct romfs_mountpt_s*)newp->f_inode->i_private; + DEBUGASSERT(rm != NULL); + + /* Check if the mount is still healthy */ + + romfs_semtake(rm); + ret = romfs_checkmount(rm); + if (ret != OK) + { + fdbg("romfs_checkmount failed: %d\n", ret); + goto errout_with_semaphore; + } + + /* Recover the old private data from the old struct file instance */ + + oldrf = oldp->f_priv; + + /* Create an new instance of the file private data to describe the new + * dup'ed file. + */ + + newrf = (FAR struct romfs_file_s *)malloc(sizeof(struct romfs_file_s)); + if (!newrf) + { + fdbg("Failed to allocate private data\n", ret); + ret = -ENOMEM; + goto errout_with_semaphore; + } + + /* Copy all file private data (except for the buffer) */ + + newrf->rf_startoffset = oldrf->rf_startoffset; + newrf->rf_size = oldrf->rf_size; + + /* Configure buffering to support access to this file */ + + ret = romfs_fileconfigure(rm, newrf); + if (ret < 0) + { + fdbg("Failed configure buffering: %d\n", ret); + goto errout_with_semaphore; + } + + /* Attach the new private date to the new struct file instance */ + + newp->f_priv = newrf; + + /* Then insert the new instance into the mountpoint structure. + * It needs to be there (1) to handle error conditions that effect + * all files, and (2) to inform the umount logic that we are busy + * (but a simple reference count could have done that). + */ + + newrf->rf_next = rm->rm_head; + rm->rm_head = newrf->rf_next; + + romfs_semgive(rm); + return OK; + + /* Error exits */ + +errout_with_semaphore: + romfs_semgive(rm); + return ret; +} + /**************************************************************************** * Name: romfs_opendir * @@ -589,12 +689,12 @@ static int romfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int romfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir) +static int romfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct fs_dirent_s *dir) { - struct romfs_mountpt_s *rm; - struct romfs_dirinfo_s dirinfo; - int ret; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_dirinfo_s dirinfo; + int ret; fvdbg("relpath: '%s'\n", relpath); @@ -654,14 +754,15 @@ errout_with_semaphore: * ****************************************************************************/ -static int romfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) +static int romfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir) { - struct romfs_mountpt_s *rm; - uint32_t linkoffset; - uint32_t next; - uint32_t info; - uint32_t size; - int ret; + FAR struct romfs_mountpt_s *rm; + uint32_t linkoffset; + uint32_t next; + uint32_t info; + uint32_t size; + int ret; fvdbg("Entry\n"); @@ -749,9 +850,10 @@ errout_with_semaphore: * ****************************************************************************/ -static int romfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) +static int romfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir) { - struct romfs_mountpt_s *rm; + FAR struct romfs_mountpt_s *rm; int ret; fvdbg("Entry\n"); @@ -788,8 +890,8 @@ static int romfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) * ****************************************************************************/ -static int romfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle) +static int romfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle) { struct romfs_mountpt_s *rm; int ret; @@ -813,7 +915,7 @@ static int romfs_bind(FAR struct inode *blkdriver, const void *data, /* Create an instance of the mountpt state structure */ - rm = (struct romfs_mountpt_s *)zalloc(sizeof(struct romfs_mountpt_s)); + rm = (FAR struct romfs_mountpt_s *)zalloc(sizeof(struct romfs_mountpt_s)); if (!rm) { fdbg("Failed to allocate mountpoint structure\n"); @@ -874,9 +976,9 @@ errout_with_sem: * ****************************************************************************/ -static int romfs_unbind(void *handle, FAR struct inode **blkdriver) +static int romfs_unbind(FAR void *handle, FAR struct inode **blkdriver) { - struct romfs_mountpt_s *rm = (struct romfs_mountpt_s*)handle; + FAR struct romfs_mountpt_s *rm = (FAR struct romfs_mountpt_s*)handle; int ret; fvdbg("Entry\n"); @@ -948,10 +1050,10 @@ static int romfs_unbind(void *handle, FAR struct inode **blkdriver) * ****************************************************************************/ -static int romfs_statfs(struct inode *mountpt, struct statfs *buf) +static int romfs_statfs(FAR struct inode *mountpt, FAR struct statfs *buf) { - struct romfs_mountpt_s *rm; - int ret; + FAR struct romfs_mountpt_s *rm; + int ret; fvdbg("Entry\n"); @@ -1004,11 +1106,12 @@ errout_with_semaphore: * ****************************************************************************/ -static int romfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) +static int romfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf) { - struct romfs_mountpt_s *rm; - struct romfs_dirinfo_s dirinfo; - int ret; + FAR struct romfs_mountpt_s *rm; + FAR struct romfs_dirinfo_s dirinfo; + int ret; fvdbg("Entry\n"); diff --git a/nuttx/fs/romfs/fs_romfs.h b/nuttx/fs/romfs/fs_romfs.h index 4081517fb..6a337d2c5 100644 --- a/nuttx/fs/romfs/fs_romfs.h +++ b/nuttx/fs/romfs/fs_romfs.h @@ -159,7 +159,6 @@ struct romfs_mountpt_s struct romfs_file_s { struct romfs_file_s *rf_next; /* Retained in a singly linked list */ - bool rf_open; /* true: The file is (still) open */ uint32_t rf_startoffset; /* Offset to the start of the file data */ uint32_t rf_size; /* Size of the file in bytes */ uint32_t rf_cachesector; /* Current sector in the rf_buffer */ diff --git a/nuttx/fs/romfs/fs_romfsutil.c b/nuttx/fs/romfs/fs_romfsutil.c index 6ea114b5e..4857fb6d3 100644 --- a/nuttx/fs/romfs/fs_romfsutil.c +++ b/nuttx/fs/romfs/fs_romfsutil.c @@ -613,7 +613,7 @@ int romfs_fsconfigure(struct romfs_mountpt_s *rm) } /**************************************************************************** - * Name: romfs_ffileconfigure + * Name: romfs_fileconfigure * * Desciption: * This function is called as part of the ROMFS file open operation It @@ -649,6 +649,7 @@ int romfs_fileconfigure(struct romfs_mountpt_s *rm, struct romfs_file_s *rf) return -ENOMEM; } } + return OK; } @@ -663,7 +664,6 @@ int romfs_fileconfigure(struct romfs_mountpt_s *rm, struct romfs_file_s *rf) int romfs_checkmount(struct romfs_mountpt_s *rm) { - struct romfs_file_s *file; struct inode *inode; struct geometry geo; int ret; @@ -692,14 +692,8 @@ int romfs_checkmount(struct romfs_mountpt_s *rm) /* If we get here, the mount is NOT healthy */ rm->rm_mounted = false; - - /* Make sure that this is flagged in every opened file */ - - for (file = rm->rm_head; file; file = file->rf_next) - { - file->rf_open = false; - } } + return -ENODEV; } diff --git a/nuttx/include/nuttx/fs/fs.h b/nuttx/include/nuttx/fs/fs.h index 1759310bc..3138a8412 100644 --- a/nuttx/include/nuttx/fs/fs.h +++ b/nuttx/include/nuttx/fs/fs.h @@ -161,6 +161,7 @@ struct mountpt_operations */ int (*sync)(FAR struct file *filp); + int (*dup)(FAR const struct file *oldp, FAR struct file *newp); /* Directory operations */ diff --git a/nuttx/include/unistd.h b/nuttx/include/unistd.h index c5289624b..46eb14cdd 100644 --- a/nuttx/include/unistd.h +++ b/nuttx/include/unistd.h @@ -169,7 +169,7 @@ EXTERN int execv(FAR const char *path, FAR char *const argv[]); /* Non-standard functions to manage symbol tables */ struct symtab_s; /* See include/nuttx/binfmt/symtab.h */ -EXTERN void exec_getsymtab(FAR struct symtab_s **symtab, FAR int *nsymbols); +EXTERN void exec_getsymtab(FAR const struct symtab_s **symtab, FAR int *nsymbols); EXTERN void exec_setsymtab(FAR const struct symtab_s *symtab, int nsymbols); #endif diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index dfe57089e..638b27f87 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -70,8 +70,6 @@ struct spawn_parms_s * Public Data ****************************************************************************/ -extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; - /**************************************************************************** * Private Data ****************************************************************************/ @@ -157,7 +155,7 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, FAR char *const argv[]) { struct sched_param param; - FAR struct symtab_s *symtab; + FAR const struct symtab_s *symtab; int nsymbols; int pid; int ret = OK; diff --git a/nuttx/libc/unistd/lib_execsymtab.c b/nuttx/libc/unistd/lib_execsymtab.c index 7abb2d74e..34b798bb4 100644 --- a/nuttx/libc/unistd/lib_execsymtab.c +++ b/nuttx/libc/unistd/lib_execsymtab.c @@ -69,13 +69,13 @@ * Public Variables ****************************************************************************/ -extern struct symtab_s CONFIG_EXECFUNCS_SYMTAB; +extern const struct symtab_s CONFIG_EXECFUNCS_SYMTAB; /**************************************************************************** * Private Data ****************************************************************************/ -static FAR struct symtab_s *g_exec_symtab = &CONFIG_EXECFUNCS_SYMTAB; +static FAR const struct symtab_s *g_exec_symtab = &CONFIG_EXECFUNCS_SYMTAB; static int g_exec_nsymbols = CONFIG_EXECFUNCS_NSYMBOLS; /**************************************************************************** @@ -97,7 +97,7 @@ static int g_exec_nsymbols = CONFIG_EXECFUNCS_NSYMBOLS; * ****************************************************************************/ -void exec_getsymtab(FAR struct symtab_s **symtab, FAR int *nsymbols) +void exec_getsymtab(FAR const struct symtab_s **symtab, FAR int *nsymbols) { irqstate_t flags; diff --git a/nuttx/libc/unistd/lib_execv.c b/nuttx/libc/unistd/lib_execv.c index e35138be5..48b089913 100644 --- a/nuttx/libc/unistd/lib_execv.c +++ b/nuttx/libc/unistd/lib_execv.c @@ -119,7 +119,7 @@ int execv(FAR const char *path, FAR char *const argv[]) { - FAR struct symtab_s *symtab; + FAR const struct symtab_s *symtab; int nsymbols; int ret; @@ -148,4 +148,4 @@ int execv(FAR const char *path, FAR char *const argv[]) return ERROR; } -#endif /* CONFIG_LIBC_EXECFUNCS */ \ No newline at end of file +#endif /* CONFIG_LIBC_EXECFUNCS */ -- cgit v1.2.3 From cc3614dfe8f67033dca8c7c1f40c3367a0d3ca06 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 14 Jan 2013 19:22:32 +0000 Subject: Finish dup logic for open files; fix bug in sigtimedwait(), would return wrong signo value if the signal was already pending git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5517 42af7a65-404d-4744-a932-0658087f49c3 --- apps/builtin/Kconfig | 15 +++++ apps/builtin/binfs.c | 37 ++++++++++- nuttx/ChangeLog | 9 +++ nuttx/TODO | 24 +------- nuttx/fs/fat/fs_fat32.c | 126 +++++++++++++++++++++++++++++++++++++- nuttx/fs/fat/fs_fat32.h | 1 - nuttx/fs/fat/fs_fat32util.c | 10 +-- nuttx/fs/nfs/nfs_node.h | 3 +- nuttx/fs/nfs/nfs_util.c | 9 +-- nuttx/fs/nfs/nfs_vfsops.c | 106 ++++++++++++++++++++++++++++---- nuttx/fs/nfs/rpc_clnt.c | 28 ++++----- nuttx/fs/nxffs/nxffs.h | 41 +++++++------ nuttx/fs/nxffs/nxffs_initialize.c | 4 +- nuttx/fs/nxffs/nxffs_open.c | 62 ++++++++++++++++++- nuttx/fs/romfs/fs_romfs.c | 2 +- nuttx/include/nuttx/fs/fs.h | 2 +- nuttx/sched/mq_initialize.c | 4 +- nuttx/sched/sig_timedwait.c | 2 +- nuttx/sched/task_vfork.c | 2 +- 19 files changed, 384 insertions(+), 103 deletions(-) diff --git a/apps/builtin/Kconfig b/apps/builtin/Kconfig index 8310e6df9..5b262734d 100644 --- a/apps/builtin/Kconfig +++ b/apps/builtin/Kconfig @@ -12,4 +12,19 @@ config BUILTIN to support built-in applications in the NuttShell (NSH). if BUILTIN + + config APPS_BINDIR + bool "BINFS File System" + default n + ---help--- + The BINFS file system is current just a toy. The BINFS may, for example, + be mount at /bin. Then all of the built-in applications will appear as + executable file in /bin if you list them from NSH like: + + nsh> ls -l /bin + + At present, the BINFS supports nothing more than that. It is planned, + however, to support execution of the builtin applications from BINFS as + well (via a binfmt/ loader). However, that is down the road. + endif diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c index 4159c9663..365021c7f 100644 --- a/apps/builtin/binfs.c +++ b/apps/builtin/binfs.c @@ -85,6 +85,8 @@ static int binfs_close(FAR struct file *filep); static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp); + static int binfs_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir); static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); @@ -120,7 +122,7 @@ const struct mountpt_operations binfs_operations = binfs_ioctl, /* ioctl */ NULL, /* sync */ - NULL, /* dup */ + binfs_dup, /* dup */ binfs_opendir, /* opendir */ NULL, /* closedir */ @@ -296,6 +298,39 @@ static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return -ENOTTY; } +/**************************************************************************** + * Name: binfs_dup + * + * Description: + * Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + struct binfs_state_s *bm; + int ret = -ENOSYS; + + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Sanity checks */ + + DEBUGASSERT(oldp->f_priv == NULL && oldp->f_inode != NULL); + + /* mountpoint private data from the inode reference from the file + * structure + */ + + bm = (struct binfs_state_s*)oldp->f_inode->i_private; + DEBUGASSERT(bm != NULL); + + /* Opening of elements within the pseudo-file system is not yet supported + * and, hence, neither is dup'ing the opened file. + */ + + return ret; +} + /**************************************************************************** * Name: binfs_opendir * diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index cb0244e20..4ba0fe985 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3940,3 +3940,12 @@ implemented). * fs/romfs: Remove the rf_open flag. It looks good, but actually does nothing. + * fs/fat: Remove the ff_open flag. Same story as for the ROMFS + rf_open flag. + * fs/fat/fs_fat32.c, fs/nxffs/nxffs_initialize, and + fs/nfs/nfs_vfsops.c: Completed implementation of the dup() methods. + There is still no good test available. + * sched/sig_timedwait.c: sigtimedwait() would return a bad signal + number if the signal was already pending when the function was + called. + called. diff --git a/nuttx/TODO b/nuttx/TODO index 28a9ce68b..0d02e10e6 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 13, 2013) +NuttX TODO List (Last updated January 14, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -15,7 +15,7 @@ nuttx/ (17) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (12) Libraries (libc/, ) - (10) File system/Generic drivers (fs/, drivers/) + (9) File system/Generic drivers (fs/, drivers/) (5) Graphics subystem (graphics/) (1) Pascal add-on (pcode/) (1) Documentation (Documentation/) @@ -879,26 +879,6 @@ o File system / Generic drivers (fs/, drivers/) Status: Open Priority: Medium - Title: dup AND dup2 WILL NOT WORK ON FILES IN A MOUNTED VOLUME - Description: The current implementation of dup() and dup2() will only - work with open device drivers and sockets. It will not - work with open files in a file system. Support for dup'ing - open files on a mounted volume has not been implemented yet. - - There is a stubbed out, partial implemenation in fs/fs_files.c. - In would perform the dup2() operation by re-opening the file - and setting the file pointer. The logic, however, would require - that we remember the (relative) path to the file in the mounted - volume for each open file. - - An option might to add a dup() method to the file system - mountpoint interface. - - A limitation that results from this is that you cannot - redirect I/O to an from and file. - Status: Open - Priority: High - o Graphics subystem (graphics/) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/fs/fat/fs_fat32.c b/nuttx/fs/fat/fs_fat32.c index 788e6bebc..7164a9f8f 100644 --- a/nuttx/fs/fat/fs_fat32.c +++ b/nuttx/fs/fat/fs_fat32.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/fat/fs_fat32.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -86,7 +86,9 @@ static ssize_t fat_write(FAR struct file *filep, const char *buffer, size_t buflen); static off_t fat_seek(FAR struct file *filep, off_t offset, int whence); static int fat_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + static int fat_sync(FAR struct file *filep); +static int fat_dup(FAR const struct file *oldp, FAR struct file *newp); static int fat_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir); @@ -129,7 +131,7 @@ const struct mountpt_operations fat_operations = fat_ioctl, /* ioctl */ fat_sync, /* sync */ - NULL, /* dup */ + fat_dup, /* dup */ fat_opendir, /* opendir */ NULL, /* closedir */ @@ -313,7 +315,6 @@ static int fat_open(FAR struct file *filep, const char *relpath, /* Initialize the file private data (only need to initialize non-zero elements) */ - ff->ff_open = true; ff->ff_oflags = oflags; /* Save information that can be used later to recover the directory entry */ @@ -898,6 +899,7 @@ static off_t fat_seek(FAR struct file *filep, off_t offset, int whence) DEBUGASSERT(fs != NULL); /* Map the offset according to the whence option */ + switch (whence) { case SEEK_SET: /* The offset is set to offset bytes. */ @@ -971,6 +973,7 @@ static off_t fat_seek(FAR struct file *filep, off_t offset, int whence) ret = cluster; goto errout_with_semaphore; } + ff->ff_startcluster = cluster; } @@ -1232,6 +1235,123 @@ errout_with_semaphore: return ret; } +/**************************************************************************** + * Name: fat_dup + * + * Description: Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +static int fat_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + FAR struct fat_mountpt_s *fs; + FAR struct fat_file_s *oldff; + FAR struct fat_file_s *newff; + int ret; + + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Sanity checks */ + + DEBUGASSERT(oldp->f_priv != NULL && + newp->f_priv == NULL && + newp->f_inode != NULL); + + /* Recover our private data from the struct file instance */ + + fs = (struct fat_mountpt_s *)oldp->f_inode->i_private; + DEBUGASSERT(fs != NULL); + + /* Check if the mount is still healthy */ + + fat_semtake(fs); + ret = fat_checkmount(fs); + if (ret != OK) + { + goto errout_with_semaphore; + } + + /* Recover the old private data from the old struct file instance */ + + oldff = oldp->f_priv; + + /* Create a new instance of the file private date to describe the + * dup'ed file. + */ + + newff = (struct fat_file_s *)kmalloc(sizeof(struct fat_file_s)); + if (!newff) + { + ret = -ENOMEM; + goto errout_with_semaphore; + } + + /* Create a file buffer to support partial sector accesses */ + + newff->ff_buffer = (uint8_t*)fat_io_alloc(fs->fs_hwsectorsize); + if (!newff->ff_buffer) + { + ret = -ENOMEM; + goto errout_with_struct; + } + + /* Copy the rest of the open open file state from the old file structure. + * There are some assumptions and potential issues here: + * + * 1) We assume that the higher level logic has copied the elements of + * the file structure, in particular, the file position. + * 2) There is a problem with ff_size if there are multiple opened + * file structures, each believing they know the size of the file. + * If one instance modifies the file length, then the new size of + * the opened file will be unknown to the other. That is a lurking + * bug! + * + * One good solution to this might be to add a refernce count to the + * file structure. Then, instead of dup'ing the whole structure + * as is done here, just increment the reference count on the + * structure. The would have to be integrated with open logic as + * well, however, so that the same file structure is re-used if the + * file is re-opened. + */ + + newff->ff_bflags = 0; + newff->ff_oflags = oldff->ff_oflags; + newff->ff_sectorsincluster = oldff->ff_sectorsincluster; + newff->ff_dirindex = oldff->ff_dirindex; + newff->ff_currentcluster = oldff->ff_currentcluster; + newff->ff_dirsector = oldff->ff_dirsector; + newff->ff_size = oldff->ff_size; + newff->ff_currentsector = 0; + newff->ff_cachesector = 0; + + /* Attach the private date to the struct file instance */ + + newp->f_priv = newff; + + /* Then insert the new instance into the mountpoint structure. + * It needs to be there (1) to handle error conditions that effect + * all files, and (2) to inform the umount logic that we are busy + * (but a simple reference count could have done that). + */ + + newff->ff_next = fs->fs_head; + fs->fs_head = newff->ff_next; + + fat_semgive(fs); + return OK; + + /* Error exits -- goto's are nasty things, but they sure can make error + * handling a lot simpler. + */ + +errout_with_struct: + kfree(newff); + +errout_with_semaphore: + fat_semgive(fs); + return ret; +} + /**************************************************************************** * Name: fat_opendir * diff --git a/nuttx/fs/fat/fs_fat32.h b/nuttx/fs/fat/fs_fat32.h index 71a21333b..81f3f4675 100644 --- a/nuttx/fs/fat/fs_fat32.h +++ b/nuttx/fs/fat/fs_fat32.h @@ -752,7 +752,6 @@ struct fat_mountpt_s struct fat_file_s { struct fat_file_s *ff_next; /* Retained in a singly linked list */ - bool ff_open; /* true: The file is (still) open */ uint8_t ff_bflags; /* The file buffer flags */ uint8_t ff_oflags; /* Flags provided when file was opened */ uint8_t ff_sectorsincluster; /* Sectors remaining in cluster */ diff --git a/nuttx/fs/fat/fs_fat32util.c b/nuttx/fs/fat/fs_fat32util.c index 7231456d7..9aa1d3992 100644 --- a/nuttx/fs/fat/fs_fat32util.c +++ b/nuttx/fs/fat/fs_fat32util.c @@ -692,8 +692,6 @@ int fat_checkmount(struct fat_mountpt_s *fs) if (fs && fs->fs_mounted) { - struct fat_file_s *file; - /* We still think the mount is healthy. Check an see if this is * still the case */ @@ -715,14 +713,8 @@ int fat_checkmount(struct fat_mountpt_s *fs) /* If we get here, the mount is NOT healthy */ fs->fs_mounted = false; - - /* Make sure that this is flagged in every opened file */ - - for (file = fs->fs_head; file; file = file->ff_next) - { - file->ff_open = false; - } } + return -ENODEV; } diff --git a/nuttx/fs/nfs/nfs_node.h b/nuttx/fs/nfs/nfs_node.h index 4ae9e162c..408bd1993 100644 --- a/nuttx/fs/nfs/nfs_node.h +++ b/nuttx/fs/nfs/nfs_node.h @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nfs/nfs_node.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Jose Pablo Rojas Vargas. All rights reserved. * Author: Jose Pablo Rojas Vargas * Gregory Nutt @@ -70,6 +70,7 @@ struct nfsnode { struct nfsnode *n_next; /* Retained in a singly linked list. */ + uint8_t n_crefs; /* Reference count (for nfs_dup) */ uint8_t n_type; /* File type */ uint8_t n_fhsize; /* Size in bytes of the file handle */ uint8_t n_flags; /* Node flags */ diff --git a/nuttx/fs/nfs/nfs_util.c b/nuttx/fs/nfs/nfs_util.c index 73fda72a7..e7d28b3d7 100644 --- a/nuttx/fs/nfs/nfs_util.c +++ b/nuttx/fs/nfs/nfs_util.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nfs/nfs_util.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -213,7 +213,6 @@ int nfs_request(struct nfsmount *nmp, int procnum, { struct rpcclnt *clnt = nmp->nm_rpcclnt; struct nfs_reply_header replyh; - int trylater_delay; int error; tryagain: @@ -250,12 +249,6 @@ tryagain: if (error == EAGAIN) { error = 0; - trylater_delay *= NFS_TIMEOUTMUL; - if (trylater_delay > NFS_MAXTIMEO) - { - trylater_delay = NFS_MAXTIMEO; - } - goto tryagain; } diff --git a/nuttx/fs/nfs/nfs_vfsops.c b/nuttx/fs/nfs/nfs_vfsops.c index efb026c7f..01e999ac8 100644 --- a/nuttx/fs/nfs/nfs_vfsops.c +++ b/nuttx/fs/nfs/nfs_vfsops.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nfs/nfs_vfsops.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Jose Pablo Rojas Vargas. All rights reserved. * Author: Jose Pablo Rojas Vargas * Gregory Nutt @@ -133,6 +133,7 @@ static int nfs_close(FAR struct file *filep); static ssize_t nfs_read(FAR struct file *filep, char *buffer, size_t buflen); static ssize_t nfs_write(FAR struct file *filep, const char *buffer, size_t buflen); +static int nfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int nfs_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir); static int nfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); @@ -168,7 +169,7 @@ const struct mountpt_operations nfs_operations = NULL, /* ioctl */ NULL, /* sync */ - NULL, /* dup */ + nfs_dup, /* dup */ nfs_opendir, /* opendir */ NULL, /* closedir */ @@ -359,7 +360,7 @@ static int nfs_filecreate(FAR struct nfsmount *nmp, struct nfsnode *np, /* Save the attributes in the file data structure */ - tmp = *ptr++; /* handle_follows */ + tmp = *ptr; /* handle_follows */ if (!tmp) { fdbg("WARNING: no file attributes\n"); @@ -369,7 +370,6 @@ static int nfs_filecreate(FAR struct nfsmount *nmp, struct nfsnode *np, /* Initialize the file attributes */ nfs_attrupdate(np, (FAR struct nfs_fattr *)ptr); - ptr += uint32_increment(sizeof(struct nfs_fattr)); } /* Any following dir_wcc data is ignored for now */ @@ -412,7 +412,7 @@ static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np) reqlen += (int)np->n_fhsize; ptr += uint32_increment(np->n_fhsize); - /* Copy the variable-length attribtes */ + /* Copy the variable-length attributes */ *ptr++ = nfs_false; /* Don't change mode */ *ptr++ = nfs_false; /* Don't change uid */ @@ -423,7 +423,7 @@ static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np) *ptr++ = HTONL(NFSV3SATTRTIME_TOSERVER); /* Use the server's time */ *ptr++ = HTONL(NFSV3SATTRTIME_TOSERVER); /* Use the server's time */ *ptr++ = nfs_false; /* No guard value */ - reqlen += 9*sizeof(uint32_t) + reqlen += 9 * sizeof(uint32_t); /* Perform the SETATTR RPC */ @@ -553,9 +553,9 @@ static int nfs_fileopen(FAR struct nfsmount *nmp, struct nfsnode *np, static int nfs_open(FAR struct file *filep, FAR const char *relpath, int oflags, mode_t mode) { - struct nfsmount *nmp; - struct nfsnode *np = NULL; - int error; + struct nfsmount *nmp; + struct nfsnode *np; + int error; /* Sanity checks */ @@ -634,6 +634,8 @@ static int nfs_open(FAR struct file *filep, FAR const char *relpath, * non-zero elements) */ + np->n_crefs = 1; + /* Attach the private data to the struct file instance */ filep->f_priv = np; @@ -656,6 +658,7 @@ errout_with_semaphore: { kfree(np); } + nfs_semgive(nmp); return -error; } @@ -693,8 +696,22 @@ static int nfs_close(FAR struct file *filep) nfs_semtake(nmp); - /* Find our file structure in the list of file structures containted in the - * mount structure. + /* Decrement the reference count. If the reference count would not + * decrement to zero, then that is all we have to do. + */ + + if (np->n_crefs > 1) + { + np->n_crefs--; + nfs_semgive(nmp); + return OK; + } + + /* There are no more references to the file structure. Now we need to + * free up all resources associated with the open file. + * + * First, find our file structure in the list of file structures + * containted in the mount structure. */ for (prev = NULL, curr = nmp->nm_head; curr; prev = curr, curr = curr->n_next) @@ -759,8 +776,8 @@ static ssize_t nfs_read(FAR struct file *filep, char *buffer, size_t buflen) /* Recover our private data from the struct file instance */ - nmp = (struct nfsmount*) filep->f_inode->i_private; - np = (struct nfsnode*) filep->f_priv; + nmp = (struct nfsmount*)filep->f_inode->i_private; + np = (struct nfsnode*)filep->f_priv; DEBUGASSERT(nmp != NULL); @@ -1093,6 +1110,66 @@ errout_with_semaphore: return -error; } +/**************************************************************************** + * Name: binfs_dup + * + * Description: + * Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +static int nfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + struct nfsmount *nmp; + FAR struct nfsnode *np; + int error; + + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Sanity checks */ + + DEBUGASSERT(oldp->f_priv != NULL && oldp->f_inode != NULL); + + /* Recover our private data from the struct file instance */ + + nmp = (struct nfsmount*)oldp->f_inode->i_private; + np = (struct nfsnode*)oldp->f_priv; + + DEBUGASSERT(nmp != NULL); + + /* Check if the mount is still healthy */ + + nfs_semtake(nmp); + error = nfs_checkmount(nmp); + if (error != OK) + { + fdbg("ERROR: nfs_checkmount failed: %d\n", error); + nfs_semgive(nmp); + return -error; + } + + /* Increment the reference count on the NFS node structure */ + + DEBUGASSERT(np->n_crefs < 0xff); + np->n_crefs++; + + /* And save this as the file data for the new node */ + + newp->f_priv = np; + + /* Then insert the new instance at the head of the list in the mountpoint + * tructure. It needs to be there (1) to handle error conditions that effect + * all files, and (2) to inform the umount logic that we are busy. We + * cannot unmount the file system if this list is not empty! + */ + + np->n_next = nmp->nm_head; + nmp->nm_head = np; + + nfs_semgive(nmp); + return OK; +} + /**************************************************************************** * Name: nfs_opendir * @@ -1756,12 +1833,15 @@ bad: { kfree(nmp->nm_so); } + if (nmp->nm_rpcclnt) { kfree(nmp->nm_rpcclnt); } + kfree(nmp); } + return error; } diff --git a/nuttx/fs/nfs/rpc_clnt.c b/nuttx/fs/nfs/rpc_clnt.c index 0e2a394ba..9c2ada4f2 100644 --- a/nuttx/fs/nfs/rpc_clnt.c +++ b/nuttx/fs/nfs/rpc_clnt.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nfs/rpc_clnt.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Jose Pablo Rojas Vargas. All rights reserved. * Author: Jose Pablo Rojas Vargas * Gregory Nutt @@ -224,8 +224,6 @@ static int rpcclnt_receive(FAR struct rpcclnt *rpc, FAR struct sockaddr *aname, static int rpcclnt_reply(FAR struct rpcclnt *rpc, int procid, int prog, FAR void *reply, size_t resplen) { - FAR struct rpc_reply_header *replyheader; - uint32_t rxid; int error; /* Get the next RPC reply from the socket */ @@ -235,22 +233,22 @@ static int rpcclnt_reply(FAR struct rpcclnt *rpc, int procid, int prog, { fdbg("ERROR: rpcclnt_receive returned: %d\n", error); - /* If we failed because of a timeout, then try sending the CALL - * message again. - */ + /* If we failed because of a timeout, then try sending the CALL + * message again. + */ - if (error == EAGAIN || error == ETIMEDOUT) - { - rpc->rc_timeout = true; - } - } + if (error == EAGAIN || error == ETIMEDOUT) + { + rpc->rc_timeout = true; + } + } /* Get the xid and check that it is an RPC replysvr */ else { - replyheader = (FAR struct rpc_reply_header *)reply; - rxid = replyheader->rp_xid; + FAR struct rpc_reply_header *replyheader = + (FAR struct rpc_reply_header *)reply; if (replyheader->rp_direction != rpc_reply) { @@ -260,7 +258,7 @@ static int rpcclnt_reply(FAR struct rpcclnt *rpc, int procid, int prog, } } - return OK; + return error; } /**************************************************************************** @@ -275,7 +273,6 @@ static uint32_t rpcclnt_newxid(void) { static uint32_t rpcclnt_xid = 0; static uint32_t rpcclnt_xid_touched = 0; - int xidp = 0; srand(time(NULL)); if ((rpcclnt_xid == 0) && (rpcclnt_xid_touched == 0)) @@ -285,6 +282,7 @@ static uint32_t rpcclnt_newxid(void) } else { + int xidp = 0; do { xidp = rand(); diff --git a/nuttx/fs/nxffs/nxffs.h b/nuttx/fs/nxffs/nxffs.h index 616dc7197..083e00fa7 100644 --- a/nuttx/fs/nxffs/nxffs.h +++ b/nuttx/fs/nxffs/nxffs.h @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -1044,6 +1044,7 @@ extern int nxffs_pack(FAR struct nxffs_volume_s *volume); * - nxffs_read() is defined in nxffs_read.c * - nxffs_write() is defined in nxffs_write.c * - nxffs_ioctl() is defined in nxffs_ioctl.c + * - nxffs_dup() is defined in nxffs_open.c * - nxffs_opendir(), nxffs_readdir(), and nxffs_rewindir() are defined in * nxffs_dirent.c * - nxffs_bind() and nxffs_unbind() are defined in nxffs_initialize.c @@ -1058,25 +1059,25 @@ struct fs_dirent_s; struct statfs; struct stat; -extern int nxffs_open(FAR struct file *filep, FAR const char *relpath, - int oflags, mode_t mode); -extern int nxffs_close(FAR struct file *filep); -extern ssize_t nxffs_read(FAR struct file *filep, FAR char *buffer, - size_t buflen); -extern ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, - size_t buflen); -extern int nxffs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); -extern int nxffs_opendir(FAR struct inode *mountpt, FAR const char *relpath, - FAR struct fs_dirent_s *dir); -extern int nxffs_readdir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); -extern int nxffs_rewinddir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); -extern int nxffs_bind(FAR struct inode *blkdriver, FAR const void *data, - FAR void **handle); -extern int nxffs_unbind(FAR void *handle, FAR struct inode **blkdriver); -extern int nxffs_statfs(FAR struct inode *mountpt, FAR struct statfs *buf); -extern int nxffs_stat(FAR struct inode *mountpt, FAR const char *relpath, - FAR struct stat *buf); -extern int nxffs_unlink(FAR struct inode *mountpt, FAR const char *relpath); +int nxffs_open(FAR struct file *filep, FAR const char *relpath, int oflags, + mode_t mode); +int nxffs_close(FAR struct file *filep); +ssize_t nxffs_read(FAR struct file *filep, FAR char *buffer, size_t buflen); +ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +int nxffs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +int nxffs_dup(FAR const struct file *oldp, FAR struct file *newp); +int nxffs_opendir(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct fs_dirent_s *dir); +int nxffs_readdir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); +int nxffs_rewinddir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); +int nxffs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle); +int nxffs_unbind(FAR void *handle, FAR struct inode **blkdriver); +int nxffs_statfs(FAR struct inode *mountpt, FAR struct statfs *buf); +int nxffs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf); +int nxffs_unlink(FAR struct inode *mountpt, FAR const char *relpath); #endif /* __FS_NXFFS_NXFFS_H */ diff --git a/nuttx/fs/nxffs/nxffs_initialize.c b/nuttx/fs/nxffs/nxffs_initialize.c index 0aa424869..4e7428c73 100644 --- a/nuttx/fs/nxffs/nxffs_initialize.c +++ b/nuttx/fs/nxffs/nxffs_initialize.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_initialize.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -84,7 +84,7 @@ const struct mountpt_operations nxffs_operations = nxffs_ioctl, /* ioctl */ NULL, /* sync -- No buffered data */ - NULL, /* dup -- not implemented */ + nxffs_dup, /* dup */ nxffs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/nuttx/fs/nxffs/nxffs_open.c b/nuttx/fs/nxffs/nxffs_open.c index eb7817c57..b1e99267f 100644 --- a/nuttx/fs/nxffs/nxffs_open.c +++ b/nuttx/fs/nxffs/nxffs_open.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_open.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -1023,7 +1023,7 @@ int nxffs_open(FAR struct file *filep, FAR const char *relpath, #endif /* Limitation: A file must be opened for reading or writing, but not both. - * There is no general for extending the size of of a file. Extending the + * There is no general way of extending the size of a file. Extending the * file size of possible if the file to be extended is the last in the * sequence on FLASH, but since that case is not the general case, no file * extension is supported. @@ -1058,6 +1058,64 @@ int nxffs_open(FAR struct file *filep, FAR const char *relpath, return ret; } +/**************************************************************************** + * Name: binfs_dup + * + * Description: + * Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +int nxffs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ +#ifdef CONFIG_DEBUG + FAR struct nxffs_volume_s *volume; +#endif + FAR struct nxffs_ofile_s *ofile; + + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Sanity checks */ + +#ifdef CONFIG_DEBUG + DEBUGASSERT(oldp->f_priv == NULL && oldp->f_inode != NULL); + + /* Get the mountpoint private data from the NuttX inode reference in the + * file structure + */ + + volume = (FAR struct nxffs_volume_s*)oldp->f_inode->i_private; + DEBUGASSERT(volume != NULL); +#endif + + /* Recover the open file state from the struct file instance */ + + ofile = (FAR struct nxffs_ofile_s *)oldp->f_priv; + + /* I do not think we need exclusive access to the volume to do this. + * The volume exclsem protects the open file list and, hence, would + * assure that the ofile is stable. However, it is assumed that the + * caller holds a value file descriptor associated with this ofile, + * so it should be stable throughout the life of this function. + */ + + /* Limitations: I do not think we have to be concerned about the + * usual NXFFS file limitations here: dup'ing cannot resulting + * in mixed reading and writing to the same file, or multiple + * writer to different file. + * + * I notice that nxffs_wropen will prohibit multiple opens for + * writing. But I do not thing that dup'ing a file already opened + * for writing suffers from any of these issues. + */ + + /* Just increment the reference count on the ofile */ + + ofile->crefs++; + newp->f_priv = (FAR void *)ofile; + return OK; +} + /**************************************************************************** * Name: nxffs_close * diff --git a/nuttx/fs/romfs/fs_romfs.c b/nuttx/fs/romfs/fs_romfs.c index de87c7fec..2814aa49d 100644 --- a/nuttx/fs/romfs/fs_romfs.c +++ b/nuttx/fs/romfs/fs_romfs.c @@ -636,7 +636,7 @@ static int romfs_dup(FAR const struct file *oldp, FAR struct file *newp) * dup'ed file. */ - newrf = (FAR struct romfs_file_s *)malloc(sizeof(struct romfs_file_s)); + newrf = (FAR struct romfs_file_s *)kmalloc(sizeof(struct romfs_file_s)); if (!newrf) { fdbg("Failed to allocate private data\n", ret); diff --git a/nuttx/include/nuttx/fs/fs.h b/nuttx/include/nuttx/fs/fs.h index 3138a8412..327bf37ca 100644 --- a/nuttx/include/nuttx/fs/fs.h +++ b/nuttx/include/nuttx/fs/fs.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/fs/fs.h * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/sched/mq_initialize.c b/nuttx/sched/mq_initialize.c index 5b03a1120..dd7c7ed0f 100644 --- a/nuttx/sched/mq_initialize.c +++ b/nuttx/sched/mq_initialize.c @@ -217,11 +217,11 @@ void mq_initialize(void) void mq_desblockalloc(void) { - struct mq_des_block_s *mqdesblock; + FAR struct mq_des_block_s *mqdesblock; /* Allocate a block of message descriptors */ - mqdesblock = (struct mq_des_block_s *)kmalloc(sizeof(struct mq_des_block_s)); + mqdesblock = (FAR struct mq_des_block_s *)kmalloc(sizeof(struct mq_des_block_s)); if (mqdesblock) { int i; diff --git a/nuttx/sched/sig_timedwait.c b/nuttx/sched/sig_timedwait.c index b07b8f2a1..f8c619b21 100644 --- a/nuttx/sched/sig_timedwait.c +++ b/nuttx/sched/sig_timedwait.c @@ -228,7 +228,7 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, /* The return value is the number of the signal that awakened us */ - ret = info->si_signo; + ret = sigpend->info.si_signo; } /* We will have to wait for a signal to be posted to this task. */ diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c index 0ea09b048..4b42c7b36 100644 --- a/nuttx/sched/task_vfork.c +++ b/nuttx/sched/task_vfork.c @@ -291,7 +291,7 @@ pid_t task_vforkstart(FAR _TCB *child) * still running. */ - while ((ret = kill(pid, 0)) == OK) + while (kill(pid, 0) == OK) { /* Yes.. then we can yield to it -- assuming that it has not lowered * its priority. sleep(0) might be a safer thing to do since it does -- cgit v1.2.3 From 87b33d354695294b519f7f6f1275592faf4fee46 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 14 Jan 2013 22:06:19 +0000 Subject: Configre configs/ubw32/ostest to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5518 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 6 +- nuttx/arch/Kconfig | 18 + nuttx/arch/arm/Kconfig | 2 + nuttx/arch/arm/src/common/up_internal.h | 4 +- nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c | 4 +- nuttx/arch/arm/src/kinetis/kinetis_start.c | 2 +- nuttx/arch/mips/Kconfig | 2 + nuttx/arch/mips/src/common/up_internal.h | 4 +- nuttx/arch/mips/src/pic32mx/Kconfig | 6 +- nuttx/arch/mips/src/pic32mx/pic32mx-head.S | 21 +- nuttx/configs/README.txt | 2 +- nuttx/configs/kwikstik-k40/ostest/defconfig | 2 +- nuttx/configs/mirtoo/nsh/defconfig | 6 +- nuttx/configs/mirtoo/nxffs/defconfig | 6 +- nuttx/configs/mirtoo/ostest/defconfig | 6 +- nuttx/configs/pcblogic-pic32mx/nsh/defconfig | 10 +- nuttx/configs/pcblogic-pic32mx/ostest/defconfig | 10 +- nuttx/configs/pic32-starterkit/nsh/defconfig | 10 +- nuttx/configs/pic32-starterkit/nsh2/defconfig | 10 +- nuttx/configs/pic32-starterkit/ostest/defconfig | 10 +- nuttx/configs/pic32mx7mmb/nsh/defconfig | 10 +- nuttx/configs/pic32mx7mmb/ostest/defconfig | 10 +- nuttx/configs/sure-pic32mx/nsh/defconfig | 10 +- nuttx/configs/sure-pic32mx/ostest/defconfig | 10 +- nuttx/configs/sure-pic32mx/usbnsh/defconfig | 10 +- nuttx/configs/twr-k60n512/nsh/defconfig | 2 +- nuttx/configs/twr-k60n512/ostest/defconfig | 2 +- nuttx/configs/ubw32/README.txt | 27 +- nuttx/configs/ubw32/nsh/Make.defs | 4 +- nuttx/configs/ubw32/nsh/defconfig | 10 +- nuttx/configs/ubw32/nsh/ld.script | 317 -------- nuttx/configs/ubw32/ostest/Make.defs | 4 +- nuttx/configs/ubw32/ostest/appconfig | 39 - nuttx/configs/ubw32/ostest/defconfig | 927 +++++++++++++---------- nuttx/configs/ubw32/ostest/ld.script | 317 -------- nuttx/configs/ubw32/scripts/ld.script | 317 ++++++++ 36 files changed, 945 insertions(+), 1212 deletions(-) delete mode 100644 nuttx/configs/ubw32/nsh/ld.script delete mode 100644 nuttx/configs/ubw32/ostest/appconfig delete mode 100644 nuttx/configs/ubw32/ostest/ld.script create mode 100644 nuttx/configs/ubw32/scripts/ld.script diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 4ba0fe985..41ac95db0 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3948,4 +3948,8 @@ * sched/sig_timedwait.c: sigtimedwait() would return a bad signal number if the signal was already pending when the function was called. - called. + * configs/ubw32/scripts: All common linker scripts moved to this + scripts sub-directory + * configs/ubw32/ostest: Configuration configured to use the + kconfig-frontends tools. + diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig index 7d34b56f4..d43137adb 100644 --- a/nuttx/arch/Kconfig +++ b/nuttx/arch/Kconfig @@ -109,6 +109,10 @@ config ARCH_NOINTC bool default n +config ARCH_VECNOTIRQ + bool + default n + config ARCH_DMA bool default n @@ -141,6 +145,20 @@ config ENDIAN_BIG ---help--- Select if architecture operates using big-endian byte ordering. +config ARCH_HAVE_RAMFUNCS + bool + default n + +config ARCH_RAMFUNCS + bool "Copy functions to RAM on startup" + default n + depends on ARCH_HAVE_RAMFUNCS + ---help--- + Copy some functions to RAM at boot time. This is done in some + architectures to improve performance. In other cases, it is done + so that FLASH can be reconfigured while the MCU executes out of + SRAM. + comment "Board Settings" config BOARD_LOOPSPERMSEC diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index bc7634695..36343e319 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -47,6 +47,8 @@ config ARCH_CHIP_KINETIS select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_IRQPRIO + select ARCH_HAVE_RAMFUNCS + select ARCH_RAMFUNCS ---help--- Freescale Kinetis Architectures (ARM Cortex-M4) diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h index 0d3c5b1f2..55071345f 100644 --- a/nuttx/arch/arm/src/common/up_internal.h +++ b/nuttx/arch/arm/src/common/up_internal.h @@ -188,7 +188,7 @@ extern uint32_t _ebss; /* End+1 of .bss */ * will create a function named foo that will execute from RAM. */ -#ifdef CONFIG_BOOT_RAMFUNCS +#ifdef CONFIG_ARCH_RAMFUNCS # define __ramfunc__ __attribute__ ((section(".ramfunc"))) @@ -204,7 +204,7 @@ extern const uint32_t _framfuncs; /* Copy source address in FLASH */ extern uint32_t _sramfuncs; /* Copy destination start address in RAM */ extern uint32_t _eramfuncs; /* Copy destination start address in RAM */ -#endif /* CONFIG_BOOT_RAMFUNCS */ +#endif /* CONFIG_ARCH_RAMFUNCS */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c index 31ea235d2..ad6e42884 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -55,8 +55,8 @@ * Private Definitions ****************************************************************************/ -#ifndef CONFIG_BOOT_RAMFUNCS -# error "CONFIG_BOOT_RAMFUNCS must be defined for this logic" +#ifndef CONFIG_ARCH_RAMFUNCS +# error "CONFIG_ARCH_RAMFUNCS must be defined for this logic" #endif /**************************************************************************** diff --git a/nuttx/arch/arm/src/kinetis/kinetis_start.c b/nuttx/arch/arm/src/kinetis/kinetis_start.c index c8f20fbdd..2f73cb2e6 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_start.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_start.c @@ -116,7 +116,7 @@ void __start(void) * at _framfuncs */ -#ifdef CONFIG_BOOT_RAMFUNCS +#ifdef CONFIG_ARCH_RAMFUNCS for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) { *dest++ = *src++; diff --git a/nuttx/arch/mips/Kconfig b/nuttx/arch/mips/Kconfig index 772b6f663..1b10e26ae 100644 --- a/nuttx/arch/mips/Kconfig +++ b/nuttx/arch/mips/Kconfig @@ -12,6 +12,8 @@ config ARCH_CHIP_PIC32MX bool "PIC32MX" select ARCH_MIPS32 select ARCH_IRQPRIO + select ARCH_VECNOTIRQ + select ARCH_HAVE_RAMFUNCS ---help--- Microchip PIC32MX320F032H (MIPS32) diff --git a/nuttx/arch/mips/src/common/up_internal.h b/nuttx/arch/mips/src/common/up_internal.h index 0eb1ed6a0..b284961b0 100644 --- a/nuttx/arch/mips/src/common/up_internal.h +++ b/nuttx/arch/mips/src/common/up_internal.h @@ -152,7 +152,7 @@ extern uint32_t _sdata; /* Start of .data */ extern uint32_t _edata; /* End+1 of .data */ extern uint32_t _sbss; /* Start of .bss */ extern uint32_t _ebss; /* End+1 of .bss */ -#ifdef CONFIG_PIC32MX_RAMFUNCS +#ifdef CONFIG_ARCH_RAMFUNCS extern uint32_t _sramfunc; /* Start of ramfuncs */ extern uint32_t _eramfunc; /* End+1 of ramfuncs */ extern uint32_t _ramfunc_loadaddr; /* Start of ramfuncs in FLASH */ @@ -160,7 +160,7 @@ extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ extern uint32_t _bmxdkpba_address; /* BMX register setting */ extern uint32_t _bmxdudba_address; /* BMX register setting */ extern uint32_t _bmxdupba_address; /* BMX register setting */ -#endif /* CONFIG_PIC32MX_RAMFUNCS */ +#endif /* CONFIG_ARCH_RAMFUNCS */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/nuttx/arch/mips/src/pic32mx/Kconfig b/nuttx/arch/mips/src/pic32mx/Kconfig index bcb99cf6d..6ac10608b 100644 --- a/nuttx/arch/mips/src/pic32mx/Kconfig +++ b/nuttx/arch/mips/src/pic32mx/Kconfig @@ -533,10 +533,14 @@ config PIC32MX_CM1 bool "Comparator 1 (CM1)" default n -config PIC32MX_CM2 +config PIC32MX_CM2 bool "Comparator 2 (CM2)" default n +config PIC32MX_CM3 + bool "Comparator 3 (CM3)" + default n + config PIC32MX_RTCC bool "Real-Time Clock and Calendar (RTCC)" default n diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S index 7224ee122..2e1a34080 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-head.S +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-head.S @@ -367,7 +367,7 @@ __start: * initializing bus matrix registers. */ -#ifdef CONFIG_PIC32MX_RAMFUNCS +#ifdef CONFIG_ARCH_RAMFUNCS la t1, _ramfunc_sizeof beqz t1, .Lnoramfuncs nop @@ -598,17 +598,26 @@ halt: devconfig: devconfig3: #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + .long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \ CONFIG_PIC32MX_PMDL1WAY << 28 | CONFIG_PIC32MX_IOL1WAY << 29 | \ CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \ DEVCFG3_UNUSED -#else + +#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + + .long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \ + DEVCFG3_UNUSED + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + .long CONFIG_PIC32MX_USERID << DEVCFG3_USERID_SHIFT | \ CONFIG_PIC32MX_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \ CONFIG_PIC32MX_FMIIEN << 24 | CONFIG_PIC32MX_FETHIO << 25 | \ CONFIG_PIC32MX_FCANIO << 26 | CONFIG_PIC32MX_FSCM1IO << 29 | \ CONFIG_PIC32MX_USBIDO << 30 | CONFIG_PIC32MX_VBUSIO << 31 | \ DEVCFG3_UNUSED + #endif devconfig2: @@ -618,22 +627,27 @@ devconfig2: devconfig1: #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + .long CONFIG_PIC32MX_FNOSC | CONFIG_PIC32MX_FSOSCEN | \ CONFIG_PIC32MX_IESO | CONFIG_PIC32MX_POSCMOD | \ CONFIG_PIC32MX_OSCOUT << 10 | \ CONFIG_PIC32MX_PBDIV | CONFIG_PIC32MX_FCKSM | \ DEVCFG1_WINDIS | CONFIG_PIC32MX_WDENABLE | \ DEVCFG1_FWDTWINSZ_75 | DEVCFG1_UNUSED + #else + .long CONFIG_PIC32MX_FNOSC | CONFIG_PIC32MX_FSOSCEN | \ CONFIG_PIC32MX_IESO | CONFIG_PIC32MX_POSCMOD | \ CONFIG_PIC32MX_OSCOUT << 10 | \ CONFIG_PIC32MX_PBDIV | CONFIG_PIC32MX_FCKSM | \ CONFIG_PIC32MX_WDENABLE | DEVCFG1_UNUSED + #endif devconfig0: #if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2) + .long CONFIG_PIC32MX_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \ DEVCFG0_JTAGEN | \ CONFIG_PIC32MX_ICESEL << DEVCFG0_ICESEL_SHIFT | \ @@ -641,13 +655,16 @@ devconfig0: CONFIG_PIC32MX_BOOTFLASHWP << 24 | \ CONFIG_PIC32MX_CODEWP << 28 | \ DEVCFG0_UNUSED + #else + .long CONFIG_PIC32MX_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \ CONFIG_PIC32MX_ICESEL << 3 | \ CONFIG_PIC32MX_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \ CONFIG_PIC32MX_BOOTFLASHWP << 24 | \ CONFIG_PIC32MX_CODEWP << 28 | \ DEVCFG0_UNUSED + #endif .size devconfig, .-devconfig diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 4800f02ee..babdf7330 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1590,7 +1590,7 @@ defconfig -- This is a configuration file similar to the Linux operation from FLASH but must copy initialized .data sections to RAM. CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH but copy themselves entirely into RAM for better performance. - CONFIG_BOOT_RAMFUNCS - Other configurations may copy just some functions + CONFIG_ARCH_RAMFUNCS - Other configurations may copy just some functions into RAM, either for better performance or for errata workarounds. CONFIG_STACK_ALIGNMENT - Set if the your application has specific stack alignment requirements (may not be supported diff --git a/nuttx/configs/kwikstik-k40/ostest/defconfig b/nuttx/configs/kwikstik-k40/ostest/defconfig index 5f0291ced..ff8c39c1f 100755 --- a/nuttx/configs/kwikstik-k40/ostest/defconfig +++ b/nuttx/configs/kwikstik-k40/ostest/defconfig @@ -460,7 +460,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # CONFIG_BOOT_RUNFROMFLASH=n CONFIG_BOOT_COPYTORAM=n -CONFIG_BOOT_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y CONFIG_CUSTOM_STACK=n CONFIG_IDLETHREAD_STACKSIZE=1024 CONFIG_USERMAIN_STACKSIZE=2048 diff --git a/nuttx/configs/mirtoo/nsh/defconfig b/nuttx/configs/mirtoo/nsh/defconfig index 94a6b8b17..6e0d3bf70 100644 --- a/nuttx/configs/mirtoo/nsh/defconfig +++ b/nuttx/configs/mirtoo/nsh/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in linker scripts as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n CONFIG_PIC32MX_CM3=n CONFIG_PIC32MX_RTCC=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y # # Mirtoo Board Settings diff --git a/nuttx/configs/mirtoo/nxffs/defconfig b/nuttx/configs/mirtoo/nxffs/defconfig index d633e56d9..ed50e0325 100644 --- a/nuttx/configs/mirtoo/nxffs/defconfig +++ b/nuttx/configs/mirtoo/nxffs/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in linker scripts as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n CONFIG_PIC32MX_CM3=n CONFIG_PIC32MX_RTCC=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y # # Mirtoo Board Settings diff --git a/nuttx/configs/mirtoo/ostest/defconfig b/nuttx/configs/mirtoo/ostest/defconfig index 471dab444..5c8b69785 100644 --- a/nuttx/configs/mirtoo/ostest/defconfig +++ b/nuttx/configs/mirtoo/ostest/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in linker scripts as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -105,7 +105,6 @@ CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n CONFIG_PIC32MX_CM3=n CONFIG_PIC32MX_RTCC=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -113,9 +112,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig index 7bce554ac..6f1ef7dc9 100644 --- a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig index 730b8134a..1df428f8a 100644 --- a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index 32220d89b..f1c543e5f 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n CONFIG_PIC32MX_CAN1=n CONFIG_PIC32MX_CAN2=n CONFIG_PIC32MX_ETHERNET=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig index a7a1ff18a..f681b7689 100644 --- a/nuttx/configs/pic32-starterkit/nsh2/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n CONFIG_PIC32MX_CAN1=n CONFIG_PIC32MX_CAN2=n CONFIG_PIC32MX_ETHERNET=y -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig index 3a55de491..6a077f209 100644 --- a/nuttx/configs/pic32-starterkit/ostest/defconfig +++ b/nuttx/configs/pic32-starterkit/ostest/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n CONFIG_PIC32MX_CAN1=n CONFIG_PIC32MX_CAN2=n CONFIG_PIC32MX_ETHERNET=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig index d39f8bc40..66cd240e2 100644 --- a/nuttx/configs/pic32mx7mmb/nsh/defconfig +++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n CONFIG_PIC32MX_CAN1=n CONFIG_PIC32MX_CAN2=n CONFIG_PIC32MX_ETHERNET=y -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/pic32mx7mmb/ostest/defconfig b/nuttx/configs/pic32mx7mmb/ostest/defconfig index b3cecf98d..7cb71995e 100644 --- a/nuttx/configs/pic32mx7mmb/ostest/defconfig +++ b/nuttx/configs/pic32mx7mmb/ostest/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -108,7 +108,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -119,13 +118,6 @@ CONFIG_PIC32MX_USBHOST=n CONFIG_PIC32MX_CAN1=n CONFIG_PIC32MX_CAN2=n CONFIG_PIC32MX_ETHERNET=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/sure-pic32mx/nsh/defconfig b/nuttx/configs/sure-pic32mx/nsh/defconfig index 60c4dc53d..07b31a1ae 100644 --- a/nuttx/configs/sure-pic32mx/nsh/defconfig +++ b/nuttx/configs/sure-pic32mx/nsh/defconfig @@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/sure-pic32mx/ostest/defconfig b/nuttx/configs/sure-pic32mx/ostest/defconfig index 1bca11c47..86bb3b307 100644 --- a/nuttx/configs/sure-pic32mx/ostest/defconfig +++ b/nuttx/configs/sure-pic32mx/ostest/defconfig @@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/sure-pic32mx/usbnsh/defconfig b/nuttx/configs/sure-pic32mx/usbnsh/defconfig index 978e16541..9f6046f21 100644 --- a/nuttx/configs/sure-pic32mx/usbnsh/defconfig +++ b/nuttx/configs/sure-pic32mx/usbnsh/defconfig @@ -62,7 +62,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -103,7 +103,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -111,13 +110,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=y CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/twr-k60n512/nsh/defconfig b/nuttx/configs/twr-k60n512/nsh/defconfig index 7a4bb3b3a..3f272b55a 100644 --- a/nuttx/configs/twr-k60n512/nsh/defconfig +++ b/nuttx/configs/twr-k60n512/nsh/defconfig @@ -462,7 +462,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # CONFIG_BOOT_RUNFROMFLASH=n CONFIG_BOOT_COPYTORAM=n -CONFIG_BOOT_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y CONFIG_CUSTOM_STACK=n CONFIG_IDLETHREAD_STACKSIZE=1024 CONFIG_USERMAIN_STACKSIZE=2048 diff --git a/nuttx/configs/twr-k60n512/ostest/defconfig b/nuttx/configs/twr-k60n512/ostest/defconfig index 355e5773b..fd27ffc2b 100644 --- a/nuttx/configs/twr-k60n512/ostest/defconfig +++ b/nuttx/configs/twr-k60n512/ostest/defconfig @@ -459,7 +459,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n # CONFIG_BOOT_RUNFROMFLASH=n CONFIG_BOOT_COPYTORAM=n -CONFIG_BOOT_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y CONFIG_CUSTOM_STACK=n CONFIG_IDLETHREAD_STACKSIZE=1024 CONFIG_USERMAIN_STACKSIZE=2048 diff --git a/nuttx/configs/ubw32/README.txt b/nuttx/configs/ubw32/README.txt index 801be39a9..63cb1bb54 100644 --- a/nuttx/configs/ubw32/README.txt +++ b/nuttx/configs/ubw32/README.txt @@ -586,15 +586,26 @@ Where is one of the following: This configuration directory, performs a simple OS test using apps/examples/ostest. - Serial Output. - -------------- - The OS test produces all of its test output on the serial console. - This configuration has UART1 enabled as a serial console. + NOTES: + ------ + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: - TX -- J4 pin 31: U1TX/RF8 - RX -- J4 pin 30: U1RX/RF2 - GND -- J4 pin 40: GND - Vcc -- J4 pin 39: 5V + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Serial Output. + + The OS test produces all of its test output on the serial console. + This configuration has UART1 enabled as a serial console. + + TX -- J4 pin 31: U1TX/RF8 + RX -- J4 pin 30: U1RX/RF2 + GND -- J4 pin 40: GND + Vcc -- J4 pin 39: 5V nsh: ==== diff --git a/nuttx/configs/ubw32/nsh/Make.defs b/nuttx/configs/ubw32/nsh/Make.defs index ae0e44ae4..f393bbfdf 100644 --- a/nuttx/configs/ubw32/nsh/Make.defs +++ b/nuttx/configs/ubw32/nsh/Make.defs @@ -44,13 +44,13 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mknulldeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/nsh/ld.script}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps.sh ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/nsh/ld.script + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script endif CC = $(CROSSDEV)gcc diff --git a/nuttx/configs/ubw32/nsh/defconfig b/nuttx/configs/ubw32/nsh/defconfig index ad18c12b6..89afd5912 100644 --- a/nuttx/configs/ubw32/nsh/defconfig +++ b/nuttx/configs/ubw32/nsh/defconfig @@ -60,7 +60,7 @@ CONFIG_ARCH_DMA=n # Enable support for RAM-based functions # (If selected, then modifications are needed in ld.script as well) # -CONFIG_PIC32MX_RAMFUNCS=n +CONFIG_ARCH_RAMFUNCS=n # # Identify toolchain and linker options @@ -102,7 +102,6 @@ CONFIG_PIC32MX_ADC=n CONFIG_PIC32MX_CVR=n CONFIG_PIC32MX_CM1=n CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y CONFIG_PIC32MX_DDP=n CONFIG_PIC32MX_FLASH=n CONFIG_PIC32MX_BMX=n @@ -110,13 +109,6 @@ CONFIG_PIC32MX_DMA=n CONFIG_PIC32MX_CHE=n CONFIG_PIC32MX_USBDEV=n CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y # # PIC32MX Configuration Settings diff --git a/nuttx/configs/ubw32/nsh/ld.script b/nuttx/configs/ubw32/nsh/ld.script deleted file mode 100644 index 43e64a51b..000000000 --- a/nuttx/configs/ubw32/nsh/ld.script +++ /dev/null @@ -1,317 +0,0 @@ -/**************************************************************************** - * configs/ubw32/nsh/ld.script - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ -/* Memory Regions ***********************************************************/ - -MEMORY -{ - /* The PIC32MX460F512L has 512Kb of program FLASH at physical address - * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000 - */ - - kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 512K - - /* The PIC32MX460F512L has 12Kb of boot FLASH at physical address - * 0x1fc00000. The initial reset vector is in KSEG1, but all other - * accesses are in KSEG0. - * - * REGION PHYSICAL KSEG SIZE - * DESCRIPTION START ADDR (BYTES) - * ------------- ---------- ------ ---------------------- - * Exceptions:* - * Reset 0x1fc00000 KSEG1 512 512 - * TLB Refill 0x1fc00200 KSEG1 256 768 - * Cache Error 0x1fc00300 KSEG1 128 896 - * Others 0x1fc00380 KSEG1 128 1024 (1Kb) - * Interrupt 0x1fc00400 KSEG1 128 1152 - * JTAG 0x1fc00480 KSEG1 16 1168 - * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) - * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc02ff0 KSEG1 16 12288 (12Kb) - * - * Exceptions assume: - * - * STATUS: BEV=0/1 and EXL=0 - * CAUSE: IV=1 - * JTAG: ProbEn=0 - * And multi-vector support disabled - */ - - kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 - kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 - kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 - kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 - kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 - kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 - kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 - kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16 - - /* The PIC32MX460F512L has 32Kb of data memory at physical address - * 0x00000000. Since the PIC32MX has no data cache, this memory is - * always accessed through KSEG1. - * - * When used with MPLAB, we need to set aside 512 bytes of memory - * for use by MPLAB. - */ - - kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512 -} - -OUTPUT_FORMAT("elf32-tradlittlemips") -OUTPUT_ARCH(pic32mx) -ENTRY(__start) - -SECTIONS -{ - /* Boot FLASH sections */ - - .reset : - { - KEEP (*(.reset)) - } > kseg1_reset - - /* Exception handlers. The following is assumed: - * - * STATUS: BEV=1 and EXL=0 - * CAUSE: IV=1 - * JTAG: ProbEn=0 - * And multi-vector support disabled - * - * In that configuration, the vector locations become: - * - * Reset, Soft Reset bfc0:0000 - * TLB Refill bfc0:0200 - * Cache Error bfc0:0300 - * All others bfc0:0380 - * Interrupt bfc0:0400 - * EJTAG Debug bfc0:0480 - */ - - /* KSEG1 exception handler "trampolines" */ - - .gen_excpt : - { - KEEP (*(.gen_excpt)) - } > kseg1_genexcpt - - .ebase_excpt : - { - KEEP (*(.ebase_excpt)) - } > kseg1_ebexcpt - - .bev_excpt : - { - KEEP (*(.bev_excpt)) - } > kseg1_bevexcpt - - .int_excpt : - { - KEEP (*(.int_excpt)) - } > kseg1_intexcpt - - .dbg_excpt = ORIGIN(kseg1_dbgexcpt); - - .start : - { - /* KSEG0 Reset startup logic */ - - *(.start) - - /* KSEG0 exception handlers */ - - *(.nmi_handler) - *(.bev_handler) - *(.int_handler) - } > kseg0_bootmem - - .dbg_code = ORIGIN(kseg1_dbgcode); - - .devcfg : - { - KEEP (*(.devcfg)) - } > kseg1_devcfg - - /* Program FLASH sections */ - - .text : - { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.stub) - KEEP (*(.text.*personality*)) - *(.gnu.linkonce.t.*) - *(.gnu.warning) - *(.mips16.fn.*) - *(.mips16.call.*) - - /* Read-only data is included in the text section */ - - *(.rodata .rodata.*) - *(.rodata1) - *(.gnu.linkonce.r.*) - - /* Small initialized constant global and static data */ - - *(.sdata2 .sdata2.*) - *(.gnu.linkonce.s2.*) - - /* Uninitialized constant global and static data */ - - *(.sbss2 .sbss2.*) - *(.gnu.linkonce.sb2.*) - _etext = ABSOLUTE(.); - } > kseg0_progmem - - /* Initialization data begins here in progmem */ - - _data_loaddr = LOADADDR(.data); - - .eh_frame_hdr : { *(.eh_frame_hdr) } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - - /* RAM functions are positioned at the beginning of RAM so that - * they can be guaranteed to satisfy the 2Kb alignment requirement. - */ - -/* This causes failures if there are no RAM functions - .ramfunc ALIGN(2K) : - { - _sramfunc = ABSOLUTE(.); - *(.ramfunc .ramfunc.*) - _eramfunc = ABSOLUTE(.); - } > kseg1_datamem AT > kseg0_progmem - - _ramfunc_loadaddr = LOADADDR(.ramfunc); - _ramfunc_sizeof = SIZEOF(.ramfunc); - _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; - _bmxdudba_address = LENGTH(kseg1_datamem) ; - _bmxdupba_address = LENGTH(kseg1_datamem) ; -*/ - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - KEEP (*(.gnu.linkonce.d.*personality*)) - *(.data1) - } > kseg1_datamem AT > kseg0_progmem - - .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } - _gp = ALIGN(16) + 0x7FF0 ; - - .got : - { - *(.got.plt) *(.got) - } > kseg1_datamem AT > kseg0_progmem - - .sdata : - { - *(.sdata .sdata.* .gnu.linkonce.s.*) - } > kseg1_datamem AT > kseg0_progmem - - .lit8 : - { - *(.lit8) - } > kseg1_datamem AT > kseg0_progmem - - .lit4 : - { - *(.lit4) - _edata = ABSOLUTE(.); - } >kseg1_datamem AT>kseg0_progmem - - .sbss : - { - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } >kseg1_datamem - - .bss : - { - *(.dynbss) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > kseg1_datamem - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* DWARF debug sections */ - /* DWARF 1 */ - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* SGI/MIPS DWARF 2 extensions */ - - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /DISCARD/ : { *(.note.GNU-stack) } -} diff --git a/nuttx/configs/ubw32/ostest/Make.defs b/nuttx/configs/ubw32/ostest/Make.defs index 54276acf7..b46589913 100644 --- a/nuttx/configs/ubw32/ostest/Make.defs +++ b/nuttx/configs/ubw32/ostest/Make.defs @@ -44,13 +44,13 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mknulldeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps.sh ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script endif CC = $(CROSSDEV)gcc diff --git a/nuttx/configs/ubw32/ostest/appconfig b/nuttx/configs/ubw32/ostest/appconfig deleted file mode 100644 index 6278529fa..000000000 --- a/nuttx/configs/ubw32/ostest/appconfig +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################ -# configs/ubw32/ostest/appconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/ostest - diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig index 60322d4f6..3a387ab99 100644 --- a/nuttx/configs/ubw32/ostest/defconfig +++ b/nuttx/configs/ubw32/ostest/defconfig @@ -1,249 +1,334 @@ -############################################################################ -# configs/ubw32/ostest/defconfig -# -# Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="mips" -CONFIG_ARCH_MIPS=y -CONFIG_ARCH_MIPS32=y -CONFIG_ARCH_CHIP="pic32mx" -CONFIG_ARCH_CHIP_PIC32MX460F512L=y -CONFIG_ARCH_BOARD="ubw32" -CONFIG_ARCH_BOARD_UBW32=y -CONFIG_BOARD_LOOPSPERMSEC=8079 -CONFIG_DRAM_SIZE=32768 -CONFIG_DRAM_START=0xa0000000 -CONFIG_ARCH_NOINTC=n -CONFIG_ARCH_VECNOTIRQ=y -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set # -# Enable support for RAM-based functions -# (If selected, then modifications are needed in ld.script as well) +# Customize Header Files # -CONFIG_PIC32MX_RAMFUNCS=n +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set # -# Identify toolchain and linker options +# Debug Options # -CONFIG_PIC32MX_MICROCHIPW=n -CONFIG_PIC32MX_MICROCHIPL=n -CONFIG_PIC32MX_MICROCHIPW_LITE=y -CONFIG_PIC32MX_MICROCHIPL_LITE=n +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set # -# Individual subsystems can be enabled: +# System Type # +# CONFIG_ARCH_8051 is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +CONFIG_ARCH_MIPS=y +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="mips" +CONFIG_ARCH_FAMILY="mips32" +CONFIG_ARCH_CHIP="pic32mx" +CONFIG_BOARD_LOOPSPERMSEC=8079 +# CONFIG_ARCH_CALIBRATION is not set +# CONFIG_SERIAL_TERMIOS is not set +CONFIG_ARCH_CHIP_PIC32MX=y +CONFIG_ARCH_MIPS32=y -CONFIG_PIC32MX_WDT=n -CONFIG_PIC32MX_RTCC=n -CONFIG_PIC32MX_TIMER1=n -CONFIG_PIC32MX_TIMER2=n -CONFIG_PIC32MX_TIMER3=n -CONFIG_PIC32MX_TIMER4=n -CONFIG_PIC32MX_TIMER5=n -CONFIG_PIC32MX_IC1=n -CONFIG_PIC32MX_IC2=n -CONFIG_PIC32MX_IC3=n -CONFIG_PIC32MX_IC4=n -CONFIG_PIC32MX_IC5=n -CONFIG_PIC32MX_OC1=n -CONFIG_PIC32MX_OC2=n -CONFIG_PIC32MX_OC3=n -CONFIG_PIC32MX_OC4=n -CONFIG_PIC32MX_OC5=n -CONFIG_PIC32MX_I2C1=n -CONFIG_PIC32MX_I2C2=n -CONFIG_PIC32MX_SPI1=n -CONFIG_PIC32MX_SPI2=n +# +# MIPS32 Configuration Options +# +# CONFIG_MIPS32_TOOLCHAIN_GNU_ELF is not set +# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL is not set +# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_LITE is not set +# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW is not set +CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE=y +# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPOPENL is not set +# CONFIG_MIPS32_TOOLCHAIN_PINGUINOW is not set +# CONFIG_MIPS32_TOOLCHAIN_PINGUINOL is not set + +# +# PIC32MX Configuration Options +# +# CONFIG_ARCH_CHIP_PIC32MX110F016B is not set +# CONFIG_ARCH_CHIP_PIC32MX110F016C is not set +# CONFIG_ARCH_CHIP_PIC32MX110F016D is not set +# CONFIG_ARCH_CHIP_PIC32MX120F032B is not set +# CONFIG_ARCH_CHIP_PIC32MX120F032C is not set +# CONFIG_ARCH_CHIP_PIC32MX120F032D is not set +# CONFIG_ARCH_CHIP_PIC32MX130F064B is not set +# CONFIG_ARCH_CHIP_PIC32MX130F064C is not set +# CONFIG_ARCH_CHIP_PIC32MX130F064D is not set +# CONFIG_ARCH_CHIP_PIC32MX150F128B is not set +# CONFIG_ARCH_CHIP_PIC32MX150F128C is not set +# CONFIG_ARCH_CHIP_PIC32MX150F128D is not set +# CONFIG_ARCH_CHIP_PIC32MX210F016B is not set +# CONFIG_ARCH_CHIP_PIC32MX210F016C is not set +# CONFIG_ARCH_CHIP_PIC32MX210F016D is not set +# CONFIG_ARCH_CHIP_PIC32MX220F032B is not set +# CONFIG_ARCH_CHIP_PIC32MX220F032C is not set +# CONFIG_ARCH_CHIP_PIC32MX220F032D is not set +# CONFIG_ARCH_CHIP_PIC32MX230F064B is not set +# CONFIG_ARCH_CHIP_PIC32MX230F064C is not set +# CONFIG_ARCH_CHIP_PIC32MX230F064D is not set +# CONFIG_ARCH_CHIP_PIC32MX250F128B is not set +# CONFIG_ARCH_CHIP_PIC32MX250F128C is not set +# CONFIG_ARCH_CHIP_PIC32MX250F128D is not set +# CONFIG_ARCH_CHIP_PIC32MX320F032H is not set +# CONFIG_ARCH_CHIP_PIC32MX320F064H is not set +# CONFIG_ARCH_CHIP_PIC32MX320F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX320F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX340F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX340F256H is not set +# CONFIG_ARCH_CHIP_PIC32MX340F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX340F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX360F256L is not set +# CONFIG_ARCH_CHIP_PIC32MX360F512L is not set +# CONFIG_ARCH_CHIP_PIC32MX420F032H is not set +# CONFIG_ARCH_CHIP_PIC32MX440F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX440F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX440F256H is not set +# CONFIG_ARCH_CHIP_PIC32MX440F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX460F256L is not set +CONFIG_ARCH_CHIP_PIC32MX460F512L=y +# CONFIG_ARCH_CHIP_PIC32MX534F064H is not set +# CONFIG_ARCH_CHIP_PIC32MX534F064L is not set +# CONFIG_ARCH_CHIP_PIC32MX564F064H is not set +# CONFIG_ARCH_CHIP_PIC32MX564F064L is not set +# CONFIG_ARCH_CHIP_PIC32MX564F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX564F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX575F256H is not set +# CONFIG_ARCH_CHIP_PIC32MX575F256L is not set +# CONFIG_ARCH_CHIP_PIC32MX575F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX575F512L is not set +# CONFIG_ARCH_CHIP_PIC32MX664F064H is not set +# CONFIG_ARCH_CHIP_PIC32MX664F064L is not set +# CONFIG_ARCH_CHIP_PIC32MX664F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX664F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX675F256H is not set +# CONFIG_ARCH_CHIP_PIC32MX675F256L is not set +# CONFIG_ARCH_CHIP_PIC32MX675F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX675F512L is not set +# CONFIG_ARCH_CHIP_PIC32MX695F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX695F512L is not set +# CONFIG_ARCH_CHIP_PIC32MX764F128H is not set +# CONFIG_ARCH_CHIP_PIC32MX764F128L is not set +# CONFIG_ARCH_CHIP_PIC32MX775F256H is not set +# CONFIG_ARCH_CHIP_PIC32MX775F256L is not set +# CONFIG_ARCH_CHIP_PIC32MX775F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX775F512L is not set +# CONFIG_ARCH_CHIP_PIC32MX795F512H is not set +# CONFIG_ARCH_CHIP_PIC32MX795F512L is not set +CONFIG_ARCH_CHIP_PIC32MX4=y +# CONFIG_PIC32MX_MVEC is not set +CONFIG_PIC32MX_T1=y + +# +# PIC32MX Peripheral Support +# +# CONFIG_PIC32MX_WDT is not set +# CONFIG_PIC32MX_T2 is not set +# CONFIG_PIC32MX_T3 is not set +# CONFIG_PIC32MX_T4 is not set +# CONFIG_PIC32MX_T5 is not set +# CONFIG_PIC32MX_IC1 is not set +# CONFIG_PIC32MX_IC2 is not set +# CONFIG_PIC32MX_IC3 is not set +# CONFIG_PIC32MX_IC4 is not set +# CONFIG_PIC32MX_IC5 is not set +# CONFIG_PIC32MX_OC1 is not set +# CONFIG_PIC32MX_OC2 is not set +# CONFIG_PIC32MX_OC3 is not set +# CONFIG_PIC32MX_OC4 is not set +# CONFIG_PIC32MX_OC5 is not set +# CONFIG_PIC32MX_I2C1 is not set +# CONFIG_PIC32MX_I2C2 is not set +# CONFIG_PIC32MX_I2C3 is not set +# CONFIG_PIC32MX_I2C4 is not set +# CONFIG_PIC32MX_I2C5 is not set +# CONFIG_PIC32MX_SPI1 is not set +# CONFIG_PIC32MX_SPI2 is not set +# CONFIG_PIC32MX_SPI3 is not set +# CONFIG_PIC32MX_SPI4 is not set CONFIG_PIC32MX_UART1=y -CONFIG_PIC32MX_UART2=n -CONFIG_PIC32MX_PMP=n -CONFIG_PIC32MX_ADC=n -CONFIG_PIC32MX_CVR=n -CONFIG_PIC32MX_CM1=n -CONFIG_PIC32MX_CM2=n -CONFIG_PIC32MX_OSC=y -CONFIG_PIC32MX_DDP=n -CONFIG_PIC32MX_FLASH=n -CONFIG_PIC32MX_BMX=n -CONFIG_PIC32MX_DMA=n -CONFIG_PIC32MX_CHE=n -CONFIG_PIC32MX_USBDEV=n -CONFIG_PIC32MX_USBHOST=n -CONFIG_PIC32MX_IOPORTA=y -CONFIG_PIC32MX_IOPORTB=y -CONFIG_PIC32MX_IOPORTC=y -CONFIG_PIC32MX_IOPORTD=y -CONFIG_PIC32MX_IOPORTE=y -CONFIG_PIC32MX_IOPORTF=y -CONFIG_PIC32MX_IOPORTG=y - -# -# PIC32MX Configuration Settings +# CONFIG_PIC32MX_UART2 is not set +# CONFIG_PIC32MX_UART3 is not set +# CONFIG_PIC32MX_UART4 is not set +# CONFIG_PIC32MX_UART5 is not set +# CONFIG_PIC32MX_UART6 is not set +# CONFIG_PIC32MX_ADC is not set +# CONFIG_PIC32MX_PMP is not set +# CONFIG_PIC32MX_CM1 is not set +# CONFIG_PIC32MX_CM2 is not set +# CONFIG_PIC32MX_CM3 is not set +# CONFIG_PIC32MX_RTCC is not set +# CONFIG_PIC32MX_DMA is not set +# CONFIG_PIC32MX_FLASH is not set +# CONFIG_PIC32MX_USBDEV is not set +# CONFIG_PIC32MX_USBHOST is not set +# CONFIG_PIC32MX_CAN1 is not set +# CONFIG_PIC32MX_CAN2 is not set +# CONFIG_PIC32MX_ETHERNET is not set +# CONFIG_PIC32MX_CTMU is not set + +# +# PIC32MX Peripheral Interrupt Priorities +# +CONFIG_PIC32MX_CTPRIO=16 +CONFIG_PIC32MX_CS0PRIO=16 +CONFIG_PIC32MX_CS1PRIO=16 +CONFIG_PIC32MX_INT0PRIO=16 +CONFIG_PIC32MX_INT1PRIO=16 +CONFIG_PIC32MX_INT2PRIO=16 +CONFIG_PIC32MX_INT3PRIO=16 +CONFIG_PIC32MX_INT4PRIO=16 +CONFIG_PIC32MX_T1PRIO=16 +CONFIG_PIC32MX_UART1PRIO=16 + +# +# Device Configuration 0 (DEVCFG0) # CONFIG_PIC32MX_DEBUGGER=2 CONFIG_PIC32MX_ICESEL=1 +CONFIG_PIC32MX_PROGFLASHWP=0xff +CONFIG_PIC32MX_BOOTFLASHWP=1 +CONFIG_PIC32MX_CODEWP=1 # -# PIC32MX specific serial device driver settings +# Device Configuration 3 (DEVCFG3) # -CONFIG_UART1_SERIAL_CONSOLE=y -CONFIG_UART2_SERIAL_CONSOLE=n - -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 - -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 +CONFIG_PIC32MX_USBIDO=0 +CONFIG_PIC32MX_VBUSIO=0 +# CONFIG_PIC32MX_WDENABLE is not set +CONFIG_PIC32MX_FETHIO=1 +CONFIG_PIC32MX_FMIIEN=1 -CONFIG_UART1_BAUD=115200 -CONFIG_UART2_BAUD=115200 +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +CONFIG_ARCH_VECNOTIRQ=y +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +# CONFIG_ARCH_HAVE_VFORK is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 +# +# Board Settings +# +CONFIG_DRAM_START=0xa0000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 +# +# Board Selection +# +# CONFIG_ARCH_BOARD_PCBLOGICPIC32MX is not set +CONFIG_ARCH_BOARD_UBW32=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="ubw32" # -# General build options +# Common Board Options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=y -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=n +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y # -# General OS setup +# Board-Specific Options # -CONFIG_USER_ENTRYPOINT="ostest_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_SCHED=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=0 -CONFIG_SCHED_INSTRUMENTATION=n +# CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=4 CONFIG_START_DAY=26 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=y -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WORKQUEUE=n -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=17 -CONFIG_SCHED_WAITPID=n -CONFIG_SCHED_ATEXIT=n - -# -# Settings for nxflat -# -CONFIG_NXFLAT=n -CONFIG_NXFLAT_DUMPBUFFER=n -CONFIG_SYMTAB_ORDEREDBYNAME=y - -# -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. -# -# There are certain dependency relationships in these -# features. -# -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. -# -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_POLL=y # -# Misc libc settings -# -CONFIG_NOPRINTF_FIELDWIDTH=n - -# -# Allow for architecture optimized implementations -# -# The architecture can provide optimized versions of the -# following to improve system performance +# Signal Numbers # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 # # Sizes of configurable things (0 disables) @@ -254,9 +339,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -264,250 +346,299 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Filesystem configuration +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART1=y +CONFIG_MCU_SERIAL=y +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support # -CONFIG_FS_FAT=n -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n +# CONFIG_NET is not set # -# Maintain legacy build behavior (revisit) +# File Systems # -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +# +# File system configuration +# +# CONFIG_FS_RAMMAP is not set # -# SPI-based MMC/SD driver +# System Logging # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 +# CONFIG_SYSLOG is not set # -# Block driver buffering +# Graphics Support # -CONFIG_FS_READAHEAD=n -CONFIG_FS_WRITEBUFFER=n +# CONFIG_NX is not set # -# SDIO-based MMC/SD driver +# Memory Management # -CONFIG_SDIO_DMA=n -CONFIG_MMCSD_MMCSUPPORT=n -CONFIG_MMCSD_HAVECARDDETECT=n +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set # -# TCP/IP and UDP support via uIP +# Binary Formats # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y # -# UIP Network Utilities +# Library Routines # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 # -# USB Device Configuration +# Standard C Library Options # -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# USB Serial Device Configuration +# Non-standard Helper Functions # -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=5 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 +# CONFIG_LIB_KBDCODEC is not set # -# USB serial device class driver (Standard CDC ACM class) +# Basic CXX Support # -CONFIG_CDCACM=n -CONFIG_CDCACM_CONSOLE=n -#CONFIG_CDCACM_EP0MAXPACKET -CONFIG_CDCACM_EPINTIN=1 -#CONFIG_CDCACM_EPINTIN_FSSIZE -#CONFIG_CDCACM_EPINTIN_HSSIZE -CONFIG_CDCACM_EPBULKOUT=3 -#CONFIG_CDCACM_EPBULKOUT_FSSIZE -#CONFIG_CDCACM_EPBULKOUT_HSSIZE -CONFIG_CDCACM_EPBULKIN=2 -#CONFIG_CDCACM_EPBULKIN_FSSIZE -#CONFIG_CDCACM_EPBULKIN_HSSIZE -#CONFIG_CDCACM_NWRREQS -#CONFIG_CDCACM_NRDREQS -#CONFIG_CDCACM_VENDORID -#CONFIG_CDCACM_VENDORSTR -#CONFIG_CDCACM_PRODUCTID -#CONFIG_CDCACM_PRODUCTSTR -#CONFIG_CDCACM_RXBUFSIZE -#CONFIG_CDCACM_TXBUFSIZE +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set # -# USB Storage Device Configuration +# Application Configuration +# + # -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=1 -CONFIG_USBMSC_EPBULKIN=2 -CONFIG_USBMSC_NRDREQS=8 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=64 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y - -# -# Settings for examples/uip -# -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n - -# -# Settings for examples/nettest -# -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 - -# -# Settings for examples/ostest +# Built-In Applications # +# CONFIG_BUILTIN is not set + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set CONFIG_EXAMPLES_OSTEST_LOOPS=1 CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set # -# Settings for apps/nshlib +# Interpreters # -CONFIG_NSH_BUILTIN_APPS=n -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_ARCHINIT=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" # -# Architecture-specific NSH options +# Interpreters # -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set # -# Settings for examples/usbserial +# Network Utilities # -CONFIG_EXAMPLES_USBSERIAL_INONLY=n -CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n -CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n -CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set # -# Settings for examples/usbstorage +# ModBus # -CONFIG_EXAMPLES_USBMSC_NLUNS=1 -CONFIG_EXAMPLES_USBMSC_DEVMINOR1=0 -CONFIG_EXAMPLES_USBMSC_DEVPATH1="/dev/mmcsd0" -CONFIG_EXAMPLES_USBMSC_TRACEINIT=n -CONFIG_EXAMPLES_USBMSC_TRACECLASS=n -CONFIG_EXAMPLES_USBMSC_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBMSC_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBMSC_TRACEINTERRUPTS=n # -# Settings for examples/cdcacm +# FreeModbus # -# Configuration prequisites: +# CONFIG_MODBUS is not set + +# +# NSH Library # -CONFIG_EXAMPLES_CDCACM_DEVMINOR=0 -CONFIG_EXAMPLES_CDCACM_TRACEINIT=n -CONFIG_EXAMPLES_CDCACM_TRACECLASS=n -CONFIG_EXAMPLES_CDCACM_TRACETRANSFERS=n -CONFIG_EXAMPLES_CDCACM_TRACECONTROLLER=n -CONFIG_EXAMPLES_CDCACM_TRACEINTERRUPTS=n +# CONFIG_NSH_LIBRARY is not set # -# Stack and heap information +# NxWidgets/NxWM # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/ubw32/ostest/ld.script b/nuttx/configs/ubw32/ostest/ld.script deleted file mode 100644 index 3a64fff23..000000000 --- a/nuttx/configs/ubw32/ostest/ld.script +++ /dev/null @@ -1,317 +0,0 @@ -/**************************************************************************** - * configs/ubw32/ostest/ld.script - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ -/* Memory Regions ***********************************************************/ - -MEMORY -{ - /* The PIC32MX460F512L has 512Kb of program FLASH at physical address - * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000 - */ - - kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 512K - - /* The PIC32MX460F512L has 12Kb of boot FLASH at physical address - * 0x1fc00000. The initial reset vector is in KSEG1, but all other - * accesses are in KSEG0. - * - * REGION PHYSICAL KSEG SIZE - * DESCRIPTION START ADDR (BYTES) - * ------------- ---------- ------ ---------------------- - * Exceptions:* - * Reset 0x1fc00000 KSEG1 512 512 - * TLB Refill 0x1fc00200 KSEG1 256 768 - * Cache Error 0x1fc00300 KSEG1 128 896 - * Others 0x1fc00380 KSEG1 128 1024 (1Kb) - * Interrupt 0x1fc00400 KSEG1 128 1152 - * JTAG 0x1fc00480 KSEG1 16 1168 - * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) - * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc02ff0 KSEG1 16 12288 (12Kb) - * - * Exceptions assume: - * - * STATUS: BEV=0/1 and EXL=0 - * CAUSE: IV=1 - * JTAG: ProbEn=0 - * And multi-vector support disabled - */ - - kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 - kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 - kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 - kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 - kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 - kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 - kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 - kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16 - - /* The PIC32MX460F512L has 32Kb of data memory at physical address - * 0x00000000. Since the PIC32MX has no data cache, this memory is - * always accessed through KSEG1. - * - * When used with MPLAB, we need to set aside 512 bytes of memory - * for use by MPLAB. - */ - - kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512 -} - -OUTPUT_FORMAT("elf32-tradlittlemips") -OUTPUT_ARCH(pic32mx) -ENTRY(__start) - -SECTIONS -{ - /* Boot FLASH sections */ - - .reset : - { - KEEP (*(.reset)) - } > kseg1_reset - - /* Exception handlers. The following is assumed: - * - * STATUS: BEV=1 and EXL=0 - * CAUSE: IV=1 - * JTAG: ProbEn=0 - * And multi-vector support disabled - * - * In that configuration, the vector locations become: - * - * Reset, Soft Reset bfc0:0000 - * TLB Refill bfc0:0200 - * Cache Error bfc0:0300 - * All others bfc0:0380 - * Interrupt bfc0:0400 - * EJTAG Debug bfc0:0480 - */ - - /* KSEG1 exception handler "trampolines" */ - - .gen_excpt : - { - KEEP (*(.gen_excpt)) - } > kseg1_genexcpt - - .ebase_excpt : - { - KEEP (*(.ebase_excpt)) - } > kseg1_ebexcpt - - .bev_excpt : - { - KEEP (*(.bev_excpt)) - } > kseg1_bevexcpt - - .int_excpt : - { - KEEP (*(.int_excpt)) - } > kseg1_intexcpt - - .dbg_excpt = ORIGIN(kseg1_dbgexcpt); - - .start : - { - /* KSEG0 Reset startup logic */ - - *(.start) - - /* KSEG0 exception handlers */ - - *(.nmi_handler) - *(.bev_handler) - *(.int_handler) - } > kseg0_bootmem - - .dbg_code = ORIGIN(kseg1_dbgcode); - - .devcfg : - { - KEEP (*(.devcfg)) - } > kseg1_devcfg - - /* Program FLASH sections */ - - .text : - { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.stub) - KEEP (*(.text.*personality*)) - *(.gnu.linkonce.t.*) - *(.gnu.warning) - *(.mips16.fn.*) - *(.mips16.call.*) - - /* Read-only data is included in the text section */ - - *(.rodata .rodata.*) - *(.rodata1) - *(.gnu.linkonce.r.*) - - /* Small initialized constant global and static data */ - - *(.sdata2 .sdata2.*) - *(.gnu.linkonce.s2.*) - - /* Uninitialized constant global and static data */ - - *(.sbss2 .sbss2.*) - *(.gnu.linkonce.sb2.*) - _etext = ABSOLUTE(.); - } > kseg0_progmem - - /* Initialization data begins here in progmem */ - - _data_loaddr = LOADADDR(.data); - - .eh_frame_hdr : { *(.eh_frame_hdr) } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - - /* RAM functions are positioned at the beginning of RAM so that - * they can be guaranteed to satisfy the 2Kb alignment requirement. - */ - -/* This causes failures if there are no RAM functions - .ramfunc ALIGN(2K) : - { - _sramfunc = ABSOLUTE(.); - *(.ramfunc .ramfunc.*) - _eramfunc = ABSOLUTE(.); - } > kseg1_datamem AT > kseg0_progmem - - _ramfunc_loadaddr = LOADADDR(.ramfunc); - _ramfunc_sizeof = SIZEOF(.ramfunc); - _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; - _bmxdudba_address = LENGTH(kseg1_datamem) ; - _bmxdupba_address = LENGTH(kseg1_datamem) ; -*/ - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - KEEP (*(.gnu.linkonce.d.*personality*)) - *(.data1) - } > kseg1_datamem AT > kseg0_progmem - - .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } - _gp = ALIGN(16) + 0x7FF0 ; - - .got : - { - *(.got.plt) *(.got) - } > kseg1_datamem AT > kseg0_progmem - - .sdata : - { - *(.sdata .sdata.* .gnu.linkonce.s.*) - } > kseg1_datamem AT > kseg0_progmem - - .lit8 : - { - *(.lit8) - } > kseg1_datamem AT > kseg0_progmem - - .lit4 : - { - *(.lit4) - _edata = ABSOLUTE(.); - } >kseg1_datamem AT>kseg0_progmem - - .sbss : - { - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } >kseg1_datamem - - .bss : - { - *(.dynbss) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > kseg1_datamem - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* DWARF debug sections */ - /* DWARF 1 */ - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* SGI/MIPS DWARF 2 extensions */ - - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /DISCARD/ : { *(.note.GNU-stack) } -} diff --git a/nuttx/configs/ubw32/scripts/ld.script b/nuttx/configs/ubw32/scripts/ld.script new file mode 100644 index 000000000..c25820b11 --- /dev/null +++ b/nuttx/configs/ubw32/scripts/ld.script @@ -0,0 +1,317 @@ +/**************************************************************************** + * configs/ubw32/scripts/ld.script + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* Memory Regions ***********************************************************/ + +MEMORY +{ + /* The PIC32MX460F512L has 512Kb of program FLASH at physical address + * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000 + */ + + kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 512K + + /* The PIC32MX460F512L has 12Kb of boot FLASH at physical address + * 0x1fc00000. The initial reset vector is in KSEG1, but all other + * accesses are in KSEG0. + * + * REGION PHYSICAL KSEG SIZE + * DESCRIPTION START ADDR (BYTES) + * ------------- ---------- ------ ---------------------- + * Exceptions:* + * Reset 0x1fc00000 KSEG1 512 512 + * TLB Refill 0x1fc00200 KSEG1 256 768 + * Cache Error 0x1fc00300 KSEG1 128 896 + * Others 0x1fc00380 KSEG1 128 1024 (1Kb) + * Interrupt 0x1fc00400 KSEG1 128 1152 + * JTAG 0x1fc00480 KSEG1 16 1168 + * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) + * Debug code 0x1fc02000 KSEG1 4096-16 12272 + * DEVCFG3-0 0x1fc02ff0 KSEG1 16 12288 (12Kb) + * + * Exceptions assume: + * + * STATUS: BEV=0/1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + */ + + kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 + kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 + kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 + kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 + kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 + kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 + kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 + kseg1_devcfg (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16 + + /* The PIC32MX460F512L has 32Kb of data memory at physical address + * 0x00000000. Since the PIC32MX has no data cache, this memory is + * always accessed through KSEG1. + * + * When used with MPLAB, we need to set aside 512 bytes of memory + * for use by MPLAB. + */ + + kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512 +} + +OUTPUT_FORMAT("elf32-tradlittlemips") +OUTPUT_ARCH(pic32mx) +ENTRY(__start) + +SECTIONS +{ + /* Boot FLASH sections */ + + .reset : + { + KEEP (*(.reset)) + } > kseg1_reset + + /* Exception handlers. The following is assumed: + * + * STATUS: BEV=1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + * + * In that configuration, the vector locations become: + * + * Reset, Soft Reset bfc0:0000 + * TLB Refill bfc0:0200 + * Cache Error bfc0:0300 + * All others bfc0:0380 + * Interrupt bfc0:0400 + * EJTAG Debug bfc0:0480 + */ + + /* KSEG1 exception handler "trampolines" */ + + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg1_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg1_ebexcpt + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg1_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg1_intexcpt + + .dbg_excpt = ORIGIN(kseg1_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + } > kseg0_bootmem + + .dbg_code = ORIGIN(kseg1_dbgcode); + + .devcfg : + { + KEEP (*(.devcfg)) + } > kseg1_devcfg + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_progmem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + /* RAM functions are positioned at the beginning of RAM so that + * they can be guaranteed to satisfy the 2Kb alignment requirement. + */ + +/* This causes failures if there are no RAM functions + .ramfunc ALIGN(2K) : + { + _sramfunc = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfunc = ABSOLUTE(.); + } > kseg1_datamem AT > kseg0_progmem + + _ramfunc_loadaddr = LOADADDR(.ramfunc); + _ramfunc_sizeof = SIZEOF(.ramfunc); + _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; + _bmxdudba_address = LENGTH(kseg1_datamem) ; + _bmxdupba_address = LENGTH(kseg1_datamem) ; +*/ + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg1_datamem AT > kseg0_progmem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg1_datamem AT > kseg0_progmem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > kseg1_datamem AT > kseg0_progmem + + .lit8 : + { + *(.lit8) + } > kseg1_datamem AT > kseg0_progmem + + .lit4 : + { + *(.lit4) + _edata = ABSOLUTE(.); + } >kseg1_datamem AT>kseg0_progmem + + .sbss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >kseg1_datamem + + .bss : + { + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > kseg1_datamem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} -- cgit v1.2.3 From f55cabeb593496691293a330daa7c6a3d99eae2e Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 15 Jan 2013 00:03:58 +0000 Subject: Don't build drivers/mtd unless CONFIG_MTD is defined (Denis Carikli) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5519 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/configs/amber/hello/defconfig | 2 +- nuttx/configs/avr32dev1/nsh/defconfig | 2 +- nuttx/configs/avr32dev1/ostest/defconfig | 2 +- nuttx/configs/c5471evm/httpd/defconfig | 2 +- nuttx/configs/c5471evm/nettest/defconfig | 2 +- nuttx/configs/c5471evm/nsh/defconfig | 2 +- nuttx/configs/c5471evm/ostest/defconfig | 2 +- nuttx/configs/compal_e88/nsh_highram/defconfig | 2 +- nuttx/configs/compal_e99/nsh_compalram/defconfig | 2 +- nuttx/configs/compal_e99/nsh_highram/defconfig | 2 +- nuttx/configs/demo9s12ne64/ostest/defconfig | 2 +- nuttx/configs/ea3131/nsh/defconfig | 1 + nuttx/configs/ea3131/ostest/defconfig | 1 + nuttx/configs/ea3131/pgnsh/defconfig | 1 + nuttx/configs/ea3131/usbserial/defconfig | 1 + nuttx/configs/ea3131/usbstorage/defconfig | 1 + nuttx/configs/ea3152/ostest/defconfig | 1 + nuttx/configs/eagle100/httpd/defconfig | 2 +- nuttx/configs/eagle100/nettest/defconfig | 2 +- nuttx/configs/eagle100/nsh/defconfig | 2 +- nuttx/configs/eagle100/nxflat/defconfig | 2 +- nuttx/configs/eagle100/ostest/defconfig | 2 +- nuttx/configs/eagle100/thttpd/defconfig | 2 +- nuttx/configs/ekk-lm3s9b96/nsh/defconfig | 2 +- nuttx/configs/ekk-lm3s9b96/ostest/defconfig | 2 +- nuttx/configs/ez80f910200kitg/ostest/defconfig | 2 +- nuttx/configs/ez80f910200zco/dhcpd/defconfig | 2 +- nuttx/configs/ez80f910200zco/httpd/defconfig | 2 +- nuttx/configs/ez80f910200zco/nettest/defconfig | 2 +- nuttx/configs/ez80f910200zco/nsh/defconfig | 2 +- nuttx/configs/ez80f910200zco/ostest/defconfig | 2 +- nuttx/configs/ez80f910200zco/poll/defconfig | 2 +- nuttx/configs/hymini-stm32v/buttons/defconfig | 1 + nuttx/configs/hymini-stm32v/nsh/defconfig | 1 + nuttx/configs/hymini-stm32v/nsh2/defconfig | 1 + nuttx/configs/hymini-stm32v/nx/defconfig | 1 + nuttx/configs/hymini-stm32v/nxlines/defconfig | 1 + nuttx/configs/hymini-stm32v/usbserial/defconfig | 1 + nuttx/configs/hymini-stm32v/usbstorage/defconfig | 1 + nuttx/configs/kwikstik-k40/ostest/defconfig | 1 + nuttx/configs/lincoln60/nsh/defconfig | 2 +- nuttx/configs/lincoln60/ostest/defconfig | 2 +- nuttx/configs/lm3s6432-s2e/nsh/defconfig | 2 +- nuttx/configs/lm3s6432-s2e/ostest/defconfig | 2 +- nuttx/configs/lm3s6965-ek/nsh/defconfig | 2 +- nuttx/configs/lm3s6965-ek/ostest/defconfig | 2 +- nuttx/configs/lm3s8962-ek/nsh/defconfig | 2 +- nuttx/configs/lm3s8962-ek/nx/defconfig | 2 +- nuttx/configs/lm3s8962-ek/ostest/defconfig | 2 +- nuttx/configs/lpc4330-xplorer/nsh/defconfig | 1 + nuttx/configs/lpc4330-xplorer/ostest/defconfig | 1 + nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/nx/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig | 2 +- nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig | 2 +- nuttx/configs/m68332evb/defconfig | 2 +- nuttx/configs/mbed/hidkbd/defconfig | 2 +- nuttx/configs/mbed/nsh/defconfig | 2 +- nuttx/configs/mcu123-lpc214x/composite/defconfig | 2 +- nuttx/configs/mcu123-lpc214x/ostest/defconfig | 2 +- nuttx/configs/mcu123-lpc214x/usbserial/defconfig | 2 +- nuttx/configs/mcu123-lpc214x/usbstorage/defconfig | 2 +- nuttx/configs/micropendous3/hello/defconfig | 2 +- nuttx/configs/mirtoo/nsh/defconfig | 2 +- nuttx/configs/mirtoo/nxffs/defconfig | 2 +- nuttx/configs/mirtoo/ostest/defconfig | 2 +- nuttx/configs/mx1ads/ostest/defconfig | 2 +- nuttx/configs/ne64badge/ostest/defconfig | 2 +- nuttx/configs/ntosd-dm320/nettest/defconfig | 2 +- nuttx/configs/ntosd-dm320/nsh/defconfig | 2 +- nuttx/configs/ntosd-dm320/ostest/defconfig | 2 +- nuttx/configs/ntosd-dm320/poll/defconfig | 2 +- nuttx/configs/ntosd-dm320/thttpd/defconfig | 2 +- nuttx/configs/ntosd-dm320/udp/defconfig | 2 +- nuttx/configs/ntosd-dm320/uip/defconfig | 2 +- nuttx/configs/nucleus2g/nsh/defconfig | 2 +- nuttx/configs/nucleus2g/ostest/defconfig | 2 +- nuttx/configs/nucleus2g/usbserial/defconfig | 2 +- nuttx/configs/nucleus2g/usbstorage/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/ftpc/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nettest/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/nx/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/ostest/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/thttpd/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/usbserial/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig | 2 +- nuttx/configs/olimex-lpc2378/nsh/defconfig | 2 +- nuttx/configs/olimex-lpc2378/ostest/defconfig | 2 +- nuttx/configs/olimex-stm32-p107/nsh/defconfig | 1 + nuttx/configs/olimex-stm32-p107/ostest/defconfig | 1 + nuttx/configs/olimex-strp711/nettest/defconfig | 2 +- nuttx/configs/olimex-strp711/nsh/defconfig | 2 +- nuttx/configs/olimex-strp711/ostest/defconfig | 2 +- nuttx/configs/pcblogic-pic32mx/nsh/defconfig | 2 +- nuttx/configs/pcblogic-pic32mx/ostest/defconfig | 2 +- nuttx/configs/pic32-starterkit/nsh/defconfig | 2 +- nuttx/configs/pic32-starterkit/nsh2/defconfig | 2 +- nuttx/configs/pic32-starterkit/ostest/defconfig | 2 +- nuttx/configs/pic32mx7mmb/nsh/defconfig | 2 +- nuttx/configs/pic32mx7mmb/ostest/defconfig | 2 +- nuttx/configs/pjrc-8051/defconfig | 2 +- nuttx/configs/qemu-i486/nsh/defconfig | 2 +- nuttx/configs/qemu-i486/ostest/defconfig | 2 +- nuttx/configs/rgmp/arm/default/defconfig | 2 +- nuttx/configs/rgmp/arm/nsh/defconfig | 2 +- nuttx/configs/rgmp/x86/cxxtest/defconfig | 2 +- nuttx/configs/rgmp/x86/default/defconfig | 2 +- nuttx/configs/rgmp/x86/helloxx/defconfig | 2 +- nuttx/configs/rgmp/x86/nsh/defconfig | 2 +- nuttx/configs/sam3u-ek/knsh/defconfig | 1 + nuttx/configs/sam3u-ek/nsh/defconfig | 1 + nuttx/configs/sam3u-ek/nx/defconfig | 1 + nuttx/configs/sam3u-ek/ostest/defconfig | 1 + nuttx/configs/sam3u-ek/touchscreen/defconfig | 1 + nuttx/configs/sim/mount/defconfig | 8 -------- nuttx/configs/sim/nettest/defconfig | 8 -------- nuttx/configs/sim/nsh/defconfig | 8 -------- nuttx/configs/sim/nsh2/defconfig | 8 -------- nuttx/configs/sim/nx/defconfig | 8 -------- nuttx/configs/sim/nxffs/defconfig | 8 -------- nuttx/configs/sim/pashello/defconfig | 8 -------- nuttx/configs/sim/touchscreen/defconfig | 8 -------- nuttx/configs/skp16c26/ostest/defconfig | 3 ++- nuttx/configs/stm3210e-eval/RIDE/defconfig | 1 + nuttx/configs/stm3210e-eval/buttons/defconfig | 1 + nuttx/configs/stm3210e-eval/composite/defconfig | 1 + nuttx/configs/stm3210e-eval/nsh/defconfig | 1 + nuttx/configs/stm3210e-eval/nsh2/defconfig | 1 + nuttx/configs/stm3210e-eval/nx/defconfig | 1 + nuttx/configs/stm3210e-eval/nxconsole/defconfig | 1 + nuttx/configs/stm3210e-eval/nxlines/defconfig | 1 + nuttx/configs/stm3210e-eval/nxtext/defconfig | 1 + nuttx/configs/stm3210e-eval/ostest/defconfig | 1 + nuttx/configs/stm3210e-eval/pm/defconfig | 1 + nuttx/configs/stm3210e-eval/usbserial/defconfig | 1 + nuttx/configs/stm3210e-eval/usbstorage/defconfig | 1 + nuttx/configs/stm3220g-eval/dhcpd/defconfig | 1 + nuttx/configs/stm3220g-eval/nettest/defconfig | 1 + nuttx/configs/stm3220g-eval/nsh/defconfig | 1 + nuttx/configs/stm3220g-eval/nsh2/defconfig | 1 + nuttx/configs/stm3220g-eval/ostest/defconfig | 1 + nuttx/configs/stm3220g-eval/telnetd/defconfig | 1 + nuttx/configs/stm3240g-eval/dhcpd/defconfig | 1 + nuttx/configs/stm3240g-eval/nettest/defconfig | 1 + nuttx/configs/stm3240g-eval/nsh/defconfig | 1 + nuttx/configs/stm3240g-eval/nsh2/defconfig | 1 + nuttx/configs/stm3240g-eval/nxconsole/defconfig | 1 + nuttx/configs/stm3240g-eval/nxwm/defconfig | 1 + nuttx/configs/stm3240g-eval/ostest/defconfig | 1 + nuttx/configs/stm3240g-eval/telnetd/defconfig | 1 + nuttx/configs/stm3240g-eval/webserver/defconfig | 1 + nuttx/configs/stm32f4discovery/nsh/defconfig | 8 -------- nuttx/configs/stm32f4discovery/pm/defconfig | 8 -------- nuttx/configs/sure-pic32mx/nsh/defconfig | 2 +- nuttx/configs/sure-pic32mx/ostest/defconfig | 2 +- nuttx/configs/sure-pic32mx/usbnsh/defconfig | 2 +- nuttx/configs/teensy/hello/defconfig | 2 +- nuttx/configs/teensy/nsh/defconfig | 2 +- nuttx/configs/teensy/usbstorage/defconfig | 2 +- nuttx/configs/twr-k60n512/nsh/defconfig | 1 + nuttx/configs/twr-k60n512/ostest/defconfig | 1 + nuttx/configs/ubw32/nsh/defconfig | 2 +- nuttx/configs/us7032evb1/nsh/defconfig | 2 +- nuttx/configs/us7032evb1/ostest/defconfig | 2 +- nuttx/configs/vsn/nsh/defconfig | 1 + nuttx/drivers/mtd/Make.defs | 3 +++ 171 files changed, 164 insertions(+), 186 deletions(-) diff --git a/nuttx/configs/amber/hello/defconfig b/nuttx/configs/amber/hello/defconfig index 7e3d4ad70..8bdb55db4 100644 --- a/nuttx/configs/amber/hello/defconfig +++ b/nuttx/configs/amber/hello/defconfig @@ -226,7 +226,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/avr32dev1/nsh/defconfig b/nuttx/configs/avr32dev1/nsh/defconfig index acca1fbac..bd2f3703f 100755 --- a/nuttx/configs/avr32dev1/nsh/defconfig +++ b/nuttx/configs/avr32dev1/nsh/defconfig @@ -245,7 +245,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/avr32dev1/ostest/defconfig b/nuttx/configs/avr32dev1/ostest/defconfig index 084c66233..72d0c3ae3 100755 --- a/nuttx/configs/avr32dev1/ostest/defconfig +++ b/nuttx/configs/avr32dev1/ostest/defconfig @@ -245,7 +245,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/c5471evm/httpd/defconfig b/nuttx/configs/c5471evm/httpd/defconfig index 8f4bd6927..3280b7c16 100644 --- a/nuttx/configs/c5471evm/httpd/defconfig +++ b/nuttx/configs/c5471evm/httpd/defconfig @@ -265,4 +265,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/c5471evm/nettest/defconfig b/nuttx/configs/c5471evm/nettest/defconfig index 71065fc66..131e73f52 100644 --- a/nuttx/configs/c5471evm/nettest/defconfig +++ b/nuttx/configs/c5471evm/nettest/defconfig @@ -265,4 +265,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/c5471evm/nsh/defconfig b/nuttx/configs/c5471evm/nsh/defconfig index 3750f9e5d..49fc8f9d0 100644 --- a/nuttx/configs/c5471evm/nsh/defconfig +++ b/nuttx/configs/c5471evm/nsh/defconfig @@ -265,4 +265,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/c5471evm/ostest/defconfig b/nuttx/configs/c5471evm/ostest/defconfig index f4d7b8c36..13013a2bd 100644 --- a/nuttx/configs/c5471evm/ostest/defconfig +++ b/nuttx/configs/c5471evm/ostest/defconfig @@ -265,4 +265,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/compal_e88/nsh_highram/defconfig b/nuttx/configs/compal_e88/nsh_highram/defconfig index d67674f4e..a6868e869 100644 --- a/nuttx/configs/compal_e88/nsh_highram/defconfig +++ b/nuttx/configs/compal_e88/nsh_highram/defconfig @@ -284,4 +284,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/compal_e99/nsh_compalram/defconfig b/nuttx/configs/compal_e99/nsh_compalram/defconfig index e8c53947b..058dc2aa2 100644 --- a/nuttx/configs/compal_e99/nsh_compalram/defconfig +++ b/nuttx/configs/compal_e99/nsh_compalram/defconfig @@ -286,4 +286,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/compal_e99/nsh_highram/defconfig b/nuttx/configs/compal_e99/nsh_highram/defconfig index 1d405874e..ee1405ca5 100644 --- a/nuttx/configs/compal_e99/nsh_highram/defconfig +++ b/nuttx/configs/compal_e99/nsh_highram/defconfig @@ -330,4 +330,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/demo9s12ne64/ostest/defconfig b/nuttx/configs/demo9s12ne64/ostest/defconfig index 79224989f..3222b63ee 100755 --- a/nuttx/configs/demo9s12ne64/ostest/defconfig +++ b/nuttx/configs/demo9s12ne64/ostest/defconfig @@ -219,7 +219,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ea3131/nsh/defconfig b/nuttx/configs/ea3131/nsh/defconfig index 8c7b351af..43510fa59 100644 --- a/nuttx/configs/ea3131/nsh/defconfig +++ b/nuttx/configs/ea3131/nsh/defconfig @@ -225,6 +225,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/ea3131/ostest/defconfig b/nuttx/configs/ea3131/ostest/defconfig index 19838ceab..6da813d9e 100644 --- a/nuttx/configs/ea3131/ostest/defconfig +++ b/nuttx/configs/ea3131/ostest/defconfig @@ -225,6 +225,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/ea3131/pgnsh/defconfig b/nuttx/configs/ea3131/pgnsh/defconfig index 1cc2bec7e..2a9eeff93 100644 --- a/nuttx/configs/ea3131/pgnsh/defconfig +++ b/nuttx/configs/ea3131/pgnsh/defconfig @@ -268,6 +268,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/ea3131/usbserial/defconfig b/nuttx/configs/ea3131/usbserial/defconfig index a82f69877..40c0897f7 100644 --- a/nuttx/configs/ea3131/usbserial/defconfig +++ b/nuttx/configs/ea3131/usbserial/defconfig @@ -228,6 +228,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/ea3131/usbstorage/defconfig b/nuttx/configs/ea3131/usbstorage/defconfig index a957fb3ab..0659383a6 100644 --- a/nuttx/configs/ea3131/usbstorage/defconfig +++ b/nuttx/configs/ea3131/usbstorage/defconfig @@ -229,6 +229,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/ea3152/ostest/defconfig b/nuttx/configs/ea3152/ostest/defconfig index 6d0bb63f0..d4d978649 100644 --- a/nuttx/configs/ea3152/ostest/defconfig +++ b/nuttx/configs/ea3152/ostest/defconfig @@ -226,6 +226,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SDIO-based MMC/SD driver diff --git a/nuttx/configs/eagle100/httpd/defconfig b/nuttx/configs/eagle100/httpd/defconfig index bd0ac7664..bb6636445 100644 --- a/nuttx/configs/eagle100/httpd/defconfig +++ b/nuttx/configs/eagle100/httpd/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/eagle100/nettest/defconfig b/nuttx/configs/eagle100/nettest/defconfig index 9b1f616c6..8f969ee79 100644 --- a/nuttx/configs/eagle100/nettest/defconfig +++ b/nuttx/configs/eagle100/nettest/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/eagle100/nsh/defconfig b/nuttx/configs/eagle100/nsh/defconfig index 079bbc60e..ed1c7b074 100644 --- a/nuttx/configs/eagle100/nsh/defconfig +++ b/nuttx/configs/eagle100/nsh/defconfig @@ -223,7 +223,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/eagle100/nxflat/defconfig b/nuttx/configs/eagle100/nxflat/defconfig index 110f906cb..590a30516 100644 --- a/nuttx/configs/eagle100/nxflat/defconfig +++ b/nuttx/configs/eagle100/nxflat/defconfig @@ -227,7 +227,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/eagle100/ostest/defconfig b/nuttx/configs/eagle100/ostest/defconfig index 6d3b4ddad..229aec59c 100644 --- a/nuttx/configs/eagle100/ostest/defconfig +++ b/nuttx/configs/eagle100/ostest/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/eagle100/thttpd/defconfig b/nuttx/configs/eagle100/thttpd/defconfig index 2aca2582e..7e1282368 100644 --- a/nuttx/configs/eagle100/thttpd/defconfig +++ b/nuttx/configs/eagle100/thttpd/defconfig @@ -228,7 +228,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig index adb9bb5fa..0bf59edf4 100644 --- a/nuttx/configs/ekk-lm3s9b96/nsh/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/nsh/defconfig @@ -240,7 +240,7 @@ CONFIG_NFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig index 821502036..3ac3c066a 100644 --- a/nuttx/configs/ekk-lm3s9b96/ostest/defconfig +++ b/nuttx/configs/ekk-lm3s9b96/ostest/defconfig @@ -239,7 +239,7 @@ CONFIG_NFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ez80f910200kitg/ostest/defconfig b/nuttx/configs/ez80f910200kitg/ostest/defconfig index 80c9e682e..d86177828 100644 --- a/nuttx/configs/ez80f910200kitg/ostest/defconfig +++ b/nuttx/configs/ez80f910200kitg/ostest/defconfig @@ -222,7 +222,7 @@ CONFIG_MMCSD_MMCSUPPORT=y CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=20000000 -CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SDIO is not set # CONFIG_SDIO_MUXBUS is not set # CONFIG_MTD is not set # CONFIG_PIPES is not set diff --git a/nuttx/configs/ez80f910200zco/dhcpd/defconfig b/nuttx/configs/ez80f910200zco/dhcpd/defconfig index 95baadc13..043526165 100644 --- a/nuttx/configs/ez80f910200zco/dhcpd/defconfig +++ b/nuttx/configs/ez80f910200zco/dhcpd/defconfig @@ -209,7 +209,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ez80f910200zco/httpd/defconfig b/nuttx/configs/ez80f910200zco/httpd/defconfig index 6a910ee0b..329b97053 100644 --- a/nuttx/configs/ez80f910200zco/httpd/defconfig +++ b/nuttx/configs/ez80f910200zco/httpd/defconfig @@ -209,7 +209,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ez80f910200zco/nettest/defconfig b/nuttx/configs/ez80f910200zco/nettest/defconfig index 22cf35a0c..94eedae20 100644 --- a/nuttx/configs/ez80f910200zco/nettest/defconfig +++ b/nuttx/configs/ez80f910200zco/nettest/defconfig @@ -209,7 +209,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ez80f910200zco/nsh/defconfig b/nuttx/configs/ez80f910200zco/nsh/defconfig index 8ad3930ff..7b8f12a41 100644 --- a/nuttx/configs/ez80f910200zco/nsh/defconfig +++ b/nuttx/configs/ez80f910200zco/nsh/defconfig @@ -209,7 +209,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ez80f910200zco/ostest/defconfig b/nuttx/configs/ez80f910200zco/ostest/defconfig index 88c1b7279..e414cfcc1 100644 --- a/nuttx/configs/ez80f910200zco/ostest/defconfig +++ b/nuttx/configs/ez80f910200zco/ostest/defconfig @@ -225,7 +225,7 @@ CONFIG_MMCSD_MMCSUPPORT=y CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=20000000 -CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SDIO is not set # CONFIG_SDIO_MUXBUS is not set # CONFIG_MTD is not set # CONFIG_PIPES is not set diff --git a/nuttx/configs/ez80f910200zco/poll/defconfig b/nuttx/configs/ez80f910200zco/poll/defconfig index 82cea4fcf..23c9fe747 100644 --- a/nuttx/configs/ez80f910200zco/poll/defconfig +++ b/nuttx/configs/ez80f910200zco/poll/defconfig @@ -209,7 +209,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/buttons/defconfig b/nuttx/configs/hymini-stm32v/buttons/defconfig index e90ded32a..fc258df0c 100644 --- a/nuttx/configs/hymini-stm32v/buttons/defconfig +++ b/nuttx/configs/hymini-stm32v/buttons/defconfig @@ -277,6 +277,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/nsh/defconfig b/nuttx/configs/hymini-stm32v/nsh/defconfig index eeb3b09ff..5736aadc8 100755 --- a/nuttx/configs/hymini-stm32v/nsh/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh/defconfig @@ -274,6 +274,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/nsh2/defconfig b/nuttx/configs/hymini-stm32v/nsh2/defconfig index ecf4c3a3d..7183a8632 100644 --- a/nuttx/configs/hymini-stm32v/nsh2/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh2/defconfig @@ -308,6 +308,7 @@ CONFIG_FS_WRITEBUFFER=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # STM32 SDIO-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/nx/defconfig b/nuttx/configs/hymini-stm32v/nx/defconfig index c6e049142..4e522cfd8 100644 --- a/nuttx/configs/hymini-stm32v/nx/defconfig +++ b/nuttx/configs/hymini-stm32v/nx/defconfig @@ -291,6 +291,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/nxlines/defconfig b/nuttx/configs/hymini-stm32v/nxlines/defconfig index fb968c483..7d1e8b975 100644 --- a/nuttx/configs/hymini-stm32v/nxlines/defconfig +++ b/nuttx/configs/hymini-stm32v/nxlines/defconfig @@ -295,6 +295,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/usbserial/defconfig b/nuttx/configs/hymini-stm32v/usbserial/defconfig index 0c7317a00..b53a79dd8 100755 --- a/nuttx/configs/hymini-stm32v/usbserial/defconfig +++ b/nuttx/configs/hymini-stm32v/usbserial/defconfig @@ -277,6 +277,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/hymini-stm32v/usbstorage/defconfig b/nuttx/configs/hymini-stm32v/usbstorage/defconfig index 16f43a1ce..d89a33a03 100755 --- a/nuttx/configs/hymini-stm32v/usbstorage/defconfig +++ b/nuttx/configs/hymini-stm32v/usbstorage/defconfig @@ -284,6 +284,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/kwikstik-k40/ostest/defconfig b/nuttx/configs/kwikstik-k40/ostest/defconfig index ff8c39c1f..826af71b8 100755 --- a/nuttx/configs/kwikstik-k40/ostest/defconfig +++ b/nuttx/configs/kwikstik-k40/ostest/defconfig @@ -286,6 +286,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lincoln60/nsh/defconfig b/nuttx/configs/lincoln60/nsh/defconfig index 908b01e3a..abdea0c86 100644 --- a/nuttx/configs/lincoln60/nsh/defconfig +++ b/nuttx/configs/lincoln60/nsh/defconfig @@ -258,7 +258,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lincoln60/ostest/defconfig b/nuttx/configs/lincoln60/ostest/defconfig index ea42f5763..8ab244f0d 100644 --- a/nuttx/configs/lincoln60/ostest/defconfig +++ b/nuttx/configs/lincoln60/ostest/defconfig @@ -268,7 +268,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lm3s6432-s2e/nsh/defconfig b/nuttx/configs/lm3s6432-s2e/nsh/defconfig index a09bc6717..cb3bbdeb4 100644 --- a/nuttx/configs/lm3s6432-s2e/nsh/defconfig +++ b/nuttx/configs/lm3s6432-s2e/nsh/defconfig @@ -238,7 +238,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lm3s6432-s2e/ostest/defconfig b/nuttx/configs/lm3s6432-s2e/ostest/defconfig index 9387fd086..a3ec72422 100644 --- a/nuttx/configs/lm3s6432-s2e/ostest/defconfig +++ b/nuttx/configs/lm3s6432-s2e/ostest/defconfig @@ -237,7 +237,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lm3s6965-ek/nsh/defconfig b/nuttx/configs/lm3s6965-ek/nsh/defconfig index 5c288f95d..ccda5d9e8 100755 --- a/nuttx/configs/lm3s6965-ek/nsh/defconfig +++ b/nuttx/configs/lm3s6965-ek/nsh/defconfig @@ -280,7 +280,7 @@ CONFIG_MMCSD_MMCSUPPORT=y CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SDIO is not set # CONFIG_SDIO_MUXBUS is not set # CONFIG_MTD is not set # CONFIG_NETDEVICES is not set diff --git a/nuttx/configs/lm3s6965-ek/ostest/defconfig b/nuttx/configs/lm3s6965-ek/ostest/defconfig index 67633c916..7a1b0eb0a 100755 --- a/nuttx/configs/lm3s6965-ek/ostest/defconfig +++ b/nuttx/configs/lm3s6965-ek/ostest/defconfig @@ -259,7 +259,7 @@ CONFIG_MMCSD_MMCSUPPORT=y CONFIG_MMCSD_HAVECARDDETECT=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SDIO is not set # CONFIG_SDIO_MUXBUS is not set # CONFIG_MTD is not set # CONFIG_PIPES is not set diff --git a/nuttx/configs/lm3s8962-ek/nsh/defconfig b/nuttx/configs/lm3s8962-ek/nsh/defconfig index 4a35f8d4a..f49b977aa 100755 --- a/nuttx/configs/lm3s8962-ek/nsh/defconfig +++ b/nuttx/configs/lm3s8962-ek/nsh/defconfig @@ -238,7 +238,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lm3s8962-ek/nx/defconfig b/nuttx/configs/lm3s8962-ek/nx/defconfig index 3ca6ade21..b92bd8e95 100755 --- a/nuttx/configs/lm3s8962-ek/nx/defconfig +++ b/nuttx/configs/lm3s8962-ek/nx/defconfig @@ -252,7 +252,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lm3s8962-ek/ostest/defconfig b/nuttx/configs/lm3s8962-ek/ostest/defconfig index 169ac9c8f..cdf0477bc 100755 --- a/nuttx/configs/lm3s8962-ek/ostest/defconfig +++ b/nuttx/configs/lm3s8962-ek/ostest/defconfig @@ -237,7 +237,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpc4330-xplorer/nsh/defconfig b/nuttx/configs/lpc4330-xplorer/nsh/defconfig index 78b9e3f71..99c920078 100644 --- a/nuttx/configs/lpc4330-xplorer/nsh/defconfig +++ b/nuttx/configs/lpc4330-xplorer/nsh/defconfig @@ -330,6 +330,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig index 342fe04a0..fc853de17 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig +++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig @@ -327,6 +327,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 2e0d2eea6..824fcfb2c 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -270,7 +270,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig index 23f375a47..c11cf623f 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -266,7 +266,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig b/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig index 3f8474103..d4b3b8953 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/nx/defconfig @@ -283,7 +283,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig index 10b63eb2d..831b717b9 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/ostest/defconfig @@ -268,7 +268,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig b/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig index b6ea25948..299750371 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -270,7 +270,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig index 9e4bcb15d..fd055ee02 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig +++ b/nuttx/configs/lpcxpresso-lpc1768/usbstorage/defconfig @@ -264,7 +264,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/m68332evb/defconfig b/nuttx/configs/m68332evb/defconfig index 4c4020184..7e49073a9 100644 --- a/nuttx/configs/m68332evb/defconfig +++ b/nuttx/configs/m68332evb/defconfig @@ -216,4 +216,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/mbed/hidkbd/defconfig b/nuttx/configs/mbed/hidkbd/defconfig index b4bf00872..94b007355 100644 --- a/nuttx/configs/mbed/hidkbd/defconfig +++ b/nuttx/configs/mbed/hidkbd/defconfig @@ -263,7 +263,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mbed/nsh/defconfig b/nuttx/configs/mbed/nsh/defconfig index 2156af80e..40a230b52 100755 --- a/nuttx/configs/mbed/nsh/defconfig +++ b/nuttx/configs/mbed/nsh/defconfig @@ -258,7 +258,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mcu123-lpc214x/composite/defconfig b/nuttx/configs/mcu123-lpc214x/composite/defconfig index 04fbe2b9e..682facbab 100644 --- a/nuttx/configs/mcu123-lpc214x/composite/defconfig +++ b/nuttx/configs/mcu123-lpc214x/composite/defconfig @@ -199,7 +199,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mcu123-lpc214x/ostest/defconfig b/nuttx/configs/mcu123-lpc214x/ostest/defconfig index 9d59439be..7d0c50157 100644 --- a/nuttx/configs/mcu123-lpc214x/ostest/defconfig +++ b/nuttx/configs/mcu123-lpc214x/ostest/defconfig @@ -197,7 +197,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mcu123-lpc214x/usbserial/defconfig b/nuttx/configs/mcu123-lpc214x/usbserial/defconfig index 3097f7d78..c9f528c37 100644 --- a/nuttx/configs/mcu123-lpc214x/usbserial/defconfig +++ b/nuttx/configs/mcu123-lpc214x/usbserial/defconfig @@ -197,7 +197,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mcu123-lpc214x/usbstorage/defconfig b/nuttx/configs/mcu123-lpc214x/usbstorage/defconfig index 7b22bf6b0..4273315c6 100644 --- a/nuttx/configs/mcu123-lpc214x/usbstorage/defconfig +++ b/nuttx/configs/mcu123-lpc214x/usbstorage/defconfig @@ -199,7 +199,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/micropendous3/hello/defconfig b/nuttx/configs/micropendous3/hello/defconfig index ebc755abc..2708c5d52 100644 --- a/nuttx/configs/micropendous3/hello/defconfig +++ b/nuttx/configs/micropendous3/hello/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mirtoo/nsh/defconfig b/nuttx/configs/mirtoo/nsh/defconfig index 6e0d3bf70..9beaf6728 100644 --- a/nuttx/configs/mirtoo/nsh/defconfig +++ b/nuttx/configs/mirtoo/nsh/defconfig @@ -285,7 +285,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mirtoo/nxffs/defconfig b/nuttx/configs/mirtoo/nxffs/defconfig index ed50e0325..50929eb0e 100644 --- a/nuttx/configs/mirtoo/nxffs/defconfig +++ b/nuttx/configs/mirtoo/nxffs/defconfig @@ -285,7 +285,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mirtoo/ostest/defconfig b/nuttx/configs/mirtoo/ostest/defconfig index 5c8b69785..7c8596dbf 100644 --- a/nuttx/configs/mirtoo/ostest/defconfig +++ b/nuttx/configs/mirtoo/ostest/defconfig @@ -276,7 +276,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/mx1ads/ostest/defconfig b/nuttx/configs/mx1ads/ostest/defconfig index 54dbf6cce..d432b8469 100644 --- a/nuttx/configs/mx1ads/ostest/defconfig +++ b/nuttx/configs/mx1ads/ostest/defconfig @@ -328,4 +328,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ne64badge/ostest/defconfig b/nuttx/configs/ne64badge/ostest/defconfig index e6e0df700..a730c93eb 100755 --- a/nuttx/configs/ne64badge/ostest/defconfig +++ b/nuttx/configs/ne64badge/ostest/defconfig @@ -225,7 +225,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ntosd-dm320/nettest/defconfig b/nuttx/configs/ntosd-dm320/nettest/defconfig index dd2aff53c..ee70127e3 100644 --- a/nuttx/configs/ntosd-dm320/nettest/defconfig +++ b/nuttx/configs/ntosd-dm320/nettest/defconfig @@ -324,4 +324,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/nsh/defconfig b/nuttx/configs/ntosd-dm320/nsh/defconfig index 98de53fe0..83f0dde79 100644 --- a/nuttx/configs/ntosd-dm320/nsh/defconfig +++ b/nuttx/configs/ntosd-dm320/nsh/defconfig @@ -355,4 +355,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/ostest/defconfig b/nuttx/configs/ntosd-dm320/ostest/defconfig index 5d606453b..94a946db3 100644 --- a/nuttx/configs/ntosd-dm320/ostest/defconfig +++ b/nuttx/configs/ntosd-dm320/ostest/defconfig @@ -320,4 +320,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/poll/defconfig b/nuttx/configs/ntosd-dm320/poll/defconfig index e43eccce5..d80868883 100644 --- a/nuttx/configs/ntosd-dm320/poll/defconfig +++ b/nuttx/configs/ntosd-dm320/poll/defconfig @@ -331,4 +331,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/thttpd/defconfig b/nuttx/configs/ntosd-dm320/thttpd/defconfig index fbb6d644f..632e9a16e 100644 --- a/nuttx/configs/ntosd-dm320/thttpd/defconfig +++ b/nuttx/configs/ntosd-dm320/thttpd/defconfig @@ -399,4 +399,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/udp/defconfig b/nuttx/configs/ntosd-dm320/udp/defconfig index 5859279d0..3d79e75ac 100644 --- a/nuttx/configs/ntosd-dm320/udp/defconfig +++ b/nuttx/configs/ntosd-dm320/udp/defconfig @@ -332,4 +332,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/ntosd-dm320/uip/defconfig b/nuttx/configs/ntosd-dm320/uip/defconfig index 69387e7f6..6e08a3702 100644 --- a/nuttx/configs/ntosd-dm320/uip/defconfig +++ b/nuttx/configs/ntosd-dm320/uip/defconfig @@ -332,4 +332,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/nucleus2g/nsh/defconfig b/nuttx/configs/nucleus2g/nsh/defconfig index 2c440bc7f..8f3e50971 100755 --- a/nuttx/configs/nucleus2g/nsh/defconfig +++ b/nuttx/configs/nucleus2g/nsh/defconfig @@ -259,7 +259,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/nucleus2g/ostest/defconfig b/nuttx/configs/nucleus2g/ostest/defconfig index c32b1e715..8f6cc8ac1 100755 --- a/nuttx/configs/nucleus2g/ostest/defconfig +++ b/nuttx/configs/nucleus2g/ostest/defconfig @@ -258,7 +258,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/nucleus2g/usbserial/defconfig b/nuttx/configs/nucleus2g/usbserial/defconfig index abe9ac020..edd2160b4 100755 --- a/nuttx/configs/nucleus2g/usbserial/defconfig +++ b/nuttx/configs/nucleus2g/usbserial/defconfig @@ -259,7 +259,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/nucleus2g/usbstorage/defconfig b/nuttx/configs/nucleus2g/usbstorage/defconfig index adab8f4f0..8ea4614be 100755 --- a/nuttx/configs/nucleus2g/usbstorage/defconfig +++ b/nuttx/configs/nucleus2g/usbstorage/defconfig @@ -260,7 +260,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig index 8ff0d95aa..15b26899b 100755 --- a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig @@ -281,7 +281,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig index 634601187..fce1ed26f 100755 --- a/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -329,7 +329,7 @@ CONFIG_MMCSD_NSLOTS=1 # CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SDIO=y is not set # CONFIG_SDIO_MUXBUS is not set # CONFIG_MTD is not set # CONFIG_PIPES is not set diff --git a/nuttx/configs/olimex-lpc1766stk/nettest/defconfig b/nuttx/configs/olimex-lpc1766stk/nettest/defconfig index 4ab823b8c..5b6b3d676 100755 --- a/nuttx/configs/olimex-lpc1766stk/nettest/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nettest/defconfig @@ -273,7 +273,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index 096f08a8a..8ed82a3ed 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -285,7 +285,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/nx/defconfig b/nuttx/configs/olimex-lpc1766stk/nx/defconfig index 28ad229d6..f27acf40e 100755 --- a/nuttx/configs/olimex-lpc1766stk/nx/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nx/defconfig @@ -286,7 +286,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/ostest/defconfig b/nuttx/configs/olimex-lpc1766stk/ostest/defconfig index 02732e74a..f341a49c4 100755 --- a/nuttx/configs/olimex-lpc1766stk/ostest/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/ostest/defconfig @@ -268,7 +268,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig b/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig index 9becdee04..259457cf6 100755 --- a/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -278,7 +278,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig b/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig index fe42a861f..f684dcde3 100755 --- a/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/thttpd/defconfig @@ -276,7 +276,7 @@ CONFIG_FS_ROMFS=y CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig b/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig index 995cbad59..122e61485 100755 --- a/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/usbserial/defconfig @@ -269,7 +269,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig b/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig index e11c2c404..51743e020 100755 --- a/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/usbstorage/defconfig @@ -270,7 +270,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc2378/nsh/defconfig b/nuttx/configs/olimex-lpc2378/nsh/defconfig index fcddbaaca..c6728adb7 100755 --- a/nuttx/configs/olimex-lpc2378/nsh/defconfig +++ b/nuttx/configs/olimex-lpc2378/nsh/defconfig @@ -214,7 +214,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-lpc2378/ostest/defconfig b/nuttx/configs/olimex-lpc2378/ostest/defconfig index b7216c7c4..01e1918fd 100755 --- a/nuttx/configs/olimex-lpc2378/ostest/defconfig +++ b/nuttx/configs/olimex-lpc2378/ostest/defconfig @@ -214,7 +214,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-stm32-p107/nsh/defconfig b/nuttx/configs/olimex-stm32-p107/nsh/defconfig index 0a831ce9f..09d447e14 100644 --- a/nuttx/configs/olimex-stm32-p107/nsh/defconfig +++ b/nuttx/configs/olimex-stm32-p107/nsh/defconfig @@ -316,6 +316,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-stm32-p107/ostest/defconfig b/nuttx/configs/olimex-stm32-p107/ostest/defconfig index 272832381..6bc065784 100644 --- a/nuttx/configs/olimex-stm32-p107/ostest/defconfig +++ b/nuttx/configs/olimex-stm32-p107/ostest/defconfig @@ -324,6 +324,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-strp711/nettest/defconfig b/nuttx/configs/olimex-strp711/nettest/defconfig index a8767c7be..bc95f0c02 100755 --- a/nuttx/configs/olimex-strp711/nettest/defconfig +++ b/nuttx/configs/olimex-strp711/nettest/defconfig @@ -248,7 +248,7 @@ CONFIG_ENC28J60_HALFDUPPLEX=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-strp711/nsh/defconfig b/nuttx/configs/olimex-strp711/nsh/defconfig index b621945ed..886498eae 100644 --- a/nuttx/configs/olimex-strp711/nsh/defconfig +++ b/nuttx/configs/olimex-strp711/nsh/defconfig @@ -231,7 +231,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/olimex-strp711/ostest/defconfig b/nuttx/configs/olimex-strp711/ostest/defconfig index 02804cd67..b5621315a 100644 --- a/nuttx/configs/olimex-strp711/ostest/defconfig +++ b/nuttx/configs/olimex-strp711/ostest/defconfig @@ -231,7 +231,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig index 6f1ef7dc9..fe24cb886 100644 --- a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig @@ -273,7 +273,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig index 1df428f8a..19196eae9 100644 --- a/nuttx/configs/pcblogic-pic32mx/ostest/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/ostest/defconfig @@ -263,7 +263,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index f1c543e5f..8bf0432e2 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -356,7 +356,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig index f681b7689..fb54a2949 100644 --- a/nuttx/configs/pic32-starterkit/nsh2/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig @@ -355,7 +355,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pic32-starterkit/ostest/defconfig b/nuttx/configs/pic32-starterkit/ostest/defconfig index 6a077f209..39f7d04af 100644 --- a/nuttx/configs/pic32-starterkit/ostest/defconfig +++ b/nuttx/configs/pic32-starterkit/ostest/defconfig @@ -353,7 +353,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig index 66cd240e2..62f524ee2 100644 --- a/nuttx/configs/pic32mx7mmb/nsh/defconfig +++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig @@ -371,7 +371,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pic32mx7mmb/ostest/defconfig b/nuttx/configs/pic32mx7mmb/ostest/defconfig index 7cb71995e..4595913cd 100644 --- a/nuttx/configs/pic32mx7mmb/ostest/defconfig +++ b/nuttx/configs/pic32mx7mmb/ostest/defconfig @@ -353,7 +353,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/pjrc-8051/defconfig b/nuttx/configs/pjrc-8051/defconfig index b41d74e31..43c2347a9 100644 --- a/nuttx/configs/pjrc-8051/defconfig +++ b/nuttx/configs/pjrc-8051/defconfig @@ -215,4 +215,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/qemu-i486/nsh/defconfig b/nuttx/configs/qemu-i486/nsh/defconfig index 792157fe0..09e252e0b 100644 --- a/nuttx/configs/qemu-i486/nsh/defconfig +++ b/nuttx/configs/qemu-i486/nsh/defconfig @@ -316,4 +316,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/qemu-i486/ostest/defconfig b/nuttx/configs/qemu-i486/ostest/defconfig index b0036289a..aeae97df1 100644 --- a/nuttx/configs/qemu-i486/ostest/defconfig +++ b/nuttx/configs/qemu-i486/ostest/defconfig @@ -232,4 +232,4 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y diff --git a/nuttx/configs/rgmp/arm/default/defconfig b/nuttx/configs/rgmp/arm/default/defconfig index 0c40e8bd2..88843e365 100644 --- a/nuttx/configs/rgmp/arm/default/defconfig +++ b/nuttx/configs/rgmp/arm/default/defconfig @@ -226,7 +226,7 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y ########################################## # RGMP specific configuration diff --git a/nuttx/configs/rgmp/arm/nsh/defconfig b/nuttx/configs/rgmp/arm/nsh/defconfig index 0ae14b141..47c685aae 100644 --- a/nuttx/configs/rgmp/arm/nsh/defconfig +++ b/nuttx/configs/rgmp/arm/nsh/defconfig @@ -227,7 +227,7 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y ########################################## # RGMP specific configuration diff --git a/nuttx/configs/rgmp/x86/cxxtest/defconfig b/nuttx/configs/rgmp/x86/cxxtest/defconfig index 1d2996557..b1634e1e5 100644 --- a/nuttx/configs/rgmp/x86/cxxtest/defconfig +++ b/nuttx/configs/rgmp/x86/cxxtest/defconfig @@ -332,7 +332,7 @@ CONFIG_NET_RESOLV_ENTRIES=4 CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # Settings for examples/uip diff --git a/nuttx/configs/rgmp/x86/default/defconfig b/nuttx/configs/rgmp/x86/default/defconfig index 070ffcb30..383e0ff5f 100644 --- a/nuttx/configs/rgmp/x86/default/defconfig +++ b/nuttx/configs/rgmp/x86/default/defconfig @@ -187,7 +187,7 @@ CONFIG_NET_RESOLV_ENTRIES=4 CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # Settings for examples/uip diff --git a/nuttx/configs/rgmp/x86/helloxx/defconfig b/nuttx/configs/rgmp/x86/helloxx/defconfig index c8400560a..159195224 100644 --- a/nuttx/configs/rgmp/x86/helloxx/defconfig +++ b/nuttx/configs/rgmp/x86/helloxx/defconfig @@ -394,7 +394,7 @@ CONFIG_USER_ENTRYPOINT="helloxx_main" CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # uClibc++ Standard C++ Library diff --git a/nuttx/configs/rgmp/x86/nsh/defconfig b/nuttx/configs/rgmp/x86/nsh/defconfig index 891d58ba8..6f10b234a 100644 --- a/nuttx/configs/rgmp/x86/nsh/defconfig +++ b/nuttx/configs/rgmp/x86/nsh/defconfig @@ -236,7 +236,7 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y ########################################## # RGMP specific configuration diff --git a/nuttx/configs/sam3u-ek/knsh/defconfig b/nuttx/configs/sam3u-ek/knsh/defconfig index 30f60f0e3..709c3e785 100755 --- a/nuttx/configs/sam3u-ek/knsh/defconfig +++ b/nuttx/configs/sam3u-ek/knsh/defconfig @@ -274,6 +274,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sam3u-ek/nsh/defconfig b/nuttx/configs/sam3u-ek/nsh/defconfig index 971598464..38520a9aa 100755 --- a/nuttx/configs/sam3u-ek/nsh/defconfig +++ b/nuttx/configs/sam3u-ek/nsh/defconfig @@ -249,6 +249,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sam3u-ek/nx/defconfig b/nuttx/configs/sam3u-ek/nx/defconfig index dd55d9c93..a21a6570d 100755 --- a/nuttx/configs/sam3u-ek/nx/defconfig +++ b/nuttx/configs/sam3u-ek/nx/defconfig @@ -258,6 +258,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sam3u-ek/ostest/defconfig b/nuttx/configs/sam3u-ek/ostest/defconfig index bf15cb1a5..5125f5ba9 100755 --- a/nuttx/configs/sam3u-ek/ostest/defconfig +++ b/nuttx/configs/sam3u-ek/ostest/defconfig @@ -250,6 +250,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sam3u-ek/touchscreen/defconfig b/nuttx/configs/sam3u-ek/touchscreen/defconfig index 414eadb6e..278c55478 100755 --- a/nuttx/configs/sam3u-ek/touchscreen/defconfig +++ b/nuttx/configs/sam3u-ek/touchscreen/defconfig @@ -283,6 +283,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sim/mount/defconfig b/nuttx/configs/sim/mount/defconfig index d5e108782..7caa87852 100644 --- a/nuttx/configs/sim/mount/defconfig +++ b/nuttx/configs/sim/mount/defconfig @@ -223,11 +223,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/nettest/defconfig b/nuttx/configs/sim/nettest/defconfig index 1df980ea8..c216e2edc 100644 --- a/nuttx/configs/sim/nettest/defconfig +++ b/nuttx/configs/sim/nettest/defconfig @@ -222,11 +222,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index 2d627a66d..794b3107d 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -267,11 +267,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/nsh2/defconfig b/nuttx/configs/sim/nsh2/defconfig index c9e5b343f..b7e31b9e3 100644 --- a/nuttx/configs/sim/nsh2/defconfig +++ b/nuttx/configs/sim/nsh2/defconfig @@ -369,11 +369,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/nx/defconfig b/nuttx/configs/sim/nx/defconfig index 714d5dbb6..0fddca096 100644 --- a/nuttx/configs/sim/nx/defconfig +++ b/nuttx/configs/sim/nx/defconfig @@ -323,11 +323,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/nxffs/defconfig b/nuttx/configs/sim/nxffs/defconfig index c8aadee25..79f5b0f93 100644 --- a/nuttx/configs/sim/nxffs/defconfig +++ b/nuttx/configs/sim/nxffs/defconfig @@ -232,11 +232,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/pashello/defconfig b/nuttx/configs/sim/pashello/defconfig index fedf401d8..b40ec626e 100644 --- a/nuttx/configs/sim/pashello/defconfig +++ b/nuttx/configs/sim/pashello/defconfig @@ -211,11 +211,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/sim/touchscreen/defconfig b/nuttx/configs/sim/touchscreen/defconfig index df2a0553c..6a2e3e304 100644 --- a/nuttx/configs/sim/touchscreen/defconfig +++ b/nuttx/configs/sim/touchscreen/defconfig @@ -318,11 +318,3 @@ CONFIG_PTHREAD_STACK_MIN=256 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= - -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y diff --git a/nuttx/configs/skp16c26/ostest/defconfig b/nuttx/configs/skp16c26/ostest/defconfig index cf93d5b10..40ff5b3a1 100644 --- a/nuttx/configs/skp16c26/ostest/defconfig +++ b/nuttx/configs/skp16c26/ostest/defconfig @@ -324,4 +324,5 @@ CONFIG_HEAP_SIZE= CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y + diff --git a/nuttx/configs/stm3210e-eval/RIDE/defconfig b/nuttx/configs/stm3210e-eval/RIDE/defconfig index 6d84e7c36..662537a9d 100755 --- a/nuttx/configs/stm3210e-eval/RIDE/defconfig +++ b/nuttx/configs/stm3210e-eval/RIDE/defconfig @@ -282,6 +282,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/buttons/defconfig b/nuttx/configs/stm3210e-eval/buttons/defconfig index 37e19171f..3c8fca222 100644 --- a/nuttx/configs/stm3210e-eval/buttons/defconfig +++ b/nuttx/configs/stm3210e-eval/buttons/defconfig @@ -293,6 +293,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/composite/defconfig b/nuttx/configs/stm3210e-eval/composite/defconfig index 7fee33794..b5c39f928 100755 --- a/nuttx/configs/stm3210e-eval/composite/defconfig +++ b/nuttx/configs/stm3210e-eval/composite/defconfig @@ -299,6 +299,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nsh/defconfig b/nuttx/configs/stm3210e-eval/nsh/defconfig index b5e52e494..12ebc34c2 100755 --- a/nuttx/configs/stm3210e-eval/nsh/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh/defconfig @@ -290,6 +290,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nsh2/defconfig b/nuttx/configs/stm3210e-eval/nsh2/defconfig index 30a0bb327..063307143 100644 --- a/nuttx/configs/stm3210e-eval/nsh2/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh2/defconfig @@ -355,6 +355,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nx/defconfig b/nuttx/configs/stm3210e-eval/nx/defconfig index 0ad42dfbe..bff031617 100644 --- a/nuttx/configs/stm3210e-eval/nx/defconfig +++ b/nuttx/configs/stm3210e-eval/nx/defconfig @@ -307,6 +307,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nxconsole/defconfig b/nuttx/configs/stm3210e-eval/nxconsole/defconfig index 7dd5878bf..94dbf500f 100644 --- a/nuttx/configs/stm3210e-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3210e-eval/nxconsole/defconfig @@ -308,6 +308,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nxlines/defconfig b/nuttx/configs/stm3210e-eval/nxlines/defconfig index 068a17acb..760b3a6e1 100644 --- a/nuttx/configs/stm3210e-eval/nxlines/defconfig +++ b/nuttx/configs/stm3210e-eval/nxlines/defconfig @@ -307,6 +307,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/nxtext/defconfig b/nuttx/configs/stm3210e-eval/nxtext/defconfig index b6f88a3ca..d8b1fbe1e 100644 --- a/nuttx/configs/stm3210e-eval/nxtext/defconfig +++ b/nuttx/configs/stm3210e-eval/nxtext/defconfig @@ -307,6 +307,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/ostest/defconfig b/nuttx/configs/stm3210e-eval/ostest/defconfig index 0553b1a98..eb14399ea 100755 --- a/nuttx/configs/stm3210e-eval/ostest/defconfig +++ b/nuttx/configs/stm3210e-eval/ostest/defconfig @@ -302,6 +302,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/pm/defconfig b/nuttx/configs/stm3210e-eval/pm/defconfig index 61bd995c8..c113ddf60 100644 --- a/nuttx/configs/stm3210e-eval/pm/defconfig +++ b/nuttx/configs/stm3210e-eval/pm/defconfig @@ -386,6 +386,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/usbserial/defconfig b/nuttx/configs/stm3210e-eval/usbserial/defconfig index 94059c07c..c1f935e96 100755 --- a/nuttx/configs/stm3210e-eval/usbserial/defconfig +++ b/nuttx/configs/stm3210e-eval/usbserial/defconfig @@ -292,6 +292,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3210e-eval/usbstorage/defconfig b/nuttx/configs/stm3210e-eval/usbstorage/defconfig index 5c1ed5fb2..3e7119353 100755 --- a/nuttx/configs/stm3210e-eval/usbstorage/defconfig +++ b/nuttx/configs/stm3210e-eval/usbstorage/defconfig @@ -299,6 +299,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/dhcpd/defconfig b/nuttx/configs/stm3220g-eval/dhcpd/defconfig index 29baf9af0..627136ebb 100644 --- a/nuttx/configs/stm3220g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3220g-eval/dhcpd/defconfig @@ -363,6 +363,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/nettest/defconfig b/nuttx/configs/stm3220g-eval/nettest/defconfig index 08e04ad0e..39c1bb8ed 100644 --- a/nuttx/configs/stm3220g-eval/nettest/defconfig +++ b/nuttx/configs/stm3220g-eval/nettest/defconfig @@ -363,6 +363,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/nsh/defconfig b/nuttx/configs/stm3220g-eval/nsh/defconfig index bd9d02860..8486c4fd6 100644 --- a/nuttx/configs/stm3220g-eval/nsh/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh/defconfig @@ -409,6 +409,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/nsh2/defconfig b/nuttx/configs/stm3220g-eval/nsh2/defconfig index b5fe843bc..bc641b8be 100644 --- a/nuttx/configs/stm3220g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh2/defconfig @@ -408,6 +408,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/ostest/defconfig b/nuttx/configs/stm3220g-eval/ostest/defconfig index f63f96c9a..3ec417516 100644 --- a/nuttx/configs/stm3220g-eval/ostest/defconfig +++ b/nuttx/configs/stm3220g-eval/ostest/defconfig @@ -353,6 +353,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3220g-eval/telnetd/defconfig b/nuttx/configs/stm3220g-eval/telnetd/defconfig index f529198f1..b89e7d4f7 100644 --- a/nuttx/configs/stm3220g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3220g-eval/telnetd/defconfig @@ -363,6 +363,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/dhcpd/defconfig b/nuttx/configs/stm3240g-eval/dhcpd/defconfig index 5199cf85c..91682111b 100644 --- a/nuttx/configs/stm3240g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3240g-eval/dhcpd/defconfig @@ -369,6 +369,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/nettest/defconfig b/nuttx/configs/stm3240g-eval/nettest/defconfig index c5e0da795..257a4d252 100644 --- a/nuttx/configs/stm3240g-eval/nettest/defconfig +++ b/nuttx/configs/stm3240g-eval/nettest/defconfig @@ -369,6 +369,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig index 6c19ed531..82caf1622 100644 --- a/nuttx/configs/stm3240g-eval/nsh/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh/defconfig @@ -414,6 +414,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/nsh2/defconfig b/nuttx/configs/stm3240g-eval/nsh2/defconfig index 08690ade3..9e7d57ade 100644 --- a/nuttx/configs/stm3240g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh2/defconfig @@ -414,6 +414,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/nxconsole/defconfig b/nuttx/configs/stm3240g-eval/nxconsole/defconfig index 202fa4378..92c3ceb75 100644 --- a/nuttx/configs/stm3240g-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3240g-eval/nxconsole/defconfig @@ -413,6 +413,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/nxwm/defconfig b/nuttx/configs/stm3240g-eval/nxwm/defconfig index a220af2d1..34eaa9ec6 100644 --- a/nuttx/configs/stm3240g-eval/nxwm/defconfig +++ b/nuttx/configs/stm3240g-eval/nxwm/defconfig @@ -415,6 +415,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig index fcc54aa4b..f9e690a10 100644 --- a/nuttx/configs/stm3240g-eval/ostest/defconfig +++ b/nuttx/configs/stm3240g-eval/ostest/defconfig @@ -358,6 +358,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/telnetd/defconfig b/nuttx/configs/stm3240g-eval/telnetd/defconfig index 5aef41c27..ec04476b7 100644 --- a/nuttx/configs/stm3240g-eval/telnetd/defconfig +++ b/nuttx/configs/stm3240g-eval/telnetd/defconfig @@ -369,6 +369,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm3240g-eval/webserver/defconfig b/nuttx/configs/stm3240g-eval/webserver/defconfig index 6d09968e9..792eafa0a 100644 --- a/nuttx/configs/stm3240g-eval/webserver/defconfig +++ b/nuttx/configs/stm3240g-eval/webserver/defconfig @@ -414,6 +414,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/stm32f4discovery/nsh/defconfig b/nuttx/configs/stm32f4discovery/nsh/defconfig index 98034e22e..d9917b3a8 100644 --- a/nuttx/configs/stm32f4discovery/nsh/defconfig +++ b/nuttx/configs/stm32f4discovery/nsh/defconfig @@ -376,14 +376,6 @@ CONFIG_FAT_MAXFNAME=32 CONFIG_FS_NXFFS=n CONFIG_FS_ROMFS=n -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y - # # SPI-based MMC/SD driver # diff --git a/nuttx/configs/stm32f4discovery/pm/defconfig b/nuttx/configs/stm32f4discovery/pm/defconfig index 3e24168cd..1636f6ecb 100644 --- a/nuttx/configs/stm32f4discovery/pm/defconfig +++ b/nuttx/configs/stm32f4discovery/pm/defconfig @@ -395,14 +395,6 @@ CONFIG_FAT_MAXFNAME=32 CONFIG_FS_NXFFS=n CONFIG_FS_ROMFS=n -# -# Maintain legacy build behavior (revisit) -# - -CONFIG_MMCSD=y -CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y - # # SPI-based MMC/SD driver # diff --git a/nuttx/configs/sure-pic32mx/nsh/defconfig b/nuttx/configs/sure-pic32mx/nsh/defconfig index 07b31a1ae..d15bac1f4 100644 --- a/nuttx/configs/sure-pic32mx/nsh/defconfig +++ b/nuttx/configs/sure-pic32mx/nsh/defconfig @@ -285,7 +285,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sure-pic32mx/ostest/defconfig b/nuttx/configs/sure-pic32mx/ostest/defconfig index 86bb3b307..a04f2171a 100644 --- a/nuttx/configs/sure-pic32mx/ostest/defconfig +++ b/nuttx/configs/sure-pic32mx/ostest/defconfig @@ -264,7 +264,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/sure-pic32mx/usbnsh/defconfig b/nuttx/configs/sure-pic32mx/usbnsh/defconfig index 9f6046f21..3ebfde834 100644 --- a/nuttx/configs/sure-pic32mx/usbnsh/defconfig +++ b/nuttx/configs/sure-pic32mx/usbnsh/defconfig @@ -282,7 +282,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/teensy/hello/defconfig b/nuttx/configs/teensy/hello/defconfig index 8fafe1a10..cc2b6c9c1 100644 --- a/nuttx/configs/teensy/hello/defconfig +++ b/nuttx/configs/teensy/hello/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/teensy/nsh/defconfig b/nuttx/configs/teensy/nsh/defconfig index faeb0b103..0cc877731 100755 --- a/nuttx/configs/teensy/nsh/defconfig +++ b/nuttx/configs/teensy/nsh/defconfig @@ -221,7 +221,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/teensy/usbstorage/defconfig b/nuttx/configs/teensy/usbstorage/defconfig index 1f0186897..590a6f8bb 100755 --- a/nuttx/configs/teensy/usbstorage/defconfig +++ b/nuttx/configs/teensy/usbstorage/defconfig @@ -222,7 +222,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/twr-k60n512/nsh/defconfig b/nuttx/configs/twr-k60n512/nsh/defconfig index 3f272b55a..959379bea 100644 --- a/nuttx/configs/twr-k60n512/nsh/defconfig +++ b/nuttx/configs/twr-k60n512/nsh/defconfig @@ -286,6 +286,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/twr-k60n512/ostest/defconfig b/nuttx/configs/twr-k60n512/ostest/defconfig index fd27ffc2b..14d3435da 100644 --- a/nuttx/configs/twr-k60n512/ostest/defconfig +++ b/nuttx/configs/twr-k60n512/ostest/defconfig @@ -285,6 +285,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/ubw32/nsh/defconfig b/nuttx/configs/ubw32/nsh/defconfig index 89afd5912..8769fa677 100644 --- a/nuttx/configs/ubw32/nsh/defconfig +++ b/nuttx/configs/ubw32/nsh/defconfig @@ -272,7 +272,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/us7032evb1/nsh/defconfig b/nuttx/configs/us7032evb1/nsh/defconfig index 2405dc2d3..5bf0bd71d 100644 --- a/nuttx/configs/us7032evb1/nsh/defconfig +++ b/nuttx/configs/us7032evb1/nsh/defconfig @@ -197,7 +197,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/us7032evb1/ostest/defconfig b/nuttx/configs/us7032evb1/ostest/defconfig index e910f112f..5b40baf88 100644 --- a/nuttx/configs/us7032evb1/ostest/defconfig +++ b/nuttx/configs/us7032evb1/ostest/defconfig @@ -197,7 +197,7 @@ CONFIG_FS_ROMFS=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y -CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/configs/vsn/nsh/defconfig b/nuttx/configs/vsn/nsh/defconfig index 2b7d8a20c..5952f4724 100755 --- a/nuttx/configs/vsn/nsh/defconfig +++ b/nuttx/configs/vsn/nsh/defconfig @@ -333,6 +333,7 @@ CONFIG_I2C_SLAVE=n CONFIG_MMCSD=y CONFIG_MMCSD_SPI=y CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y # # SPI-based MMC/SD driver diff --git a/nuttx/drivers/mtd/Make.defs b/nuttx/drivers/mtd/Make.defs index 7db7592d4..3102f1447 100644 --- a/nuttx/drivers/mtd/Make.defs +++ b/nuttx/drivers/mtd/Make.defs @@ -37,6 +37,8 @@ # Include MTD drivers +ifeq ($(CONFIG_MTD),y) + CSRCS += at45db.c flash_eraseall.c ftl.c m25px.c rammtd.c ramtron.c ifeq ($(CONFIG_MTD_AT24XX),y) @@ -60,3 +62,4 @@ endif DEPPATH += --dep-path mtd VPATH += :mtd +endif -- cgit v1.2.3 From 90a72e97d3f18a5e230578c63113da119622a73a Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 15 Jan 2013 15:40:18 +0000 Subject: Implement vfork() for the MIPS32 architecture git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5520 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 3 + nuttx/Documentation/NuttX.html | 4 +- nuttx/TODO | 21 ++- nuttx/arch/arm/src/arm/vfork.S | 3 + nuttx/arch/arm/src/armv7-m/vfork.S | 3 + nuttx/arch/arm/src/common/up_vfork.c | 2 +- nuttx/arch/arm/src/common/up_vfork.h | 8 +- nuttx/arch/mips/Kconfig | 1 + nuttx/arch/mips/src/mips32/Kconfig | 8 ++ nuttx/arch/mips/src/mips32/up_vfork.c | 254 ++++++++++++++++++++++++++++++++++ nuttx/arch/mips/src/mips32/up_vfork.h | 132 ++++++++++++++++++ nuttx/arch/mips/src/mips32/vfork.S | 154 +++++++++++++++++++++ nuttx/arch/mips/src/pic32mx/Make.defs | 4 +- nuttx/configs/ubw32/ostest/defconfig | 9 +- nuttx/sched/task_vfork.c | 8 +- 15 files changed, 599 insertions(+), 15 deletions(-) create mode 100644 nuttx/arch/mips/src/mips32/up_vfork.c create mode 100644 nuttx/arch/mips/src/mips32/up_vfork.h create mode 100644 nuttx/arch/mips/src/mips32/vfork.S diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 41ac95db0..2d2cd8259 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3952,4 +3952,7 @@ scripts sub-directory * configs/ubw32/ostest: Configuration configured to use the kconfig-frontends tools. + * arch/mips/src/mips32/up_vfork.c, up_vfork.h, and vfork.S: + Implement vfork() for MIPS32 (no floating point support) + * configs/ubw32/ostest: Enable the vfork() test. diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index 22651de79..c5f1ebc9c 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -381,7 +381,7 @@

          -

        • Well documented in the NuttX User Guide.
          • +
        • Well documented in the NuttX User Guide.

          • @@ -3833,7 +3833,7 @@ pascal-3.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org> - User Guide + User Guide diff --git a/nuttx/TODO b/nuttx/TODO index 0d02e10e6..58ca4cc8e 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (10) Task/Scheduler (sched/) + (11) Task/Scheduler (sched/) (1) Memory Managment (mm/) (3) Signals (sched/, arch/) (2) pthreads (sched/) @@ -195,6 +195,25 @@ o Task/Scheduler (sched/) Status: Open Priority: Low + Title: IMPROVED TASK CONTROL BLOCK STRUCTURE + All task resources that are shared amongst threads have + their own "break-away", reference-counted structure. The + Task Control Block (TCB) of each thread holds a reference + to each breakaway structure (see include/nuttx/sched.h). + It would be more efficent to have one reference counted + structure that holds all of the shared resources. + + These are the current shared structures: + - Environment varaibles (struct environ_s) + - PIC data space and address environments (struct dspace_s) + - File descriptors (struct filelist) + - FILE streams (struct streamlist) + - Sockets (struct socketlist) + Status: Open + Priority: Low. This is an enhancement. It would slight reduce + memory usage but would also increase coupling. These + resources are nicely modular now. + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/arch/arm/src/arm/vfork.S b/nuttx/arch/arm/src/arm/vfork.S index 226d9f7de..7c3c8b727 100644 --- a/nuttx/arch/arm/src/arm/vfork.S +++ b/nuttx/arch/arm/src/arm/vfork.S @@ -105,6 +105,7 @@ vfork: mov r0, sp /* Save the value of the stack on entry */ sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + /* CPU registers */ /* Save the volatile registers */ str r4, [sp, #VFORK_R4_OFFSET] @@ -121,6 +122,8 @@ vfork: str r0, [sp, #VFORK_SP_OFFSET] str lr, [sp, #VFORK_LR_OFFSET] + /* Floating point registers (not yet) */ + /* Then, call up_vfork(), passing it a pointer to the stack structure */ mov r0, sp diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S index 386fca33c..f36ff23aa 100644 --- a/nuttx/arch/arm/src/armv7-m/vfork.S +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -108,6 +108,7 @@ vfork: mov r0, sp /* Save the value of the stack on entry */ sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + /* CPU registers */ /* Save the volatile registers */ str r4, [sp, #VFORK_R4_OFFSET] @@ -124,6 +125,8 @@ vfork: str r0, [sp, #VFORK_SP_OFFSET] str lr, [sp, #VFORK_LR_OFFSET] + /* Floating point registers (not yet) */ + /* Then, call up_vfork(), passing it a pointer to the stack structure */ mov r0, sp diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c index 5349378bc..3b653e317 100644 --- a/nuttx/arch/arm/src/common/up_vfork.c +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -208,7 +208,7 @@ pid_t up_vfork(const struct vfork_s *context) svdbg("New stack base:%08x SP:%08x FP:%08x\n", child->adj_stack_ptr, newsp, newfp); - /* Update the stack pointer, frame pointer, and voltile registers. When + /* Update the stack pointer, frame pointer, and volatile registers. When * the child TCB was initialized, all of the values were set to zero. * up_initial_state() altered a few values, but the return value in R0 * should be cleared to zero, providing the indication to the newly started diff --git a/nuttx/arch/arm/src/common/up_vfork.h b/nuttx/arch/arm/src/common/up_vfork.h index a4505474a..97edf9aaa 100644 --- a/nuttx/arch/arm/src/common/up_vfork.h +++ b/nuttx/arch/arm/src/common/up_vfork.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/arm-vfork.h + * arch/arm/src/common/up_vfork.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,6 +53,7 @@ #define VFORK_R8_OFFSET (4*4) /* Volatile register r8 */ #define VFORK_R9_OFFSET (5*4) /* Volatile register r9 */ #define VFORK_R10_OFFSET (6*4) /* Volatile register r10 */ + #define VFORK_FP_OFFSET (7*4) /* Frame pointer */ #define VFORK_SP_OFFSET (8*4) /* Stack pointer*/ #define VFORK_LR_OFFSET (9*4) /* Return address*/ @@ -66,6 +67,8 @@ #ifndef __ASSEMBLY__ struct vfork_s { + /* CPU registers */ + uint32_t r4; /* Volatile register r4 */ uint32_t r5; /* Volatile register r5 */ uint32_t r6; /* Volatile register r6 */ @@ -73,9 +76,12 @@ struct vfork_s uint32_t r8; /* Volatile register r8 */ uint32_t r9; /* Volatile register r9 */ uint32_t r10; /* Volatile register r10 */ + uint32_t fp; /* Frame pointer */ uint32_t sp; /* Stack pointer*/ uint32_t lr; /* Return address*/ + + /* Floating point registers (not yet) */ }; #endif diff --git a/nuttx/arch/mips/Kconfig b/nuttx/arch/mips/Kconfig index 1b10e26ae..86482ef7a 100644 --- a/nuttx/arch/mips/Kconfig +++ b/nuttx/arch/mips/Kconfig @@ -22,6 +22,7 @@ endchoice config ARCH_MIPS32 bool default n + select ARCH_HAVE_VFORK config ARCH_FAMILY string diff --git a/nuttx/arch/mips/src/mips32/Kconfig b/nuttx/arch/mips/src/mips32/Kconfig index b8b5d9b92..c7a4499c2 100644 --- a/nuttx/arch/mips/src/mips32/Kconfig +++ b/nuttx/arch/mips/src/mips32/Kconfig @@ -47,4 +47,12 @@ config MIPS32_TOOLCHAIN_PINGUINOL endchoice +config MIPS32_FRAMEPOINTER + bool "ABI Uses Frame Pointer" + default n + depends on ARCH_HAVE_VFORK + ---help--- + Register r30 may be a frame pointer in some ABIs. Or may just be + saved register s8. It makes a difference for vfork handling. + endif diff --git a/nuttx/arch/mips/src/mips32/up_vfork.c b/nuttx/arch/mips/src/mips32/up_vfork.c new file mode 100644 index 000000000..6b7e27f31 --- /dev/null +++ b/nuttx/arch/mips/src/mips32/up_vfork.c @@ -0,0 +1,254 @@ +/**************************************************************************** + * arch/mips/src/mips32/up_vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_vfork.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STACK_ALIGNMENT +# define CONFIG_STACK_ALIGNMENT 4 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + * + * Input Paremeters: + * context - Caller context information saved by vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +pid_t up_vfork(const struct vfork_s *context) +{ + _TCB *parent = (FAR _TCB *)g_readytorun.head; + _TCB *child; + size_t stacksize; + uint32_t newsp; +#if CONFIG_MIPS32_FRAMEPOINTER + uint32_t newfp; +#endif + uint32_t stackutil; + int ret; + + svdbg("s0:%08x s1:%08x s2:%08x s3:%08x s4:%08x\n", + context->s0, context->s1, context->s2, context->s3, context->s4); +#if CONFIG_MIPS32_FRAMEPOINTER + svdbg("s5:%08x s6:%08x s7:%08x\n", + context->s5, context->s6, context->s7); +#ifdef MIPS32_SAVE_GP + svdbg("fp:%08x sp:%08x ra:%08x gp:%08x\n", + context->fp, context->sp, context->ra, context->gp); +#else + svdbg("fp:%08x sp:%08x ra:%08x\n", + context->fp context->sp, context->ra); +#endif +#else + svdbg("s5:%08x s6:%08x s7:%08x s8:%08x\n", + context->s5, context->s6, context->s7, context->s8); +#ifdef MIPS32_SAVE_GP + svdbg("sp:%08x ra:%08x gp:%08x\n", + context->sp, context->ra, context->gp); +#else + svdbg("sp:%08x ra:%08x\n", + context->sp, context->ra); +#endif +#endif + + /* Allocate and initialize a TCB for the child task. */ + + child = task_vforksetup((start_t)context->ra); + if (!child) + { + sdbg("task_vforksetup failed\n"); + return (pid_t)ERROR; + } + + svdbg("Parent=%p Child=%p\n", parent, child); + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Allocate the stack for the TCB */ + + ret = up_create_stack(child, stacksize); + if (ret != OK) + { + sdbg("up_create_stack failed: %d\n", ret); + task_vforkabort(child, -ret); + return (pid_t)ERROR; + } + + /* How much of the parent's stack was utilized? The MIPS uses + * a push-down stack so that the current stack pointer should + * be lower than the initial, adjusted stack pointer. The + * stack usage should be the difference between those two. + */ + + DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); + stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + + svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); + + /* Make some feeble effort to perserve the stack contents. This is + * feeble because the stack surely contains invalid pointers and other + * content that will not work in the child context. However, if the + * user follows all of the caveats of vfor() usage, even this feeble + * effort is overkill. + */ + + newsp = (uint32_t)child->adj_stack_ptr - stackutil; + memcpy((void *)newsp, (const void *)context->sp, stackutil); + + /* Was there a frame pointer in place before? */ + +#if CONFIG_MIPS32_FRAMEPOINTER + if (context->fp <= (uint32_t)parent->adj_stack_ptr && + context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize) + { + uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp; + newfp = (uint32_t)child->adj_stack_ptr - frameutil; + } + else + { + newfp = context->fp; + } + + svdbg("Old stack base:%08x SP:%08x FP:%08x\n", + parent->adj_stack_ptr, context->sp, context->fp); + svdbg("New stack base:%08x SP:%08x FP:%08x\n", + child->adj_stack_ptr, newsp, newfp); +#else + svdbg("Old stack base:%08x SP:%08x\n", + parent->adj_stack_ptr, context->sp); + svdbg("New stack base:%08x SP:%08x\n", + child->adj_stack_ptr, newsp); +#endif + + /* Update the stack pointer, frame pointer, global pointer and saved + * registers. When the child TCB was initialized, all of the values + * were set to zero. up_initial_state() altered a few values, but the + * return value in v0 should be cleared to zero, providing the + * indication to the newly started child thread. + */ + + child->xcp.regs[REG_S0] = context->s0; /* Saved register s0 */ + child->xcp.regs[REG_S1] = context->s1; /* Saved register s1 */ + child->xcp.regs[REG_S2] = context->s2; /* Saved register s2 */ + child->xcp.regs[REG_S3] = context->s3; /* Volatile register s3 */ + child->xcp.regs[REG_S4] = context->s4; /* Volatile register s4 */ + child->xcp.regs[REG_S5] = context->s5; /* Volatile register s5 */ + child->xcp.regs[REG_S6] = context->s6; /* Volatile register s6 */ + child->xcp.regs[REG_S7] = context->s7; /* Volatile register s7 */ +#if CONFIG_MIPS32_FRAMEPOINTER + child->xcp.regs[REG_FP] = newfp; /* Frame pointer */ +#else + child->xcp.regs[REG_S8] = context->s8; /* Volatile register s8 */ +#endif + child->xcp.regs[REG_SP] = newsp; /* Stack pointer */ +#if MIPS32_SAVE_GP + child->xcp.regs[REG_GP] = newsp; /* Global pointer */ +#endif + + /* And, finally, start the child task. On a failure, task_vforkstart() + * will discard the TCB by calling task_vforkabort(). + */ + + return task_vforkstart(child); +} diff --git a/nuttx/arch/mips/src/mips32/up_vfork.h b/nuttx/arch/mips/src/mips32/up_vfork.h new file mode 100644 index 000000000..556633072 --- /dev/null +++ b/nuttx/arch/mips/src/mips32/up_vfork.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/mips/src/mips/up_vfork.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_VFORK_H +#define __ARCH_MIPS_SRC_MIPS32_VFORK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Register r30 may be a frame pointer in some ABIs. Or may just be saved + * register s8. It makes a difference for vfork handling. + */ + +#undef VFORK_HAVE_FP + +/* r0 zero Always has the value 0. + * r1 at Temporary generally used by assembler. + * r2-r3 v0-v1 Used for expression evaluations and to hold the integer and + * pointer type function return values. + * r4-r7 a0-a3 Used for passing arguments to functions; values are not + * preserved across function calls. + * r8-r15 t0-t7 Temporary registers used for expression evaluation; values + * are not preserved across function calls. + * r16-r23 s0-s7 Saved registers; values are preserved across function calls. + * r24-r25 t8-t9 Temporary registers used for expression evaluations; values + * are not preserved across function calls. When calling + * position independent functions r25 must contain the address + * of the called function. + * r26-r27 k0-k1 Used only by the operating system. + * r28 gp Global pointer and context pointer. + * r29 sp Stack pointer. + * r30 s8 Saved register (like s0-s7). If a frame pointer is used, + * then this is the frame pointer. + * r31 ra Return address. + */ + +#define VFORK_S0_OFFSET (0*4) /* Saved register s0 */ +#define VFORK_S1_OFFSET (1*4) /* Saved register s1 */ +#define VFORK_S2_OFFSET (2*4) /* Saved register s2 */ +#define VFORK_S3_OFFSET (3*4) /* Saved register s3 */ +#define VFORK_S4_OFFSET (4*4) /* Saved register s4 */ +#define VFORK_S5_OFFSET (5*4) /* Saved register s5 */ +#define VFORK_S6_OFFSET (6*4) /* Saved register s6 */ +#define VFORK_S7_OFFSET (7*4) /* Saved register s7 */ + +#ifdef CONFIG_MIPS32_FRAMEPOINTER +# define VFORK_FP_OFFSET (8*4) /* Frame pointer */ +#else +# define VFORK_S8_OFFSET (8*4) /* Saved register s8 */ +#endif + +#define VFORK_SP_OFFSET (9*4) /* Stack pointer*/ +#define VFORK_RA_OFFSET (10*4) /* Return address*/ +#ifdef MIPS32_SAVE_GP +# define VFORK_GP_OFFSET (11*4) /* Global pointer */ +# define VFORK_SIZEOF (12*4) +#else +# define VFORK_SIZEOF (11*4) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct vfork_s +{ + /* CPU registers */ + + uint32_t s0; /* Saved register s0 */ + uint32_t s1; /* Saved register s1 */ + uint32_t s2; /* Saved register s2 */ + uint32_t s3; /* Saved register s3 */ + uint32_t s4; /* Saved register s4 */ + uint32_t s5; /* Saved register s5 */ + uint32_t s6; /* Saved register s6 */ + uint32_t s7; /* Saved register s7 */ +#ifdef CONFIG_MIPS32_FRAMEPOINTER + uint32_t fp; /* Frame pointer */ +#else + uint32_t s8; /* Saved register s8 */ +#endif + uint32_t sp; /* Stack pointer*/ + uint32_t ra; /* Return address*/ +#ifdef MIPS32_SAVE_GP + uint32_t gp; /* Global pointer */ +#endif + + /* Floating point registers (not yet) */ +}; +#endif + +#endif /* __ARCH_MIPS_SRC_MIPS32_VFORK_H */ diff --git a/nuttx/arch/mips/src/mips32/vfork.S b/nuttx/arch/mips/src/mips32/vfork.S new file mode 100644 index 000000000..2b7d180d3 --- /dev/null +++ b/nuttx/arch/mips/src/mips32/vfork.S @@ -0,0 +1,154 @@ +/************************************************************************************ + * arch/mips/src/mips32/vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "up_vfork.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .file "vfork.S" + .globl up_vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling up_vfork() with the vfork() + * context as an argument. The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .text + .align 2 + .globl vfork + .type vfork, function + .set nomips16 + .ent vfork + +vfork: + /* Create a stack frame */ + + move $t0, $sp /* Save the value of the stack on entry */ + addiu $sp, $sp, -VFORK_SIZEOF /* Allocate the structure on the stack */ + + /* CPU registers */ + /* Save the saved registers */ + + sw $s0, VFORK_S0_OFFSET($sp) + sw $s1, VFORK_S1_OFFSET($sp) + sw $s2, VFORK_S2_OFFSET($sp) + sw $s3, VFORK_S3_OFFSET($sp) + sw $s4, VFORK_S4_OFFSET($sp) + sw $s5, VFORK_S5_OFFSET($sp) + sw $s6, VFORK_S6_OFFSET($sp) + sw $s7, VFORK_S7_OFFSET($sp) + +#ifdef CONFIG_MIPS32_FRAMEPOINTER + sw $fp, VFORK_FP_OFFSET($sp) +#else + sw $s8, VFORK_S8_OFFSET($sp) +#endif + + /* Save the global pointer, stack pointer, and return address */ + + sw $t0, VFORK_SP_OFFSET($sp) + sw $ra, VFORK_RA_OFFSET($sp) +#ifdef MIPS32_SAVE_GP + sw $gp, VFORK_GP_OFFSET($sp) +#endif + + /* Floating point registers (not yet) */ + + /* Then, call up_vfork(), passing it a pointer to the stack structure */ + + move $a0, $sp + jal up_vfork + nop + + /* Release the stack data and return the value returned by up_vfork */ + + lw $ra, VFORK_RA_OFFSET($sp) + addiu $sp, $sp, VFORK_SIZEOF + j $ra + + .end vfork + .size vfork, .-vfork diff --git a/nuttx/arch/mips/src/pic32mx/Make.defs b/nuttx/arch/mips/src/pic32mx/Make.defs index 46fef84dc..861e1c301 100644 --- a/nuttx/arch/mips/src/pic32mx/Make.defs +++ b/nuttx/arch/mips/src/pic32mx/Make.defs @@ -39,14 +39,14 @@ HEAD_ASRC = pic32mx-head.S # Common MIPS files -CMN_ASRCS = up_syscall0.S +CMN_ASRCS = up_syscall0.S vfork.S CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \ up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c \ up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ up_puts.c up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_swint0.c up_udelay.c \ - up_unblocktask.c up_usestack.c + up_unblocktask.c up_usestack.c up_vfork.c # Configuration dependent common files diff --git a/nuttx/configs/ubw32/ostest/defconfig b/nuttx/configs/ubw32/ostest/defconfig index 3a387ab99..a722e25e7 100644 --- a/nuttx/configs/ubw32/ostest/defconfig +++ b/nuttx/configs/ubw32/ostest/defconfig @@ -72,13 +72,10 @@ CONFIG_ARCH_MIPS32=y # MIPS32 Configuration Options # # CONFIG_MIPS32_TOOLCHAIN_GNU_ELF is not set -# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL is not set -# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_LITE is not set # CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW is not set CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE=y -# CONFIG_MIPS32_TOOLCHAIN_MICROCHIPOPENL is not set # CONFIG_MIPS32_TOOLCHAIN_PINGUINOW is not set -# CONFIG_MIPS32_TOOLCHAIN_PINGUINOL is not set +# CONFIG_MIPS32_FRAMEPOINTER is not set # # PIC32MX Configuration Options @@ -245,7 +242,7 @@ CONFIG_ARCH_VECNOTIRQ=y CONFIG_ARCH_IRQPRIO=y # CONFIG_CUSTOM_STACK is not set # CONFIG_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set +CONFIG_ARCH_HAVE_VFORK=y CONFIG_ARCH_STACKDUMP=y # CONFIG_ENDIAN_BIG is not set CONFIG_ARCH_HAVE_RAMFUNCS=y @@ -308,7 +305,7 @@ CONFIG_DEV_CONSOLE=y # CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y # CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_WAITPID is not set +CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set CONFIG_USER_ENTRYPOINT="ostest_main" diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c index 4b42c7b36..46b2d8e9f 100644 --- a/nuttx/sched/task_vfork.c +++ b/nuttx/sched/task_vfork.c @@ -287,7 +287,11 @@ pid_t task_vforkstart(FAR _TCB *child) #endif #else - /* Again exploiting that execv() bug: Check if the child thread is + /* The following logic does not appear to work... It gets stuff in an + * infinite kill() loop and hogs the processor. Therefore, it looks + * as though CONFIG_SCHED_WAITPID may be a requirement to used vfork(). + * + * Again exploiting that execv() bug: Check if the child thread is * still running. */ @@ -331,4 +335,4 @@ void task_vforkabort(FAR _TCB *child, int errcode) sched_releasetcb(child); set_errno(errcode); -} \ No newline at end of file +} -- cgit v1.2.3 From fcb316906d1741c28292e94eb7f09bd4d71ccb48 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 15 Jan 2013 21:01:37 +0000 Subject: Implement redirection of output from NSH builtin commands to a file in a mounted volume git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5521 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/builtin/Kconfig | 9 + apps/builtin/binfs.c | 6 +- apps/builtin/builtin.c | 4 +- apps/builtin/builtin.h | 2 +- apps/builtin/exec_builtin.c | 397 ++++++++++++-- apps/include/apps.h | 41 +- apps/nshlib/Makefile | 2 +- apps/nshlib/nsh.h | 3 +- apps/nshlib/nsh_apps.c | 220 -------- apps/nshlib/nsh_builtin.c | 226 ++++++++ apps/nshlib/nsh_codeccmd.c | 1076 +++++++++++++++++++------------------- apps/nshlib/nsh_parse.c | 95 ++-- nuttx/configs/sim/nsh/defconfig | 3 +- nuttx/configs/vsn/src/README.txt | 3 +- nuttx/fs/fat/fs_fat32.c | 19 +- nuttx/fs/romfs/fs_romfs.c | 17 +- 17 files changed, 1225 insertions(+), 900 deletions(-) delete mode 100644 apps/nshlib/nsh_apps.c create mode 100644 apps/nshlib/nsh_builtin.c diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index bf329a40d..ea4fcd07b 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -467,3 +467,5 @@ * apps/examples/ostest/waitpid.c: Add a test for waitpid(), waitid(), and wait(). * builtin/binfs.c: Add hooks for dup() method (not implemented). + * builtin/exec_builtin.c, nshlib/nsh_parse.c, and nshlib/nsh_builtin.c: + NSH now supports re-direction of I/O to files (but still not from). diff --git a/apps/builtin/Kconfig b/apps/builtin/Kconfig index 5b262734d..1049712aa 100644 --- a/apps/builtin/Kconfig +++ b/apps/builtin/Kconfig @@ -27,4 +27,13 @@ if BUILTIN however, to support execution of the builtin applications from BINFS as well (via a binfmt/ loader). However, that is down the road. +config BUILTIN_PROXY_STACKSIZE + int "Builtin Proxy Stack Size" + default 1024 + ---help--- + If exec_builting uses I/O redirection options, then it will require + an intermediary/proxy task to muck with the file descriptors. This + configuration item specifies the stack size used for the proxy. Default: + 1024 bytes. + endif diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c index 365021c7f..1fc2e7940 100644 --- a/apps/builtin/binfs.c +++ b/apps/builtin/binfs.c @@ -399,7 +399,7 @@ static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) /* Have we reached the end of the directory */ index = dir->u.binfs.fb_index; - if (builtins[index].name == NULL) + if (g_builtins[index].name == NULL) { /* We signal the end of the directory by returning the * special error -ENOENT @@ -412,9 +412,9 @@ static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) { /* Save the filename and file type */ - fvdbg("Entry %d: \"%s\"\n", index, builtins[index].name); + fvdbg("Entry %d: \"%s\"\n", index, g_builtins[index].name); dir->fd_dir.d_type = DTYPE_FILE; - strncpy(dir->fd_dir.d_name, builtins[index].name, NAME_MAX+1); + strncpy(dir->fd_dir.d_name, g_builtins[index].name, NAME_MAX+1); /* The application list is terminated by an entry with a NULL name. * Therefore, there is at least one more entry in the list. diff --git a/apps/builtin/builtin.c b/apps/builtin/builtin.c index a6ed7dd3f..e0ae9888a 100644 --- a/apps/builtin/builtin.c +++ b/apps/builtin/builtin.c @@ -64,7 +64,7 @@ extern "C" { #include "builtin_proto.h" -const struct builtin_s builtins[] = +const struct builtin_s g_builtins[] = { # include "builtin_list.h" { NULL, 0, 0, 0 } @@ -90,7 +90,7 @@ const struct builtin_s builtins[] = int number_builtins(void) { - return sizeof(builtins)/sizeof(struct builtin_s) - 1; + return sizeof(g_builtins)/sizeof(struct builtin_s) - 1; } diff --git a/apps/builtin/builtin.h b/apps/builtin/builtin.h index 3f7ddd7ce..4593809ee 100644 --- a/apps/builtin/builtin.h +++ b/apps/builtin/builtin.h @@ -60,7 +60,7 @@ extern "C" { #define EXTERN extern #endif -EXTERN const struct builtin_s builtins[]; +EXTERN const struct builtin_s g_builtins[]; /**************************************************************************** * Public Functions diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index dc3630230..a3e79a945 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -1,13 +1,15 @@ /**************************************************************************** * apps/builtin/exec_builtin.c * + * Originally by: + * * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * - * With updates, modifications, and general maintenance by: + * With subsequent updates, modifications, and general maintenance by: * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Auther: Gregory Nutt + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,18 +45,45 @@ ****************************************************************************/ #include -#include -#include +#include #include +#include +#include #include +#include + +#include #include "builtin.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_BUILTIN_PROXY_STACKSIZE +# define CONFIG_BUILTIN_PROXY_STACKSIZE 1024 +#endif + /**************************************************************************** * Private Types ****************************************************************************/ +struct builtin_parms_s +{ + /* Input values */ + + FAR const char *redirfile; + FAR const char **argv; + int oflags; + int index; + + /* Returned values */ + + pid_t result; + int errcode; +}; + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -63,10 +92,276 @@ * Private Data ****************************************************************************/ +static sem_t g_builtin_parmsem = SEM_INITIALIZER(1); +static sem_t g_builtin_execsem = SEM_INITIALIZER(0); +static struct builtin_parms_s g_builtin_parms; + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: bultin_semtake and builtin_semgive + * + * Description: + * Give and take semaphores + * + * Input Parameters: + * + * sem - The semaphore to act on. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bultin_semtake(FAR sem_t *sem) +{ + int ret; + + do + { + ret = sem_wait(sem); + ASSERT(ret == 0 || errno == EINTR); + } + while (ret != 0); +} + +#define builtin_semgive(sem) sem_post(sem) + +/**************************************************************************** + * Name: builtin_taskcreate + * + * Description: + * Execute the builtin task + * + * Returned Value: + * On success, the task ID of the builtin task is returned; On failure, -1 + * (ERROR) is returned and the errno is set appropriately. + * + ****************************************************************************/ + +static int builtin_taskcreate(int index, FAR const char **argv) +{ + int ret; + + /* Disable pre-emption. This means that although we start the builtin + * application here, it will not actually run until pre-emption is + * re-enabled below. + */ + + sched_lock(); + + /* Start the builtin application task */ + + ret = TASK_CREATE(g_builtins[index].name, g_builtins[index].priority, + g_builtins[index].stacksize, g_builtins[index].main, + (argv) ? &argv[1] : (FAR const char **)NULL); + + /* If robin robin scheduling is enabled, then set the scheduling policy + * of the new task to SCHED_RR before it has a chance to run. + */ + +#if CONFIG_RR_INTERVAL > 0 + if (ret > 0) + { + struct sched_param param; + + /* Pre-emption is disabled so the task creation and the + * following operation will be atomic. The priority of the + * new task cannot yet have changed from its initial value. + */ + + param.sched_priority = g_builtins[index].priority; + (void)sched_setscheduler(ret, SCHED_RR, ¶m); + } +#endif + + /* Now let the builtin application run */ + + sched_unlock(); + + /* Return the task ID of the new task if the task was sucessfully + * started. Otherwise, ret will be ERROR (and the errno value will + * be set appropriately). + */ + + return ret; +} + +/**************************************************************************** + * Name: builtin_proxy + * + * Description: + * Perform output redirection, then execute the builtin task. + * + * Input Parameters: + * Standard task start-up parameters + * + * Returned Value: + * Standard task return value. + * + ****************************************************************************/ + +static int builtin_proxy(int argc, char *argv[]) +{ + int fd; + int ret = ERROR; + + /* Open the output file for redirection */ + + svdbg("Open'ing redirfile=%s oflags=%04x mode=0644\n", + g_builtin_parms.redirfile, g_builtin_parms.oflags); + + fd = open(g_builtin_parms.redirfile, g_builtin_parms.oflags, 0644); + if (fd < 0) + { + /* Remember the errno value. ret is already set to ERROR */ + + g_builtin_parms.errcode = errno; + sdbg("ERROR: open of %s failed: %d\n", + g_builtin_parms.redirfile, g_builtin_parms.errcode); + } + + /* Does the return file descriptor happen to match the required file + * desciptor number? + */ + + else if (fd != 1) + { + /* No.. dup2 to get the correct file number */ + + svdbg("Dup'ing %d->1\n", fd); + + ret = dup2(fd, 1); + if (ret < 0) + { + g_builtin_parms.errcode = errno; + sdbg("ERROR: dup2 failed: %d\n", g_builtin_parms.errcode); + } + + svdbg("Closing fd=%d\n", fd); + close(fd); + } + + /* Was the setup successful? */ + + if (ret == OK) + { + /* Yes.. Start the task. On success, the task ID of the builtin task + * is returned; On failure, -1 (ERROR) is returned and the errno + * is set appropriately. + */ + + ret = builtin_taskcreate(g_builtin_parms.index, g_builtin_parms.argv); + if (ret < 0) + { + g_builtin_parms.errcode = errno; + sdbg("ERROR: builtin_taskcreate failed: %d\n", + g_builtin_parms.errcode); + } + } + + /* Post the semaphore to inform the parent task that we have completed + * what we need to do. + */ + + g_builtin_parms.result = ret; + builtin_semgive(&g_builtin_execsem); + return 0; +} + +/**************************************************************************** + * Name: builtin_startproxy + * + * Description: + * Perform output redirection, then execute the builtin task. + * + * Input Parameters: + * Standard task start-up parameters + * + * Returned Value: + * On success, the task ID of the builtin task is returned; On failure, -1 + * (ERROR) is returned and the errno is set appropriately. + * + ****************************************************************************/ + +static inline int builtin_startproxy(int index, FAR const char **argv, + FAR const char *redirfile, int oflags) +{ + struct sched_param param; + pid_t proxy; + int errcode; + int ret; + + DEBUGASSERT(path); + + svdbg("index=%d argv=%p redirfile=%s oflags=%04x\n", + index, argv, redirfile, oflags); + + /* We will have to go through an intermediary/proxy task in order to + * perform the I/O redirection. This would be a natural place to fork(). + * However, true fork() behavior requires an MMU and most implementations + * of vfork() are not capable of these operations. + * + * Even without fork(), we can still do the job, but parameter passing is + * messier. Unfortunately, there is no (clean) way to pass binary values + * as a task parameter, so we will use a semaphore-protected global + * structure. + */ + + /* Get exclusive access to the global parameter structure */ + + bultin_semtake(&g_builtin_parmsem); + + /* Populate the parameter structure */ + + g_builtin_parms.redirfile = redirfile; + g_builtin_parms.argv = argv; + g_builtin_parms.result = ERROR; + g_builtin_parms.oflags = oflags; + g_builtin_parms.index = index; + + /* Get the priority of this (parent) task */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + errcode = errno; + sdbg("ERROR: sched_getparam failed: %d\n", errcode); + goto errout; + } + + /* Start the intermediary/proxy task at the same priority as the parent task. */ + + proxy = TASK_CREATE("builtin_proxy", param.sched_priority, + CONFIG_BUILTIN_PROXY_STACKSIZE, (main_t)builtin_proxy, + (FAR const char **)NULL); + if (proxy < 0) + { + errcode = errno; + sdbg("ERROR: Failed to start builtin_proxy: %d\n", errcode); + goto errout; + } + + /* Wait for the proxy to complete its job. We could use waitpid() + * for this. + */ + + bultin_semtake(&g_builtin_execsem); + + /* Get the result and relinquish our access to the parameter structure */ + + set_errno(g_builtin_parms.errcode); + builtin_semgive(&g_builtin_parmsem); + return g_builtin_parms.result; + +errout: + set_errno(errcode); + builtin_semgive(&g_builtin_parmsem); + return ERROR; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -86,10 +381,10 @@ const char *builtin_getname(int index) { return NULL; } - - return builtins[index].name; + + return g_builtins[index].name; } - + /**************************************************************************** * Name: builtin_isavail * @@ -102,10 +397,10 @@ const char *builtin_getname(int index) int builtin_isavail(FAR const char *appname) { int i; - - for (i = 0; builtins[i].name; i++) + + for (i = 0; g_builtins[i].name; i++) { - if (!strcmp(builtins[i].name, appname)) + if (!strcmp(g_builtins[i].name, appname)) { return i; } @@ -114,74 +409,60 @@ int builtin_isavail(FAR const char *appname) set_errno(ENOENT); return ERROR; } - + /**************************************************************************** - * Name: builtin_isavail + * Name: exec_builtin * * Description: - * Execute the application with name 'appname', providing the arguments - * in the argv[] array. + * Executes builtin applications registered during 'make context' time. + * New application is run in a separate task context (and thread). + * + * Input Parameter: + * filename - Name of the linked-in binary to be started. + * argv - Argument list + * redirfile - If output if redirected, this parameter will be non-NULL + * and will provide the full path to the file. + * oflags - If output is redirected, this parameter will provide the + * open flags to use. This will support file replacement + * of appending to an existing file. * * Returned Value: - * On success, the task ID of the builtin application is returned. On - * failure, -1 (ERROR) is returned an the errno value is set appropriately. + * This is an end-user function, so it follows the normal convention: + * Returns the PID of the exec'ed module. On failure, it.returns + * -1 (ERROR) and sets errno appropriately. * ****************************************************************************/ -int exec_builtin(FAR const char *appname, FAR const char **argv) +int exec_builtin(FAR const char *appname, FAR const char **argv, + FAR const char *redirfile, int oflags) { - pid_t pid; int index; + int ret = ERROR; /* Verify that an application with this name exists */ index = builtin_isavail(appname); if (index >= 0) { - /* Disable pre-emption. This means that although we start the builtin - * application here, it will not actually run until pre-emption is - * re-enabled below. - */ - - sched_lock(); - - /* Start the builtin application task */ + /* Is output being redirected? */ - pid = TASK_CREATE(builtins[index].name, builtins[index].priority, - builtins[index].stacksize, builtins[index].main, - (argv) ? &argv[1] : (const char **)NULL); - - /* If robin robin scheduling is enabled, then set the scheduling policy - * of the new task to SCHED_RR before it has a chance to run. - */ - -#if CONFIG_RR_INTERVAL > 0 - if (pid > 0) + if (redirfile) { - struct sched_param param; - - /* Pre-emption is disabled so the task creation and the - * following operation will be atomic. The priority of the - * new task cannot yet have changed from its initial value. - */ - - param.sched_priority = builtins[index].priority; - sched_setscheduler(pid, SCHED_RR, ¶m); + ret = builtin_startproxy(index, argv, redirfile, oflags); } -#endif - /* Now let the builtin application run */ - - sched_unlock(); - - /* Return the task ID of the new task if the task was sucessfully - * started. Otherwise, pid will be ERROR (and the errno value will - * be set appropriately). - */ + else + { + /* Start the builtin application task */ - return pid; + ret = builtin_taskcreate(index, argv); + } } - /* Return ERROR with errno set appropriately */ - return ERROR; + /* Return the task ID of the new task if the task was sucessfully + * started. Otherwise, ret will be ERROR (and the errno value will + * be set appropriately). + */ + + return ret; } diff --git a/apps/include/apps.h b/apps/include/apps.h index 37599ac5c..f806d8aed 100644 --- a/apps/include/apps.h +++ b/apps/include/apps.h @@ -1,9 +1,16 @@ /**************************************************************************** * apps/include/apps.h * - * Copyright(C) 2011 Uros Platise. All rights reserved. + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -64,27 +71,27 @@ struct builtin_s * Public Data ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + /* The "bindir" is file system that supports access to the builtin applications. * It is typically mounted under /bin. */ #ifdef CONFIG_APPS_BINDIR -struct mountpt_operations; -extern const struct mountpt_operations binfs_operations; +EXTERN mountpt_operations; +EXTERN const struct mountpt_operations binfs_operations; #endif /**************************************************************************** * Public Functions ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - /**************************************************************************** * Name: builtin_isavail * @@ -129,8 +136,13 @@ EXTERN const char *builtin_getname(int index); * New application is run in a separate task context (and thread). * * Input Parameter: - * filename - Name of the linked-in binary to be started. - * argv - Argument list + * filename - Name of the linked-in binary to be started. + * argv - Argument list + * redirfile - If output if redirected, this parameter will be non-NULL + * and will provide the full path to the file. + * oflags - If output is redirected, this parameter will provide the + * open flags to use. This will support file replacement + * of appending to an existing file. * * Returned Value: * This is an end-user function, so it follows the normal convention: @@ -139,7 +151,8 @@ EXTERN const char *builtin_getname(int index); * ****************************************************************************/ -EXTERN int exec_builtin(FAR const char *appname, FAR const char **argv); +EXTERN int exec_builtin(FAR const char *appname, FAR const char **argv, + FAR const char *redirfile, int oflags); #undef EXTERN #if defined(__cplusplus) diff --git a/apps/nshlib/Makefile b/apps/nshlib/Makefile index 7ddbb67bf..5c5269685 100644 --- a/apps/nshlib/Makefile +++ b/apps/nshlib/Makefile @@ -44,7 +44,7 @@ CSRCS = nsh_init.c nsh_parse.c nsh_console.c nsh_fscmds.c nsh_ddcmd.c \ nsh_proccmds.c nsh_mmcmds.c nsh_envcmds.c nsh_dbgcmds.c ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -CSRCS += nsh_apps.c +CSRCS += nsh_builtin.c endif ifeq ($(CONFIG_NSH_ROMFSETC),y) diff --git a/apps/nshlib/nsh.h b/apps/nshlib/nsh.h index a046a384f..253a803f8 100644 --- a/apps/nshlib/nsh.h +++ b/apps/nshlib/nsh.h @@ -491,7 +491,8 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline); /* Application interface */ #ifdef CONFIG_NSH_BUILTIN_APPS -int nsh_execapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, FAR char **argv); +int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, + FAR char **argv, FAR const char *redirfile, int oflags); #endif /* Working directory support */ diff --git a/apps/nshlib/nsh_apps.c b/apps/nshlib/nsh_apps.c deleted file mode 100644 index ea8791eef..000000000 --- a/apps/nshlib/nsh_apps.c +++ /dev/null @@ -1,220 +0,0 @@ -/**************************************************************************** - * apps/nshlib/nsh_apps.c - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_SCHED_WAITPID -# include -#endif - -#include -#include -#include - -#include - -#include "nsh.h" -#include "nsh_console.h" - -#ifdef CONFIG_NSH_BUILTIN_APPS - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nsh_execapp - * - * Description: - * Attempt to execute the application task whose name is 'cmd' - * - * Returned Value: - * <0 If exec_builtin() fails, then the negated errno value - * is returned. - * -1 (ERROR) if the application task corresponding to 'cmd' could not - * be started (possibly because it doesn not exist). - * 0 (OK) if the application task corresponding to 'cmd' was - * and successfully started. If CONFIG_SCHED_WAITPID is - * defined, this return value also indicates that the - * application returned successful status (EXIT_SUCCESS) - * 1 If CONFIG_SCHED_WAITPID is defined, then this return value - * indicates that the application task was spawned successfully - * but returned failure exit status. - * - ****************************************************************************/ - -int nsh_execapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, - FAR char **argv) -{ - int ret = OK; - - /* Lock the scheduler to prevent the application from running until the - * waitpid() has been called. - */ - - sched_lock(); - - /* Try to find and execute the command within the list of builtin - * applications. - */ - - ret = exec_builtin(cmd, (FAR const char **)argv); - if (ret >= 0) - { - /* The application was successfully started (but still blocked because - * the scheduler is locked). If the application was not backgrounded, - * then we need to wait here for the application to exit. These really - * only works works with the following options: - * - * - CONFIG_NSH_DISABLEBG - Do not run commands in background - * - CONFIG_SCHED_WAITPID - Required to run external commands in - * foreground - * - * These concepts do not apply cleanly to the external applications. - */ - -#ifdef CONFIG_SCHED_WAITPID - - /* CONFIG_SCHED_WAITPID is selected, so we may run the command in - * foreground unless we were specifically requested to run the command - * in background (and running commands in background is enabled). - */ - -# ifndef CONFIG_NSH_DISABLEBG - if (vtbl->np.np_bg == false) -# endif /* CONFIG_NSH_DISABLEBG */ - { - int rc = 0; - - /* Wait for the application to exit. Since we have locked the - * scheduler above, we know that the application has not yet - * started and there is no possibility that it has already exited. - * The scheduler will be unlocked while waitpid is waiting and the - * application will be able to run. - */ - - ret = waitpid(ret, &rc, 0); - if (ret >= 0) - { - /* We can't return the exact status (nsh has nowhere to put it) - * so just pass back zero/nonzero in a fashion that doesn't look - * like an error. - */ - - ret = (rc == 0) ? OK : 1; - - /* TODO: Set the environment variable '?' to a string corresponding - * to WEXITSTATUS(rc) so that $? will expand to the exit status of - * the most recently executed task. - */ - } - } -# ifndef CONFIG_NSH_DISABLEBG - else -# endif /* CONFIG_NSH_DISABLEBG */ -#endif /* CONFIG_SCHED_WAITPID */ - - /* We get here if either: - * - * - CONFIG_SCHED_WAITPID is not selected meaning that all commands - * have to be run in background, or - * - CONFIG_SCHED_WAITPID and CONFIG_NSH_DISABLEBG are both selected, but the - * user requested to run the command in background. - * - * NOTE that the case of a) CONFIG_SCHED_WAITPID is not selected and - * b) CONFIG_NSH_DISABLEBG selected cannot be supported. In that event, all - * commands will have to run in background. The waitpid() API must be - * available to support running the command in foreground. - */ - -#if !defined(CONFIG_SCHED_WAITPID) || !defined(CONFIG_NSH_DISABLEBG) - { - struct sched_param param; - sched_getparam(0, ¶m); - nsh_output(vtbl, "%s [%d:%d]\n", cmd, ret, param.sched_priority); - - /* Backgrounded commands always 'succeed' as long as we can start - * them. - */ - - ret = OK; - } -#endif /* !CONFIG_SCHED_WAITPID || !CONFIG_NSH_DISABLEBG */ - } - - sched_unlock(); - - /* If exec_builtin() or waitpid() failed, then return the negated errno - * value. - */ - - if (ret < 0) - { - return -errno; - } - - return ret; -} - -#endif /* CONFIG_NSH_BUILTIN_APPS */ diff --git a/apps/nshlib/nsh_builtin.c b/apps/nshlib/nsh_builtin.c new file mode 100644 index 000000000..16e3e9427 --- /dev/null +++ b/apps/nshlib/nsh_builtin.c @@ -0,0 +1,226 @@ +/**************************************************************************** + * apps/nshlib/nsh_builtin.c + * + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_SCHED_WAITPID +# include +#endif + +#include +#include +#include + +#include + +#include "nsh.h" +#include "nsh_console.h" + +#ifdef CONFIG_NSH_BUILTIN_APPS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_builtin + * + * Description: + * Attempt to execute the application task whose name is 'cmd' + * + * Returned Value: + * <0 If exec_builtin() fails, then the negated errno value + * is returned. + * -1 (ERROR) if the application task corresponding to 'cmd' could not + * be started (possibly because it doesn not exist). + * 0 (OK) if the application task corresponding to 'cmd' was + * and successfully started. If CONFIG_SCHED_WAITPID is + * defined, this return value also indicates that the + * application returned successful status (EXIT_SUCCESS) + * 1 If CONFIG_SCHED_WAITPID is defined, then this return value + * indicates that the application task was spawned successfully + * but returned failure exit status. + * + ****************************************************************************/ + +int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, + FAR char **argv, FAR const char *redirfile, int oflags) +{ + int ret = OK; + + /* Lock the scheduler to prevent the application from running until the + * waitpid() has been called. + */ + + sched_lock(); + + /* Try to find and execute the command within the list of builtin + * applications. + */ + + ret = exec_builtin(cmd, (FAR const char **)argv, redirfile, oflags); + if (ret >= 0) + { + /* The application was successfully started (but still blocked because + * the scheduler is locked). If the application was not backgrounded, + * then we need to wait here for the application to exit. These really + * only works works with the following options: + * + * - CONFIG_NSH_DISABLEBG - Do not run commands in background + * - CONFIG_SCHED_WAITPID - Required to run external commands in + * foreground + * + * These concepts do not apply cleanly to the external applications. + */ + +#ifdef CONFIG_SCHED_WAITPID + + /* CONFIG_SCHED_WAITPID is selected, so we may run the command in + * foreground unless we were specifically requested to run the command + * in background (and running commands in background is enabled). + */ + +# ifndef CONFIG_NSH_DISABLEBG + if (vtbl->np.np_bg == false) +# endif /* CONFIG_NSH_DISABLEBG */ + { + int rc = 0; + + /* Wait for the application to exit. Since we have locked the + * scheduler above, we know that the application has not yet + * started and there is no possibility that it has already exited. + * The scheduler will be unlocked while waitpid is waiting and the + * application will be able to run. + */ + + ret = waitpid(ret, &rc, 0); + if (ret >= 0) + { + /* We can't return the exact status (nsh has nowhere to put it) + * so just pass back zero/nonzero in a fashion that doesn't look + * like an error. + */ + + ret = (rc == 0) ? OK : 1; + + /* TODO: Set the environment variable '?' to a string corresponding + * to WEXITSTATUS(rc) so that $? will expand to the exit status of + * the most recently executed task. + */ + } + } +# ifndef CONFIG_NSH_DISABLEBG + else +# endif /* CONFIG_NSH_DISABLEBG */ +#endif /* CONFIG_SCHED_WAITPID */ + + /* We get here if either: + * + * - CONFIG_SCHED_WAITPID is not selected meaning that all commands + * have to be run in background, or + * - CONFIG_SCHED_WAITPID and CONFIG_NSH_DISABLEBG are both selected, but the + * user requested to run the command in background. + * + * NOTE that the case of a) CONFIG_SCHED_WAITPID is not selected and + * b) CONFIG_NSH_DISABLEBG selected cannot be supported. In that event, all + * commands will have to run in background. The waitpid() API must be + * available to support running the command in foreground. + */ + +#if !defined(CONFIG_SCHED_WAITPID) || !defined(CONFIG_NSH_DISABLEBG) + { + struct sched_param param; + sched_getparam(ret, ¶m); + nsh_output(vtbl, "%s [%d:%d]\n", cmd, ret, param.sched_priority); + + /* Backgrounded commands always 'succeed' as long as we can start + * them. + */ + + ret = OK; + } +#endif /* !CONFIG_SCHED_WAITPID || !CONFIG_NSH_DISABLEBG */ + } + + sched_unlock(); + + /* If exec_builtin() or waitpid() failed, then return -1 (ERROR) with the + * errno value set appropriately. + */ + + if (ret < 0) + { + return ERROR; + } + + return ret; +} + +#endif /* CONFIG_NSH_BUILTIN_APPS */ diff --git a/apps/nshlib/nsh_codeccmd.c b/apps/nshlib/nsh_codeccmd.c index 8c1f5adbd..779fc5ecd 100644 --- a/apps/nshlib/nsh_codeccmd.c +++ b/apps/nshlib/nsh_codeccmd.c @@ -1,538 +1,538 @@ -/**************************************************************************** - * apps/nshlib/nsh_apps.c - * - * This file is part of NuttX, contributed by Darcy Gong - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Darcy Gong 2012-10-30 - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifdef CONFIG_NETUTILS_CODECS - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_NSH_DISABLE_URLENCODE) && defined(CONFIG_NSH_DISABLE_URLDECODE) -# undef CONFIG_CODECS_URLCODE -#endif - -#ifdef CONFIG_CODECS_URLCODE -#include -#endif - -#if defined(CONFIG_NSH_DISABLE_BASE64ENC) && defined(CONFIG_NSH_DISABLE_BASE64ENC) -# undef CONFIG_CODECS_BASE64 -#endif - -#ifdef CONFIG_CODECS_BASE64 -#include -#endif - -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) -#include -#endif - -#include "nsh.h" -#include "nsh_console.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_NSH_CODECS_BUFSIZE -# define CONFIG_NSH_CODECS_BUFSIZE 128 -#endif - -#define CODEC_MODE_URLENCODE 1 -#define CODEC_MODE_URLDECODE 2 -#define CODEC_MODE_BASE64ENC 3 -#define CODEC_MODE_BASE64DEC 4 -#define CODEC_MODE_HASH_MD5 5 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -typedef void (*codec_callback_t)(FAR char *src_buff, int src_buff_len, - FAR char *dst_buff, FAR int *dst_buff_len, - int mode); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: urlencode_cb - ****************************************************************************/ - -#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLENCODE) -static void urlencode_cb(FAR char *src_buff, int src_buff_len, - FAR char *dst_buff, FAR int *dst_buff_len, int mode) -{ - urlencode(src_buff,src_buff_len,dst_buff,dst_buff_len); -} -#endif - -/**************************************************************************** - * Name: urldecode_cb - ****************************************************************************/ - -#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) -static void urldecode_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, - FAR int *dst_buff_len, int mode) -{ - urldecode(src_buff,src_buff_len,dst_buff,dst_buff_len); -} -#endif - -/**************************************************************************** - * Name: b64enc_cb - ****************************************************************************/ - -#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) -static void b64enc_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, - FAR int *dst_buff_len, int mode) -{ - if (mode == 0) - { - //dst_buff = - base64_encode((unsigned char *)src_buff, src_buff_len, - (unsigned char *)dst_buff, (size_t *)dst_buff_len); - } - else - { - //dst_buff = - base64w_encode((unsigned char *)src_buff, src_buff_len, - (unsigned char *)dst_buff, (size_t *)dst_buff_len); - } -} -#endif - -/**************************************************************************** - * Name: b64dec_cb - ****************************************************************************/ - -#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64DEC) -static void b64dec_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, - FAR int *dst_buff_len, int mode) -{ - if (mode == 0) - { - //dst_buff = - base64_decode((unsigned char *)src_buff, src_buff_len, - (unsigned char *)dst_buff, (size_t *)dst_buff_len); - } - else - { - //dst_buff = - base64w_decode((unsigned char *)src_buff, src_buff_len, - (unsigned char *)dst_buff,(size_t *)dst_buff_len); - } -} -#endif - -/**************************************************************************** - * Name: md5_cb - ****************************************************************************/ - -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) -static void md5_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, - FAR int *dst_buff_len, int mode) -{ - MD5Update((MD5_CTX *)dst_buff, (unsigned char *)src_buff, src_buff_len); -} -#endif - -/**************************************************************************** - * Name: calc_codec_buffsize - ****************************************************************************/ - -static int calc_codec_buffsize(int src_buffsize, uint8_t mode) -{ - switch (mode) - { - case CODEC_MODE_URLENCODE: - return src_buffsize*3+1; - case CODEC_MODE_URLDECODE: - return src_buffsize+1; - case CODEC_MODE_BASE64ENC: - return ((src_buffsize + 2)/ 3 * 4)+1; - case CODEC_MODE_BASE64DEC: - return (src_buffsize / 4 * 3 + 2)+1; - case CODEC_MODE_HASH_MD5: - return 32+1; - default: - return src_buffsize+1; - } -} - -/**************************************************************************** - * Name: cmd_codecs_proc - ****************************************************************************/ - -static int cmd_codecs_proc(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv, - uint8_t mode, codec_callback_t func) -{ -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) - static const unsigned char hex_chars[] = "0123456789abcdef"; - MD5_CTX ctx; - unsigned char mac[16]; - char *pSrc; - char *pDest; -#endif - - char *localfile = NULL; - char *src_buffer = NULL; - char *buffer = NULL; - char *fullpath = NULL; - const char *fmt; - char *s_data; - bool badarg = false; - bool is_file = false; - bool is_websafe=false; - int option; - int fd = -1; - int buff_len = 0; - int src_buff_len = 0; - int i = 0; - int ret = OK; - - /* Get the command options */ - - while ((option = getopt(argc, argv, ":fw")) != ERROR) - { - switch (option) - { - case 'f': - is_file = true; - break; - -#ifdef CONFIG_CODECS_BASE64 - case 'w': - is_websafe = true; - - if (!(mode == CODEC_MODE_BASE64ENC || mode == CODEC_MODE_BASE64DEC)) - { - badarg = true; - } - break; -#endif - case ':': - nsh_output(vtbl, g_fmtargrequired, argv[0]); - badarg = true; - break; - - case '?': - default: - nsh_output(vtbl, g_fmtarginvalid, argv[0]); - badarg = true; - break; - } - } - - /* If a bad argument was encountered, then return without processing the command */ - - if (badarg) - { - return ERROR; - } - - /* There should be exactly on parameter left on the command-line */ - - if (optind == argc-1) - { - s_data = argv[optind]; - } - else if (optind >= argc) - { - fmt = g_fmttoomanyargs; - goto errout; - } - else - { - fmt = g_fmtargrequired; - goto errout; - } - -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) - if (mode == CODEC_MODE_HASH_MD5) - { - MD5Init(&ctx); - } -#endif - - if (is_file) - { - /* Get the local file name */ - - localfile = s_data; - - /* Get the full path to the local file */ - - fullpath = nsh_getfullpath(vtbl, localfile); - - /* Open the local file for writing */ - - fd = open(fullpath, O_RDONLY|O_TRUNC, 0644); - if (fd < 0) - { - nsh_output(vtbl, g_fmtcmdfailed, argv[0], "open", NSH_ERRNO); - ret = ERROR; - goto exit; - } - - src_buffer = malloc(CONFIG_NSH_CODECS_BUFSIZE+2); -#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) - if (mode == CODEC_MODE_BASE64ENC) - { - src_buff_len = CONFIG_NSH_CODECS_BUFSIZE / 3 * 3; - } - else -#endif - { - src_buff_len = CONFIG_NSH_CODECS_BUFSIZE; - } - - buff_len = calc_codec_buffsize(src_buff_len+2, mode); - buffer = malloc(buff_len); - while(true) - { - memset(src_buffer, 0, src_buff_len+2); - ret=read(fd, src_buffer, src_buff_len); - if (ret < 0) - { - nsh_output(vtbl, g_fmtcmdfailed, argv[0], "read", NSH_ERRNO); - ret = ERROR; - goto exit; - } - else if(ret==0) - { - break; - } - -#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) - if (mode == CODEC_MODE_URLDECODE) - { - if (src_buffer[src_buff_len-1]=='%') - { - ret += read(fd,&src_buffer[src_buff_len],2); - } - else if (src_buffer[src_buff_len-2]=='%') - { - ret += read(fd,&src_buffer[src_buff_len],1); - } - } -#endif - memset(buffer, 0, buff_len); - if (func) - { -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) - if (mode == CODEC_MODE_HASH_MD5) - { - func(src_buffer, ret, (char *)&ctx, &buff_len,0); - } - else -#endif - { - func(src_buffer, ret, buffer, &buff_len,(is_websafe)?1:0); - nsh_output(vtbl, "%s", buffer); - } - } - - buff_len = calc_codec_buffsize(src_buff_len+2, mode); - } - -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) - if (mode == CODEC_MODE_HASH_MD5) - { - MD5Final(mac, &ctx); - pSrc = (char *)&mac; - pDest = buffer; - for(i=0;i<16;i++,pSrc++) - { - *pDest++ = hex_chars[(*pSrc) >> 4]; - *pDest++ = hex_chars[(*pSrc) & 0x0f]; - } - - *pDest='\0'; - nsh_output(vtbl, "%s\n", buffer); - } -#endif - ret = OK; - goto exit; - } - else - { - src_buffer = s_data; - src_buff_len = strlen(s_data); - buff_len = calc_codec_buffsize(src_buff_len, mode); - buffer = malloc(buff_len); - buffer[0]=0; - if (!buffer) - { - fmt = g_fmtcmdoutofmemory; - goto errout; - } - - memset(buffer, 0, buff_len); - if (func) - { -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) - if (mode == CODEC_MODE_HASH_MD5) - { - func(src_buffer, src_buff_len, (char *)&ctx, &buff_len, 0); - MD5Final(mac, &ctx); - pSrc = (char *)&mac; - pDest = buffer; - for(i=0;i<16;i++,pSrc++) - { - *pDest++ = hex_chars[(*pSrc) >> 4]; - *pDest++ = hex_chars[(*pSrc) & 0x0f]; - } - - *pDest='\0'; - } - else -#endif - { - func(src_buffer, src_buff_len, buffer, &buff_len,(is_websafe)?1:0); - } - } - - nsh_output(vtbl, "%s\n",buffer); - src_buffer = NULL; - goto exit; - } - -exit: - if (fd >= 0) - { - close(fd); - } - - if (fullpath) - { - free(fullpath); - } - - if (src_buffer) - { - free(src_buffer); - } - - if (buffer) - { - free(buffer); - } - - return ret; - -errout: - nsh_output(vtbl, fmt, argv[0]); - ret = ERROR; - goto exit; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: cmd_urlencode - ****************************************************************************/ - -#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLENCODE) -int cmd_urlencode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) -{ - return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_URLENCODE, urlencode_cb); -} -#endif - -/**************************************************************************** - * Name: cmd_urldecode - ****************************************************************************/ - -#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) -int cmd_urldecode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) -{ - return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_URLDECODE, urldecode_cb); -} -#endif - -/**************************************************************************** - * Name: cmd_base64encode - ****************************************************************************/ - -#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) -int cmd_base64encode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) -{ - return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_BASE64ENC, b64enc_cb); -} -#endif - -/**************************************************************************** - * Name: cmd_base64decode - ****************************************************************************/ - -#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64DEC) -int cmd_base64decode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) -{ - return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_BASE64DEC, b64dec_cb); -} -#endif - -/**************************************************************************** - * Name: cmd_md5 - ****************************************************************************/ - -#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) -int cmd_md5(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) -{ - return cmd_codecs_proc(vtbl,argc,argv,CODEC_MODE_HASH_MD5,md5_cb); -} -#endif - -#endif /* CONFIG_NETUTILS_CODECS */ +/**************************************************************************** + * apps/nshlib/nsh_codeccmd.c + * + * This file is part of NuttX, contributed by Darcy Gong + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Darcy Gong 2012-10-30 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifdef CONFIG_NETUTILS_CODECS + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_NSH_DISABLE_URLENCODE) && defined(CONFIG_NSH_DISABLE_URLDECODE) +# undef CONFIG_CODECS_URLCODE +#endif + +#ifdef CONFIG_CODECS_URLCODE +#include +#endif + +#if defined(CONFIG_NSH_DISABLE_BASE64ENC) && defined(CONFIG_NSH_DISABLE_BASE64ENC) +# undef CONFIG_CODECS_BASE64 +#endif + +#ifdef CONFIG_CODECS_BASE64 +#include +#endif + +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) +#include +#endif + +#include "nsh.h" +#include "nsh_console.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_NSH_CODECS_BUFSIZE +# define CONFIG_NSH_CODECS_BUFSIZE 128 +#endif + +#define CODEC_MODE_URLENCODE 1 +#define CODEC_MODE_URLDECODE 2 +#define CODEC_MODE_BASE64ENC 3 +#define CODEC_MODE_BASE64DEC 4 +#define CODEC_MODE_HASH_MD5 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef void (*codec_callback_t)(FAR char *src_buff, int src_buff_len, + FAR char *dst_buff, FAR int *dst_buff_len, + int mode); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: urlencode_cb + ****************************************************************************/ + +#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLENCODE) +static void urlencode_cb(FAR char *src_buff, int src_buff_len, + FAR char *dst_buff, FAR int *dst_buff_len, int mode) +{ + urlencode(src_buff,src_buff_len,dst_buff,dst_buff_len); +} +#endif + +/**************************************************************************** + * Name: urldecode_cb + ****************************************************************************/ + +#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) +static void urldecode_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, + FAR int *dst_buff_len, int mode) +{ + urldecode(src_buff,src_buff_len,dst_buff,dst_buff_len); +} +#endif + +/**************************************************************************** + * Name: b64enc_cb + ****************************************************************************/ + +#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) +static void b64enc_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, + FAR int *dst_buff_len, int mode) +{ + if (mode == 0) + { + //dst_buff = + base64_encode((unsigned char *)src_buff, src_buff_len, + (unsigned char *)dst_buff, (size_t *)dst_buff_len); + } + else + { + //dst_buff = + base64w_encode((unsigned char *)src_buff, src_buff_len, + (unsigned char *)dst_buff, (size_t *)dst_buff_len); + } +} +#endif + +/**************************************************************************** + * Name: b64dec_cb + ****************************************************************************/ + +#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64DEC) +static void b64dec_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, + FAR int *dst_buff_len, int mode) +{ + if (mode == 0) + { + //dst_buff = + base64_decode((unsigned char *)src_buff, src_buff_len, + (unsigned char *)dst_buff, (size_t *)dst_buff_len); + } + else + { + //dst_buff = + base64w_decode((unsigned char *)src_buff, src_buff_len, + (unsigned char *)dst_buff,(size_t *)dst_buff_len); + } +} +#endif + +/**************************************************************************** + * Name: md5_cb + ****************************************************************************/ + +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) +static void md5_cb(FAR char *src_buff, int src_buff_len, FAR char *dst_buff, + FAR int *dst_buff_len, int mode) +{ + MD5Update((MD5_CTX *)dst_buff, (unsigned char *)src_buff, src_buff_len); +} +#endif + +/**************************************************************************** + * Name: calc_codec_buffsize + ****************************************************************************/ + +static int calc_codec_buffsize(int src_buffsize, uint8_t mode) +{ + switch (mode) + { + case CODEC_MODE_URLENCODE: + return src_buffsize*3+1; + case CODEC_MODE_URLDECODE: + return src_buffsize+1; + case CODEC_MODE_BASE64ENC: + return ((src_buffsize + 2)/ 3 * 4)+1; + case CODEC_MODE_BASE64DEC: + return (src_buffsize / 4 * 3 + 2)+1; + case CODEC_MODE_HASH_MD5: + return 32+1; + default: + return src_buffsize+1; + } +} + +/**************************************************************************** + * Name: cmd_codecs_proc + ****************************************************************************/ + +static int cmd_codecs_proc(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv, + uint8_t mode, codec_callback_t func) +{ +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) + static const unsigned char hex_chars[] = "0123456789abcdef"; + MD5_CTX ctx; + unsigned char mac[16]; + char *pSrc; + char *pDest; +#endif + + char *localfile = NULL; + char *src_buffer = NULL; + char *buffer = NULL; + char *fullpath = NULL; + const char *fmt; + char *s_data; + bool badarg = false; + bool is_file = false; + bool is_websafe=false; + int option; + int fd = -1; + int buff_len = 0; + int src_buff_len = 0; + int i = 0; + int ret = OK; + + /* Get the command options */ + + while ((option = getopt(argc, argv, ":fw")) != ERROR) + { + switch (option) + { + case 'f': + is_file = true; + break; + +#ifdef CONFIG_CODECS_BASE64 + case 'w': + is_websafe = true; + + if (!(mode == CODEC_MODE_BASE64ENC || mode == CODEC_MODE_BASE64DEC)) + { + badarg = true; + } + break; +#endif + case ':': + nsh_output(vtbl, g_fmtargrequired, argv[0]); + badarg = true; + break; + + case '?': + default: + nsh_output(vtbl, g_fmtarginvalid, argv[0]); + badarg = true; + break; + } + } + + /* If a bad argument was encountered, then return without processing the command */ + + if (badarg) + { + return ERROR; + } + + /* There should be exactly on parameter left on the command-line */ + + if (optind == argc-1) + { + s_data = argv[optind]; + } + else if (optind >= argc) + { + fmt = g_fmttoomanyargs; + goto errout; + } + else + { + fmt = g_fmtargrequired; + goto errout; + } + +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) + if (mode == CODEC_MODE_HASH_MD5) + { + MD5Init(&ctx); + } +#endif + + if (is_file) + { + /* Get the local file name */ + + localfile = s_data; + + /* Get the full path to the local file */ + + fullpath = nsh_getfullpath(vtbl, localfile); + + /* Open the local file for writing */ + + fd = open(fullpath, O_RDONLY|O_TRUNC, 0644); + if (fd < 0) + { + nsh_output(vtbl, g_fmtcmdfailed, argv[0], "open", NSH_ERRNO); + ret = ERROR; + goto exit; + } + + src_buffer = malloc(CONFIG_NSH_CODECS_BUFSIZE+2); +#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) + if (mode == CODEC_MODE_BASE64ENC) + { + src_buff_len = CONFIG_NSH_CODECS_BUFSIZE / 3 * 3; + } + else +#endif + { + src_buff_len = CONFIG_NSH_CODECS_BUFSIZE; + } + + buff_len = calc_codec_buffsize(src_buff_len+2, mode); + buffer = malloc(buff_len); + while(true) + { + memset(src_buffer, 0, src_buff_len+2); + ret=read(fd, src_buffer, src_buff_len); + if (ret < 0) + { + nsh_output(vtbl, g_fmtcmdfailed, argv[0], "read", NSH_ERRNO); + ret = ERROR; + goto exit; + } + else if(ret==0) + { + break; + } + +#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) + if (mode == CODEC_MODE_URLDECODE) + { + if (src_buffer[src_buff_len-1]=='%') + { + ret += read(fd,&src_buffer[src_buff_len],2); + } + else if (src_buffer[src_buff_len-2]=='%') + { + ret += read(fd,&src_buffer[src_buff_len],1); + } + } +#endif + memset(buffer, 0, buff_len); + if (func) + { +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) + if (mode == CODEC_MODE_HASH_MD5) + { + func(src_buffer, ret, (char *)&ctx, &buff_len,0); + } + else +#endif + { + func(src_buffer, ret, buffer, &buff_len,(is_websafe)?1:0); + nsh_output(vtbl, "%s", buffer); + } + } + + buff_len = calc_codec_buffsize(src_buff_len+2, mode); + } + +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) + if (mode == CODEC_MODE_HASH_MD5) + { + MD5Final(mac, &ctx); + pSrc = (char *)&mac; + pDest = buffer; + for(i=0;i<16;i++,pSrc++) + { + *pDest++ = hex_chars[(*pSrc) >> 4]; + *pDest++ = hex_chars[(*pSrc) & 0x0f]; + } + + *pDest='\0'; + nsh_output(vtbl, "%s\n", buffer); + } +#endif + ret = OK; + goto exit; + } + else + { + src_buffer = s_data; + src_buff_len = strlen(s_data); + buff_len = calc_codec_buffsize(src_buff_len, mode); + buffer = malloc(buff_len); + buffer[0]=0; + if (!buffer) + { + fmt = g_fmtcmdoutofmemory; + goto errout; + } + + memset(buffer, 0, buff_len); + if (func) + { +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) + if (mode == CODEC_MODE_HASH_MD5) + { + func(src_buffer, src_buff_len, (char *)&ctx, &buff_len, 0); + MD5Final(mac, &ctx); + pSrc = (char *)&mac; + pDest = buffer; + for(i=0;i<16;i++,pSrc++) + { + *pDest++ = hex_chars[(*pSrc) >> 4]; + *pDest++ = hex_chars[(*pSrc) & 0x0f]; + } + + *pDest='\0'; + } + else +#endif + { + func(src_buffer, src_buff_len, buffer, &buff_len,(is_websafe)?1:0); + } + } + + nsh_output(vtbl, "%s\n",buffer); + src_buffer = NULL; + goto exit; + } + +exit: + if (fd >= 0) + { + close(fd); + } + + if (fullpath) + { + free(fullpath); + } + + if (src_buffer) + { + free(src_buffer); + } + + if (buffer) + { + free(buffer); + } + + return ret; + +errout: + nsh_output(vtbl, fmt, argv[0]); + ret = ERROR; + goto exit; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cmd_urlencode + ****************************************************************************/ + +#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLENCODE) +int cmd_urlencode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_URLENCODE, urlencode_cb); +} +#endif + +/**************************************************************************** + * Name: cmd_urldecode + ****************************************************************************/ + +#if defined(CONFIG_CODECS_URLCODE) && !defined(CONFIG_NSH_DISABLE_URLDECODE) +int cmd_urldecode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_URLDECODE, urldecode_cb); +} +#endif + +/**************************************************************************** + * Name: cmd_base64encode + ****************************************************************************/ + +#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64ENC) +int cmd_base64encode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_BASE64ENC, b64enc_cb); +} +#endif + +/**************************************************************************** + * Name: cmd_base64decode + ****************************************************************************/ + +#if defined(CONFIG_CODECS_BASE64) && !defined(CONFIG_NSH_DISABLE_BASE64DEC) +int cmd_base64decode(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + return cmd_codecs_proc(vtbl, argc, argv, CODEC_MODE_BASE64DEC, b64dec_cb); +} +#endif + +/**************************************************************************** + * Name: cmd_md5 + ****************************************************************************/ + +#if defined(CONFIG_CODECS_HASH_MD5) && !defined(CONFIG_NSH_DISABLE_MD5) +int cmd_md5(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) +{ + return cmd_codecs_proc(vtbl,argc,argv,CODEC_MODE_HASH_MD5,md5_cb); +} +#endif + +#endif /* CONFIG_NETUTILS_CODECS */ diff --git a/apps/nshlib/nsh_parse.c b/apps/nshlib/nsh_parse.c index 70fa39f62..15723b497 100644 --- a/apps/nshlib/nsh_parse.c +++ b/apps/nshlib/nsh_parse.c @@ -1,7 +1,7 @@ /**************************************************************************** * apps/nshlib/nsh_parse.c * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -72,7 +72,7 @@ /* Argument list size * - * argv[0]: The command name. + * argv[0]: The command name. * argv[1]: The beginning of argument (up to CONFIG_NSH_MAXARGUMENTS) * argv[argc-3]: Possibly '>' or '>>' * argv[argc-2]: Possibly @@ -226,7 +226,7 @@ static const struct cmdmap_s g_cmdmap[] = { "help", cmd_help, 1, 3, "[-v] []" }, # endif #endif - + #if CONFIG_NFILE_DESCRIPTORS > 0 #ifndef CONFIG_NSH_DISABLE_HEXDUMP { "hexdump", cmd_hexdump, 2, 2, "" }, @@ -723,15 +723,11 @@ static int cmd_exit(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) * Name: nsh_execute * * Description: - * Exectue the command in argv[0] + * Execute the command in argv[0] * * Returned Value: - * <0 If exec_builtin() fails, then the negated errno value - * is returned. * -1 (ERRROR) if the command was unsuccessful * 0 (OK) if the command was successful - * 1 if an application task was spawned successfully, but - * returned failure exit status. * ****************************************************************************/ @@ -751,21 +747,6 @@ static int nsh_execute(FAR struct nsh_vtbl_s *vtbl, int argc, char *argv[]) */ cmd = argv[0]; - - /* Try to find a command in the application library. */ - -#ifdef CONFIG_NSH_BUILTIN_APPS - ret = nsh_execapp(vtbl, cmd, argv); - - /* If the built-in application was successfully started, return OK - * or 1 (if the application returned a non-zero exit status). - */ - - if (ret >= 0) - { - return ret; - } -#endif /* See if the command is one that we understand */ @@ -1352,7 +1333,7 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) /* Parse all of the arguments following the command name. The form * of argv is: * - * argv[0]: The command name. + * argv[0]: The command name. * argv[1]: The beginning of argument (up to CONFIG_NSH_MAXARGUMENTS) * argv[argc-3]: Possibly '>' or '>>' * argv[argc-2]: Possibly @@ -1410,6 +1391,47 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) } } + /* Check if the maximum number of arguments was exceeded */ + + if (argc > CONFIG_NSH_MAXARGUMENTS) + { + nsh_output(vtbl, g_fmttoomanyargs, cmd); + } + + /* Does this command correspond to a builtin command? + * nsh_builtin() returns: + * + * -1 (ERROR) if the application task corresponding to 'argv[0]' could not + * be started (possibly because it doesn not exist). + * 0 (OK) if the application task corresponding to 'argv[0]' was + * and successfully started. If CONFIG_SCHED_WAITPID is + * defined, this return value also indicates that the + * application returned successful status (EXIT_SUCCESS) + * 1 If CONFIG_SCHED_WAITPID is defined, then this return value + * indicates that the application task was spawned successfully + * but returned failure exit status. + * + * Note the priority if not effected by nice-ness. + */ + +#ifdef CONFIG_NSH_BUILTIN_APPS + ret = nsh_builtin(vtbl, argv[0], argv, redirfile, oflags); + if (ret >= 0) + { + /* nsh_builtin() returned 0 or 1. This means that the builtin + * command was successfully started (although it may not have ran + * successfully). So certainly it is not an NSH command. + */ + + return nsh_saveresult(vtbl, ret != OK); + } + + /* No, not a built in command (or, at least, we were unable to start a + * builtin command of that name). Treat it like an NSH command. + */ + +#endif + /* Redirected output? */ if (vtbl->np.np_redirect) @@ -1431,23 +1453,13 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) } } - /* Check if the maximum number of arguments was exceeded */ - - if (argc > CONFIG_NSH_MAXARGUMENTS) - { - nsh_output(vtbl, g_fmttoomanyargs, cmd); - } - /* Handle the case where the command is executed in background. * However is app is to be started as builtin new process will - * be created anyway, so skip this step. */ + * be created anyway, so skip this step. + */ #ifndef CONFIG_NSH_DISABLEBG - if (vtbl->np.np_bg -#ifdef CONFIG_NSH_BUILTIN_APPS - && builtin_isavail(argv[0]) < 0 -#endif - ) + if (vtbl->np.np_bg) { struct sched_param param; struct nsh_vtbl_s *bkgvtbl; @@ -1514,6 +1526,7 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) priority = min_priority; } } + param.sched_priority = priority; } @@ -1553,8 +1566,6 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) * * -1 (ERRROR) if the command was unsuccessful * 0 (OK) if the command was successful - * 1 if an application task was spawned successfully, but - * returned failure exit status. */ ret = nsh_execute(vtbl, argc, argv); @@ -1568,11 +1579,11 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) nsh_undirect(vtbl, save); } - /* Treat both errors and non-zero return codes as "errors" so that - * it is possible to test for non-zero returns in nsh scripts. + /* Mark errors so that it is possible to test for non-zero return values + * in nsh scripts. */ - if (ret != OK) + if (ret < 0) { goto errout; } diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index 794b3107d..cec10459a 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -73,7 +73,7 @@ CONFIG_SCHED_WORKPRIORITY=192 CONFIG_SCHED_WORKPERIOD=50000 CONFIG_SCHED_WORKSTACKSIZE=1024 CONFIG_SIG_SIGWORK=17 -CONFIG_SCHED_WAITPID=n +CONFIG_SCHED_WAITPID=y CONFIG_SCHED_ATEXIT=n CONFIG_SCHED_ONEXIT=n @@ -224,6 +224,7 @@ CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 # # Settings for apps/nshlib # +CONFIG_NSH_BUILTIN_APPS=n CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=80 diff --git a/nuttx/configs/vsn/src/README.txt b/nuttx/configs/vsn/src/README.txt index 87a538a10..732ede5e6 100644 --- a/nuttx/configs/vsn/src/README.txt +++ b/nuttx/configs/vsn/src/README.txt @@ -12,8 +12,7 @@ Execution starts in the following order: is set. It must be set for the VSN board. - boot, performs initial chip and board initialization - - sched/os_bringup.c then calls either user_start or exec_builtin() - with application as set in the .config + - sched/os_bringup.c then calls user entry defined in the .config file. Naming throughout the code diff --git a/nuttx/fs/fat/fs_fat32.c b/nuttx/fs/fat/fs_fat32.c index 7164a9f8f..c10c28a5c 100644 --- a/nuttx/fs/fat/fs_fat32.c +++ b/nuttx/fs/fat/fs_fat32.c @@ -1314,15 +1314,16 @@ static int fat_dup(FAR const struct file *oldp, FAR struct file *newp) * file is re-opened. */ - newff->ff_bflags = 0; - newff->ff_oflags = oldff->ff_oflags; - newff->ff_sectorsincluster = oldff->ff_sectorsincluster; - newff->ff_dirindex = oldff->ff_dirindex; - newff->ff_currentcluster = oldff->ff_currentcluster; - newff->ff_dirsector = oldff->ff_dirsector; - newff->ff_size = oldff->ff_size; - newff->ff_currentsector = 0; - newff->ff_cachesector = 0; + newff->ff_bflags = 0; /* File buffer flags */ + newff->ff_oflags = oldff->ff_oflags; /* File open flags */ + newff->ff_sectorsincluster = oldff->ff_sectorsincluster; /* Sectors remaining in cluster */ + newff->ff_dirindex = oldff->ff_dirindex; /* Index to directory entry */ + newff->ff_currentcluster = oldff->ff_currentcluster; /* Current cluster */ + newff->ff_dirsector = oldff->ff_dirsector; /* Sector containing directory entry */ + newff->ff_size = oldff->ff_size; /* Size of the file */ + newff->ff_startcluster = oldff->ff_startcluster; /* Start cluster of file on media */ + newff->ff_currentsector = oldff->ff_currentsector; /* Current sector */ + newff->ff_cachesector = 0; /* Sector in file buffer */ /* Attach the private date to the struct file instance */ diff --git a/nuttx/fs/romfs/fs_romfs.c b/nuttx/fs/romfs/fs_romfs.c index 2814aa49d..6a6fca355 100644 --- a/nuttx/fs/romfs/fs_romfs.c +++ b/nuttx/fs/romfs/fs_romfs.c @@ -56,6 +56,7 @@ #include #include +#include #include #include #include @@ -225,7 +226,7 @@ static int romfs_open(FAR struct file *filep, FAR const char *relpath, * file. */ - rf = (FAR struct romfs_file_s *)zalloc(sizeof(struct romfs_file_s)); + rf = (FAR struct romfs_file_s *)kzalloc(sizeof(struct romfs_file_s)); if (!rf) { fdbg("Failed to allocate private data\n", ret); @@ -317,12 +318,12 @@ static int romfs_close(FAR struct file *filep) if (!rm->rm_xipbase && rf->rf_buffer) { - free(rf->rf_buffer); + kfree(rf->rf_buffer); } /* Then free the file structure itself. */ - free(rf); + kfree(rf); filep->f_priv = NULL; return ret; } @@ -915,7 +916,7 @@ static int romfs_bind(FAR struct inode *blkdriver, FAR const void *data, /* Create an instance of the mountpt state structure */ - rm = (FAR struct romfs_mountpt_s *)zalloc(sizeof(struct romfs_mountpt_s)); + rm = (FAR struct romfs_mountpt_s *)kzalloc(sizeof(struct romfs_mountpt_s)); if (!rm) { fdbg("Failed to allocate mountpoint structure\n"); @@ -959,12 +960,12 @@ static int romfs_bind(FAR struct inode *blkdriver, FAR const void *data, errout_with_buffer: if (!rm->rm_xipbase) { - free(rm->rm_buffer); + kfree(rm->rm_buffer); } errout_with_sem: sem_destroy(&rm->rm_sem); - free(rm); + kfree(rm); return ret; } @@ -1031,11 +1032,11 @@ static int romfs_unbind(FAR void *handle, FAR struct inode **blkdriver) if (!rm->rm_xipbase && rm->rm_buffer) { - free(rm->rm_buffer); + kfree(rm->rm_buffer); } sem_destroy(&rm->rm_sem); - free(rm); + kfree(rm); return OK; } -- cgit v1.2.3 From 77efc9f9cdd5828ab724b3355f0f0737bb15b579 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 16 Jan 2013 14:14:14 +0000 Subject: BINFS now supports open, close, and FIOC_FILENAME ioctl git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5522 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 4 + apps/builtin/binfs.c | 331 +++++++++------------------------------ apps/include/apps.h | 3 + nuttx/TODO | 21 ++- nuttx/binfmt/binfmt_execmodule.c | 14 +- nuttx/fs/nfs/nfs_vfsops.c | 61 +++++--- nuttx/fs/nxffs/nxffs_open.c | 3 +- nuttx/include/nuttx/fs/binfs.h | 80 ++++++++++ nuttx/include/nuttx/fs/ioctl.h | 1 + 9 files changed, 216 insertions(+), 302 deletions(-) create mode 100644 nuttx/include/nuttx/fs/binfs.h diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index ea4fcd07b..f91dc318b 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -469,3 +469,7 @@ * builtin/binfs.c: Add hooks for dup() method (not implemented). * builtin/exec_builtin.c, nshlib/nsh_parse.c, and nshlib/nsh_builtin.c: NSH now supports re-direction of I/O to files (but still not from). + * builtin/binfs.c: Greatly simplified (it is going to need to be + very lightweight). Now supports open, close, and a new ioctl to recover + the builtin filename. The latter will be needed to support a binfs + binfmt. diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c index 1fc2e7940..611e2b3bb 100644 --- a/apps/builtin/binfs.c +++ b/apps/builtin/binfs.c @@ -45,7 +45,6 @@ #include #include -#include #include #include #include @@ -53,8 +52,11 @@ #include #include +#include #include +#include + #include "builtin.h" #if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_APPS_BINDIR) @@ -63,24 +65,12 @@ * Private Types ****************************************************************************/ -/* This structure represents the overall mountpoint state. An instance of this - * structure is retained as inode private data on each mountpoint that is - * mounted with a fat32 filesystem. - */ - -struct binfs_state_s -{ - sem_t bm_sem; /* Used to assume thread-safe access */ -}; - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void binfs_semtake(struct binfs_state_s *bm); -static inline void binfs_semgive(struct binfs_state_s *bm); static int binfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode); + int oflags, mode_t mode); static int binfs_close(FAR struct file *filep); static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); @@ -89,15 +79,19 @@ static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int binfs_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir); -static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); -static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir); +static int binfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); +static int binfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); -static int binfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle); -static int binfs_unbind(void *handle, FAR struct inode **blkdriver); -static int binfs_statfs(struct inode *mountpt, struct statfs *buf); +static int binfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle); +static int binfs_unbind(FAR void *handle, FAR struct inode **blkdriver); +static int binfs_statfs(FAR struct inode *mountpt, + FAR struct statfs *buf); -static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf); +static int binfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf); /**************************************************************************** * Private Variables @@ -144,71 +138,42 @@ const struct mountpt_operations binfs_operations = * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: binfs_semtake - ****************************************************************************/ - -static void binfs_semtake(struct binfs_state_s *bm) -{ - /* Take the semaphore (perhaps waiting) */ - - while (sem_wait(&bm->bm_sem) != 0) - { - /* The only case that an error should occur here is if - * the wait was awakened by a signal. - */ - - ASSERT(errno == EINTR); - } -} - -/**************************************************************************** - * Name: binfs_semgive - ****************************************************************************/ - -static inline void binfs_semgive(struct binfs_state_s *bm) -{ - sem_post(&bm->bm_sem); -} - /**************************************************************************** * Name: binfs_open ****************************************************************************/ -static int binfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode) +static int binfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode) { - struct binfs_state_s *bm; - int ret = -ENOSYS; + int index; fvdbg("Open '%s'\n", relpath); - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv == NULL && filep->f_inode != NULL); - - /* mountpoint private data from the inode reference from the file - * structure - */ - - bm = (struct binfs_state_s*)filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - /* BINFS is read-only. Any attempt to open with any kind of write * access is not permitted. */ if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0) { - fdbg("Only O_RDONLY supported\n"); - ret = -EACCES; + fdbg("ERROR: Only O_RDONLY supported\n"); + return -EACCES; } - /* Save open-specific state in filep->f_priv */ + /* Check if the an entry exists with this name in the root directory. + * so the 'relpath' must be the name of the builtin function. + */ - /* Opening of elements within the pseudo-file system is not yet supported */ + index = builtin_isavail(relpath); + if (index < 0) + { + fdbg("ERROR: Builting %s does not exist\n", relpath); + return -ENOENT; + } - return ret; + /* Save the index as the open-specific state in filep->f_priv */ + + filep->f_priv = (FAR void *)index; + return OK; } /**************************************************************************** @@ -217,31 +182,8 @@ static int binfs_open(FAR struct file *filep, const char *relpath, static int binfs_close(FAR struct file *filep) { - struct binfs_state_s *bm; - int ret = -ENOSYS; - fvdbg("Closing\n"); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state from the struct file instance */ - /* bf = filep->f_priv; */ - - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* Free the open file state */ - /* free(bf); */ - - filep->f_priv = NULL; - - /* Since open() is not yet supported, neither is close(). */ - - return ret; + return OK; } /**************************************************************************** @@ -250,25 +192,10 @@ static int binfs_close(FAR struct file *filep) static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) { - struct binfs_state_s *bm; + /* Reading is not supported. Just return end-of-file */ fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); - - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state data from the struct file instance */ - /* bf = filep->f_priv; */ - - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* Since open is not yet supported, neither is reading */ - - return -ENOSYS; + return 0; } /**************************************************************************** @@ -277,25 +204,36 @@ static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { - struct binfs_state_s *bm; + int ret; fvdbg("cmd: %d arg: %08lx\n", cmd, arg); - /* Sanity checks */ - - DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); - - /* Recover the open file state from the struct file instance */ - /* bf = filep->f_priv; */ + /* Only one IOCTL command is supported */ - /* Recover the file system state from the inode */ - - bm = filep->f_inode->i_private; - DEBUGASSERT(bm != NULL); + if (cmd == FIOC_FILENAME) + { + /* IN: FAR char const ** pointer + * OUT: Pointer to a persistent file name (Guaranteed to persist while + * the file is open). + */ - /* No ioctl commands yet supported */ + FAR const char **ptr = (FAR const char **)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + } + else + { + *ptr = g_builtins[(int)filep->f_priv].name; + ret = OK; + } + } + else + { + ret = -ENOTTY; + } - return -ENOTTY; + return ret; } /**************************************************************************** @@ -308,27 +246,12 @@ static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp) { - struct binfs_state_s *bm; - int ret = -ENOSYS; - fvdbg("Dup %p->%p\n", oldp, newp); - /* Sanity checks */ - - DEBUGASSERT(oldp->f_priv == NULL && oldp->f_inode != NULL); - - /* mountpoint private data from the inode reference from the file - * structure - */ - - bm = (struct binfs_state_s*)oldp->f_inode->i_private; - DEBUGASSERT(bm != NULL); - - /* Opening of elements within the pseudo-file system is not yet supported - * and, hence, neither is dup'ing the opened file. - */ + /* Copy the index from the old to the new file structure */ - return ret; + newp->f_priv = oldp->f_priv; + return OK; } /**************************************************************************** @@ -342,36 +265,19 @@ static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp) static int binfs_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir) { - struct binfs_state_s *bm; - int ret; - fvdbg("relpath: \"%s\"\n", relpath ? relpath : "NULL"); - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - /* The requested directory must be the volume-relative "root" directory */ if (relpath && relpath[0] != '\0') { - ret = -ENOENT; - goto errout_with_semaphore; + return -ENOENT; } /* Set the index to the first entry */ dir->u.binfs.fb_index = 0; - ret = OK; - -errout_with_semaphore: - binfs_semgive(bm); - return ret; + return OK; } /**************************************************************************** @@ -383,19 +289,9 @@ errout_with_semaphore: static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) { - struct binfs_state_s *bm; unsigned int index; int ret; - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - /* Have we reached the end of the directory */ index = dir->u.binfs.fb_index; @@ -426,11 +322,10 @@ static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) * standard f_pos instead of our own private fb_index. */ - dir->u.binfs.fb_index = index; - ret = OK; + dir->u.binfs.fb_index = index; + ret = OK; } - binfs_semgive(bm); return ret; } @@ -443,22 +338,9 @@ static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) { - struct binfs_state_s *bm; - fvdbg("Entry\n"); - /* Sanity checks */ - - DEBUGASSERT(mountpt != NULL && mountpt->i_private != NULL); - - /* Recover the file system state from the inode instance */ - - bm = mountpt->i_private; - binfs_semtake(bm); - - dir->u.binfs.fb_index = 0; - - binfs_semgive(bm); + dir->u.binfs.fb_index = 0; return OK; } @@ -476,29 +358,7 @@ static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) static int binfs_bind(FAR struct inode *blkdriver, const void *data, void **handle) { - struct binfs_state_s *bm; - fvdbg("Entry\n"); - - /* Create an instance of the mountpt state structure */ - - bm = (struct binfs_state_s *)zalloc(sizeof(struct binfs_state_s)); - if (!bm) - { - fdbg("Failed to allocate mountpoint structure\n"); - return -ENOMEM; - } - - /* Initialize the allocated mountpt state structure. The filesystem is - * responsible for one reference ont the blkdriver inode and does not - * have to addref() here (but does have to release in ubind(). - */ - - sem_init(&bm->bm_sem, 0, 1); /* Initialize the semaphore that controls access */ - - /* Mounted! */ - - *handle = (void*)bm; return OK; } @@ -512,22 +372,7 @@ static int binfs_bind(FAR struct inode *blkdriver, const void *data, static int binfs_unbind(void *handle, FAR struct inode **blkdriver) { - struct binfs_state_s *bm = (struct binfs_state_s*)handle; - fvdbg("Entry\n"); - -#ifdef CONFIG_DEBUG - if (!bm) - { - return -EINVAL; - } -#endif - - /* Check if there are sill any files opened on the filesystem. */ - - /* Release the mountpoint private data */ - - sem_destroy(&bm->bm_sem); return OK; } @@ -540,19 +385,8 @@ static int binfs_unbind(void *handle, FAR struct inode **blkdriver) static int binfs_statfs(struct inode *mountpt, struct statfs *buf) { - struct binfs_state_s *bm; - fvdbg("Entry\n"); - /* Sanity checks */ - - DEBUGASSERT(mountpt && mountpt->i_private); - - /* Get the mountpoint private data from the inode structure */ - - bm = mountpt->i_private; - binfs_semtake(bm); - /* Fill in the statfs info */ memset(buf, 0, sizeof(struct statfs)); @@ -562,8 +396,6 @@ static int binfs_statfs(struct inode *mountpt, struct statfs *buf) buf->f_bfree = 0; buf->f_bavail = 0; buf->f_namelen = NAME_MAX; - - binfs_semgive(bm); return OK; } @@ -576,20 +408,8 @@ static int binfs_statfs(struct inode *mountpt, struct statfs *buf) static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) { - struct binfs_state_s *bm; - int ret; - fvdbg("Entry\n"); - /* Sanity checks */ - - DEBUGASSERT(mountpt && mountpt->i_private); - - /* Get the mountpoint private data from the inode structure */ - - bm = mountpt->i_private; - binfs_semtake(bm); - /* The requested directory must be the volume-relative "root" directory */ if (relpath && relpath[0] != '\0') @@ -598,8 +418,7 @@ static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *b if (builtin_isavail(relpath) < 0) { - ret = -ENOENT; - goto errout_with_semaphore; + return -ENOENT; } /* It's a execute-only file name */ @@ -615,14 +434,10 @@ static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *b /* File/directory size, access block size */ - buf->st_size = 0; - buf->st_blksize = 0; - buf->st_blocks = 0; - ret = OK; - -errout_with_semaphore: - binfs_semgive(bm); - return ret; + buf->st_size = 0; + buf->st_blksize = 0; + buf->st_blocks = 0; + return OK; } /**************************************************************************** diff --git a/apps/include/apps.h b/apps/include/apps.h index f806d8aed..9f1918e57 100644 --- a/apps/include/apps.h +++ b/apps/include/apps.h @@ -48,9 +48,12 @@ ****************************************************************************/ #include + #include #include +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/nuttx/TODO b/nuttx/TODO index 58ca4cc8e..248d2dafa 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (11) Task/Scheduler (sched/) + (10) Task/Scheduler (sched/) (1) Memory Managment (mm/) (3) Signals (sched/, arch/) (2) pthreads (sched/) @@ -58,16 +58,6 @@ o Task/Scheduler (sched/) Status: Closed. No, this behavior will not be implemented. Priority: Medium, required for good emulation of process/pthread model. - Title: MISSING ERRNO SETTINGS - Description: Several APIs do not set errno. Need to review all APIs. - Update: These are being fixed as they are encountered. There is - no accounting of how many interfaces have this problem. - Status: Open? There has been an effort over the past few years to assure - that all errno settings are in place. What is the current state? - Unknown. - Priority: Medium, required for standard compliance (but makes the - code bigger) - Title: TICKLESS OS Description: On a side note, I have thought about a tick-less timer for the OS for a long time. Basically we could replace the periodic system @@ -178,7 +168,14 @@ o Task/Scheduler (sched/) You would think that this should be a clone of the existing pthread join logic. Howver there is no need for zombies - in NuttX so, the status if the parent has already exit'ed. + in NuttX so no need to keep the status if the parent has + already exit'ed. Other simplifications: + + 1. Keep the array/list of return status in the parent + tasks TCB. + 2. Use a fixed size array of return status (perhaps the + the enire array is allocated so that that is con + penalty for tasks that have no childre. At present, exit status is not retained. If waitpid() is called after the child task has exit'ed it simpley diff --git a/nuttx/binfmt/binfmt_execmodule.c b/nuttx/binfmt/binfmt_execmodule.c index 400451c40..df8da5343 100644 --- a/nuttx/binfmt/binfmt_execmodule.c +++ b/nuttx/binfmt/binfmt_execmodule.c @@ -1,7 +1,7 @@ /**************************************************************************** * binfmt/binfmt_execmodule.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,6 +47,7 @@ #include #include +#include #include #include "os_internal.h" @@ -167,7 +168,7 @@ int exec_module(FAR const struct binary_s *binp, int priority) /* Allocate a TCB for the new task. */ - tcb = (FAR _TCB*)zalloc(sizeof(_TCB)); + tcb = (FAR _TCB*)kzalloc(sizeof(_TCB)); if (!tcb) { err = ENOMEM; @@ -177,7 +178,7 @@ int exec_module(FAR const struct binary_s *binp, int priority) /* Allocate the stack for the new task */ #ifndef CONFIG_CUSTOM_STACK - stack = (FAR uint32_t*)malloc(binp->stacksize); + stack = (FAR uint32_t*)kmalloc(binp->stacksize); if (!tcb) { err = ENOMEM; @@ -201,6 +202,9 @@ int exec_module(FAR const struct binary_s *binp, int priority) goto errout_with_stack; } + /* Note that tcb->flags are not modified. 0=normal task */ + /* tcb->flags |= TCB_FLAG_TTYPE_TASK; */ + /* Add the D-Space address as the PIC base address. By convention, this * must be the first allocated address space. */ @@ -257,14 +261,14 @@ errout_with_stack: #ifndef CONFIG_CUSTOM_STACK tcb->stack_alloc_ptr = NULL; sched_releasetcb(tcb); - free(stack); + kfree(stack); #else sched_releasetcb(tcb); #endif goto errout; errout_with_tcb: - free(tcb); + kfree(tcb); errout: errno = err; bdbg("returning errno: %d\n", err); diff --git a/nuttx/fs/nfs/nfs_vfsops.c b/nuttx/fs/nfs/nfs_vfsops.c index 01e999ac8..2ff4ff9d3 100644 --- a/nuttx/fs/nfs/nfs_vfsops.c +++ b/nuttx/fs/nfs/nfs_vfsops.c @@ -680,6 +680,7 @@ static int nfs_close(FAR struct file *filep) FAR struct nfsnode *np; FAR struct nfsnode *prev; FAR struct nfsnode *curr; + int ret; /* Sanity checks */ @@ -703,8 +704,7 @@ static int nfs_close(FAR struct file *filep) if (np->n_crefs > 1) { np->n_crefs--; - nfs_semgive(nmp); - return OK; + ret = OK; } /* There are no more references to the file structure. Now we need to @@ -714,38 +714,47 @@ static int nfs_close(FAR struct file *filep) * containted in the mount structure. */ - for (prev = NULL, curr = nmp->nm_head; curr; prev = curr, curr = curr->n_next) - { - /* Check if this node is ours */ + else + { + /* Assume file structure will not be found. This should never happen. */ + + ret = -EINVAL; - if (np == curr) - { - /* Yes.. remove it from the list of file structures */ + for (prev = NULL, curr = nmp->nm_head; + curr; + prev = curr, curr = curr->n_next) + { + /* Check if this node is ours */ + + if (np == curr) + { + /* Yes.. remove it from the list of file structures */ - if (prev) - { - /* Remove from mid-list */ + if (prev) + { + /* Remove from mid-list */ - prev->n_next = np->n_next; - } - else - { - /* Remove from the head of the list */ + prev->n_next = np->n_next; + } + else + { + /* Remove from the head of the list */ - nmp->nm_head = np->n_next; - } + nmp->nm_head = np->n_next; + } - /* Then deallocate the file structure and return success */ + /* Then deallocate the file structure and return success */ - kfree(np); - nfs_semgive(nmp); - return OK; - } - } + kfree(np); + ret = OK; + break; + } + } + } - fdbg("ERROR: file structure not found in list: %p\n", np); + filep->f_priv = NULL; nfs_semgive(nmp); - return EINVAL; + return ret; } /**************************************************************************** diff --git a/nuttx/fs/nxffs/nxffs_open.c b/nuttx/fs/nxffs/nxffs_open.c index b1e99267f..9fa4ef2e0 100644 --- a/nuttx/fs/nxffs/nxffs_open.c +++ b/nuttx/fs/nxffs/nxffs_open.c @@ -1188,9 +1188,10 @@ int nxffs_close(FAR struct file *filep) ofile->crefs--; } - filep->f_priv = NULL; + filep->f_priv = NULL; sem_post(&volume->exclsem); + errout: return ret; } diff --git a/nuttx/include/nuttx/fs/binfs.h b/nuttx/include/nuttx/fs/binfs.h new file mode 100644 index 000000000..6125384a9 --- /dev/null +++ b/nuttx/include/nuttx/fs/binfs.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * include/nuttx/fs/binfs.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_FS_BINFS_H +#define __INCLUDE_NUTTX_FS_BINFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* This is the BINFS ioctl that can be used to recover the filename + * associated with the builtin task. + */ + +#define FIOC_FILENAME FIOC_USER /* IN: FAR const char ** pointer + * OUT: Pointer to a persistent file name + * (Guaranteed to persist while the file + * is open). + */ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_FS_BINFS_H */ diff --git a/nuttx/include/nuttx/fs/ioctl.h b/nuttx/include/nuttx/fs/ioctl.h index 19f29b1fb..8f2fdd7d9 100644 --- a/nuttx/include/nuttx/fs/ioctl.h +++ b/nuttx/include/nuttx/fs/ioctl.h @@ -105,6 +105,7 @@ #define FIOC_OPTIMIZE _FIOC(0x0003) /* IN: None * OUT: None */ +#define FIOC_USER _FIOC(0x0004) /* File system-specific */ /* NuttX file system ioctl definitions **************************************/ -- cgit v1.2.3 From 4f7967b4c678bef1a42eda3acf739c8bbefd9a07 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 16 Jan 2013 15:41:27 +0000 Subject: apps/builtin/binfs.c moved to nuttx/fs/binfs/fs_binfs.c git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5523 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/builtin/Kconfig | 14 -- apps/builtin/Makefile | 4 - apps/builtin/binfs.c | 448 ----------------------------------- apps/builtin/builtin.c | 2 + apps/builtin/builtin.h | 77 ------ apps/builtin/exec_builtin.c | 3 +- apps/include/apps.h | 17 -- apps/nshlib/nsh_mntcmds.c | 2 +- nuttx/ChangeLog | 3 +- nuttx/configs/sim/README.txt | 7 +- nuttx/configs/sim/nsh/appconfig | 3 + nuttx/configs/sim/nsh/defconfig | 12 +- nuttx/configs/vsn/nsh/defconfig | 2 +- nuttx/fs/Kconfig | 3 +- nuttx/fs/Makefile | 15 +- nuttx/fs/binfs/Kconfig | 19 ++ nuttx/fs/binfs/Make.defs | 48 ++++ nuttx/fs/binfs/fs_binfs.c | 447 ++++++++++++++++++++++++++++++++++ nuttx/fs/fat/Make.defs | 9 +- nuttx/fs/fs_mount.c | 13 +- nuttx/fs/mmap/Make.defs | 9 +- nuttx/fs/nfs/Make.defs | 9 +- nuttx/fs/nxffs/Make.defs | 9 +- nuttx/fs/romfs/Make.defs | 9 +- nuttx/include/nuttx/binfmt/builtin.h | 85 +++++++ nuttx/include/nuttx/fs/binfs.h | 16 +- nuttx/include/nuttx/fs/dirent.h | 6 +- nuttx/tools/mkconfig.c | 6 +- 29 files changed, 694 insertions(+), 605 deletions(-) delete mode 100644 apps/builtin/binfs.c delete mode 100644 apps/builtin/builtin.h create mode 100644 nuttx/fs/binfs/Kconfig create mode 100644 nuttx/fs/binfs/Make.defs create mode 100644 nuttx/fs/binfs/fs_binfs.c create mode 100644 nuttx/include/nuttx/binfmt/builtin.h diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index f91dc318b..5bc3b2149 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -473,3 +473,5 @@ very lightweight). Now supports open, close, and a new ioctl to recover the builtin filename. The latter will be needed to support a binfs binfmt. + * builtin/binfs.c: Move apps/builtin/binfs.c to fs/binfs/fs_binfs.c + CONFIG_APPS_BINDIR rename CONFIG_FS_BINFS diff --git a/apps/builtin/Kconfig b/apps/builtin/Kconfig index 1049712aa..37150e8a9 100644 --- a/apps/builtin/Kconfig +++ b/apps/builtin/Kconfig @@ -13,20 +13,6 @@ config BUILTIN if BUILTIN - config APPS_BINDIR - bool "BINFS File System" - default n - ---help--- - The BINFS file system is current just a toy. The BINFS may, for example, - be mount at /bin. Then all of the built-in applications will appear as - executable file in /bin if you list them from NSH like: - - nsh> ls -l /bin - - At present, the BINFS supports nothing more than that. It is planned, - however, to support execution of the builtin applications from BINFS as - well (via a binfmt/ loader). However, that is down the road. - config BUILTIN_PROXY_STACKSIZE int "Builtin Proxy Stack Size" default 1024 diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index 8c8928886..d77054f41 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -41,10 +41,6 @@ include $(APPDIR)/Make.defs ASRCS = CSRCS = builtin.c exec_builtin.c -ifeq ($(CONFIG_APPS_BINDIR),y) -CSRCS += binfs.c -endif - AOBJS = $(ASRCS:.S=$(OBJEXT)) COBJS = $(CSRCS:.c=$(OBJEXT)) diff --git a/apps/builtin/binfs.c b/apps/builtin/binfs.c deleted file mode 100644 index 611e2b3bb..000000000 --- a/apps/builtin/binfs.c +++ /dev/null @@ -1,448 +0,0 @@ -/**************************************************************************** - * apps/builtin/binfs.c - * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "builtin.h" - -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_APPS_BINDIR) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int binfs_open(FAR struct file *filep, const char *relpath, - int oflags, mode_t mode); -static int binfs_close(FAR struct file *filep); -static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); -static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); - -static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp); - -static int binfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir); -static int binfs_readdir(FAR struct inode *mountpt, - FAR struct fs_dirent_s *dir); -static int binfs_rewinddir(FAR struct inode *mountpt, - FAR struct fs_dirent_s *dir); - -static int binfs_bind(FAR struct inode *blkdriver, FAR const void *data, - FAR void **handle); -static int binfs_unbind(FAR void *handle, FAR struct inode **blkdriver); -static int binfs_statfs(FAR struct inode *mountpt, - FAR struct statfs *buf); - -static int binfs_stat(FAR struct inode *mountpt, FAR const char *relpath, - FAR struct stat *buf); - -/**************************************************************************** - * Private Variables - ****************************************************************************/ - -/**************************************************************************** - * Public Variables - ****************************************************************************/ - -/* See fs_mount.c -- this structure is explicitly externed there. - * We use the old-fashioned kind of initializers so that this will compile - * with any compiler. - */ - -const struct mountpt_operations binfs_operations = -{ - binfs_open, /* open */ - binfs_close, /* close */ - binfs_read, /* read */ - NULL, /* write */ - NULL, /* seek */ - binfs_ioctl, /* ioctl */ - - NULL, /* sync */ - binfs_dup, /* dup */ - - binfs_opendir, /* opendir */ - NULL, /* closedir */ - binfs_readdir, /* readdir */ - binfs_rewinddir, /* rewinddir */ - - binfs_bind, /* bind */ - binfs_unbind, /* unbind */ - binfs_statfs, /* statfs */ - - NULL, /* unlink */ - NULL, /* mkdir */ - NULL, /* rmdir */ - NULL, /* rename */ - binfs_stat /* stat */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: binfs_open - ****************************************************************************/ - -static int binfs_open(FAR struct file *filep, FAR const char *relpath, - int oflags, mode_t mode) -{ - int index; - - fvdbg("Open '%s'\n", relpath); - - /* BINFS is read-only. Any attempt to open with any kind of write - * access is not permitted. - */ - - if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0) - { - fdbg("ERROR: Only O_RDONLY supported\n"); - return -EACCES; - } - - /* Check if the an entry exists with this name in the root directory. - * so the 'relpath' must be the name of the builtin function. - */ - - index = builtin_isavail(relpath); - if (index < 0) - { - fdbg("ERROR: Builting %s does not exist\n", relpath); - return -ENOENT; - } - - /* Save the index as the open-specific state in filep->f_priv */ - - filep->f_priv = (FAR void *)index; - return OK; -} - -/**************************************************************************** - * Name: binfs_close - ****************************************************************************/ - -static int binfs_close(FAR struct file *filep) -{ - fvdbg("Closing\n"); - return OK; -} - -/**************************************************************************** - * Name: binfs_read - ****************************************************************************/ - -static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) -{ - /* Reading is not supported. Just return end-of-file */ - - fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); - return 0; -} - -/**************************************************************************** - * Name: binfs_ioctl - ****************************************************************************/ - -static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) -{ - int ret; - - fvdbg("cmd: %d arg: %08lx\n", cmd, arg); - - /* Only one IOCTL command is supported */ - - if (cmd == FIOC_FILENAME) - { - /* IN: FAR char const ** pointer - * OUT: Pointer to a persistent file name (Guaranteed to persist while - * the file is open). - */ - - FAR const char **ptr = (FAR const char **)((uintptr_t)arg); - if (ptr == NULL) - { - ret = -EINVAL; - } - else - { - *ptr = g_builtins[(int)filep->f_priv].name; - ret = OK; - } - } - else - { - ret = -ENOTTY; - } - - return ret; -} - -/**************************************************************************** - * Name: binfs_dup - * - * Description: - * Duplicate open file data in the new file structure. - * - ****************************************************************************/ - -static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp) -{ - fvdbg("Dup %p->%p\n", oldp, newp); - - /* Copy the index from the old to the new file structure */ - - newp->f_priv = oldp->f_priv; - return OK; -} - -/**************************************************************************** - * Name: binfs_opendir - * - * Description: - * Open a directory for read access - * - ****************************************************************************/ - -static int binfs_opendir(struct inode *mountpt, const char *relpath, - struct fs_dirent_s *dir) -{ - fvdbg("relpath: \"%s\"\n", relpath ? relpath : "NULL"); - - /* The requested directory must be the volume-relative "root" directory */ - - if (relpath && relpath[0] != '\0') - { - return -ENOENT; - } - - /* Set the index to the first entry */ - - dir->u.binfs.fb_index = 0; - return OK; -} - -/**************************************************************************** - * Name: binfs_readdir - * - * Description: Read the next directory entry - * - ****************************************************************************/ - -static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) -{ - unsigned int index; - int ret; - - /* Have we reached the end of the directory */ - - index = dir->u.binfs.fb_index; - if (g_builtins[index].name == NULL) - { - /* We signal the end of the directory by returning the - * special error -ENOENT - */ - - fvdbg("Entry %d: End of directory\n", index); - ret = -ENOENT; - } - else - { - /* Save the filename and file type */ - - fvdbg("Entry %d: \"%s\"\n", index, g_builtins[index].name); - dir->fd_dir.d_type = DTYPE_FILE; - strncpy(dir->fd_dir.d_name, g_builtins[index].name, NAME_MAX+1); - - /* The application list is terminated by an entry with a NULL name. - * Therefore, there is at least one more entry in the list. - */ - - index++; - - /* Set up the next directory entry offset. NOTE that we could use the - * standard f_pos instead of our own private fb_index. - */ - - dir->u.binfs.fb_index = index; - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: binfs_rewindir - * - * Description: Reset directory read to the first entry - * - ****************************************************************************/ - -static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) -{ - fvdbg("Entry\n"); - - dir->u.binfs.fb_index = 0; - return OK; -} - -/**************************************************************************** - * Name: binfs_bind - * - * Description: This implements a portion of the mount operation. This - * function allocates and initializes the mountpoint private data and - * binds the blockdriver inode to the filesystem private data. The final - * binding of the private data (containing the blockdriver) to the - * mountpoint is performed by mount(). - * - ****************************************************************************/ - -static int binfs_bind(FAR struct inode *blkdriver, const void *data, - void **handle) -{ - fvdbg("Entry\n"); - return OK; -} - -/**************************************************************************** - * Name: binfs_unbind - * - * Description: This implements the filesystem portion of the umount - * operation. - * - ****************************************************************************/ - -static int binfs_unbind(void *handle, FAR struct inode **blkdriver) -{ - fvdbg("Entry\n"); - return OK; -} - -/**************************************************************************** - * Name: binfs_statfs - * - * Description: Return filesystem statistics - * - ****************************************************************************/ - -static int binfs_statfs(struct inode *mountpt, struct statfs *buf) -{ - fvdbg("Entry\n"); - - /* Fill in the statfs info */ - - memset(buf, 0, sizeof(struct statfs)); - buf->f_type = BINFS_MAGIC; - buf->f_bsize = 0; - buf->f_blocks = 0; - buf->f_bfree = 0; - buf->f_bavail = 0; - buf->f_namelen = NAME_MAX; - return OK; -} - -/**************************************************************************** - * Name: binfs_stat - * - * Description: Return information about a file or directory - * - ****************************************************************************/ - -static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) -{ - fvdbg("Entry\n"); - - /* The requested directory must be the volume-relative "root" directory */ - - if (relpath && relpath[0] != '\0') - { - /* Check if there is a file with this name. */ - - if (builtin_isavail(relpath) < 0) - { - return -ENOENT; - } - - /* It's a execute-only file name */ - - buf->st_mode = S_IFREG|S_IXOTH|S_IXGRP|S_IXUSR; - } - else - { - /* It's a read/execute-only directory name */ - - buf->st_mode = S_IFDIR|S_IROTH|S_IRGRP|S_IRUSR|S_IXOTH|S_IXGRP|S_IXUSR; - } - - /* File/directory size, access block size */ - - buf->st_size = 0; - buf->st_blksize = 0; - buf->st_blocks = 0; - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_APPS_BINDIR */ - diff --git a/apps/builtin/builtin.c b/apps/builtin/builtin.c index e0ae9888a..90c0b1353 100644 --- a/apps/builtin/builtin.c +++ b/apps/builtin/builtin.c @@ -40,6 +40,8 @@ ****************************************************************************/ #include + +#include #include /**************************************************************************** diff --git a/apps/builtin/builtin.h b/apps/builtin/builtin.h deleted file mode 100644 index 4593809ee..000000000 --- a/apps/builtin/builtin.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * apps/builtin/builtin.h - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Authors: Uros Platise - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __APPS_BUILTIN_BUILTIN_H -#define __APPS_BUILTIN_BUILTIN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -EXTERN const struct builtin_s g_builtins[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -EXTERN int number_builtins(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __APPS_BUILTIN_BUILTIN_H */ - diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index a3e79a945..6868d7ee7 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -53,10 +53,9 @@ #include #include +#include #include -#include "builtin.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/apps/include/apps.h b/apps/include/apps.h index 9f1918e57..0fb807c14 100644 --- a/apps/include/apps.h +++ b/apps/include/apps.h @@ -62,14 +62,6 @@ * Public Types ****************************************************************************/ -struct builtin_s -{ - const char *name; /* Invocation name and as seen under /sbin/ */ - int priority; /* Use: SCHED_PRIORITY_DEFAULT */ - int stacksize; /* Desired stack size */ - main_t main; /* Entry point: main(int argc, char *argv[]) */ -}; - /**************************************************************************** * Public Data ****************************************************************************/ @@ -82,15 +74,6 @@ extern "C" { #define EXTERN extern #endif -/* The "bindir" is file system that supports access to the builtin applications. - * It is typically mounted under /bin. - */ - -#ifdef CONFIG_APPS_BINDIR -EXTERN mountpt_operations; -EXTERN const struct mountpt_operations binfs_operations; -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/apps/nshlib/nsh_mntcmds.c b/apps/nshlib/nsh_mntcmds.c index f6eb26c31..b16ba8465 100644 --- a/apps/nshlib/nsh_mntcmds.c +++ b/apps/nshlib/nsh_mntcmds.c @@ -131,7 +131,7 @@ static int mount_handler(FAR const char *mountpoint, break; #endif -#ifdef CONFIG_APPS_BINDIR +#ifdef CONFIG_FS_BINFS case BINFS_MAGIC: fstype = "bindir"; break; diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2d2cd8259..ed85f06e1 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3955,4 +3955,5 @@ * arch/mips/src/mips32/up_vfork.c, up_vfork.h, and vfork.S: Implement vfork() for MIPS32 (no floating point support) * configs/ubw32/ostest: Enable the vfork() test. - + * fs/binfs: Move apps/builtin/binfs.c to fs/binfs/fs_binfs.c + CONFIG_APPS_BINDIR rename CONFIG_FS_BINFS diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 8abfd9c23..165e92b96 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -270,8 +270,9 @@ nsh Description ----------- - Configures to use the NuttShell at apps/examples/nsh. This configuration - may be selected as follows: + Configures to use the NuttShell at apps/examples/nsh. This version has + one builtin function: This configuration: apps/examples/hello. This + configuration may be selected as follows: cd /tools ./configure.sh sim/nsh @@ -281,7 +282,7 @@ nsh2 Description ----------- This is another example that configures to use the NuttShell at apps/examples/nsh. - Unlike nsh, this version uses NSH built-in functions. The nx, nxhello, and + Like nsh, this version uses NSH built-in functions: The nx, nxhello, and nxlines examples are included as built-in functions. X11 Configuration diff --git a/nuttx/configs/sim/nsh/appconfig b/nuttx/configs/sim/nsh/appconfig index 264588e51..3f50f6818 100644 --- a/nuttx/configs/sim/nsh/appconfig +++ b/nuttx/configs/sim/nsh/appconfig @@ -42,3 +42,6 @@ CONFIGURED_APPS += examples/nsh CONFIGURED_APPS += system/readline CONFIGURED_APPS += nshlib +# Example built-in application + +CONFIGURED_APPS += examples/hello diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index cec10459a..146519aa6 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -1,7 +1,7 @@ ############################################################################ # sim/nsh/defconfig # -# Copyright (C) 2008-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2008-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ CONFIG_ARCH_BOARD_SIM=y CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_DEBUG=n CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n +CONFIG_DEBUG_SYMBOLS=y CONFIG_HAVE_CXX=n CONFIG_HAVE_CXXINITIALIZE=n @@ -170,6 +170,7 @@ CONFIG_FAT_LFN=n CONFIG_FAT_MAXFNAME=32 CONFIG_FS_NXFFS=n CONFIG_FS_ROMFS=y +CONFIG_FS_BINFS=y # # TCP/IP and UDP support via uIP @@ -193,6 +194,11 @@ CONFIG_NET_STATISTICS=y #CONFIG_NET_ARPTAB_SIZE=8 CONFIG_NET_BROADCAST=n +# +# Settings for examples/hello +# +CONFIG_EXAMPLES_HELLO_BUILTIN=y + # # UIP Network Utilities # @@ -224,7 +230,7 @@ CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 # # Settings for apps/nshlib # -CONFIG_NSH_BUILTIN_APPS=n +CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=80 diff --git a/nuttx/configs/vsn/nsh/defconfig b/nuttx/configs/vsn/nsh/defconfig index 5952f4724..5ec7e06eb 100755 --- a/nuttx/configs/vsn/nsh/defconfig +++ b/nuttx/configs/vsn/nsh/defconfig @@ -526,4 +526,4 @@ CONFIG_HEAP_SIZE= CONFIG_APPS_DIR="../apps" # Provide /dev/ramX and then: mount -t binfs /dev/ram0 /bin -CONFIG_APPS_BINDIR=y +CONFIG_FS_BINFS=y diff --git a/nuttx/fs/Kconfig b/nuttx/fs/Kconfig index 1d1046735..dfbfda3fa 100644 --- a/nuttx/fs/Kconfig +++ b/nuttx/fs/Kconfig @@ -5,11 +5,12 @@ comment "File system configuration" -source fs/fat/Kconfig source fs/mmap/Kconfig +source fs/fat/Kconfig source fs/nfs/Kconfig source fs/nxffs/Kconfig source fs/romfs/Kconfig +source fs/binfs/Kconfig comment "System Logging" diff --git a/nuttx/fs/Makefile b/nuttx/fs/Makefile index 6955c164b..2a1fd75a8 100644 --- a/nuttx/fs/Makefile +++ b/nuttx/fs/Makefile @@ -1,7 +1,7 @@ ############################################################################ # fs/Makefile # -# Copyright (C) 2007, 2008, 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2011-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -72,6 +72,9 @@ CSRCS += fs_registerdriver.c fs_unregisterdriver.c CSRCS += fs_registerblockdriver.c fs_unregisterblockdriver.c \ fs_findblockdriver.c fs_openblockdriver.c fs_closeblockdriver.c +DEPPATH = +VPATH = . + include mmap/Make.defs # Stream support @@ -91,13 +94,17 @@ endif # Additional files required is mount-able file systems are supported ifneq ($(CONFIG_DISABLE_MOUNTPOINT),y) + CSRCS += fs_fsync.c fs_mkdir.c fs_mount.c fs_rename.c fs_rmdir.c \ fs_umount.c fs_unlink.c CSRCS += fs_foreachmountpoint.c + include fat/Make.defs include romfs/Make.defs include nxffs/Make.defs include nfs/Make.defs +include binfs/Make.defs + endif endif @@ -108,8 +115,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libfs$(LIBEXT) -SUBDIRS = mmap fat romfs nxffs:nfs -VPATH = mmap:fat:romfs:nxffs:nfs +SUBDIRS = mmap fat romfs nxffs nfs binfs all: $(BIN) @@ -123,8 +129,7 @@ $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) .depend: Makefile $(SRCS) - $(Q) $(MKDEP) --dep-path . $(MMAPDEPPATH) $(FATDEPPATH) $(ROMFSDEPPATH) $(NXFFSDEPPATH) $(NFSDEPPATH) \ - "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) $(MKDEP) --dep-path . $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep $(Q) touch $@ depend: .depend diff --git a/nuttx/fs/binfs/Kconfig b/nuttx/fs/binfs/Kconfig new file mode 100644 index 000000000..eedbe497d --- /dev/null +++ b/nuttx/fs/binfs/Kconfig @@ -0,0 +1,19 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +config FS_BINFS + bool "BINFS File System" + default n + depends on BUILTIN + ---help--- + The BINFS file system is provides access to builtin applications through + the NuttX file system. The BINFS may, for example, be mount at /bin. + Then all of the built-in applications will appear as executable files in + /bin. Then, for example, you list them from NSH like: + + nsh> ls -l /bin + + If the BINFS BINFMT loader is also enabled, then the builtin applications + can be executed through the normal mechanisms (posix_spawn(), exev(), etc.) diff --git a/nuttx/fs/binfs/Make.defs b/nuttx/fs/binfs/Make.defs new file mode 100644 index 000000000..a65b7367f --- /dev/null +++ b/nuttx/fs/binfs/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# fs/binfs/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name Nuttx nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_FS_BINFS),y) +# Files required for BINFS file system support + +ASRCS += +CSRCS += fs_binfs.c + +# Include BINFS build support + +DEPPATH += --dep-path binfs +VPATH += :binfs +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)binfs} + +endif diff --git a/nuttx/fs/binfs/fs_binfs.c b/nuttx/fs/binfs/fs_binfs.c new file mode 100644 index 000000000..2508719e7 --- /dev/null +++ b/nuttx/fs/binfs/fs_binfs.c @@ -0,0 +1,447 @@ +/**************************************************************************** + * fs/binfs/fs_binfs.c + * + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_FS_BINFS) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int binfs_open(FAR struct file *filep, const char *relpath, + int oflags, mode_t mode); +static int binfs_close(FAR struct file *filep); +static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen); +static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + +static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp); + +static int binfs_opendir(struct inode *mountpt, const char *relpath, + struct fs_dirent_s *dir); +static int binfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); +static int binfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); + +static int binfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle); +static int binfs_unbind(FAR void *handle, FAR struct inode **blkdriver); +static int binfs_statfs(FAR struct inode *mountpt, + FAR struct statfs *buf); + +static int binfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/* See fs_mount.c -- this structure is explicitly externed there. + * We use the old-fashioned kind of initializers so that this will compile + * with any compiler. + */ + +const struct mountpt_operations binfs_operations = +{ + binfs_open, /* open */ + binfs_close, /* close */ + binfs_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + binfs_ioctl, /* ioctl */ + + NULL, /* sync */ + binfs_dup, /* dup */ + + binfs_opendir, /* opendir */ + NULL, /* closedir */ + binfs_readdir, /* readdir */ + binfs_rewinddir, /* rewinddir */ + + binfs_bind, /* bind */ + binfs_unbind, /* unbind */ + binfs_statfs, /* statfs */ + + NULL, /* unlink */ + NULL, /* mkdir */ + NULL, /* rmdir */ + NULL, /* rename */ + binfs_stat /* stat */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: binfs_open + ****************************************************************************/ + +static int binfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode) +{ + int index; + + fvdbg("Open '%s'\n", relpath); + + /* BINFS is read-only. Any attempt to open with any kind of write + * access is not permitted. + */ + + if ((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0) + { + fdbg("ERROR: Only O_RDONLY supported\n"); + return -EACCES; + } + + /* Check if the an entry exists with this name in the root directory. + * so the 'relpath' must be the name of the builtin function. + */ + + index = builtin_isavail(relpath); + if (index < 0) + { + fdbg("ERROR: Builting %s does not exist\n", relpath); + return -ENOENT; + } + + /* Save the index as the open-specific state in filep->f_priv */ + + filep->f_priv = (FAR void *)index; + return OK; +} + +/**************************************************************************** + * Name: binfs_close + ****************************************************************************/ + +static int binfs_close(FAR struct file *filep) +{ + fvdbg("Closing\n"); + return OK; +} + +/**************************************************************************** + * Name: binfs_read + ****************************************************************************/ + +static ssize_t binfs_read(FAR struct file *filep, char *buffer, size_t buflen) +{ + /* Reading is not supported. Just return end-of-file */ + + fvdbg("Read %d bytes from offset %d\n", buflen, filep->f_pos); + return 0; +} + +/**************************************************************************** + * Name: binfs_ioctl + ****************************************************************************/ + +static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + int ret; + + fvdbg("cmd: %d arg: %08lx\n", cmd, arg); + + /* Only one IOCTL command is supported */ + + if (cmd == FIOC_FILENAME) + { + /* IN: FAR char const ** pointer + * OUT: Pointer to a persistent file name (Guaranteed to persist while + * the file is open). + */ + + FAR const char **ptr = (FAR const char **)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + } + else + { + *ptr = g_builtins[(int)filep->f_priv].name; + ret = OK; + } + } + else + { + ret = -ENOTTY; + } + + return ret; +} + +/**************************************************************************** + * Name: binfs_dup + * + * Description: + * Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +static int binfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + fvdbg("Dup %p->%p\n", oldp, newp); + + /* Copy the index from the old to the new file structure */ + + newp->f_priv = oldp->f_priv; + return OK; +} + +/**************************************************************************** + * Name: binfs_opendir + * + * Description: + * Open a directory for read access + * + ****************************************************************************/ + +static int binfs_opendir(struct inode *mountpt, const char *relpath, + struct fs_dirent_s *dir) +{ + fvdbg("relpath: \"%s\"\n", relpath ? relpath : "NULL"); + + /* The requested directory must be the volume-relative "root" directory */ + + if (relpath && relpath[0] != '\0') + { + return -ENOENT; + } + + /* Set the index to the first entry */ + + dir->u.binfs.fb_index = 0; + return OK; +} + +/**************************************************************************** + * Name: binfs_readdir + * + * Description: Read the next directory entry + * + ****************************************************************************/ + +static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) +{ + unsigned int index; + int ret; + + /* Have we reached the end of the directory */ + + index = dir->u.binfs.fb_index; + if (g_builtins[index].name == NULL) + { + /* We signal the end of the directory by returning the + * special error -ENOENT + */ + + fvdbg("Entry %d: End of directory\n", index); + ret = -ENOENT; + } + else + { + /* Save the filename and file type */ + + fvdbg("Entry %d: \"%s\"\n", index, g_builtins[index].name); + dir->fd_dir.d_type = DTYPE_FILE; + strncpy(dir->fd_dir.d_name, g_builtins[index].name, NAME_MAX+1); + + /* The application list is terminated by an entry with a NULL name. + * Therefore, there is at least one more entry in the list. + */ + + index++; + + /* Set up the next directory entry offset. NOTE that we could use the + * standard f_pos instead of our own private fb_index. + */ + + dir->u.binfs.fb_index = index; + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: binfs_rewindir + * + * Description: Reset directory read to the first entry + * + ****************************************************************************/ + +static int binfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) +{ + fvdbg("Entry\n"); + + dir->u.binfs.fb_index = 0; + return OK; +} + +/**************************************************************************** + * Name: binfs_bind + * + * Description: This implements a portion of the mount operation. This + * function allocates and initializes the mountpoint private data and + * binds the blockdriver inode to the filesystem private data. The final + * binding of the private data (containing the blockdriver) to the + * mountpoint is performed by mount(). + * + ****************************************************************************/ + +static int binfs_bind(FAR struct inode *blkdriver, const void *data, + void **handle) +{ + fvdbg("Entry\n"); + return OK; +} + +/**************************************************************************** + * Name: binfs_unbind + * + * Description: This implements the filesystem portion of the umount + * operation. + * + ****************************************************************************/ + +static int binfs_unbind(void *handle, FAR struct inode **blkdriver) +{ + fvdbg("Entry\n"); + return OK; +} + +/**************************************************************************** + * Name: binfs_statfs + * + * Description: Return filesystem statistics + * + ****************************************************************************/ + +static int binfs_statfs(struct inode *mountpt, struct statfs *buf) +{ + fvdbg("Entry\n"); + + /* Fill in the statfs info */ + + memset(buf, 0, sizeof(struct statfs)); + buf->f_type = BINFS_MAGIC; + buf->f_bsize = 0; + buf->f_blocks = 0; + buf->f_bfree = 0; + buf->f_bavail = 0; + buf->f_namelen = NAME_MAX; + return OK; +} + +/**************************************************************************** + * Name: binfs_stat + * + * Description: Return information about a file or directory + * + ****************************************************************************/ + +static int binfs_stat(struct inode *mountpt, const char *relpath, struct stat *buf) +{ + fvdbg("Entry\n"); + + /* The requested directory must be the volume-relative "root" directory */ + + if (relpath && relpath[0] != '\0') + { + /* Check if there is a file with this name. */ + + if (builtin_isavail(relpath) < 0) + { + return -ENOENT; + } + + /* It's a execute-only file name */ + + buf->st_mode = S_IFREG|S_IXOTH|S_IXGRP|S_IXUSR; + } + else + { + /* It's a read/execute-only directory name */ + + buf->st_mode = S_IFDIR|S_IROTH|S_IRGRP|S_IRUSR|S_IXOTH|S_IXGRP|S_IXUSR; + } + + /* File/directory size, access block size */ + + buf->st_size = 0; + buf->st_blksize = 0; + buf->st_blocks = 0; + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_BINFS */ + diff --git a/nuttx/fs/fat/Make.defs b/nuttx/fs/fat/Make.defs index 136302b86..2769ab602 100644 --- a/nuttx/fs/fat/Make.defs +++ b/nuttx/fs/fat/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # Make.defs # -# Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2008, 2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -44,7 +44,10 @@ CSRCS += fs_fat32.c fs_fat32dirent.c fs_fat32attrib.c fs_fat32util.c ASRCS += CSRCS += fs_mkfatfs.c fs_configfat.c fs_writefat.c -# Argument for dependency checking +# Include FAT build support + +DEPPATH += --dep-path fat +VPATH += :fat +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)fat} -FATDEPPATH = --dep-path fat endif diff --git a/nuttx/fs/fs_mount.c b/nuttx/fs/fs_mount.c index 228c1fc6e..1b3da8dc3 100644 --- a/nuttx/fs/fs_mount.c +++ b/nuttx/fs/fs_mount.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/fs_mount.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,10 +47,6 @@ #include -#ifdef CONFIG_APPS_BINDIR -# include -#endif - #include "fs_internal.h" /* At least one filesystem must be defined, or this file will not compile. @@ -78,7 +74,7 @@ /* These file systems do not require block drivers */ -#if defined(CONFIG_FS_NXFFS) || defined(CONFIG_APPS_BINDIR) || defined(CONFIG_NFS) +#if defined(CONFIG_FS_NXFFS) || defined(CONFIG_FS_BINFS) || defined(CONFIG_NFS) # define NONBDFS_SUPPORT #endif @@ -123,6 +119,9 @@ extern const struct mountpt_operations nxffs_operations; #ifdef CONFIG_NFS extern const struct mountpt_operations nfs_operations; #endif +#ifdef CONFIG_FS_BINFS +extern const struct mountpt_operations binfs_operations; +#endif static const struct fsmap_t g_nonbdfsmap[] = { @@ -132,7 +131,7 @@ static const struct fsmap_t g_nonbdfsmap[] = #ifdef CONFIG_NFS { "nfs", &nfs_operations }, #endif -#ifdef CONFIG_APPS_BINDIR +#ifdef CONFIG_FS_BINFS { "binfs", &binfs_operations }, #endif { NULL, NULL }, diff --git a/nuttx/fs/mmap/Make.defs b/nuttx/fs/mmap/Make.defs index 59857fe9c..b85d9f60f 100644 --- a/nuttx/fs/mmap/Make.defs +++ b/nuttx/fs/mmap/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # fs/mmap/Make.defs # -# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -40,4 +40,9 @@ ifeq ($(CONFIG_FS_RAMMAP),y) CSRCS += fs_munmap.c fs_rammap.c endif -MMAPDEPPATH = --dep-path mmap +# Include MMAP build support + +DEPPATH += --dep-path mmap +VPATH += :mmap +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)mmap} + diff --git a/nuttx/fs/nfs/Make.defs b/nuttx/fs/nfs/Make.defs index fc4682f85..ec2177fcf 100644 --- a/nuttx/fs/nfs/Make.defs +++ b/nuttx/fs/nfs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # Make.defs # -# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -44,7 +44,10 @@ CSRCS += ASRCS += CSRCS += rpc_clnt.c nfs_util.c nfs_vfsops.c -# Argument for dependency checking +# Include NFS build support + +DEPPATH += --dep-path nfs +VPATH += :nfs +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)nfs} -NFSDEPPATH = --dep-path nfs endif diff --git a/nuttx/fs/nxffs/Make.defs b/nuttx/fs/nxffs/Make.defs index b67ae4472..ccf1ba661 100644 --- a/nuttx/fs/nxffs/Make.defs +++ b/nuttx/fs/nxffs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # fs/nxffs/Make.defs # -# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -40,7 +40,10 @@ CSRCS += nxffs_block.c nxffs_blockstats.c nxffs_cache.c nxffs_dirent.c \ nxffs_open.c nxffs_pack.c nxffs_read.c nxffs_reformat.c \ nxffs_stat.c nxffs_unlink.c nxffs_util.c nxffs_write.c -# Argument for dependency checking +# Include NXFFS build support + +DEPPATH += --dep-path nxffs +VPATH += :nxffs +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)nxffs} -NXFFSDEPPATH = --dep-path nxffs endif diff --git a/nuttx/fs/romfs/Make.defs b/nuttx/fs/romfs/Make.defs index 77de93c05..e87cbdf9e 100644 --- a/nuttx/fs/romfs/Make.defs +++ b/nuttx/fs/romfs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # fs/romfs/Make.defs # -# Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 2008, 2011, 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,7 +39,10 @@ ifeq ($(CONFIG_FS_ROMFS),y) ASRCS += CSRCS += fs_romfs.c fs_romfsutil.c -# Argument for dependency checking +# Include ROMFS build support + +DEPPATH += --dep-path romfs +VPATH += :romfs +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)fs$(DELIM)romfs} -ROMFSDEPPATH = --dep-path romfs endif diff --git a/nuttx/include/nuttx/binfmt/builtin.h b/nuttx/include/nuttx/binfmt/builtin.h new file mode 100644 index 000000000..c27605cac --- /dev/null +++ b/nuttx/include/nuttx/binfmt/builtin.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * include/nuttx/binfmt/builtin.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_BINFMT_BUILTIN_H +#define __INCLUDE_NUTTX_BINFMT_BUILTIN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct builtin_s +{ + const char *name; /* Invocation name and as seen under /sbin/ */ + int priority; /* Use: SCHED_PRIORITY_DEFAULT */ + int stacksize; /* Desired stack size */ + main_t main; /* Entry point: main(int argc, char *argv[]) */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +EXTERN const struct builtin_s g_builtins[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +EXTERN int number_builtins(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __INCLUDE_NUTTX_BINFMT_BUILTIN_H */ + diff --git a/nuttx/include/nuttx/fs/binfs.h b/nuttx/include/nuttx/fs/binfs.h index 6125384a9..df92375e3 100644 --- a/nuttx/include/nuttx/fs/binfs.h +++ b/nuttx/include/nuttx/fs/binfs.h @@ -44,6 +44,8 @@ #include +#ifdef CONFIG_FS_BINFS + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -62,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Function Prototypes + * Public Data ****************************************************************************/ #ifdef __cplusplus @@ -72,9 +74,21 @@ extern "C" { #define EXTERN extern #endif +/* The "bindir" is file system that supports access to the builtin applications. + * It is typically mounted under /bin. + */ + +EXTERN mountpt_operations; +EXTERN const struct mountpt_operations binfs_operations; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + #undef EXTERN #ifdef __cplusplus } #endif +#endif /* CONFIG_FS_BINFS */ #endif /* __INCLUDE_NUTTX_FS_BINFS_H */ diff --git a/nuttx/include/nuttx/fs/dirent.h b/nuttx/include/nuttx/fs/dirent.h index 75867c87a..f8d356850 100644 --- a/nuttx/include/nuttx/fs/dirent.h +++ b/nuttx/include/nuttx/fs/dirent.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/fs/dirent.h * - * Copyright (C) 2007, 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -102,7 +102,7 @@ struct fs_romfsdir_s }; #endif /* CONFIG_FS_ROMFS */ -#ifdef CONFIG_APPS_BINDIR +#ifdef CONFIG_FS_BINFS /* The apps/ pseudo bin/ directory. The state value is simply an index */ struct fs_binfsdir_s @@ -179,7 +179,7 @@ struct fs_dirent_s #ifdef CONFIG_FS_ROMFS struct fs_romfsdir_s romfs; #endif -#ifdef CONFIG_APPS_BINDIR +#ifdef CONFIG_FS_BINFS struct fs_binfsdir_s binfs; #endif #ifdef CONFIG_FS_NXFFS diff --git a/nuttx/tools/mkconfig.c b/nuttx/tools/mkconfig.c index f4a1168c5..fe3e00491 100644 --- a/nuttx/tools/mkconfig.c +++ b/nuttx/tools/mkconfig.c @@ -1,7 +1,7 @@ /**************************************************************************** * tools/mkconfig.c * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -213,14 +213,14 @@ int main(int argc, char **argv, char **envp) printf("# undef CONFIG_FS_FAT\n"); printf("# undef CONFIG_FS_ROMFS\n"); printf("# undef CONFIG_FS_NXFFS\n"); - printf("# undef CONFIG_APPS_BINDIR\n"); + printf("# undef CONFIG_FS_BINFS\n"); printf("# undef CONFIG_NFS\n"); printf("#endif\n\n"); printf("/* Check if any readable and writable filesystem (OR USB storage) is supported */\n\n"); printf("#undef CONFIG_FS_READABLE\n"); printf("#undef CONFIG_FS_WRITABLE\n"); printf("#if defined(CONFIG_FS_FAT) || defined(CONFIG_FS_ROMFS) || defined(CONFIG_USBMSC) || \\\n"); - printf(" defined(CONFIG_FS_NXFFS) || defined(CONFIG_APPS_BINDIR) || defined(CONFIG_NFS)\n"); + printf(" defined(CONFIG_FS_NXFFS) || defined(CONFIG_FS_BINFS) || defined(CONFIG_NFS)\n"); printf("# define CONFIG_FS_READABLE 1\n"); printf("#endif\n\n"); printf("#if defined(CONFIG_FS_FAT) || defined(CONFIG_USBMSC) || defined(CONFIG_FS_NXFFS) || \\\n"); -- cgit v1.2.3 From 38efdf0ce37cc3413acee30d966f242aa8a77acd Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 16 Jan 2013 17:05:00 +0000 Subject: Rename apps/include/apps.h to builtin.h. Move parts of apps/builtins/exec_builtin.c to binfmt/libbuiltin/libbuiltin_utils.c git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5524 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 6 ++ apps/README.txt | 3 +- apps/builtin/Kconfig | 10 +- apps/builtin/builtin.c | 1 - apps/builtin/exec_builtin.c | 46 +-------- apps/include/apps.h | 148 ----------------------------- apps/include/builtin.h | 111 ++++++++++++++++++++++ apps/nshlib/Kconfig | 2 +- apps/nshlib/nsh_builtin.c | 3 +- apps/nshlib/nsh_parse.c | 2 +- nuttx/ChangeLog | 5 + nuttx/Documentation/NuttShell.html | 2 +- nuttx/binfmt/Kconfig | 14 +++ nuttx/binfmt/Makefile | 3 +- nuttx/binfmt/libbuiltin/Kconfig | 4 + nuttx/binfmt/libbuiltin/Make.defs | 49 ++++++++++ nuttx/binfmt/libbuiltin/libbuiltin_utils.c | 121 +++++++++++++++++++++++ nuttx/fs/binfs/fs_binfs.c | 3 +- nuttx/include/nuttx/binfmt/builtin.h | 81 +++++++++++++++- nuttx/include/nuttx/fs/binfs.h | 11 --- nuttx/include/nuttx/fs/ioctl.h | 6 +- 21 files changed, 402 insertions(+), 229 deletions(-) delete mode 100644 apps/include/apps.h create mode 100644 apps/include/builtin.h create mode 100644 nuttx/binfmt/libbuiltin/Kconfig create mode 100644 nuttx/binfmt/libbuiltin/Make.defs create mode 100644 nuttx/binfmt/libbuiltin/libbuiltin_utils.c diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 5bc3b2149..6faac9e4b 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -475,3 +475,9 @@ binfmt. * builtin/binfs.c: Move apps/builtin/binfs.c to fs/binfs/fs_binfs.c CONFIG_APPS_BINDIR rename CONFIG_FS_BINFS + * apps/include/builtin.h: Some of the content of + apps/include/apps.h moved to include/nuttx/binfmt/builtin.h. + apps/include/apps.h renamed builtin.h + * pps/builtin/exec_builtins.c: Move utility builtin + utility functions from apps/builtin/exec_builtins.c to + binfmt/libbuiltin/libbuiltin_utils.c \ No newline at end of file diff --git a/apps/README.txt b/apps/README.txt index 4a336abdb..55accfcf6 100644 --- a/apps/README.txt +++ b/apps/README.txt @@ -7,7 +7,6 @@ Contents General Directory Location Built-In Applications - Built-In Startup main() function NuttShell (NSH) Built-In Commands Synchronous Built-In Commands Application Configuration File @@ -62,7 +61,7 @@ collected during the make context build phase. To execute an application function: - exec_builtin() is defined in the nuttx/include/apps/apps.h + exec_builtin() is defined in the nuttx/include/apps/builtin.h NuttShell (NSH) Built-In Commands --------------------------------- diff --git a/apps/builtin/Kconfig b/apps/builtin/Kconfig index 37150e8a9..c3371d708 100644 --- a/apps/builtin/Kconfig +++ b/apps/builtin/Kconfig @@ -3,21 +3,13 @@ # see misc/tools/kconfig-language.txt. # -config BUILTIN - bool "Support Builtin Applications" - default n - ---help--- - Enable support for builtin applications. This features assigns a string - name to an application. This feature is also the underlying requirement - to support built-in applications in the NuttShell (NSH). - if BUILTIN config BUILTIN_PROXY_STACKSIZE int "Builtin Proxy Stack Size" default 1024 ---help--- - If exec_builting uses I/O redirection options, then it will require + If exec_builtin uses I/O redirection options, then it will require an intermediary/proxy task to muck with the file descriptors. This configuration item specifies the stack size used for the proxy. Default: 1024 bytes. diff --git a/apps/builtin/builtin.c b/apps/builtin/builtin.c index 90c0b1353..7655a531d 100644 --- a/apps/builtin/builtin.c +++ b/apps/builtin/builtin.c @@ -42,7 +42,6 @@ #include #include -#include /**************************************************************************** * Private Types diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index 6868d7ee7..05648590d 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -54,7 +54,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -365,50 +365,6 @@ errout: * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: builtin_getname - * - * Description: - * Return the name of the application at index in the table of builtin - * applications. - * - ****************************************************************************/ - -const char *builtin_getname(int index) -{ - if (index < 0 || index >= number_builtins()) - { - return NULL; - } - - return g_builtins[index].name; -} - -/**************************************************************************** - * Name: builtin_isavail - * - * Description: - * Return the index into the table of applications for the applicaiton with - * the name 'appname'. - * - ****************************************************************************/ - -int builtin_isavail(FAR const char *appname) -{ - int i; - - for (i = 0; g_builtins[i].name; i++) - { - if (!strcmp(g_builtins[i].name, appname)) - { - return i; - } - } - - set_errno(ENOENT); - return ERROR; -} - /**************************************************************************** * Name: exec_builtin * diff --git a/apps/include/apps.h b/apps/include/apps.h deleted file mode 100644 index 0fb807c14..000000000 --- a/apps/include/apps.h +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * apps/include/apps.h - * - * Originally by: - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * With subsequent updates, modifications, and general maintenance by: - * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __APPS_INCLUDE_APPS_H -#define __APPS_INCLUDE_APPS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: builtin_isavail - * - * Description: - * Checks for availabiliy of application registerred during compile time. - * - * Input Parameter: - * filename - Name of the linked-in binary to be started. - * - * Returned Value: - * This is an end-user function, so it follows the normal convention: - * Returns index of builtin application. If it is not found then it - * returns -1 (ERROR) and sets errno appropriately. - * - ****************************************************************************/ - -EXTERN int builtin_isavail(FAR const char *appname); - -/**************************************************************************** - * Name: builtin_getname - * - * Description: - * Returns pointer to a name of built-in application pointed by the - * index. - * - * Input Parameter: - * index, from 0 and on ... - * - * Returned Value: - * Returns valid pointer pointing to the app name if index is valid. - * Otherwise NULL is returned. - * - ****************************************************************************/ - -EXTERN const char *builtin_getname(int index); - -/**************************************************************************** - * Name: exec_builtin - * - * Description: - * Executes builtin applications registered during 'make context' time. - * New application is run in a separate task context (and thread). - * - * Input Parameter: - * filename - Name of the linked-in binary to be started. - * argv - Argument list - * redirfile - If output if redirected, this parameter will be non-NULL - * and will provide the full path to the file. - * oflags - If output is redirected, this parameter will provide the - * open flags to use. This will support file replacement - * of appending to an existing file. - * - * Returned Value: - * This is an end-user function, so it follows the normal convention: - * Returns the PID of the exec'ed module. On failure, it.returns - * -1 (ERROR) and sets errno appropriately. - * - ****************************************************************************/ - -EXTERN int exec_builtin(FAR const char *appname, FAR const char **argv, - FAR const char *redirfile, int oflags); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __APPS_INCLUDE_APPS_H */ diff --git a/apps/include/builtin.h b/apps/include/builtin.h new file mode 100644 index 000000000..24cf204fa --- /dev/null +++ b/apps/include/builtin.h @@ -0,0 +1,111 @@ +/**************************************************************************** + * apps/include/builtin.h + * + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __APPS_INCLUDE_BUILTIN_H +#define __APPS_INCLUDE_BUILTIN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: exec_builtin + * + * Description: + * Executes builtin applications registered during 'make context' time. + * New application is run in a separate task context (and thread). + * + * Input Parameter: + * filename - Name of the linked-in binary to be started. + * argv - Argument list + * redirfile - If output if redirected, this parameter will be non-NULL + * and will provide the full path to the file. + * oflags - If output is redirected, this parameter will provide the + * open flags to use. This will support file replacement + * of appending to an existing file. + * + * Returned Value: + * This is an end-user function, so it follows the normal convention: + * Returns the PID of the exec'ed module. On failure, it.returns + * -1 (ERROR) and sets errno appropriately. + * + ****************************************************************************/ + +EXTERN int exec_builtin(FAR const char *appname, FAR const char **argv, + FAR const char *redirfile, int oflags); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __APPS_INCLUDE_BUILTIN_H */ diff --git a/apps/nshlib/Kconfig b/apps/nshlib/Kconfig index e60e9c480..9cfc020a5 100644 --- a/apps/nshlib/Kconfig +++ b/apps/nshlib/Kconfig @@ -15,7 +15,7 @@ if NSH_LIBRARY config NSH_BUILTIN_APPS bool "Enable built-in applications" default y - depends on BUILTIN + select BUILTIN ---help--- Support external registered, "built-in" applications that can be executed from the NSH command line (see apps/README.txt for diff --git a/apps/nshlib/nsh_builtin.c b/apps/nshlib/nsh_builtin.c index 16e3e9427..ba39e8dfe 100644 --- a/apps/nshlib/nsh_builtin.c +++ b/apps/nshlib/nsh_builtin.c @@ -54,7 +54,8 @@ #include #include -#include +#include +#include #include "nsh.h" #include "nsh_console.h" diff --git a/apps/nshlib/nsh_parse.c b/apps/nshlib/nsh_parse.c index 15723b497..c36724372 100644 --- a/apps/nshlib/nsh_parse.c +++ b/apps/nshlib/nsh_parse.c @@ -59,7 +59,7 @@ #endif #ifdef CONFIG_NSH_BUILTIN_APPS -# include +# include #endif #include diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index ed85f06e1..57925a8b3 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3957,3 +3957,8 @@ * configs/ubw32/ostest: Enable the vfork() test. * fs/binfs: Move apps/builtin/binfs.c to fs/binfs/fs_binfs.c CONFIG_APPS_BINDIR rename CONFIG_FS_BINFS + * include/nuttx/binfmt/builtin.h: Some of the content of + apps/include/apps.h moved to include/nuttx/binfmt/builtin.h + * binfmt/libbuiltin/libbuiltin_utils.c: Move utility builtin + utility functions from apps/builtin/exec_builtins.c to + binfmt/libbuiltin/libbuiltin_utils.c \ No newline at end of file diff --git a/nuttx/Documentation/NuttShell.html b/nuttx/Documentation/NuttShell.html index 95a75b22c..273898476 100644 --- a/nuttx/Documentation/NuttShell.html +++ b/nuttx/Documentation/NuttShell.html @@ -3261,7 +3261,7 @@ Builtin Apps:

          Built-In Application Utility Functions. - The utility functions exported by the builtin application logic are prototyped in apps/include/apps.h. + The utility functions exported by the builtin application logic are prototyped in nuttx/include/nuttx/binfmt/builtin.h and apps/include/builtin.h. These utility functions include:

          diff --git a/nuttx/binfmt/Kconfig b/nuttx/binfmt/Kconfig index 495bd050f..8d6c0bb18 100644 --- a/nuttx/binfmt/Kconfig +++ b/nuttx/binfmt/Kconfig @@ -49,6 +49,20 @@ if ELF source binfmt/libelf/Kconfig endif +config BUILTIN + bool "Support Builtin Applications" + default n + ---help--- + Enable support for builtin applications. This features assigns a string + name to an application and in addition if FS_BINFS is defined, retaining + those names in a file system from which they can be executed. This feature + is also the underlying requirement to support built-in applications in the + NuttShell (NSH). + +if BUILTIN +source binfmt/libbuiltin/Kconfig +endif + endif config PIC diff --git a/nuttx/binfmt/Makefile b/nuttx/binfmt/Makefile index 8ec0d877c..49dcd3d32 100644 --- a/nuttx/binfmt/Makefile +++ b/nuttx/binfmt/Makefile @@ -1,7 +1,7 @@ ############################################################################ # nxflat/Makefile # -# Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -65,6 +65,7 @@ DEPPATH = --dep-path . include libnxflat$(DELIM)Make.defs include libelf$(DELIM)Make.defs +include libbuiltin$(DELIM)Make.defs BINFMT_AOBJS = $(BINFMT_ASRCS:.S=$(OBJEXT)) BINFMT_COBJS = $(BINFMT_CSRCS:.c=$(OBJEXT)) diff --git a/nuttx/binfmt/libbuiltin/Kconfig b/nuttx/binfmt/libbuiltin/Kconfig new file mode 100644 index 000000000..ae2bf3130 --- /dev/null +++ b/nuttx/binfmt/libbuiltin/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# diff --git a/nuttx/binfmt/libbuiltin/Make.defs b/nuttx/binfmt/libbuiltin/Make.defs new file mode 100644 index 000000000..1d129294c --- /dev/null +++ b/nuttx/binfmt/libbuiltin/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# binfmt/libbuiltin/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Legacy configurations don't set CONFIG_BUILTIN +# ifeq ($(CONFIG_BUILTIN),y) + +# Builtin application interfaces + +BINFMT_CSRCS += libbuiltin_utils.c + +# Hook the libelf subdirectory into the build + +VPATH += libbuiltin +SUBDIRS += libbuiltin +DEPPATH += --dep-path libbuiltin + +# endif diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_utils.c b/nuttx/binfmt/libbuiltin/libbuiltin_utils.c new file mode 100644 index 000000000..b53becff9 --- /dev/null +++ b/nuttx/binfmt/libbuiltin/libbuiltin_utils.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * binfmt/libbuiltin/libbuiltin_utils.c + * + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_getname + * + * Description: + * Return the name of the application at index in the table of builtin + * applications. + * + ****************************************************************************/ + +FAR const char *builtin_getname(int index) +{ + if (index < 0 || index >= number_builtins()) + { + return NULL; + } + + return g_builtins[index].name; +} + +/**************************************************************************** + * Name: builtin_isavail + * + * Description: + * Return the index into the table of applications for the applicaiton with + * the name 'appname'. + * + ****************************************************************************/ + +int builtin_isavail(FAR const char *appname) +{ + int i; + + for (i = 0; g_builtins[i].name; i++) + { + if (!strncmp(g_builtins[i].name, appname, NAME_MAX)) + { + return i; + } + } + + set_errno(ENOENT); + return ERROR; +} diff --git a/nuttx/fs/binfs/fs_binfs.c b/nuttx/fs/binfs/fs_binfs.c index 2508719e7..ed6326eba 100644 --- a/nuttx/fs/binfs/fs_binfs.c +++ b/nuttx/fs/binfs/fs_binfs.c @@ -54,10 +54,9 @@ #include #include #include +#include #include -#include - #if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_FS_BINFS) /**************************************************************************** diff --git a/nuttx/include/nuttx/binfmt/builtin.h b/nuttx/include/nuttx/binfmt/builtin.h index c27605cac..632f8944d 100644 --- a/nuttx/include/nuttx/binfmt/builtin.h +++ b/nuttx/include/nuttx/binfmt/builtin.h @@ -1,10 +1,15 @@ /**************************************************************************** * include/nuttx/binfmt/builtin.h * + * Originally by: + * * Copyright (C) 2011 Uros Platise. All rights reserved. - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Authors: Uros Platise - * Gregory Nutt + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,7 +48,7 @@ ****************************************************************************/ #include -#include +#include /**************************************************************************** * Public Types @@ -68,13 +73,79 @@ extern "C" { #define EXTERN extern #endif +/* The g_builtins[] array holds information about each builtin function. If + * support for builtin functions is enabled in the NuttX configuration, then + * this arrary (along with the number_builtins() function) must be provided + * by the application code. + */ + EXTERN const struct builtin_s g_builtins[]; /**************************************************************************** * Public Functions ****************************************************************************/ -EXTERN int number_builtins(void); +/**************************************************************************** + * Utility Functions Provided to Applications by binfmt/libbuiltin + ****************************************************************************/ +/**************************************************************************** + * Name: builtin_isavail + * + * Description: + * Checks for availabiliy of application registerred during compile time. + * + * Input Parameter: + * filename - Name of the linked-in binary to be started. + * + * Returned Value: + * This is an end-user function, so it follows the normal convention: + * Returns index of builtin application. If it is not found then it + * returns -1 (ERROR) and sets errno appropriately. + * + ****************************************************************************/ + +int builtin_isavail(FAR const char *appname); + +/**************************************************************************** + * Name: builtin_getname + * + * Description: + * Returns pointer to a name of built-in application pointed by the + * index. + * + * Input Parameter: + * index, from 0 and on ... + * + * Returned Value: + * Returns valid pointer pointing to the app name if index is valid. + * Otherwise NULL is returned. + * + ****************************************************************************/ + +FAR const char *builtin_getname(int index); + +/**************************************************************************** + * Data Set Access Functions Provided to Applications by binfmt/libbuiltin + ****************************************************************************/ +/**************************************************************************** + * Name: number_builtins + * + * Description: + * Returns the number of builtin functions in the g_builtins[] array. If + * support for builtin functions is enabled in the NuttX configuration, + * then this function (along with g_builtins[]) must be provided by the + * application code. + * + * Input Parameter: + * None + * + * Returned Value: + * The number of entries in the g_builtins[] array. This function does + * not return failures. + * + ****************************************************************************/ + +int number_builtins(void); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/include/nuttx/fs/binfs.h b/nuttx/include/nuttx/fs/binfs.h index df92375e3..d967506d8 100644 --- a/nuttx/include/nuttx/fs/binfs.h +++ b/nuttx/include/nuttx/fs/binfs.h @@ -42,22 +42,11 @@ #include -#include - #ifdef CONFIG_FS_BINFS /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* This is the BINFS ioctl that can be used to recover the filename - * associated with the builtin task. - */ - -#define FIOC_FILENAME FIOC_USER /* IN: FAR const char ** pointer - * OUT: Pointer to a persistent file name - * (Guaranteed to persist while the file - * is open). - */ /**************************************************************************** * Type Definitions diff --git a/nuttx/include/nuttx/fs/ioctl.h b/nuttx/include/nuttx/fs/ioctl.h index 8f2fdd7d9..9cde497a8 100644 --- a/nuttx/include/nuttx/fs/ioctl.h +++ b/nuttx/include/nuttx/fs/ioctl.h @@ -105,7 +105,11 @@ #define FIOC_OPTIMIZE _FIOC(0x0003) /* IN: None * OUT: None */ -#define FIOC_USER _FIOC(0x0004) /* File system-specific */ +#define FIOC_FILENAME _FIOC(0x0004) /* IN: FAR const char ** pointer + * OUT: Pointer to a persistent file name + * (Guaranteed to persist while the file + * is open). + */ /* NuttX file system ioctl definitions **************************************/ -- cgit v1.2.3 From a568e1e63afed4a9a1fb075568eec16ab76c158d Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 16 Jan 2013 19:08:23 +0000 Subject: Add a binary 'loader' so that builtin applications can be executed from the BINFS file system git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5525 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 8 +- apps/nshlib/Kconfig | 2 +- apps/nshlib/nsh_mntcmds.c | 72 ++++++--- apps/nshlib/nsh_parse.c | 2 +- nuttx/ChangeLog | 5 +- nuttx/binfmt/builtin.c | 195 +++++++++++++++++++++++ nuttx/binfmt/elf.c | 2 +- nuttx/binfmt/libbuiltin/Make.defs | 9 +- nuttx/configs/cloudctrl/nsh/defconfig | 2 +- nuttx/configs/compal_e88/nsh_highram/defconfig | 2 + nuttx/configs/compal_e99/nsh_compalram/defconfig | 2 + nuttx/configs/compal_e99/nsh_highram/defconfig | 2 + nuttx/configs/fire-stm32v2/nsh/defconfig | 10 +- nuttx/configs/hymini-stm32v/nsh2/defconfig | 1 + nuttx/configs/mirtoo/ostest/defconfig | 2 +- nuttx/configs/olimex-lpc1766stk/ftpc/defconfig | 3 +- nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 1 + nuttx/configs/olimex-stm32-p107/nsh/defconfig | 1 + nuttx/configs/pcblogic-pic32mx/nsh/defconfig | 1 + nuttx/configs/pic32-starterkit/nsh/defconfig | 1 + nuttx/configs/pic32-starterkit/nsh2/defconfig | 1 + nuttx/configs/pic32mx7mmb/nsh/defconfig | 1 + nuttx/configs/sam3u-ek/touchscreen/defconfig | 1 + nuttx/configs/shenzhou/nsh/defconfig | 2 +- nuttx/configs/shenzhou/nxwm/defconfig | 2 +- nuttx/configs/shenzhou/thttpd/defconfig | 2 +- nuttx/configs/sim/nsh/defconfig | 1 + nuttx/configs/sim/nsh2/defconfig | 1 + nuttx/configs/stm3210e-eval/nsh2/defconfig | 1 + nuttx/configs/stm3210e-eval/nxconsole/defconfig | 1 + nuttx/configs/stm3210e-eval/pm/defconfig | 1 + nuttx/configs/stm3220g-eval/nsh/defconfig | 1 + nuttx/configs/stm3220g-eval/nsh2/defconfig | 1 + nuttx/configs/stm3220g-eval/ostest/defconfig | 2 +- nuttx/configs/stm3240g-eval/nsh/defconfig | 1 + nuttx/configs/stm3240g-eval/nsh2/defconfig | 1 + nuttx/configs/stm3240g-eval/nxconsole/defconfig | 1 + nuttx/configs/stm3240g-eval/ostest/defconfig | 2 +- nuttx/configs/stm3240g-eval/webserver/defconfig | 2 +- nuttx/configs/stm32f100rc_generic/nsh/defconfig | 2 +- nuttx/configs/stm32f4discovery/nsh/defconfig | 1 + nuttx/configs/stm32f4discovery/pm/defconfig | 1 + nuttx/configs/sure-pic32mx/nsh/defconfig | 1 + nuttx/configs/sure-pic32mx/usbnsh/defconfig | 1 + nuttx/configs/ubw32/nsh/defconfig | 1 + nuttx/configs/vsn/nsh/defconfig | 1 + nuttx/fs/fs_mount.c | 2 +- 47 files changed, 316 insertions(+), 42 deletions(-) create mode 100644 nuttx/binfmt/builtin.c diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 6faac9e4b..14eb78950 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -478,6 +478,10 @@ * apps/include/builtin.h: Some of the content of apps/include/apps.h moved to include/nuttx/binfmt/builtin.h. apps/include/apps.h renamed builtin.h - * pps/builtin/exec_builtins.c: Move utility builtin + * apps/builtin/exec_builtins.c: Move utility builtin utility functions from apps/builtin/exec_builtins.c to - binfmt/libbuiltin/libbuiltin_utils.c \ No newline at end of file + binfmt/libbuiltin/libbuiltin_utils.c + * apps/nshlib/nsh_mountcmds.c: The block driver/source + argument is now optional. Many files systems do not need + a source and it is really stupid to have to enter a bogus + source parameter. diff --git a/apps/nshlib/Kconfig b/apps/nshlib/Kconfig index 9cfc020a5..e60e9c480 100644 --- a/apps/nshlib/Kconfig +++ b/apps/nshlib/Kconfig @@ -15,7 +15,7 @@ if NSH_LIBRARY config NSH_BUILTIN_APPS bool "Enable built-in applications" default y - select BUILTIN + depends on BUILTIN ---help--- Support external registered, "built-in" applications that can be executed from the NSH command line (see apps/README.txt for diff --git a/apps/nshlib/nsh_mntcmds.c b/apps/nshlib/nsh_mntcmds.c index b16ba8465..f8e3a142a 100644 --- a/apps/nshlib/nsh_mntcmds.c +++ b/apps/nshlib/nsh_mntcmds.c @@ -133,7 +133,7 @@ static int mount_handler(FAR const char *mountpoint, #ifdef CONFIG_FS_BINFS case BINFS_MAGIC: - fstype = "bindir"; + fstype = "binfs"; break; #endif @@ -198,9 +198,11 @@ int cmd_df(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) defined(CONFIG_FS_READABLE) && !defined(CONFIG_NSH_DISABLE_MOUNT) int cmd_mount(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) { - FAR char *source; - FAR char *target; - FAR char *filesystem = NULL; + FAR const char *source; + FAR char *fullsource; + FAR const char *target; + FAR char *fulltarget; + FAR const char *filesystem = NULL; bool badarg = false; int option; int ret; @@ -248,19 +250,32 @@ int cmd_mount(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) return ERROR; } - /* There are two required arguments after the options: the source and target - * paths. + /* There may be one or two required arguments after the options: the source + * and target paths. Some file systems do not require the source parameter + * so if there is only one parameter left, it must be the target. */ - if (optind + 2 < argc) + if (optind >= argc) { - nsh_output(vtbl, g_fmttoomanyargs, argv[0]); + nsh_output(vtbl, g_fmtargrequired, argv[0]); return ERROR; } - else if (optind + 2 > argc) + + source = NULL; + target = argv[optind]; + optind++; + + if (optind < argc) { - nsh_output(vtbl, g_fmtargrequired, argv[0]); - return ERROR; + source = target; + target = argv[optind]; + optind++; + + if (optind < argc) + { + nsh_output(vtbl, g_fmttoomanyargs, argv[0]); + return ERROR; + } } /* While the above parsing for the -t argument looks nice, the -t argument @@ -277,29 +292,44 @@ int cmd_mount(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv) * working directory. */ - source = nsh_getfullpath(vtbl, argv[optind]); - if (!source) + fullsource = NULL; + fulltarget = NULL; + + if (source) { - return ERROR; + fullsource = nsh_getfullpath(vtbl, source); + if (!fullsource) + { + return ERROR; + } } - target = nsh_getfullpath(vtbl, argv[optind+1]); - if (!target) + fulltarget = nsh_getfullpath(vtbl, target); + if (!fulltarget) { - nsh_freefullpath(source); - return ERROR; + ret = ERROR; + goto errout; } /* Perform the mount */ - ret = mount(source, target, filesystem, 0, NULL); + ret = mount(fullsource, fulltarget, filesystem, 0, NULL); if (ret < 0) { nsh_output(vtbl, g_fmtcmdfailed, argv[0], "mount", NSH_ERRNO); } - nsh_freefullpath(source); - nsh_freefullpath(target); +errout: + if (fullsource) + { + nsh_freefullpath(fullsource); + } + + if (fulltarget) + { + nsh_freefullpath(fulltarget); + } + return ret; } #endif diff --git a/apps/nshlib/nsh_parse.c b/apps/nshlib/nsh_parse.c index c36724372..ef4125a63 100644 --- a/apps/nshlib/nsh_parse.c +++ b/apps/nshlib/nsh_parse.c @@ -301,7 +301,7 @@ static const struct cmdmap_s g_cmdmap[] = #if !defined(CONFIG_DISABLE_MOUNTPOINT) && CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_FS_READABLE) # ifndef CONFIG_NSH_DISABLE_MOUNT - { "mount", cmd_mount, 1, 5, "[-t ]" }, + { "mount", cmd_mount, 1, 5, "[-t [] ]" }, # endif #endif diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 57925a8b3..8d6d81363 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3961,4 +3961,7 @@ apps/include/apps.h moved to include/nuttx/binfmt/builtin.h * binfmt/libbuiltin/libbuiltin_utils.c: Move utility builtin utility functions from apps/builtin/exec_builtins.c to - binfmt/libbuiltin/libbuiltin_utils.c \ No newline at end of file + binfmt/libbuiltin/libbuiltin_utils.c + * binfmt/builtin.c and binfmt/libbuiltin: Add a binary "loader" + that can be used to execute builtin programs from the BINFS + file system. diff --git a/nuttx/binfmt/builtin.c b/nuttx/binfmt/builtin.c new file mode 100644 index 000000000..e591ebea8 --- /dev/null +++ b/nuttx/binfmt/builtin.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * binfmt/builtin.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BUILTIN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int builtin_loadbinary(FAR struct binary_s *binp); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct binfmt_s g_builtin_binfmt = +{ + NULL, /* next */ + builtin_loadbinary, /* load */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_loadbinary + * + * Description: + * Verify that the file is an builtin binary. + * + ****************************************************************************/ + +static int builtin_loadbinary(struct binary_s *binp) +{ + FAR const char *filename; + int fd; + int index; + int ret; + + bvdbg("Loading file: %s\n", binp->filename); + + /* Open the binary file for reading (only) */ + + fd = open(filename, O_RDONLY); + if (fd < 0) + { + int errval = errno; + bdbg("ERROR: Failed to open binary %s: %d\n", filename, errval); + return -errval; + } + + /* If this file is a BINFS file system, then we can recover the name of + * the file using the FIOC_FILENAME ioctl() call. + */ + + ret = ioctl(fd, FIOC_FILENAME, (unsigned long)((uintptr_t)&filename)); + if (ret < 0) + { + int errval = errno; + bdbg("ERROR: FIOC_FILENAME ioctl failed: %d\n", errval); + return -errval; + } + + /* Other file systems may also support FIOC_FILENAME, so the real proof + * is that we can look up the index to this name in g_builtins[]. + */ + + index = builtin_isavail(filename); + if (index < 0) + { + int errval = errno; + bdbg("ERROR: %s is not a builtin application\n", filename); + return -errval; + + } + + /* Return the load information. NOTE: that there is no way to configure + * the priority. That is a bug and needs to be fixed. + */ + + binp->entrypt = g_builtins[index].main; + binp->stacksize = g_builtins[index].stacksize; + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_initialize + * + * Description: + * Builtin support is built unconditionally. However, it order to + * use this binary format, this function must be called during system + * format in order to register the builtin binary format. + * + * Returned Value: + * This is a NuttX internal function so it follows the convention that + * 0 (OK) is returned on success and a negated errno is returned on + * failure. + * + ****************************************************************************/ + +int builtin_initialize(void) +{ + int ret; + + /* Register ourselves as a binfmt loader */ + + bvdbg("Registering Builtin Loader\n"); + + ret = register_binfmt(&g_builtin_binfmt); + if (ret != 0) + { + bdbg("Failed to register binfmt: %d\n", ret); + } + + return ret; +} + +/**************************************************************************** + * Name: builtin_uninitialize + * + * Description: + * Unregister the builtin binary loader + * + * Returned Value: + * None + * + ****************************************************************************/ + +void builtin_uninitialize(void) +{ + unregister_binfmt(&g_builtin_binfmt); +} + +#endif /* CONFIG_BUILTIN */ + diff --git a/nuttx/binfmt/elf.c b/nuttx/binfmt/elf.c index bcebf13ca..9dc59fbdd 100644 --- a/nuttx/binfmt/elf.c +++ b/nuttx/binfmt/elf.c @@ -183,7 +183,7 @@ static int elf_loadbinary(struct binary_s *binp) bvdbg("Loading file: %s\n", binp->filename); - /* Initialize the xflat library to load the program binary. */ + /* Initialize the ELF library to load the program binary. */ ret = elf_init(binp->filename, &loadinfo); elf_dumploadinfo(&loadinfo); diff --git a/nuttx/binfmt/libbuiltin/Make.defs b/nuttx/binfmt/libbuiltin/Make.defs index 1d129294c..96e8b6c37 100644 --- a/nuttx/binfmt/libbuiltin/Make.defs +++ b/nuttx/binfmt/libbuiltin/Make.defs @@ -33,11 +33,14 @@ # ############################################################################ -# Legacy configurations don't set CONFIG_BUILTIN -# ifeq ($(CONFIG_BUILTIN),y) +ifeq ($(CONFIG_BUILTIN),y) # Builtin application interfaces +BINFMT_CSRCS += builtin.c + +# Builtin library interfaces + BINFMT_CSRCS += libbuiltin_utils.c # Hook the libelf subdirectory into the build @@ -46,4 +49,4 @@ VPATH += libbuiltin SUBDIRS += libbuiltin DEPPATH += --dep-path libbuiltin -# endif +endif diff --git a/nuttx/configs/cloudctrl/nsh/defconfig b/nuttx/configs/cloudctrl/nsh/defconfig index 8f145d3ab..009d9bdfa 100644 --- a/nuttx/configs/cloudctrl/nsh/defconfig +++ b/nuttx/configs/cloudctrl/nsh/defconfig @@ -463,6 +463,7 @@ CONFIG_MM_REGIONS=1 # CONFIG_BINFMT_DISABLE is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set +CONFIG_BUILTIN=y # CONFIG_SYMTAB_ORDEREDBYNAME is not set # @@ -505,7 +506,6 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/compal_e88/nsh_highram/defconfig b/nuttx/configs/compal_e88/nsh_highram/defconfig index a6868e869..7715317b7 100644 --- a/nuttx/configs/compal_e88/nsh_highram/defconfig +++ b/nuttx/configs/compal_e88/nsh_highram/defconfig @@ -250,6 +250,8 @@ CONFIG_NSH_NOMAC=y CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 + +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y # diff --git a/nuttx/configs/compal_e99/nsh_compalram/defconfig b/nuttx/configs/compal_e99/nsh_compalram/defconfig index 058dc2aa2..8739c6b91 100644 --- a/nuttx/configs/compal_e99/nsh_compalram/defconfig +++ b/nuttx/configs/compal_e99/nsh_compalram/defconfig @@ -256,6 +256,8 @@ CONFIG_NSH_NOMAC=y CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 + +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y # diff --git a/nuttx/configs/compal_e99/nsh_highram/defconfig b/nuttx/configs/compal_e99/nsh_highram/defconfig index ee1405ca5..9efcd9a81 100644 --- a/nuttx/configs/compal_e99/nsh_highram/defconfig +++ b/nuttx/configs/compal_e99/nsh_highram/defconfig @@ -254,6 +254,8 @@ CONFIG_NSH_NOMAC=y CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 + +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y # diff --git a/nuttx/configs/fire-stm32v2/nsh/defconfig b/nuttx/configs/fire-stm32v2/nsh/defconfig index 266098496..7a4bc1bed 100644 --- a/nuttx/configs/fire-stm32v2/nsh/defconfig +++ b/nuttx/configs/fire-stm32v2/nsh/defconfig @@ -501,6 +501,15 @@ CONFIG_FAT_MAXFNAME=32 CONFIG_MM_REGIONS=1 # CONFIG_GRAN is not set +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + # # Library Routines # @@ -531,7 +540,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/hymini-stm32v/nsh2/defconfig b/nuttx/configs/hymini-stm32v/nsh2/defconfig index 7183a8632..61c7fcd69 100644 --- a/nuttx/configs/hymini-stm32v/nsh2/defconfig +++ b/nuttx/configs/hymini-stm32v/nsh2/defconfig @@ -447,6 +447,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/mirtoo/ostest/defconfig b/nuttx/configs/mirtoo/ostest/defconfig index 7c8596dbf..46612d993 100644 --- a/nuttx/configs/mirtoo/ostest/defconfig +++ b/nuttx/configs/mirtoo/ostest/defconfig @@ -401,7 +401,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # -CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_BUILTIN_APPS=n CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 diff --git a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig index 15b26899b..a25be53de 100755 --- a/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/ftpc/defconfig @@ -163,7 +163,7 @@ CONFIG_RAW_BINARY=n # # General OS setup # -CONFIG_USER_ENTRYPOINT="ftpc_main" +CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_DEBUG=n CONFIG_DEBUG_VERBOSE=n CONFIG_DEBUG_SYMBOLS=n @@ -489,6 +489,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="RIGHT" # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index 8ed82a3ed..c096cdb0e 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -470,6 +470,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="RIGHT" # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/olimex-stm32-p107/nsh/defconfig b/nuttx/configs/olimex-stm32-p107/nsh/defconfig index 09d447e14..1dcb5123a 100644 --- a/nuttx/configs/olimex-stm32-p107/nsh/defconfig +++ b/nuttx/configs/olimex-stm32-p107/nsh/defconfig @@ -476,6 +476,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig index fe24cb886..d59e2b7d2 100644 --- a/nuttx/configs/pcblogic-pic32mx/nsh/defconfig +++ b/nuttx/configs/pcblogic-pic32mx/nsh/defconfig @@ -398,6 +398,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/pic32-starterkit/nsh/defconfig b/nuttx/configs/pic32-starterkit/nsh/defconfig index 8bf0432e2..b50dd77fb 100644 --- a/nuttx/configs/pic32-starterkit/nsh/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh/defconfig @@ -562,6 +562,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/pic32-starterkit/nsh2/defconfig b/nuttx/configs/pic32-starterkit/nsh2/defconfig index fb54a2949..2a1be755d 100644 --- a/nuttx/configs/pic32-starterkit/nsh2/defconfig +++ b/nuttx/configs/pic32-starterkit/nsh2/defconfig @@ -561,6 +561,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/pic32mx7mmb/nsh/defconfig b/nuttx/configs/pic32mx7mmb/nsh/defconfig index 62f524ee2..eb4b64e72 100644 --- a/nuttx/configs/pic32mx7mmb/nsh/defconfig +++ b/nuttx/configs/pic32mx7mmb/nsh/defconfig @@ -608,6 +608,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/sam3u-ek/touchscreen/defconfig b/nuttx/configs/sam3u-ek/touchscreen/defconfig index 278c55478..25f808635 100755 --- a/nuttx/configs/sam3u-ek/touchscreen/defconfig +++ b/nuttx/configs/sam3u-ek/touchscreen/defconfig @@ -443,6 +443,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/shenzhou/nsh/defconfig b/nuttx/configs/shenzhou/nsh/defconfig index 383522b6f..d23290e86 100644 --- a/nuttx/configs/shenzhou/nsh/defconfig +++ b/nuttx/configs/shenzhou/nsh/defconfig @@ -463,6 +463,7 @@ CONFIG_MM_REGIONS=1 # CONFIG_BINFMT_DISABLE is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set +CONFIG_BUILTIN=y # CONFIG_SYMTAB_ORDEREDBYNAME is not set # @@ -505,7 +506,6 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/shenzhou/nxwm/defconfig b/nuttx/configs/shenzhou/nxwm/defconfig index b9bf72aeb..e13fb72dc 100644 --- a/nuttx/configs/shenzhou/nxwm/defconfig +++ b/nuttx/configs/shenzhou/nxwm/defconfig @@ -586,6 +586,7 @@ CONFIG_MM_REGIONS=1 # CONFIG_BINFMT_EXEPATH is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set +# CONFIG_BUILTIN is not set # CONFIG_PIC is not set # CONFIG_SYMTAB_ORDEREDBYNAME is not set @@ -630,7 +631,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Named Applications # -CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/shenzhou/thttpd/defconfig b/nuttx/configs/shenzhou/thttpd/defconfig index d7af34821..05d5fa337 100644 --- a/nuttx/configs/shenzhou/thttpd/defconfig +++ b/nuttx/configs/shenzhou/thttpd/defconfig @@ -474,7 +474,6 @@ CONFIG_HAVE_CXX=y # # Named Applications # -CONFIG_BUILTIN=y # # Examples @@ -835,6 +834,7 @@ CONFIG_NETUTILS_WEBCLIENT=y # NSH Library # CONFIG_NSH_LIBRARY=y +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y # diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index 146519aa6..3f52dfe69 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -230,6 +230,7 @@ CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/sim/nsh2/defconfig b/nuttx/configs/sim/nsh2/defconfig index b7e31b9e3..bcbe806cc 100644 --- a/nuttx/configs/sim/nsh2/defconfig +++ b/nuttx/configs/sim/nsh2/defconfig @@ -274,6 +274,7 @@ CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3210e-eval/nsh2/defconfig b/nuttx/configs/stm3210e-eval/nsh2/defconfig index 063307143..2be2dcefd 100644 --- a/nuttx/configs/stm3210e-eval/nsh2/defconfig +++ b/nuttx/configs/stm3210e-eval/nsh2/defconfig @@ -571,6 +571,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3210e-eval/nxconsole/defconfig b/nuttx/configs/stm3210e-eval/nxconsole/defconfig index 94dbf500f..9e7ed363f 100644 --- a/nuttx/configs/stm3210e-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3210e-eval/nxconsole/defconfig @@ -496,6 +496,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3210e-eval/pm/defconfig b/nuttx/configs/stm3210e-eval/pm/defconfig index c113ddf60..e4a976727 100644 --- a/nuttx/configs/stm3210e-eval/pm/defconfig +++ b/nuttx/configs/stm3210e-eval/pm/defconfig @@ -616,6 +616,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3220g-eval/nsh/defconfig b/nuttx/configs/stm3220g-eval/nsh/defconfig index 8486c4fd6..71a03d212 100644 --- a/nuttx/configs/stm3220g-eval/nsh/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh/defconfig @@ -672,6 +672,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3220g-eval/nsh2/defconfig b/nuttx/configs/stm3220g-eval/nsh2/defconfig index bc641b8be..84950645b 100644 --- a/nuttx/configs/stm3220g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3220g-eval/nsh2/defconfig @@ -659,6 +659,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3220g-eval/ostest/defconfig b/nuttx/configs/stm3220g-eval/ostest/defconfig index 3ec417516..f03f67cbd 100644 --- a/nuttx/configs/stm3220g-eval/ostest/defconfig +++ b/nuttx/configs/stm3220g-eval/ostest/defconfig @@ -562,7 +562,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # -CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_BUILTIN_APPS=n CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 diff --git a/nuttx/configs/stm3240g-eval/nsh/defconfig b/nuttx/configs/stm3240g-eval/nsh/defconfig index 82caf1622..efc60cd2f 100644 --- a/nuttx/configs/stm3240g-eval/nsh/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh/defconfig @@ -672,6 +672,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3240g-eval/nsh2/defconfig b/nuttx/configs/stm3240g-eval/nsh2/defconfig index 9e7d57ade..122910e4e 100644 --- a/nuttx/configs/stm3240g-eval/nsh2/defconfig +++ b/nuttx/configs/stm3240g-eval/nsh2/defconfig @@ -619,6 +619,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3240g-eval/nxconsole/defconfig b/nuttx/configs/stm3240g-eval/nxconsole/defconfig index 92c3ceb75..bd8be9f5d 100644 --- a/nuttx/configs/stm3240g-eval/nxconsole/defconfig +++ b/nuttx/configs/stm3240g-eval/nxconsole/defconfig @@ -642,6 +642,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm3240g-eval/ostest/defconfig b/nuttx/configs/stm3240g-eval/ostest/defconfig index f9e690a10..f7eb4ef95 100644 --- a/nuttx/configs/stm3240g-eval/ostest/defconfig +++ b/nuttx/configs/stm3240g-eval/ostest/defconfig @@ -574,7 +574,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # -CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_BUILTIN_APPS=n CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 diff --git a/nuttx/configs/stm3240g-eval/webserver/defconfig b/nuttx/configs/stm3240g-eval/webserver/defconfig index 792eafa0a..6b4d47e53 100644 --- a/nuttx/configs/stm3240g-eval/webserver/defconfig +++ b/nuttx/configs/stm3240g-eval/webserver/defconfig @@ -673,7 +673,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # -CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_BUILTIN_APPS=n CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 diff --git a/nuttx/configs/stm32f100rc_generic/nsh/defconfig b/nuttx/configs/stm32f100rc_generic/nsh/defconfig index 12193e7ed..aea79ff3f 100644 --- a/nuttx/configs/stm32f100rc_generic/nsh/defconfig +++ b/nuttx/configs/stm32f100rc_generic/nsh/defconfig @@ -393,6 +393,7 @@ CONFIG_MM_REGIONS=1 # CONFIG_BINFMT_DISABLE is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set +CONFIG_BUILTIN=y CONFIG_SYMTAB_ORDEREDBYNAME=y # @@ -428,7 +429,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Named Applications # -CONFIG_BUILTIN=y # # Examples diff --git a/nuttx/configs/stm32f4discovery/nsh/defconfig b/nuttx/configs/stm32f4discovery/nsh/defconfig index d9917b3a8..3ec117055 100644 --- a/nuttx/configs/stm32f4discovery/nsh/defconfig +++ b/nuttx/configs/stm32f4discovery/nsh/defconfig @@ -603,6 +603,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/stm32f4discovery/pm/defconfig b/nuttx/configs/stm32f4discovery/pm/defconfig index 1636f6ecb..332235050 100644 --- a/nuttx/configs/stm32f4discovery/pm/defconfig +++ b/nuttx/configs/stm32f4discovery/pm/defconfig @@ -622,6 +622,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/sure-pic32mx/nsh/defconfig b/nuttx/configs/sure-pic32mx/nsh/defconfig index d15bac1f4..a5977733c 100644 --- a/nuttx/configs/sure-pic32mx/nsh/defconfig +++ b/nuttx/configs/sure-pic32mx/nsh/defconfig @@ -434,6 +434,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/sure-pic32mx/usbnsh/defconfig b/nuttx/configs/sure-pic32mx/usbnsh/defconfig index 3ebfde834..3ab4563e9 100644 --- a/nuttx/configs/sure-pic32mx/usbnsh/defconfig +++ b/nuttx/configs/sure-pic32mx/usbnsh/defconfig @@ -431,6 +431,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/ubw32/nsh/defconfig b/nuttx/configs/ubw32/nsh/defconfig index 8769fa677..c9718ca8d 100644 --- a/nuttx/configs/ubw32/nsh/defconfig +++ b/nuttx/configs/ubw32/nsh/defconfig @@ -421,6 +421,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/configs/vsn/nsh/defconfig b/nuttx/configs/vsn/nsh/defconfig index 5ec7e06eb..88d14aba6 100755 --- a/nuttx/configs/vsn/nsh/defconfig +++ b/nuttx/configs/vsn/nsh/defconfig @@ -459,6 +459,7 @@ CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 # # Settings for apps/nshlib # +CONFIG_BUILTIN=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_STRERROR=n diff --git a/nuttx/fs/fs_mount.c b/nuttx/fs/fs_mount.c index 1b3da8dc3..a91e7d366 100644 --- a/nuttx/fs/fs_mount.c +++ b/nuttx/fs/fs_mount.c @@ -221,7 +221,7 @@ int mount(FAR const char *source, FAR const char *target, /* Find the specified filesystem. Try the block driver file systems first */ #ifdef BDFS_SUPPORT - if ((mops = mount_findfs(g_bdfsmap, filesystemtype)) != NULL) + if (source && (mops = mount_findfs(g_bdfsmap, filesystemtype)) != NULL) { /* Make sure that a block driver argument was provided */ -- cgit v1.2.3 From e7e1c6aee0e0d84f290995a092c1722878a54044 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 16 Jan 2013 21:38:00 +0000 Subject: convert configs/sim/nsh to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5526 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/Makefile | 8 +- apps/examples/README.txt | 2 +- apps/examples/hello/Makefile | 2 +- nuttx/ChangeLog | 3 + nuttx/Documentation/NuttShell.html | 18 +- nuttx/configs/compal_e88/nsh_highram/defconfig | 2 +- nuttx/configs/compal_e99/nsh_compalram/defconfig | 2 +- nuttx/configs/compal_e99/nsh_highram/defconfig | 3 +- nuttx/configs/sim/README.txt | 19 +- nuttx/configs/sim/nsh/appconfig | 47 -- nuttx/configs/sim/nsh/defconfig | 627 ++++++++++++++++------- 11 files changed, 479 insertions(+), 254 deletions(-) delete mode 100644 nuttx/configs/sim/nsh/appconfig diff --git a/apps/examples/Makefile b/apps/examples/Makefile index a11dbf240..939748075 100644 --- a/apps/examples/Makefile +++ b/apps/examples/Makefile @@ -57,13 +57,11 @@ SUBDIRS += usbserial sendmail usbstorage usbterm watchdog wget wgetjson CNTXTDIRS = pwm ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) -CNTXTDIRS += adc can cdcacm composite cxxtest dhcpd discover ftpd json keypadtest -CNTXTDIRS += modbus nettest nxlines relays qencoder telnetd watchdog wgetjson +CNTXTDIRS += adc can cdcacm composite cxxtest dhcpd discover ftpd hello json +CNTXTDIRS += keypadtestmodbus nettest nxlines relays qencoder telnetd watchdog +CNTXTDIRS += wgetjson endif -ifeq ($(CONFIG_EXAMPLES_HELLO_BUILTIN),y) -CNTXTDIRS += hello -endif ifeq ($(CONFIG_EXAMPLES_HELLOXX_BUILTIN),y) CNTXTDIRS += helloxx endif diff --git a/apps/examples/README.txt b/apps/examples/README.txt index 5c6332ee3..5996cbb70 100644 --- a/apps/examples/README.txt +++ b/apps/examples/README.txt @@ -491,7 +491,7 @@ examples/hello than examples/null with a single printf statement. Really useful only for bringing up new NuttX architectures. - * CONFIG_EXAMPLES_HELLO_BUILTIN + * CONFIG_NSH_BUILTIN_APPS Build the "Hello, World" example as an NSH built-in application. examples/helloxx diff --git a/apps/examples/hello/Makefile b/apps/examples/hello/Makefile index fc98fa7f4..c3b9744d7 100644 --- a/apps/examples/hello/Makefile +++ b/apps/examples/hello/Makefile @@ -83,7 +83,7 @@ $(COBJS): %$(OBJEXT): %.c $(call ARCHIVE, $(BIN), $(OBJS)) @touch .built -ifeq ($(CONFIG_EXAMPLES_HELLO_BUILTIN),y) +ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) $(BUILTIN_REGISTRY)$(DELIM)$(APPNAME)_main.bdat: $(DEPCONFIG) Makefile $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 8d6d81363..6bc66ec9d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3965,3 +3965,6 @@ * binfmt/builtin.c and binfmt/libbuiltin: Add a binary "loader" that can be used to execute builtin programs from the BINFS file system. + * configs/sim/nsh: Convert to use kconfig-frontends configuration + tool. + diff --git a/nuttx/Documentation/NuttShell.html b/nuttx/Documentation/NuttShell.html index 273898476..950428e8a 100644 --- a/nuttx/Documentation/NuttShell.html +++ b/nuttx/Documentation/NuttShell.html @@ -2518,6 +2518,8 @@ nsh> Support external registered, "builtin" applications that can be executed from the NSH command line (see apps/README.txt for more information). + This required CONFIG_BUILTIN to enable NuttX support for + "builtin" applications. @@ -3227,8 +3229,20 @@ struct cmdmap_s

          These applications are built-into NSH in the sense that they can be executed by simply typing the name of the application at the NSH prompt. - Built-in application support is enabled with the configuration option CONFIG_NSH_BUILTIN_APPS. - When this configuration option is set, you will also be able to see the built-in applications if you enter "nsh> help". + Built-in application support is enabled with these configuration option: +

          +
            +
          • + CONFIG_BUILTIN: + Enable NuttX support for builtin applications. +
            • +
          • + CONFIG_NSH_BUILTIN_APPS: + Enable NSH support for builtin applications. +
            • +
          +

          + When these configuration options are set, you will also be able to see the built-in applications if you enter "nsh> help". They will appear at the bottom of the list of NSH commands under:

          diff --git a/nuttx/configs/compal_e88/nsh_highram/defconfig b/nuttx/configs/compal_e88/nsh_highram/defconfig index 7715317b7..9d5c0e3c4 100644 --- a/nuttx/configs/compal_e88/nsh_highram/defconfig +++ b/nuttx/configs/compal_e88/nsh_highram/defconfig @@ -256,7 +256,7 @@ CONFIG_NSH_BUILTIN_APPS=y # # Settings for examples/hello -CONFIG_EXAMPLES_HELLO_BUILTIN=y +# # # Settings for examples/wget diff --git a/nuttx/configs/compal_e99/nsh_compalram/defconfig b/nuttx/configs/compal_e99/nsh_compalram/defconfig index 8739c6b91..79fe93ab5 100644 --- a/nuttx/configs/compal_e99/nsh_compalram/defconfig +++ b/nuttx/configs/compal_e99/nsh_compalram/defconfig @@ -224,7 +224,7 @@ CONFIG_NET_RESOLV_ENTRIES=4 # # Settings for examples/hello -CONFIG_EXAMPLES_HELLO_BUILTIN=y +# # # Settings for examples/uip diff --git a/nuttx/configs/compal_e99/nsh_highram/defconfig b/nuttx/configs/compal_e99/nsh_highram/defconfig index 9efcd9a81..11ee153fa 100644 --- a/nuttx/configs/compal_e99/nsh_highram/defconfig +++ b/nuttx/configs/compal_e99/nsh_highram/defconfig @@ -260,7 +260,8 @@ CONFIG_NSH_BUILTIN_APPS=y # # Settings for examples/hello -CONFIG_EXAMPLES_HELLO_BUILTIN=y +# + CONFIG_EXAMPLES_NXHELLO_BUILTIN=y CONFIG_EXAMPLES_NXTEXT_BUILTIN=y CONFIG_EXAMPLES_NXIMAGE_BUILTIN=y diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 165e92b96..6e124a3a1 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -270,13 +270,26 @@ nsh Description ----------- - Configures to use the NuttShell at apps/examples/nsh. This version has - one builtin function: This configuration: apps/examples/hello. This - configuration may be selected as follows: + Configures to use the NuttShell at apps/examples/nsh. This configuration + may be selected as follows: cd /tools ./configure.sh sim/nsh + NOTES: + ------ + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. This version has one builtin function: This configuration: + apps/examples/hello. + nsh2 Description diff --git a/nuttx/configs/sim/nsh/appconfig b/nuttx/configs/sim/nsh/appconfig deleted file mode 100644 index 3f50f6818..000000000 --- a/nuttx/configs/sim/nsh/appconfig +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# configs/sim/nsh/appconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nsh - -# The NSH Library - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - -# Example built-in application - -CONFIGURED_APPS += examples/hello diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index 3f52dfe69..8dc5ddcce 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -1,148 +1,154 @@ -############################################################################ -# sim/nsh/defconfig -# -# Copyright (C) 2008-2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture selection # -CONFIG_ARCH="sim" -CONFIG_ARCH_SIM=y -CONFIG_ARCH_BOARD="sim" -CONFIG_ARCH_BOARD_SIM=y +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y # -# General OS setup +# Build Setup # -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set CONFIG_DEBUG_SYMBOLS=y -CONFIG_HAVE_CXX=n -CONFIG_HAVE_CXXINITIALIZE=n -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=0 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=32 -CONFIG_START_YEAR=2008 -CONFIG_START_MONTH=6 -CONFIG_START_DAY=1 -CONFIG_JULIAN_TIME=n -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n -CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WORKQUEUE=n -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=17 -CONFIG_SCHED_WAITPID=y -CONFIG_SCHED_ATEXIT=n -CONFIG_SCHED_ONEXIT=n +# +# System Type +# +# CONFIG_ARCH_8051 is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +CONFIG_ARCH_SIM=y +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="sim" +CONFIG_BOARD_LOOPSPERMSEC= # -# System Logging +# Simulation Configuration Options # +# CONFIG_SIM_M32 is not set +# CONFIG_SIM_WALLTIME is not set -CONFIG_SYSLOG=n -CONFIG_SYSLOG_DEVPATH="/dev/syslog" -CONFIG_SYSLOG_CHAR=n +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_IRQPRIO is not set +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_STACKDUMP is not set +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_RAMLOG=n -CONFIG_RAMLOG_CONSOLE=n -CONFIG_RAMLOG_SYSLOG=y -#CONFIG_RAMLOG_NPOLLWAITERS -#CONFIG_RAMLOG_CONSOLE_BUFSIZE +# +# Board Settings +# +CONFIG_DRAM_START= +CONFIG_DRAM_SIZE= # -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. +# Boot options # -# There are certain dependency relationships in these -# features. +CONFIG_BOOT_RUNFROMEXTSRAM=y +# CONFIG_BOOT_RUNFROMFLASH is not set +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + # -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. +# Board Selection # -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n -CONFIG_DISABLE_POLL=y +CONFIG_ARCH_BOARD_SIM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sim" # -# Misc libc settings +# Common Board Options # -CONFIG_NOPRINTF_FIELDWIDTH=n +CONFIG_NSH_MMCSDMINOR=0 # -# Allow for architecture optimized implementations +# Board-Specific Options # -# The architecture can provide optimized versions of the -# following to improve sysem performance + # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=32 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2008 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=1 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y # -# General build options +# Signal Numbers # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=n -CONFIG_RAW_BINARY=n +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 # # Sizes of configurable things (0 disables) @@ -153,8 +159,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=32 CONFIG_NFILE_STREAMS=16 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=1024 -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=32 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=4 @@ -162,91 +166,299 @@ CONFIG_PREALLOC_WDOGS=32 CONFIG_PREALLOC_TIMERS=8 # -# Filesystem configuration +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=8192 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration # +# CONFIG_FS_RAMMAP is not set CONFIG_FS_FAT=y CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=n +CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FS_NXFFS is not set CONFIG_FS_ROMFS=y CONFIG_FS_BINFS=y # -# TCP/IP and UDP support via uIP +# System Logging # -CONFIG_NET=n -CONFIG_NET_IPv6=n -CONFIG_NSOCKET_DESCRIPTORS=0 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_BUFSIZE=420 -CONFIG_NET_TCP=n -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_UDP=n -CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=10 -CONFIG_NET_ICMP=n -CONFIG_NET_ICMP_PING=n -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=y -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_SYSLOG is not set # -# Settings for examples/hello +# Graphics Support # -CONFIG_EXAMPLES_HELLO_BUILTIN=y +# CONFIG_NX is not set # -# UIP Network Utilities +# Memory Management # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_GRAN is not set # -# Settings for examples/uip -CONFIG_EXAMPLES_UIP_IPADDR=0xc0a80080 -CONFIG_EXAMPLES_UIP_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set # -# Settings for examples/nettest -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=n -CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a +# Library Routines +# # -# Settings for examples/ostest -CONFIG_EXAMPLES_OSTEST_LOOPS=100 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=1024 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# Settings for apps/nshlib +# Non-standard Helper Functions # -CONFIG_BUILTIN=y +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=80 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_ROMFSETC=y -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=n -CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=n -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 CONFIG_NSH_ROMFSMOUNTPT="/etc" CONFIG_NSH_INITSCRIPT="init.d/rcS" CONFIG_NSH_ROMFSDEVNO=1 @@ -255,23 +467,54 @@ CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FATSECTSIZE=512 CONFIG_NSH_FATNSECTORS=1024 CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_CONDEV is not set +# CONFIG_NSH_ARCHINIT is not set # -# Settings for examples/mount -CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" -#CONFIG_EXAMPLES_MOUNT_NSECTORS=2048 -#CONFIG_EXAMPLES_MOUNT_SECTORSIZE=512 -#CONFIG_EXAMPLES_MOUNT_RAMDEVNO=1 +# NxWidgets/NxWM +# # -# Stack and heap information +# System NSH Add-Ons # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set -- cgit v1.2.3 From caeef71797019505fd450b1a0ae573ac5e490c6e Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 17 Jan 2013 00:30:12 +0000 Subject: Change the way thread priority is handled in binfmt/ to better match the way that priority is set up for the builtin tasks git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5527 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/elf/elf_main.c | 2 +- apps/examples/nxflat/nxflat_main.c | 2 +- nuttx/Documentation/NuttXBinfmt.html | 26 +++++- nuttx/Documentation/NuttXNxFlat.html | 2 +- nuttx/binfmt/binfmt_exec.c | 18 +--- nuttx/binfmt/binfmt_execmodule.c | 6 +- nuttx/binfmt/binfmt_loadmodule.c | 43 ++++++++++ nuttx/binfmt/builtin.c | 1 + nuttx/binfmt/libbuiltin/Make.defs | 4 +- nuttx/binfmt/libbuiltin/libbuiltin_getname.c | 92 ++++++++++++++++++++ nuttx/binfmt/libbuiltin/libbuiltin_isavail.c | 102 ++++++++++++++++++++++ nuttx/binfmt/libbuiltin/libbuiltin_utils.c | 121 --------------------------- nuttx/configs/sim/README.txt | 10 +++ nuttx/include/nuttx/binfmt/binfmt.h | 11 ++- 14 files changed, 290 insertions(+), 150 deletions(-) create mode 100644 nuttx/binfmt/libbuiltin/libbuiltin_getname.c create mode 100644 nuttx/binfmt/libbuiltin/libbuiltin_isavail.c delete mode 100644 nuttx/binfmt/libbuiltin/libbuiltin_utils.c diff --git a/apps/examples/elf/elf_main.c b/apps/examples/elf/elf_main.c index 66a47592c..2b5c0eb5e 100644 --- a/apps/examples/elf/elf_main.c +++ b/apps/examples/elf/elf_main.c @@ -321,7 +321,7 @@ int elf_main(int argc, char *argv[]) /* Execute the ELF module */ - ret = exec_module(&bin, 50); + ret = exec_module(&bin); mm_update(&g_mmstep, "after exec_module"); diff --git a/apps/examples/nxflat/nxflat_main.c b/apps/examples/nxflat/nxflat_main.c index 536bc1dd8..0c4846a5c 100644 --- a/apps/examples/nxflat/nxflat_main.c +++ b/apps/examples/nxflat/nxflat_main.c @@ -243,7 +243,7 @@ int nxflat_main(int argc, char *argv[]) /* Execute the ELF module */ - ret = exec_module(&bin, 50); + ret = exec_module(&bin); if (ret < 0) { err("ERROR: Failed to execute program '%s'\n", dirlist[i]); diff --git a/nuttx/Documentation/NuttXBinfmt.html b/nuttx/Documentation/NuttXBinfmt.html index 9c9fd3a51..7528b188b 100644 --- a/nuttx/Documentation/NuttXBinfmt.html +++ b/nuttx/Documentation/NuttXBinfmt.html @@ -8,7 +8,7 @@

          NuttX Binary Loader

          -

          Last Updated: December 17, 2012

          +

          Last Updated: January 16, 2013

          @@ -141,7 +141,7 @@ struct binary_s { /* Information provided to the loader to load and bind a module */ - FAR const char *filename; /* Full path to the binary to be loaded1 */ + FAR const char *filename; /* Full path to the binary to be loaded */ FAR const char **argv; /* Argument list */ FAR const struct symtab_s *exports; /* Table of exported symbols */ int nexports; /* The number of symbols in exports[] */ @@ -153,13 +153,33 @@ struct binary_s main_t entrypt; /* Entry point into a program module */ FAR void *mapped; /* Memory-mapped, address space */ FAR void *alloc[BINFMT_NALLOC]; /* Allocated address spaces */ + + /* Constructors/destructors */ + #ifdef CONFIG_BINFMT_CONSTRUCTORS FAR binfmt_ctor_t *ctors; /* Pointer to a list of constructors */ FAR binfmt_dtor_t *dtors; /* Pointer to a list of destructors */ uint16_t nctors; /* Number of constructors in the list */ uint16_t ndtors; /* Number of destructors in the list */ #endif + + /* Address environment. + * + * addrenv - This is the handle created by up_addrenv_create() that can be + * used to manage the tasks address space. + */ + +#ifdef CONFIG_ADDRENV + task_addrenv_t addrenv; /* Task address environment */ +#endif + size_t mapsize; /* Size of the mapped address region (needed for munmap) */ + + /* Start-up information that is provided by the loader, but may be modified + * by the caller between load_module() and exec_module() calls. + */ + + uint8_t priority; /* Task execution priority */ size_t stacksize; /* Size of the stack in bytes (unallocated) */ };
        @@ -291,7 +311,7 @@ This is a NuttX internal function so it follows the convention that 0 (OK<

        Function Prototype:

           #include <:nuttx/binfmt/binfmt.h>
-int exec_module(FAR const struct binary_s *bin, int priority);
+int exec_module(FAR const struct binary_s *bin);

        Description:

          diff --git a/nuttx/Documentation/NuttXNxFlat.html b/nuttx/Documentation/NuttXNxFlat.html index 3a2ed8046..ed04f7f77 100644 --- a/nuttx/Documentation/NuttXNxFlat.html +++ b/nuttx/Documentation/NuttXNxFlat.html @@ -668,7 +668,7 @@ cat ../syscall/syscall.csv ../libc/lib.csv | sort >tmp.csv

        -

        int exec_module(FAR const struct binary_s *bin, int priority) +

        int exec_module(FAR const struct binary_s *bin)

          Description: Execute a module that has been loaded into memory by load_module(). diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c index d5e274710..d878c8cc5 100644 --- a/nuttx/binfmt/binfmt_exec.c +++ b/nuttx/binfmt/binfmt_exec.c @@ -40,7 +40,6 @@ #include #include -#include #include #include @@ -75,8 +74,7 @@ * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. The priority of the executed program is set to be the - * same as the priority of the calling thread. + * one call. * * Input Parameter: * filename - Fulll path to the binary to be loaded @@ -95,18 +93,8 @@ int exec(FAR const char *filename, FAR const char **argv, FAR const struct symtab_s *exports, int nexports) { struct binary_s bin; - struct sched_param param; int ret; - /* Get the priority of this thread */ - - ret = sched_getparam(0, ¶m); - if (ret < 0) - { - bdbg("ERROR: sched_getparam failed: %d\n", errno); - return ERROR; - } - /* Load the module into memory */ memset(&bin, 0, sizeof(struct binary_s)); @@ -121,9 +109,9 @@ int exec(FAR const char *filename, FAR const char **argv, return ERROR; } - /* Then start the module at the priority of this thread */ + /* Then start the module */ - ret = exec_module(&bin, param.sched_priority); + ret = exec_module(&bin); if (ret < 0) { bdbg("ERROR: Failed to execute program '%s'\n", filename); diff --git a/nuttx/binfmt/binfmt_execmodule.c b/nuttx/binfmt/binfmt_execmodule.c index df8da5343..afa445abb 100644 --- a/nuttx/binfmt/binfmt_execmodule.c +++ b/nuttx/binfmt/binfmt_execmodule.c @@ -144,7 +144,7 @@ static inline int exec_ctors(FAR const struct binary_s *binp) * ****************************************************************************/ -int exec_module(FAR const struct binary_s *binp, int priority) +int exec_module(FAR const struct binary_s *binp) { FAR _TCB *tcb; #ifndef CONFIG_CUSTOM_STACK @@ -187,12 +187,12 @@ int exec_module(FAR const struct binary_s *binp, int priority) /* Initialize the task */ - ret = task_init(tcb, binp->filename, priority, stack, + ret = task_init(tcb, binp->filename, binp->priority, stack, binp->stacksize, binp->entrypt, binp->argv); #else /* Initialize the task */ - ret = task_init(tcb, binp->filename, priority, stack, + ret = task_init(tcb, binp->filename, binp->priority, stack, binp->entrypt, binp->argv); #endif if (ret < 0) diff --git a/nuttx/binfmt/binfmt_loadmodule.c b/nuttx/binfmt/binfmt_loadmodule.c index 112a6b35b..4f3dc6952 100644 --- a/nuttx/binfmt/binfmt_loadmodule.c +++ b/nuttx/binfmt/binfmt_loadmodule.c @@ -66,6 +66,39 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: load_default_priority + * + * Description: + * Set the default priority of the module to be loaded. This may be + * changed (1) by the actions of the binary format's load() method if + * the binary format contains priority informaition, or (2) by the user + * between calls to load_module() and exec_module(). + * + * Returned Value: + * Zero (OK) is returned on success; Otherwise, -1 (ERROR) is returned and + * the errno variable is set appropriately. + * + ****************************************************************************/ + +static int load_default_priority(FAR struct binary_s *bin) +{ + struct sched_param param; + + /* Get the priority of this thread */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + bdbg("ERROR: sched_getparam failed: %d\n", errno); + return ERROR; + } + + /* Save that as the priority of child thread */ + + bin->priority = param.sched_priority; +} + /**************************************************************************** * Name: load_absmodule * @@ -145,6 +178,16 @@ int load_module(FAR struct binary_s *bin) if (bin && bin->filename) #endif { + /* Set the default priority of the new program. */ + + ret = load_default_priority(bin) + if (ret < 0) + { + /* The errno is already set in this case */ + + return ERROR; + } + /* Were we given a relative path? Or an absolute path to the file to * be loaded? Absolute paths start with '/'. */ diff --git a/nuttx/binfmt/builtin.c b/nuttx/binfmt/builtin.c index e591ebea8..d36cb6326 100644 --- a/nuttx/binfmt/builtin.c +++ b/nuttx/binfmt/builtin.c @@ -136,6 +136,7 @@ static int builtin_loadbinary(struct binary_s *binp) binp->entrypt = g_builtins[index].main; binp->stacksize = g_builtins[index].stacksize; + binp->priority = g_builtins[index].priority; return OK; } diff --git a/nuttx/binfmt/libbuiltin/Make.defs b/nuttx/binfmt/libbuiltin/Make.defs index 96e8b6c37..5eec1acde 100644 --- a/nuttx/binfmt/libbuiltin/Make.defs +++ b/nuttx/binfmt/libbuiltin/Make.defs @@ -41,9 +41,9 @@ BINFMT_CSRCS += builtin.c # Builtin library interfaces -BINFMT_CSRCS += libbuiltin_utils.c +BINFMT_CSRCS += libbuiltin_getname.c libbuiltin_isavail.c -# Hook the libelf subdirectory into the build +# Hook the libbuiltin subdirectory into the build VPATH += libbuiltin SUBDIRS += libbuiltin diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_getname.c b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c new file mode 100644 index 000000000..01ac024f7 --- /dev/null +++ b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * binfmt/libbuiltin/libbuiltin_getname.c + * + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_getname + * + * Description: + * Return the name of the application at index in the table of builtin + * applications. + * + ****************************************************************************/ + +FAR const char *builtin_getname(int index) +{ + if (index < 0 || index >= number_builtins()) + { + return NULL; + } + + return g_builtins[index].name; +} diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c new file mode 100644 index 000000000..f99a4b81d --- /dev/null +++ b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * binfmt/libbuiltin/libbuiltin_isavail.c + * + * Originally by: + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With subsequent updates, modifications, and general maintenance by: + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: builtin_isavail + * + * Description: + * Return the index into the table of applications for the applicaiton with + * the name 'appname'. + * + ****************************************************************************/ + +int builtin_isavail(FAR const char *appname) +{ + int i; + + for (i = 0; g_builtins[i].name; i++) + { + if (!strncmp(g_builtins[i].name, appname, NAME_MAX)) + { + return i; + } + } + + set_errno(ENOENT); + return ERROR; +} diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_utils.c b/nuttx/binfmt/libbuiltin/libbuiltin_utils.c deleted file mode 100644 index b53becff9..000000000 --- a/nuttx/binfmt/libbuiltin/libbuiltin_utils.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * binfmt/libbuiltin/libbuiltin_utils.c - * - * Originally by: - * - * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise - * - * With subsequent updates, modifications, and general maintenance by: - * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: builtin_getname - * - * Description: - * Return the name of the application at index in the table of builtin - * applications. - * - ****************************************************************************/ - -FAR const char *builtin_getname(int index) -{ - if (index < 0 || index >= number_builtins()) - { - return NULL; - } - - return g_builtins[index].name; -} - -/**************************************************************************** - * Name: builtin_isavail - * - * Description: - * Return the index into the table of applications for the applicaiton with - * the name 'appname'. - * - ****************************************************************************/ - -int builtin_isavail(FAR const char *appname) -{ - int i; - - for (i = 0; g_builtins[i].name; i++) - { - if (!strncmp(g_builtins[i].name, appname, NAME_MAX)) - { - return i; - } - } - - set_errno(ENOENT); - return ERROR; -} diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 6e124a3a1..67ff73019 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -290,6 +290,16 @@ nsh 2. This version has one builtin function: This configuration: apps/examples/hello. + 3. This configuration has BINFS enabled so that the builtin applications + can be made visible in the file system. For example: + + NuttShell (NSH) NuttX-6.24 + nsh> mount -t binfs /bin + nsh> ls /bin + /bin: + hello + nsh> + nsh2 Description diff --git a/nuttx/include/nuttx/binfmt/binfmt.h b/nuttx/include/nuttx/binfmt/binfmt.h index 480e82c09..c6c7c874a 100644 --- a/nuttx/include/nuttx/binfmt/binfmt.h +++ b/nuttx/include/nuttx/binfmt/binfmt.h @@ -117,6 +117,12 @@ struct binary_s #endif size_t mapsize; /* Size of the mapped address region (needed for munmap) */ + + /* Start-up information that is provided by the loader, but may be modified + * by the caller between load_module() and exec_module() calls. + */ + + uint8_t priority; /* Task execution priority */ size_t stacksize; /* Size of the stack in bytes (unallocated) */ }; @@ -221,15 +227,14 @@ int unload_module(FAR const struct binary_s *bin); * ****************************************************************************/ -int exec_module(FAR const struct binary_s *bin, int priority); +int exec_module(FAR const struct binary_s *bin); /**************************************************************************** * Name: exec * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. The priority of the executed program is set to be the - * same as the priority of the calling thread. + * one call. * * Input Parameter: * filename - Fulll path to the binary to be loaded -- cgit v1.2.3