From e9d0885500d437cc6c89370d8131913bd1e7310b Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 17 Jan 2013 14:43:55 +0000 Subject: Add logic to automatically unload module on exit; Several patches from Mike Smith git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5528 42af7a65-404d-4744-a932-0658087f49c3 --- apps/builtin/Makefile | 2 +- apps/builtin/builtin.c | 33 ++++--------- apps/builtin/exec_builtin.c | 16 +++++-- nuttx/TODO | 23 ++++++++-- nuttx/binfmt/Makefile | 4 ++ nuttx/binfmt/binfmt_exec.c | 69 +++++++++++++++++++++++++++- nuttx/binfmt/builtin.c | 8 ++-- nuttx/binfmt/libbuiltin/libbuiltin_getname.c | 14 ++++-- nuttx/binfmt/libbuiltin/libbuiltin_isavail.c | 7 +-- nuttx/configs/sim/nsh/defconfig | 3 +- nuttx/fs/binfs/fs_binfs.c | 10 ++-- nuttx/include/nuttx/binfmt/binfmt.h | 47 +++++++++++++++++-- nuttx/include/nuttx/binfmt/builtin.h | 26 ++++------- nuttx/sched/Kconfig | 36 +++++++-------- nuttx/tools/Makefile.export | 12 +++-- 15 files changed, 214 insertions(+), 96 deletions(-) diff --git a/apps/builtin/Makefile b/apps/builtin/Makefile index d77054f41..f89532871 100644 --- a/apps/builtin/Makefile +++ b/apps/builtin/Makefile @@ -39,7 +39,7 @@ include $(APPDIR)/Make.defs # Source and object files ASRCS = -CSRCS = builtin.c exec_builtin.c +CSRCS = builtin.c builtin_list.c exec_builtin.c AOBJS = $(ASRCS:.S=$(OBJEXT)) COBJS = $(CSRCS:.c=$(OBJEXT)) diff --git a/apps/builtin/builtin.c b/apps/builtin/builtin.c index 7655a531d..d26f0a044 100644 --- a/apps/builtin/builtin.c +++ b/apps/builtin/builtin.c @@ -55,27 +55,8 @@ * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#include "builtin_proto.h" - -const struct builtin_s g_builtins[] = -{ -# include "builtin_list.h" - { NULL, 0, 0, 0 } -}; - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - +extern const struct builtin_s g_builtins[]; +extern const int g_builtin_count; /**************************************************************************** * Private Data @@ -89,9 +70,11 @@ const struct builtin_s g_builtins[] = * Public Functions ****************************************************************************/ -int number_builtins(void) +FAR const struct builtin_s *builtin_for_index(int index) { - return sizeof(g_builtins)/sizeof(struct builtin_s) - 1; + if (index < g_builtin_count) + { + return &g_builtins[index]; + } + return NULL; } - - diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index 05648590d..d4431164c 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -142,8 +142,17 @@ static void bultin_semtake(FAR sem_t *sem) static int builtin_taskcreate(int index, FAR const char **argv) { + FAR const struct builtin_s *b; int ret; + b = builtin_for_index(index); + + if (b == NULL) + { + errno = ENOENT; + return ERROR; + } + /* Disable pre-emption. This means that although we start the builtin * application here, it will not actually run until pre-emption is * re-enabled below. @@ -153,8 +162,7 @@ static int builtin_taskcreate(int index, FAR const char **argv) /* Start the builtin application task */ - ret = TASK_CREATE(g_builtins[index].name, g_builtins[index].priority, - g_builtins[index].stacksize, g_builtins[index].main, + ret = TASK_CREATE(b->name, b->priority, b->stacksize, b->main, (argv) ? &argv[1] : (FAR const char **)NULL); /* If robin robin scheduling is enabled, then set the scheduling policy @@ -171,7 +179,7 @@ static int builtin_taskcreate(int index, FAR const char **argv) * new task cannot yet have changed from its initial value. */ - param.sched_priority = g_builtins[index].priority; + param.sched_priority = b->priority; (void)sched_setscheduler(ret, SCHED_RR, ¶m); } #endif @@ -293,8 +301,6 @@ static inline int builtin_startproxy(int index, FAR const char **argv, int errcode; int ret; - DEBUGASSERT(path); - svdbg("index=%d argv=%p redirfile=%s oflags=%04x\n", index, argv, redirfile, oflags); diff --git a/nuttx/TODO b/nuttx/TODO index 248d2dafa..91b4aebaa 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -6,7 +6,7 @@ standards, things that could be improved, and ideas for enhancements. nuttx/ - (10) Task/Scheduler (sched/) + (11) Task/Scheduler (sched/) (1) Memory Managment (mm/) (3) Signals (sched/, arch/) (2) pthreads (sched/) @@ -193,7 +193,7 @@ o Task/Scheduler (sched/) Priority: Low Title: IMPROVED TASK CONTROL BLOCK STRUCTURE - All task resources that are shared amongst threads have + Description: All task resources that are shared amongst threads have their own "break-away", reference-counted structure. The Task Control Block (TCB) of each thread holds a reference to each breakaway structure (see include/nuttx/sched.h). @@ -206,11 +206,26 @@ o Task/Scheduler (sched/) - File descriptors (struct filelist) - FILE streams (struct streamlist) - Sockets (struct socketlist) - Status: Open - Priority: Low. This is an enhancement. It would slight reduce + Status: Open + Priority: Low. This is an enhancement. It would slight reduce memory usage but would also increase coupling. These resources are nicely modular now. + Title: ISSUES WITH atexit() AND on_exit() + Description: These functions execute with the following bad properties: + + 1. They run with interrupts disabled, + 2. They run in supervisor mode (if applicable), and + 3. They do not obey any setup of PIC or address + environments. Do they need to? + + The fix for all of these issues it to have the callbacks + run on the caller's thread (as with signal handlers). + Status: Open + Priority: Medium Low. This is an important change to some less + important interfaces. For the average user, these + functions are just fine the way they are. + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/binfmt/Makefile b/nuttx/binfmt/Makefile index 49dcd3d32..2f692beb1 100644 --- a/nuttx/binfmt/Makefile +++ b/nuttx/binfmt/Makefile @@ -52,6 +52,10 @@ ifeq ($(CONFIG_BINFMT_EXEPATH),y) BINFMT_CSRCS += binfmt_exepath.c endif +ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) +BINFMT_CSRCS += binfmt_schedunload.c +endif + # Symbol table source files BINFMT_CSRCS += symtab_findbyname.c symtab_findbyvalue.c diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c index d878c8cc5..1cead4384 100644 --- a/nuttx/binfmt/binfmt_exec.c +++ b/nuttx/binfmt/binfmt_exec.c @@ -74,7 +74,9 @@ * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. + * one call. If CONFIG_SCHED_ONEXIT is also defined, this function will + * automatically call schedule_unload() to unload the module when task + * exits. * * Input Parameter: * filename - Fulll path to the binary to be loaded @@ -84,7 +86,7 @@ * * Returned Value: * This is an end-user function, so it follows the normal convention: - * Returns the PID of the exec'ed module. On failure, it.returns + * It returns the PID of the exec'ed module. On failure, it returns * -1 (ERROR) and sets errno appropriately. * ****************************************************************************/ @@ -92,6 +94,66 @@ int exec(FAR const char *filename, FAR const char **argv, FAR const struct symtab_s *exports, int nexports) { +#ifdef CONFIG_SCHED_ONEXIT + FAR struct binary_s *bin; + int errorcode; + int ret; + + /* Allocate the load information */ + + bin = (FAR struct binary_s *)kzalloc(sizeof(struct binary_s)); + if (!bin) + { + set_errno(ENOMEM); + return ERROR; + } + + /* Load the module into memory */ + + bin->filename = filename; + bin->exports = exports; + bin->nexports = nexports; + + ret = load_module(bin); + if (ret < 0) + { + bdbg("ERROR: Failed to load program '%s'\n", filename); + kfree(bin); + return ERROR; + } + + /* Disable pre-emption so that the executed module does + * not return until we get a chance to connect the on_exit + * handler. + */ + + sched_lock(); + + /* Then start the module */ + + ret = exec_module(bin); + if (ret < 0) + { + bdbg("ERROR: Failed to execute program '%s'\n", filename); + sched_unlock(); + unload_module(bin); + kfree(bin); + return ERROR; + } + + /* Set up to unload the module (and free the binary_s structure) + * when the task exists. + */ + + ret = schedul_unload(ret, bin); + if (ret < 0) + { + bdbg("ERROR: Failed to schedul unload '%s'\n", filename); + } + + sched_unlock(); + return ret; +#else struct binary_s bin; int ret; @@ -119,7 +181,10 @@ int exec(FAR const char *filename, FAR const char **argv, return ERROR; } + /* TODO: How does the module get unloaded in this case? */ + return ret; +#endif } #endif /* CONFIG_BINFMT_DISABLE */ diff --git a/nuttx/binfmt/builtin.c b/nuttx/binfmt/builtin.c index d36cb6326..d80d9f5d8 100644 --- a/nuttx/binfmt/builtin.c +++ b/nuttx/binfmt/builtin.c @@ -89,6 +89,7 @@ static struct binfmt_s g_builtin_binfmt = static int builtin_loadbinary(struct binary_s *binp) { FAR const char *filename; + FAR const struct builtin_s *b; int fd; int index; int ret; @@ -134,9 +135,10 @@ static int builtin_loadbinary(struct binary_s *binp) * the priority. That is a bug and needs to be fixed. */ - binp->entrypt = g_builtins[index].main; - binp->stacksize = g_builtins[index].stacksize; - binp->priority = g_builtins[index].priority; + b = builtin_for_index(index); + binp->entrypt = b->main; + binp->stacksize = b->stacksize; + binp->priority = b->priority; return OK; } diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_getname.c b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c index 01ac024f7..9da2bac29 100644 --- a/nuttx/binfmt/libbuiltin/libbuiltin_getname.c +++ b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c @@ -83,10 +83,14 @@ FAR const char *builtin_getname(int index) { - if (index < 0 || index >= number_builtins()) - { - return NULL; - } + struct builtin_s *b; - return g_builtins[index].name; + b = builtin_for_index(index); + + if (b != NULL) + { + return b->name; + } + + return NULL; } diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c index f99a4b81d..b1d55ff21 100644 --- a/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c +++ b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c @@ -80,18 +80,19 @@ * Name: builtin_isavail * * Description: - * Return the index into the table of applications for the applicaiton with + * Return the index into the table of applications for the application with * the name 'appname'. * ****************************************************************************/ int builtin_isavail(FAR const char *appname) { + FAR const char *n; int i; - for (i = 0; g_builtins[i].name; i++) + for (i = 0; n = builtin_getname(i); i++) { - if (!strncmp(g_builtins[i].name, appname, NAME_MAX)) + if (!strncmp(n, appname, NAME_MAX)) { return i; } diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index 8dc5ddcce..c5eadb122 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -116,7 +116,7 @@ CONFIG_MSEC_PER_TICK=10 CONFIG_RR_INTERVAL=0 # CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=32 -# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_HAVE_PARENT=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=6 @@ -148,6 +148,7 @@ CONFIG_DISABLE_POLL=y CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCHLD=4 CONFIG_SIG_SIGCONDTIMEDOUT=16 # diff --git a/nuttx/fs/binfs/fs_binfs.c b/nuttx/fs/binfs/fs_binfs.c index ed6326eba..56ea472af 100644 --- a/nuttx/fs/binfs/fs_binfs.c +++ b/nuttx/fs/binfs/fs_binfs.c @@ -222,7 +222,7 @@ static int binfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } else { - *ptr = g_builtins[(int)filep->f_priv].name; + *ptr = builtin_getname((int)filep->f_priv); ret = OK; } } @@ -287,13 +287,15 @@ static int binfs_opendir(struct inode *mountpt, const char *relpath, static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) { + FAR const char *name; unsigned int index; int ret; /* Have we reached the end of the directory */ index = dir->u.binfs.fb_index; - if (g_builtins[index].name == NULL) + name = builtin_getname(index); + if (name == NULL) { /* We signal the end of the directory by returning the * special error -ENOENT @@ -306,9 +308,9 @@ static int binfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) { /* Save the filename and file type */ - fvdbg("Entry %d: \"%s\"\n", index, g_builtins[index].name); + fvdbg("Entry %d: \"%s\"\n", index, name); dir->fd_dir.d_type = DTYPE_FILE; - strncpy(dir->fd_dir.d_name, g_builtins[index].name, NAME_MAX+1); + strncpy(dir->fd_dir.d_name, name, NAME_MAX+1); /* The application list is terminated by an entry with a NULL name. * Therefore, there is at least one more entry in the list. diff --git a/nuttx/include/nuttx/binfmt/binfmt.h b/nuttx/include/nuttx/binfmt/binfmt.h index c6c7c874a..472ba0fc4 100644 --- a/nuttx/include/nuttx/binfmt/binfmt.h +++ b/nuttx/include/nuttx/binfmt/binfmt.h @@ -82,6 +82,18 @@ typedef FAR void (*binfmt_dtor_t)(void); struct symtab_s; struct binary_s { + /* If CONFIG_SCHED_HAVE_PARENT is defined then schedul_unload() will + * manage instances of struct binary_s allocated with kmalloc. It + * will keep the binary data in a link list and when SIGCHLD is received + * (meaning that the task has exit'ed, schedul_unload() will find the + * data, unload the module, and free the structure. + */ + +#ifdef CONFIG_SCHED_HAVE_PARENT + FAR struct binary_s *flink; /* Supports a singly linked list */ + pid_t pid; /* Task ID of the child task */ +#endif + /* Information provided to the loader to load and bind a module */ FAR const char *filename; /* Full path to the binary to be loaded (See NOTE 1 above) */ @@ -222,19 +234,48 @@ int unload_module(FAR const struct binary_s *bin); * * Returned Value: * This is an end-user function, so it follows the normal convention: - * Returns the PID of the exec'ed module. On failure, it.returns + * Returns the PID of the exec'ed module. On failure, it returns * -1 (ERROR) and sets errno appropriately. * ****************************************************************************/ int exec_module(FAR const struct binary_s *bin); +/**************************************************************************** + * Name: schedule_unload + * + * Description: + * If CONFIG_SCHED_HAVE_PARENT is defined, this function may be called by + * the parent of the the newly created task to automatically unload the + * module when the task exits. This assumes that (1) the caller is the + * parent of the created task, (2) that bin was allocated with kmalloc() + * or friends. It will also automatically free the structure with kfree() + * after unloading the module. + * + * Input Parameter: + * pid - The task ID of the child task + * bin - This structure must have been allocated with kmalloc() and must + * persist until the task unloads + * + * Returned Value: + * This is an end-user function, so it follows the normal convention: + * It returns 0 (OK) if the callback was successfully scheduled. On + * failure, it returns -1 (ERROR) and sets errno appropriately. + * + ****************************************************************************/ + +#ifdef CONFIG_SCHED_HAVE_PARENT +int schedule_unload(pid_t pid, FAR const struct binary_s *bin); +#endif + /**************************************************************************** * Name: exec * * Description: * This is a convenience function that wraps load_ and exec_module into - * one call. + * one call. If CONFIG_SCHED_ONEXIT is also defined, this function will + * automatically call schedule_unload() to unload the module when task + * exits. * * Input Parameter: * filename - Fulll path to the binary to be loaded @@ -244,7 +285,7 @@ int exec_module(FAR const struct binary_s *bin); * * Returned Value: * This is an end-user function, so it follows the normal convention: - * Returns the PID of the exec'ed module. On failure, it.returns + * It returns the PID of the exec'ed module. On failure, it returns * -1 (ERROR) and sets errno appropriately. * ****************************************************************************/ diff --git a/nuttx/include/nuttx/binfmt/builtin.h b/nuttx/include/nuttx/binfmt/builtin.h index 632f8944d..5921cc518 100644 --- a/nuttx/include/nuttx/binfmt/builtin.h +++ b/nuttx/include/nuttx/binfmt/builtin.h @@ -73,14 +73,6 @@ extern "C" { #define EXTERN extern #endif -/* The g_builtins[] array holds information about each builtin function. If - * support for builtin functions is enabled in the NuttX configuration, then - * this arrary (along with the number_builtins() function) must be provided - * by the application code. - */ - -EXTERN const struct builtin_s g_builtins[]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -128,24 +120,24 @@ FAR const char *builtin_getname(int index); * Data Set Access Functions Provided to Applications by binfmt/libbuiltin ****************************************************************************/ /**************************************************************************** - * Name: number_builtins + * Name: builtin_for_index * * Description: - * Returns the number of builtin functions in the g_builtins[] array. If - * support for builtin functions is enabled in the NuttX configuration, - * then this function (along with g_builtins[]) must be provided by the - * application code. + * Returns the builtin_s structure for the selected builtin. + * If support for builtin functions is enabled in the NuttX configuration, + * then this function must be provided by the application code. * * Input Parameter: - * None + * index, from 0 and on... * * Returned Value: - * The number of entries in the g_builtins[] array. This function does - * not return failures. + * Returns valid pointer pointing to the builtin_s structure if index is + * valid. + * Otherwise, NULL is returned. * ****************************************************************************/ -int number_builtins(void); +EXTERN FAR const struct builtin_s *builtin_for_index(int index); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/sched/Kconfig b/nuttx/sched/Kconfig index 6d53a03aa..11d74b583 100644 --- a/nuttx/sched/Kconfig +++ b/nuttx/sched/Kconfig @@ -4,7 +4,7 @@ # config MSEC_PER_TICK - int "tick timer" + int "Milliseconds per system timer tick" default 10 ---help--- The default system timer is 100Hz or MSEC_PER_TICK=10. This setting @@ -12,7 +12,7 @@ config MSEC_PER_TICK system timer interrupts at some interrupt interval other than 10 msec. config RR_INTERVAL - int "round robin timeslice" + int "Round robin timeslice (MSEC)" default 0 ---help--- The round robin timeslice will be set this number of milliseconds; @@ -39,7 +39,7 @@ config TASK_NAME_SIZE disable. config SCHED_HAVE_PARENT - bool "Remember Parent" + bool "Support parent/child task relationships" default n ---help--- Remember the ID of the parent thread when a new child thread is @@ -56,15 +56,15 @@ config JULIAN_TIME Enables Julian time conversions config START_YEAR - int "start year" + int "Start year" default 2013 config START_MONTH - int "start month" + int "Start month" default 1 config START_DAY - int "start day" + int "Start day" default 1 config DEV_CONSOLE @@ -372,7 +372,7 @@ endif comment "Sizes of configurable things (0 disables)" config MAX_TASKS - int "Max tasks" + int "Max number of tasks" default 32 ---help--- The maximum number of simultaneously active tasks. This value must be @@ -386,33 +386,32 @@ config MAX_TASK_ARGS receive (i.e., maxmum value of 'argc') config NPTHREAD_KEYS - int "Number of pthread keys" + int "Maximum number of pthread keys" default 4 ---help--- The number of items of thread- specific data that can be retained config NFILE_DESCRIPTORS - int "Max file descriptors" + int "Maximum number of file descriptors per task" default 16 ---help--- - The maximum number of file - descriptors (one for each open) + The maximum number of file descriptors per task (one for each open) config NFILE_STREAMS - int "Max file streams" + int "Maximum number of FILE streams" default 16 ---help--- The maximum number of streams that can be fopen'ed config NAME_MAX - int "name max" + int "Maximum size of a file name" default 32 ---help--- The maximum size of a file name. config PREALLOC_MQ_MSGS - int "Pre-allocated messages" + int "Number of pre-allocated messages" default 32 ---help--- The number of pre-allocated message structures. The system manages @@ -426,21 +425,20 @@ config MQ_MAXMSGSIZE setting (does not include other message structure overhead. config MAX_WDOGPARMS - int "max watchdog parms" + int "Maximum number of watchdog parameters" default 4 ---help--- - Maximum number of parameters that - can be passed to a watchdog handler + Maximum number of parameters that can be passed to a watchdog handler config PREALLOC_WDOGS - int "Pre-allocated watchdogs" + int "Number of pre-allocated watchdog timers" default 32 ---help--- The number of pre-allocated watchdog structures. The system manages a pool of preallocated watchdog structures to minimize dynamic allocations config PREALLOC_TIMERS - int "Pre-allocated timers" + int "Number of pre-allocated POSIX timers" default 8 ---help--- The number of pre-allocated POSIX timer structures. The system manages a diff --git a/nuttx/tools/Makefile.export b/nuttx/tools/Makefile.export index 002cb526b..6dfe72bf9 100644 --- a/nuttx/tools/Makefile.export +++ b/nuttx/tools/Makefile.export @@ -37,14 +37,18 @@ include $(TOPDIR)/.config include $(EXPORTDIR)/Make.defs ifdef ARCHSCRIPT +# +# ARCHSCRIPT may contain a leading -T; it must not be followed by a space +# for this to work. +# ifeq ($(WINTOOL),y) -LDPATH = ${shell cygpath -u $(patsubst -T,,$(ARCHSCRIPT))} +LDPATH = $(shell cygpath -u $(patsubst -T%,%,$(ARCHSCRIPT))) else -LDPATH = $(patsubst -T,,$(ARCHSCRIPT)) +LDPATH = $(patsubst -T%,%,$(ARCHSCRIPT)) endif -LDNAME = ${shell basename ${LDPATH}} -LDDIR = ${shell dirname ${LDPATH}} +LDNAME = ${notdir ${LDPATH}} +LDDIR = ${dir ${LDPATH}} endif ARCHSUBDIR = "arch/$(CONFIG_ARCH)/src" -- cgit v1.2.3 From 19e43efe230a2b8720d98cba5a6ad156942e291f Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 17 Jan 2013 18:32:13 +0000 Subject: NSH will now run files from the file system; Add logic to unload and clean-up after running a task from a file system; Extensions to builtin apps from Mike Smith git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5529 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 3 + apps/builtin/builtin_list.c | 79 +++++++ apps/examples/nsh/nsh_main.c | 38 +++ apps/nshlib/Kconfig | 11 +- apps/nshlib/Makefile | 4 + apps/nshlib/nsh.h | 5 + apps/nshlib/nsh_builtin.c | 27 ++- apps/nshlib/nsh_fileapps.c | 298 ++++++++++++++++++++++++ apps/nshlib/nsh_parse.c | 37 ++- nuttx/ChangeLog | 4 + nuttx/arch/arm/include/stm32/chip.h | 38 ++- nuttx/binfmt/binfmt_exec.c | 10 +- nuttx/binfmt/binfmt_loadmodule.c | 4 +- nuttx/binfmt/binfmt_schedunload.c | 333 +++++++++++++++++++++++++++ nuttx/binfmt/builtin.c | 4 +- nuttx/binfmt/libbuiltin/libbuiltin_getname.c | 8 +- nuttx/binfmt/libbuiltin/libbuiltin_isavail.c | 6 +- nuttx/configs/sim/nsh/defconfig | 12 +- nuttx/include/nuttx/binfmt/binfmt.h | 2 +- nuttx/include/nuttx/binfmt/builtin.h | 30 +++ nuttx/libc/spawn/lib_ps.c | 2 +- nuttx/tools/mkconfig.c | 2 +- 22 files changed, 927 insertions(+), 30 deletions(-) create mode 100644 apps/builtin/builtin_list.c create mode 100644 apps/nshlib/nsh_fileapps.c create mode 100644 nuttx/binfmt/binfmt_schedunload.c diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index 14eb78950..ba8dec613 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -485,3 +485,6 @@ argument is now optional. Many files systems do not need a source and it is really stupid to have to enter a bogus source parameter. + * apps/nshlib/nsh_fileapp.c: Add the ability to execute a file + from a file system using posix_spawn(). + * apps/builtin/: Extensions from Mike Smith. diff --git a/apps/builtin/builtin_list.c b/apps/builtin/builtin_list.c new file mode 100644 index 000000000..a5556bf54 --- /dev/null +++ b/apps/builtin/builtin_list.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * apps/builtin/builtin_list.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#include "builtin_proto.h" + +const struct builtin_s g_builtins[] = +{ +# include "builtin_list.h" + { NULL, 0, 0, 0 } +}; + +const int g_builtin_count = sizeof(g_builtins) / sizeof(g_builtins[0]); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + diff --git a/apps/examples/nsh/nsh_main.c b/apps/examples/nsh/nsh_main.c index 97792cb2a..d9bfc2018 100644 --- a/apps/examples/nsh/nsh_main.c +++ b/apps/examples/nsh/nsh_main.c @@ -46,6 +46,12 @@ #include #include +#if defined(CONFIG_FS_BINFS) && (CONFIG_BUILTIN) +#include +#endif +#if defined(CONFIG_LIBC_EXECFUNCS) && defined(CONFIG_EXECFUNCS_SYMTAB) +#include +#endif #include @@ -75,6 +81,21 @@ * Public Data ****************************************************************************/ +/* If posix_spawn() is enabled as required for CONFIG_NSH_FILE_APPS, then + * a symbol table is needed by the internals of posix_spawn(). The symbol + * table is needed to support ELF and NXFLAT binaries to dynamically link to + * the base code. However, if only the BINFS file system is supported, then + * no Makefile is needed. + * + * This is a kludge to plug the missing file system in the case where BINFS + * is used. REVISIT: This will, of course, be in the way if you want to + * support ELF or NXFLAT binaries! + */ + +#if defined(CONFIG_LIBC_EXECFUNCS) && defined(CONFIG_EXECFUNCS_SYMTAB) +const struct symtab_s CONFIG_EXECFUNCS_SYMTAB[1]; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -98,6 +119,23 @@ int nsh_main(int argc, char *argv[]) up_cxxinitialize(); #endif + /* Make sure that we are using our symbol take */ + +#if defined(CONFIG_LIBC_EXECFUNCS) && defined(CONFIG_EXECFUNCS_SYMTAB) + exec_setsymtab(CONFIG_EXECFUNCS_SYMTAB, 0); +#endif + + /* Register the BINFS file system */ + +#if defined(CONFIG_FS_BINFS) && (CONFIG_BUILTIN) + ret = builtin_initialize(); + if (ret < 0) + { + fprintf(stderr, "ERROR: builtin_initialize failed: %d\n", ret); + exitval = 1; + } +#endif + /* Initialize the NSH library */ nsh_initialize(); diff --git a/apps/nshlib/Kconfig b/apps/nshlib/Kconfig index e60e9c480..f6a5aa045 100644 --- a/apps/nshlib/Kconfig +++ b/apps/nshlib/Kconfig @@ -14,7 +14,7 @@ config NSH_LIBRARY if NSH_LIBRARY config NSH_BUILTIN_APPS bool "Enable built-in applications" - default y + default n depends on BUILTIN ---help--- Support external registered, "built-in" applications that can be @@ -22,6 +22,15 @@ config NSH_BUILTIN_APPS more information). This options requires support for builtin applications (BUILTIN). +config NSH_FILE_APPS + bool "Enable execution of program files" + default n + depends on LIBC_EXECFUNCS + ---help--- + Support execution of program files residing within a file + system. This options requires support for the posix_spawn() + interface (LIBC_EXECFUNCS). + menu "Disable Individual commands" config NSH_DISABLE_BASE64DEC diff --git a/apps/nshlib/Makefile b/apps/nshlib/Makefile index 5c5269685..948f43d52 100644 --- a/apps/nshlib/Makefile +++ b/apps/nshlib/Makefile @@ -47,6 +47,10 @@ ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) CSRCS += nsh_builtin.c endif +ifeq ($(CONFIG_NSH_FILE_APPS),y) +CSRCS += nsh_fileapps.c +endif + ifeq ($(CONFIG_NSH_ROMFSETC),y) CSRCS += nsh_romfsetc.c endif diff --git a/apps/nshlib/nsh.h b/apps/nshlib/nsh.h index 253a803f8..64099a8df 100644 --- a/apps/nshlib/nsh.h +++ b/apps/nshlib/nsh.h @@ -495,6 +495,11 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, FAR char **argv, FAR const char *redirfile, int oflags); #endif +#ifdef CONFIG_NSH_FILE_APPS +int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, + FAR char **argv, FAR const char *redirfile, int oflags); +#endif + /* Working directory support */ #if CONFIG_NFILE_DESCRIPTORS > 0 && !defined(CONFIG_DISABLE_ENVIRON) diff --git a/apps/nshlib/nsh_builtin.c b/apps/nshlib/nsh_builtin.c index ba39e8dfe..2d23ca8d8 100644 --- a/apps/nshlib/nsh_builtin.c +++ b/apps/nshlib/nsh_builtin.c @@ -51,6 +51,7 @@ #endif #include +#include #include #include @@ -129,20 +130,34 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, ret = exec_builtin(cmd, (FAR const char **)argv, redirfile, oflags); if (ret >= 0) { - /* The application was successfully started (but still blocked because - * the scheduler is locked). If the application was not backgrounded, - * then we need to wait here for the application to exit. These really - * only works works with the following options: + /* The application was successfully started with pre-emption disabled. + * In the simplest cases, the application will not have run because the + * the scheduler is locked. but in the case were I/O redirected, a + * proxy task ran and, as result, so may have the application. + * + * If the application did not run and if the application was not + * backgrounded, then we need to wait here for the application to + * exit. This only works works with the following options: * * - CONFIG_NSH_DISABLEBG - Do not run commands in background * - CONFIG_SCHED_WAITPID - Required to run external commands in * foreground - * - * These concepts do not apply cleanly to the external applications. */ #ifdef CONFIG_SCHED_WAITPID + /* Check if the application is still running */ + + if (kill(ret, 0) < 0) + { + /* It is not running. In this case, we have no idea if the + * application ran successfully or not. Let's assume that is + * did. + */ + + return 0; + } + /* CONFIG_SCHED_WAITPID is selected, so we may run the command in * foreground unless we were specifically requested to run the command * in background (and running commands in background is enabled). diff --git a/apps/nshlib/nsh_fileapps.c b/apps/nshlib/nsh_fileapps.c new file mode 100644 index 000000000..7f9f58e53 --- /dev/null +++ b/apps/nshlib/nsh_fileapps.c @@ -0,0 +1,298 @@ +/**************************************************************************** + * apps/nshlib/nsh_fileapps.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_SCHED_WAITPID +# include +#endif + +#include +#include +#include +#include +#include + +#include "nsh.h" +#include "nsh_console.h" + +#ifdef CONFIG_NSH_FILE_APPS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_fileapp + * + * Description: + * Attempt to execute the application task whose name is 'cmd' + * + * Returned Value: + * <0 If exec_builtin() fails, then the negated errno value + * is returned. + * -1 (ERROR) if the application task corresponding to 'cmd' could not + * be started (possibly because it doesn not exist). + * 0 (OK) if the application task corresponding to 'cmd' was + * and successfully started. If CONFIG_SCHED_WAITPID is + * defined, this return value also indicates that the + * application returned successful status (EXIT_SUCCESS) + * 1 If CONFIG_SCHED_WAITPID is defined, then this return value + * indicates that the application task was spawned successfully + * but returned failure exit status. + * + ****************************************************************************/ + +int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, + FAR char **argv, FAR const char *redirfile, int oflags) +{ + posix_spawn_file_actions_t file_actions; + posix_spawnattr_t attr; + pid_t pid; + int ret; + + /* Initialize the attributes file actions structure */ + + ret = posix_spawn_file_actions_init(&file_actions); + if (ret != 0) + { + /* posix_spawn_file_actions_init returns a positive errno value on + * failure. + */ + + nsh_output(vtbl, g_fmtcmdfailed, cmd, "posix_spawn_file_actions_init", + NSH_ERRNO_OF(ret)); + goto errout; + } + + ret = posix_spawnattr_init(&attr); + if (ret != 0) + { + /* posix_spawnattr_init returns a positive errno value on failure. */ + + nsh_output(vtbl, g_fmtcmdfailed, cmd, "posix_spawnattr_init", + NSH_ERRNO); + goto errout_with_actions; + } + + /* Handle re-direction of output */ + + if (redirfile) + { + ret = posix_spawn_file_actions_addopen(&file_actions, 1, redirfile, + oflags, 0644); + if (ret != 0) + { + /* posix_spawn_file_actions_addopen returns a positive errno + * value on failure. + */ + + nsh_output(vtbl, g_fmtcmdfailed, cmd, + "posix_spawn_file_actions_addopen", + NSH_ERRNO); + goto errout_with_attrs; + } + } + + /* Lock the scheduler to prevent the application from running until the + * waitpid() has been called. + */ + + sched_lock(); + + /* Execute the program. posix_spawnp returns a positive errno value on + * failure. + */ + + ret = posix_spawnp(&pid, cmd, &file_actions, &attr, &argv[1], NULL); + if (ret == OK) + { + /* The application was successfully started with pre-emption disabled. + * In the simplest cases, the application will not have run because the + * the scheduler is locked. but in the case were I/O redirected, a + * proxy task ran and, as result, so may have the application. + * + * If the application did not run and if the application was not + * backgrounded, then we need to wait here for the application to + * exit. This only works works with the following options: + * + * - CONFIG_NSH_DISABLEBG - Do not run commands in background + * - CONFIG_SCHED_WAITPID - Required to run external commands in + * foreground + */ + +#ifdef CONFIG_SCHED_WAITPID + /* Check if the application is still running */ + + if (kill(ret, 0) < 0) + { + /* It is not running. In this case, we have no idea if the + * application ran successfully or not. Let's assume that is + * did. + */ + + return 0; + } + + /* CONFIG_SCHED_WAITPID is selected, so we may run the command in + * foreground unless we were specifically requested to run the command + * in background (and running commands in background is enabled). + */ + +# ifndef CONFIG_NSH_DISABLEBG + if (vtbl->np.np_bg == false) +# endif /* CONFIG_NSH_DISABLEBG */ + { + int rc = 0; + + /* Wait for the application to exit. Since we have locked the + * scheduler above, we know that the application has not yet + * started and there is no possibility that it has already exited. + * The scheduler will be unlocked while waitpid is waiting and the + * application will be able to run. + */ + + ret = waitpid(pid, &rc, 0); + if (ret >= 0) + { + /* We can't return the exact status (nsh has nowhere to put it) + * so just pass back zero/nonzero in a fashion that doesn't look + * like an error. + */ + + ret = (rc == 0) ? OK : 1; + + /* TODO: Set the environment variable '?' to a string corresponding + * to WEXITSTATUS(rc) so that $? will expand to the exit status of + * the most recently executed task. + */ + } + } +# ifndef CONFIG_NSH_DISABLEBG + else +# endif /* CONFIG_NSH_DISABLEBG */ +#endif /* CONFIG_SCHED_WAITPID */ + + /* We get here if either: + * + * - CONFIG_SCHED_WAITPID is not selected meaning that all commands + * have to be run in background, or + * - CONFIG_SCHED_WAITPID and CONFIG_NSH_DISABLEBG are both selected, but the + * user requested to run the command in background. + * + * NOTE that the case of a) CONFIG_SCHED_WAITPID is not selected and + * b) CONFIG_NSH_DISABLEBG selected cannot be supported. In that event, all + * commands will have to run in background. The waitpid() API must be + * available to support running the command in foreground. + */ + +#if !defined(CONFIG_SCHED_WAITPID) || !defined(CONFIG_NSH_DISABLEBG) + { + struct sched_param param; + sched_getparam(ret, ¶m); + nsh_output(vtbl, "%s [%d:%d]\n", cmd, ret, param.sched_priority); + + /* Backgrounded commands always 'succeed' as long as we can start + * them. + */ + + ret = OK; + } +#endif /* !CONFIG_SCHED_WAITPID || !CONFIG_NSH_DISABLEBG */ + } + + sched_unlock(); + + /* Free attibutes and file actions. Ignoring return values in the case + * of an error. + */ + +errout_with_actions: + (void)posix_spawn_file_actions_destroy(&file_actions); + +errout_with_attrs: + (void)posix_spawnattr_destroy(&attr); + +errout: + /* Most posix_spawn interfaces return a positive errno value on failure + * and do not set the errno variable. + */ + + if (ret > 0) + { + /* Set the errno value and return -1 */ + + set_errno(ret); + ret = ERROR; + } + else if (ret < 0) + { + /* Return -1 on failure. errno should have been set. */ + + ret = ERROR; + } + + return ret; +} + +#endif /* CONFIG_NSH_FILE_APPS */ diff --git a/apps/nshlib/nsh_parse.c b/apps/nshlib/nsh_parse.c index ef4125a63..f679d9b32 100644 --- a/apps/nshlib/nsh_parse.c +++ b/apps/nshlib/nsh_parse.c @@ -61,6 +61,7 @@ #ifdef CONFIG_NSH_BUILTIN_APPS # include #endif + #include #include "nsh.h" @@ -1398,6 +1399,40 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) nsh_output(vtbl, g_fmttoomanyargs, cmd); } + /* Does this command correspond to an application filename? + * nsh_fileapp() returns: + * + * -1 (ERROR) if the application task corresponding to 'argv[0]' could not + * be started (possibly because it doesn not exist). + * 0 (OK) if the application task corresponding to 'argv[0]' was + * and successfully started. If CONFIG_SCHED_WAITPID is + * defined, this return value also indicates that the + * application returned successful status (EXIT_SUCCESS) + * 1 If CONFIG_SCHED_WAITPID is defined, then this return value + * indicates that the application task was spawned successfully + * but returned failure exit status. + * + * Note the priority if not effected by nice-ness. + */ + +#ifdef CONFIG_NSH_FILE_APPS + ret = nsh_fileapp(vtbl, argv[0], argv, redirfile, oflags); + if (ret >= 0) + { + /* nsh_fileapp() returned 0 or 1. This means that the builtin + * command was successfully started (although it may not have ran + * successfully). So certainly it is not an NSH command. + */ + + return nsh_saveresult(vtbl, ret != OK); + } + + /* No, not a built in command (or, at least, we were unable to start a + * builtin command of that name). Treat it like an NSH command. + */ + +#endif + /* Does this command correspond to a builtin command? * nsh_builtin() returns: * @@ -1414,7 +1449,7 @@ int nsh_parse(FAR struct nsh_vtbl_s *vtbl, char *cmdline) * Note the priority if not effected by nice-ness. */ -#ifdef CONFIG_NSH_BUILTIN_APPS +#if defined(CONFIG_NSH_BUILTIN_APPS) && (!defined(CONFIG_NSH_FILE_APPS) || !defined(CONFIG_FS_BINFS)) ret = nsh_builtin(vtbl, argv[0], argv, redirfile, oflags); if (ret >= 0) { diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 6bc66ec9d..1b0c5338b 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3967,4 +3967,8 @@ file system. * configs/sim/nsh: Convert to use kconfig-frontends configuration tool. + * binfmt/binfmt_schedunload.c: Add logic based on SIGCHLD to + automatically unload and clean-up after running a task that + was loaded into memory. + * binfmt/libbuiltin: Extensions from Mike Smith diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index d34c2eb4f..b7ec7dbba 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -183,9 +183,43 @@ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +/* STM32 F103 Medium Density Family *************************************************/ +/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin + * packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6) +# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2,3,4 */ +# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + /* STM32 F103 High Density Family ***************************************************/ -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ - * only in the available FLASH and SRAM. +/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and + * differ only in the available FLASH and SRAM. */ #elif defined(CONFIG_ARCH_CHIP_STM32F103RET6) diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c index 1cead4384..7f45fb841 100644 --- a/nuttx/binfmt/binfmt_exec.c +++ b/nuttx/binfmt/binfmt_exec.c @@ -43,6 +43,7 @@ #include #include +#include #include #include "binfmt_internal.h" @@ -97,6 +98,7 @@ int exec(FAR const char *filename, FAR const char **argv, #ifdef CONFIG_SCHED_ONEXIT FAR struct binary_s *bin; int errorcode; + int pid; int ret; /* Allocate the load information */ @@ -131,8 +133,8 @@ int exec(FAR const char *filename, FAR const char **argv, /* Then start the module */ - ret = exec_module(bin); - if (ret < 0) + pid = exec_module(bin); + if (pid < 0) { bdbg("ERROR: Failed to execute program '%s'\n", filename); sched_unlock(); @@ -145,14 +147,14 @@ int exec(FAR const char *filename, FAR const char **argv, * when the task exists. */ - ret = schedul_unload(ret, bin); + ret = schedule_unload(pid, bin); if (ret < 0) { bdbg("ERROR: Failed to schedul unload '%s'\n", filename); } sched_unlock(); - return ret; + return pid; #else struct binary_s bin; int ret; diff --git a/nuttx/binfmt/binfmt_loadmodule.c b/nuttx/binfmt/binfmt_loadmodule.c index 4f3dc6952..322ed2c48 100644 --- a/nuttx/binfmt/binfmt_loadmodule.c +++ b/nuttx/binfmt/binfmt_loadmodule.c @@ -84,6 +84,7 @@ static int load_default_priority(FAR struct binary_s *bin) { struct sched_param param; + int ret; /* Get the priority of this thread */ @@ -97,6 +98,7 @@ static int load_default_priority(FAR struct binary_s *bin) /* Save that as the priority of child thread */ bin->priority = param.sched_priority; + return ret; } /**************************************************************************** @@ -180,7 +182,7 @@ int load_module(FAR struct binary_s *bin) { /* Set the default priority of the new program. */ - ret = load_default_priority(bin) + ret = load_default_priority(bin); if (ret < 0) { /* The errno is already set in this case */ diff --git a/nuttx/binfmt/binfmt_schedunload.c b/nuttx/binfmt/binfmt_schedunload.c new file mode 100644 index 000000000..972d17963 --- /dev/null +++ b/nuttx/binfmt/binfmt_schedunload.c @@ -0,0 +1,333 @@ +/**************************************************************************** + * binfmt/binfmt_schedunload.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "binfmt_internal.h" + +#if !defined(CONFIG_BINFMT_DISABLE) && defined(CONFIG_SCHED_HAVE_PARENT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +FAR struct binary_s *g_unloadhead; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: unload_list_add + * + * Description: + * If CONFIG_SCHED_HAVE_PARENT is defined then schedul_unload() will + * manage instances of struct binary_s allocated with kmalloc. It + * will keep the binary data in a link list and when SIGCHLD is received + * (meaning that the task has exit'ed, schedul_unload() will find the + * data, unload the module, and free the structure. + * + * This function will add one structure to the linked list + * + * Input Parameter: + * pid - The task ID of the child task + * bin - This structure must have been allocated with kmalloc() and must + * persist until the task unloads + + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void unload_list_add(pid_t pid, FAR struct binary_s *bin) +{ + irqstate_t flags; + + /* Save the PID in the structure so that we recover it later */ + + bin->pid = pid; + + /* Disable deliver of any signals while we muck with the list. The graceful + * way to do this would be block delivery of SIGCHLD would be with + * sigprocmask. Here we do it the quick'n'dirty way by just disabling + * interrupts. + */ + + flags = irqsave(); + bin->flink = g_unloadhead; + g_unloadhead = bin; + irqrestore(flags); +} + +/**************************************************************************** + * Name: unload_list_remove + * + * Description: + * If CONFIG_SCHED_HAVE_PARENT is defined then schedul_unload() will + * manage instances of struct binary_s allocated with kmalloc. It + * will keep the binary data in a link list and when SIGCHLD is received + * (meaning that the task has exit'ed, schedul_unload() will find the + * data, unload the module, and free the structure. + * + * This function will remove one structure to the linked list + * + * Input Parameter: + * pid - The task ID of the child task + * + * Returned Value: + * On success, the load structure is returned. NULL is returned on + * failure. + * + ****************************************************************************/ + +static FAR struct binary_s *unload_list_remove(pid_t pid) +{ + FAR struct binary_s *curr; + FAR struct binary_s *prev; + + /* Note the asymmetry. We do not have to disable interrupts here because + * the main thread cannot run while we are in the interrupt handler. Here, + * it should be sufficient to disable pre-emption so that no other thread + * can run. + */ + + sched_lock(); + + /* Find the structure in the unload list with the matching PID */ + + for (prev = NULL, curr = g_unloadhead; + curr && (curr->pid != pid); + prev = curr, curr = curr->flink); + + /* Did we find it? It must be there. Hmmm.. we should probably ASSERT if + * we do not! + */ + + if (curr) + { + /* Was there another entry before this one? */ + + if (prev) + { + /* Yes.. remove the current entry from after the previous entry */ + + prev->flink = curr->flink; + } + else + { + /* No.. remove the current entry from the head of the list */ + + g_unloadhead = curr->flink; + } + + /* Nullify the forward link ... superstitious */ + + curr->flink = NULL; + } + + sched_unlock(); + return curr; +} + +/**************************************************************************** + * Name: unload_callback + * + * Description: + * If CONFIG_SCHED_HAVE_PARENT is defined, this function may be called to + * automatically unload the module when task exits. It assumes that + * bin was allocated with kmalloc() or friends and will also automatically + * free the structure with kfree() when the task exists. + * + * Input Parameter: + * pid - The ID of the task that just exited + * arg - A reference to the load structure cast to FAR void * + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void unload_callback(int signo, siginfo_t *info, void *ucontext) +{ + FAR struct binary_s *bin; + int ret; + + /* Sanity checking */ + + if (!info || signo != SIGCHLD) + { + blldbg("ERROR:Bad signal callback: signo=%d info=%p\n", signo, callback); + return; + } + + /* Get the load information for this pid */ + + bin = unload_list_remove(info->si_pid); + if (!bin) + { + blldbg("ERROR: Could not find load info for PID=%d\n", info->si_pid); + return; + } + + /* Unload the module */ + + ret = unload_module(bin); + if (ret < 0) + { + blldbg("ERROR: unload_module failed: %d\n", get_errno()); + } + + /* Free the load structure */ + + kfree(bin); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: schedule_unload + * + * Description: + * If CONFIG_SCHED_HAVE_PARENT is defined, this function may be called by + * the parent of the the newly created task to automatically unload the + * module when the task exits. This assumes that (1) the caller is the + * parent of the created task, (2) that bin was allocated with kmalloc() + * or friends. It will also automatically free the structure with kfree() + * after unloading the module. + * + * Input Parameter: + * pid - The task ID of the child task + * bin - This structure must have been allocated with kmalloc() and must + * persist until the task unloads + * + * Returned Value: + * This is an end-user function, so it follows the normal convention: + * It returns 0 (OK) if the callback was successfully scheduled. On + * failure, it returns -1 (ERROR) and sets errno appropriately. + * + * On failures, the 'bin' structure will not be deallocated and the + * module not not be unloaded. + * + ****************************************************************************/ + +int schedule_unload(pid_t pid, FAR struct binary_s *bin) +{ + struct sigaction act; + struct sigaction oact; + sigset_t sigset; + irqstate_t flags; + int errorcode; + int ret; + + /* Make sure that SIGCHLD is unmasked */ + + (void)sigemptyset(&sigset); + (void)sigaddset(&sigset, SIGCHLD); + ret = sigprocmask(SIG_UNBLOCK, &sigset, NULL); + if (ret != OK) + { + /* The errno value will get trashed by the following debug output */ + + errorcode = get_errno(); + bvdbg("ERROR: sigprocmask failed: %d\n", ret); + goto errout; + } + + /* Add the structure to the list. We want to do this *before* connecting + * the signal handler. This does, however, make error recovery more + * complex if sigaction() fails below because then we have to remove the + * unload structure for the list in an unexpected context. + */ + + unload_list_add(pid, bin); + + /* Register the SIGCHLD handler */ + + act.sa_sigaction = unload_callback; + act.sa_flags = SA_SIGINFO; + + (void)sigfillset(&act.sa_mask); + (void)sigdelset(&act.sa_mask, SIGCHLD); + + ret = sigaction(SIGCHLD, &act, &oact); + if (ret != OK) + { + /* The errno value will get trashed by the following debug output */ + + errorcode = get_errno(); + bvdbg("ERROR: sigaction failed: %d\n" , ret); + + /* Emergency removal from the list */ + + flags = irqsave(); + if (unload_list_remove(pid) != bin) + { + blldbg("ERROR: Failed to remove structure\n"); + } + + goto errout; + } + + return OK; + +errout: + set_errno(errorcode); + return ERROR; +} + +#endif /* !CONFIG_BINFMT_DISABLE && CONFIG_SCHED_HAVE_PARENT */ + diff --git a/nuttx/binfmt/builtin.c b/nuttx/binfmt/builtin.c index d80d9f5d8..e492f72e5 100644 --- a/nuttx/binfmt/builtin.c +++ b/nuttx/binfmt/builtin.c @@ -98,11 +98,11 @@ static int builtin_loadbinary(struct binary_s *binp) /* Open the binary file for reading (only) */ - fd = open(filename, O_RDONLY); + fd = open(binp->filename, O_RDONLY); if (fd < 0) { int errval = errno; - bdbg("ERROR: Failed to open binary %s: %d\n", filename, errval); + bdbg("ERROR: Failed to open binary %s: %d\n", binp->filename, errval); return -errval; } diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_getname.c b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c index 9da2bac29..d1e3958b3 100644 --- a/nuttx/binfmt/libbuiltin/libbuiltin_getname.c +++ b/nuttx/binfmt/libbuiltin/libbuiltin_getname.c @@ -83,13 +83,13 @@ FAR const char *builtin_getname(int index) { - struct builtin_s *b; + FAR const struct builtin_s *builtin; - b = builtin_for_index(index); + builtin = builtin_for_index(index); - if (b != NULL) + if (builtin != NULL) { - return b->name; + return builtin->name; } return NULL; diff --git a/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c index b1d55ff21..7a480c0f3 100644 --- a/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c +++ b/nuttx/binfmt/libbuiltin/libbuiltin_isavail.c @@ -87,12 +87,12 @@ int builtin_isavail(FAR const char *appname) { - FAR const char *n; + FAR const char *name; int i; - for (i = 0; n = builtin_getname(i); i++) + for (i = 0; (name = builtin_getname(i)); i++) { - if (!strncmp(n, appname, NAME_MAX)) + if (!strncmp(name, appname, NAME_MAX)) { return i; } diff --git a/nuttx/configs/sim/nsh/defconfig b/nuttx/configs/sim/nsh/defconfig index c5eadb122..7b72ac303 100644 --- a/nuttx/configs/sim/nsh/defconfig +++ b/nuttx/configs/sim/nsh/defconfig @@ -130,7 +130,8 @@ CONFIG_SDCLONE_DISABLE=y # CONFIG_SCHED_WORKQUEUE is not set CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_ONEXIT_MAX=1 CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_DISABLE_OS_API=y # CONFIG_DISABLE_CLOCK is not set @@ -259,7 +260,8 @@ CONFIG_MM_REGIONS=1 # Binary Formats # # CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set +CONFIG_BINFMT_EXEPATH=y +CONFIG_PATH_INITIAL="/bin" # CONFIG_NXFLAT is not set # CONFIG_ELF is not set CONFIG_BUILTIN=y @@ -284,7 +286,10 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_EOL_IS_LF is not set # CONFIG_EOL_IS_BOTH_CRLF is not set CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_LIBC_EXECFUNCS=y +CONFIG_EXECFUNCS_SYMTAB="g_symtab" +CONFIG_EXECFUNCS_NSYMBOLS=0 +CONFIG_POSIX_SPAWN_STACKSIZE=1024 # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y @@ -410,6 +415,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_NSH_LIBRARY=y CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILE_APPS=y # # Disable Individual commands diff --git a/nuttx/include/nuttx/binfmt/binfmt.h b/nuttx/include/nuttx/binfmt/binfmt.h index 472ba0fc4..590d88402 100644 --- a/nuttx/include/nuttx/binfmt/binfmt.h +++ b/nuttx/include/nuttx/binfmt/binfmt.h @@ -265,7 +265,7 @@ int exec_module(FAR const struct binary_s *bin); ****************************************************************************/ #ifdef CONFIG_SCHED_HAVE_PARENT -int schedule_unload(pid_t pid, FAR const struct binary_s *bin); +int schedule_unload(pid_t pid, FAR struct binary_s *bin); #endif /**************************************************************************** diff --git a/nuttx/include/nuttx/binfmt/builtin.h b/nuttx/include/nuttx/binfmt/builtin.h index 5921cc518..6ff565395 100644 --- a/nuttx/include/nuttx/binfmt/builtin.h +++ b/nuttx/include/nuttx/binfmt/builtin.h @@ -77,6 +77,36 @@ extern "C" { * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: builtin_initialize + * + * Description: + * Builtin support is built unconditionally. However, it order to + * use this binary format, this function must be called during system + * format in order to register the builtin binary format. + * + * Returned Value: + * This is a NuttX internal function so it follows the convention that + * 0 (OK) is returned on success and a negated errno is returned on + * failure. + * + ****************************************************************************/ + +int builtin_initialize(void); + +/**************************************************************************** + * Name: builtin_uninitialize + * + * Description: + * Unregister the builtin binary loader + * + * Returned Value: + * None + * + ****************************************************************************/ + +void builtin_uninitialize(void); + /**************************************************************************** * Utility Functions Provided to Applications by binfmt/libbuiltin ****************************************************************************/ diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index 638b27f87..000f711a3 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -247,7 +247,7 @@ static int ps_exec(FAR pid_t *pidp, FAR const char *path, errout: sched_unlock(); - return OK; + return ret; } /**************************************************************************** diff --git a/nuttx/tools/mkconfig.c b/nuttx/tools/mkconfig.c index fe3e00491..d8d09df34 100644 --- a/nuttx/tools/mkconfig.c +++ b/nuttx/tools/mkconfig.c @@ -116,7 +116,7 @@ int main(int argc, char **argv, char **envp) printf(" * configured (at present, NXFLAT is the only supported binary.\n"); printf(" * format).\n"); printf(" */\n\n"); - printf("#if !defined(CONFIG_NXFLAT) && !defined(CONFIG_ELF)\n"); + printf("#if !defined(CONFIG_NXFLAT) && !defined(CONFIG_ELF) && !defined(CONFIG_BUILTIN)\n"); printf("# undef CONFIG_BINFMT_DISABLE\n"); printf("# define CONFIG_BINFMT_DISABLE 1\n"); printf("#endif\n\n"); -- cgit v1.2.3 From 2f653578c632ec95e94f67306af24c7d82700d28 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 17 Jan 2013 20:25:32 +0000 Subject: Misc bug fixes related to NSH file execution git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5530 42af7a65-404d-4744-a932-0658087f49c3 --- apps/builtin/exec_builtin.c | 16 +++++++++++++ apps/nshlib/nsh_builtin.c | 54 +++++++++++++++++++++++++++----------------- apps/nshlib/nsh_fileapps.c | 53 +++++++++++++++++++++++++++---------------- nuttx/configs/sim/README.txt | 33 ++++++++++++++++++++------- nuttx/libc/spawn/lib_ps.c | 16 +++++++++++++ 5 files changed, 123 insertions(+), 49 deletions(-) diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index d4431164c..803d1ef34 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -46,6 +46,7 @@ #include +#include #include #include #include @@ -92,7 +93,9 @@ struct builtin_parms_s ****************************************************************************/ static sem_t g_builtin_parmsem = SEM_INITIALIZER(1); +#ifndef CONFIG_SCHED_WAITPID static sem_t g_builtin_execsem = SEM_INITIALIZER(0); +#endif static struct builtin_parms_s g_builtin_parms; /**************************************************************************** @@ -274,7 +277,9 @@ static int builtin_proxy(int argc, char *argv[]) */ g_builtin_parms.result = ret; +#ifndef CONFIG_SCHED_WAITPID builtin_semgive(&g_builtin_execsem); +#endif return 0; } @@ -299,6 +304,9 @@ static inline int builtin_startproxy(int index, FAR const char **argv, struct sched_param param; pid_t proxy; int errcode; +#ifdef CONFIG_SCHED_WAITPID + int status; +#endif int ret; svdbg("index=%d argv=%p redirfile=%s oflags=%04x\n", @@ -353,7 +361,15 @@ static inline int builtin_startproxy(int index, FAR const char **argv, * for this. */ +#ifdef CONFIG_SCHED_WAITPID + ret = waitpid(proxy, &status, 0); + if (ret < 0) + { + sdbg("ERROR: waitpid() failed: %d\n", errno); + } +#else bultin_semtake(&g_builtin_execsem); +#endif /* Get the result and relinquish our access to the parameter structure */ diff --git a/apps/nshlib/nsh_builtin.c b/apps/nshlib/nsh_builtin.c index 2d23ca8d8..343a0824b 100644 --- a/apps/nshlib/nsh_builtin.c +++ b/apps/nshlib/nsh_builtin.c @@ -51,7 +51,6 @@ #endif #include -#include #include #include @@ -117,8 +116,8 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { int ret = OK; - /* Lock the scheduler to prevent the application from running until the - * waitpid() has been called. + /* Lock the scheduler in an attempt to prevent the application from + * running until waitpid() has been called. */ sched_lock(); @@ -146,18 +145,6 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, #ifdef CONFIG_SCHED_WAITPID - /* Check if the application is still running */ - - if (kill(ret, 0) < 0) - { - /* It is not running. In this case, we have no idea if the - * application ran successfully or not. Let's assume that is - * did. - */ - - return 0; - } - /* CONFIG_SCHED_WAITPID is selected, so we may run the command in * foreground unless we were specifically requested to run the command * in background (and running commands in background is enabled). @@ -169,15 +156,40 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { int rc = 0; - /* Wait for the application to exit. Since we have locked the - * scheduler above, we know that the application has not yet - * started and there is no possibility that it has already exited. - * The scheduler will be unlocked while waitpid is waiting and the - * application will be able to run. + /* Wait for the application to exit. We did locked the scheduler + * above, but that does not guarantee that the application did not + * run in the case where I/O was redirected. The scheduler will + * be unlocked while waitpid is waiting and if the application has + * not yet run, it will be able to to do so. */ ret = waitpid(ret, &rc, 0); - if (ret >= 0) + if (ret < 0) + { + /* If the child thread does not exist, waitpid() will return + * the error ECHLD. Since we know that the task was successfully + * started, this must be one of the cases described above; we + * have to assume that the task already exit'ed. In this case, + * we have no idea if the application ran successfully or not + * (because NuttX does not retain exit status of child tasks). + * Let's assume that is did run successfully. + */ + + int errcode = errno; + if (errcode == ECHILD) + { + ret = OK; + } + else + { + nsh_output(vtbl, g_fmtcmdfailed, cmd, "waitpid", + NSH_ERRNO_OF(errcode)); + } + } + + /* Waitpid completed the wait successfully */ + + else { /* We can't return the exact status (nsh has nowhere to put it) * so just pass back zero/nonzero in a fashion that doesn't look diff --git a/apps/nshlib/nsh_fileapps.c b/apps/nshlib/nsh_fileapps.c index 7f9f58e53..92146a68d 100644 --- a/apps/nshlib/nsh_fileapps.c +++ b/apps/nshlib/nsh_fileapps.c @@ -44,7 +44,6 @@ #endif #include -#include #include #include #include @@ -154,8 +153,8 @@ int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, } } - /* Lock the scheduler to prevent the application from running until the - * waitpid() has been called. + /* Lock the scheduler in an attempt to prevent the application from + * running until waitpid() has been called. */ sched_lock(); @@ -182,17 +181,6 @@ int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, */ #ifdef CONFIG_SCHED_WAITPID - /* Check if the application is still running */ - - if (kill(ret, 0) < 0) - { - /* It is not running. In this case, we have no idea if the - * application ran successfully or not. Let's assume that is - * did. - */ - - return 0; - } /* CONFIG_SCHED_WAITPID is selected, so we may run the command in * foreground unless we were specifically requested to run the command @@ -205,15 +193,40 @@ int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { int rc = 0; - /* Wait for the application to exit. Since we have locked the - * scheduler above, we know that the application has not yet - * started and there is no possibility that it has already exited. - * The scheduler will be unlocked while waitpid is waiting and the - * application will be able to run. + /* Wait for the application to exit. We did locked the scheduler + * above, but that does not guarantee that the application did not + * run in the case where I/O was redirected. The scheduler will + * be unlocked while waitpid is waiting and if the application has + * not yet run, it will be able to to do so. */ ret = waitpid(pid, &rc, 0); - if (ret >= 0) + if (ret < 0) + { + /* If the child thread does not exist, waitpid() will return + * the error ECHLD. Since we know that the task was successfully + * started, this must be one of the cases described above; we + * have to assume that the task already exit'ed. In this case, + * we have no idea if the application ran successfully or not + * (because NuttX does not retain exit status of child tasks). + * Let's assume that is did run successfully. + */ + + int errcode = errno; + if (errcode == ECHILD) + { + ret = OK; + } + else + { + nsh_output(vtbl, g_fmtcmdfailed, cmd, "waitpid", + NSH_ERRNO_OF(errcode)); + } + } + + /* Waitpid completed the wait successfully */ + + else { /* We can't return the exact status (nsh has nowhere to put it) * so just pass back zero/nonzero in a fashion that doesn't look diff --git a/nuttx/configs/sim/README.txt b/nuttx/configs/sim/README.txt index 67ff73019..963a46e08 100644 --- a/nuttx/configs/sim/README.txt +++ b/nuttx/configs/sim/README.txt @@ -291,14 +291,31 @@ nsh apps/examples/hello. 3. This configuration has BINFS enabled so that the builtin applications - can be made visible in the file system. For example: - - NuttShell (NSH) NuttX-6.24 - nsh> mount -t binfs /bin - nsh> ls /bin - /bin: - hello - nsh> + can be made visible in the file system. Because of that, the + build in applications do not work as other examples. + + For example trying to execute the hello builtin application will + fail: + + nsh> hello + nsh: hello: command not found + nsh> + + Unless you first mount the BINFS file system: + + nsh> mount -t binfs /bin + nsh> ls /bin + /bin: + hello + nsh> echo $PATH + /bin + nsh> hello + Hello, World!! + nsh> + + Notice that the executable 'hello' is found using the value in the PATH + variable (which was preset to "/bin"). If the PATH variable were not set + then you would have to use /bin/hello on the command line. nsh2 diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c index 000f711a3..1bf7c2113 100644 --- a/nuttx/libc/spawn/lib_ps.c +++ b/nuttx/libc/spawn/lib_ps.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -75,7 +76,9 @@ struct spawn_parms_s ****************************************************************************/ static sem_t g_ps_parmsem = SEM_INITIALIZER(1); +#ifndef CONFIG_SCHED_WAITPID static sem_t g_ps_execsem = SEM_INITIALIZER(0); +#endif static struct spawn_parms_s g_ps_parms; /**************************************************************************** @@ -425,7 +428,9 @@ static int spawn_proxy(int argc, char *argv[]) */ g_ps_parms.result = ret; +#ifndef CONFIG_SCHED_WAITPID ps_semgive(&g_ps_execsem); +#endif return 0; } @@ -540,6 +545,9 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, { struct sched_param param; pid_t proxy; +#ifdef CONFIG_SCHED_WAITPID + int status; +#endif int ret; DEBUGASSERT(path); @@ -613,7 +621,15 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, /* Wait for the proxy to complete its job */ +#ifdef CONFIG_SCHED_WAITPID + ret = waitpid(proxy, &status, 0); + if (ret < 0) + { + sdbg("ERROR: waitpid() failed: %d\n", errno); + } +#else ps_semtake(&g_ps_execsem); +#endif /* Get the result and relinquish our access to the parameter structure */ -- cgit v1.2.3 From 76753ad9cb67133892000f19de10f93de78bb525 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 01:52:42 +0000 Subject: Add internal API task_reparent(), used in posix_spawn(). Move libc/spawn/lib_ps.c to sched/task_posixspawn.c; Move libc/spawn/spawn.h to include/nuttx/spawn.h git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5531 42af7a65-404d-4744-a932-0658087f49c3 --- apps/builtin/exec_builtin.c | 44 ++- apps/nshlib/nsh_builtin.c | 26 +- apps/nshlib/nsh_fileapps.c | 21 +- nuttx/ChangeLog | 7 +- nuttx/binfmt/binfmt_exec.c | 1 - nuttx/include/nuttx/spawn.h | 121 ++++++ nuttx/include/signal.h | 9 +- nuttx/libc/spawn/Make.defs | 2 - nuttx/libc/spawn/lib_ps.c | 639 -------------------------------- nuttx/libc/spawn/lib_psfa_addaction.c | 2 +- nuttx/libc/spawn/lib_psfa_addclose.c | 2 +- nuttx/libc/spawn/lib_psfa_adddup2.c | 2 +- nuttx/libc/spawn/lib_psfa_addopen.c | 2 +- nuttx/libc/spawn/lib_psfa_destroy.c | 2 +- nuttx/libc/spawn/lib_psfa_dump.c | 2 +- nuttx/libc/spawn/spawn.h | 121 ------ nuttx/sched/Makefile | 6 +- nuttx/sched/os_internal.h | 3 + nuttx/sched/task_posixspawn.c | 673 ++++++++++++++++++++++++++++++++++ nuttx/sched/task_reparent.c | 145 ++++++++ nuttx/syscall/syscall.csv | 2 + 21 files changed, 1029 insertions(+), 803 deletions(-) create mode 100644 nuttx/include/nuttx/spawn.h delete mode 100644 nuttx/libc/spawn/lib_ps.c delete mode 100644 nuttx/libc/spawn/spawn.h create mode 100644 nuttx/sched/task_posixspawn.c create mode 100644 nuttx/sched/task_reparent.c diff --git a/apps/builtin/exec_builtin.c b/apps/builtin/exec_builtin.c index 803d1ef34..60e8b742d 100644 --- a/apps/builtin/exec_builtin.c +++ b/apps/builtin/exec_builtin.c @@ -124,7 +124,7 @@ static void bultin_semtake(FAR sem_t *sem) do { ret = sem_wait(sem); - ASSERT(ret == 0 || errno == EINTR); + ASSERT(ret == 0 || get_errno() == EINTR); } while (ret != 0); } @@ -152,7 +152,7 @@ static int builtin_taskcreate(int index, FAR const char **argv) if (b == NULL) { - errno = ENOENT; + set_errno(ENOENT); return ERROR; } @@ -228,7 +228,7 @@ static int builtin_proxy(int argc, char *argv[]) { /* Remember the errno value. ret is already set to ERROR */ - g_builtin_parms.errcode = errno; + g_builtin_parms.errcode = get_errno(); sdbg("ERROR: open of %s failed: %d\n", g_builtin_parms.redirfile, g_builtin_parms.errcode); } @@ -246,7 +246,7 @@ static int builtin_proxy(int argc, char *argv[]) ret = dup2(fd, 1); if (ret < 0) { - g_builtin_parms.errcode = errno; + g_builtin_parms.errcode = get_errno(); sdbg("ERROR: dup2 failed: %d\n", g_builtin_parms.errcode); } @@ -266,12 +266,18 @@ static int builtin_proxy(int argc, char *argv[]) ret = builtin_taskcreate(g_builtin_parms.index, g_builtin_parms.argv); if (ret < 0) { - g_builtin_parms.errcode = errno; + g_builtin_parms.errcode = get_errno(); sdbg("ERROR: builtin_taskcreate failed: %d\n", g_builtin_parms.errcode); } } + /* NOTE: There is a logical error here if CONFIG_SCHED_HAVE_PARENT is + * defined: The new task is the child of this proxy task, not the + * original caller. As a consequence, operations like waitpid() will + * fail on the caller's thread. + */ + /* Post the semaphore to inform the parent task that we have completed * what we need to do. */ @@ -340,11 +346,21 @@ static inline int builtin_startproxy(int index, FAR const char **argv, ret = sched_getparam(0, ¶m); if (ret < 0) { - errcode = errno; + errcode = get_errno(); sdbg("ERROR: sched_getparam failed: %d\n", errcode); - goto errout; + goto errout_with_sem; } + /* Disable pre-emption so that the proxy does not run until we waitpid + * is called. This is probably unnecessary since the builtin_proxy has + * the same priority as this thread; it should be schedule behind this + * task in the ready-to-run list. + */ + +#ifdef CONFIG_SCHED_WAITPID + sched_lock(); +#endif + /* Start the intermediary/proxy task at the same priority as the parent task. */ proxy = TASK_CREATE("builtin_proxy", param.sched_priority, @@ -352,9 +368,9 @@ static inline int builtin_startproxy(int index, FAR const char **argv, (FAR const char **)NULL); if (proxy < 0) { - errcode = errno; + errcode = get_errno(); sdbg("ERROR: Failed to start builtin_proxy: %d\n", errcode); - goto errout; + goto errout_with_lock; } /* Wait for the proxy to complete its job. We could use waitpid() @@ -365,7 +381,8 @@ static inline int builtin_startproxy(int index, FAR const char **argv, ret = waitpid(proxy, &status, 0); if (ret < 0) { - sdbg("ERROR: waitpid() failed: %d\n", errno); + sdbg("ERROR: waitpid() failed: %d\n", get_errno()); + goto errout_with_lock; } #else bultin_semtake(&g_builtin_execsem); @@ -377,7 +394,12 @@ static inline int builtin_startproxy(int index, FAR const char **argv, builtin_semgive(&g_builtin_parmsem); return g_builtin_parms.result; -errout: +errout_with_lock: +#ifdef CONFIG_SCHED_WAITPID + sched_unlock(); +#endif + +errout_with_sem: set_errno(errcode); builtin_semgive(&g_builtin_parmsem); return ERROR; diff --git a/apps/nshlib/nsh_builtin.c b/apps/nshlib/nsh_builtin.c index 343a0824b..0d5a0231c 100644 --- a/apps/nshlib/nsh_builtin.c +++ b/apps/nshlib/nsh_builtin.c @@ -131,12 +131,14 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { /* The application was successfully started with pre-emption disabled. * In the simplest cases, the application will not have run because the - * the scheduler is locked. but in the case were I/O redirected, a - * proxy task ran and, as result, so may have the application. + * the scheduler is locked. But in the case where I/O was redirected, a + * proxy task ran and broke our lock. As result, the application may + * have aso ran if its priority was higher than than the priority of + * this thread. * - * If the application did not run and if the application was not - * backgrounded, then we need to wait here for the application to - * exit. This only works works with the following options: + * If the application did not run to completion and if the application + * was not backgrounded, then we need to wait here for the application + * to exit. This only works works with the following options: * * - CONFIG_NSH_DISABLEBG - Do not run commands in background * - CONFIG_SCHED_WAITPID - Required to run external commands in @@ -156,11 +158,17 @@ int nsh_builtin(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { int rc = 0; - /* Wait for the application to exit. We did locked the scheduler + /* Wait for the application to exit. We did lock the scheduler * above, but that does not guarantee that the application did not - * run in the case where I/O was redirected. The scheduler will - * be unlocked while waitpid is waiting and if the application has - * not yet run, it will be able to to do so. + * already run to completion in the case where I/O was redirected. + * Here the scheduler will be unlocked while waitpid is waiting + * and if the application has not yet run, it will now be able to + * do so. + * + * Also, if CONFIG_SCHED_HAVE_PARENT is defined waitpid() might fail + * even if task is still active: If the I/O was re-directed by a + * proxy task, then the ask is a child of the proxy, and not this + * task. waitpid() fails with ECHILD in either case. */ ret = waitpid(ret, &rc, 0); diff --git a/apps/nshlib/nsh_fileapps.c b/apps/nshlib/nsh_fileapps.c index 92146a68d..9ff230f1a 100644 --- a/apps/nshlib/nsh_fileapps.c +++ b/apps/nshlib/nsh_fileapps.c @@ -168,12 +168,14 @@ int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { /* The application was successfully started with pre-emption disabled. * In the simplest cases, the application will not have run because the - * the scheduler is locked. but in the case were I/O redirected, a - * proxy task ran and, as result, so may have the application. + * the scheduler is locked. But in the case where I/O was redirected, a + * proxy task ran and broke our lock. As result, the application may + * have aso ran if its priority was higher than than the priority of + * this thread. * - * If the application did not run and if the application was not - * backgrounded, then we need to wait here for the application to - * exit. This only works works with the following options: + * If the application did not run to completion and if the application + * was not backgrounded, then we need to wait here for the application + * to exit. This only works works with the following options: * * - CONFIG_NSH_DISABLEBG - Do not run commands in background * - CONFIG_SCHED_WAITPID - Required to run external commands in @@ -193,11 +195,12 @@ int nsh_fileapp(FAR struct nsh_vtbl_s *vtbl, FAR const char *cmd, { int rc = 0; - /* Wait for the application to exit. We did locked the scheduler + /* Wait for the application to exit. We did lock the scheduler * above, but that does not guarantee that the application did not - * run in the case where I/O was redirected. The scheduler will - * be unlocked while waitpid is waiting and if the application has - * not yet run, it will be able to to do so. + * already run to completion in the case where I/O was redirected. + * Here the scheduler will be unlocked while waitpid is waiting + * and if the application has not yet run, it will now be able to + * do so. */ ret = waitpid(pid, &rc, 0); diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 1b0c5338b..2a1561abe 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3971,4 +3971,9 @@ automatically unload and clean-up after running a task that was loaded into memory. * binfmt/libbuiltin: Extensions from Mike Smith - + * sched/task_reparent.c: Add internal interface to change the + parent task. + * sched/task_posixspawn(): Move libc/spawn/lib_ps.c to + sched/task_posixspawn() now it requires internal, reparenting + interfaces + * include/nuttx/spawn(): Move libc/spawn.h to include/nuttx/spawn.h diff --git a/nuttx/binfmt/binfmt_exec.c b/nuttx/binfmt/binfmt_exec.c index 7f45fb841..4226b6cfc 100644 --- a/nuttx/binfmt/binfmt_exec.c +++ b/nuttx/binfmt/binfmt_exec.c @@ -97,7 +97,6 @@ int exec(FAR const char *filename, FAR const char **argv, { #ifdef CONFIG_SCHED_ONEXIT FAR struct binary_s *bin; - int errorcode; int pid; int ret; diff --git a/nuttx/include/nuttx/spawn.h b/nuttx/include/nuttx/spawn.h new file mode 100644 index 000000000..f84ae8355 --- /dev/null +++ b/nuttx/include/nuttx/spawn.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * include/nuttx/spawn.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SPAWN_H +#define __INCLUDE_NUTTX_SPAWN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ +/* This enumerator identifies a file action */ + +enum spawn_file_actions_e +{ + SPAWN_FILE_ACTION_NONE = 0, + SPAWN_FILE_ACTION_CLOSE, + SPAWN_FILE_ACTION_DUP2, + SPAWN_FILE_ACTION_OPEN +}; + +/* posix_spawn_file_actions_addclose(), posix_spawn_file_actions_adddup2(), + * and posix_spawn_file_actions_addopen() will allocate memory and append + * a new file action to an instance of posix_spawn_file_actions_t. The + * internal representation of these structures are defined below: + */ + +struct spawn_general_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* A member of enum spawn_file_actions_e */ +}; + +struct spawn_close_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_CLOSE */ + int fd; /* The file descriptor to close */ +}; + +struct spawn_dup2_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_DUP2 */ + int fd1; /* The first file descriptor for dup2() */ + int fd2; /* The second file descriptor for dup2() */ +}; + +struct spawn_open_file_action_s +{ + FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ + enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_OPEN */ + int fd; /* The file descriptor after opening */ + int oflags; /* Open flags */ + mode_t mode; /* File creation mode */ + char path[1]; /* Start of the path to be + * opened */ +}; + +#define SIZEOF_OPEN_FILE_ACTION_S(n) \ + (sizeof(struct spawn_open_file_action_s) + (n)) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +void add_file_action(FAR posix_spawn_file_actions_t *file_action, + FAR struct spawn_general_file_action_s *entry); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_SPAWN_H */ diff --git a/nuttx/include/signal.h b/nuttx/include/signal.h index 30726105b..7c6b4cd55 100644 --- a/nuttx/include/signal.h +++ b/nuttx/include/signal.h @@ -61,14 +61,17 @@ /* All signals are "real time" signals */ -#define SIGRTMIN 0 /* First real time signal */ -#define SIGRTMAX 31 /* Last real time signal */ +#define SIGRTMIN MIN_SIGNO /* First real time signal */ +#define SIGRTMAX MAX_SIGNO /* Last real time signal */ /* A few of the real time signals are used within the OS. They have * default values that can be overridden from the configuration file. The * rest are all user signals. * - * These are semi-standard signal definitions: + * The signal number zero is wasted for the most part. It is a valid + * signal number, but has special meaning at many interfaces (e.g., Kill()). + * + * These are the semi-standard signal definitions: */ #ifndef CONFIG_SIG_SIGUSR1 diff --git a/nuttx/libc/spawn/Make.defs b/nuttx/libc/spawn/Make.defs index 99ee781ce..8cb086fee 100644 --- a/nuttx/libc/spawn/Make.defs +++ b/nuttx/libc/spawn/Make.defs @@ -37,8 +37,6 @@ ifeq ($(CONFIG_LIBC_EXECFUNCS),y) -CSRCS += lib_ps.c - CSRCS += lib_psfa_addaction.c lib_psfa_addclose.c lib_psfa_adddup2.c CSRCS += lib_psfa_addopen.c lib_psfa_destroy.c lib_psfa_init.c diff --git a/nuttx/libc/spawn/lib_ps.c b/nuttx/libc/spawn/lib_ps.c deleted file mode 100644 index 1bf7c2113..000000000 --- a/nuttx/libc/spawn/lib_ps.c +++ /dev/null @@ -1,639 +0,0 @@ -/**************************************************************************** - * libc/string/lib_ps.c - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "spawn/spawn.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct spawn_parms_s -{ - int result; - FAR pid_t *pid; - FAR const char *path; - FAR const posix_spawn_file_actions_t *file_actions; - FAR const posix_spawnattr_t *attr; - FAR char *const *argv; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static sem_t g_ps_parmsem = SEM_INITIALIZER(1); -#ifndef CONFIG_SCHED_WAITPID -static sem_t g_ps_execsem = SEM_INITIALIZER(0); -#endif -static struct spawn_parms_s g_ps_parms; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ps_semtake and ps_semgive - * - * Description: - * Give and take semaphores - * - * Input Parameters: - * - * sem - The semaphore to act on. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void ps_semtake(FAR sem_t *sem) -{ - int ret; - - do - { - ret = sem_wait(sem); - ASSERT(ret == 0 || errno == EINTR); - } - while (ret != 0); -} - -#define ps_semgive(sem) sem_post(sem) - -/**************************************************************************** - * Name: ps_exec - * - * Description: - * Execute the task from the file system. - * - * Input Parameters: - * - * pidp - Upon successful completion, this will return the task ID of the - * child task in the variable pointed to by a non-NULL 'pid' argument.| - * - * path - The 'path' argument identifies the file to execute. If - * CONFIG_BINFMT_EXEPATH is defined, this may be either a relative or - * or an absolute path. Otherwise, it must be an absolute path. - * - * attr - If the value of the 'attr' parameter is NULL, the all default - * values for the POSIX spawn attributes will be used. Otherwise, the - * attributes will be set according to the spawn flags. The - * following spawn flags are supported: - * - * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param - * value. - * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to - * the sched_policy value. - * - * NOTE: POSIX_SPAWN_SETSIGMASK is handled in ps_proxy(). - * - * argv - argv[] is the argument list for the new task. argv[] is an - * array of pointers to null-terminated strings. The list is terminated - * with a null pointer. - * - * Returned Value: - * This function will return zero on success. Otherwise, an error number - * will be returned as the function return value to indicate the error. - * This errno value may be that set by execv(), sched_setpolicy(), or - * sched_setparam(). - * - ****************************************************************************/ - -static int ps_exec(FAR pid_t *pidp, FAR const char *path, - FAR const posix_spawnattr_t *attr, - FAR char *const argv[]) -{ - struct sched_param param; - FAR const struct symtab_s *symtab; - int nsymbols; - int pid; - int ret = OK; - - DEBUGASSERT(path); - - /* Get the current symbol table selection */ - - exec_getsymtab(&symtab, &nsymbols); - - /* Disable pre-emption so that we can modify the task parameters after - * we start the new task; the new task will not actually begin execution - * until we re-enable pre-emption. - */ - - sched_lock(); - - /* Start the task */ - - pid = exec(path, (FAR const char **)argv, symtab, nsymbols); - if (pid < 0) - { - ret = errno; - sdbg("ERROR: exec failed: %d\n", ret); - goto errout; - } - - /* Return the task ID to the caller */ - - if (pid) - { - *pidp = pid; - } - - /* Now set the attributes. Note that we ignore all of the return values - * here because we have already successfully started the task. If we - * return an error value, then we would also have to stop the task. - */ - - if (attr) - { - /* If we are only setting the priority, then call sched_setparm() - * to set the priority of the of the new task. - */ - - if ((attr->flags & POSIX_SPAWN_SETSCHEDPARAM) != 0) - { - /* Get the priority from the attrributes */ - - param.sched_priority = attr->priority; - - /* If we are setting *both* the priority and the scheduler, - * then we will call sched_setscheduler() below. - */ - - if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) == 0) - { - svdbg("Setting priority=%d for pid=%d\n", - param.sched_priority, pid); - - (void)sched_setparam(pid, ¶m); - } - } - - /* If we are only changing the scheduling policy, then reset - * the priority to the default value (the same as this thread) in - * preparation for the sched_setscheduler() call below. - */ - - else if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) - { - (void)sched_getparam(0, ¶m); - } - - /* Are we setting the scheduling policy? If so, use the priority - * setting determined above. - */ - - if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) - { - svdbg("Setting policy=%d priority=%d for pid=%d\n", - attr->policy, param.sched_priority, pid); - - (void)sched_setscheduler(pid, attr->policy, ¶m); - } - } - - /* Re-enable pre-emption and return */ - -errout: - sched_unlock(); - return ret; -} - -/**************************************************************************** - * Name: spawn_close, spawn_dup2, and spawn_open - * - * Description: - * Implement individual file actions - * - * Input Parameters: - * action - describes the action to be performed - * - * Returned Value: - * posix_spawn() and posix_spawnp() will return zero on success. - * Otherwise, an error number will be returned as the function return - * value to indicate the error. - * - ****************************************************************************/ - -static inline int spawn_close(FAR struct spawn_close_file_action_s *action) -{ - /* The return value from close() is ignored */ - - svdbg("Closing fd=%d\n", action->fd); - - (void)close(action->fd); - return OK; -} - -static inline int spawn_dup2(FAR struct spawn_dup2_file_action_s *action) -{ - int ret; - - /* Perform the dup */ - - svdbg("Dup'ing %d->%d\n", action->fd1, action->fd2); - - ret = dup2(action->fd1, action->fd2); - if (ret < 0) - { - int errcode = errno; - - sdbg("ERROR: dup2 failed: %d\n", errcode); - return errcode; - } - - return OK; -} - -static inline int spawn_open(FAR struct spawn_open_file_action_s *action) -{ - int fd; - int ret = OK; - - /* Open the file */ - - svdbg("Open'ing path=%s oflags=%04x mode=%04x\n", - action->path, action->oflags, action->mode); - - fd = open(action->path, action->oflags, action->mode); - if (fd < 0) - { - ret = errno; - sdbg("ERROR: open failed: %d\n", ret); - } - - /* Does the return file descriptor happen to match the required file - * desciptor number? - */ - - else if (fd != action->fd) - { - /* No.. dup2 to get the correct file number */ - - svdbg("Dup'ing %d->%d\n", fd, action->fd); - - ret = dup2(fd, action->fd); - if (ret < 0) - { - ret = errno; - sdbg("ERROR: dup2 failed: %d\n", ret); - } - - svdbg("Closing fd=%d\n", fd); - close(fd); - } - - return ret; -} - -/**************************************************************************** - * Name: spawn_proxy - * - * Description: - * Perform file_actions, then execute the task from the file system. - * - * Input Parameters: - * Standard task start-up parameters - * - * Returned Value: - * Standard task return value. - * - ****************************************************************************/ - -static int spawn_proxy(int argc, char *argv[]) -{ - FAR struct spawn_general_file_action_s *entry; - FAR const posix_spawnattr_t *attr = g_ps_parms.attr; - int ret = OK; - - /* Perform file actions and/or set a custom signal mask. We get here only - * if the file_actions parameter to posix_spawn[p] was non-NULL and/or the - * option to change the signal mask was selected. - */ - -#ifndef CONFIG_DISABLE_SIGNALS - DEBUGASSERT((g_ps_parms.file_actions && *g_ps_parms.file_actions) || - (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0)); -#else - DEBUGASSERT(g_ps_parms.file_actions && *g_ps_parms.file_actions); -#endif - - /* Check if we need to change the signal mask */ - -#ifndef CONFIG_DISABLE_SIGNALS - if (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0) - { - (void)sigprocmask(SIG_SETMASK, &attr->sigmask, NULL); - } - - /* Were we also requested to perform file actions? */ - - if (g_ps_parms.file_actions) -#endif - { - /* Execute each file action */ - - for (entry = (FAR struct spawn_general_file_action_s *)*g_ps_parms.file_actions; - entry && ret == OK; - entry = entry->flink) - { - switch (entry->action) - { - case SPAWN_FILE_ACTION_CLOSE: - ret = spawn_close((FAR struct spawn_close_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_DUP2: - ret = spawn_dup2((FAR struct spawn_dup2_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_OPEN: - ret = spawn_open((FAR struct spawn_open_file_action_s *)entry); - break; - - case SPAWN_FILE_ACTION_NONE: - default: - sdbg("ERROR: Unknown action: %d\n", entry->action); - ret = EINVAL; - break; - } - } - } - - /* Check for failures */ - - if (ret == OK) - { - /* Start the task */ - - ret = ps_exec(g_ps_parms.pid, g_ps_parms.path, attr, g_ps_parms.argv); - } - - /* Post the semaphore to inform the parent task that we have completed - * what we need to do. - */ - - g_ps_parms.result = ret; -#ifndef CONFIG_SCHED_WAITPID - ps_semgive(&g_ps_execsem); -#endif - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: posix_spawn - * - * Description: - * The posix_spawn() and posix_spawnp() functions will create a new, - * child task, constructed from a regular executable file. - * - * Input Parameters: - * - * pid - Upon successful completion, posix_spawn() and posix_spawnp() will - * return the task ID of the child task to the parent task, in the - * variable pointed to by a non-NULL 'pid' argument. If the 'pid' - * argument is a null pointer, the process ID of the child is not - * returned to the caller. - * - * path - The 'path' argument to posix_spawn() is the absolute path that - * identifies the file to execute. The 'path' argument to posix_spawnp() - * may also be a relative path and will be used to construct a pathname - * that identifies the file to execute. In the case of a relative path, - * the path prefix for the file will be obtained by a search of the - * directories passed as the environment variable PATH. - * - * NOTE: NuttX provides only one implementation: If - * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior - * is supported; otherwise, only posix_spawn behavior is supported. - * - * file_actions - If 'file_actions' is a null pointer, then file - * descriptors open in the calling process will remain open in the - * child process (unless CONFIG_FDCLONE_STDIO is defined). If - * 'file_actions' is not NULL, then the file descriptors open in the - * child process will be those open in the calling process as modified - * by the spawn file actions object pointed to by file_actions. - * - * attr - If the value of the 'attr' parameter is NULL, the all default - * values for the POSIX spawn attributes will be used. Otherwise, the - * attributes will be set according to the spawn flags. The - * posix_spawnattr_t spawn attributes object type is defined in spawn.h. - * It will contains these attributes, not all of which are supported by - * NuttX: - * - * - POSIX_SPAWN_SETPGROUP: Setting of the new task's process group is - * not supported. NuttX does not support process groups. - * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param - * value. - * - POSIX_SPAWN_SETSCHEDULER: Set the new task's scheduler policy to - * the sched_policy value. - * - POSIX_SPAWN_RESETIDS: Resetting of the effective user ID of the child - * process is not supported. NuttX does not support effective user - * IDs. - * - POSIX_SPAWN_SETSIGMASK: Set the new task's signal mask. - * - POSIX_SPAWN_SETSIGDEF: Resetting signal default actions is not - * supported. NuttX does not support default signal actions. - * - * argv - argv[] is the argument list for the new task. argv[] is an - * array of pointers to null-terminated strings. The list is terminated - * with a null pointer. - * - * envp - The envp[] argument is not used by NuttX and may be NULL. In - * standard implementations, envp[] is an array of character pointers to - * null-terminated strings that provide the environment for the new - * process image. The environment array is terminated by a null pointer. - * In NuttX, the envp[] argument is ignored and the new task will simply - * inherit the environment of the parent task. - * - * Returned Value: - * posix_spawn() and posix_spawnp() will return zero on success. - * Otherwise, an error number will be returned as the function return - * value to indicate the error: - * - * - EINVAL: The value specified by 'file_actions' or 'attr' is invalid. - * - Any errors that might have been return if vfork() and excec[l|v]() - * had been called. - * - * Assumptions/Limitations: - * - NuttX provides only posix_spawn() or posix_spawnp() behavior - * depending upon the setting of CONFIG_BINFMT_EXEPATH: If - * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior - * is supported; otherwise, only posix_spawn behavior is supported. - * - The 'envp' argument is not used and the 'environ' variable is not - * altered (NuttX does not support the 'environ' variable). - * - Process groups are not supported (POSIX_SPAWN_SETPGROUP). - * - Effective user IDs are not supported (POSIX_SPAWN_RESETIDS). - * - Signal default actions cannot be modified in the newly task executed - * because NuttX does not support default signal actions - * (POSIX_SPAWN_SETSIGDEF). - * - * POSIX Compatibility - * - The value of the argv[0] received by the child task is assigned by - * NuttX. For the caller of posix_spawn(), the provided argv[0] will - * correspond to argv[1] received by the new task. - * - ****************************************************************************/ - -#ifdef CONFIG_BINFMT_EXEPATH -int posix_spawnp(FAR pid_t *pid, FAR const char *path, - FAR const posix_spawn_file_actions_t *file_actions, - FAR const posix_spawnattr_t *attr, - FAR char *const argv[], FAR char *const envp[]) -#else -int posix_spawn(FAR pid_t *pid, FAR const char *path, - FAR const posix_spawn_file_actions_t *file_actions, - FAR const posix_spawnattr_t *attr, - FAR char *const argv[], FAR char *const envp[]) -#endif -{ - struct sched_param param; - pid_t proxy; -#ifdef CONFIG_SCHED_WAITPID - int status; -#endif - int ret; - - DEBUGASSERT(path); - - svdbg("pid=%p path=%s file_actions=%p attr=%p argv=%p\n", - pid, path, file_actions, attr, argv); - - /* If there are no file actions to be performed and there is no change to - * the signal mask, then start the new child task directly from the parent task. - */ - -#ifndef CONFIG_DISABLE_SIGNALS - if ((file_actions == NULL || *file_actions == NULL) && - (attr == NULL || (attr->flags & POSIX_SPAWN_SETSIGMASK) == 0)) -#else - if (file_actions == NULL || *file_actions == NULL) -#endif - { - return ps_exec(pid, path, attr, argv); - } - - /* Otherwise, we will have to go through an intermediary/proxy task in order - * to perform the I/O redirection. This would be a natural place to fork(). - * However, true fork() behavior requires an MMU and most implementations - * of vfork() are not capable of these operations. - * - * Even without fork(), we can still do the job, but parameter passing is - * messier. Unfortunately, there is no (clean) way to pass binary values - * as a task parameter, so we will use a semaphore-protected global - * structure. - */ - - /* Get exclusive access to the global parameter structure */ - - ps_semtake(&g_ps_parmsem); - - /* Populate the parameter structure */ - - g_ps_parms.result = ENOSYS; - g_ps_parms.pid = pid; - g_ps_parms.path = path; - g_ps_parms.file_actions = file_actions; - g_ps_parms.attr = attr; - g_ps_parms.argv = argv; - - /* Get the priority of this (parent) task */ - - ret = sched_getparam(0, ¶m); - if (ret < 0) - { - int errcode = errno; - - sdbg("ERROR: sched_getparam failed: %d\n", errcode); - ps_semgive(&g_ps_parmsem); - return errcode; - } - - /* Start the intermediary/proxy task at the same priority as the parent task. */ - - proxy = TASK_CREATE("spawn_proxy", param.sched_priority, - CONFIG_POSIX_SPAWN_STACKSIZE, (main_t)spawn_proxy, - (FAR const char **)NULL); - if (proxy < 0) - { - int errcode = errno; - - sdbg("ERROR: Failed to start spawn_proxy: %d\n", errcode); - ps_semgive(&g_ps_parmsem); - return errcode; - } - - /* Wait for the proxy to complete its job */ - -#ifdef CONFIG_SCHED_WAITPID - ret = waitpid(proxy, &status, 0); - if (ret < 0) - { - sdbg("ERROR: waitpid() failed: %d\n", errno); - } -#else - ps_semtake(&g_ps_execsem); -#endif - - /* Get the result and relinquish our access to the parameter structure */ - - ret = g_ps_parms.result; - ps_semgive(&g_ps_parmsem); - return ret; -} diff --git a/nuttx/libc/spawn/lib_psfa_addaction.c b/nuttx/libc/spawn/lib_psfa_addaction.c index 3f297d7cf..8700efc2a 100644 --- a/nuttx/libc/spawn/lib_psfa_addaction.c +++ b/nuttx/libc/spawn/lib_psfa_addaction.c @@ -41,7 +41,7 @@ #include -#include "spawn/spawn.h" +#include /**************************************************************************** * Global Functions diff --git a/nuttx/libc/spawn/lib_psfa_addclose.c b/nuttx/libc/spawn/lib_psfa_addclose.c index bf22a153a..1c72f0f82 100644 --- a/nuttx/libc/spawn/lib_psfa_addclose.c +++ b/nuttx/libc/spawn/lib_psfa_addclose.c @@ -44,7 +44,7 @@ #include #include -#include "spawn/spawn.h" +#include /**************************************************************************** * Global Functions diff --git a/nuttx/libc/spawn/lib_psfa_adddup2.c b/nuttx/libc/spawn/lib_psfa_adddup2.c index fc788a4e9..deb3cbdb3 100644 --- a/nuttx/libc/spawn/lib_psfa_adddup2.c +++ b/nuttx/libc/spawn/lib_psfa_adddup2.c @@ -44,7 +44,7 @@ #include #include -#include "spawn/spawn.h" +#include /**************************************************************************** * Global Functions diff --git a/nuttx/libc/spawn/lib_psfa_addopen.c b/nuttx/libc/spawn/lib_psfa_addopen.c index 385e1cfc3..66bbd813a 100644 --- a/nuttx/libc/spawn/lib_psfa_addopen.c +++ b/nuttx/libc/spawn/lib_psfa_addopen.c @@ -45,7 +45,7 @@ #include #include -#include "spawn/spawn.h" +#include /**************************************************************************** * Global Functions diff --git a/nuttx/libc/spawn/lib_psfa_destroy.c b/nuttx/libc/spawn/lib_psfa_destroy.c index 5d0a644d8..a21886645 100644 --- a/nuttx/libc/spawn/lib_psfa_destroy.c +++ b/nuttx/libc/spawn/lib_psfa_destroy.c @@ -43,7 +43,7 @@ #include #include -#include "spawn/spawn.h" +#include /**************************************************************************** * Global Functions diff --git a/nuttx/libc/spawn/lib_psfa_dump.c b/nuttx/libc/spawn/lib_psfa_dump.c index d7bf1576d..0dbaeb023 100644 --- a/nuttx/libc/spawn/lib_psfa_dump.c +++ b/nuttx/libc/spawn/lib_psfa_dump.c @@ -43,7 +43,7 @@ #include #include -#include "spawn/spawn.h" +#include #ifdef CONFIG_DEBUG diff --git a/nuttx/libc/spawn/spawn.h b/nuttx/libc/spawn/spawn.h deleted file mode 100644 index 3f4e195cc..000000000 --- a/nuttx/libc/spawn/spawn.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * libc/spawn/spawn.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __LIBC_SPAWN_SPAWN_H -#define __LIBC_SPAWN_SPAWN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Type Definitions - ****************************************************************************/ -/* This enumerator identifies a file action */ - -enum spawn_file_actions_e -{ - SPAWN_FILE_ACTION_NONE = 0, - SPAWN_FILE_ACTION_CLOSE, - SPAWN_FILE_ACTION_DUP2, - SPAWN_FILE_ACTION_OPEN -}; - -/* posix_spawn_file_actions_addclose(), posix_spawn_file_actions_adddup2(), - * and posix_spawn_file_actions_addopen() will allocate memory and append - * a new file action to an instance of posix_spawn_file_actions_t. The - * internal representation of these structures are defined below: - */ - -struct spawn_general_file_action_s -{ - FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ - enum spawn_file_actions_e action; /* A member of enum spawn_file_actions_e */ -}; - -struct spawn_close_file_action_s -{ - FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ - enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_CLOSE */ - int fd; /* The file descriptor to close */ -}; - -struct spawn_dup2_file_action_s -{ - FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ - enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_DUP2 */ - int fd1; /* The first file descriptor for dup2() */ - int fd2; /* The second file descriptor for dup2() */ -}; - -struct spawn_open_file_action_s -{ - FAR struct spawn_general_file_action_s *flink; /* Supports a singly linked list */ - enum spawn_file_actions_e action; /* SPAWN_FILE_ACTION_OPEN */ - int fd; /* The file descriptor after opening */ - int oflags; /* Open flags */ - mode_t mode; /* File creation mode */ - char path[1]; /* Start of the path to be - * opened */ -}; - -#define SIZEOF_OPEN_FILE_ACTION_S(n) \ - (sizeof(struct spawn_open_file_action_s) + (n)) - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -void add_file_action(FAR posix_spawn_file_actions_t *file_action, - FAR struct spawn_general_file_action_s *entry); - -#ifdef __cplusplus -} -#endif - -#endif /* __LIBC_SPAWN_SPAWN_H */ diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile index 3d6b58bac..73c67239e 100644 --- a/nuttx/sched/Makefile +++ b/nuttx/sched/Makefile @@ -48,7 +48,7 @@ TSK_SRCS = prctl.c task_create.c task_init.c task_setup.c task_activate.c \ task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c \ sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c \ sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c \ - sched_verifytcb.c sched_releasetcb.c + sched_verifytcb.c sched_releasetcb.c task_posixspawn.c SCHED_SRCS = sched_setparam.c sched_setpriority.c sched_getparam.c \ sched_setscheduler.c sched_getscheduler.c \ @@ -67,6 +67,10 @@ ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) SCHED_SRCS += sched_reprioritize.c endif +ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) +SCHED_SRCS += task_reparent.c +endif + ifeq ($(CONFIG_SCHED_WAITPID),y) SCHED_SRCS += sched_waitpid.c ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h index 32d9fb4ac..f21d9654f 100644 --- a/nuttx/sched/os_internal.h +++ b/nuttx/sched/os_internal.h @@ -268,6 +268,9 @@ int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, int task_argsetup(FAR _TCB *tcb, FAR const char *name, FAR const char *argv[]); void task_exithook(FAR _TCB *tcb, int status); int task_deletecurrent(void); +#ifdef CONFIG_SCHED_HAVE_PARENT +int task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid); +#endif #ifndef CONFIG_CUSTOM_STACK int kernel_thread(FAR const char *name, int priority, int stack_size, main_t entry, FAR const char *argv[]); diff --git a/nuttx/sched/task_posixspawn.c b/nuttx/sched/task_posixspawn.c new file mode 100644 index 000000000..4201e759b --- /dev/null +++ b/nuttx/sched/task_posixspawn.c @@ -0,0 +1,673 @@ +/**************************************************************************** + * sched/task_posixspawn.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "os_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct spawn_parms_s +{ + int result; + FAR pid_t *pid; + FAR const char *path; + FAR const posix_spawn_file_actions_t *file_actions; + FAR const posix_spawnattr_t *attr; + FAR char *const *argv; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static sem_t g_ps_parmsem = SEM_INITIALIZER(1); +#ifndef CONFIG_SCHED_WAITPID +static sem_t g_ps_execsem = SEM_INITIALIZER(0); +#endif +static struct spawn_parms_s g_ps_parms; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spawn_semtake and spawn_semgive + * + * Description: + * Give and take semaphores + * + * Input Parameters: + * + * sem - The semaphore to act on. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spawn_semtake(FAR sem_t *sem) +{ + int ret; + + do + { + ret = sem_wait(sem); + ASSERT(ret == 0 || errno == EINTR); + } + while (ret != 0); +} + +#define spawn_semgive(sem) sem_post(sem) + +/**************************************************************************** + * Name: spawn_exec + * + * Description: + * Execute the task from the file system. + * + * Input Parameters: + * + * pidp - Upon successful completion, this will return the task ID of the + * child task in the variable pointed to by a non-NULL 'pid' argument.| + * + * path - The 'path' argument identifies the file to execute. If + * CONFIG_BINFMT_EXEPATH is defined, this may be either a relative or + * or an absolute path. Otherwise, it must be an absolute path. + * + * attr - If the value of the 'attr' parameter is NULL, the all default + * values for the POSIX spawn attributes will be used. Otherwise, the + * attributes will be set according to the spawn flags. The + * following spawn flags are supported: + * + * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param + * value. + * - POSIX_SPAWN_SETSCHEDULER: Set the new tasks scheduler priority to + * the sched_policy value. + * + * NOTE: POSIX_SPAWN_SETSIGMASK is handled in ps_proxy(). + * + * argv - argv[] is the argument list for the new task. argv[] is an + * array of pointers to null-terminated strings. The list is terminated + * with a null pointer. + * + * Returned Value: + * This function will return zero on success. Otherwise, an error number + * will be returned as the function return value to indicate the error. + * This errno value may be that set by execv(), sched_setpolicy(), or + * sched_setparam(). + * + ****************************************************************************/ + +static int spawn_exec(FAR pid_t *pidp, FAR const char *path, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[]) +{ + struct sched_param param; + FAR const struct symtab_s *symtab; + int nsymbols; + int pid; + int ret = OK; + + DEBUGASSERT(path); + + /* Get the current symbol table selection */ + + exec_getsymtab(&symtab, &nsymbols); + + /* Disable pre-emption so that we can modify the task parameters after + * we start the new task; the new task will not actually begin execution + * until we re-enable pre-emption. + */ + + sched_lock(); + + /* Start the task */ + + pid = exec(path, (FAR const char **)argv, symtab, nsymbols); + if (pid < 0) + { + ret = errno; + sdbg("ERROR: exec failed: %d\n", ret); + goto errout; + } + + /* Return the task ID to the caller */ + + if (pid) + { + *pidp = pid; + } + + /* Now set the attributes. Note that we ignore all of the return values + * here because we have already successfully started the task. If we + * return an error value, then we would also have to stop the task. + */ + + if (attr) + { + /* If we are only setting the priority, then call sched_setparm() + * to set the priority of the of the new task. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDPARAM) != 0) + { + /* Get the priority from the attrributes */ + + param.sched_priority = attr->priority; + + /* If we are setting *both* the priority and the scheduler, + * then we will call sched_setscheduler() below. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) == 0) + { + svdbg("Setting priority=%d for pid=%d\n", + param.sched_priority, pid); + + (void)sched_setparam(pid, ¶m); + } + } + + /* If we are only changing the scheduling policy, then reset + * the priority to the default value (the same as this thread) in + * preparation for the sched_setscheduler() call below. + */ + + else if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) + { + (void)sched_getparam(0, ¶m); + } + + /* Are we setting the scheduling policy? If so, use the priority + * setting determined above. + */ + + if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) + { + svdbg("Setting policy=%d priority=%d for pid=%d\n", + attr->policy, param.sched_priority, pid); + + (void)sched_setscheduler(pid, attr->policy, ¶m); + } + } + + /* Re-enable pre-emption and return */ + +errout: + sched_unlock(); + return ret; +} + +/**************************************************************************** + * Name: spawn_close, spawn_dup2, and spawn_open + * + * Description: + * Implement individual file actions + * + * Input Parameters: + * action - describes the action to be performed + * + * Returned Value: + * posix_spawn() and posix_spawnp() will return zero on success. + * Otherwise, an error number will be returned as the function return + * value to indicate the error. + * + ****************************************************************************/ + +static inline int spawn_close(FAR struct spawn_close_file_action_s *action) +{ + /* The return value from close() is ignored */ + + svdbg("Closing fd=%d\n", action->fd); + + (void)close(action->fd); + return OK; +} + +static inline int spawn_dup2(FAR struct spawn_dup2_file_action_s *action) +{ + int ret; + + /* Perform the dup */ + + svdbg("Dup'ing %d->%d\n", action->fd1, action->fd2); + + ret = dup2(action->fd1, action->fd2); + if (ret < 0) + { + int errcode = errno; + + sdbg("ERROR: dup2 failed: %d\n", errcode); + return errcode; + } + + return OK; +} + +static inline int spawn_open(FAR struct spawn_open_file_action_s *action) +{ + int fd; + int ret = OK; + + /* Open the file */ + + svdbg("Open'ing path=%s oflags=%04x mode=%04x\n", + action->path, action->oflags, action->mode); + + fd = open(action->path, action->oflags, action->mode); + if (fd < 0) + { + ret = errno; + sdbg("ERROR: open failed: %d\n", ret); + } + + /* Does the return file descriptor happen to match the required file + * desciptor number? + */ + + else if (fd != action->fd) + { + /* No.. dup2 to get the correct file number */ + + svdbg("Dup'ing %d->%d\n", fd, action->fd); + + ret = dup2(fd, action->fd); + if (ret < 0) + { + ret = errno; + sdbg("ERROR: dup2 failed: %d\n", ret); + } + + svdbg("Closing fd=%d\n", fd); + close(fd); + } + + return ret; +} + +/**************************************************************************** + * Name: spawn_proxy + * + * Description: + * Perform file_actions, then execute the task from the file system. + * + * Input Parameters: + * Standard task start-up parameters + * + * Returned Value: + * Standard task return value. + * + ****************************************************************************/ + +static int spawn_proxy(int argc, char *argv[]) +{ + FAR struct spawn_general_file_action_s *entry; + FAR const posix_spawnattr_t *attr = g_ps_parms.attr; + int ret = OK; + + /* Perform file actions and/or set a custom signal mask. We get here only + * if the file_actions parameter to posix_spawn[p] was non-NULL and/or the + * option to change the signal mask was selected. + */ + +#ifndef CONFIG_DISABLE_SIGNALS + DEBUGASSERT((g_ps_parms.file_actions && *g_ps_parms.file_actions) || + (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0)); +#else + DEBUGASSERT(g_ps_parms.file_actions && *g_ps_parms.file_actions); +#endif + + /* Check if we need to change the signal mask */ + +#ifndef CONFIG_DISABLE_SIGNALS + if (attr && (attr->flags & POSIX_SPAWN_SETSIGMASK) != 0) + { + (void)sigprocmask(SIG_SETMASK, &attr->sigmask, NULL); + } + + /* Were we also requested to perform file actions? */ + + if (g_ps_parms.file_actions) +#endif + { + /* Execute each file action */ + + for (entry = (FAR struct spawn_general_file_action_s *)*g_ps_parms.file_actions; + entry && ret == OK; + entry = entry->flink) + { + switch (entry->action) + { + case SPAWN_FILE_ACTION_CLOSE: + ret = spawn_close((FAR struct spawn_close_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_DUP2: + ret = spawn_dup2((FAR struct spawn_dup2_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_OPEN: + ret = spawn_open((FAR struct spawn_open_file_action_s *)entry); + break; + + case SPAWN_FILE_ACTION_NONE: + default: + sdbg("ERROR: Unknown action: %d\n", entry->action); + ret = EINVAL; + break; + } + } + } + + /* Check for failures */ + + if (ret == OK) + { + /* Start the task */ + + ret = spawn_exec(g_ps_parms.pid, g_ps_parms.path, attr, + g_ps_parms.argv); + +#ifdef CONFIG_SCHED_HAVE_PARENT + if (ret == OK) + { + /* Change of the parent of the task we just spawned to our parent. + * What should we do in the event of a failure? + */ + + int tmp = task_reparent(0, 0, *g_ps_parms.pid); + if (tmp < 0) + { + sdbg("ERROR: task_reparent() failed: %d\n", tmp); + } + } +#endif + } + + /* Post the semaphore to inform the parent task that we have completed + * what we need to do. + */ + + g_ps_parms.result = ret; +#ifndef CONFIG_SCHED_WAITPID + spawn_semgive(&g_ps_execsem); +#endif + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: posix_spawn + * + * Description: + * The posix_spawn() and posix_spawnp() functions will create a new, + * child task, constructed from a regular executable file. + * + * Input Parameters: + * + * pid - Upon successful completion, posix_spawn() and posix_spawnp() will + * return the task ID of the child task to the parent task, in the + * variable pointed to by a non-NULL 'pid' argument. If the 'pid' + * argument is a null pointer, the process ID of the child is not + * returned to the caller. + * + * path - The 'path' argument to posix_spawn() is the absolute path that + * identifies the file to execute. The 'path' argument to posix_spawnp() + * may also be a relative path and will be used to construct a pathname + * that identifies the file to execute. In the case of a relative path, + * the path prefix for the file will be obtained by a search of the + * directories passed as the environment variable PATH. + * + * NOTE: NuttX provides only one implementation: If + * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior + * is supported; otherwise, only posix_spawn behavior is supported. + * + * file_actions - If 'file_actions' is a null pointer, then file + * descriptors open in the calling process will remain open in the + * child process (unless CONFIG_FDCLONE_STDIO is defined). If + * 'file_actions' is not NULL, then the file descriptors open in the + * child process will be those open in the calling process as modified + * by the spawn file actions object pointed to by file_actions. + * + * attr - If the value of the 'attr' parameter is NULL, the all default + * values for the POSIX spawn attributes will be used. Otherwise, the + * attributes will be set according to the spawn flags. The + * posix_spawnattr_t spawn attributes object type is defined in spawn.h. + * It will contains these attributes, not all of which are supported by + * NuttX: + * + * - POSIX_SPAWN_SETPGROUP: Setting of the new task's process group is + * not supported. NuttX does not support process groups. + * - POSIX_SPAWN_SETSCHEDPARAM: Set new tasks priority to the sched_param + * value. + * - POSIX_SPAWN_SETSCHEDULER: Set the new task's scheduler policy to + * the sched_policy value. + * - POSIX_SPAWN_RESETIDS: Resetting of the effective user ID of the child + * process is not supported. NuttX does not support effective user + * IDs. + * - POSIX_SPAWN_SETSIGMASK: Set the new task's signal mask. + * - POSIX_SPAWN_SETSIGDEF: Resetting signal default actions is not + * supported. NuttX does not support default signal actions. + * + * argv - argv[] is the argument list for the new task. argv[] is an + * array of pointers to null-terminated strings. The list is terminated + * with a null pointer. + * + * envp - The envp[] argument is not used by NuttX and may be NULL. In + * standard implementations, envp[] is an array of character pointers to + * null-terminated strings that provide the environment for the new + * process image. The environment array is terminated by a null pointer. + * In NuttX, the envp[] argument is ignored and the new task will simply + * inherit the environment of the parent task. + * + * Returned Value: + * posix_spawn() and posix_spawnp() will return zero on success. + * Otherwise, an error number will be returned as the function return + * value to indicate the error: + * + * - EINVAL: The value specified by 'file_actions' or 'attr' is invalid. + * - Any errors that might have been return if vfork() and excec[l|v]() + * had been called. + * + * Assumptions/Limitations: + * - NuttX provides only posix_spawn() or posix_spawnp() behavior + * depending upon the setting of CONFIG_BINFMT_EXEPATH: If + * CONFIG_BINFMT_EXEPATH is defined, then only posix_spawnp() behavior + * is supported; otherwise, only posix_spawn behavior is supported. + * - The 'envp' argument is not used and the 'environ' variable is not + * altered (NuttX does not support the 'environ' variable). + * - Process groups are not supported (POSIX_SPAWN_SETPGROUP). + * - Effective user IDs are not supported (POSIX_SPAWN_RESETIDS). + * - Signal default actions cannot be modified in the newly task executed + * because NuttX does not support default signal actions + * (POSIX_SPAWN_SETSIGDEF). + * + * POSIX Compatibility + * - The value of the argv[0] received by the child task is assigned by + * NuttX. For the caller of posix_spawn(), the provided argv[0] will + * correspond to argv[1] received by the new task. + * + ****************************************************************************/ + +#ifdef CONFIG_BINFMT_EXEPATH +int posix_spawnp(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[], FAR char *const envp[]) +#else +int posix_spawn(FAR pid_t *pid, FAR const char *path, + FAR const posix_spawn_file_actions_t *file_actions, + FAR const posix_spawnattr_t *attr, + FAR char *const argv[], FAR char *const envp[]) +#endif +{ + struct sched_param param; + pid_t proxy; +#ifdef CONFIG_SCHED_WAITPID + int status; +#endif + int ret; + + DEBUGASSERT(path); + + svdbg("pid=%p path=%s file_actions=%p attr=%p argv=%p\n", + pid, path, file_actions, attr, argv); + + /* If there are no file actions to be performed and there is no change to + * the signal mask, then start the new child task directly from the parent task. + */ + +#ifndef CONFIG_DISABLE_SIGNALS + if ((file_actions == NULL || *file_actions == NULL) && + (attr == NULL || (attr->flags & POSIX_SPAWN_SETSIGMASK) == 0)) +#else + if (file_actions == NULL || *file_actions == NULL) +#endif + { + return spawn_exec(pid, path, attr, argv); + } + + /* Otherwise, we will have to go through an intermediary/proxy task in order + * to perform the I/O redirection. This would be a natural place to fork(). + * However, true fork() behavior requires an MMU and most implementations + * of vfork() are not capable of these operations. + * + * Even without fork(), we can still do the job, but parameter passing is + * messier. Unfortunately, there is no (clean) way to pass binary values + * as a task parameter, so we will use a semaphore-protected global + * structure. + */ + + /* Get exclusive access to the global parameter structure */ + + spawn_semtake(&g_ps_parmsem); + + /* Populate the parameter structure */ + + g_ps_parms.result = ENOSYS; + g_ps_parms.pid = pid; + g_ps_parms.path = path; + g_ps_parms.file_actions = file_actions; + g_ps_parms.attr = attr; + g_ps_parms.argv = argv; + + /* Get the priority of this (parent) task */ + + ret = sched_getparam(0, ¶m); + if (ret < 0) + { + int errcode = errno; + + sdbg("ERROR: sched_getparam failed: %d\n", errcode); + spawn_semgive(&g_ps_parmsem); + return errcode; + } + + /* Disable pre-emption so that the proxy does not run until we waitpid + * is called. This is probably unnecessary since the spawn_proxy has + * the same priority as this thread; it should be schedule behind this + * task in the ready-to-run list. + */ + +#ifdef CONFIG_SCHED_WAITPID + sched_lock(); +#endif + + /* Start the intermediary/proxy task at the same priority as the parent + * task. + */ + + proxy = TASK_CREATE("spawn_proxy", param.sched_priority, + CONFIG_POSIX_SPAWN_STACKSIZE, (main_t)spawn_proxy, + (FAR const char **)NULL); + if (proxy < 0) + { + ret = get_errno(); + sdbg("ERROR: Failed to start spawn_proxy: %d\n", ret); + + goto errout_with_lock; + } + + /* Wait for the proxy to complete its job */ + +#ifdef CONFIG_SCHED_WAITPID + ret = waitpid(proxy, &status, 0); + if (ret < 0) + { + sdbg("ERROR: waitpid() failed: %d\n", errno); + goto errout_with_lock; + } +#else + spawn_semtake(&g_ps_execsem); +#endif + + /* Get the result and relinquish our access to the parameter structure */ + + ret = g_ps_parms.result; + +errout_with_lock: +#ifdef CONFIG_SCHED_WAITPID + sched_unlock(); +#endif + spawn_semgive(&g_ps_parmsem); + return ret; +} diff --git a/nuttx/sched/task_reparent.c b/nuttx/sched/task_reparent.c new file mode 100644 index 000000000..9daa0743b --- /dev/null +++ b/nuttx/sched/task_reparent.c @@ -0,0 +1,145 @@ +/***************************************************************************** + * sched/task_reparent.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include + +#include "os_internal.h" + +#ifdef CONFIG_SCHED_HAVE_PARENT + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: task_reparent + * + * Description: + * Change the parent of a task. + * + * Parameters: + * oldpid - PID of the old parent task (0 if this task) + * newpid - PID ot the new parent task (0 for the parent of this task) + * chpid - PID of the child to be reparented. + * + * Return Value: + * 0 (OK) on success; A negated errno value on failure. + * + *****************************************************************************/ + +int task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid) +{ + _TCB *oldtcb; + _TCB *newtcb; + _TCB *chtcb; + irqstate_t flags; + int ret; + + /* If oldpid is zero, then we are parent task. */ + + if (oldpid == 0) + { + oldpid = getpid(); + } + + /* Get the current parent task's TCB */ + + oldtcb = sched_gettcb(oldpid); + if (!oldtcb) + { + return -ESRCH; + } + + /* Disable interrupts so that nothing can change from this point */ + + flags = irqsave(); + + /* If newpid is zero, then new is the parent of oldpid. */ + + if (newpid == 0) + { + newpid = oldtcb->parent; + } + + /* Get the new parent task's TCB */ + + newtcb = sched_gettcb(newpid); + if (!newtcb) + { + ret = -ESRCH; + goto errout_with_ints; + } + + /* Get the child tasks TCB */ + + chtcb = sched_gettcb(chpid); + if (!chtcb) + { + ret = -ECHILD; + goto errout_with_ints; + } + + /* Verify that oldpid is the parent of chpid */ + + if (chtcb->parent != oldpid) + { + ret = -ECHILD; + goto errout_with_ints; + } + + /* Okay, reparent the child */ + + DEBUGASSERT(oldtcb->nchildren > 0); + chtcb->parent = newpid; + oldtcb->nchildren--; + newtcb->nchildren++; + ret = OK; + +errout_with_ints: + irqrestore(flags); + return ret; +} + +#endif /* CONFIG_SCHED_HAVE_PARENT */ diff --git a/nuttx/syscall/syscall.csv b/nuttx/syscall/syscall.csv index 4ccd53f9d..5bc52a71d 100644 --- a/nuttx/syscall/syscall.csv +++ b/nuttx/syscall/syscall.csv @@ -43,6 +43,8 @@ "prctl","sys/prctl.h", "CONFIG_TASK_NAME_SIZE > 0","int","int","..." "clock_systimer","nuttx/clock.h","!defined(CONFIG_DISABLE_CLOCK)","uint32_t" "poll","poll.h","!defined(CONFIG_DISABLE_POLL) && (CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0)","int","FAR struct pollfd*","nfds_t","int" +"posix_spawnp", defined(CONFIG_BINFMT_EXEPATH), "int","FAR pid_t *","FAR const char *","FAR const posix_spawn_file_actions_t *","FAR const posix_spawnattr_t *","FAR char *const []","FAR char *const []" +"posix_spawn", !defined(CONFIG_BINFMT_EXEPATH), "int","FAR pid_t *","FAR const char *","FAR const posix_spawn_file_actions_t *","FAR const posix_spawnattr_t *","FAR char *const []","FAR char *const []" "pthread_barrier_destroy","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_barrier_t*" "pthread_barrier_init","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_barrier_t*","FAR const pthread_barrierattr_t*","unsigned int" "pthread_barrier_wait","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_barrier_t*" -- cgit v1.2.3 From 55b9700d59bb38db9427258b5dd2e1020a6fef67 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 13:34:09 +0000 Subject: STM32 I2C changes from Mike Smith git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5532 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/stm32/stm32_i2c.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.c b/nuttx/arch/arm/src/stm32/stm32_i2c.c index c44a823db..18687c6f4 100644 --- a/nuttx/arch/arm/src/stm32/stm32_i2c.c +++ b/nuttx/arch/arm/src/stm32/stm32_i2c.c @@ -1245,11 +1245,11 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Disable acknowledge when last byte is to be received */ + priv->dcnt--; if (priv->dcnt == 1) { stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); } - priv->dcnt--; #ifdef CONFIG_I2C_POLLED irqrestore(state); @@ -1985,7 +1985,6 @@ int up_i2creset(FAR struct i2c_dev_s * dev) unit32_ scl_gpio; unit32_ sda_gpio; int ret = ERROR; - irqstate_t state; ASSERT(dev); @@ -2010,6 +2009,10 @@ int up_i2creset(FAR struct i2c_dev_s * dev) scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; @@ -2017,7 +2020,7 @@ int up_i2creset(FAR struct i2c_dev_s * dev) { /* Give up if we have tried too hard */ - if (clock_count++ > 1000) + if (clock_count++ > 10) { goto out; } @@ -2032,7 +2035,7 @@ int up_i2creset(FAR struct i2c_dev_s * dev) { /* Give up if we have tried too hard */ - if (stretch_count++ > 1000) + if (stretch_count++ > 10) { goto out; } -- cgit v1.2.3 From 3ff155d04803d8b19f0f56602e95b4034bc33820 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 16:37:37 +0000 Subject: Beginnings of definitions for the LPC1788; convert olimex-lpc1766stk to use kconfig-frontends git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5533 42af7a65-404d-4744-a932-0658087f49c3 --- apps/nshlib/nsh_netcmds.c | 5 +- nuttx/ChangeLog | 5 + nuttx/arch/arm/include/lpc17xx/chip.h | 377 ++++++++++ nuttx/arch/arm/include/lpc17xx/irq.h | 203 +----- nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h | 245 +++++++ nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h | 294 ++++++++ nuttx/arch/arm/src/lpc17xx/Kconfig | 56 +- nuttx/arch/arm/src/lpc17xx/chip.h | 158 +---- nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c | 3 +- nuttx/configs/olimex-lpc1766stk/README.txt | 55 +- nuttx/configs/olimex-lpc1766stk/nsh/appconfig | 66 -- nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 951 ++++++++++++++++---------- nuttx/drivers/mmcsd/Kconfig | 2 +- nuttx/sched/Makefile | 172 ++--- nuttx/sched/os_internal.h | 2 +- nuttx/sched/task_posixspawn.c | 3 +- nuttx/sched/task_reparent.c | 77 +-- 17 files changed, 1731 insertions(+), 943 deletions(-) create mode 100644 nuttx/arch/arm/include/lpc17xx/chip.h create mode 100644 nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h create mode 100644 nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h delete mode 100644 nuttx/configs/olimex-lpc1766stk/nsh/appconfig diff --git a/apps/nshlib/nsh_netcmds.c b/apps/nshlib/nsh_netcmds.c index 506950e14..473045c40 100644 --- a/apps/nshlib/nsh_netcmds.c +++ b/apps/nshlib/nsh_netcmds.c @@ -53,12 +53,13 @@ #include #include +#include +#include + #include #include -#include #include #include -#include #ifdef CONFIG_NET_STATISTICS # include diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2a1561abe..c61479cad 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3977,3 +3977,8 @@ sched/task_posixspawn() now it requires internal, reparenting interfaces * include/nuttx/spawn(): Move libc/spawn.h to include/nuttx/spawn.h + * arch/arm/include/lpc17xx/chip.h, irq178x.h: Integrate Marcelo + Rommel's LPC1788 definitions into the base LPC17xx. + * configs/olimex-lpc1766stk/nsh: Convert configuration to use + the kconfig-frontends tools. + * sched/task_reparent.c: Simplify reparenting interface. diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h new file mode 100644 index 000000000..d2c436d35 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/chip.h @@ -0,0 +1,377 @@ +/************************************************************************************ + * arch/arm/include/lpc17xx/chip.h + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * with LPC178x support from Rommel Marcelo + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H +#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_LPC1751) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ +# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1752) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ +# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1754) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 1 /* One CAN controller */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1756) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1758) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1759) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1764) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 0 /* No I2S modules */ +# define LPC17_NDAC 0 /* No DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1765) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1766) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1767) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 0 /* No USB host controller */ +# define LPC17_NUSBOTG 0 /* No USB OTG controller */ +# define LPC17_NUSBDEV 0 /* No USB device controller */ +# define LPC17_NCAN 0 /* No CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) +# define LPC176x 1 /* LPC175/6 family */ +# undef LPC178x /* Not LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_NCAN 2 /* Two CAN controllers */ +# define LPC17_NI2S 1 /* One I2S module */ +# define LPC17_NDAC 1 /* One DAC module */ +#elif defined(CONFIG_ARCH_CHIP_LPC1773) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_NUSBHOST /* No USB host controller */ +# undef LPC17_NUSBOTG /* No USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* No LCD controller */ +# undef LPC17_HAVE_QEI /* No QEI interface */ +# undef LPC17_HAVE_SD /* No SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1774) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ +# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ +# define LPC17_CPUSRAM_SIZE (8*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LPC17_NUSBHOST /* One USB host controller */ +# undef LPC17_NUSBOTG /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1776) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1777) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1778) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# undef LPC17_HAVE_LCD /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1785) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# undef LPC17_HAVE_QEI /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1786) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (16*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1787) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#elif defined(CONFIG_ARCH_CHIP_LPC1788) +# undef LPC176x /* Not LPC175/6 family */ +# define LPC178x 1 /* LPC177/8 family */ +# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ +# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ +# define LPC17_CPUSRAM_SIZE (32*1024) +# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */ +# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */ +# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ +# define LPC17_NUSBHOST 1 /* One USB host controller */ +# define LPC17_NUSBOTG 1 /* One USB OTG controller */ +# define LPC17_NUSBDEV 1 /* One USB device controller */ +# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */ +# define LPC17_HAVE_LCD 1 /* One LCD controller */ +# define LPC17_HAVE_QEI 1 /* One QEI interface */ +# define LPC17_HAVE_SD 1 /* One SD controller */ +#else +# error "Unsupported LPC17xx chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */ diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h index a7eebb32c..c058f6367 100644 --- a/nuttx/arch/arm/include/lpc17xx/irq.h +++ b/nuttx/arch/arm/include/lpc17xx/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/lpc17xxx/irq.h + * arch/arm/include/lpc17xxx/irq.h * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,12 +33,12 @@ * ****************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h */ -#ifndef __ARCH_LPC17XX_IRQ_H -#define __ARCH_LPC17XX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H /**************************************************************************** * Included Files @@ -47,17 +47,17 @@ #ifndef __ASSEMBLY__ # include #endif +#include /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ - /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. */ -/* Processor Exceptions (vectors 0-15) */ +/* Common Processor Exceptions (vectors 0-15) */ #define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ /* Vector 0: Reset stack pointer value */ @@ -75,185 +75,24 @@ /* External interrupts (vectors >= 16) */ -#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ -#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) - * Capture 0 - 1 (CR0, CR1) */ -#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 - * Capture 0-1 */ -#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * Modem Control Change - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) - * Transmit Holding Register Empty (THRE) - * Rx Data Available (RDA) - * Character Time-out Indicator (CTI) - * End of Auto-Baud (ABEO) - * Auto-Baud Time-Out (ABTO) */ -#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 - * Capture 0-1 of PWM1 */ -#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ -#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ -#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ -#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) - * Mode Fault (MODF) */ -#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 - * Rx FIFO half full of SSP0 - * Rx Timeout of SSP0 - * Rx Overrun of SSP0 */ -#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty - * Rx FIFO half full - * Rx Timeout - * Rx Overrun */ -#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ -#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) - * Alarm (RTCALF) */ -#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ -#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ -#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ -#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) - * Note: EINT3 channel is shared with GPIO interrupts */ -#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ -#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ -#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, - * USB_INT_REQ_DMA */ -#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, - * CAN 1 Tx, CAN 1 Rx */ -#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, - * IntStatus of DMA channel 1 */ -#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ -#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, - * TxFinishedInt, TxErrorInt,* TxUnderrunInt, - * RxDoneInt, RxFinishedInt, RxErrorInt, - * RxOverrunInt */ -#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ -#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], - * ICAP[2:0], FES */ -#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, - * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int - * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, - * POS2REV_Int */ -#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ -#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ -#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ -#define LPC17_IRQ_NEXTINT (35) -#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) +#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ -/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and - * 2 (only). We go through some special efforts to keep the number of IRQs - * to a minimum in this sparse interrupt case. - * - * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 - * 14 interrupts on Port 2: p2.0 - p2.13 - * -- - * 42 - */ - -#ifdef CONFIG_GPIO_IRQ -# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ -# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ - - /* Set 1: 12 interrupts p0.0-p0.11 */ - -# define LPC17_VALID_GPIOINT0L (0x00000ffful) -# define LPC17_VALID_SHIFT0L (0) -# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) - -# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) -# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) -# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) -# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) -# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) -# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) -# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) -# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) -# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) -# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) -# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) -# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) -# define LPC17_VALID_NIRQS0L (12) - - /* Set 2: 16 interrupts p0.15-p0.30 */ - -# define LPC17_VALID_GPIOINT0H (0x7fff8000ull) -# define LPC17_VALID_SHIFT0H (15) -# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) - -# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0) -# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1) -# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2) -# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3) -# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4) -# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5) -# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6) -# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7) -# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8) -# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9) -# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10) -# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11) -# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12) -# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13) -# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14) -# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15) -# define LPC17_VALID_NIRQS0H (16) +/* Family Specfic Interrupts */ - /* Set 3: 14 interrupts p2.0-p2.13 */ - -# define LPC17_VALID_GPIOINT2 (0x00003ffful) -# define LPC17_VALID_SHIFT2 (0) -# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) - -# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0) -# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1) -# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2) -# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3) -# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4) -# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5) -# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6) -# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7) -# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8) -# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9) -# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10) -# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11) -# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12) -# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13) -# define LPC17_VALID_NIRQS2 (14) -# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2) +#if defined(LPC176x) /* LPC175/6 family */ +# include +#elif defined(LPC178x) /* LPC177/8 family */ +# include #else -# define LPC17_NGPIOAIRQS (0) +# error "Unknown LPC17xx family" #endif -/* Total number of IRQ numbers */ - -#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) - /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ typedef void (*vic_vector_t)(uint32_t *regs); -#endif /**************************************************************************** * Inline functions @@ -267,19 +106,15 @@ typedef void (*vic_vector_t)(uint32_t *regs); * Public Function Prototypes ****************************************************************************/ -#ifndef __ASSEMBLY__ #ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern +extern "C" +{ #endif -#undef EXTERN #ifdef __cplusplus } #endif -#endif +#endif __ASSEMBLY__ -#endif /* __ARCH_LPC17XX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */ diff --git a/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h new file mode 100644 index 000000000..ac97195e6 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/lpc176x_irq.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/lpc17xx/lpc176x_irq.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF) + * Mode Fault (MODF) */ +#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */ +#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_IRQ_NEXTINT (35) +#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30 + * 14 interrupts on Port 2: p2.0 - p2.13 + * -- + * 42 + */ + +#ifdef CONFIG_GPIO_IRQ +# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ +# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 12 interrupts p0.0-p0.11 */ + +# define LPC17_VALID_GPIOINT0L (0x00000ffful) +# define LPC17_VALID_SHIFT0L (0) +# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) +# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) +# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) +# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) +# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) +# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) +# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) +# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) +# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) +# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) +# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) +# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) +# define LPC17_VALID_NIRQS0L (12) + + /* Set 2: 16 interrupts p0.15-p0.30 */ + +# define LPC17_VALID_GPIOINT0H (0x7fff8000ull) +# define LPC17_VALID_SHIFT0H (15) +# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) + +# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0) +# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1) +# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2) +# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3) +# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4) +# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5) +# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6) +# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7) +# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8) +# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9) +# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10) +# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11) +# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12) +# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13) +# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14) +# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15) +# define LPC17_VALID_NIRQS0H (16) + + /* Set 3: 14 interrupts p2.0-p2.13 */ + +# define LPC17_VALID_GPIOINT2 (0x00003ffful) +# define LPC17_VALID_SHIFT2 (0) +# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) + +# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0) +# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1) +# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2) +# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3) +# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4) +# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5) +# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6) +# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7) +# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8) +# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9) +# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10) +# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11) +# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12) +# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13) +# define LPC17_VALID_NIRQS2 (14) +# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2) +#else +# define LPC17_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */ + diff --git a/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h new file mode 100644 index 000000000..9f7cbf9a7 --- /dev/null +++ b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h @@ -0,0 +1,294 @@ +/**************************************************************************** + * arch/arm/include/lpc17xxx/lpc178x_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* External interrupts (vectors >= 16) */ + +#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */ +#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2) + * Capture 0 - 1 (CR0, CR1) */ +#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3 + * Capture 0-1 */ +#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * Modem Control Change + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1 + * Capture 0-1 of PWM1 */ +#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ +#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ +#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ +/* (LPC17_IRQ_EXTINT+13) Unused */ +#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 + * Rx FIFO half full of SSP0 + * Rx Timeout of SSP0 + * Rx Overrun of SSP0 */ +#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty + * Rx FIFO half full + * Rx Timeout + * Rx Overrun */ +#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */ +#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF) + * Alarm (RTCALF) */ +#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */ +#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */ +#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */ +#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3) + * Note: EINT3 channel is shared with GPIO interrupts */ +#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */ +#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */ +#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP, + * USB_INT_REQ_DMA */ +#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx, + * CAN 1 Tx, CAN 1 Rx */ +#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0, + * IntStatus of DMA channel 1 */ +#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */ +#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt, + * TxFinishedInt, TxErrorInt,* TxUnderrunInt, + * RxDoneInt, RxFinishedInt, RxErrorInt, + * RxOverrunInt */ +#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */ +#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0], + * ICAP[2:0], FES */ +#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int, + * DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int + * POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int, + * POS2REV_Int */ +#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */ +#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */ +#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */ +#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS) + * Transmit Holding Register Empty (THRE) + * Rx Data Available (RDA) + * Character Time-out Indicator (CTI) + * End of Auto-Baud (ABEO) + * Auto-Baud Time-Out (ABTO) */ +#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2 + * Rx FIFO half full of SSP2 + * Rx Timeout of SSP2 + * Rx Overrun of SSP2 */ +#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt + * BER, VCompI, LNBUI, FUFI, CrsrI */ +#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt + * P0xREI, P2xREI, P0xFEI, P2xFEI */ +#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0 + * Capture 0-1 of PWM0 */ +#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt + * EE_PROG_DONE, EE_RW_DONE */ +#define LPC17_IRQ_NEXTINT (40) +#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and + * 2 (only). We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * 31 interrupts on Port 0: p0.0 - p0.30 + * 31 interrupts on Port 2: p2.0 - p2.30 + * -- + * 42 + */ + +#ifdef CONFIG_GPIO_IRQ +//~ # define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrrupt set */ +//~ # define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */ + + /* Set 1: 16 interrupts p0.0-p0.15 */ + +//~ # define LPC17_VALID_GPIOINT0L (0x00000ffful) +# define LPC17_VALID_SHIFT0L (0) +# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT) + +# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0) +# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1) +# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2) +# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3) +# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4) +# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5) +# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6) +# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7) +# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8) +# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9) +# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10) +# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11) +# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12) +# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13) +# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14) +# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15) +# define LPC17_VALID_NIRQS0L (16) + + /* Set 2: 16 interrupts p0.16-p0.31 */ + +//~ # define LPC17_VALID_GPIOINT0H (0x7fff8000ull) +# define LPC17_VALID_SHIFT0H (15) +# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L) + +# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0) +# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1) +# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2) +# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3) +# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4) +# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5) +# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6) +# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7) +# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8) +# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9) +# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10) +# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11) +# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12) +# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13) +# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14) +# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15) +# define LPC17_VALID_NIRQS0H (16) + + /* Set 3: 16 interrupts p2.0-p2.15 */ + +//~ # define LPC17_VALID_GPIOINT2 (0x00003ffful) +# define LPC17_VALID_SHIFT2L (0) +# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H) + +# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0) +# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1) +# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2) +# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3) +# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4) +# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5) +# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6) +# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7) +# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8) +# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9) +# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10) +# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11) +# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12) +# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13) +# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14) +# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15) +# define LPC17_VALID_NIRQS2L (16) + + /* Set 3: 16 interrupts p2.16 - p2.31 */ + +# define LPC17_VALID_SHIFT2H (15) +# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L) + +# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0) +# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1) +# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2) +# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3) +# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4) +# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5) +# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6) +# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7) +# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8) +# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9) +# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10) +# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11) +# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12) +# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13) +# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14) +# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15) +# define LPC17_VALID_NIRQS2H (16) + +# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H) +#else +# define LPC17_NGPIOAIRQS (0) +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */ + diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index 8acd67595..b7dd7ac34 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -12,49 +12,101 @@ choice config ARCH_CHIP_LPC1751 bool "LPC1751" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1752 bool "LPC1752" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1754 bool "LPC1754" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1756 bool "LPC1756" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1758 bool "LPC1758" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1759 bool "LPC1759" + select ARCH_FAMILY_LPC175X config ARCH_CHIP_LPC1764 bool "LPC1764" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1765 bool "LPC1765" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1766 bool "LPC1766" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1767 bool "LPC1767" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1768 bool "LPC1768" + select ARCH_FAMILY_LPC176X config ARCH_CHIP_LPC1769 bool "LPC1769" + select ARCH_FAMILY_LPC176X + +config ARCH_CHIP_LPC1773 + bool "LPC1773" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1774 + bool "LPC1774" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1776 + bool "LPC1776" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1777 + bool "LPC1777" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1778 + bool "LPC1778" + select ARCH_FAMILY_LPC177X + +config ARCH_CHIP_LPC1785 + bool "LPC1785" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1786 + bool "LPC1786" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1787 + bool "LPC1787" + select ARCH_FAMILY_LPC178X + +config ARCH_CHIP_LPC1788 + bool "LPC1788" + select ARCH_FAMILY_LPC178X endchoice config ARCH_FAMILY_LPC175X bool - default y if ARCH_CHIP_LPC1751 || ARCH_CHIP_LPC1752 || ARCH_CHIP_LPC1754 || ARCH_CHIP_LPC1756 || ARCH_CHIP_LPC1758 || ARCH_CHIP_LPC1759 config ARCH_FAMILY_LPC176X bool - default y if ARCH_CHIP_LPC1764 || ARCH_CHIP_LPC1765 || ARCH_CHIP_LPC1766 || ARCH_CHIP_LPC1767 || ARCH_CHIP_LPC1768 || ARCH_CHIP_LPC1769 + +config ARCH_FAMILY_LPC177X + bool + +config ARCH_FAMILY_LPC178X + bool menu "LPC17xx Peripheral Support" diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 982482017..60dda773d 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,159 +41,7 @@ ************************************************************************************/ #include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1767) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 0 /* No USB device controller */ -# define LPC17_NCAN 0 /* No CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1766) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1765) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1764) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1759) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1758) -# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */ -# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */ -# define LPC17_CPUSRAM_SIZE (32*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1756) -# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 2 /* Two CAN controllers */ -# define LPC17_NI2S 1 /* One I2S module */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1754) -# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */ -# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 1 /* One USB host controller */ -# define LPC17_NUSBOTG 1 /* One USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 1 /* One DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1752) -# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */ -# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */ -# define LPC17_CPUSRAM_SIZE (16*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#elif defined(CONFIG_ARCH_CHIP_LPC1751) -# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */ -# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */ -# define LPC17_CPUSRAM_SIZE (8*1024) -# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */ -# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */ -# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */ -# define LPC17_NUSBHOST 0 /* No USB host controller */ -# define LPC17_NUSBOTG 0 /* No USB OTG controller */ -# define LPC17_NUSBDEV 1 /* One USB device controller */ -# define LPC17_NCAN 1 /* One CAN controller */ -# define LPC17_NI2S 0 /* No I2S modules */ -# define LPC17_NDAC 0 /* No DAC module */ -#else -# error "Unsupported LPC17xx chip" -#endif +#include /* Include only the memory map. Other chip hardware files should then include this * file for the proper setup @@ -201,6 +49,10 @@ #include "lpc17_memorymap.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + /* NVIC priority levels *************************************************************/ /* Each priority field holds a priority value, 0-31. The lower the value, the greater * the priority of the corresponding interrupt. The processor implements only diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index 76c446c7d..db6fbe1f8 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_ssp.c * - * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -926,4 +926,3 @@ void ssp_flush(FAR struct spi_dev_s *dev) } #endif /* CONFIG_LPC17_SSP0/1 */ - diff --git a/nuttx/configs/olimex-lpc1766stk/README.txt b/nuttx/configs/olimex-lpc1766stk/README.txt index 13c63d18b..990d1141a 100644 --- a/nuttx/configs/olimex-lpc1766stk/README.txt +++ b/nuttx/configs/olimex-lpc1766stk/README.txt @@ -935,44 +935,37 @@ Where is one of the following: Configuration Notes: - 1. Uses the buildroot toolchaing (CONFIG_LPC17_BUILDROOT=y). But that is - easily reconfigured (see above) - 2. Support for FAT long file names is built-in but can easily be - removed if you are concerned about Microsoft patent issues (see the - section "FAT Long File Names" in the top-level COPYING file). - - CONFIG_FS_FAT=y - CONFIG_FAT_LCNAMES=y <-- Long file name support - CONFIG_FAT_LFN=y - CONFIG_FAT_MAXFNAME=32 - CONFIG_FS_NXFFS=n - CONFIG_FS_ROMFS=n + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: - 3. Includes logic to support a button test (apps/examples/buttons). To - enable the button test, make the following changes in the .config - after configuring: + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. - -CONFIG_ARCH_BUTTONS=n - +CONFIG_ARCH_BUTTONS=y + 2. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: - -CONFIG_GPIO_IRQ=n - -CONFIG_ARCH_IRQBUTTONS=n - +CONFIG_GPIO_IRQ=y - +CONFIG_ARCH_IRQBUTTONS=y + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain - 4. This example supports the CAN loopback test (apps/examples/can) but this - must be manually enabled by selecting: + 3. This configuration supports a network. You may have to change + these settings for your network: - CONFIG_CAN=y : Enable the generic CAN infrastructure - CONFIG_LPC17_CAN1=y : Enable CAN1 - CONFIG_CAN_LOOPBACK=y : Enable CAN loopback mode + CONFIG_NSH_IPADDR=0x0a000002 : IP address: 10.0.0.2 + CONFIG_NSH_DRIPADDR=0x0a000001 : Gateway: 10.0.0.1 + CONFIG_NSH_NETMASK=0xffffff00 : Netmask: 255.255.255.0 - See also apps/examples/README.txt - - Special CAN-only debug options: + 4. This configuration supports the SPI-based MMC/SD card slot. + FAT file system support for FAT long file names is built-in but + can easily be removed if you are concerned about Microsoft patent + issues (see the section "FAT Long File Names" in the top-level + COPYING file). - CONFIG_DEBUG_CAN - CONFIG_CAN_REGDEBUG + CONFIG_FAT_LFN=y : Enables long file name support nx: An example using the NuttX graphics system (NX). This example uses diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig b/nuttx/configs/olimex-lpc1766stk/nsh/appconfig deleted file mode 100644 index b535ca869..000000000 --- a/nuttx/configs/olimex-lpc1766stk/nsh/appconfig +++ /dev/null @@ -1,66 +0,0 @@ -############################################################################ -# configs/olimex-lpc1766stk/nsh/appconfig -# -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# Path to example in apps/examples containing the user_start entry point - -CONFIGURED_APPS += examples/nsh - -# NSH library - -CONFIGURED_APPS += system/readline -CONFIGURED_APPS += nshlib - -# Networking support - -ifeq ($(CONFIG_NET),y) -CONFIGURED_APPS += netutils/uiplib -CONFIGURED_APPS += netutils/dhcpc -CONFIGURED_APPS += netutils/resolv -CONFIGURED_APPS += netutils/tftpc -CONFIGURED_APPS += netutils/webclient -ifeq ($(CONFIG_NSH_TELNET),y) -CONFIGURED_APPS += netutils/telnetd -endif -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CONFIGURED_APPS += examples/buttons -endif - -ifeq ($(CONFIG_CAN),y) -CONFIGURED_APPS += examples/can -endif - - diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index c096cdb0e..0f16933b8 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -1,255 +1,292 @@ -############################################################################ -# configs/olimex-lpc1766stk/nsh/defconfig -# -# Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ -# -# Architecture Selection # -CONFIG_ARCH="arm" +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +CONFIG_ARCH_CHIP_LPC17XX=y +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="lpc17xx" -CONFIG_ARCH_CHIP_LPC17XX=y -CONFIG_ARCH_CHIP_LPC1766=y -CONFIG_ARCH_BOARD="olimex-lpc1766stk" -CONFIG_ARCH_BOARD_LPC1766STK=y +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set CONFIG_BOARD_LOOPSPERMSEC=8111 -CONFIG_DRAM_SIZE=32768 -CONFIG_DRAM_START=0x10000000 -CONFIG_ARCH_IRQPRIO=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_BOOTLOADER=n -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_BUTTONS=n -CONFIG_ARCH_CALIBRATION=n -CONFIG_ARCH_DMA=n +# CONFIG_ARCH_CALIBRATION is not set # -# Identify toolchain and linker options +# ARMV7M Configuration Options # -CONFIG_LPC17_CODESOURCERYW=n -CONFIG_LPC17_CODESOURCERYL=n -CONFIG_LPC17_DEVKITARM=n -CONFIG_LPC17_BUILDROOT=y +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y # -# Individual subsystems can be enabled: +# LPC17xx Configuration Options # +# CONFIG_ARCH_CHIP_LPC1751 is not set +# CONFIG_ARCH_CHIP_LPC1752 is not set +# CONFIG_ARCH_CHIP_LPC1754 is not set +# CONFIG_ARCH_CHIP_LPC1756 is not set +# CONFIG_ARCH_CHIP_LPC1758 is not set +# CONFIG_ARCH_CHIP_LPC1759 is not set +# CONFIG_ARCH_CHIP_LPC1764 is not set +# CONFIG_ARCH_CHIP_LPC1765 is not set +CONFIG_ARCH_CHIP_LPC1766=y +# CONFIG_ARCH_CHIP_LPC1767 is not set +# CONFIG_ARCH_CHIP_LPC1768 is not set +# CONFIG_ARCH_CHIP_LPC1769 is not set +# CONFIG_ARCH_CHIP_LPC1773 is not set +# CONFIG_ARCH_CHIP_LPC1774 is not set +# CONFIG_ARCH_CHIP_LPC1776 is not set +# CONFIG_ARCH_CHIP_LPC1777 is not set +# CONFIG_ARCH_CHIP_LPC1778 is not set +# CONFIG_ARCH_CHIP_LPC1785 is not set +# CONFIG_ARCH_CHIP_LPC1786 is not set +# CONFIG_ARCH_CHIP_LPC1787 is not set +# CONFIG_ARCH_CHIP_LPC1788 is not set +CONFIG_ARCH_FAMILY_LPC176X=y + +# +# LPC17xx Peripheral Support +# +CONFIG_LPC17_MAINOSC=y +CONFIG_LPC17_PLL0=y +CONFIG_LPC17_PLL1=y CONFIG_LPC17_ETHERNET=y -CONFIG_LPC17_USBHOST=n -CONFIG_LPC17_USBOTG=n -CONFIG_LPC17_USBDEV=n +# CONFIG_LPC17_USBHOST is not set +# CONFIG_LPC17_USBDEV is not set CONFIG_LPC17_UART0=y -CONFIG_LPC17_UART1=n -CONFIG_LPC17_UART2=n -CONFIG_LPC17_UART3=n -CONFIG_LPC17_CAN1=n -CONFIG_LPC17_CAN2=n -CONFIG_LPC17_SPI=n -CONFIG_LPC17_SSP0=n +# CONFIG_LPC17_UART1 is not set +# CONFIG_LPC17_UART2 is not set +# CONFIG_LPC17_UART3 is not set +# CONFIG_LPC17_CAN1 is not set +# CONFIG_LPC17_CAN2 is not set +# CONFIG_LPC17_SPI is not set +# CONFIG_LPC17_SSP0 is not set CONFIG_LPC17_SSP1=y -CONFIG_LPC17_I2C0=n -CONFIG_LPC17_I2C1=n -CONFIG_LPC17_I2S=n -CONFIG_LPC17_TMR0=n -CONFIG_LPC17_TMR1=n -CONFIG_LPC17_TMR2=n -CONFIG_LPC17_TMR3=n -CONFIG_LPC17_RIT=n -CONFIG_LPC17_PWM=n -CONFIG_LPC17_MCPWM=n -CONFIG_LPC17_QEI=n -CONFIG_LPC17_RTC=n -CONFIG_LPC17_WDT=n -CONFIG_LPC17_ADC=n -CONFIG_LPC17_DAC=n -CONFIG_LPC17_GPDMA=n +# CONFIG_LPC17_I2C0 is not set +# CONFIG_LPC17_I2C1 is not set +# CONFIG_LPC17_I2C2 is not set +# CONFIG_LPC17_I2S is not set +# CONFIG_LPC17_TMR0 is not set +# CONFIG_LPC17_TMR1 is not set +# CONFIG_LPC17_TMR2 is not set +# CONFIG_LPC17_TMR3 is not set +# CONFIG_LPC17_RIT is not set +# CONFIG_LPC17_PWM is not set +# CONFIG_LPC17_MCPWM is not set +# CONFIG_LPC17_QEI is not set +# CONFIG_LPC17_RTC is not set +# CONFIG_LPC17_WDT is not set +# CONFIG_LPC17_ADC is not set +# CONFIG_LPC17_DAC is not set +# CONFIG_LPC17_GPDMA is not set +# CONFIG_LPC17_FLASH is not set # -# LPC17xx Button interrupt support +# Serial driver options # -CONFIG_GPIO_IRQ=n -CONFIG_ARCH_IRQBUTTONS=n +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_UART0_FLOWCONTROL is not set # -# LPC17xx specific serial device driver settings +# ADC driver options # -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART3_SERIAL_CONSOLE=n - -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART3_TXBUFSIZE=256 - -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART3_RXBUFSIZE=256 -CONFIG_UART0_BAUD=57600 -CONFIG_UART2_BAUD=57600 -CONFIG_UART3_BAUD=57600 -CONFIG_UART1_BAUD=57600 - -CONFIG_UART0_BITS=8 -CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART3_BITS=8 - -CONFIG_UART0_PARITY=0 -CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART3_PARITY=0 +# +# CAN driver options +# +# CONFIG_GPIO_IRQ is not set -CONFIG_UART0_2STOP=0 -CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 -CONFIG_UART3_2STOP=0 +# +# I2C driver options +# # -# LPC17xx specific PHY/Ethernet device driver settings +# Ethernet driver options # -CONFIG_PHY_KS8721=y CONFIG_PHY_AUTONEG=y -CONFIG_PHY_SPEED100=n -CONFIG_PHY_FDUPLEX=y CONFIG_NET_EMACRAM_SIZE=8192 CONFIG_NET_NTXDESC=7 CONFIG_NET_NRXDESC=7 -CONFIG_NET_REGDEBUG=n +CONFIG_NET_PRIORITY=0 +# CONFIG_NET_WOL is not set +# CONFIG_NET_HASH is not set +# CONFIG_NET_MULTICAST is not set # -# General build options +# USB device driver options # -CONFIG_RRLOAD_BINARY=n -CONFIG_INTELHEX_BINARY=y -CONFIG_MOTOROLA_SREC=n -CONFIG_RAW_BINARY=n # -# General OS setup +# USB host driver options # -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DEBUG=n -CONFIG_DEBUG_VERBOSE=n -CONFIG_DEBUG_SYMBOLS=n -CONFIG_DEBUG_NET=n -CONFIG_DEBUG_USB=n -CONFIG_DEBUG_GPIO=n -CONFIG_DEBUG_CAN=n -CONFIG_MM_REGIONS=2 -CONFIG_ARCH_LOWPUTC=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=n -CONFIG_TASK_NAME_SIZE=0 -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=30 -CONFIG_GREGORIAN_TIME=n -CONFIG_JULIAN_TIME=n -CONFIG_DEV_CONSOLE=y -CONFIG_DEV_LOWCONSOLE=n -CONFIG_MUTEX_TYPES=n -CONFIG_PRIORITY_INHERITANCE=n -CONFIG_SEM_PREALLOCHOLDERS=0 -CONFIG_SEM_NNESTPRIO=0 -CONFIG_FDCLONE_DISABLE=n -CONFIG_FDCLONE_STDIO=n -CONFIG_SDCLONE_DISABLE=y -CONFIG_SCHED_WORKQUEUE=n -CONFIG_SCHED_WORKPRIORITY=192 -CONFIG_SCHED_WORKPERIOD=50000 -CONFIG_SCHED_WORKSTACKSIZE=1024 -CONFIG_SIG_SIGWORK=17 -CONFIG_SCHED_WAITPID=y -CONFIG_SCHED_ATEXIT=n # -# Settings for NXFLAT +# Architecture Options # -CONFIG_NXFLAT=y -CONFIG_NXFLAT_DUMPBUFFER=n -CONFIG_SYMTAB_ORDEREDBYNAME=y +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set # -# The following can be used to disable categories of -# APIs supported by the OS. If the compiler supports -# weak functions, then it should not be necessary to -# disable functions unless you want to restrict usage -# of those APIs. +# Board Settings # -# There are certain dependency relationships in these -# features. +CONFIG_DRAM_START=0x10000000 +CONFIG_DRAM_SIZE=32768 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + # -# o mq_notify logic depends on signals to awaken tasks -# waiting for queues to become full or empty. -# o pthread_condtimedwait() depends on signals to wake -# up waiting tasks. +# Boot options # -CONFIG_DISABLE_CLOCK=n -CONFIG_DISABLE_POSIX_TIMERS=n -CONFIG_DISABLE_PTHREAD=n -CONFIG_DISABLE_SIGNALS=n -CONFIG_DISABLE_MQUEUE=n -CONFIG_DISABLE_MOUNTPOINT=n -CONFIG_DISABLE_ENVIRON=n -CONFIG_DISABLE_POLL=y +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set # -# Misc libc settings +# Board Selection # -CONFIG_NOPRINTF_FIELDWIDTH=n +CONFIG_ARCH_BOARD_LPC1766STK=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-lpc1766stk" # -# Allow for architecture optimized implementations +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 + # -# The architecture can provide optimized versions of the -# following to improve system performance +# Board-Specific Options # -CONFIG_ARCH_MEMCPY=n -CONFIG_ARCH_MEMCMP=n -CONFIG_ARCH_MEMMOVE=n -CONFIG_ARCH_MEMSET=n -CONFIG_ARCH_STRCMP=n -CONFIG_ARCH_STRCPY=n -CONFIG_ARCH_STRNCPY=n -CONFIG_ARCH_STRLEN=n -CONFIG_ARCH_STRNLEN=n -CONFIG_ARCH_BZERO=n + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=30 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +CONFIG_SCHED_WAITPID=y +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_DISABLE_ENVIRON is not set +CONFIG_DISABLE_POLL=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 # # Sizes of configurable things (0 disables) @@ -260,9 +297,6 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -CONFIG_STDIO_BUFFER_SIZE=256 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_MQ_MAXMSGSIZE=32 CONFIG_MAX_WDOGPARMS=2 @@ -270,263 +304,426 @@ CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_TIMERS=4 # -# Filesystem configuration +# Stack and heap information # -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -CONFIG_FS_NXFFS=n -CONFIG_FS_ROMFS=n +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # -# Maintain legacy build behavior (revisit) -# - +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_OWNBUS is not set +# CONFIG_SPI_EXCHANGE is not set +# CONFIG_SPI_CMDDATA is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_HAVECARDDETECT is not set CONFIG_MMCSD_SPI=y -CONFIG_MTD=y +CONFIG_MMCSD_SPICLOCK=12500000 +# CONFIG_MMCSD_SDIO is not set +# CONFIG_MTD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_NET_SLIP is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set # -# SPI-based MMC/SD driver +# UART0 Configuration # -CONFIG_MMCSD_NSLOTS=1 -CONFIG_MMCSD_READONLY=n -CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=57600 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set # -# Block driver buffering +# System Logging Device Options # -CONFIG_FS_READAHEAD=n -CONFIG_FS_WRITEBUFFER=n # -# SDIO-based MMC/SD driver +# System Logging # -CONFIG_SDIO_DMA=n -CONFIG_MMCSD_MMCSUPPORT=n -CONFIG_MMCSD_HAVECARDDETECT=n +# CONFIG_RAMLOG is not set # -# TCP/IP and UDP support via uIP +# Networking Support # CONFIG_NET=y -CONFIG_NET_IPv6=n +CONFIG_ARCH_HAVE_PHY=y +CONFIG_PHY_KS8721=y +# CONFIG_PHY_DP83848C is not set +# CONFIG_PHY_LAN8720 is not set +# CONFIG_PHY_DM9161 is not set +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_MULTIBUFFER is not set +# CONFIG_NET_IPv6 is not set CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 CONFIG_NET_SOCKOPTS=y CONFIG_NET_BUFSIZE=562 +# CONFIG_NET_TCPURGDATA is not set CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=8 -CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 -CONFIG_NET_TCPBACKLOG=n CONFIG_NET_MAX_LISTENPORTS=8 +CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 +CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 +CONFIG_NET_TCP_RECVDELAY=0 +# CONFIG_NET_TCPBACKLOG is not set CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y -#CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_UDP_CONNS=8 +# CONFIG_NET_BROADCAST is not set CONFIG_NET_ICMP=y CONFIG_NET_ICMP_PING=y -#CONFIG_NET_PINGADDRCONF=0 -CONFIG_NET_STATISTICS=n -#CONFIG_NET_RECEIVE_WINDOW= -#CONFIG_NET_ARPTAB_SIZE=8 -CONFIG_NET_BROADCAST=n +# CONFIG_NET_PINGADDRCONF is not set +# CONFIG_NET_IGMP is not set +# CONFIG_NET_STATISTICS is not set +CONFIG_NET_RECEIVE_WINDOW=562 +CONFIG_NET_ARPTAB_SIZE=16 +# CONFIG_NET_ARP_IPIN is not set # -# UIP Network Utilities +# File Systems # -CONFIG_NET_DHCP_LIGHT=n -CONFIG_NET_RESOLV_ENTRIES=4 # -# CAN device driver settings +# File system configuration # -CONFIG_CAN=n -CONFIG_CAN_EXTID=n -#CONFIG_CAN_FIFOSIZE -#CONFIG_CAN_NPENDINGRTR -CONFIG_CAN_LOOPBACK=n -CONFIG_CAN_REGDEBUG=n -CONFIG_CAN1_BAUD=700000 -CONFIG_CAN2_BAUD=700000 +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_BINFS is not set # -# USB Device Configuration +# System Logging # -CONFIG_USBDEV=n -CONFIG_USBDEV_ISOCHRONOUS=n -CONFIG_USBDEV_DUALSPEED=n -CONFIG_USBDEV_SELFPOWERED=y -CONFIG_USBDEV_REMOTEWAKEUP=n -CONFIG_USBDEV_MAXPOWER=100 -CONFIG_USBDEV_TRACE=n -CONFIG_USBDEV_TRACE_NRECORDS=128 +# CONFIG_SYSLOG is not set # -# USB Host Configuration +# Graphics Support # -CONFIG_USBHOST=n -CONFIG_USBHOST_NPREALLOC=0 -CONFIG_USBHOST_BULK_DISABLE=n -CONFIG_USBHOST_INT_DISABLE=y -CONFIG_USBHOST_ISOC_DISABLE=y +# CONFIG_NX is not set # -# LPC17xx USB Device Configuration +# Memory Management # -CONFIG_LPC17_USBDEV_FRAME_INTERRUPT=n -CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT=n -CONFIG_LPC17_USBDEV_DMA=n -CONFIG_LPC17_USBDEV_NDMADESCRIPTORS=0 -CONFIG_LPC17_USBDEV_DMAINTMASK=0 +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set # -# LPC17xx USB Host Configuration +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +CONFIG_NXFLAT=y +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +CONFIG_PIC=y +CONFIG_SYMTAB_ORDEREDBYNAME=y + # -# OHCI RAM layout: +# Library Routines # -CONFIG_USBHOST_OHCIRAM_SIZE=1536 -CONFIG_USBHOST_NEDS=2 -CONFIG_USBHOST_NTDS=3 -CONFIG_USBHOST_TDBUFFERS=3 -CONFIG_USBHOST_TDBUFSIZE=128 -CONFIG_USBHOST_IOBUFSIZE=512 # -# USB Serial Device Configuration +# Standard C Library Options # -CONFIG_PL2303=n -CONFIG_PL2303_EPINTIN=1 -CONFIG_PL2303_EPBULKOUT=2 -CONFIG_PL2303_EPBULKIN=5 -CONFIG_PL2303_NWRREQS=4 -CONFIG_PL2303_NRDREQS=4 -CONFIG_PL2303_VENDORID=0x067b -CONFIG_PL2303_PRODUCTID=0x2303 -CONFIG_PL2303_VENDORSTR="Nuttx" -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # -# USB Storage Device Configuration +# Non-standard Helper Functions # -CONFIG_USBMSC=n -CONFIG_USBMSC_EP0MAXPACKET=64 -CONFIG_USBMSC_EPBULKOUT=2 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_VENDORID=0x584e -CONFIG_USBMSC_VENDORSTR="NuttX" -CONFIG_USBMSC_PRODUCTID=0x5342 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_VERSIONNO=0x0399 -CONFIG_USBMSC_REMOVABLE=y +# CONFIG_LIB_KBDCODEC is not set # -# Settings for examples/uip +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration # -CONFIG_EXAMPLES_UIP_IPADDR=0x0a000002 -CONFIG_EXAMPLES_UIP_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_UIP_NETMASK=0xffffff00 -CONFIG_EXAMPLES_UIP_DHCPC=n # -# Settings for examples/nettest +# Built-In Applications # -CONFIG_EXAMPLES_NETTEST_SERVER=n -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=n -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002 -CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001 -CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 -CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # -# Settings for examples/ostest +# Examples # -CONFIG_EXAMPLES_OSTEST_LOOPS=1 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set # -# Settings for examples/buttons +# Interpreters # -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=7 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_BUTTONS_NAME0="BUT1" -CONFIG_EXAMPLES_BUTTONS_NAME1="BUT2" -CONFIG_EXAMPLES_BUTTONS_NAME2="WAKE-UP" -CONFIG_EXAMPLES_BUTTONS_NAME3="CENTER" -CONFIG_EXAMPLES_BUTTONS_NAME4="UP" -CONFIG_EXAMPLES_BUTTONS_NAME5="DOWN" -CONFIG_EXAMPLES_BUTTONS_NAME6="LEFT" -CONFIG_EXAMPLES_BUTTONS_NAME7="RIGHT" # -# Settings for apps/nshlib +# Interpreters # -CONFIG_BUILTIN=y +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_RESOLV=y +CONFIG_NET_RESOLV_ENTRIES=8 +CONFIG_NET_RESOLV_MAXRESPONSE=96 +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +# CONFIG_NETUTILS_THTTPD is not set +CONFIG_NETUTILS_UIPLIB=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_DISCOVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_STRERROR=n CONFIG_NSH_LINELEN=64 CONFIG_NSH_NESTDEPTH=3 -CONFIG_NSH_DISABLESCRIPT=n -CONFIG_NSH_DISABLEBG=n -CONFIG_NSH_ROMFSETC=n +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_CONSOLE=y -CONFIG_NSH_TELNET=y +# CONFIG_NSH_CONDEV is not set CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_TELNET=y +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 CONFIG_NSH_IOBUFFER_SIZE=512 -CONFIG_NSH_DHCPC=n -CONFIG_NSH_NOMAC=y +# CONFIG_NSH_TELNET_LOGIN is not set CONFIG_NSH_IPADDR=0x0a000002 CONFIG_NSH_DRIPADDR=0x0a000001 CONFIG_NSH_NETMASK=0xffffff00 -CONFIG_NSH_ROMFSMOUNTPT="/etc" -CONFIG_NSH_INITSCRIPT="init.d/rcS" -CONFIG_NSH_ROMFSDEVNO=0 -CONFIG_NSH_ROMFSSECTSIZE=64 -CONFIG_NSH_FATDEVNO=1 -CONFIG_NSH_FATSECTSIZE=512 -CONFIG_NSH_FATNSECTORS=1024 -CONFIG_NSH_FATMOUNTPT="/tmp" +CONFIG_NSH_NOMAC=y +CONFIG_NSH_MAX_ROUNDTRIP=20 # -# Architecture-specific NSH options +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons # -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDMINOR=0 # -# Settings for examples/usbserial +# Custom Free Memory Command # -CONFIG_EXAMPLES_USBSERIAL_INONLY=n -CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n -CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n -CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n +# CONFIG_SYSTEM_FREE is not set -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n +# +# I2C tool +# # -# Stack and heap information +# FLASH Program Installation # -CONFIG_BOOT_RUNFROMFLASH=n -CONFIG_BOOT_COPYTORAM=n -CONFIG_CUSTOM_STACK=n -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -CONFIG_HEAP_BASE= -CONFIG_HEAP_SIZE= +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/drivers/mmcsd/Kconfig b/nuttx/drivers/mmcsd/Kconfig index 5cdc23bcf..2d9a04bbb 100644 --- a/nuttx/drivers/mmcsd/Kconfig +++ b/nuttx/drivers/mmcsd/Kconfig @@ -53,7 +53,7 @@ config MMCSD_SPICLOCK config MMCSD_SDIO bool "MMC/SD sdio transfer support" - default y + default n if MMCSD_SDIO config SDIO_DMA diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile index 73c67239e..38d3e047f 100644 --- a/nuttx/sched/Makefile +++ b/nuttx/sched/Makefile @@ -35,166 +35,172 @@ -include $(TOPDIR)/Make.defs -ASRCS = -AOBJS = $(ASRCS:.S=$(OBJEXT)) - -MISC_SRCS = os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c \ - sched_garbage.c sched_setupstreams.c sched_getfiles.c sched_getsockets.c \ - sched_getstreams.c sched_setupidlefiles.c sched_setuptaskfiles.c \ - sched_setuppthreadfiles.c sched_releasefiles.c - -TSK_SRCS = prctl.c task_create.c task_init.c task_setup.c task_activate.c \ - task_start.c task_delete.c task_deletecurrent.c task_exithook.c \ - task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c \ - sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c \ - sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c \ - sched_verifytcb.c sched_releasetcb.c task_posixspawn.c - -SCHED_SRCS = sched_setparam.c sched_setpriority.c sched_getparam.c \ - sched_setscheduler.c sched_getscheduler.c \ - sched_yield.c sched_rrgetinterval.c sched_foreach.c \ - sched_lock.c sched_unlock.c sched_lockcount.c sched_self.c +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +MISC_SRCS = os_start.c os_bringup.c errno_getptr.c errno_get.c errno_set.c +MISC_SRCS += sched_garbage.c sched_setupstreams.c sched_getfiles.c sched_getsockets.c +MISC_SRCS += sched_getstreams.c sched_setupidlefiles.c sched_setuptaskfiles.c +MISC_SRCS += sched_setuppthreadfiles.c sched_releasefiles.c + +TSK_SRCS = prctl.c task_create.c task_init.c task_setup.c task_activate.c +TSK_SRCS += task_start.c task_delete.c task_deletecurrent.c task_exithook.c +TSK_SRCS += task_restart.c task_vfork.c exit.c getpid.c sched_addreadytorun.c +TSK_SRCS += sched_removereadytorun.c sched_addprioritized.c sched_mergepending.c +TSK_SRCS += sched_addblocked.c sched_removeblocked.c sched_free.c sched_gettcb.c +TSK_SRCS += sched_verifytcb.c sched_releasetcb.c + +ifneq ($(CONFIG_BINFMT_DISABLE),y) +ifeq ($(CONFIG_LIBC_EXECFUNCS),y) +TSK_SRCS += task_posixspawn.c +endif +endif + +SCHED_SRCS = sched_setparam.c sched_setpriority.c sched_getparam.c +SCHED_SRCS += sched_setscheduler.c sched_getscheduler.c +SCHED_SRCS += sched_yield.c sched_rrgetinterval.c sched_foreach.c +SCHED_SRCS += sched_lock.c sched_unlock.c sched_lockcount.c sched_self.c ifeq ($(CONFIG_SCHED_ATEXIT),y) -SCHED_SRCS += atexit.c +SCHED_SRCS += atexit.c endif ifeq ($(CONFIG_SCHED_ONEXIT),y) -SCHED_SRCS += on_exit.c +SCHED_SRCS += on_exit.c endif ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -SCHED_SRCS += sched_reprioritize.c +SCHED_SRCS += sched_reprioritize.c endif ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) -SCHED_SRCS += task_reparent.c +SCHED_SRCS += task_reparent.c endif ifeq ($(CONFIG_SCHED_WAITPID),y) -SCHED_SRCS += sched_waitpid.c +SCHED_SRCS += sched_waitpid.c ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) -SCHED_SRCS += sched_waitid.c sched_wait.c +SCHED_SRCS += sched_waitid.c sched_wait.c endif endif -ENV_SRCS = env_getenvironptr.c env_dup.c env_share.c env_release.c \ - env_findvar.c env_removevar.c \ - env_clearenv.c env_getenv.c env_putenv.c env_setenv.c env_unsetenv.c +ENV_SRCS = env_getenvironptr.c env_dup.c env_share.c env_release.c +ENV_SRCS += env_findvar.c env_removevar.c +ENV_SRCS += env_clearenv.c env_getenv.c env_putenv.c env_setenv.c env_unsetenv.c -WDOG_SRCS = wd_initialize.c wd_create.c wd_start.c wd_cancel.c wd_delete.c \ - wd_gettime.c +WDOG_SRCS = wd_initialize.c wd_create.c wd_start.c wd_cancel.c wd_delete.c +WDOG_SRCS += wd_gettime.c -TIME_SRCS = sched_processtimer.c +TIME_SRCS = sched_processtimer.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) -TIME_SRCS += sleep.c usleep.c +TIME_SRCS += sleep.c usleep.c endif -CLOCK_SRCS = clock_initialize.c clock_settime.c clock_gettime.c clock_getres.c \ - clock_time2ticks.c clock_abstime2ticks.c clock_ticks2time.c \ - clock_gettimeofday.c clock_systimer.c +CLOCK_SRCS = clock_initialize.c clock_settime.c clock_gettime.c clock_getres.c +CLOCK_SRCS += clock_time2ticks.c clock_abstime2ticks.c clock_ticks2time.c +CLOCK_SRCS += clock_gettimeofday.c clock_systimer.c -SIGNAL_SRCS = sig_initialize.c \ - sig_action.c sig_procmask.c sig_pending.c sig_suspend.c \ - sig_kill.c sig_queue.c sig_waitinfo.c sig_timedwait.c \ - sig_findaction.c sig_allocatependingsigaction.c \ - sig_releasependingsigaction.c sig_unmaskpendingsignal.c \ - sig_removependingsignal.c sig_releasependingsignal.c sig_lowest.c \ - sig_mqnotempty.c sig_cleanup.c sig_received.c sig_deliver.c pause.c +SIGNAL_SRCS = sig_initialize.c +SIGNAL_SRCS += sig_action.c sig_procmask.c sig_pending.c sig_suspend.c +SIGNAL_SRCS += sig_kill.c sig_queue.c sig_waitinfo.c sig_timedwait.c +SIGNAL_SRCS += sig_findaction.c sig_allocatependingsigaction.c +SIGNAL_SRCS += sig_releasependingsigaction.c sig_unmaskpendingsignal.c +SIGNAL_SRCS += sig_removependingsignal.c sig_releasependingsignal.c sig_lowest.c +SIGNAL_SRCS += sig_mqnotempty.c sig_cleanup.c sig_received.c sig_deliver.c pause.c -MQUEUE_SRCS = mq_open.c mq_close.c mq_unlink.c mq_send.c mq_timedsend.c\ - mq_sndinternal.c mq_receive.c mq_timedreceive.c mq_rcvinternal.c \ - mq_initialize.c mq_descreate.c mq_findnamed.c mq_msgfree.c mq_msgqfree.c +MQUEUE_SRCS = mq_open.c mq_close.c mq_unlink.c mq_send.c mq_timedsend.c +MQUEUE_SRCS += mq_sndinternal.c mq_receive.c mq_timedreceive.c mq_rcvinternal.c +MQUEUE_SRCS += mq_initialize.c mq_descreate.c mq_findnamed.c mq_msgfree.c mq_msgqfree.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) -MQUEUE_SRCS += mq_waitirq.c +MQUEUE_SRCS += mq_waitirq.c endif ifneq ($(CONFIG_DISABLE_SIGNALS),y) -MQUEUE_SRCS += mq_notify.c +MQUEUE_SRCS += mq_notify.c endif -PTHREAD_SRCS = pthread_create.c pthread_exit.c pthread_join.c pthread_detach.c \ - pthread_yield.c pthread_getschedparam.c pthread_setschedparam.c \ - pthread_mutexinit.c pthread_mutexdestroy.c \ - pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c \ - pthread_condinit.c pthread_conddestroy.c \ - pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c \ - pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c \ - pthread_cancel.c pthread_setcancelstate.c \ - pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c \ - pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c \ - pthread_removejoininfo.c pthread_once.c pthread_setschedprio.c +PTHREAD_SRCS = pthread_create.c pthread_exit.c pthread_join.c pthread_detach.c +PTHREAD_SRCS += pthread_yield.c pthread_getschedparam.c pthread_setschedparam.c +PTHREAD_SRCS += pthread_mutexinit.c pthread_mutexdestroy.c +PTHREAD_SRCS += pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c +PTHREAD_SRCS += pthread_condinit.c pthread_conddestroy.c +PTHREAD_SRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c +PTHREAD_SRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c +PTHREAD_SRCS += pthread_cancel.c pthread_setcancelstate.c +PTHREAD_SRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c +PTHREAD_SRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c +PTHREAD_SRCS += pthread_removejoininfo.c pthread_once.c pthread_setschedprio.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) -PTHREAD_SRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c +PTHREAD_SRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c endif -SEM_SRCS = sem_initialize.c sem_destroy.c sem_open.c sem_close.c sem_unlink.c \ - sem_wait.c sem_trywait.c sem_timedwait.c sem_post.c sem_findnamed.c +SEM_SRCS = sem_initialize.c sem_destroy.c sem_open.c sem_close.c sem_unlink.c +SEM_SRCS += sem_wait.c sem_trywait.c sem_timedwait.c sem_post.c sem_findnamed.c ifneq ($(CONFIG_DISABLE_SIGNALS),y) -SEM_SRCS += sem_waitirq.c +SEM_SRCS += sem_waitirq.c endif ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -SEM_SRCS += sem_holder.c +SEM_SRCS += sem_holder.c endif ifneq ($(CONFIG_DISABLE_POSIX_TIMERS),y) -TIMER_SRCS = timer_initialize.c timer_create.c timer_delete.c timer_getoverrun.c \ - timer_gettime.c timer_settime.c timer_release.c +TIMER_SRCS += timer_initialize.c timer_create.c timer_delete.c timer_getoverrun.c +TIMER_SRCS += timer_gettime.c timer_settime.c timer_release.c endif ifeq ($(CONFIG_SCHED_WORKQUEUE),y) -WORK_SRCS = work_thread.c work_queue.c work_cancel.c work_signal.c +WORK_SRCS = work_thread.c work_queue.c work_cancel.c work_signal.c endif ifeq ($(CONFIG_PAGING),y) -PGFILL_SRCS = pg_miss.c pg_worker.c +PGFILL_SRCS = pg_miss.c pg_worker.c endif -IRQ_SRCS = irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c +IRQ_SRCS = irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c -KMM_SRCS = kmm_initialize.c kmm_addregion.c kmm_semaphore.c \ - kmm_kmalloc.c kmm_kzalloc.c kmm_krealloc.c kmm_kfree.c +KMM_SRCS = kmm_initialize.c kmm_addregion.c kmm_semaphore.c +KMM_SRCS = kmm_kmalloc.c kmm_kzalloc.c kmm_krealloc.c kmm_kfree.c -CSRCS = $(MISC_SRCS) $(TSK_SRCS) $(SCHED_SRCS) $(WDOG_SRCS) $(TIME_SRCS) \ - $(SEM_SRCS) $(TIMER_SRCS) $(WORK_SRCS) $(PGFILL_SRCS) $(IRQ_SRCS) +CSRCS = $(MISC_SRCS) $(TSK_SRCS) $(SCHED_SRCS) $(WDOG_SRCS) $(TIME_SRCS) \ + $(SEM_SRCS) $(TIMER_SRCS) $(WORK_SRCS) $(PGFILL_SRCS) $(IRQ_SRCS) ifneq ($(CONFIG_DISABLE_CLOCK),y) -CSRCS += $(CLOCK_SRCS) +CSRCS += $(CLOCK_SRCS) endif ifneq ($(CONFIG_DISABLE_PTHREAD),y) -CSRCS += $(PTHREAD_SRCS) +CSRCS += $(PTHREAD_SRCS) endif ifneq ($(CONFIG_DISABLE_SIGNALS),y) -CSRCS += $(SIGNAL_SRCS) +CSRCS += $(SIGNAL_SRCS) endif ifneq ($(CONFIG_DISABLE_MQUEUE),y) -CSRCS += $(MQUEUE_SRCS) +CSRCS += $(MQUEUE_SRCS) endif ifneq ($(CONFIG_DISABLE_ENVIRON),y) -CSRCS += $(ENV_SRCS) +CSRCS += $(ENV_SRCS) endif ifeq ($(CONFIG_NUTTX_KERNEL),y) -CSRCS += $(KMM_SRCS) +CSRCS += $(KMM_SRCS) endif -COBJS = $(CSRCS:.c=$(OBJEXT)) +COBJS = $(CSRCS:.c=$(OBJEXT)) -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) -BIN = libsched$(LIBEXT) +BIN = libsched$(LIBEXT) -all: $(BIN) +all: $(BIN) .PHONY: context depend clean distclean $(AOBJS): %$(OBJEXT): %.S diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h index f21d9654f..95b42c7ae 100644 --- a/nuttx/sched/os_internal.h +++ b/nuttx/sched/os_internal.h @@ -269,7 +269,7 @@ int task_argsetup(FAR _TCB *tcb, FAR const char *name, FAR const char *argv[]); void task_exithook(FAR _TCB *tcb, int status); int task_deletecurrent(void); #ifdef CONFIG_SCHED_HAVE_PARENT -int task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid); +int task_reparent(pid_t ppid, pid_t chpid); #endif #ifndef CONFIG_CUSTOM_STACK int kernel_thread(FAR const char *name, int priority, int stack_size, diff --git a/nuttx/sched/task_posixspawn.c b/nuttx/sched/task_posixspawn.c index 4201e759b..7bb9c9a4d 100644 --- a/nuttx/sched/task_posixspawn.c +++ b/nuttx/sched/task_posixspawn.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -431,7 +432,7 @@ static int spawn_proxy(int argc, char *argv[]) * What should we do in the event of a failure? */ - int tmp = task_reparent(0, 0, *g_ps_parms.pid); + int tmp = task_reparent(0, *g_ps_parms.pid); if (tmp < 0) { sdbg("ERROR: task_reparent() failed: %d\n", tmp); diff --git a/nuttx/sched/task_reparent.c b/nuttx/sched/task_reparent.c index 9daa0743b..244825f80 100644 --- a/nuttx/sched/task_reparent.c +++ b/nuttx/sched/task_reparent.c @@ -60,8 +60,8 @@ * Change the parent of a task. * * Parameters: - * oldpid - PID of the old parent task (0 if this task) - * newpid - PID ot the new parent task (0 for the parent of this task) + * ppid - PID of the new parent task (0 for grandparent, i.e. the parent + * of the current parent task) * chpid - PID of the child to be reparented. * * Return Value: @@ -69,72 +69,69 @@ * *****************************************************************************/ -int task_reparent(pid_t oldpid, pid_t newpid, pid_t chpid) +int task_reparent(pid_t ppid, pid_t chpid) { - _TCB *oldtcb; - _TCB *newtcb; + _TCB *ptcb; _TCB *chtcb; + _TCB *otcb; + pid_t opid; irqstate_t flags; int ret; - /* If oldpid is zero, then we are parent task. */ + /* Disable interrupts so that nothing can change in the relatinoship of + * the three task: Child, current parent, and new parent. + */ - if (oldpid == 0) - { - oldpid = getpid(); - } + flags = irqsave(); - /* Get the current parent task's TCB */ + /* Get the child tasks TCB (chtcb) */ - oldtcb = sched_gettcb(oldpid); - if (!oldtcb) + chtcb = sched_gettcb(chpid); + if (!chtcb) { - return -ESRCH; + ret = -ECHILD; + goto errout_with_ints; } - /* Disable interrupts so that nothing can change from this point */ + /* Get the PID of the child task's parent (opid) */ - flags = irqsave(); + opid = chtcb->parent; - /* If newpid is zero, then new is the parent of oldpid. */ + /* Get the TCB of the child task's parent (otcb) */ - if (newpid == 0) - { - newpid = oldtcb->parent; - } - - /* Get the new parent task's TCB */ - - newtcb = sched_gettcb(newpid); - if (!newtcb) + otcb = sched_gettcb(opid); + if (!otcb) { ret = -ESRCH; goto errout_with_ints; } - /* Get the child tasks TCB */ + /* If new parent task's PID (ppid) is zero, then new parent is the + * grandparent will be the new parent, i.e., the parent of the current + * parent task. + */ - chtcb = sched_gettcb(chpid); - if (!chtcb) + if (ppid == 0) { - ret = -ECHILD; - goto errout_with_ints; + ppid = otcb->parent; } + + /* Get the new parent task's TCB (ptcb) */ - /* Verify that oldpid is the parent of chpid */ - - if (chtcb->parent != oldpid) + ptcb = sched_gettcb(ppid); + if (!ptcb) { - ret = -ECHILD; + ret = -ESRCH; goto errout_with_ints; } - /* Okay, reparent the child */ + /* Then reparent the child */ + + DEBUGASSERT(otcb->nchildren > 0); - DEBUGASSERT(oldtcb->nchildren > 0); - chtcb->parent = newpid; - oldtcb->nchildren--; - newtcb->nchildren++; + chtcb->parent = ppid; /* The task specified by ppid is the new parent */ + otcb->nchildren--; /* The orignal parent now has one few children */ + ptcb->nchildren++; /* The new parent has one additional child */ ret = OK; errout_with_ints: -- cgit v1.2.3 From 40041c8792340b6148338cb3e3a28266fdff7373 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 19:16:44 +0000 Subject: Refactor all lpc17xx header files (more like STM32 header file structure now) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5534 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc17xx/irq.h | 2 +- nuttx/arch/arm/src/lpc17xx/chip.h | 4 +- .../arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h | 136 ++++ .../arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h | 234 ++++++ .../arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h | 64 ++ .../arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h | 72 ++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_adc.h | 180 +++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h | 510 ++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_dac.h | 97 +++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h | 597 ++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h | 417 ++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h | 293 +++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2c.h | 208 +++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2s.h | 62 ++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h | 280 +++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h | 71 ++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h | 71 ++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h | 635 +++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_pwm.h | 63 ++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h | 190 +++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_rit.h | 92 +++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h | 270 +++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_spi.h | 141 ++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_ssp.h | 174 +++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h | 494 ++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_timer.h | 250 ++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h | 339 ++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h | 778 +++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h | 108 +++ nuttx/arch/arm/src/lpc17xx/lpc17_adc.c | 5 +- nuttx/arch/arm/src/lpc17xx/lpc17_adc.h | 268 +++---- nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_can.c | 5 +- nuttx/arch/arm/src/lpc17xx/lpc17_can.h | 504 ++---------- nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c | 4 +- nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.h | 84 ++ nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.h | 84 ++ nuttx/arch/arm/src/lpc17xx/lpc17_dac.c | 5 +- nuttx/arch/arm/src/lpc17xx/lpc17_dac.h | 65 +- nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c | 7 +- nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h | 550 +------------ nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c | 4 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h | 527 ++++--------- nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c | 11 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h | 284 +++---- nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c | 3 +- nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c | 9 +- nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h | 150 +--- nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h | 380 ++++----- nuttx/arch/arm/src/lpc17xx/lpc17_internal.h | 854 --------------------- nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 4 +- nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c | 8 +- nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.h | 84 ++ nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h | 280 ------- nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h | 136 ---- nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h | 635 --------------- nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_qei.h | 132 +--- nuttx/arch/arm/src/lpc17xx/lpc17_rit.h | 34 +- nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h | 332 ++------ nuttx/arch/arm/src/lpc17xx/lpc17_serial.c | 6 +- nuttx/arch/arm/src/lpc17xx/lpc17_serial.h | 6 +- nuttx/arch/arm/src/lpc17xx/lpc17_spi.c | 5 +- nuttx/arch/arm/src/lpc17xx/lpc17_spi.h | 173 +++-- nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c | 5 +- nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h | 347 +++++---- nuttx/arch/arm/src/lpc17xx/lpc17_start.c | 3 +- nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h | 494 ------------ nuttx/arch/arm/src/lpc17xx/lpc17_timer.h | 312 ++------ nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c | 2 +- nuttx/arch/arm/src/lpc17xx/lpc17_uart.h | 339 -------- nuttx/arch/arm/src/lpc17xx/lpc17_usb.h | 778 ------------------- nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c | 9 +- nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c | 8 +- nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h | 50 +- nuttx/configs/lincoln60/src/up_boot.c | 1 - nuttx/configs/lincoln60/src/up_buttons.c | 4 +- nuttx/configs/lincoln60/src/up_leds.c | 4 +- .../lpcxpresso-lpc1768/src/lpcxpresso_internal.h | 4 +- nuttx/configs/lpcxpresso-lpc1768/src/up_boot.c | 2 +- nuttx/configs/lpcxpresso-lpc1768/src/up_leds.c | 4 +- nuttx/configs/lpcxpresso-lpc1768/src/up_oled.c | 5 +- nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c | 13 +- nuttx/configs/mbed/src/up_boot.c | 2 +- nuttx/configs/mbed/src/up_leds.c | 4 +- nuttx/configs/nucleus2g/src/up_boot.c | 2 +- nuttx/configs/nucleus2g/src/up_leds.c | 4 +- nuttx/configs/nucleus2g/src/up_outputs.c | 4 +- nuttx/configs/nucleus2g/src/up_ssp.c | 9 +- nuttx/configs/olimex-lpc1766stk/src/up_boot.c | 2 +- nuttx/configs/olimex-lpc1766stk/src/up_buttons.c | 2 +- nuttx/configs/olimex-lpc1766stk/src/up_can.c | 1 - nuttx/configs/olimex-lpc1766stk/src/up_lcd.c | 2 +- nuttx/configs/olimex-lpc1766stk/src/up_leds.c | 2 +- nuttx/configs/olimex-lpc1766stk/src/up_nsh.c | 4 +- nuttx/configs/olimex-lpc1766stk/src/up_ssp.c | 3 +- nuttx/configs/olimex-lpc1766stk/src/up_usbmsc.c | 2 +- 101 files changed, 8266 insertions(+), 6643 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_adc.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_dac.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2c.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2s.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_pwm.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_rit.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_spi.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_ssp.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_timer.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h create mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.h create mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_internal.h create mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_uart.h delete mode 100644 nuttx/arch/arm/src/lpc17xx/lpc17_usb.h diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h index c058f6367..91875804c 100644 --- a/nuttx/arch/arm/include/lpc17xx/irq.h +++ b/nuttx/arch/arm/include/lpc17xx/irq.h @@ -114,7 +114,7 @@ extern "C" #ifdef __cplusplus } #endif -#endif __ASSEMBLY__ +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index 60dda773d..d9b3998fe 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/chip.h * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,7 +47,7 @@ * file for the proper setup */ -#include "lpc17_memorymap.h" +#include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h new file mode 100644 index 000000000..094a47788 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h @@ -0,0 +1,136 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc176x_memorymap.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ +# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ +# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ +#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ +#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ +# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ +#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_SCS_BASE 0xe000e000 +#define LPC17_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ + /* -0x40017fff: Reserved */ +#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ +#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ +#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ + /* -0x400a7fff: Reserved */ +#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ + /* -0x400affff: Reserved */ +#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ + /* -0x400b7fff: Reserved */ +#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ + /* -0x400fbfff: Reserved */ +#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ +#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ +#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h new file mode 100644 index 000000000..fb0c7c700 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h @@ -0,0 +1,234 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lp176x_pinconfig.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* GPIO pin definitions *************************************************************/ +/* NOTE that functions have a alternate pins that can be selected. These alternates + * are identified with a numerica suffix like _1, _2, or _3. Your board.h file + * should select the correct alternative for your board by including definitions + * such as: + * + * #define GPIO_UART1_RXD GPIO_UART1_RXD_1 + * + * (without the suffix) + */ + +#define GPIO_CAN1_RD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_UART3_TXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_I2C1_SDA_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_CAN1_TD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_UART3_RXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_I2C1_SCL_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_AD0p7 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_AD0p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAN2_RD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAN2_TD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_I2S_RXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_SSP0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_SPI_SCK (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_SSP0_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_SPI_SSEL (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SSP0_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SPI_MISO (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SSP0_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SPI_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_I2C1_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_I2C1_SCL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_CAN1_RD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_CAN1_TD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_AD0p0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_I2S_RXCLK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_AD0p1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_I2S_RXWS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_AD0p2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_I2S_RXSDA_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_AD0p3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_AOUT (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_USB_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_USB_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_USB_DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_USB_DM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_ENET_TXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_ENET_TXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_ENET_TXEN (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_ENET_CRS (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_ENET_RXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_ENET_RXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_ENET_RXER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_ENET_REFCLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_ENET_MDIO_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_USB_UPLED (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_PWM1p1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_MCPWM_MCOA0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_USB_PPWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_MCPWM_MCI0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_PWM1p2_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_SSP0_SCK_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_MCPWM_MCABORT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_PWM1p3_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_SSP0_SSEL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_MCPWM_MCOB0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_USB_PWRD (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_MCPWM_MCI1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_PWM1p4_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_SSP0_MISO_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_MCPWM_MCI2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_PWM1p5_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_SSP0_MOSI_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_MCPWM_MCOA1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_MCPWM_MCOB1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_PWM1p6_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_USB_OVRCR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_MCPWM_MCOA2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_PCAP1p0_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_MAT0p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_MCPWM_MCOB2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_PCAP1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_MAT0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_USB_VBUS (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_AD0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_SSP1_SCK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_AD0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_PWM1p1_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_PWM1p2_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_UART1_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_PWM1p3_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_PWM1p4_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_PWM1p5_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_PWM1p6_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_PCAP1p0_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CAN2_RD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_CAN2_TD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_ENET_MDC_2 (GPIO_ALT3 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_USB_CONNECT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_ENET_MDIO_2 (GPIO_ALT3 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_EINT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_NMI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_EINT1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_I2S_TXCLK_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_PEINT2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_I2S_TXWS_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_EINT3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_I2S_TXSDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_MAT0p0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_PWM1p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_STCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_MAT0p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_PWM1p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_RXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_MAT2p0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_TXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_MAT2p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h new file mode 100644 index 000000000..21e8e6c33 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc178x_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h new file mode 100644 index 000000000..53c2b26a9 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h @@ -0,0 +1,72 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lp178x_pinconfig.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* GPIO pin definitions *************************************************************/ +/* NOTE that functions have a alternate pins that can be selected. These alternates + * are identified with a numerica suffix like _1, _2, or _3. Your board.h file + * should select the correct alternative for your board by including definitions + * such as: + * + * #define GPIO_UART1_RXD GPIO_UART1_RXD_1 + * + * (without the suffix) + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_adc.h new file mode 100644 index 000000000..8cec0d325 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_adc.h @@ -0,0 +1,180 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_adc.h + * + * Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ +#define LPC17_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ +#define LPC17_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ + +#define LPC17_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) +#define LPC17_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ +#define LPC17_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ +#define LPC17_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ +#define LPC17_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ +#define LPC17_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ +#define LPC17_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ +#define LPC17_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ +#define LPC17_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ + +#define LPC17_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ +#define LPC17_ADC_TRM_OFFSET 0x0034 /* ADC trim register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_ADC_CR (LPC17_ADC_BASE+LPC17_ADC_CR_OFFSET) +#define LPC17_ADC_GDR (LPC17_ADC_BASE+LPC17_ADC_GDR_OFFSET) +#define LPC17_ADC_INTEN (LPC17_ADC_BASE+LPC17_ADC_INTEN_OFFSET) + +#define LPC17_ADC_DR(n) (LPC17_ADC_BASE+LPC17_ADC_DR_OFFSET(n)) +#define LPC17_ADC_DR0 (LPC17_ADC_BASE+LPC17_ADC_DR0_OFFSET) +#define LPC17_ADC_DR1 (LPC17_ADC_BASE+LPC17_ADC_DR1_OFFSET) +#define LPC17_ADC_DR2 (LPC17_ADC_BASE+LPC17_ADC_DR2_OFFSET) +#define LPC17_ADC_DR3 (LPC17_ADC_BASE+LPC17_ADC_DR3_OFFSET) +#define LPC17_ADC_DR4 (LPC17_ADC_BASE+LPC17_ADC_DR4_OFFSET) +#define LPC17_ADC_DR5 (LPC17_ADC_BASE+LPC17_ADC_DR5_OFFSET) +#define LPC17_ADC_DR6 (LPC17_ADC_BASE+LPC17_ADC_DR6_OFFSET) +#define LPC17_ADC_DR7 (LPC17_ADC_BASE+LPC17_ADC_DR7_OFFSET) + +#define LPC17_ADC_STAT (LPC17_ADC_BASE+LPC17_ADC_STAT_OFFSET) +#define LPC17_ADC_TRM (LPC17_ADC_BASE+LPC17_ADC_TRM_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* A/D Control Register */ + +#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */ +#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK) +#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */ +#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT) +#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */ + /* Bits 17-20: Reserved */ +#define ADC_CR_PDN (1 << 21) /* Bit 21: A/D converter power-down mode */ + /* Bits 22-23: Reserved */ +#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */ +#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT) +# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */ +# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */ +# define ADC_CR_START_P2p10 (2 << ADC_CR_START_SHIFT) /* Start edge on P2.10/EINT0/NMI */ +# define ADC_CR_START_P1p27 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.27/CLKOUT/USB_OVRCRn/CAP0.1 */ +# define ADC_CR_START_MAT0p1 (4 << ADC_CR_START_SHIFT) /* Start edge on MAT0.1 */ +# define ADC_CR_START_MAT0p3 (5 << ADC_CR_START_SHIFT) /* Start edge on MAT0.3 */ +# define ADC_CR_START_MAT1p0 (6 << ADC_CR_START_SHIFT) /* Start edge on MAT1.0 */ +# define ADC_CR_START_MAT1p1 (7 << ADC_CR_START_SHIFT) /* Start edge on MAT1.1 */ +#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */ + /* Bits 28-31: Reserved */ +/* A/D Global Data Register AND Channel 0-7 Data Register */ + /* Bits 0-3: Reserved */ +#define ADC_DR_RESULT_SHIFT (4) /* Bits 4-15: Result of conversion (DONE==1) */ +#define ADC_DR_RESULT_MASK (0x0fff << ADC_DR_RESULT_SHIFT) + /* Bits 16-23: Reserved */ +#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ +#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT) + /* Bits 27-29: Reserved */ +#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ +#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ + +/* A/D Interrupt Enable Register */ + +#define ADC_INTEN_CHAN(n) (1 << (n)) +#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */ +#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */ +#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */ +#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */ +#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */ +#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */ +#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */ +#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */ +#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */ + /* Bits 9-31: Reserved */ +/* A/D Status Register */ + +#define ADC_STAT_DONE(n) (1 << (n)) +#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */ +#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */ +#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */ +#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */ +#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */ +#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */ +#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */ +#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */ +#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8) +#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */ +#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */ +#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */ +#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */ +#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */ +#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */ +#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */ +#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */ +#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */ + /* Bits 17-31: Reserved */ +/* ADC trim register */ + /* Bits 0-3: Reserved */ +#define ADC_TRM_ADCOFFS_SHIFT (4) /* Bits 4-7: A/D offset trim bits */ +#define ADC_TRM_ADCOFFS_MASK (15 << ADC_TRM_ADCOFFS_SHIFT) +#define ADC_TRM_TRIM_SHIFT (8) /* Bits 8-11: Written-to by boot code */ +#define ADC_TRM_TRIM_MASK (15 << ADC_TRM_TRIM_SHIFT) + /* Bits 12-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h new file mode 100644 index 000000000..84b019d61 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_can.h @@ -0,0 +1,510 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_can.h + * + * Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */ +#define LPC17_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */ +#define LPC17_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */ +#define LPC17_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */ +#define LPC17_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */ +#define LPC17_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */ +#define LPC17_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */ +#define LPC17_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */ +#define LPC17_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */ +#define LPC17_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */ +#define LPC17_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */ + +/* Central CAN registers */ + +#define LPC17_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */ +#define LPC17_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */ +#define LPC17_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */ + +/* CAN1/2 registers */ + +#define LPC17_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */ +#define LPC17_CAN_CMR_OFFSET 0x0004 /* Command bits */ +#define LPC17_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */ +#define LPC17_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */ +#define LPC17_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */ +#define LPC17_CAN_BTR_OFFSET 0x0014 /* Bus Timing */ +#define LPC17_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */ +#define LPC17_CAN_SR_OFFSET 0x001c /* Status Register */ +#define LPC17_CAN_RFS_OFFSET 0x0020 /* Receive frame status */ +#define LPC17_CAN_RID_OFFSET 0x0024 /* Received Identifier */ +#define LPC17_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */ +#define LPC17_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */ +#define LPC17_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */ +#define LPC17_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */ +#define LPC17_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */ +#define LPC17_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */ +#define LPC17_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */ +#define LPC17_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */ +#define LPC17_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */ +#define LPC17_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */ +#define LPC17_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */ +#define LPC17_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */ +#define LPC17_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */ +#define LPC17_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */ + +/* Register addresses ***************************************************************/ +/* CAN acceptance filter registers */ + +#define LPC17_CANAF_AFMR (LPC17_CANAF_BASE+LPC17_CANAF_AFMR_OFFSET) +#define LPC17_CANAF_SFFSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFSA_OFFSET) +#define LPC17_CANAF_SFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFGRPSA_OFFSET) +#define LPC17_CANAF_EFFSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFSA_OFFSET) +#define LPC17_CANAF_EFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFGRPSA_OFFSET) +#define LPC17_CANAF_EOT (LPC17_CANAF_BASE+LPC17_CANAF_EOT_OFFSET) +#define LPC17_CANAF_LUTERRAD (LPC17_CANAF_BASE+LPC17_CANAF_LUTERRAD_OFFSET) +#define LPC17_CANAF_LUTERR (LPC17_CANAF_BASE+LPC17_CANAF_LUTERR_OFFSET) +#define LPC17_CANAF_FCANIE (LPC17_CANAF_BASE+LPC17_CANAF_FCANIE_OFFSET) +#define LPC17_CANAF_FCANIC0 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC0_OFFSET) +#define LPC17_CANAF_FCANIC1 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC1_OFFSET) + +/* Central CAN registers */ + +#define LPC17_CAN_TXSR (LPC17_CAN_BASE+LPC17_CAN_TXSR_OFFSET) +#define LPC17_CAN_RXSR (LPC17_CAN_BASE+LPC17_CAN_RXSR_OFFSET) +#define LPC17_CAN_MSR (LPC17_CAN_BASE+LPC17_CAN_MSR_OFFSET) + +/* CAN1/2 registers */ + +#define LPC17_CAN1_MOD (LPC17_CAN1_BASE+LPC17_CAN_MOD_OFFSET) +#define LPC17_CAN1_CMR (LPC17_CAN1_BASE+LPC17_CAN_CMR_OFFSET) +#define LPC17_CAN1_GSR (LPC17_CAN1_BASE+LPC17_CAN_GSR_OFFSET) +#define LPC17_CAN1_ICR (LPC17_CAN1_BASE+LPC17_CAN_ICR_OFFSET) +#define LPC17_CAN1_IER (LPC17_CAN1_BASE+LPC17_CAN_IER_OFFSET) +#define LPC17_CAN1_BTR (LPC17_CAN1_BASE+LPC17_CAN_BTR_OFFSET) +#define LPC17_CAN1_EWL (LPC17_CAN1_BASE+LPC17_CAN_EWL_OFFSET) +#define LPC17_CAN1_SR (LPC17_CAN1_BASE+LPC17_CAN_SR_OFFSET) +#define LPC17_CAN1_RFS (LPC17_CAN1_BASE+LPC17_CAN_RFS_OFFSET) +#define LPC17_CAN1_RID (LPC17_CAN1_BASE+LPC17_CAN_RID_OFFSET) +#define LPC17_CAN1_RDA (LPC17_CAN1_BASE+LPC17_CAN_RDA_OFFSET) +#define LPC17_CAN1_RDB (LPC17_CAN1_BASE+LPC17_CAN_RDB_OFFSET) +#define LPC17_CAN1_TFI1 (LPC17_CAN1_BASE+LPC17_CAN_TFI1_OFFSET) +#define LPC17_CAN1_TID1 (LPC17_CAN1_BASE+LPC17_CAN_TID1_OFFSET) +#define LPC17_CAN1_TDA1 (LPC17_CAN1_BASE+LPC17_CAN_TDA1_OFFSET) +#define LPC17_CAN1_TDB1 (LPC17_CAN1_BASE+LPC17_CAN_TDB1_OFFSET) +#define LPC17_CAN1_TFI2 (LPC17_CAN1_BASE+LPC17_CAN_TFI2_OFFSET) +#define LPC17_CAN1_TID2 (LPC17_CAN1_BASE+LPC17_CAN_TID2_OFFSET) +#define LPC17_CAN1_TDA2 (LPC17_CAN1_BASE+LPC17_CAN_TDA2_OFFSET) +#define LPC17_CAN1_TDB2 (LPC17_CAN1_BASE+LPC17_CAN_TDB2_OFFSET) +#define LPC17_CAN1_TFI3 (LPC17_CAN1_BASE+LPC17_CAN_TFI3_OFFSET) +#define LPC17_CAN1_TID3 (LPC17_CAN1_BASE+LPC17_CAN_TID3_OFFSET) +#define LPC17_CAN1_TDA3 (LPC17_CAN1_BASE+LPC17_CAN_TDA3_OFFSET) +#define LPC17_CAN1_TDB3 (LPC17_CAN1_BASE+LPC17_CAN_TDB3_OFFSET) + +#define LPC17_CAN2_MOD (LPC17_CAN2_BASE+LPC17_CAN_MOD_OFFSET) +#define LPC17_CAN2_CMR (LPC17_CAN2_BASE+LPC17_CAN_CMR_OFFSET) +#define LPC17_CAN2_GSR (LPC17_CAN2_BASE+LPC17_CAN_GSR_OFFSET) +#define LPC17_CAN2_ICR (LPC17_CAN2_BASE+LPC17_CAN_ICR_OFFSET) +#define LPC17_CAN2_IER (LPC17_CAN2_BASE+LPC17_CAN_IER_OFFSET) +#define LPC17_CAN2_BTR (LPC17_CAN2_BASE+LPC17_CAN_BTR_OFFSET) +#define LPC17_CAN2_EWL (LPC17_CAN2_BASE+LPC17_CAN_EWL_OFFSET) +#define LPC17_CAN2_SR (LPC17_CAN2_BASE+LPC17_CAN_SR_OFFSET) +#define LPC17_CAN2_RFS (LPC17_CAN2_BASE+LPC17_CAN_RFS_OFFSET) +#define LPC17_CAN2_RID (LPC17_CAN2_BASE+LPC17_CAN_RID_OFFSET) +#define LPC17_CAN2_RDA (LPC17_CAN2_BASE+LPC17_CAN_RDA_OFFSET) +#define LPC17_CAN2_RDB (LPC17_CAN2_BASE+LPC17_CAN_RDB_OFFSET) +#define LPC17_CAN2_TFI1 (LPC17_CAN2_BASE+LPC17_CAN_TFI1_OFFSET) +#define LPC17_CAN2_TID1 (LPC17_CAN2_BASE+LPC17_CAN_TID1_OFFSET) +#define LPC17_CAN2_TDA1 (LPC17_CAN2_BASE+LPC17_CAN_TDA1_OFFSET) +#define LPC17_CAN2_TDB1 (LPC17_CAN2_BASE+LPC17_CAN_TDB1_OFFSET) +#define LPC17_CAN2_TFI2 (LPC17_CAN2_BASE+LPC17_CAN_TFI2_OFFSET) +#define LPC17_CAN2_TID2 (LPC17_CAN2_BASE+LPC17_CAN_TID2_OFFSET) +#define LPC17_CAN2_TDA2 (LPC17_CAN2_BASE+LPC17_CAN_TDA2_OFFSET) +#define LPC17_CAN2_TDB2 (LPC17_CAN2_BASE+LPC17_CAN_TDB2_OFFSET) +#define LPC17_CAN2_TFI3 (LPC17_CAN2_BASE+LPC17_CAN_TFI3_OFFSET) +#define LPC17_CAN2_TID3 (LPC17_CAN2_BASE+LPC17_CAN_TID3_OFFSET) +#define LPC17_CAN2_TDA3 (LPC17_CAN2_BASE+LPC17_CAN_TDA3_OFFSET) +#define LPC17_CAN2_TDB3 (LPC17_CAN2_BASE+LPC17_CAN_TDB3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* CAN acceptance filter registers */ +/* Acceptance Filter Register */ + +#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */ +#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */ +#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */ + /* Bits 3-31: Reserved */ +/* Standard Frame Individual Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Standard Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */ +#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT) + /* Bits 11-31: Reserved */ +/* Extended Frame Group Start Address Register */ + /* Bits 0-1: Reserved */ +#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */ +#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT) + /* Bits 11-31: Reserved */ +/* End of AF Tables register */ + /* Bits 0-1: Reserved */ +#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */ +#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Address register */ + /* Bits 0-1: Reserved */ +#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */ +#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT) + /* Bits 11-31: Reserved */ +/* LUT Error Register */ + +#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */ + /* Bits 1-31: Reserved */ +/* FullCAN interrupt enable register */ + +#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */ + /* Bits 1-31: Reserved */ + +/* FullCAN interrupt and capture register 0 */ + +#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */ + +/* FullCAN interrupt and capture register 1 */ + +#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */ + +/* Central CAN registers */ +/* CAN Central Transmit Status Register */ + +#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */ +#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */ + /* Bits 2-7: Reserved */ +#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */ +#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */ + /* Bits 10-15: Reserved */ +#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */ +#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */ + /* Bits 18-31: Reserved */ +/* CAN Central Receive Status Register */ + +#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */ +#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */ + /* Bits 2-7: Reserved */ +#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */ +#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */ + /* Bits 10-15: Reserved */ +#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */ +#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */ + /* Bits 18-31: Reserved */ +/* CAN Central Miscellaneous Register */ + +#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */ +#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */ + /* Bits 2-7: Reserved */ +#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */ +#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */ + /* Bits 10-31: Reserved */ +/* CAN1/2 registers */ +/* CAN operating mode */ + +#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */ +#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */ +#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */ +#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */ +#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */ +#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */ + /* Bit 6: Reserved */ +#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */ + /* Bits 8-31: Reserved */ +/* Command bits */ + +#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */ +#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */ +#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */ +#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */ +#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */ +#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */ +#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */ +#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */ + /* Bits 8-31: Reserved */ +/* Controller Status and Error Counters */ + +#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */ +#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */ +#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */ +#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */ +#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */ +#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */ + /* Bits 8-15: Reserved */ +#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */ +#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT) +#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */ +#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT) + +/* Interrupt and capture register */ + +#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */ +#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */ +#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */ +#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */ +#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */ +#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */ +#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */ +#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */ +#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */ +#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */ + /* Bits 11-15: Reserved */ +#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ +#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) +# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ +# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ +# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ +# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ +# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ +# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ +# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ +# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ +# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ +# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ +# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ +# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ +# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ +# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ +# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ +# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ +# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ +# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ +# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ +# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ +# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ +# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ +#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ +#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ +#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT) +# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT) +#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */ +#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT) + +/* Interrupt Enable */ + +#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */ +#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */ +#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */ +#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */ +#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */ +#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */ +#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */ +#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */ +#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */ +#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */ +#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */ + /* Bits 11-31: Reserved */ +/* Bus Timing */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT) + /* Bits 10-13: Reserved */ +#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_TSEG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */ +#define CAN_BTR_TSEG1_MASK (15 << CAN_BTR_TSEG1_SHIFT) +#define CAN_BTR_TSEG2_SHIFT (20) /* Bits 20-22: smaple to next delay */ +#define CAN_BTR_TSEG2_MASK (7 << CAN_BTR_TSEG2_SHIFT) +#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */ + /* Bits 24-31: Reserved */ + +#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ +#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ +#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ + +/* Error Warning Limit */ + +#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ +#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) + /* Bits 8-31: Reserved */ +/* Status Register */ + +#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */ +#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */ +#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */ +#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */ +#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */ +#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */ +#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */ +#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */ +#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */ +#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */ +#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */ +#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */ +#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */ +#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */ +#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */ +#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */ +#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */ +#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */ +#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */ +#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */ +#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */ +#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */ +#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */ +#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */ + /* Bits 24-31: Reserved */ +/* Receive frame status */ + +#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */ +#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT) +#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */ + /* Bits 11-15: Reserved */ +#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */ +#define CAN_RFS_DLC_MASK (15 << CAN_RFS_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */ +#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Received Identifier */ + +#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ +/* Received data bytes 1-4 */ + +#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */ +#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT) +#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */ +#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT) +#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */ +#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT) +#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */ +#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT) + +/* Received data bytes 5-8 */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and + * Transmit frame info (Tx Buffer 3) common bit field definitions + */ + +#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */ +#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT) + /* Bits 8-15: Reserved */ +#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */ +#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT) + /* Bits 20-29: Reserved */ +#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */ +#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ + +/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and + * Transmit Identifier (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ + /* Bits 11-31: Reserved */ +#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ + /* Bits 29-31: Reserved */ + +/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and + * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */ +#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT) +#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */ +#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT) +#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */ +#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT) +#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ +#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) + +/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and + * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. + */ + +#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */ +#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) +#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */ +#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) +#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */ +#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) +#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */ +#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_dac.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_dac.h new file mode 100644 index 000000000..be78bef05 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_dac.h @@ -0,0 +1,97 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_dac.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_DAC_CR_OFFSET 0x0000 /* D/A Converter Register */ +#define LPC17_DAC_CTRL_OFFSET 0x0004 /* DAC Control register */ +#define LPC17_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_DAC_CR (LPC17_DAC_BASE+LPC17_DAC_CR_OFFSET) +#define LPC17_DAC_CTRL (LPC17_DAC_BASE+LPC17_DAC_CTRL_OFFSET) +#define LPC17_DAC_CNTVAL (LPC17_DAC_BASE+LPC17_DAC_CNTVAL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* D/A Converter Register */ + /* Bits 0-5: Reserved */ +#define DAC_CR_VALUE_SHIFT (6) /* Bits 6-15: Controls voltage on the AOUT pin */ +#define DAC_CR_VALUE_MASK (0x3ff << DAC_CR_VALUE_SHIFT) +#define DAC_CR_BIAS (1 << 16) /* Bit 16: Controls DAC settling time */ + /* Bits 17-31: Reserved */ +/* DAC Control register */ + +#define DAC_CTRL_INTDMAREQ (1 << 0) /* Bit 0: Timer timed out */ +#define DAC_CTRL_DBLBUFEN (1 << 1) /* Bit 1: Enable DACR double-buffering */ +#define DAC_CTRL_CNTEN (1 << 2) /* Bit 2: Enable timeout counter */ +#define DAC_CTRL_DMAEN (1 << 3) /* Bit 3: Enable DMA access */ + /* Bits 4-31: Reserved */ +/* DAC Counter Value register */ + +#define DAC_CNTVAL_SHIFT (0) /* Bits 0-15: Reload value for DAC interrupt/DMA timer */ +#define DAC_CNTVAL_MASK (0xffff << DAC_CNTVAL_SHIFT) + /* Bits 8-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h new file mode 100644 index 000000000..b0791ced9 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h @@ -0,0 +1,597 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_ethernet.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* MAC registers */ + +#define LPC17_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */ +#define LPC17_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */ +#define LPC17_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */ +#define LPC17_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */ +#define LPC17_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */ +#define LPC17_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */ +#define LPC17_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */ +#define LPC17_ETH_TEST_OFFSET 0x001c /* Test register */ +#define LPC17_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */ +#define LPC17_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */ +#define LPC17_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */ +#define LPC17_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */ +#define LPC17_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */ +#define LPC17_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */ +#define LPC17_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */ +#define LPC17_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */ +#define LPC17_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */ + +/* Control registers */ + +#define LPC17_ETH_CMD_OFFSET 0x0100 /* Command register */ +#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */ +#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */ +#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */ +#define LPC17_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */ +#define LPC17_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */ +#define LPC17_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */ +#define LPC17_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */ +#define LPC17_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */ +#define LPC17_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */ +#define LPC17_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */ +#define LPC17_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */ +#define LPC17_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */ +#define LPC17_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */ +#define LPC17_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */ +#define LPC17_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */ +#define LPC17_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */ + +/* Rx filter registers */ + +#define LPC17_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */ +#define LPC17_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */ +#define LPC17_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */ +#define LPC17_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */ +#define LPC17_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */ + +/* Module control registers */ + +#define LPC17_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */ +#define LPC17_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */ +#define LPC17_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */ + +/* Register addresses ***************************************************************/ +/* MAC registers */ + +#define LPC17_ETH_MAC1 (LPC17_ETH_BASE+LPC17_ETH_MAC1_OFFSET) +#define LPC17_ETH_MAC2 (LPC17_ETH_BASE+LPC17_ETH_MAC2_OFFSET) +#define LPC17_ETH_IPGT (LPC17_ETH_BASE+LPC17_ETH_IPGT_OFFSET) +#define LPC17_ETH_IPGR (LPC17_ETH_BASE+LPC17_ETH_IPGR_OFFSET) +#define LPC17_ETH_CLRT (LPC17_ETH_BASE+LPC17_ETH_CLRT_OFFSET) +#define LPC17_ETH_MAXF (LPC17_ETH_BASE+LPC17_ETH_MAXF_OFFSET) +#define LPC17_ETH_SUPP (LPC17_ETH_BASE+LPC17_ETH_SUPP_OFFSET) +#define LPC17_ETH_TEST (LPC17_ETH_BASE+LPC17_ETH_TEST_OFFSET) +#define LPC17_ETH_MCFG (LPC17_ETH_BASE+LPC17_ETH_MCFG_OFFSET) +#define LPC17_ETH_MCMD (LPC17_ETH_BASE+LPC17_ETH_MCMD_OFFSET) +#define LPC17_ETH_MADR (LPC17_ETH_BASE+LPC17_ETH_MADR_OFFSET) +#define LPC17_ETH_MWTD (LPC17_ETH_BASE+LPC17_ETH_MWTD_OFFSET) +#define LPC17_ETH_MRDD (LPC17_ETH_BASE+LPC17_ETH_MRDD_OFFSET) +#define LPC17_ETH_MIND (LPC17_ETH_BASE+LPC17_ETH_MIND_OFFSET) +#define LPC17_ETH_SA0 (LPC17_ETH_BASE+LPC17_ETH_SA0_OFFSET) +#define LPC17_ETH_SA1 (LPC17_ETH_BASE+LPC17_ETH_SA1_OFFSET) +#define LPC17_ETH_SA2 (LPC17_ETH_BASE+LPC17_ETH_SA2_OFFSET) + +/* Control registers */ + +#define LPC17_ETH_CMD (LPC17_ETH_BASE+LPC17_ETH_CMD_OFFSET) +#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET) +#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET) +#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET) +#define LPC17_ETH_RXDESCNO (LPC17_ETH_BASE+LPC17_ETH_RXDESCNO_OFFSET) +#define LPC17_ETH_RXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_RXPRODIDX_OFFSET) +#define LPC17_ETH_RXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_RXCONSIDX_OFFSET) +#define LPC17_ETH_TXDESC (LPC17_ETH_BASE+LPC17_ETH_TXDESC_OFFSET) +#define LPC17_ETH_TXSTAT (LPC17_ETH_BASE+LPC17_ETH_TXSTAT_OFFSET) +#define LPC17_ETH_TXDESCRNO (LPC17_ETH_BASE+LPC17_ETH_TXDESCRNO_OFFSET) +#define LPC17_ETH_TXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_TXPRODIDX_OFFSET) +#define LPC17_ETH_TXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_TXCONSIDX_OFFSET) +#define LPC17_ETH_TSV0 (LPC17_ETH_BASE+LPC17_ETH_TSV0_OFFSET) +#define LPC17_ETH_TSV1 (LPC17_ETH_BASE+LPC17_ETH_TSV1_OFFSET) +#define LPC17_ETH_RSV (LPC17_ETH_BASE+LPC17_ETH_RSV_OFFSET) +#define LPC17_ETH_FCCNTR (LPC17_ETH_BASE+LPC17_ETH_FCCNTR_OFFSET) +#define LPC17_ETH_FCSTAT (LPC17_ETH_BASE+LPC17_ETH_FCSTAT_OFFSET) + +/* Rx filter registers */ + +#define LPC17_ETH_RXFLCTRL (LPC17_ETH_BASE+LPC17_ETH_RXFLCTRL_OFFSET) +#define LPC17_ETH_RXFLWOLST (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLST_OFFSET) +#define LPC17_ETH_RXFLWOLCLR (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLCLR_OFFSET) +#define LPC17_ETH_HASHFLL (LPC17_ETH_BASE+LPC17_ETH_HASHFLL_OFFSET) +#define LPC17_ETH_HASHFLH (LPC17_ETH_BASE+LPC17_ETH_HASHFLH_OFFSET) + +/* Module control registers */ + +#define LPC17_ETH_INTST (LPC17_ETH_BASE+LPC17_ETH_INTST_OFFSET) +#define LPC17_ETH_INTEN (LPC17_ETH_BASE+LPC17_ETH_INTEN_OFFSET) +#define LPC17_ETH_INTCLR (LPC17_ETH_BASE+LPC17_ETH_INTCLR_OFFSET) +#define LPC17_ETH_INTSET (LPC17_ETH_BASE+LPC17_ETH_INTSET_OFFSET) +#define LPC17_ETH_PWRDOWN (LPC17_ETH_BASE+LPC17_ETH_PWRDOWN_OFFSET) + +/* Register bit definitions *********************************************************/ +/* MAC registers */ +/* MAC configuration register 1 (MAC1) */ + +#define ETH_MAC1_RE (1 << 0) /* Bit 0: Receive enable */ +#define ETH_MAC1_PARF (1 << 1) /* Bit 1: Passall all receive frames */ +#define ETH_MAC1_RFC (1 << 2) /* Bit 2: RX flow control */ +#define ETH_MAC1_TFC (1 << 3) /* Bit 3: TX flow control */ +#define ETH_MAC1_LPBK (1 << 4) /* Bit 4: Loopback */ + /* Bits 5-7: Reserved */ +#define ETH_MAC1_TXRST (1 << 8) /* Bit 8: Reset TX */ +#define ETH_MAC1_MCSTXRST (1 << 9) /* Bit 9: Reset MCS/TX */ +#define ETH_MAC1_RXRST (1 << 10) /* Bit 10: Reset RX */ +#define ETH_MAC1_MCSRXRST (1 << 11) /* Bit 11: Reset MCS/RX */ + /* Bits 12-13: Reserved */ +#define ETH_MAC1_SIMRST (1 << 14) /* Bit 14: Simulation reset */ +#define ETH_MAC1_SOFTRST (1 << 15) /* Bit 15: Soft reset */ + /* Bits 16-31: Reserved */ +/* MAC configuration register 2 (MAC2) */ + +#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */ +#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */ +#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge frame enable */ +#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */ +#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */ +#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */ +#define ETH_MAC2_VLANPADEN (1 << 6) /* Bit 6: VLAN pad enable */ +#define ETH_MAC2_AUTOPADEN (1 << 7) /* Bit 7: Auto detect pad enable */ +#define ETH_MAC2_PPE (1 << 8) /* Bit 8: Pure preamble enforcement */ +#define ETH_MAC2_LPE (1 << 9) /* Bit 9: Long preamble enforcement */ + /* Bits 10-11: Reserved */ +#define ETH_MAC2_NBKOFF (1 << 12) /* Bit 12: No backoff */ +#define ETH_MAC2_BPNBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */ +#define ETH_MAC2_EXDEF (1 << 14) /* Bit 14: Excess defer */ + /* Bits 15-31: Reserved */ +/* Back-to-Back Inter-Packet-Gap register (IPGT) */ + +#define ETH_IPGT_SHIFT (0) /* Bits 0-6 */ +#define ETH_IPGT_MASK (0x7f << ETH_IPGT_SHIFT) + /* Bits 7-31: Reserved */ +/* Non Back-to-Back Inter-Packet-Gap register (IPGR) */ + +#define ETH_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */ +#define ETH_IPGR_GAP2_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) + /* Bit 7: Reserved */ +#define ETH_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */ +#define ETH_IPGR_GAP1_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) + /* Bits 15-31: Reserved */ +/* Collision window / Retry register (CLRT) */ + +#define ETH_CLRT_RMAX_SHIFT (0) /* Bits 0-3: Retransmission maximum */ +#define ETH_CLRT_RMAX_MASK (15 << ETH_CLRT_RMAX_SHIFT) + /* Bits 4-7: Reserved */ +#define ETH_CLRT_COLWIN_SHIFT (8) /* Bits 8-13: Collision window */ +#define ETH_CLRT_COLWIN_MASK (0x3f << ETH_CLRT_COLWIN_SHIFT) + /* Bits 14-31: Reserved */ +/* Maximum Frame register (MAXF) */ + +#define ETH_MAXF_SHIFT (0) /* Bits 0-15 */ +#define ETH_MAXF_MASK (0xffff << ETH_MAXF_SHIFT) + /* Bits 16-31: Reserved */ +/* PHY Support register (SUPP) */ + /* Bits 0-7: Reserved */ +#define ETH_SUPP_SPEED (1 << 8) /* Bit 8: 0=10Bps 1=100Bps */ + /* Bits 9-31: Reserved */ +/* Test register (TEST) */ + +#define ETH_TEST_SPQ (1 << 0) /* Bit 0: Shortcut pause quanta */ +#define ETH_TEST_TP (1 << 1) /* Bit 1: Test pause */ +#define ETH_TEST_TBP (1 << 2) /* Bit 2: Test packpressure */ + /* Bits 3-31: Reserved */ +/* MII Mgmt Configuration register (MCFG) */ + +#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */ +#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */ +#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5: Clock select */ +#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV8 (3 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV10 (4 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV14 (5 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV20 (6 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV28 (7 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV36 (8 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV40 (9 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV44 (10 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV48 (11 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV52 (12 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV56 (13 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV60 (14 << ETH_MCFG_CLKSEL_SHIFT) +# define ETH_MCFG_CLKSEL_DIV64 (15 << ETH_MCFG_CLKSEL_SHIFT) + /* Bits 6-14: Reserved */ +#define ETH_MCFG_MIIRST (1 << 15) /* Bit 15: Reset MII mgmt */ + /* Bits 16-31: Reserved */ +/* MII Mgmt Command register (MCMD) */ + +#define ETH_MCMD_READ (1 << 0) /* Bit 0: Single read cycle */ +#define ETH_MCMD_SCAN (1 << 1) /* Bit 1: Continuous read cycles */ + /* Bits 2-31: Reserved */ +#define ETH_MCMD_WRITE (0) + +/* MII Mgmt Address register (MADR) */ + +#define ETH_MADR_REGADDR_SHIFT (0) /* Bits 0-4: Register address */ +#define ETH_MADR_REGADDR_MASK (31 << ETH_MADR_REGADDR_SHIFT) + /* Bits 7-5: Reserved */ +#define ETH_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */ +#define ETH_MADR_PHYADDR_MASK (31 << ETH_MADR_PHYADDR_SHIFT) + /* Bits 13-31: Reserved */ +/* MII Mgmt Write Data register (MWTD) */ + +#define ETH_MWTD_SHIFT (0) /* Bits 0-15 */ +#define ETH_MWTD_MASK (0xffff << ETH_MWTD_SHIFT) + /* Bits 16-31: Reserved */ +/* MII Mgmt Read Data register (MRDD) */ + +#define ETH_MRDD_SHIFT (0) /* Bits 0-15 */ +#define ETH_MRDD_MASK (0xffff << ETH_MRDD_SHIFT) + /* Bits 16-31: Reserved */ +/* MII Mgmt Indicators register (MIND) */ + +#define ETH_MIND_BUSY (1 << 0) /* Bit 0: Busy */ +#define ETH_MIND_SCANNING (1 << 1) /* Bit 1: Scanning */ +#define ETH_MIND_NVALID (1 << 2) /* Bit 2: Not valid */ +#define ETH_MIND_MIIFAIL (1 << 3) /* Bit 3: MII link fail */ + /* Bits 4-31: Reserved */ +/* Station Address 0 register (SA0) */ + +#define ETH_SA0_OCTET2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */ +#define ETH_SA0_OCTET2_MASK (0xff << ETH_SA0_OCTET2_SHIFT) +#define ETH_SA0_OCTET1_SHIFT (8) /* Bits 8-15: Station address 1st octet */ +#define ETH_SA0_OCTET1_MASK (0xff << ETH_SA0_OCTET1_SHIFT) + /* Bits 16-31: Reserved */ +/* Station Address 1 register (SA1) */ + +#define ETH_SA1_OCTET4_SHIFT (0) /* Bits 0-7: Station address 4th octet */ +#define ETH_SA1_OCTET4_MASK (0xff << ETH_SA0_OCTET4_SHIFT) +#define ETH_SA1_OCTET3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */ +#define ETH_SA1_OCTET3_MASK (0xff << ETH_SA0_OCTET3_SHIFT) + /* Bits 16-31: Reserved */ +/* Station Address 2 register (SA2) */ + +#define ETH_SA2_OCTET6_SHIFT (0) /* Bits 0-7: Station address 5th octet */ +#define ETH_SA2_OCTET6_MASK (0xff << ETH_SA0_OCTET6_SHIFT) +#define ETH_SA2_OCTET5_SHIFT (8) /* Bits 8-15: Station address 6th octet */ +#define ETH_SA2_OCTET5_MASK (0xff << ETH_SA0_OCTET5_SHIFT) + /* Bits 16-31: Reserved */ +/* Control registers */ +/* Command register (CMD) */ + +#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */ +#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */ + /* Bit 2: Reserved */ +#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */ +#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */ +#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */ +#define ETH_CMD_PRFRAME (1 << 6) /* Bit 6: Pass run frame */ +#define ETH_CMD_PRFILTER (1 << 7) /* Bit 7: Pass RX filter */ +#define ETH_CMD_TXFC (1 << 8) /* Bit 8: TX flow control */ +#define ETH_CMD_RMII (1 << 9) /* Bit 9: RMII mode */ +#define ETH_CMD_FD (1 << 10) /* Bit 10: Full duplex */ + /* Bits 11-31: Reserved */ +/* Status register */ + +#define ETH_STAT_RX (1 << 0) /* Bit 0: RX status */ +#define ETH_STAT_TX (1 << 1) /* Bit 1: TX status */ + /* Bits 2-31: Reserved */ +/* Receive descriptor base address register (RXDESC) + * + * The receive descriptor base address is a byte address aligned to a word + * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest + * address in the array of descriptors. + */ + +/* Receive status base address register (RXSTAT) + * + * The receive status base address is a byte address aligned to a double word + * boundary i.e. LSB 2:0 are fixed to 000. + */ + +/* Receive number of descriptors register (RXDESCNO) */ + +#define ETH_RXDESCNO_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXDESCNO_MASK (0xffff << ETH_RXDESCNO_SHIFT) + /* Bits 16-31: Reserved */ +/* Receive produce index register (RXPRODIDX) */ + +#define ETH_RXPRODIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXPRODIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Receive consume index register (RXCONSIDX) */ + +#define ETH_RXCONSIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_RXCONSIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit descriptor base address register (TXDESC) + * + * The transmit descriptor base address is a byte address aligned to a word + * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest + * address in the array of descriptors. + */ + +/* Transmit status base address register (TXSTAT) + * + * The transmit status base address is a byte address aligned to a word + * boundary i.e. LSB1:0 are fixed to 00. The register contains the lowest + * address in the array of statuses. + */ + +/* Transmit number of descriptors register (TXDESCRNO) */ + +#define ETH_TXDESCRNO_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXDESCRNO_MASK (0xffff << ETH_TXDESCRNO_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit produce index register (TXPRODIDX) */ + +#define ETH_TXPRODIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXPRODIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit consume index register (TXCONSIDX) */ + +#define ETH_TXCONSIDX_SHIFT (0) /* Bits 0-15 */ +#define ETH_TXCONSIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) + /* Bits 16-31: Reserved */ +/* Transmit status vector 0 register (TSV0) */ + +#define ETH_TSV0_CRCERR (1 << 0) /* Bit 0: CRC error */ +#define ETH_TSV0_LENCHKERR (1 << 1) /* Bit 1: Length check error */ +#define ETH_TSV0_LENOOR (1 << 2) /* Bit 2: Length out of range */ +#define ETH_TSV0_DONE (1 << 3) /* Bit 3: Done */ +#define ETH_TSV0_MCAST (1 << 4) /* Bit 4: Multicast */ +#define ETH_TSV0_BCAST (1 << 5) /* Bit 5: Broadcast */ +#define ETH_TSV0_PKTDEFER (1 << 6) /* Bit 6: Packet Defer */ +#define ETH_TSV0_EXCDEFER (1 << 7) /* Bit 7: Excessive Defer */ +#define ETH_TSV0_EXCCOL (1 << 8) /* Bit 8: Excessive Collision */ +#define ETH_TSV0_LATECOL (1 << 9) /* Bit 9: Late Collision */ +#define ETH_TSV0_GIANT (1 << 10) /* Bit 10: Giant */ +#define ETH_TSV0_UNDRUN (1 << 11) /* Bit 11: Underrun */ +#define ETH_TSV0_TOTBYTES_SHIFT (12) /* Bits 12-27:Total bytes */ +#define ETH_TSV0_TOTBYTES_MASK (0xffff << ETH_TSV0_TOTBYTES_SHIFT) +#define ETH_TSV0_CTLFRAME (1 << 28) /* Bit 28: Control frame */ +#define ETH_TSV0_PAUSE (1 << 29) /* Bit 29: Pause */ +#define ETH_TSV0_BP (1 << 30) /* Bit 30: Backpressure */ +#define ETH_TSV0_VLAN (1 << 31) /* Bit 31: VLAN */ + +/* Transmit status vector 1 register (TSV1) */ + +#define ETH_TSV1_TXCNT_SHIFT (0) /* Bits 0-15: Transmit byte count */ +#define ETH_TSV1_TXCNT_MASK (0xffff << ETH_TSV1_TXCNT_SHIFT) +#define ETH_TSV1_COLCNT_SHIFT (16) /* Bits 16-19: Transmit collision count */ +#define ETH_TSV1_COLCNT_MASK (15 << ETH_TSV1_COLCNT_SHIFT) + /* Bits 20-31: Reserved */ +/* Receive status vector register (RSV) */ + +#define ETH_RSV_RXCNT_SHIFT (0) /* Bits 0-15: Received byte count */ +#define ETH_RSV_RXCNT_MASK (0xffff << ETH_RSV_RXCNT_SHIFT) +#define ETH_RSV_PKTPI (1 << 16) /* Bit 16: Packet previously ignored */ +#define ETH_RSV_RXEPS (1 << 17) /* Bit 17: RXDV event previously seen */ +#define ETH_RSV_CEPS (1 << 18) /* Bit 18: Carrier event previously seen */ +#define ETH_RSV_RXCV (1 << 19) /* Bit 19: Receive code violation */ +#define ETH_RSV_CRCERR (1 << 20) /* Bit 20: CRC error */ +#define ETH_RSV_LENCHKERR (1 << 21) /* Bit 21: Length check error */ +#define ETH_RSV_LENOOR (1 << 22) /* Bit 22: Length out of range */ +#define ETH_RSV_RXOK (1 << 23) /* Bit 23: Receive OK */ +#define ETH_RSV_MCAST (1 << 24) /* Bit 24: Multicast */ +#define ETH_RSV_BCAST (1 << 25) /* Bit 25: Broadcast */ +#define ETH_RSV_DRIBNIB (1 << 26) /* Bit 26: Dribble Nibble */ +#define ETH_RSV_CTLFRAME (1 << 27) /* Bit 27: Control frame */ +#define ETH_RSV_PAUSE (1 << 28) /* Bit 28: Pause */ +#define ETH_RSV_UNSUPOP (1 << 29) /* Bit 29: Unsupported Opcode */ +#define ETH_RSV_VLAN (1 << 30) /* Bit 30: VLAN */ + /* Bit 31: Reserved */ +/* Flow control counter register (FCCNTR) */ + +#define ETH_FCCNTR_MCOUNT_SHIFT (0) /* Bits 0-15: Mirror count */ +#define ETH_FCCNTR_MCOUNT_MASK (0xffff << ETH_FCCNTR_MCOUNT_SHIFT) +#define ETH_FCCNTR_PTMR_SHIFT (16) /* Bits 16-31: Pause timer */ +#define ETH_FCCNTR_PTMR_MASK (0xffff << ETH_FCCNTR_PTMR_SHIFT) + +/* Flow control status register (FCSTAT) */ + +#define ETH_FCSTAT_MCOUNT_SHIFT (0) /* Bits 0-15: Current mirror count */ +#define ETH_FCSTAT_MCOUNT_MASK (0xffff << ETH_FCSTAT_MCOUNT_SHIFT) + /* Bits 16-31: Reserved */ +/* Rx filter registers */ +/* Receive filter control register (RXFLCTRL) */ + +#define ETH_RXFLCTRL_UCASTEN (1 << 0) /* Bit 0: Accept all unicast frames */ +#define ETH_RXFLCTRL_BCASTEN (1 << 1) /* Bit 1: Accept all broadcast frames */ +#define ETH_RXFLCTRL_MCASTEN (1 << 2) /* Bit 2: Accept all multicast frames */ +#define ETH_RXFLCTRL_UCASTHASHEN (1 << 3) /* Bit 3: Accept hashed unicast */ +#define ETH_RXFLCTRL_MCASTHASHEN (1 << 4) /* Bit 4: Accect hashed multicast */ +#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */ + /* Bits 6-11: Reserved */ +#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */ +#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect match WoL interrupt */ + /* Bits 14-31: Reserved */ +/* Receive filter WoL status register (RXFLWOLST) AND + * Receive filter WoL clear register (RXFLWOLCLR) + */ + +#define ETH_RXFLWOL_UCAST (1 << 0) /* Bit 0: Unicast frame WoL */ +#define ETH_RXFLWOL_BCAST (1 << 1) /* Bit 1: Broadcast frame WoL */ +#define ETH_RXFLWOL_MCAST (1 << 2) /* Bit 2: Multicast frame WoL */ +#define ETH_RXFLWOL_UCASTHASH (1 << 3) /* Bit 3: Unicast hash filter WoL */ +#define ETH_RXFLWOL_MCASTHASH (1 << 4) /* Bit 4: Multiicast hash filter WoL */ +#define ETH_RXFLWOL_PERF (1 << 5) /* Bit 5: Perfect addr match WoL */ + /* Bit 6: Reserved */ +#define ETH_RXFLWOL_RXFIL (1 << 7) /* Bit 7: Receive filter WoL */ +#define ETH_RXFLWOL_MPKT (1 << 8) /* Bit 8: Magic pkt filter WoL */ + /* Bits 9-31: Reserved */ +/* Hash filter table LSBs register (HASHFLL) AND Hash filter table MSBs register +* (HASHFLH) Are registers containing a 32-bit value with no bitfield. + */ + +/* Module control registers */ +/* Interrupt status register (INTST), Interrupt enable register (INTEN), Interrupt + * clear register (INTCLR), and Interrupt set register (INTSET) common bit field + * definition: + */ + +#define ETH_INT_RXOVR (1 << 0) /* Bit 0: RX overrun interrupt */ +#define ETH_INT_RXERR (1 << 1) /* Bit 1: RX error interrupt */ +#define ETH_INT_RXFIN (1 << 2) /* Bit 2: RX finished interrupt */ +#define ETH_INT_RXDONE (1 << 3) /* Bit 3: RX done interrupt */ +#define ETH_INT_TXUNR (1 << 4) /* Bit 4: TX underrun interrupt */ +#define ETH_INT_TXERR (1 << 5) /* Bit 5: TX error interrupt */ +#define ETH_INT_TXFIN (1 << 6) /* Bit 6: TX finished interrupt */ +#define ETH_INT_TXDONE (1 << 7) /* Bit 7: TX done interrupt */ + /* Bits 8-11: Reserved */ +#define ETH_INT_SOFT (1 << 12) /* Bit 12: Soft interrupt */ +#define ETH_INT_WKUP (1 << 13) /* Bit 13: Wakeup interrupt */ + /* Bits 14-31: Reserved */ +/* Power-down register */ + /* Bits 0-30: Reserved */ +#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */ + +/* Descriptors Offsets **************************************************************/ + +/* Tx descriptor offsets */ + +#define LPC17_TXDESC_PACKET 0x00 /* Base address of the Tx data buffer */ +#define LPC17_TXDESC_CONTROL 0x04 /* Control Information */ +#define LPC17_TXDESC_SIZE 0x08 /* Size in bytes of one Tx descriptor */ + +/* Tx status offsets */ + +#define LPC17_TXSTAT_INFO 0x00 /* Transmit status return flags */ +#define LPC17_TXSTAT_SIZE 0x04 /* Size in bytes of one Tx status */ + +/* Rx descriptor offsets */ + +#define LPC17_RXDESC_PACKET 0x00 /* Base address of the Rx data buffer */ +#define LPC17_RXDESC_CONTROL 0x04 /* Control Information */ +#define LPC17_RXDESC_SIZE 0x08 /* Size in bytes of one Rx descriptor */ + +/* Rx status offsets */ + +#define LPC17_RXSTAT_INFO 0x00 /* Receive status return flags */ +#define LPC17_RXSTAT_HASHCRC 0x04 /* Dest and source hash CRC */ +#define LPC17_RXSTAT_SIZE 0x08 /* Size in bytes of one Rx status */ + +/* Descriptor Bit Definitions *******************************************************/ + +/* Tx descriptor bit definitions */ + +#define TXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ +#define TXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) + +#define TXDESC_CONTROL_OVERRIDE (1 << 26 /* Bit 26: Per-frame override */ +#define TXDESC_CONTROL_HUGE (1 << 27) /* Bit 27: Enable huge frame size */ +#define TXDESC_CONTROL_PAD (1 << 28) /* Bit 28: Pad short frames */ +#define TXDESC_CONTROL_CRC (1 << 29) /* Bit 29: Append CRC */ +#define TXDESC_CONTROL_LAST (1 << 30) /* Bit 30: Last descriptor of a fragment */ +#define TXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate TxDone interrupt */ + +/* Tx status bit definitions */ + +#define TXSTAT_INFO_COLCNT_SHIFT (21) /* Bits 21-24: Number of collisions */ +#define TXSTAT_INFO_COLCNT_MASK (15 << TXSTAT_INFO_COLCNT_SHIFT) +#define TXSTAT_INFO_DEFER (1 << 25) /* Bit 25: Packet deffered */ +#define TXSTAT_INFO_EXCESSDEFER (1 << 26) /* Bit 26: Excessive packet defferals */ +#define TXSTAT_INFO_EXCESSCOL (1 << 27) /* Bit 27: Excessive packet collisions */ +#define TXSTAT_INFO_LATECOL (1 << 28) /* Bit 28: Out of window collision */ +#define TXSTAT_INFO_UNDERRUN (1 << 29) /* Bit 29: Tx underrun */ +#define TXSTAT_INFO_NODESC (1 << 30) /* Bit 29: No Tx descriptor available */ +#define TXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ + +/* Rx descriptor bit definitions */ + +#define RXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ +#define RXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) +#define RXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate RxDone interrupt */ + +/* Rx status bit definitions */ + +#define RXSTAT_SAHASHCRC_SHIFT (0) /* Bits 0-8: Hash CRC calculated from the source address */ +#define RXSTAT_SAHASHCRC_MASK (0x1ff << RXSTAT_SAHASHCRC_SHIFT) +#define RXSTAT_DAHASHCRC_SHIFT (16) /* Bits 16-24: Hash CRC calculated from the dest address */ +#define RXSTAT_DAHASHCRC_MASK (0x1ff << RXSTAT_DAHASHCRC_SHIFT) + +#define RXSTAT_INFO_RXSIZE_SHIFT (0) /* Bits 0-10: Size of actual data transferred */ +#define RXSTAT_INFO_RXSIZE_MASK (0x7ff << RXSTAT_INFO_RXSIZE_SHIFT) +#define RXSTAT_INFO_CONTROL (1 << 18) /* Bit 18: This is a control frame */ +#define RXSTAT_INFO_VLAN (1 << 19) /* Bit 19: This is a VLAN frame */ +#define RXSTAT_INFO_FAILFILTER (1 << 20) /* Bit 20: Frame failed Rx filter */ +#define RXSTAT_INFO_MULTICAST (1 << 21) /* Bit 21: This is a multicast frame */ +#define RXSTAT_INFO_BROADCAST (1 << 22) /* Bit 22: This is a broadcast frame */ +#define RXSTAT_INFO_CRCERROR (1 << 23) /* Bit 23: Received frame had a CRC error */ +#define RXSTAT_INFO_SYMBOLERROR (1 << 24) /* Bit 24: PHY reported bit error */ +#define RXSTAT_INFO_LENGTHERROR (1 << 25) /* Bit 25: Invalid frame length */ +#define RXSTAT_INFO_RANGEERROR (1 << 26) /* Bit 26: Exceeds maximum packet size */ +#define RXSTAT_INFO_ALIGNERROR (1 << 27) /* Bit 27: Alignment error */ +#define RXSTAT_INFO_OVERRUN (1 << 28) /* Bit 28: Receive overrun error */ +#define RXSTAT_INFO_NODESC (1 << 29) /* Bit 29: No Rx descriptor available */ +#define RXSTAT_INFO_LASTFLAG (1 << 30) /* Bit 30: Last fragment of a frame */ +#define RXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h new file mode 100644 index 000000000..4a14c1853 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h @@ -0,0 +1,417 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_gpdma.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ +#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ +#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ +#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ +#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ +#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ +#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ +#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ +#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ +#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ +#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ +#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ +#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ +#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ + +/* Channel Registers */ + +#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */ + +#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ +#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ +#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ +#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ +#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ + +#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) + +/* Register addresses ***************************************************************/ +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) +#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) +#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) +#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) +#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) +#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) +#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) +#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) +#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) +#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) +#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) +#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) +#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) +#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) + +/* Channel Registers */ + +#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) + +#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* DMA request connections */ + +#define DMA_REQ_SSP0TX (0) +#define DMA_REQ_SSP0RX (1) +#define DMA_REQ_SSP1TX (2) +#define DMA_REQ_SSP1RX (3) +#define DMA_REQ_ADC (4) +#define DMA_REQ_I2SCH0 (5) +#define DMA_REQ_I2SCH1 (6) +#define DMA_REQ_DAC (7) + +#define DMA_REQ_UART0TX (8) +#define DMA_REQ_UART0RX (9) +#define DMA_REQ_UART1TX (10) +#define DMA_REQ_UART1RX (11) +#define DMA_REQ_UART2TX (12) +#define DMA_REQ_UART2RX (13) +#define DMA_REQ_UART3TX (14) +#define DMA_REQ_UART3RX (15) + +#define DMA_REQ_MAT0p0 (8) +#define DMA_REQ_MAT0p1 (9) +#define DMA_REQ_MAT1p0 (10) +#define DMA_REQ_MAT1p1 (11) +#define DMA_REQ_MAT2p0 (12) +#define DMA_REQ_MAT2p1 (13) +#define DMA_REQ_MAT3p0 (14) +#define DMA_REQ_MAT3p1 (15) + +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ +/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, + * respectively. Bits 8-31 are reserved. + * + * DMA Interrupt Status Register + * DMA Interrupt Terminal Count Request Status Register + * DMA Interrupt Terminal Count Request Clear Register + * DMA Interrupt Error Status Register + * DMA Interrupt Error Clear Register + * DMA Raw Interrupt Terminal Count Status Register + * DMA Raw Error Interrupt Status Register + * DMA Enabled Channel Register + */ + +#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ + +/* For each of the following registers, bits 0-15 represent a set of encoded + * DMA sources. Bits 16-31 are reserved in each case. + * + * DMA Software Burst Request Register + * DMA Software Single Request Register + * DMA Software Last Burst Request Register + * DMA Software Last Single Request Register + * DMA Synchronization Register + */ + +#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) +#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) +#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) +#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) +#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) +#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) + +#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) +#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) +#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) +#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) +#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) +#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) +#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) +#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) + +#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) +#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) +#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) +#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) +#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) +#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) +#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) +#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) + +/* DMA Configuration Register */ + +#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ +#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ + /* Bits 2-31: Reserved */ +/* Channel Registers */ + +/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ +/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ +/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list + * item. Bits 0-1 must be zero. + */ + +/* DMA Channel Control Register */ + +#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ +#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) +#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ +#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) +#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ +#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) +#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ +#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) +#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ +#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) +#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ +#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ +#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ +#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ +#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ +#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ + +/* DMA Channel Configuration Register */ + + +#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ +#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ +#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) +#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */ +#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) +#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ +#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) +# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */ +# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */ +#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ +#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ +#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ +#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ +#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ + /* Bits 19-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h new file mode 100644 index 000000000..20b4ae380 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h @@ -0,0 +1,293 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_gpio.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* GPIO block register offsets ******************************************************/ + +#define LPC17_FIO0_OFFSET 0x0000 +#define LPC17_FIO1_OFFSET 0x0020 +#define LPC17_FIO2_OFFSET 0x0040 +#define LPC17_FIO3_OFFSET 0x0060 +#define LPC17_FIO4_OFFSET 0x0080 + +#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ +#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ +#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ +#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ +#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ + +/* GPIO interrupt block register offsets ********************************************/ + +#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) +#define LPC17_GPIOINT0_OFFSET 0x0080 +#define LPC17_GPIOINT2_OFFSET 0x00a0 + +#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ +#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ +#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ +#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ +#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ +#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ + +/* Register addresses ***************************************************************/ +/* GPIO block register addresses ****************************************************/ + +#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) +#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) +#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) +#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) +#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) + +#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) + +/* GPIO interrupt block register addresses ******************************************/ + +#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) +#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) + +#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) + +#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ + +#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P2.0-13 (P0.14-31 are reserved) */ + +#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Register bit definitions *********************************************************/ +/* GPIO block register bit definitions **********************************************/ + +/* Fast GPIO Port Direction control registers (FIODIR) */ +/* Fast Mask register for ports (FIOMASK) */ +/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ +/* Fast Port Output Set registers using FIOMASK (FIOSET) */ +/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ + +#define FIO(n) (1 << (n)) /* n=0,1,..31 */ + +/* GPIO interrupt block register bit definitions ************************************/ + +/* GPIO overall Interrupt Status (IOINTSTATUS) */ +#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ + /* Bit 1: Reserved */ +#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ + /* Bits 3-31: Reserved */ + +/* GPIO Interrupt Status for Rising edge (INTSTATR) + * GPIO Interrupt Status for Falling edge (INTSTATF) + * GPIO Interrupt Clear (INTCLR) + * GPIO Interrupt Enable for Rising edge (INTENR) + * GPIO Interrupt Enable for Falling edge (INTENF) + */ + +#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqinitialize(void); +#else +# define lpc17_gpioirqinitialize() +#endif + +/************************************************************************************ + * Name: lpc17_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int lpc17_configgpio(uint16_t cfgset); + +/************************************************************************************ + * Name: lpc17_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void lpc17_gpiowrite(uint16_t pinset, bool value); + +/************************************************************************************ + * Name: lpc17_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool lpc17_gpioread(uint16_t pinset); + +/************************************************************************************ + * Name: lpc17_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqenable(int irq); +#else +# define lpc17_gpioirqenable(irq) +#endif + +/************************************************************************************ + * Name: lpc17_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqdisable(int irq); +#else +# define lpc17_gpioirqdisable(irq) +#endif + +/************************************************************************************ + * Function: lpc17_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int lpc17_dumpgpio(uint16_t pinset, const char *msg); +#else +# define lpc17_dumpgpio(p,m) +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2c.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2c.h new file mode 100644 index 000000000..96b6f19b1 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2c.h @@ -0,0 +1,208 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_i2c.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January + * 2010, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-1 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2s.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2s.h new file mode 100644 index 000000000..ab9a30425 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_i2s.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_i2s + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc17_i2s.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h new file mode 100644 index 000000000..6ec4a6b20 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h @@ -0,0 +1,280 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ +#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ +#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ +#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ +#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ +#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ +#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ +#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ +#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ +#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ +#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ +#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ +#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ +#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ +#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ +#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ +#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ +#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ +#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ +#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ +#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ +#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ +#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ +#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ +#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ +#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ +#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ +#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ +#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ +#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ + +/* Register addresses ***************************************************************/ + +#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) +#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) +#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) +#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) +#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) +#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) +#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) +#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) +#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) +#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) +#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) +#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) +#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) +#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) +#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) +#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) +#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) +#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) +#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) +#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) +#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) +#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) +#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) +#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) +#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) +#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) +#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) +#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) +#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) +#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* There are no bit field definitions for the following registers because they support + * 32-bit values: + * + * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), + * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for + * channels 0, 1, 2 (no bit field definitions) + * + * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit + * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field + * definitions) + * + * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match + * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field + * definitions). + * + * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and + * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for + * channels 0, 1, 2 (no bit field definitions) + */ + +/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control + * clear address (CONCLR) common regiser bit definitions. + */ + +#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ +#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ +#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ +#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ +#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ + /* Bits 5-7: Reserved */ +#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ +#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ +#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ +#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ + /* Bits 13-15: Reserved */ +#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ +#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ +#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ +#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ + /* Bits 21-28: Reserved */ +#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ +#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ +#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ + +/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), + * and Event Control clear address (CAPCONCLR) common register bit defintions + */ + +#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ +#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ +#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ +#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ +#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ + /* Bits 24-31: Reserved +/* Dead time register */ + +#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ +#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) +#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ +#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) +#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ +#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) + /* Bits 30-31: reserved */ +/* Commutation Pattern register */ + +#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ +#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ + /* Bits 6-31: reserved */ + +/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), + * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), + * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) + * common bit field definitions + */ + +#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ +#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ +#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ + /* Bit 3: Reserved */ +#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ +#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ +#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ + /* Bit 7: Reserved */ +#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ +#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ +#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ + /* Bits 11-14: Reserved */ +#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ + /* Bits 16-31: Reserved */ + +/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and + * Count Control clear address (CNTCONCLR) common register bit definitions. + */ + +#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ + /* Bits 28-28: Reserved */ +#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ +#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ +#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ + +/* Capture clear address */ + +#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ +#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ +#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h new file mode 100644 index 000000000..d3bdf79ab --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h @@ -0,0 +1,71 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lp17_memorymap.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#if defined(LPC176x) +# include "chip/lpc176x_memorymap.h" +#elif defined(LPC178x) +# include "chip/lpc178x_memorymap.h" +#else +# error "Unrecognized LPC17xx family" +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h new file mode 100644 index 000000000..fb4a487c2 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h @@ -0,0 +1,71 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lp17_pinconfig.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#if defined(LPC176x) +# include "chip/lpc176x_pinconfig.h" +#elif defined(LPC178x) +# include "chip/lpc178x_pinconfig.h" +#else +# error "Unrecognized LPC17xx family" +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h new file mode 100644 index 000000000..d8b8e0d37 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h @@ -0,0 +1,635 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_pinconn.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ +#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ +#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ +#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ +#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ +#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ +#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ +#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ +#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ +#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ +#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ +#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ +#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ +#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ +#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ +#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ +#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ +#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ +#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ +#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ +#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ +#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ +#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ +#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) +#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) +#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) +#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) +#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) +#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) +#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) +#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) +#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) +#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) +#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) +#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) +#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) +#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) +#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) +#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) +#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) +#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) +#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) +#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) +#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) +#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) +#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) +#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ + +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + +#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) +#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) + +#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ +#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) +#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ +#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) +#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ +#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) +#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ +#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) +#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ +#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) +#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ +#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) +#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ +#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) +#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ +#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) +#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ +#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) +#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ +#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) +#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ +#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) +#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ +#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ +#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) + +/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ + +#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ +#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) +#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ +#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) +#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ +#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) +#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ +#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) +#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ +#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) +#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ +#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) +#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ +#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) +#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ +#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) +#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ +#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) +#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ +#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) +#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ +#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) +#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ +#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) +#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ +#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) +#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) +#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) + /* Bits 30-31: Reserved */ +/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ + +#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) +#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) +#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) +#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) +#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) + +/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ + +#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) +#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) +#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ +#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) +#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ +#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) +#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ +#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) +#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ +#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) +#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ +#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) +#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ +#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) +#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ +#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) +#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ +#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) +#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ +#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) +#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ +#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) +#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ +#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) +#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ +#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) +#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ +#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) +#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ +#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) + +/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ + +#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) +#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) +#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) +#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) +#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) +#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) +#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ +#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) +#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) +#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ +#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) +#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ +#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) +#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ +#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) +#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ +#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) +#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ +#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) +#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ +#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ + +#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-17: Reserved */ +#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ +#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) +#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ +#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ +/* No description of bits -- Does this register exist? */ + +/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ + +#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-23: Reserved */ +#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ +#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) +#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ +#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ + /* Bits 0-2: Reserved */ +#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ + /* Bits 4-31: Reserved */ +/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ + +#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ +#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ +#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ +#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ +#define PINCONN_PINMODE_MASK (3) + +#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) +#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) + +#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ +#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) +#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ +#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) +#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ +#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) +#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ +#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) +#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ +#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) +#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ +#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) +#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ +#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) +#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ +#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) +#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ +#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) +#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ +#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) +#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ +#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) +#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ +#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ +#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) + +/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ + +#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ +#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) +#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ +#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) +#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ +#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) +#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ +#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) +#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ +#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) +#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ +#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) +#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ +#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) +#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ +#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) +#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ +#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) +#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ +#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) +#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ +#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ + +#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ +#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) +#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ +#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ +#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ +#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) +#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ +#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) +#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ +#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ +#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) +#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ +#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) + +/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ + +#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ +#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) +#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ +#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) +#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ +#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) +#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ +#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) +#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ +#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) +#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ +#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) +#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ +#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) +#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ +#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) +#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ +#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) +#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ +#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) +#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ +#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) +#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ +#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) +#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ +#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) +#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ +#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) +#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ +#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) +#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ +#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) + +/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ + +#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ +#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) +#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ +#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) +#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ +#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) +#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ +#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) +#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ +#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) +#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ +#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Mode select register 5 (PINMODE5: 0x4002c054) + * Pin Mode select register 6 (PINMODE6: 0x4002c058) + * No bit definitions -- do these registers exist? + */ + +#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ + +#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-17: Reserved */ +#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ +#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) +#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ +#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ +/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ + +#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-23: Reserved */ +#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ +#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) +#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ +#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ + +#define PINCONN_ODMODE0_P0(n) (1 << (n)) + +#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ +#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ +#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ +#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ +#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ +#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ +#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ +#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ +#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ +#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ +#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ +#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ + /* Bits 12-14: Reserved */ +#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ +#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ +#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ +#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ +#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ +#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ +#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ +#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ +#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ +#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ +#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ +#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ + /* Bits 27-28: Reserved */ +#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ +#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ + /* Bit 31: Reserved */ +/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ + +#define PINCONN_ODMODE1_P1(n) (1 << (n)) + +#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ +#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ + /* Bits 2-3: Reserved */ +#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ + /* Bits 5-7: Reserved */ +#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ +#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ +#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ + /* Bits 11-13: Reserved */ +#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ +#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ +#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ +#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ +#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ +#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ +#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ +#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ +#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ +#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ +#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ +#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ +#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ +#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ +#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ +#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ +#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ +#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ + +/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ + +#define PINCONN_ODMODE2_P2(n) (1 << (n)) + +#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ +#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ +#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ +#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ +#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ +#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ +#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ +#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ +#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ +#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ +#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ +#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ +#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ +#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ + /* Bits 14-31: Reserved */ +/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ + +#define PINCONN_ODMODE3_P3(n) (1 << (n)) + /* Bits 0-24: Reserved */ +#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ +#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ + /* Bits 17-31: Reserved */ +/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ + +#define PINCONN_ODMODE4_P4(n) (1 << (n)) + /* Bits 0-27: Reserved */ +#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ +#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ + /* Bits 30-31: Reserved */ +/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ + +#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch + * filtering/slew rate control */ +#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch + * filtering/slew rate control */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pwm.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pwm.h new file mode 100644 index 000000000..8a7931104 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pwm.h @@ -0,0 +1,63 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_pwm.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc17_pwm.h" +#include "chip/lpc17_mcpwm.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h new file mode 100644 index 000000000..4179ac965 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_qei.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_qei.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ +#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ +#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ +#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ +#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ +#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ +#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ +#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ +#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ +#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ +#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ +#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ +#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ +#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ +#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ + +/* Interrupt registers */ + +#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ +#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ +#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ +#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ + +/* Register addresses ***************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) +#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) +#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) +#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) +#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) +#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) +#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) +#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) +#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) +#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) +#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) +#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) +#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) +#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) +#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) + +/* Interrupt registers */ + +#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) +#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) +#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) +#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) +#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) +#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit integer values and have no bit fields defined + * in this section: + * + * Position register (POS) + * Maximum position register (MAXPOS) + * Position compare register 0 (CMPOS0) + * Position compare register 1 (CMPOS) + * Position compare register 2 (CMPOS2) + * Index count register (INXCNT) + * Index compare register (INXCMP) + * Velocity timer reload register (LOAD) + * Velocity timer register (TIME) + * Velocity counter register (VEL) + * Velocity capture register (CAP) + * Velocity compare register (VELCOMP) + * Digital filter register (FILTER) + */ + +/* Control registers */ +/* Control register */ + +#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ +#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ +#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ +#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ + /* Bits 4-31: reserved */ +/* Encoder status register */ + +#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ + /* Bits 1-31: reserved */ +/* Configuration register */ + +#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ +#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ +#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ +#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ + /* Bits 4-31: reserved */ +/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ + +/* Interrupt registers */ +/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), + * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt + * status clear register (CLR), and Interrupt status set register (SET) common + * bit definitions. + */ + +#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ +#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ +#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ +#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ +#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ +#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ +#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ +#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ +#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ +#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ +#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ +#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ +#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ + /* Bits 13-31: reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rit.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rit.h new file mode 100644 index 000000000..00029f8fe --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rit.h @@ -0,0 +1,92 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_rit.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ +#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ +#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ +#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ + +/* Register addresses ***************************************************************/ + +#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) +#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) +#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) +#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Compare register (Bits 0-31: value compared to the counter) */ + +/* Mask register (Bits 0-31: 32-bit mask value) */ + +/* Control register */ + +#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ +#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ +#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ +#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ + /* Bits 4-31: Reserved */ +/* 32-bit counter (Bits 0-31: 32-bit up counter) */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h new file mode 100644 index 000000000..ddc44d59f --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_rtc.h @@ -0,0 +1,270 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_rtc.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Miscellaneous registers */ + +#define LPC17_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */ +#define LPC17_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */ +#define LPC17_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */ +#define LPC17_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */ +#define LPC17_RTC_AUXEN_OFFSET 0x0058 /* RTC Auxiliary Enable register */ +#define LPC17_RTC_AUX_OFFSET 0x005c /* RTC Auxiliary control register */ + +/* Consolidated time registers */ + +#define LPC17_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */ +#define LPC17_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */ +#define LPC17_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */ + +/* Time counter registers */ + +#define LPC17_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */ +#define LPC17_RTC_MIN_OFFSET 0x0024 /* Minutes Register */ +#define LPC17_RTC_HOUR_OFFSET 0x0028 /* Hours Register */ +#define LPC17_RTC_DOM_OFFSET 0x002c /* Day of Month Register */ +#define LPC17_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */ +#define LPC17_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */ +#define LPC17_RTC_MONTH_OFFSET 0x0038 /* Months Register */ +#define LPC17_RTC_YEAR_OFFSET 0x003c /* Years Register */ +#define LPC17_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */ + +/* General purpose registers */ + +#define LPC17_RTC_GPREG0_OFFSET 0x0044 /* General Purpose Register 0 */ +#define LPC17_RTC_GPREG1_OFFSET 0x0048 /* General Purpose Register 1 */ +#define LPC17_RTC_GPREG2_OFFSET 0x004c /* General Purpose Register 2 */ +#define LPC17_RTC_GPREG3_OFFSET 0x0050 /* General Purpose Register 3 */ +#define LPC17_RTC_GPREG4_OFFSET 0x0054 /* General Purpose Register 4 */ + +/* Alarm register group */ + +#define LPC17_RTC_ALSEC_OFFSET 0x0060 /* Alarm value for Seconds */ +#define LPC17_RTC_ALMIN_OFFSET 0x0064 /* Alarm value for Minutes */ +#define LPC17_RTC_ALHOUR_OFFSET 0x0068 /* Alarm value for Hours */ +#define LPC17_RTC_ALDOM_OFFSET 0x006c /* Alarm value for Day of Month */ +#define LPC17_RTC_ALDOW_OFFSET 0x0070 /* Alarm value for Day of Week */ +#define LPC17_RTC_ALDOY_OFFSET 0x0074 /* Alarm value for Day of Year */ +#define LPC17_RTC_ALMON_OFFSET 0x0078 /* Alarm value for Months */ +#define LPC17_RTC_ALYEAR_OFFSET 0x007c /* Alarm value for Year */ + +/* Register addresses ***************************************************************/ +/* Miscellaneous registers */ + +#define LPC17_RTC_ILR (LPC17_RTC_BASE+LPC17_RTC_ILR_OFFSET) +#define LPC17_RTC_CCR (LPC17_RTC_BASE+LPC17_RTC_CCR_OFFSET) +#define LPC17_RTC_CIIR (LPC17_RTC_BASE+LPC17_RTC_CIIR_OFFSET) +#define LPC17_RTC_AMR (LPC17_RTC_BASE+LPC17_RTC_AMR_OFFSET) +#define LPC17_RTC_AUXEN (LPC17_RTC_BASE+LPC17_RTC_AUXEN_OFFSET) +#define LPC17_RTC_AUX (LPC17_RTC_BASE+LPC17_RTC_AUX_OFFSET) + +/* Consolidated time registers */ + +#define LPC17_RTC_CTIME0 (LPC17_RTC_BASE+LPC17_RTC_CTIME0_OFFSET) +#define LPC17_RTC_CTIME1 (LPC17_RTC_BASE+LPC17_RTC_CTIME1_OFFSET) +#define LPC17_RTC_CTIME2 (LPC17_RTC_BASE+LPC17_RTC_CTIME2_OFFSET) + +/* Time counter registers */ + +#define LPC17_RTC_SEC (LPC17_RTC_BASE+LPC17_RTC_SEC_OFFSET) +#define LPC17_RTC_MIN (LPC17_RTC_BASE+LPC17_RTC_MIN_OFFSET) +#define LPC17_RTC_HOUR (LPC17_RTC_BASE+LPC17_RTC_HOUR_OFFSET) +#define LPC17_RTC_DOM (LPC17_RTC_BASE+LPC17_RTC_DOM_OFFSET) +#define LPC17_RTC_DOW (LPC17_RTC_BASE+LPC17_RTC_DOW_OFFSET) +#define LPC17_RTC_DOY (LPC17_RTC_BASE+LPC17_RTC_DOY_OFFSET) +#define LPC17_RTC_MONTH (LPC17_RTC_BASE+LPC17_RTC_MONTH_OFFSET) +#define LPC17_RTC_YEAR (LPC17_RTC_BASE+LPC17_RTC_YEAR_OFFSET) +#define LPC17_RTC_CALIB (LPC17_RTC_BASE+LPC17_RTC_CALIB_OFFSET) + +/* General purpose registers */ + +#define LPC17_RTC_GPREG0 (LPC17_RTC_BASE+LPC17_RTC_GPREG0_OFFSET) +#define LPC17_RTC_GPREG1 (LPC17_RTC_BASE+LPC17_RTC_GPREG1_OFFSET) +#define LPC17_RTC_GPREG2 (LPC17_RTC_BASE+LPC17_RTC_GPREG2_OFFSET) +#define LPC17_RTC_GPREG3 (LPC17_RTC_BASE+LPC17_RTC_GPREG3_OFFSET) +#define LPC17_RTC_GPREG4 (LPC17_RTC_BASE+LPC17_RTC_GPREG4_OFFSET) + +/* Alarm register group */ + +#define LPC17_RTC_ALSEC (LPC17_RTC_BASE+LPC17_RTC_ALSEC_OFFSET) +#define LPC17_RTC_ALMIN (LPC17_RTC_BASE+LPC17_RTC_ALMIN_OFFSET) +#define LPC17_RTC_ALHOUR (LPC17_RTC_BASE+LPC17_RTC_ALHOUR_OFFSET) +#define LPC17_RTC_ALDOM (LPC17_RTC_BASE+LPC17_RTC_ALDOM_OFFSET) +#define LPC17_RTC_ALDOW (LPC17_RTC_BASE+LPC17_RTC_ALDOW_OFFSET) +#define LPC17_RTC_ALDOY (LPC17_RTC_BASE+LPC17_RTC_ALDOY_OFFSET) +#define LPC17_RTC_ALMON (LPC17_RTC_BASE+LPC17_RTC_ALMON_OFFSET) +#define LPC17_RTC_ALYEAR (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit values and have no bit fields to be defined: + * + * General Purpose Register 0 + * General Purpose Register 1 + * General Purpose Register 2 + * General Purpose Register 3 + * General Purpose Register 4 + */ + +/* Miscellaneous registers */ +/* Interrupt Location Register */ + +#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */ +#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */ + /* Bits 2-31: Reserved */ +/* Clock Control Register */ + +#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */ +#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */ + /* Bits 2-3: Internal test mode controls */ +#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */ + /* Bits 5-31: Reserved */ +/* Counter Increment Interrupt Register */ + +#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */ +#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */ +#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */ +#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */ +#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */ +#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */ +#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */ +#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */ + /* Bits 8-31: Reserved */ +/* Alarm Mask Register */ + +#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */ +#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */ +#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */ +#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */ +#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */ +#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */ +#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */ +#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */ + /* Bits 8-31: Reserved */ +/* RTC Auxiliary Enable register */ + /* Bits 0-3: Reserved */ +#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */ + /* Bits 5-31: Reserved */ +/* RTC Auxiliary control register */ + /* Bits 0-3: Reserved */ +#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */ + /* Bits 5-31: Reserved */ +/* Consolidated time registers */ +/* Consolidated Time Register 0 */ + +#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */ +#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT) + /* Bits 6-7: Reserved */ +#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */ +#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT) + /* Bits 14-15: Reserved */ +#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */ +#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT) + /* Bits 21-23: Reserved */ +#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */ +#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT) + /* Bits 27-31: Reserved */ +/* Consolidated Time Register 1 */ + +#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */ +#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT) + /* Bits 5-7: Reserved */ +#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */ +#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT) + /* Bits 12-15: Reserved */ +#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ +#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) + /* Bits 28-31: Reserved */ +/* Consolidated Time Register 2 */ + +#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ +#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) + /* Bits 12-31: Reserved */ +/* Time counter registers */ + +#define RTC_SEC_MASK (0x003f) +#define RTC_MIN_MASK (0x003f) +#define RTC_HOUR_MASK (0x001f) +#define RTC_DOM_MASK (0x001f) +#define RTC_DOW_MASK (0x0007) +#define RTC_DOY_MASK (0x01ff) +#define RTC_MONTH_MASK (0x000f) +#define RTC_YEAR_MASK (0x0fff) + +/* Calibration Value Register */ + +#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ +#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) +#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ + /* Bits 18-31: Reserved */ +/* Alarm register group */ + +#define RTC_ALSEC_MASK (0x003f) +#define RTC_ALMIN_MASK (0x003f) +#define RTC_ALHOUR_MASK (0x001f) +#define RTC_ALDOM_MASK (0x001f) +#define RTC_ALDOW_MASK (0x0007) +#define RTC_ALDOY_MASK (0x01ff) +#define RTC_ALMON_MASK (0x000f) +#define RTC_ALYEAR_MASK (0x0fff) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_spi.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_spi.h new file mode 100644 index 000000000..716e70cb5 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_spi.h @@ -0,0 +1,141 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_spi.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ +#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ +#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ +#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ +#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ +#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ +#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) +#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) +#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) +#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) +#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) +#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) +#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Control Register */ + /* Bits 0-1: Reserved */ +#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ +#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ +#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ +#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ +#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ +#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ +#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ +#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) +# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ +# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ +# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ +# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ +# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ +# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ +# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ +# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ +# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ + /* Bits 12-31: Reserved */ +/* SPI Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Data Register */ + +#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ +#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ + /* Bits 8-31: Reserved */ +/* SPI Clock Counter Register */ + +#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ + /* Bits 8-31: Reserved */ +/* SPI Test Control Register */ + /* Bit 0: Reserved */ +#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ +#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) + /* Bits 8-31: Reserved */ +/* SPI Test Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Interrupt Register */ + +#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ + /* Bits 1-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ssp.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ssp.h new file mode 100644 index 000000000..e97a670a8 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_ssp.h @@ -0,0 +1,174 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_ssp.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* 8 frame FIFOs for both transmit and receive */ + +#define LPC17_SSP_FIFOSZ 8 + +/* Register offsets *****************************************************************/ + +#define LPC17_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ +#define LPC17_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ +#define LPC17_SSP_DR_OFFSET 0x0008 /* Data Register */ +#define LPC17_SSP_SR_OFFSET 0x000c /* Status Register */ +#define LPC17_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ +#define LPC17_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */ +#define LPC17_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ +#define LPC17_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ +#define LPC17_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ +#define LPC17_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_SSP0_CR0 (LPC17_SSP0_BASE+LPC17_SSP_CR0_OFFSET) +#define LPC17_SSP0_CR1 (LPC17_SSP0_BASE+LPC17_SSP_CR1_OFFSET) +#define LPC17_SSP0_DR (LPC17_SSP0_BASE+LPC17_SSP_DR_OFFSET) +#define LPC17_SSP0_SR (LPC17_SSP0_BASE+LPC17_SSP_SR_OFFSET) +#define LPC17_SSP0_CPSR (LPC17_SSP0_BASE+LPC17_SSP_CPSR_OFFSET) +#define LPC17_SSP0_IMSC (LPC17_SSP0_BASE+LPC17_SSP_IMSC_OFFSET) +#define LPC17_SSP0_RIS (LPC17_SSP0_BASE+LPC17_SSP_RIS_OFFSET) +#define LPC17_SSP0_MIS (LPC17_SSP0_BASE+LPC17_SSP_MIS_OFFSET) +#define LPC17_SSP0_ICR (LPC17_SSP0_BASE+LPC17_SSP_ICR_OFFSET) +#define LPC17_SSP0_DMACR (LPC17_SSP0_BASE+LPC17_SSP_DMACR_OFFSET) + +#define LPC17_SSP1_CR0 (LPC17_SSP1_BASE+LPC17_SSP_CR0_OFFSET) +#define LPC17_SSP1_CR1 (LPC17_SSP1_BASE+LPC17_SSP_CR1_OFFSET) +#define LPC17_SSP1_DR (LPC17_SSP1_BASE+LPC17_SSP_DR_OFFSET) +#define LPC17_SSP1_SR (LPC17_SSP1_BASE+LPC17_SSP_SR_OFFSET) +#define LPC17_SSP1_CPSR (LPC17_SSP1_BASE+LPC17_SSP_CPSR_OFFSET) +#define LPC17_SSP1_IMSC (LPC17_SSP1_BASE+LPC17_SSP_IMSC_OFFSET) +#define LPC17_SSP1_RIS (LPC17_SSP1_BASE+LPC17_SSP_RIS_OFFSET) +#define LPC17_SSP1_MIS (LPC17_SSP1_BASE+LPC17_SSP_MIS_OFFSET) +#define LPC17_SSP1_ICR (LPC17_SSP1_BASE+LPC17_SSP_ICR_OFFSET) +#define LPC17_SSP1_DMACR (LPC17_SSP1_BASE+LPC17_SSP_DMACR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Control Register 0 */ + +#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */ +#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT) +# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT) +#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */ +#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT) +#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */ +#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */ +#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */ +#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT) + /* Bits 8-31: Reserved */ +/* Control Register 1 */ + +#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ +#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */ +#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ +#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ + /* Bits 4-31: Reserved */ +/* Data Register */ + +#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ + /* Bits 16-31: Reserved */ +/* Status Register */ + +#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ +#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ +#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ +#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ +#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ + /* Bits 5-31: Reserved */ +/* Clock Prescale Register */ + +#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */ + /* Bits 8-31: Reserved */ +/* Common format for interrupt control registers: + * + * Interrupt Mask Set and Clear Register (IMSC) + * Raw Interrupt Status Register (RIS) + * Masked Interrupt Status Register (MIS) + * Interrupt Clear Register (ICR) + */ + +#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */ +#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */ +#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */ +#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */ + /* Bits 4-31: Reserved */ +/* DMA Control Register */ + +#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */ +#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h new file mode 100644 index 000000000..15be1e672 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h @@ -0,0 +1,494 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_syscon.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ +#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ +#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ + +#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ +#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ +#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ +#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ +#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ + +#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ +#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ +#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ + +/* Register addresses ***************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) +#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) +#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) +#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) + +#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) +#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) +#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) +#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) +#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) +#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) + +#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) +#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET) +#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET) + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Flash accelerator module */ + /* Bits 0-11: Reserved */ +#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ +#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) +# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock + * (Up to 120 Mhz for LPC1759/69 only */ +# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ + /* Bits 16-31: Reserved */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: + * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. + * 1:User mode. The on-chip Flash memory is mapped to address 0 */ + /* Bits 1-31: Reserved */ + +/* Clocking and power control -- Clock source selection */ + +#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ +#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) +# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ +# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ +# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ + /* Bits 2-31: Reserved */ + +/* Clocking and power control - Phase locked loops */ +/* PLL0/1 Control register */ + +#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ +#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ + /* Bits 2-31: Reserved */ +/* PLL0 Configuration register */ + +#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ +#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ +#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) + /* Bits 24-31: Reserved */ +/* PLL1 Configuration register */ + +#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ +#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) +#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ +#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) + /* Bits 7-31: Reserved */ +/* PLL0 Status register */ + +#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ +#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ +#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) +#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ +#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ +#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ + /* Bits 27-31: Reserved */ +/* PLL1 Status register */ + +#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ +#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) +#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ +#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) + /* Bit 7: Reserved */ +#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ +#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ +#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ + /* Bits 11-31: Reserved */ +/* PLL0/1 Feed register */ + +#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ +#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) + /* Bits 8-31: Reserved */ +/* Clocking and power control -- Clock dividers */ +/* CPU Clock Configuration register */ + +#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) +# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ + /* Bits 8-31: Reserved */ +/* USB Clock Configuration register */ + +#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ +#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) +# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ +# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ +# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ + /* Bits 8-31: Reserved */ +/* Peripheral Clock Selection registers 0 and 1 */ + +#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ +#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ +#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ +#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_MASK (3) + +#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ +#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) +#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ +#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) +#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ +#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) +#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ +#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) +#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ +#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) + /* Bits 10-11: Reserved */ +#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ +#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) +#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ +#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) +#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ +#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) + /* Bits 18-19: Reserved */ +#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ +#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) +#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ +#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) +#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ +#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) +#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ +#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) +#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ +#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) +#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ +#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) + +#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ +#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) +#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ +#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) +#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ +#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) +#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ +#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) + /* Bits 8-9: Reserved */ +#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ +#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) +#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ +#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) +#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ +#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) +#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ +#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) +#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ +#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) +#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ +#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) +#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ +#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) + /* Bits 24-25: Reserved */ +#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ +#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) +#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ +#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) +#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ +#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) + +/* Clocking and power control - Peripheral power control registers */ +/* Power Control Register */ + +#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ +#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ +#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ +#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ +#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ + /* Bits 5-7: Reserved */ +#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ +#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ +#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ +#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ + /* Bits 12-31: Reserved */ +/* Power Control for Peripherals Register */ + + /* Bit 0: Reserved */ +#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ +#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ +#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ +#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ + /* Bit 5: Reserved */ +#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ +#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ +#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ +#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ +#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ + /* Bit 11: Reserved */ +#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ +#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ +#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ +#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ +#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ +#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ +#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ +#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ + /* Bit 20: Reserved */ +#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ +#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ +#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ +#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ +#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ +#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ +#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ + /* Bit 28: Reserved */ +#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ +#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ +#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ + +/* More clocking and power control -- Utility */ + +#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ +#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) +# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ +# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ +# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ +# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ +# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ +#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ +#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) +# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ +#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ +#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ + /* Bits 10-31: Reserved */ +/* System control registers -- External Interrupts */ +/* External Interrupt Flag register */ + +#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ +#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ +#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ +#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ + /* Bits 4-31: Reserved */ +/* External Interrupt Mode register */ + +#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ +#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ +#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ +#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ + /* Bits 4-31: Reserved */ +/* External Interrupt Polarity register */ + +#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ + /* Bits 4-31: Reserved */ +/* System control registers -- Reset */ +/* Reset Source Identification Register */ + +#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ +#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ +#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ +#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ + /* Bits 4-31: Reserved */ +/* System control registers -- Syscon Miscellaneous Registers */ + + /* Bits 0-3: Reserved */ +#define SYSCON_SCS_OSCRANGE (1 << 4) /* Bit 4: Main oscillator range select */ +#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ +#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ + /* Bits 7-31: Reserved */ +/* Device Interrupt Registers */ +/* USB Interrupt Status register */ + +#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ +#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ +#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ +#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ +#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ +#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ +#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ + /* Bit 7: Reserved */ +#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ + /* Bits 9-30: Reserved */ +#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ + +/* DMA Request Select Register */ + +#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ +#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ +#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ +#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ +#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ +#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ +#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ +#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ + /* Bits 8-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_timer.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_timer.h new file mode 100644 index 000000000..455133ee7 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_timer.h @@ -0,0 +1,250 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_timer.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC17_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC17_TMR_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC17_TMR_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC17_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC17_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC17_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC17_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC17_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC17_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC17_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC17_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC17_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC17_TMR_EMR_OFFSET 0x003c /* External Match Register */ +#define LPC17_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_TMR0_IR (LPC17_TMR0_BASE+LPC17_TMR_IR_OFFSET) +#define LPC17_TMR0_TCR (LPC17_TMR0_BASE+LPC17_TMR_TCR_OFFSET) +#define LPC17_TMR0_TC (LPC17_TMR0_BASE+LPC17_TMR_TC_OFFSET) +#define LPC17_TMR0_PR (LPC17_TMR0_BASE+LPC17_TMR_PR_OFFSET) +#define LPC17_TMR0_PC (LPC17_TMR0_BASE+LPC17_TMR_PC_OFFSET) +#define LPC17_TMR0_MCR (LPC17_TMR0_BASE+LPC17_TMR_MCR_OFFSET) +#define LPC17_TMR0_MR0 (LPC17_TMR0_BASE+LPC17_TMR_MR0_OFFSET) +#define LPC17_TMR0_MR1 (LPC17_TMR0_BASE+LPC17_TMR_MR1_OFFSET) +#define LPC17_TMR0_MR2 (LPC17_TMR0_BASE+LPC17_TMR_MR2_OFFSET) +#define LPC17_TMR0_MR3 (LPC17_TMR0_BASE+LPC17_TMR_MR3_OFFSET) +#define LPC17_TMR0_CCR (LPC17_TMR0_BASE+LPC17_TMR_CCR_OFFSET) +#define LPC17_TMR0_CR0 (LPC17_TMR0_BASE+LPC17_TMR_CR0_OFFSET) +#define LPC17_TMR0_CR1 (LPC17_TMR0_BASE+LPC17_TMR_CR1_OFFSET) +#define LPC17_TMR0_EMR (LPC17_TMR0_BASE+LPC17_TMR_EMR_OFFSET) +#define LPC17_TMR0_CTCR (LPC17_TMR0_BASE+LPC17_TMR_CTCR_OFFSET) + +#define LPC17_TMR1_IR (LPC17_TMR1_BASE+LPC17_TMR_IR_OFFSET) +#define LPC17_TMR1_TCR (LPC17_TMR1_BASE+LPC17_TMR_TCR_OFFSET) +#define LPC17_TMR1_TC (LPC17_TMR1_BASE+LPC17_TMR_TC_OFFSET) +#define LPC17_TMR1_PR (LPC17_TMR1_BASE+LPC17_TMR_PR_OFFSET) +#define LPC17_TMR1_PC (LPC17_TMR1_BASE+LPC17_TMR_PC_OFFSET) +#define LPC17_TMR1_MCR (LPC17_TMR1_BASE+LPC17_TMR_MCR_OFFSET) +#define LPC17_TMR1_MR0 (LPC17_TMR1_BASE+LPC17_TMR_MR0_OFFSET) +#define LPC17_TMR1_MR1 (LPC17_TMR1_BASE+LPC17_TMR_MR1_OFFSET) +#define LPC17_TMR1_MR2 (LPC17_TMR1_BASE+LPC17_TMR_MR2_OFFSET) +#define LPC17_TMR1_MR3 (LPC17_TMR1_BASE+LPC17_TMR_MR3_OFFSET) +#define LPC17_TMR1_CCR (LPC17_TMR1_BASE+LPC17_TMR_CCR_OFFSET) +#define LPC17_TMR1_CR0 (LPC17_TMR1_BASE+LPC17_TMR_CR0_OFFSET) +#define LPC17_TMR1_CR1 (LPC17_TMR1_BASE+LPC17_TMR_CR1_OFFSET) +#define LPC17_TMR1_EMR (LPC17_TMR1_BASE+LPC17_TMR_EMR_OFFSET) +#define LPC17_TMR1_CTCR (LPC17_TMR1_BASE+LPC17_TMR_CTCR_OFFSET) + +#define LPC17_TMR2_IR (LPC17_TMR2_BASE+LPC17_TMR_IR_OFFSET) +#define LPC17_TMR2_TCR (LPC17_TMR2_BASE+LPC17_TMR_TCR_OFFSET) +#define LPC17_TMR2_TC (LPC17_TMR2_BASE+LPC17_TMR_TC_OFFSET) +#define LPC17_TMR2_PR (LPC17_TMR2_BASE+LPC17_TMR_PR_OFFSET) +#define LPC17_TMR2_PC (LPC17_TMR2_BASE+LPC17_TMR_PC_OFFSET) +#define LPC17_TMR2_MCR (LPC17_TMR2_BASE+LPC17_TMR_MCR_OFFSET) +#define LPC17_TMR2_MR0 (LPC17_TMR2_BASE+LPC17_TMR_MR0_OFFSET) +#define LPC17_TMR2_MR1 (LPC17_TMR2_BASE+LPC17_TMR_MR1_OFFSET) +#define LPC17_TMR2_MR2 (LPC17_TMR2_BASE+LPC17_TMR_MR2_OFFSET) +#define LPC17_TMR2_MR3 (LPC17_TMR2_BASE+LPC17_TMR_MR3_OFFSET) +#define LPC17_TMR2_CCR (LPC17_TMR2_BASE+LPC17_TMR_CCR_OFFSET) +#define LPC17_TMR2_CR0 (LPC17_TMR2_BASE+LPC17_TMR_CR0_OFFSET) +#define LPC17_TMR2_CR1 (LPC17_TMR2_BASE+LPC17_TMR_CR1_OFFSET) +#define LPC17_TMR2_EMR (LPC17_TMR2_BASE+LPC17_TMR_EMR_OFFSET) +#define LPC17_TMR2_CTCR (LPC17_TMR2_BASE+LPC17_TMR_CTCR_OFFSET) + +#define LPC17_TMR3_IR (LPC17_TMR3_BASE+LPC17_TMR_IR_OFFSET) +#define LPC17_TMR3_TCR (LPC17_TMR3_BASE+LPC17_TMR_TCR_OFFSET) +#define LPC17_TMR3_TC (LPC17_TMR3_BASE+LPC17_TMR_TC_OFFSET) +#define LPC17_TMR3_PR (LPC17_TMR3_BASE+LPC17_TMR_PR_OFFSET) +#define LPC17_TMR3_PC (LPC17_TMR3_BASE+LPC17_TMR_PC_OFFSET) +#define LPC17_TMR3_MCR (LPC17_TMR3_BASE+LPC17_TMR_MCR_OFFSET) +#define LPC17_TMR3_MR0 (LPC17_TMR3_BASE+LPC17_TMR_MR0_OFFSET) +#define LPC17_TMR3_MR1 (LPC17_TMR3_BASE+LPC17_TMR_MR1_OFFSET) +#define LPC17_TMR3_MR2 (LPC17_TMR3_BASE+LPC17_TMR_MR2_OFFSET) +#define LPC17_TMR3_MR3 (LPC17_TMR3_BASE+LPC17_TMR_MR3_OFFSET) +#define LPC17_TMR3_CCR (LPC17_TMR3_BASE+LPC17_TMR_CCR_OFFSET) +#define LPC17_TMR3_CR0 (LPC17_TMR3_BASE+LPC17_TMR_CR0_OFFSET) +#define LPC17_TMR3_CR1 (LPC17_TMR3_BASE+LPC17_TMR_CR1_OFFSET) +#define LPC17_TMR3_EMR (LPC17_TMR3_BASE+LPC17_TMR_EMR_OFFSET) +#define LPC17_TMR3_CTCR (LPC17_TMR3_BASE+LPC17_TMR_CTCR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + */ + +/* Interrupt Register */ + +#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */ +#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */ +#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */ +#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */ +#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */ +#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */ + /* Bits 6-31: Reserved */ +/* Timer Control Register */ + +#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */ +#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */ + /* Bits 2-31: Reserved */ +/* Match Control Register */ + +#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ + /* Bits 12-31: Reserved */ +/* Capture Control Register */ + +#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ +#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ +#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* External Match Register */ + +#define TMR_EMR_NOTHING (0) /* Do Nothing */ +#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ +#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ +#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ + +#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ +#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ +#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ +#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ +#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ +#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) +# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) +#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ +#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) +#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ +#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) +#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ +#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) + /* Bits 12-31: Reserved */ +/* Count Control Register */ + +#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) +# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ +# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) +# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h new file mode 100644 index 000000000..1def0d009 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_uart.h @@ -0,0 +1,339 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_uart.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ +#define LPC17_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ +#define LPC17_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ +#define LPC17_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ +#define LPC17_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ +#define LPC17_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ +#define LPC17_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ +#define LPC17_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ +#define LPC17_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ +#define LPC17_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ +#define LPC17_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ +#define LPC17_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ +#define LPC17_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ +#define LPC17_UART_ICR_OFFSET 0x0024 /* IrDA Control Register (UART0,2,3 only) */ +#define LPC17_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ +#define LPC17_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ +#define LPC17_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ +#define LPC17_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ +#define LPC17_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ +#define LPC17_UART_FIFOLVL_OFFSET 0x0058 /* FIFO Level register (all) */ + +/* Register addresses ***************************************************************/ + +#define LPC17_UART0_RBR (LPC17_UART0_BASE+LPC17_UART_RBR_OFFSET) +#define LPC17_UART0_THR (LPC17_UART0_BASE+LPC17_UART_THR_OFFSET) +#define LPC17_UART0_DLL (LPC17_UART0_BASE+LPC17_UART_DLL_OFFSET) +#define LPC17_UART0_DLM (LPC17_UART0_BASE+LPC17_UART_DLM_OFFSET) +#define LPC17_UART0_IER (LPC17_UART0_BASE+LPC17_UART_IER_OFFSET) +#define LPC17_UART0_IIR (LPC17_UART0_BASE+LPC17_UART_IIR_OFFSET) +#define LPC17_UART0_FCR (LPC17_UART0_BASE+LPC17_UART_FCR_OFFSET) +#define LPC17_UART0_LCR (LPC17_UART0_BASE+LPC17_UART_LCR_OFFSET) +#define LPC17_UART0_LSR (LPC17_UART0_BASE+LPC17_UART_LSR_OFFSET) +#define LPC17_UART0_SCR (LPC17_UART0_BASE+LPC17_UART_SCR_OFFSET) +#define LPC17_UART0_ACR (LPC17_UART0_BASE+LPC17_UART_ACR_OFFSET) +#define LPC17_UART0_ICR (LPC17_UART0_BASE+LPC17_UART_ICR_OFFSET) +#define LPC17_UART0_FDR (LPC17_UART0_BASE+LPC17_UART_FDR_OFFSET) +#define LPC17_UART0_TER (LPC17_UART0_BASE+LPC17_UART_TER_OFFSET) +#define LPC17_UART0_FIFOLVL (LPC17_UART0_BASE+LPC17_UART_FIFOLVL_OFFSET) + +#define LPC17_UART1_RBR (LPC17_UART1_BASE+LPC17_UART_RBR_OFFSET) +#define LPC17_UART1_THR (LPC17_UART1_BASE+LPC17_UART_THR_OFFSET) +#define LPC17_UART1_DLL (LPC17_UART1_BASE+LPC17_UART_DLL_OFFSET) +#define LPC17_UART1_DLM (LPC17_UART1_BASE+LPC17_UART_DLM_OFFSET) +#define LPC17_UART1_IER (LPC17_UART1_BASE+LPC17_UART_IER_OFFSET) +#define LPC17_UART1_IIR (LPC17_UART1_BASE+LPC17_UART_IIR_OFFSET) +#define LPC17_UART1_FCR (LPC17_UART1_BASE+LPC17_UART_FCR_OFFSET) +#define LPC17_UART1_LCR (LPC17_UART1_BASE+LPC17_UART_LCR_OFFSET) +#define LPC17_UART1_MCR (LPC17_UART1_BASE+LPC17_UART_MCR_OFFSET) +#define LPC17_UART1_LSR (LPC17_UART1_BASE+LPC17_UART_LSR_OFFSET) +#define LPC17_UART1_MSR (LPC17_UART1_BASE+LPC17_UART_MSR_OFFSET) +#define LPC17_UART1_SCR (LPC17_UART1_BASE+LPC17_UART_SCR_OFFSET) +#define LPC17_UART1_ACR (LPC17_UART1_BASE+LPC17_UART_ACR_OFFSET) +#define LPC17_UART1_FDR (LPC17_UART1_BASE+LPC17_UART_FDR_OFFSET) +#define LPC17_UART1_TER (LPC17_UART1_BASE+LPC17_UART_TER_OFFSET) +#define LPC17_UART1_RS485CTRL (LPC17_UART1_BASE+LPC17_UART_RS485CTRL_OFFSET) +#define LPC17_UART1_ADRMATCH (LPC17_UART1_BASE+LPC17_UART_ADRMATCH_OFFSET) +#define LPC17_UART1_RS485DLY (LPC17_UART1_BASE+LPC17_UART_RS485DLY_OFFSET) +#define LPC17_UART1_FIFOLVL (LPC17_UART1_BASE+LPC17_UART_FIFOLVL_OFFSET) + +#define LPC17_UART2_RBR (LPC17_UART2_BASE+LPC17_UART_RBR_OFFSET) +#define LPC17_UART2_THR (LPC17_UART2_BASE+LPC17_UART_THR_OFFSET) +#define LPC17_UART2_DLL (LPC17_UART2_BASE+LPC17_UART_DLL_OFFSET) +#define LPC17_UART2_DLM (LPC17_UART2_BASE+LPC17_UART_DLM_OFFSET) +#define LPC17_UART2_IER (LPC17_UART2_BASE+LPC17_UART_IER_OFFSET) +#define LPC17_UART2_IIR (LPC17_UART2_BASE+LPC17_UART_IIR_OFFSET) +#define LPC17_UART2_FCR (LPC17_UART2_BASE+LPC17_UART_FCR_OFFSET) +#define LPC17_UART2_LCR (LPC17_UART2_BASE+LPC17_UART_LCR_OFFSET) +#define LPC17_UART2_LSR (LPC17_UART2_BASE+LPC17_UART_LSR_OFFSET) +#define LPC17_UART2_SCR (LPC17_UART2_BASE+LPC17_UART_SCR_OFFSET) +#define LPC17_UART2_ACR (LPC17_UART2_BASE+LPC17_UART_ACR_OFFSET) +#define LPC17_UART2_ICR (LPC17_UART2_BASE+LPC17_UART_ICR_OFFSET) +#define LPC17_UART2_FDR (LPC17_UART2_BASE+LPC17_UART_FDR_OFFSET) +#define LPC17_UART2_TER (LPC17_UART2_BASE+LPC17_UART_TER_OFFSET) +#define LPC17_UART2_FIFOLVL (LPC17_UART2_BASE+LPC17_UART_FIFOLVL_OFFSET) + +#define LPC17_UART3_RBR (LPC17_UART3_BASE+LPC17_UART_RBR_OFFSET) +#define LPC17_UART3_THR (LPC17_UART3_BASE+LPC17_UART_THR_OFFSET) +#define LPC17_UART3_DLL (LPC17_UART3_BASE+LPC17_UART_DLL_OFFSET) +#define LPC17_UART3_DLM (LPC17_UART3_BASE+LPC17_UART_DLM_OFFSET) +#define LPC17_UART3_IER (LPC17_UART3_BASE+LPC17_UART_IER_OFFSET) +#define LPC17_UART3_IIR (LPC17_UART3_BASE+LPC17_UART_IIR_OFFSET) +#define LPC17_UART3_FCR (LPC17_UART3_BASE+LPC17_UART_FCR_OFFSET) +#define LPC17_UART3_LCR (LPC17_UART3_BASE+LPC17_UART_LCR_OFFSET) +#define LPC17_UART3_LSR (LPC17_UART3_BASE+LPC17_UART_LSR_OFFSET) +#define LPC17_UART3_SCR (LPC17_UART3_BASE+LPC17_UART_SCR_OFFSET) +#define LPC17_UART3_ACR (LPC17_UART3_BASE+LPC17_UART_ACR_OFFSET) +#define LPC17_UART3_ICR (LPC17_UART3_BASE+LPC17_UART_ICR_OFFSET) +#define LPC17_UART3_FDR (LPC17_UART3_BASE+LPC17_UART_FDR_OFFSET) +#define LPC17_UART3_TER (LPC17_UART3_BASE+LPC17_UART_TER_OFFSET) +#define LPC17_UART3_FIFOLVL (LPC17_UART3_BASE+LPC17_UART_FIFOLVL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* RBR (DLAB =0) Receiver Buffer Register (all) */ + +#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ + /* Bits 8-31: Reserved */ + +/* THR (DLAB =0) Transmit Holding Register (all) */ + +#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ + /* Bits 8-31: Reserved */ + +/* DLL (DLAB =1) Divisor Latch LSB (all) */ + +#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ + /* Bits 8-31: Reserved */ + +/* DLM (DLAB =1) Divisor Latch MSB (all) */ + +#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ + /* Bits 8-31: Reserved */ + +/* IER (DLAB =0) Interrupt Enable Register (all) */ + +#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ +#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ +#define UART_IER_RLSIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */ +#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART1 only) */ + /* Bits 4-6: Reserved */ +#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART1 only) */ +#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +#define UART_IER_ALLIE (0x038f) + +/* IIR Interrupt ID Register (all) */ + +#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ +#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ +#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) +# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ +# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ +# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ +# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ +# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ + /* Bits 4-5: Reserved */ +#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ +#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) +#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ +#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +/* FCR FIFO Control Register (all) */ + +#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ +#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ +#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ +#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */ + /* Bits 4-5: Reserved */ +#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ +#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) +# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ +# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ +# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ +# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ + /* Bits 8-31: Reserved */ +/* LCR Line Control Register (all) */ + +#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ +#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) +#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ +#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ +#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ +#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) +# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ +# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ +# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ +# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ +#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ +#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ + /* Bits 8-31: Reserved */ +/* MCR Modem Control Register (UART1 only) */ + +#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ +#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ + /* Bits 2-3: Reserved */ +#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ + /* Bit 5: Reserved */ +#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ +#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ + /* Bits 8-31: Reserved */ +/* LSR Line Status Register (all) */ + +#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ +#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ +#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ +#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ +#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ +#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ +#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ +#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ + /* Bits 8-31: Reserved */ +/* MSR Modem Status Register (UART1 only) */ + +#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ +#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ +#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ +#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ +#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ +#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ +#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ +#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ + /* Bits 8-31: Reserved */ +/* SCR Scratch Pad Register (all) */ + +#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ + /* Bits 8-31: Reserved */ +/* ACR Auto-baud Control Register (all) */ + +#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ +#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ +#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ + /* Bits 3-7: Reserved */ +#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ +#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ + /* Bits 10-31: Reserved */ +/* ICA IrDA Control Register (UART0,2,3 only) */ + +#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */ +#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */ +#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */ +#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT) +# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */ +# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */ +# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */ +# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */ +# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */ +# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */ +# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */ +# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 246 x TPCLK */ + /* Bits 6-31: Reserved */ +/* FDR Fractional Divider Register (all) */ + +#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ +#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) +#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) + /* Bits 8-31: Reserved */ +/* TER Transmit Enable Register (all) */ + /* Bits 0-6: Reserved */ +#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 Control (UART1 only) */ + +#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ +#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ +#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ +#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ +#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ +#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ + /* Bits 6-31: Reserved */ +/* RS-485/EIA-485 address match (UART1 only) */ + +#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 direction control delay (UART1 only) */ + +#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ + /* Bits 8-31: Reserved */ +/* FIFOLVL FIFO Level register (all) */ + +#define UART_FIFOLVL_RX_SHIFT (0) /* Bits 0-3: Current level of the UART RX FIFO */ +#define UART_FIFOLVL_RX_MASK (15 << UART_FIFOLVL_RX_SHIFT) + /* Bits 4-7: Reserved */ +#define UART_FIFOLVL_TX_SHIFT (8) /* Bits 8-11: Current level of the UART TX FIFO */ +#define UART_FIFOLVL_TX_MASK (15 << UART_FIFOLVL_TX_SHIFT) + /* Bits 12-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h new file mode 100644 index 000000000..d1e6dd013 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_usb.h @@ -0,0 +1,778 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_usb.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ +#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ +#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ +#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ +#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ +#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ +#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ +#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ +#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ +#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ +#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ +#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ +#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ +#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ +#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ +#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ +#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ +#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ +#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ +#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ +#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ +#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ +#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ +#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ +#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ +#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ +#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ +#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ +#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ +#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ +#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ +#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ +#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ +#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ +#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ +#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ +#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ +#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ +#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ +#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ +#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ +#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ +#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ + +#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ +#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ + +/* Register addresses ***************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* Control and status registers (section 7.1) */ + +#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) +#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) +#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) +#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) +#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) +#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) + +/* Memory pointers (section 7.2) */ + +#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) +#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) +#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) +#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) +#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) +#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) +#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) + +/* Frame counters (section 7.3) */ + +#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) +#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) +#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) +#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) + +/* Root hub ports (section 7.4) */ + +#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) +#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) +#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) +#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) +#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) +#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) +#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) +#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) +#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) +#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) +#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) +#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) +#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) +#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) +#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) +#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) +#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) +#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) +#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) +#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) +#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) +#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) +#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) +#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) +#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) +#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) +#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) +#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) +#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) +#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) +#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) +#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) +#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) +#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) +#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) +#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) +#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) +#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) +#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) +#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) +#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) +#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) +#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) +#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) +#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) +#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) +#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) +#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) +#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) + +#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) +#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) + +/* Register bit definitions *********************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +/* Module ID/Revision ID */ + +#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ +#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) +#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ +#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) +#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ +#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) +# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers: + * + * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt + * Clear + */ + +#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ +#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ +#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ +#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ + /* Bits 4-31: Reserved */ +/* OTG Status and Control */ + +#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ +#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) +# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ +#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ +#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) +# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ +#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ +#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ +#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ + /* Bit 7: Reserved */ +#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ +#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ +#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ + /* Bits 11-15: Reserved */ +#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ +#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) + +/* OTG Timer */ + +#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ +#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) + /* Bits 16-31: Reserved */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ +/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt + * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority + */ + +#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ +#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ +#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ +#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ +#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ +#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ +#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ +#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ +#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ +#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ + /* Bits 10-31: Reserved */ +/* SIE Command registers: + * + * USB Command Code + */ + /* Bits 0-7: Reserved */ +#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ +#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) +#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ +#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) +#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ +#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) + /* Bits 24-31: Reserved */ +/* USB Command Data */ + +#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ +#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) + /* Bits 8-31: Reserved */ +/* USB transfer registers: + * + * USB Receive Data (Bits 0-31: Received data) + */ + +/* USB Receive Packet Length */ + +#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ +#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) +#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ +#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ + /* Bits 12-31: Reserved */ +/* USB Transmit Data (Bits 0-31: Transmit data) */ + +/* USB Transmit Packet Length */ + +#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ +#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) + /* Bits 10-31: Reserved */ +/* USB Control */ + +#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ +#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ +#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ +#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) + /* Bits 6-31: Reserved */ +/* Endpoint interrupt registers: + * + * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt + * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond + * to on RX or TX value for any of 15 logical endpoints). + */ + +#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) +#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) +#define USBDEV_LOGEPRX0 (1 << 0) +#define USBDEV_LOGEPTX0 (1 << 1) +#define USBDEV_LOGEPRX1 (1 << 2) +#define USBDEV_LOGEPTX1 (1 << 3) +#define USBDEV_LOGEPRX2 (1 << 4) +#define USBDEV_LOGEPTX2 (1 << 5) +#define USBDEV_LOGEPRX3 (1 << 6) +#define USBDEV_LOGEPTX3 (1 << 7) +#define USBDEV_LOGEPRX4 (1 << 8) +#define USBDEV_LOGEPTX4 (1 << 9) +#define USBDEV_LOGEPRX5 (1 << 10) +#define USBDEV_LOGEPTX5 (1 << 11) +#define USBDEV_LOGEPRX6 (1 << 12) +#define USBDEV_LOGEPTX6 (1 << 13) +#define USBDEV_LOGEPRX7 (1 << 14) +#define USBDEV_LOGEPTX7 (1 << 15) +#define USBDEV_LOGEPRX8 (1 << 16) +#define USBDEV_LOGEPTX8 (1 << 17) +#define USBDEV_LOGEPRX9 (1 << 18) +#define USBDEV_LOGEPTX9 (1 << 19) +#define USBDEV_LOGEPRX10 (1 << 20) +#define USBDEV_LOGEPTX10 (1 << 21) +#define USBDEV_LOGEPRX11 (1 << 22) +#define USBDEV_LOGEPTX11 (1 << 23) +#define USBDEV_LOGEPRX12 (1 << 24) +#define USBDEV_LOGEPTX12 (1 << 25) +#define USBDEV_LOGEPRX13 (1 << 26) +#define USBDEV_LOGEPTX13 (1 << 27) +#define USBDEV_LOGEPRX14 (1 << 28) +#define USBDEV_LOGEPTX14 (1 << 29) +#define USBDEV_LOGEPRX15 (1 << 30) +#define USBDEV_LOGEPTX15 (1 << 31) + +/* Endpoint realization registers: + * + * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) + */ + +#define USBDEV_PHYEP(n) (1 << (n)) +#define USBDEV_PHYEP0 (1 << 0) +#define USBDEV_PHYEP1 (1 << 1) +#define USBDEV_PHYEP2 (1 << 2) +#define USBDEV_PHYEP3 (1 << 3) +#define USBDEV_PHYEP4 (1 << 4) +#define USBDEV_PHYEP5 (1 << 5) +#define USBDEV_PHYEP6 (1 << 6) +#define USBDEV_PHYEP7 (1 << 7) +#define USBDEV_PHYEP8 (1 << 8) +#define USBDEV_PHYEP9 (1 << 9) +#define USBDEV_PHYEP10 (1 << 10) +#define USBDEV_PHYEP11 (1 << 11) +#define USBDEV_PHYEP12 (1 << 12) +#define USBDEV_PHYEP13 (1 << 13) +#define USBDEV_PHYEP14 (1 << 14) +#define USBDEV_PHYEP15 (1 << 15) +#define USBDEV_PHYEP16 (1 << 16) +#define USBDEV_PHYEP17 (1 << 17) +#define USBDEV_PHYEP18 (1 << 18) +#define USBDEV_PHYEP19 (1 << 19) +#define USBDEV_PHYEP20 (1 << 20) +#define USBDEV_PHYEP21 (1 << 21) +#define USBDEV_PHYEP22 (1 << 22) +#define USBDEV_PHYEP23 (1 << 23) +#define USBDEV_PHYEP24 (1 << 24) +#define USBDEV_PHYEP25 (1 << 25) +#define USBDEV_PHYEP26 (1 << 26) +#define USBDEV_PHYEP27 (1 << 27) +#define USBDEV_PHYEP28 (1 << 28) +#define USBDEV_PHYEP29 (1 << 29) +#define USBDEV_PHYEP30 (1 << 30) +#define USBDEV_PHYEP31 (1 << 31) + +/* USB Endpoint Index */ + +#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ +#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) + /* Bits 5-31: Reserved */ +/* USB MaxPacketSize */ + +#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ +#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) + /* Bits 10-31: Reserved */ +/* DMA registers: + * + * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers + * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions + * above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB UDCA Head */ + /* Bits 0-6: Reserved */ +#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ +#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) + +/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. + * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* + * definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ + +#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ +#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ +#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ + /* Bits 3-31: Reserved */ +/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB + * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB + * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System + * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use + * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* OTG I2C registers ****************************************************************/ + +/* I2C Receive */ + +#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ +#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Transmit */ + +#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ +#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) +#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ +#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ + /* Bits 3-31: Reserved */ +/* I2C Status */ + +#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ +#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ +#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ +#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ +#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ +#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ +#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ +#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ +#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ +#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ +#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ +#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ + /* Bits 12-31: Reserved */ +/* I2C Control */ + +#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ +#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ +#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ +#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ +#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ +#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ +#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ + /* Bits 9-31: Reserved */ +/* I2C Clock High */ + +#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Clock Low */ + +#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) + /* Bits 8-31: Reserved */ +/* Clock control registers ***********************************************************/ + +/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ + +#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ +#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ +#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ +#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ +#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ +#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ + /* Bits 5-31: Reserved */ +/* Alternate naming */ + +#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK +#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK +#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK +#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK +#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK +#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK + +/* Endpoints *************************************************************************/ + +#define LPC17_EP0_OUT 0 +#define LPC17_EP0_IN 1 +#define LPC17_CTRLEP_OUT LPC17_EP0_OUT +#define LPC17_CTRLEP_IN LPC17_EP0_IN +#define LPC17_EP1_OUT 2 +#define LPC17_EP1_IN 3 +#define LPC17_EP2_OUT 4 +#define LPC17_EP2_IN 5 +#define LPC17_EP3_OUT 6 +#define LPC17_EP3_IN 7 +#define LPC17_EP4_OUT 8 +#define LPC17_EP4_IN 9 +#define LPC17_EP5_OUT 10 +#define LPC17_EP5_IN 11 +#define LPC17_EP6_OUT 12 +#define LPC17_EP6_IN 13 +#define LPC17_EP7_OUT 14 +#define LPC17_EP7_IN 15 +#define LPC17_EP8_OUT 16 +#define LPC17_EP8_IN 17 +#define LPC17_EP9_OUT 18 +#define LPC17_EP9_IN 19 +#define LPC17_EP10_OUT 20 +#define LPC17_EP10_IN 21 +#define LPC17_EP11_OUT 22 +#define LPC17_EP11_IN 23 +#define LPC17_EP12_OUT 24 +#define LPC17_EP12_IN 25 +#define LPC17_EP13_OUT 26 +#define LPC17_EP13_IN 27 +#define LPC17_EP14_OUT 28 +#define LPC17_EP14_IN 29 +#define LPC17_EP15_OUT 30 +#define LPC17_EP15_IN 31 +#define LPC17_NUMEPS 32 + +/* Commands *************************************************************************/ + +/* USB Command Code Register */ + +#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ +#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) +#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ +#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) +#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT +#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK + +/* Device Commands */ + +#define CMD_USBDEV_SETADDRESS (0x00d0) +#define CMD_USBDEV_CONFIG (0x00d8) +#define CMD_USBDEV_SETMODE (0x00f3) +#define CMD_USBDEV_READFRAMENO (0x00f5) +#define CMD_USBDEV_READTESTREG (0x00fd) +#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ +#define CMD_USBDEV_GETSTATUS (0x00fe) +#define CMD_USBDEV_GETERRORCODE (0x00ff) +#define CMD_USBDEV_READERRORSTATUS (0x00fb) + +/* Endpoint Commands */ + +#define CMD_USBDEV_EPSELECT (0x0000) +#define CMD_USBDEV_EPSELECTCLEAR (0x0040) +#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ +#define CMD_USBDEV_EPCLRBUFFER (0x00f2) +#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) + +/* Command/response bit definitions ********************************************/ +/* SETADDRESS (0xd0) command definitions */ + +#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ +#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ + +/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ + +#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ +#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ +#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ +#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ +#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ + +/* EPSELECT (0x00) endpoint status response */ + +#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ +#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ +#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ +#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ +#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ +#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ +#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ + /* Bit 7: Reserved */ +/* EPSETSTATUS (0x40) command */ + +#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ + /* Bits 1-4: Reserved */ +#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ +#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ +#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ + +/* EPCLRBUFFER (0xf2) response */ + +#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) + +/* SETMODE(0xf3) command */ + +#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ +#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ +#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ +#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ +#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ +#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ +#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ + +/* READERRORSTATUS (0xFb) command */ + +#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ +#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ +#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ +#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ +#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ +#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ +#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ +#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ +#define CMD_READERRORSTATUS_ALLERRS (0xff) + +/* DMA ******************************************************************************/ +/* The DMA descriptor */ + +#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ +#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ +#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ +#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ +#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ + +/* Bit settings for CONFIG (offset 1 )*/ + +#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ +#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) +# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ +# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ +#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ + /* Bit 3: Reserved */ +#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ +#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ +#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) +#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ +#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT + +/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ + +#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ +#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) +#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ +#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ +#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ +#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ +#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) +#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ +#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) + +/* DMA packet size format */ + +#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ +#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) +#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ +#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ +#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h new file mode 100644 index 000000000..9c83ac4de --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_wdt.h @@ -0,0 +1,108 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc17_wdt.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */ +#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET) +#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET) +#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET) +#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET) +#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ + /* Bits 14-31: Reserved */ + +/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */ + +/* Watchdog feed sequence register */ + +#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register (Bits 0-31: Counter timer value) */ + +/* Watchdog clock source selection register */ + +#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ +#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT) +# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */ +# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ +# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ + /* Bits 2-30: Reserved */ +#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.c b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.c index ebc05d13e..81e13e342 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.c @@ -60,9 +60,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_adc.h" #if defined(CONFIG_LPC17_ADC) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h index 6b9a58345..5a1bef14a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_adc.h @@ -1,180 +1,88 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_adc.h - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ -#define LPC17_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ -#define LPC17_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ - -#define LPC17_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) -#define LPC17_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ -#define LPC17_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ -#define LPC17_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ -#define LPC17_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ -#define LPC17_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ -#define LPC17_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ -#define LPC17_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ -#define LPC17_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ - -#define LPC17_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ -#define LPC17_ADC_TRM_OFFSET 0x0034 /* ADC trim register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_ADC_CR (LPC17_ADC_BASE+LPC17_ADC_CR_OFFSET) -#define LPC17_ADC_GDR (LPC17_ADC_BASE+LPC17_ADC_GDR_OFFSET) -#define LPC17_ADC_INTEN (LPC17_ADC_BASE+LPC17_ADC_INTEN_OFFSET) - -#define LPC17_ADC_DR(n) (LPC17_ADC_BASE+LPC17_ADC_DR_OFFSET(n)) -#define LPC17_ADC_DR0 (LPC17_ADC_BASE+LPC17_ADC_DR0_OFFSET) -#define LPC17_ADC_DR1 (LPC17_ADC_BASE+LPC17_ADC_DR1_OFFSET) -#define LPC17_ADC_DR2 (LPC17_ADC_BASE+LPC17_ADC_DR2_OFFSET) -#define LPC17_ADC_DR3 (LPC17_ADC_BASE+LPC17_ADC_DR3_OFFSET) -#define LPC17_ADC_DR4 (LPC17_ADC_BASE+LPC17_ADC_DR4_OFFSET) -#define LPC17_ADC_DR5 (LPC17_ADC_BASE+LPC17_ADC_DR5_OFFSET) -#define LPC17_ADC_DR6 (LPC17_ADC_BASE+LPC17_ADC_DR6_OFFSET) -#define LPC17_ADC_DR7 (LPC17_ADC_BASE+LPC17_ADC_DR7_OFFSET) - -#define LPC17_ADC_STAT (LPC17_ADC_BASE+LPC17_ADC_STAT_OFFSET) -#define LPC17_ADC_TRM (LPC17_ADC_BASE+LPC17_ADC_TRM_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* A/D Control Register */ - -#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */ -#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK) -#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */ -#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT) -#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */ - /* Bits 17-20: Reserved */ -#define ADC_CR_PDN (1 << 21) /* Bit 21: A/D converter power-down mode */ - /* Bits 22-23: Reserved */ -#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */ -#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT) -# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */ -# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */ -# define ADC_CR_START_P2p10 (2 << ADC_CR_START_SHIFT) /* Start edge on P2.10/EINT0/NMI */ -# define ADC_CR_START_P1p27 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.27/CLKOUT/USB_OVRCRn/CAP0.1 */ -# define ADC_CR_START_MAT0p1 (4 << ADC_CR_START_SHIFT) /* Start edge on MAT0.1 */ -# define ADC_CR_START_MAT0p3 (5 << ADC_CR_START_SHIFT) /* Start edge on MAT0.3 */ -# define ADC_CR_START_MAT1p0 (6 << ADC_CR_START_SHIFT) /* Start edge on MAT1.0 */ -# define ADC_CR_START_MAT1p1 (7 << ADC_CR_START_SHIFT) /* Start edge on MAT1.1 */ -#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */ - /* Bits 28-31: Reserved */ -/* A/D Global Data Register AND Channel 0-7 Data Register */ - /* Bits 0-3: Reserved */ -#define ADC_DR_RESULT_SHIFT (4) /* Bits 4-15: Result of conversion (DONE==1) */ -#define ADC_DR_RESULT_MASK (0x0fff << ADC_DR_RESULT_SHIFT) - /* Bits 16-23: Reserved */ -#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ -#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT) - /* Bits 27-29: Reserved */ -#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ -#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ - -/* A/D Interrupt Enable Register */ - -#define ADC_INTEN_CHAN(n) (1 << (n)) -#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */ -#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */ -#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */ -#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */ -#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */ -#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */ -#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */ -#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */ -#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */ - /* Bits 9-31: Reserved */ -/* A/D Status Register */ - -#define ADC_STAT_DONE(n) (1 << (n)) -#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */ -#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */ -#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */ -#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */ -#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */ -#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */ -#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */ -#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */ -#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8) -#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */ -#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */ -#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */ -#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */ -#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */ -#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */ -#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */ -#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */ -#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */ - /* Bits 17-31: Reserved */ -/* ADC trim register */ - /* Bits 0-3: Reserved */ -#define ADC_TRM_ADCOFFS_SHIFT (4) /* Bits 4-7: A/D offset trim bits */ -#define ADC_TRM_ADCOFFS_MASK (15 << ADC_TRM_ADCOFFS_SHIFT) -#define ADC_TRM_TRIM_SHIFT (8) /* Bits 8-11: Written-to by boot code */ -#define ADC_TRM_TRIM_MASK (15 << ADC_TRM_TRIM_SHIFT) - /* Bits 12-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H */ +/**************************************************************************** + * arch/arm/src/lpc17xx/lpc17_adc.h + * + * Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip/lpc17_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_adcinitialize + * + * Description: + * Initialize the adc + * + * Returned Value: + * Valid can device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC17_ADC +FAR struct adc_dev_s *lpc17_adcinitialize(void); +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ADC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c index 501358716..5da6ffa22 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_memorymap.h" #include "lpc17_emacram.h" #include "lpc17_ohciram.h" diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_can.c b/nuttx/arch/arm/src/lpc17xx/lpc17_can.c index 409785d29..abdf8c7b7 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_can.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_can.c @@ -62,9 +62,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_can.h" #if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h index e990958fd..e15eaced5 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_can.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_can.h @@ -1,7 +1,7 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/lpc17xx/lpc17_can.h * - * Copyright (C) 2010-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,480 +31,62 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H #define __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include +#include "chip/lpc17_can.h" -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* CAN acceptance filter registers */ - -#define LPC17_CANAF_AFMR_OFFSET 0x0000 /* Acceptance Filter Register */ -#define LPC17_CANAF_SFFSA_OFFSET 0x0004 /* Standard Frame Individual Start Address Register */ -#define LPC17_CANAF_SFFGRPSA_OFFSET 0x0008 /* Standard Frame Group Start Address Register */ -#define LPC17_CANAF_EFFSA_OFFSET 0x000c /* Extended Frame Start Address Register */ -#define LPC17_CANAF_EFFGRPSA_OFFSET 0x0010 /* Extended Frame Group Start Address Register */ -#define LPC17_CANAF_EOT_OFFSET 0x0014 /* End of AF Tables register */ -#define LPC17_CANAF_LUTERRAD_OFFSET 0x0018 /* LUT Error Address register */ -#define LPC17_CANAF_LUTERR_OFFSET 0x001c /* LUT Error Register */ -#define LPC17_CANAF_FCANIE_OFFSET 0x0020 /* FullCAN interrupt enable register */ -#define LPC17_CANAF_FCANIC0_OFFSET 0x0024 /* FullCAN interrupt and capture register 0 */ -#define LPC17_CANAF_FCANIC1_OFFSET 0x0028 /* FullCAN interrupt and capture register 1 */ - -/* Central CAN registers */ - -#define LPC17_CAN_TXSR_OFFSET 0x0000 /* CAN Central Transmit Status Register */ -#define LPC17_CAN_RXSR_OFFSET 0x0004 /* CAN Central Receive Status Register */ -#define LPC17_CAN_MSR_OFFSET 0x0008 /* CAN Central Miscellaneous Register */ - -/* CAN1/2 registers */ - -#define LPC17_CAN_MOD_OFFSET 0x0000 /* CAN operating mode */ -#define LPC17_CAN_CMR_OFFSET 0x0004 /* Command bits */ -#define LPC17_CAN_GSR_OFFSET 0x0008 /* Controller Status and Error Counters */ -#define LPC17_CAN_ICR_OFFSET 0x000c /* Interrupt and capure register */ -#define LPC17_CAN_IER_OFFSET 0x0010 /* Interrupt Enable */ -#define LPC17_CAN_BTR_OFFSET 0x0014 /* Bus Timing */ -#define LPC17_CAN_EWL_OFFSET 0x0018 /* Error Warning Limit */ -#define LPC17_CAN_SR_OFFSET 0x001c /* Status Register */ -#define LPC17_CAN_RFS_OFFSET 0x0020 /* Receive frame status */ -#define LPC17_CAN_RID_OFFSET 0x0024 /* Received Identifier */ -#define LPC17_CAN_RDA_OFFSET 0x0028 /* Received data bytes 1-4 */ -#define LPC17_CAN_RDB_OFFSET 0x002c /* Received data bytes 5-8 */ -#define LPC17_CAN_TFI1_OFFSET 0x0030 /* Transmit frame info (Tx Buffer 1) */ -#define LPC17_CAN_TID1_OFFSET 0x0034 /* Transmit Identifier (Tx Buffer 1) */ -#define LPC17_CAN_TDA1_OFFSET 0x0038 /* Transmit data bytes 1-4 (Tx Buffer 1) */ -#define LPC17_CAN_TDB1_OFFSET 0x003c /* Transmit data bytes 5-8 (Tx Buffer 1) */ -#define LPC17_CAN_TFI2_OFFSET 0x0040 /* Transmit frame info (Tx Buffer 2) */ -#define LPC17_CAN_TID2_OFFSET 0x0044 /* Transmit Identifier (Tx Buffer 2) */ -#define LPC17_CAN_TDA2_OFFSET 0x0048 /* Transmit data bytes 1-4 (Tx Buffer 2) */ -#define LPC17_CAN_TDB2_OFFSET 0x004c /* Transmit data bytes 5-8 (Tx Buffer 2) */ -#define LPC17_CAN_TFI3_OFFSET 0x0050 /* Transmit frame info (Tx Buffer 3) */ -#define LPC17_CAN_TID3_OFFSET 0x0054 /* Transmit Identifier (Tx Buffer 3) */ -#define LPC17_CAN_TDA3_OFFSET 0x0058 /* Transmit data bytes 1-4 (Tx Buffer 3) */ -#define LPC17_CAN_TDB3_OFFSET 0x005c /* Transmit data bytes 5-8 (Tx Buffer 3) */ - -/* Register addresses ***************************************************************/ -/* CAN acceptance filter registers */ - -#define LPC17_CANAF_AFMR (LPC17_CANAF_BASE+LPC17_CANAF_AFMR_OFFSET) -#define LPC17_CANAF_SFFSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFSA_OFFSET) -#define LPC17_CANAF_SFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_SFFGRPSA_OFFSET) -#define LPC17_CANAF_EFFSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFSA_OFFSET) -#define LPC17_CANAF_EFFGRPSA (LPC17_CANAF_BASE+LPC17_CANAF_EFFGRPSA_OFFSET) -#define LPC17_CANAF_EOT (LPC17_CANAF_BASE+LPC17_CANAF_EOT_OFFSET) -#define LPC17_CANAF_LUTERRAD (LPC17_CANAF_BASE+LPC17_CANAF_LUTERRAD_OFFSET) -#define LPC17_CANAF_LUTERR (LPC17_CANAF_BASE+LPC17_CANAF_LUTERR_OFFSET) -#define LPC17_CANAF_FCANIE (LPC17_CANAF_BASE+LPC17_CANAF_FCANIE_OFFSET) -#define LPC17_CANAF_FCANIC0 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC0_OFFSET) -#define LPC17_CANAF_FCANIC1 (LPC17_CANAF_BASE+LPC17_CANAF_FCANIC1_OFFSET) - -/* Central CAN registers */ - -#define LPC17_CAN_TXSR (LPC17_CAN_BASE+LPC17_CAN_TXSR_OFFSET) -#define LPC17_CAN_RXSR (LPC17_CAN_BASE+LPC17_CAN_RXSR_OFFSET) -#define LPC17_CAN_MSR (LPC17_CAN_BASE+LPC17_CAN_MSR_OFFSET) - -/* CAN1/2 registers */ - -#define LPC17_CAN1_MOD (LPC17_CAN1_BASE+LPC17_CAN_MOD_OFFSET) -#define LPC17_CAN1_CMR (LPC17_CAN1_BASE+LPC17_CAN_CMR_OFFSET) -#define LPC17_CAN1_GSR (LPC17_CAN1_BASE+LPC17_CAN_GSR_OFFSET) -#define LPC17_CAN1_ICR (LPC17_CAN1_BASE+LPC17_CAN_ICR_OFFSET) -#define LPC17_CAN1_IER (LPC17_CAN1_BASE+LPC17_CAN_IER_OFFSET) -#define LPC17_CAN1_BTR (LPC17_CAN1_BASE+LPC17_CAN_BTR_OFFSET) -#define LPC17_CAN1_EWL (LPC17_CAN1_BASE+LPC17_CAN_EWL_OFFSET) -#define LPC17_CAN1_SR (LPC17_CAN1_BASE+LPC17_CAN_SR_OFFSET) -#define LPC17_CAN1_RFS (LPC17_CAN1_BASE+LPC17_CAN_RFS_OFFSET) -#define LPC17_CAN1_RID (LPC17_CAN1_BASE+LPC17_CAN_RID_OFFSET) -#define LPC17_CAN1_RDA (LPC17_CAN1_BASE+LPC17_CAN_RDA_OFFSET) -#define LPC17_CAN1_RDB (LPC17_CAN1_BASE+LPC17_CAN_RDB_OFFSET) -#define LPC17_CAN1_TFI1 (LPC17_CAN1_BASE+LPC17_CAN_TFI1_OFFSET) -#define LPC17_CAN1_TID1 (LPC17_CAN1_BASE+LPC17_CAN_TID1_OFFSET) -#define LPC17_CAN1_TDA1 (LPC17_CAN1_BASE+LPC17_CAN_TDA1_OFFSET) -#define LPC17_CAN1_TDB1 (LPC17_CAN1_BASE+LPC17_CAN_TDB1_OFFSET) -#define LPC17_CAN1_TFI2 (LPC17_CAN1_BASE+LPC17_CAN_TFI2_OFFSET) -#define LPC17_CAN1_TID2 (LPC17_CAN1_BASE+LPC17_CAN_TID2_OFFSET) -#define LPC17_CAN1_TDA2 (LPC17_CAN1_BASE+LPC17_CAN_TDA2_OFFSET) -#define LPC17_CAN1_TDB2 (LPC17_CAN1_BASE+LPC17_CAN_TDB2_OFFSET) -#define LPC17_CAN1_TFI3 (LPC17_CAN1_BASE+LPC17_CAN_TFI3_OFFSET) -#define LPC17_CAN1_TID3 (LPC17_CAN1_BASE+LPC17_CAN_TID3_OFFSET) -#define LPC17_CAN1_TDA3 (LPC17_CAN1_BASE+LPC17_CAN_TDA3_OFFSET) -#define LPC17_CAN1_TDB3 (LPC17_CAN1_BASE+LPC17_CAN_TDB3_OFFSET) - -#define LPC17_CAN2_MOD (LPC17_CAN2_BASE+LPC17_CAN_MOD_OFFSET) -#define LPC17_CAN2_CMR (LPC17_CAN2_BASE+LPC17_CAN_CMR_OFFSET) -#define LPC17_CAN2_GSR (LPC17_CAN2_BASE+LPC17_CAN_GSR_OFFSET) -#define LPC17_CAN2_ICR (LPC17_CAN2_BASE+LPC17_CAN_ICR_OFFSET) -#define LPC17_CAN2_IER (LPC17_CAN2_BASE+LPC17_CAN_IER_OFFSET) -#define LPC17_CAN2_BTR (LPC17_CAN2_BASE+LPC17_CAN_BTR_OFFSET) -#define LPC17_CAN2_EWL (LPC17_CAN2_BASE+LPC17_CAN_EWL_OFFSET) -#define LPC17_CAN2_SR (LPC17_CAN2_BASE+LPC17_CAN_SR_OFFSET) -#define LPC17_CAN2_RFS (LPC17_CAN2_BASE+LPC17_CAN_RFS_OFFSET) -#define LPC17_CAN2_RID (LPC17_CAN2_BASE+LPC17_CAN_RID_OFFSET) -#define LPC17_CAN2_RDA (LPC17_CAN2_BASE+LPC17_CAN_RDA_OFFSET) -#define LPC17_CAN2_RDB (LPC17_CAN2_BASE+LPC17_CAN_RDB_OFFSET) -#define LPC17_CAN2_TFI1 (LPC17_CAN2_BASE+LPC17_CAN_TFI1_OFFSET) -#define LPC17_CAN2_TID1 (LPC17_CAN2_BASE+LPC17_CAN_TID1_OFFSET) -#define LPC17_CAN2_TDA1 (LPC17_CAN2_BASE+LPC17_CAN_TDA1_OFFSET) -#define LPC17_CAN2_TDB1 (LPC17_CAN2_BASE+LPC17_CAN_TDB1_OFFSET) -#define LPC17_CAN2_TFI2 (LPC17_CAN2_BASE+LPC17_CAN_TFI2_OFFSET) -#define LPC17_CAN2_TID2 (LPC17_CAN2_BASE+LPC17_CAN_TID2_OFFSET) -#define LPC17_CAN2_TDA2 (LPC17_CAN2_BASE+LPC17_CAN_TDA2_OFFSET) -#define LPC17_CAN2_TDB2 (LPC17_CAN2_BASE+LPC17_CAN_TDB2_OFFSET) -#define LPC17_CAN2_TFI3 (LPC17_CAN2_BASE+LPC17_CAN_TFI3_OFFSET) -#define LPC17_CAN2_TID3 (LPC17_CAN2_BASE+LPC17_CAN_TID3_OFFSET) -#define LPC17_CAN2_TDA3 (LPC17_CAN2_BASE+LPC17_CAN_TDA3_OFFSET) -#define LPC17_CAN2_TDB3 (LPC17_CAN2_BASE+LPC17_CAN_TDB3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* CAN acceptance filter registers */ -/* Acceptance Filter Register */ - -#define CANAF_AFMR_ACCOFF (1 << 0) /* Bit 0: AF non-operational; All RX messages ignored */ -#define CANAF_AFMR_ACCBP (1 << 1) /* Bit 1: AF bypass: All RX messages accepted */ -#define CANAF_AFMR_EFCAN (1 << 2) /* Bit 2: Enable Full CAN mode */ - /* Bits 3-31: Reserved */ -/* Standard Frame Individual Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_SFFSA_SHIFT (2) /* Bits 2-10: Address of Standard Identifiers in AF Lookup RAM */ -#define CANAF_SFFSA_MASK (0x01ff << CANAF_SFFSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Standard Frame Group Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_SFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Standard Identifiers in AF Lookup RAM */ -#define CANAF_SFFGRPSA_MASK (0x01ff << CANAF_SFFGRPSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Extended Frame Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_EFFSA_SHIFT (2) /* Bits 2-10: Address of Extended Identifiers in AF Lookup RAM */ -#define CANAF_EFFSA_MASK (0x01ff << CANAF_EFFSA_SHIFT) - /* Bits 11-31: Reserved */ -/* Extended Frame Group Start Address Register */ - /* Bits 0-1: Reserved */ -#define CANAF_EFFGRPSA_SHIFT (2) /* Bits 2-10: Address of grouped Extended Identifiers in AF Lookup RAM */ -#define CANAF_EFFGRPSA_MASK (0x01ff << CANAF_EFFGRPSA_SHIFT) - /* Bits 11-31: Reserved */ -/* End of AF Tables register */ - /* Bits 0-1: Reserved */ -#define CANAF_EOT_SHIFT (2) /* Bits 2-10: Last active address in last active AF table */ -#define CANAF_EOT_MASK (0x01ff << CANAF_EOT_SHIFT) - /* Bits 11-31: Reserved */ -/* LUT Error Address register */ - /* Bits 0-1: Reserved */ -#define CANAF_LUTERRAD_SHIFT (2) /* Bits 2-10: Address in AF Lookup RAM of error */ -#define CANAF_LUTERRAD_MASK (0x01ff << CANAF_EOT_SHIFT) - /* Bits 11-31: Reserved */ -/* LUT Error Register */ - -#define CANAF_LUTERR_LUTERR (1 << 0) /* Bit 0: AF error in AF RAM tables */ - /* Bits 1-31: Reserved */ -/* FullCAN interrupt enable register */ - -#define CANAF_FCANIE_FCANIE (1 << 0) /* Bit 0: Global FullCAN Interrupt Enable */ - /* Bits 1-31: Reserved */ - -/* FullCAN interrupt and capture register 0 */ - -#define CANAF_FCANIC0_INTPND(n) (1 << (n)) /* n=0,1,2,... 31 */ - -/* FullCAN interrupt and capture register 1 */ - -#define CANAF_FCANIC1_INTPND(n) (1 << ((n)-32)) /* n=32,33,...63 */ - -/* Central CAN registers */ -/* CAN Central Transmit Status Register */ - -#define CAN_TXSR_TS1 (1 << 0) /* Bit 0: CAN1 sending */ -#define CAN_TXSR_TS2 (1 << 1) /* Bit 1: CAN2 sending */ - /* Bits 2-7: Reserved */ -#define CAN_TXSR_TBS1 (1 << 8) /* Bit 8: All 3 CAN1 TX buffers available */ -#define CAN_TXSR_TBS2 (1 << 9) /* Bit 9: All 3 CAN2 TX buffers available */ - /* Bits 10-15: Reserved */ -#define CAN_TXSR_TCS1 (1 << 16) /* Bit 16: All CAN1 xmissions completed */ -#define CAN_TXSR_TCS2 (1 << 17) /* Bit 17: All CAN2 xmissions completed */ - /* Bits 18-31: Reserved */ -/* CAN Central Receive Status Register */ - -#define CAN_RXSR_RS1 (1 << 0) /* Bit 0: CAN1 receiving */ -#define CAN_RXSR_RS2 (1 << 1) /* Bit 1: CAN2 receiving */ - /* Bits 2-7: Reserved */ -#define CAN_RXSR_RB1 (1 << 8) /* Bit 8: CAN1 received message available */ -#define CAN_RXSR_RB2 (1 << 9) /* Bit 9: CAN2 received message available */ - /* Bits 10-15: Reserved */ -#define CAN_RXSR_DOS1 (1 << 16) /* Bit 16: All CAN1 message lost */ -#define CAN_RXSR_DOS2 (1 << 17) /* Bit 17: All CAN2 message lost */ - /* Bits 18-31: Reserved */ -/* CAN Central Miscellaneous Register */ - -#define CAN_MSR_E1 (1 << 0) /* Bit 0: CAN1 error counters at limit */ -#define CAN_MSR_E2 (1 << 1) /* Bit 1: CAN2 error counters at limit */ - /* Bits 2-7: Reserved */ -#define CAN_MSR_BS1 (1 << 8) /* Bit 8: CAN1 busy */ -#define CAN_MSR_BS2 (1 << 9) /* Bit 7: CAN2 busy */ - /* Bits 10-31: Reserved */ -/* CAN1/2 registers */ -/* CAN operating mode */ - -#define CAN_MOD_RM (1 << 0) /* Bit 0: Reset Mode */ -#define CAN_MOD_LOM (1 << 1) /* Bit 1: Listen Only Mode */ -#define CAN_MOD_STM (1 << 2) /* Bit 2: Self Test Mode */ -#define CAN_MOD_TPM (1 << 3) /* Bit 3: Transmit Priority Mode */ -#define CAN_MOD_SM (1 << 4) /* Bit 4: Sleep Mode */ -#define CAN_MOD_RPM (1 << 5) /* Bit 5: Receive Polarity Mode */ - /* Bit 6: Reserved */ -#define CAN_MOD_TM (1 << 7) /* Bit 7: Test Mode */ - /* Bits 8-31: Reserved */ -/* Command bits */ - -#define CAN_CMR_TR (1 << 0) /* Bit 0: Transmission Request */ -#define CAN_CMR_AT (1 << 1) /* Bit 1: Abort Transmission */ -#define CAN_CMR_RRB (1 << 2) /* Bit 2: Release Receive Buffer */ -#define CAN_CMR_CDO (1 << 3) /* Bit 3: Clear Data Overrun */ -#define CAN_CMR_SRR (1 << 4) /* Bit 4: Self Reception Request */ -#define CAN_CMR_STB1 (1 << 5) /* Bit 5: Select Tx Buffer 1 */ -#define CAN_CMR_STB2 (1 << 6) /* Bit 6: Select Tx Buffer 2 */ -#define CAN_CMR_STB3 (1 << 7) /* Bit 7: Select Tx Buffer 3 */ - /* Bits 8-31: Reserved */ -/* Controller Status and Error Counters */ - -#define CAN_GSR_RBS (1 << 0) /* Bit 0: Receive Buffer Status */ -#define CAN_GSR_DOS (1 << 1) /* Bit 1: Data Overrun Status */ -#define CAN_GSR_TBS (1 << 2) /* Bit 2: Transmit Buffer Status */ -#define CAN_GSR_TCS (1 << 3) /* Bit 3: Transmit Complete Status */ -#define CAN_GSR_RS (1 << 4) /* Bit 4: Receive Status */ -#define CAN_GSR_TS (1 << 5) /* Bit 5: Transmit Status */ -#define CAN_GSR_ES (1 << 6) /* Bit 6: Error Status */ -#define CAN_GSR_BS (1 << 7) /* Bit 7: Bus Status */ - /* Bits 8-15: Reserved */ -#define CAN_GSR_RXERR_SHIFT (16) /* Bits 16-23: Rx Error Counter */ -#define CAN_GSR_RXERR_MASK (0xff << CAN_GSR_RXERR_SHIFT) -#define CAN_GSR_TXERR_SHIFT (24) /* Bits 24-31: Tx Error Counter */ -#define CAN_GSR_TXERR_MASK (0xff << CAN_GSR_TXERR_SHIFT) + ****************************************************************************/ -/* Interrupt and capture register */ - -#define CAN_ICR_RI (1 << 0) /* Bit 0: Receive Interrupt */ -#define CAN_ICR_TI1 (1 << 1) /* Bit 1: Transmit Interrupt 1 */ -#define CAN_ICR_EI (1 << 2) /* Bit 2: Error Warning Interrupt */ -#define CAN_ICR_DOI (1 << 3) /* Bit 3: Data Overrun Interrupt */ -#define CAN_ICR_WUI (1 << 4) /* Bit 4: Wake-Up Interrupt */ -#define CAN_ICR_EPI (1 << 5) /* Bit 5: Error Passive Interrupt */ -#define CAN_ICR_ALI (1 << 6) /* Bit 6: Arbitration Lost Interrupt */ -#define CAN_ICR_BEI (1 << 7) /* Bit 7: Bus Error Interrupt */ -#define CAN_ICR_IDI (1 << 8) /* Bit 8: ID Ready Interrupt */ -#define CAN_ICR_TI2 (1 << 9) /* Bit 9: Transmit Interrupt 2 */ -#define CAN_ICR_TI3 (1 << 10) /* Bit 10: Transmit Interrupt 3 */ - /* Bits 11-15: Reserved */ -#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ -#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) -# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ -# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ -# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ -# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ -# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ -# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ -# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ -# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ -# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ -# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ -# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ -# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ -# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ -# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ -# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ -# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ -# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ -# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ -# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ -# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ -# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ -# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ -#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ -#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ -#define CAN_ICR_ERRC_MASK (3 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_BIT (0 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_FORM (1 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_STUFF (2 << CAN_ICR_ERRC_SHIFT) -# define CAN_ICR_ERRC_OTHER (3 << CAN_ICR_ERRC_SHIFT) -#define CAN_ICR_ALCBIT_SHIFT (24) /* Bits 24-31: Bit number within frame */ -#define CAN_ICR_ALCBIT_MASK (0xff << CAN_ICR_ALCBIT_SHIFT) - -/* Interrupt Enable */ - -#define CAN_IER_RIE (1 << 0) /* Bit 0: Receiver Interrupt Enable */ -#define CAN_IER_TIE1 (1 << 1) /* Bit 1: Transmit Interrupt Enable for Buffer1 */ -#define CAN_IER_EIE (1 << 2) /* Bit 2: Error Warning Interrupt Enable */ -#define CAN_IER_DOIE (1 << 3) /* Bit 3: Data Overrun Interrupt Enable */ -#define CAN_IER_WUIE (1 << 4) /* Bit 4: Wake-Up Interrupt Enable */ -#define CAN_IER_EPIE (1 << 5) /* Bit 5: Error Passive Interrupt Enable */ -#define CAN_IER_ALIE (1 << 6) /* Bit 6: Arbitration Lost Interrupt Enable */ -#define CAN_IER_BEIE (1 << 7) /* Bit 7: Bus Error Interrupt */ -#define CAN_IER_IDIE (1 << 8) /* Bit 8: ID Ready Interrupt Enable */ -#define CAN_IER_TIE2 (1 << 9) /* Bit 9: Transmit Interrupt Enable for Buffer2 */ -#define CAN_IER_TIE3 (1 << 10) /* Bit 10: Transmit Interrupt Enable for Buffer3 */ - /* Bits 11-31: Reserved */ -/* Bus Timing */ - -#define CAN_BTR_BRP_SHIFT (0) /* Bits 0-9: Baud Rate Prescaler */ -#define CAN_BTR_BRP_MASK (0x3ff << CAN_BTR_BRP_SHIFT) - /* Bits 10-13: Reserved */ -#define CAN_BTR_SJW_SHIFT (14) /* Bits 14-15: Synchronization Jump Width */ -#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) -#define CAN_BTR_TSEG1_SHIFT (16) /* Bits 16-19: Sync to sample delay */ -#define CAN_BTR_TSEG1_MASK (15 << CAN_BTR_TSEG1_SHIFT) -#define CAN_BTR_TSEG2_SHIFT (20) /* Bits 20-22: smaple to next delay */ -#define CAN_BTR_TSEG2_MASK (7 << CAN_BTR_TSEG2_SHIFT) -#define CAN_BTR_SAM (1 << 23) /* Bit 23: Sampling */ - /* Bits 24-31: Reserved */ - -#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ -#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ -#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ - -/* Error Warning Limit */ - -#define CAN_EWL_SHIFT (0) /* Bits 0-7: Error warning limit */ -#define CAN_EWL_MASK (0xff << CAN_EWL_SHIFT) - /* Bits 8-31: Reserved */ -/* Status Register */ - -#define CAN_SR_RBS1 (1 << 0) /* Bit 0: Receive Buffer Status */ -#define CAN_SR_DOS1 (1 << 1) /* Bit 1: Data Overrun Status */ -#define CAN_SR_TBS1 (1 << 2) /* Bit 2: Transmit Buffer Status 1 */ -#define CAN_SR_TCS1 (1 << 3) /* Bit 3: Transmission Complete Status */ -#define CAN_SR_RS1 (1 << 4) /* Bit 4: Receive Status */ -#define CAN_SR_TS1 (1 << 5) /* Bit 5: Transmit Status 1 */ -#define CAN_SR_ES1 (1 << 6) /* Bit 6: Error Status */ -#define CAN_SR_BS1 (1 << 7) /* Bit 7: Bus Status */ -#define CAN_SR_RBS2 (1 << 8) /* Bit 8: Receive Buffer Status */ -#define CAN_SR_DOS2 (1 << 9) /* Bit 9: Data Overrun Status */ -#define CAN_SR_TBS2 (1 << 10) /* Bit 10: Transmit Buffer Status 2 */ -#define CAN_SR_TCS2 (1 << 11) /* Bit 11: Transmission Complete Status */ -#define CAN_SR_RS2 (1 << 12) /* Bit 12: Receive Status */ -#define CAN_SR_TS2 (1 << 13) /* Bit 13: Transmit Status 2 */ -#define CAN_SR_ES2 (1 << 14) /* Bit 14: Error Status */ -#define CAN_SR_BS2 (1 << 15) /* Bit 15: Bus Status */ -#define CAN_SR_RBS3 (1 << 16) /* Bit 16: Receive Buffer Status */ -#define CAN_SR_DOS3 (1 << 17) /* Bit 17: Data Overrun Status */ -#define CAN_SR_TBS3 (1 << 18) /* Bit 18: Transmit Buffer Status 3 */ -#define CAN_SR_TCS3 (1 << 19) /* Bit 19: Transmission Complete Status */ -#define CAN_SR_RS3 (1 << 20) /* Bit 20: Receive Status */ -#define CAN_SR_TS3 (1 << 21) /* Bit 21: Transmit Status 3 */ -#define CAN_SR_ES3 (1 << 22) /* Bit 22: Error Status */ -#define CAN_SR_BS3 (1 << 23) /* Bit 23: Bus Status */ - /* Bits 24-31: Reserved */ -/* Receive frame status */ - -#define CAN_RFS_ID_SHIFT (0) /* Bits 0-9: ID Index */ -#define CAN_RFS_ID_MASK (0x03ff << CAN_RFS_ID_SHIFT) -#define CAN_RFS_BP (1 << 10) /* Bit 10: Received in AF Bypass mode */ - /* Bits 11-15: Reserved */ -#define CAN_RFS_DLC_SHIFT (16) /* Bits 16-19: Message Data Length Code (DLC) */ -#define CAN_RFS_DLC_MASK (15 << CAN_RFS_DLC_SHIFT) - /* Bits 20-29: Reserved */ -#define CAN_RFS_RTR (1 << 30) /* Bit 30: Message Remote Transmission Request */ -#define CAN_RFS_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ - -/* Received Identifier */ - -#define CAN_RID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ - /* Bits 11-31: Reserved */ -#define CAN_RID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ - /* Bits 29-31: Reserved */ -/* Received data bytes 1-4 */ - -#define CAN_RDA_DATA1_SHIFT (0) /* Bits 0-7: If CANRFS >= 1 */ -#define CAN_RDA_DATA1_MASK (0x0ff << CAN_RDA_DATA1_SHIFT) -#define CAN_RDA_DATA2_SHIFT (8) /* Bits 8-15: If CANRFS >= 2 */ -#define CAN_RDA_DATA2_MASK (0x0ff << CAN_RDA_DATA2_SHIFT) -#define CAN_RDA_DATA3_SHIFT (16) /* Bits 16-23: If CANRFS >= 3 */ -#define CAN_RDA_DATA3_MASK (0x0ff << CAN_RDA_DATA3_SHIFT) -#define CAN_RDA_DATA4_SHIFT (24) /* Bits 24-31: If CANRFS >= 4 */ -#define CAN_RDA_DATA4_MASK (0x0ff << CAN_RDA_DATA4_SHIFT) - -/* Received data bytes 5-8 */ - -#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: If CANRFS >= 5 */ -#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) -#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: If CANRFS >= 6 */ -#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) -#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: If CANRFS >= 7 */ -#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) -#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: If CANRFS >= 8 */ -#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) - -/* Transmit frame info (Tx Buffer 1), Transmit frame info (Tx Buffer 2), and - * Transmit frame info (Tx Buffer 3) common bit field definitions - */ - -#define CAN_TFI_PRIO_SHIFT (0) /* Bits 0-7: TX buffer priority */ -#define CAN_TFI_PRIO_MASK (0xff << CAN_TFI_PRIO_SHIFT) - /* Bits 8-15: Reserved */ -#define CAN_TFI_DLC_SHIFT (16) /* Bits 16-19: TX Data Length Code */ -#define CAN_TFI_DLC_MASK (15 << CAN_TFI_DLC_SHIFT) - /* Bits 20-29: Reserved */ -#define CAN_TFI_RTR (1 << 30) /* Bit 30: TX RTR bit */ -#define CAN_TFI_FF (1 << 31) /* Bit 31: Message 29-bit vs 11-bit ID */ - -/* Transmit Identifier (Tx Buffer 1), Transmit Identifier (Tx Buffer 2), and - * Transmit Identifier (Tx Buffer 3) common bit field definitions. - */ - -#define CAN_TID_ID11_MASK (0x7ff) /* Bits 0-10: 11-bit Identifier (FF=0) */ - /* Bits 11-31: Reserved */ -#define CAN_TID_ID29_MASK (0x1fffffff) /* Bits 0-28: 29-bit Identifiter (FF=1) */ - /* Bits 29-31: Reserved */ - -/* Transmit data bytes 1-4 (Tx Buffer 1), Transmit data bytes 1-4 (Tx Buffer 2), and - * Transmit data bytes 1-4 (Tx Buffer 3) common bit field definitions. - */ +/**************************************************************************** + * Public Types + ****************************************************************************/ -#define CAN_TDA_DATA1_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 1 */ -#define CAN_TDA_DATA1_MASK (0x0ff << CAN_TDA_DATA1_SHIFT) -#define CAN_TDA_DATA2_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 2 */ -#define CAN_TDA_DATA2_MASK (0x0ff << CAN_TDA_DATA2_SHIFT) -#define CAN_TDA_DATA3_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 3 */ -#define CAN_TDA_DATA3_MASK (0x0ff << CAN_TDA_DATA3_SHIFT) -#define CAN_TDA_DATA4_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 4 */ -#define CAN_TDA_DATA4_MASK (0x0ff << CAN_TDA_DATA4_SHIFT) +/**************************************************************************** + * Public Data + ****************************************************************************/ -/* Transmit data bytes 5-8 (Tx Buffer 1), Transmit data bytes 5-8 (Tx Buffer 2), and - * Transmit data bytes 5-8 (Tx Buffer 3) common bit field definitions. - */ +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif -#define CAN_RDB_DATA5_SHIFT (0) /* Bits 0-7: RTR=0 && DLC >= 5 */ -#define CAN_RDB_DATA5_MASK (0x0ff << CAN_RDB_DATA5_SHIFT) -#define CAN_RDB_DATA6_SHIFT (8) /* Bits 8-15: RTR=0 && DLC >= 6 */ -#define CAN_RDB_DATA6_MASK (0x0ff << CAN_RDB_DATA6_SHIFT) -#define CAN_RDB_DATA7_SHIFT (16) /* Bits 16-23: RTR=0 && DLC >= 7 */ -#define CAN_RDB_DATA7_MASK (0x0ff << CAN_RDB_DATA7_SHIFT) -#define CAN_RDB_DATA8_SHIFT (24) /* Bits 24-31: RTR=0 && DLC >= 8 */ -#define CAN_RDB_DATA8_MASK (0x0ff << CAN_RDB_DATA8_SHIFT) +/**************************************************************************** + * Public Functions + ****************************************************************************/ -/************************************************************************************ - * Public Types - ************************************************************************************/ +/**************************************************************************** + * Name: lpc17_caninitialize + * + * Description: + * Initialize the selected can port + * + * Input Parameter: + * Port number (for hardware that has mutiple can interfaces) + * + * Returned Value: + * Valid can device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ +#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2)) +struct can_dev_s; +FAR struct can_dev_s *lpc17_caninitialize(int port); +#endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CAN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c index 635090e9f..aba2079e4 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c @@ -48,8 +48,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" +#include "lpc17_clockconfig.h" +#include "chip/lpc17_syscon.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.h b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.h new file mode 100644 index 000000000..ffc9fa88d --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.h @@ -0,0 +1,84 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_clockconfig.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_clockconfig + * + * Description: + * Called to initialize the LPC17XX. This does whatever setup is needed to put the + * MCU in a usable state. This includes the initialization of clocking using the + * settings in board.h. + * + ************************************************************************************/ + +void lpc17_clockconfig(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CLOCKCONFIG_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c index 242f7ac4f..dcea79e7b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c @@ -44,7 +44,7 @@ #include "nvic.h" #include "up_arch.h" -#include "lpc17_internal.h" +#include "lpc17_clrpend.h" /**************************************************************************** * Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.h b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.h new file mode 100644 index 000000000..d7bf5b90d --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.h @@ -0,0 +1,84 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_clrpend.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. Don't know why... but the LPC1766 Ethernet EMAC + * interrupt definitely needs it! + * + ************************************************************************************/ + +void lpc17_clrpend(int irq); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CLRPEND_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c index 13ac212f6..87f49ba33 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.c @@ -60,9 +60,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" + +#include "chip/lpc17_syscon.h" #include "lpc17_dac.h" #ifdef CONFIG_LPC17_DAC diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h index a35e16eae..ac8477507 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_dac.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,47 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_dac.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_DAC_CR_OFFSET 0x0000 /* D/A Converter Register */ -#define LPC17_DAC_CTRL_OFFSET 0x0004 /* DAC Control register */ -#define LPC17_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_DAC_CR (LPC17_DAC_BASE+LPC17_DAC_CR_OFFSET) -#define LPC17_DAC_CTRL (LPC17_DAC_BASE+LPC17_DAC_CTRL_OFFSET) -#define LPC17_DAC_CNTVAL (LPC17_DAC_BASE+LPC17_DAC_CNTVAL_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* D/A Converter Register */ - /* Bits 0-5: Reserved */ -#define DAC_CR_VALUE_SHIFT (6) /* Bits 6-15: Controls voltage on the AOUT pin */ -#define DAC_CR_VALUE_MASK (0x3ff << DAC_CR_VALUE_SHIFT) -#define DAC_CR_BIAS (1 << 16) /* Bit 16: Controls DAC settling time */ - /* Bits 17-31: Reserved */ -/* DAC Control register */ - -#define DAC_CTRL_INTDMAREQ (1 << 0) /* Bit 0: Timer timed out */ -#define DAC_CTRL_DBLBUFEN (1 << 1) /* Bit 1: Enable DACR double-buffering */ -#define DAC_CTRL_CNTEN (1 << 2) /* Bit 2: Enable timeout counter */ -#define DAC_CTRL_DMAEN (1 << 3) /* Bit 3: Enable DMA access */ - /* Bits 4-31: Reserved */ -/* DAC Counter Value register */ - -#define DAC_CNTVAL_SHIFT (0) /* Bits 0-15: Reload value for DAC interrupt/DMA timer */ -#define DAC_CNTVAL_MASK (0xffff << DAC_CNTVAL_SHIFT) - /* Bits 8-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ @@ -90,8 +55,34 @@ * Public Data ************************************************************************************/ +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + /************************************************************************************ * Public Functions ************************************************************************************/ +/**************************************************************************** + * Name: lpc17_dacinitialize + * + * Description: + * Initialize the DAC + * + * Returned Value: + * Valid dac device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC17_DAC +FAR struct dac_dev_s *lpc17_dacinitialize(void); +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_DAC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h index 700ad7ec3..84a7ebb15 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h @@ -42,7 +42,7 @@ #include #include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c index 47a22ec2e..bf6d18287 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -57,12 +57,13 @@ #include #include -#include "chip.h" #include "up_arch.h" -#include "lpc17_syscon.h" +#include "chip.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_ethernet.h" #include "lpc17_emacram.h" -#include "lpc17_internal.h" +#include "lpc17_clrpend.h" #include diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h index f48c6d953..77ce1cc0f 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_ethernet.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,547 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_ethernet.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ -/* MAC registers */ - -#define LPC17_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */ -#define LPC17_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */ -#define LPC17_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */ -#define LPC17_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */ -#define LPC17_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */ -#define LPC17_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */ -#define LPC17_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */ -#define LPC17_ETH_TEST_OFFSET 0x001c /* Test register */ -#define LPC17_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */ -#define LPC17_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */ -#define LPC17_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */ -#define LPC17_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */ -#define LPC17_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */ -#define LPC17_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */ -#define LPC17_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */ -#define LPC17_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */ -#define LPC17_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */ - -/* Control registers */ - -#define LPC17_ETH_CMD_OFFSET 0x0100 /* Command register */ -#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */ -#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */ -#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */ -#define LPC17_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */ -#define LPC17_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */ -#define LPC17_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */ -#define LPC17_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */ -#define LPC17_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */ -#define LPC17_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */ -#define LPC17_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */ -#define LPC17_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */ -#define LPC17_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */ -#define LPC17_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */ -#define LPC17_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */ -#define LPC17_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */ -#define LPC17_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */ - -/* Rx filter registers */ - -#define LPC17_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */ -#define LPC17_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */ -#define LPC17_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */ -#define LPC17_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */ -#define LPC17_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */ - -/* Module control registers */ - -#define LPC17_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */ -#define LPC17_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */ -#define LPC17_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */ -#define LPC17_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */ -#define LPC17_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */ - -/* Register addresses ***************************************************************/ -/* MAC registers */ - -#define LPC17_ETH_MAC1 (LPC17_ETH_BASE+LPC17_ETH_MAC1_OFFSET) -#define LPC17_ETH_MAC2 (LPC17_ETH_BASE+LPC17_ETH_MAC2_OFFSET) -#define LPC17_ETH_IPGT (LPC17_ETH_BASE+LPC17_ETH_IPGT_OFFSET) -#define LPC17_ETH_IPGR (LPC17_ETH_BASE+LPC17_ETH_IPGR_OFFSET) -#define LPC17_ETH_CLRT (LPC17_ETH_BASE+LPC17_ETH_CLRT_OFFSET) -#define LPC17_ETH_MAXF (LPC17_ETH_BASE+LPC17_ETH_MAXF_OFFSET) -#define LPC17_ETH_SUPP (LPC17_ETH_BASE+LPC17_ETH_SUPP_OFFSET) -#define LPC17_ETH_TEST (LPC17_ETH_BASE+LPC17_ETH_TEST_OFFSET) -#define LPC17_ETH_MCFG (LPC17_ETH_BASE+LPC17_ETH_MCFG_OFFSET) -#define LPC17_ETH_MCMD (LPC17_ETH_BASE+LPC17_ETH_MCMD_OFFSET) -#define LPC17_ETH_MADR (LPC17_ETH_BASE+LPC17_ETH_MADR_OFFSET) -#define LPC17_ETH_MWTD (LPC17_ETH_BASE+LPC17_ETH_MWTD_OFFSET) -#define LPC17_ETH_MRDD (LPC17_ETH_BASE+LPC17_ETH_MRDD_OFFSET) -#define LPC17_ETH_MIND (LPC17_ETH_BASE+LPC17_ETH_MIND_OFFSET) -#define LPC17_ETH_SA0 (LPC17_ETH_BASE+LPC17_ETH_SA0_OFFSET) -#define LPC17_ETH_SA1 (LPC17_ETH_BASE+LPC17_ETH_SA1_OFFSET) -#define LPC17_ETH_SA2 (LPC17_ETH_BASE+LPC17_ETH_SA2_OFFSET) - -/* Control registers */ - -#define LPC17_ETH_CMD (LPC17_ETH_BASE+LPC17_ETH_CMD_OFFSET) -#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET) -#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET) -#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET) -#define LPC17_ETH_RXDESCNO (LPC17_ETH_BASE+LPC17_ETH_RXDESCNO_OFFSET) -#define LPC17_ETH_RXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_RXPRODIDX_OFFSET) -#define LPC17_ETH_RXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_RXCONSIDX_OFFSET) -#define LPC17_ETH_TXDESC (LPC17_ETH_BASE+LPC17_ETH_TXDESC_OFFSET) -#define LPC17_ETH_TXSTAT (LPC17_ETH_BASE+LPC17_ETH_TXSTAT_OFFSET) -#define LPC17_ETH_TXDESCRNO (LPC17_ETH_BASE+LPC17_ETH_TXDESCRNO_OFFSET) -#define LPC17_ETH_TXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_TXPRODIDX_OFFSET) -#define LPC17_ETH_TXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_TXCONSIDX_OFFSET) -#define LPC17_ETH_TSV0 (LPC17_ETH_BASE+LPC17_ETH_TSV0_OFFSET) -#define LPC17_ETH_TSV1 (LPC17_ETH_BASE+LPC17_ETH_TSV1_OFFSET) -#define LPC17_ETH_RSV (LPC17_ETH_BASE+LPC17_ETH_RSV_OFFSET) -#define LPC17_ETH_FCCNTR (LPC17_ETH_BASE+LPC17_ETH_FCCNTR_OFFSET) -#define LPC17_ETH_FCSTAT (LPC17_ETH_BASE+LPC17_ETH_FCSTAT_OFFSET) - -/* Rx filter registers */ - -#define LPC17_ETH_RXFLCTRL (LPC17_ETH_BASE+LPC17_ETH_RXFLCTRL_OFFSET) -#define LPC17_ETH_RXFLWOLST (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLST_OFFSET) -#define LPC17_ETH_RXFLWOLCLR (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLCLR_OFFSET) -#define LPC17_ETH_HASHFLL (LPC17_ETH_BASE+LPC17_ETH_HASHFLL_OFFSET) -#define LPC17_ETH_HASHFLH (LPC17_ETH_BASE+LPC17_ETH_HASHFLH_OFFSET) - -/* Module control registers */ - -#define LPC17_ETH_INTST (LPC17_ETH_BASE+LPC17_ETH_INTST_OFFSET) -#define LPC17_ETH_INTEN (LPC17_ETH_BASE+LPC17_ETH_INTEN_OFFSET) -#define LPC17_ETH_INTCLR (LPC17_ETH_BASE+LPC17_ETH_INTCLR_OFFSET) -#define LPC17_ETH_INTSET (LPC17_ETH_BASE+LPC17_ETH_INTSET_OFFSET) -#define LPC17_ETH_PWRDOWN (LPC17_ETH_BASE+LPC17_ETH_PWRDOWN_OFFSET) - -/* Register bit definitions *********************************************************/ -/* MAC registers */ -/* MAC configuration register 1 (MAC1) */ - -#define ETH_MAC1_RE (1 << 0) /* Bit 0: Receive enable */ -#define ETH_MAC1_PARF (1 << 1) /* Bit 1: Passall all receive frames */ -#define ETH_MAC1_RFC (1 << 2) /* Bit 2: RX flow control */ -#define ETH_MAC1_TFC (1 << 3) /* Bit 3: TX flow control */ -#define ETH_MAC1_LPBK (1 << 4) /* Bit 4: Loopback */ - /* Bits 5-7: Reserved */ -#define ETH_MAC1_TXRST (1 << 8) /* Bit 8: Reset TX */ -#define ETH_MAC1_MCSTXRST (1 << 9) /* Bit 9: Reset MCS/TX */ -#define ETH_MAC1_RXRST (1 << 10) /* Bit 10: Reset RX */ -#define ETH_MAC1_MCSRXRST (1 << 11) /* Bit 11: Reset MCS/RX */ - /* Bits 12-13: Reserved */ -#define ETH_MAC1_SIMRST (1 << 14) /* Bit 14: Simulation reset */ -#define ETH_MAC1_SOFTRST (1 << 15) /* Bit 15: Soft reset */ - /* Bits 16-31: Reserved */ -/* MAC configuration register 2 (MAC2) */ - -#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */ -#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */ -#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge frame enable */ -#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */ -#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */ -#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */ -#define ETH_MAC2_VLANPADEN (1 << 6) /* Bit 6: VLAN pad enable */ -#define ETH_MAC2_AUTOPADEN (1 << 7) /* Bit 7: Auto detect pad enable */ -#define ETH_MAC2_PPE (1 << 8) /* Bit 8: Pure preamble enforcement */ -#define ETH_MAC2_LPE (1 << 9) /* Bit 9: Long preamble enforcement */ - /* Bits 10-11: Reserved */ -#define ETH_MAC2_NBKOFF (1 << 12) /* Bit 12: No backoff */ -#define ETH_MAC2_BPNBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */ -#define ETH_MAC2_EXDEF (1 << 14) /* Bit 14: Excess defer */ - /* Bits 15-31: Reserved */ -/* Back-to-Back Inter-Packet-Gap register (IPGT) */ - -#define ETH_IPGT_SHIFT (0) /* Bits 0-6 */ -#define ETH_IPGT_MASK (0x7f << ETH_IPGT_SHIFT) - /* Bits 7-31: Reserved */ -/* Non Back-to-Back Inter-Packet-Gap register (IPGR) */ - -#define ETH_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */ -#define ETH_IPGR_GAP2_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) - /* Bit 7: Reserved */ -#define ETH_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */ -#define ETH_IPGR_GAP1_MASK (0x7f << ETH_IPGR_GAP2_SHIFT) - /* Bits 15-31: Reserved */ -/* Collision window / Retry register (CLRT) */ - -#define ETH_CLRT_RMAX_SHIFT (0) /* Bits 0-3: Retransmission maximum */ -#define ETH_CLRT_RMAX_MASK (15 << ETH_CLRT_RMAX_SHIFT) - /* Bits 4-7: Reserved */ -#define ETH_CLRT_COLWIN_SHIFT (8) /* Bits 8-13: Collision window */ -#define ETH_CLRT_COLWIN_MASK (0x3f << ETH_CLRT_COLWIN_SHIFT) - /* Bits 14-31: Reserved */ -/* Maximum Frame register (MAXF) */ - -#define ETH_MAXF_SHIFT (0) /* Bits 0-15 */ -#define ETH_MAXF_MASK (0xffff << ETH_MAXF_SHIFT) - /* Bits 16-31: Reserved */ -/* PHY Support register (SUPP) */ - /* Bits 0-7: Reserved */ -#define ETH_SUPP_SPEED (1 << 8) /* Bit 8: 0=10Bps 1=100Bps */ - /* Bits 9-31: Reserved */ -/* Test register (TEST) */ - -#define ETH_TEST_SPQ (1 << 0) /* Bit 0: Shortcut pause quanta */ -#define ETH_TEST_TP (1 << 1) /* Bit 1: Test pause */ -#define ETH_TEST_TBP (1 << 2) /* Bit 2: Test packpressure */ - /* Bits 3-31: Reserved */ -/* MII Mgmt Configuration register (MCFG) */ - -#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */ -#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */ -#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5: Clock select */ -#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV8 (3 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV10 (4 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV14 (5 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV20 (6 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV28 (7 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV36 (8 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV40 (9 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV44 (10 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV48 (11 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV52 (12 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV56 (13 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV60 (14 << ETH_MCFG_CLKSEL_SHIFT) -# define ETH_MCFG_CLKSEL_DIV64 (15 << ETH_MCFG_CLKSEL_SHIFT) - /* Bits 6-14: Reserved */ -#define ETH_MCFG_MIIRST (1 << 15) /* Bit 15: Reset MII mgmt */ - /* Bits 16-31: Reserved */ -/* MII Mgmt Command register (MCMD) */ - -#define ETH_MCMD_READ (1 << 0) /* Bit 0: Single read cycle */ -#define ETH_MCMD_SCAN (1 << 1) /* Bit 1: Continuous read cycles */ - /* Bits 2-31: Reserved */ -#define ETH_MCMD_WRITE (0) - -/* MII Mgmt Address register (MADR) */ - -#define ETH_MADR_REGADDR_SHIFT (0) /* Bits 0-4: Register address */ -#define ETH_MADR_REGADDR_MASK (31 << ETH_MADR_REGADDR_SHIFT) - /* Bits 7-5: Reserved */ -#define ETH_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */ -#define ETH_MADR_PHYADDR_MASK (31 << ETH_MADR_PHYADDR_SHIFT) - /* Bits 13-31: Reserved */ -/* MII Mgmt Write Data register (MWTD) */ - -#define ETH_MWTD_SHIFT (0) /* Bits 0-15 */ -#define ETH_MWTD_MASK (0xffff << ETH_MWTD_SHIFT) - /* Bits 16-31: Reserved */ -/* MII Mgmt Read Data register (MRDD) */ - -#define ETH_MRDD_SHIFT (0) /* Bits 0-15 */ -#define ETH_MRDD_MASK (0xffff << ETH_MRDD_SHIFT) - /* Bits 16-31: Reserved */ -/* MII Mgmt Indicators register (MIND) */ - -#define ETH_MIND_BUSY (1 << 0) /* Bit 0: Busy */ -#define ETH_MIND_SCANNING (1 << 1) /* Bit 1: Scanning */ -#define ETH_MIND_NVALID (1 << 2) /* Bit 2: Not valid */ -#define ETH_MIND_MIIFAIL (1 << 3) /* Bit 3: MII link fail */ - /* Bits 4-31: Reserved */ -/* Station Address 0 register (SA0) */ - -#define ETH_SA0_OCTET2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */ -#define ETH_SA0_OCTET2_MASK (0xff << ETH_SA0_OCTET2_SHIFT) -#define ETH_SA0_OCTET1_SHIFT (8) /* Bits 8-15: Station address 1st octet */ -#define ETH_SA0_OCTET1_MASK (0xff << ETH_SA0_OCTET1_SHIFT) - /* Bits 16-31: Reserved */ -/* Station Address 1 register (SA1) */ - -#define ETH_SA1_OCTET4_SHIFT (0) /* Bits 0-7: Station address 4th octet */ -#define ETH_SA1_OCTET4_MASK (0xff << ETH_SA0_OCTET4_SHIFT) -#define ETH_SA1_OCTET3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */ -#define ETH_SA1_OCTET3_MASK (0xff << ETH_SA0_OCTET3_SHIFT) - /* Bits 16-31: Reserved */ -/* Station Address 2 register (SA2) */ - -#define ETH_SA2_OCTET6_SHIFT (0) /* Bits 0-7: Station address 5th octet */ -#define ETH_SA2_OCTET6_MASK (0xff << ETH_SA0_OCTET6_SHIFT) -#define ETH_SA2_OCTET5_SHIFT (8) /* Bits 8-15: Station address 6th octet */ -#define ETH_SA2_OCTET5_MASK (0xff << ETH_SA0_OCTET5_SHIFT) - /* Bits 16-31: Reserved */ -/* Control registers */ -/* Command register (CMD) */ - -#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */ -#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */ - /* Bit 2: Reserved */ -#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */ -#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */ -#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */ -#define ETH_CMD_PRFRAME (1 << 6) /* Bit 6: Pass run frame */ -#define ETH_CMD_PRFILTER (1 << 7) /* Bit 7: Pass RX filter */ -#define ETH_CMD_TXFC (1 << 8) /* Bit 8: TX flow control */ -#define ETH_CMD_RMII (1 << 9) /* Bit 9: RMII mode */ -#define ETH_CMD_FD (1 << 10) /* Bit 10: Full duplex */ - /* Bits 11-31: Reserved */ -/* Status register */ - -#define ETH_STAT_RX (1 << 0) /* Bit 0: RX status */ -#define ETH_STAT_TX (1 << 1) /* Bit 1: TX status */ - /* Bits 2-31: Reserved */ -/* Receive descriptor base address register (RXDESC) - * - * The receive descriptor base address is a byte address aligned to a word - * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest - * address in the array of descriptors. - */ - -/* Receive status base address register (RXSTAT) - * - * The receive status base address is a byte address aligned to a double word - * boundary i.e. LSB 2:0 are fixed to 000. - */ - -/* Receive number of descriptors register (RXDESCNO) */ - -#define ETH_RXDESCNO_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXDESCNO_MASK (0xffff << ETH_RXDESCNO_SHIFT) - /* Bits 16-31: Reserved */ -/* Receive produce index register (RXPRODIDX) */ - -#define ETH_RXPRODIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXPRODIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Receive consume index register (RXCONSIDX) */ - -#define ETH_RXCONSIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_RXCONSIDX_MASK (0xffff << ETH_RXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit descriptor base address register (TXDESC) - * - * The transmit descriptor base address is a byte address aligned to a word - * boundary i.e. LSB 1:0 are fixed to 00. The register contains the lowest - * address in the array of descriptors. - */ - -/* Transmit status base address register (TXSTAT) - * - * The transmit status base address is a byte address aligned to a word - * boundary i.e. LSB1:0 are fixed to 00. The register contains the lowest - * address in the array of statuses. - */ - -/* Transmit number of descriptors register (TXDESCRNO) */ - -#define ETH_TXDESCRNO_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXDESCRNO_MASK (0xffff << ETH_TXDESCRNO_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit produce index register (TXPRODIDX) */ - -#define ETH_TXPRODIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXPRODIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit consume index register (TXCONSIDX) */ - -#define ETH_TXCONSIDX_SHIFT (0) /* Bits 0-15 */ -#define ETH_TXCONSIDX_MASK (0xffff << ETH_TXPRODIDX_SHIFT) - /* Bits 16-31: Reserved */ -/* Transmit status vector 0 register (TSV0) */ - -#define ETH_TSV0_CRCERR (1 << 0) /* Bit 0: CRC error */ -#define ETH_TSV0_LENCHKERR (1 << 1) /* Bit 1: Length check error */ -#define ETH_TSV0_LENOOR (1 << 2) /* Bit 2: Length out of range */ -#define ETH_TSV0_DONE (1 << 3) /* Bit 3: Done */ -#define ETH_TSV0_MCAST (1 << 4) /* Bit 4: Multicast */ -#define ETH_TSV0_BCAST (1 << 5) /* Bit 5: Broadcast */ -#define ETH_TSV0_PKTDEFER (1 << 6) /* Bit 6: Packet Defer */ -#define ETH_TSV0_EXCDEFER (1 << 7) /* Bit 7: Excessive Defer */ -#define ETH_TSV0_EXCCOL (1 << 8) /* Bit 8: Excessive Collision */ -#define ETH_TSV0_LATECOL (1 << 9) /* Bit 9: Late Collision */ -#define ETH_TSV0_GIANT (1 << 10) /* Bit 10: Giant */ -#define ETH_TSV0_UNDRUN (1 << 11) /* Bit 11: Underrun */ -#define ETH_TSV0_TOTBYTES_SHIFT (12) /* Bits 12-27:Total bytes */ -#define ETH_TSV0_TOTBYTES_MASK (0xffff << ETH_TSV0_TOTBYTES_SHIFT) -#define ETH_TSV0_CTLFRAME (1 << 28) /* Bit 28: Control frame */ -#define ETH_TSV0_PAUSE (1 << 29) /* Bit 29: Pause */ -#define ETH_TSV0_BP (1 << 30) /* Bit 30: Backpressure */ -#define ETH_TSV0_VLAN (1 << 31) /* Bit 31: VLAN */ - -/* Transmit status vector 1 register (TSV1) */ - -#define ETH_TSV1_TXCNT_SHIFT (0) /* Bits 0-15: Transmit byte count */ -#define ETH_TSV1_TXCNT_MASK (0xffff << ETH_TSV1_TXCNT_SHIFT) -#define ETH_TSV1_COLCNT_SHIFT (16) /* Bits 16-19: Transmit collision count */ -#define ETH_TSV1_COLCNT_MASK (15 << ETH_TSV1_COLCNT_SHIFT) - /* Bits 20-31: Reserved */ -/* Receive status vector register (RSV) */ - -#define ETH_RSV_RXCNT_SHIFT (0) /* Bits 0-15: Received byte count */ -#define ETH_RSV_RXCNT_MASK (0xffff << ETH_RSV_RXCNT_SHIFT) -#define ETH_RSV_PKTPI (1 << 16) /* Bit 16: Packet previously ignored */ -#define ETH_RSV_RXEPS (1 << 17) /* Bit 17: RXDV event previously seen */ -#define ETH_RSV_CEPS (1 << 18) /* Bit 18: Carrier event previously seen */ -#define ETH_RSV_RXCV (1 << 19) /* Bit 19: Receive code violation */ -#define ETH_RSV_CRCERR (1 << 20) /* Bit 20: CRC error */ -#define ETH_RSV_LENCHKERR (1 << 21) /* Bit 21: Length check error */ -#define ETH_RSV_LENOOR (1 << 22) /* Bit 22: Length out of range */ -#define ETH_RSV_RXOK (1 << 23) /* Bit 23: Receive OK */ -#define ETH_RSV_MCAST (1 << 24) /* Bit 24: Multicast */ -#define ETH_RSV_BCAST (1 << 25) /* Bit 25: Broadcast */ -#define ETH_RSV_DRIBNIB (1 << 26) /* Bit 26: Dribble Nibble */ -#define ETH_RSV_CTLFRAME (1 << 27) /* Bit 27: Control frame */ -#define ETH_RSV_PAUSE (1 << 28) /* Bit 28: Pause */ -#define ETH_RSV_UNSUPOP (1 << 29) /* Bit 29: Unsupported Opcode */ -#define ETH_RSV_VLAN (1 << 30) /* Bit 30: VLAN */ - /* Bit 31: Reserved */ -/* Flow control counter register (FCCNTR) */ - -#define ETH_FCCNTR_MCOUNT_SHIFT (0) /* Bits 0-15: Mirror count */ -#define ETH_FCCNTR_MCOUNT_MASK (0xffff << ETH_FCCNTR_MCOUNT_SHIFT) -#define ETH_FCCNTR_PTMR_SHIFT (16) /* Bits 16-31: Pause timer */ -#define ETH_FCCNTR_PTMR_MASK (0xffff << ETH_FCCNTR_PTMR_SHIFT) - -/* Flow control status register (FCSTAT) */ - -#define ETH_FCSTAT_MCOUNT_SHIFT (0) /* Bits 0-15: Current mirror count */ -#define ETH_FCSTAT_MCOUNT_MASK (0xffff << ETH_FCSTAT_MCOUNT_SHIFT) - /* Bits 16-31: Reserved */ -/* Rx filter registers */ -/* Receive filter control register (RXFLCTRL) */ - -#define ETH_RXFLCTRL_UCASTEN (1 << 0) /* Bit 0: Accept all unicast frames */ -#define ETH_RXFLCTRL_BCASTEN (1 << 1) /* Bit 1: Accept all broadcast frames */ -#define ETH_RXFLCTRL_MCASTEN (1 << 2) /* Bit 2: Accept all multicast frames */ -#define ETH_RXFLCTRL_UCASTHASHEN (1 << 3) /* Bit 3: Accept hashed unicast */ -#define ETH_RXFLCTRL_MCASTHASHEN (1 << 4) /* Bit 4: Accect hashed multicast */ -#define ETH_RXFLCTRL_PERFEN (1 << 5) /* Bit 5: Accept perfect dest match */ - /* Bits 6-11: Reserved */ -#define ETH_RXFLCTRL_MPKTEN (1 << 12) /* Bit 12: Magic pkt filter WoL int */ -#define ETH_RXFLCTRL_RXFILEN (1 << 13) /* Bit 13: Perfect match WoL interrupt */ - /* Bits 14-31: Reserved */ -/* Receive filter WoL status register (RXFLWOLST) AND - * Receive filter WoL clear register (RXFLWOLCLR) - */ - -#define ETH_RXFLWOL_UCAST (1 << 0) /* Bit 0: Unicast frame WoL */ -#define ETH_RXFLWOL_BCAST (1 << 1) /* Bit 1: Broadcast frame WoL */ -#define ETH_RXFLWOL_MCAST (1 << 2) /* Bit 2: Multicast frame WoL */ -#define ETH_RXFLWOL_UCASTHASH (1 << 3) /* Bit 3: Unicast hash filter WoL */ -#define ETH_RXFLWOL_MCASTHASH (1 << 4) /* Bit 4: Multiicast hash filter WoL */ -#define ETH_RXFLWOL_PERF (1 << 5) /* Bit 5: Perfect addr match WoL */ - /* Bit 6: Reserved */ -#define ETH_RXFLWOL_RXFIL (1 << 7) /* Bit 7: Receive filter WoL */ -#define ETH_RXFLWOL_MPKT (1 << 8) /* Bit 8: Magic pkt filter WoL */ - /* Bits 9-31: Reserved */ -/* Hash filter table LSBs register (HASHFLL) AND Hash filter table MSBs register -* (HASHFLH) Are registers containing a 32-bit value with no bitfield. - */ - -/* Module control registers */ -/* Interrupt status register (INTST), Interrupt enable register (INTEN), Interrupt - * clear register (INTCLR), and Interrupt set register (INTSET) common bit field - * definition: - */ - -#define ETH_INT_RXOVR (1 << 0) /* Bit 0: RX overrun interrupt */ -#define ETH_INT_RXERR (1 << 1) /* Bit 1: RX error interrupt */ -#define ETH_INT_RXFIN (1 << 2) /* Bit 2: RX finished interrupt */ -#define ETH_INT_RXDONE (1 << 3) /* Bit 3: RX done interrupt */ -#define ETH_INT_TXUNR (1 << 4) /* Bit 4: TX underrun interrupt */ -#define ETH_INT_TXERR (1 << 5) /* Bit 5: TX error interrupt */ -#define ETH_INT_TXFIN (1 << 6) /* Bit 6: TX finished interrupt */ -#define ETH_INT_TXDONE (1 << 7) /* Bit 7: TX done interrupt */ - /* Bits 8-11: Reserved */ -#define ETH_INT_SOFT (1 << 12) /* Bit 12: Soft interrupt */ -#define ETH_INT_WKUP (1 << 13) /* Bit 13: Wakeup interrupt */ - /* Bits 14-31: Reserved */ -/* Power-down register */ - /* Bits 0-30: Reserved */ -#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */ - -/* Descriptors Offsets **************************************************************/ - -/* Tx descriptor offsets */ - -#define LPC17_TXDESC_PACKET 0x00 /* Base address of the Tx data buffer */ -#define LPC17_TXDESC_CONTROL 0x04 /* Control Information */ -#define LPC17_TXDESC_SIZE 0x08 /* Size in bytes of one Tx descriptor */ - -/* Tx status offsets */ - -#define LPC17_TXSTAT_INFO 0x00 /* Transmit status return flags */ -#define LPC17_TXSTAT_SIZE 0x04 /* Size in bytes of one Tx status */ - -/* Rx descriptor offsets */ - -#define LPC17_RXDESC_PACKET 0x00 /* Base address of the Rx data buffer */ -#define LPC17_RXDESC_CONTROL 0x04 /* Control Information */ -#define LPC17_RXDESC_SIZE 0x08 /* Size in bytes of one Rx descriptor */ - -/* Rx status offsets */ - -#define LPC17_RXSTAT_INFO 0x00 /* Receive status return flags */ -#define LPC17_RXSTAT_HASHCRC 0x04 /* Dest and source hash CRC */ -#define LPC17_RXSTAT_SIZE 0x08 /* Size in bytes of one Rx status */ - -/* Descriptor Bit Definitions *******************************************************/ - -/* Tx descriptor bit definitions */ - -#define TXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ -#define TXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) - -#define TXDESC_CONTROL_OVERRIDE (1 << 26 /* Bit 26: Per-frame override */ -#define TXDESC_CONTROL_HUGE (1 << 27) /* Bit 27: Enable huge frame size */ -#define TXDESC_CONTROL_PAD (1 << 28) /* Bit 28: Pad short frames */ -#define TXDESC_CONTROL_CRC (1 << 29) /* Bit 29: Append CRC */ -#define TXDESC_CONTROL_LAST (1 << 30) /* Bit 30: Last descriptor of a fragment */ -#define TXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate TxDone interrupt */ - -/* Tx status bit definitions */ - -#define TXSTAT_INFO_COLCNT_SHIFT (21) /* Bits 21-24: Number of collisions */ -#define TXSTAT_INFO_COLCNT_MASK (15 << TXSTAT_INFO_COLCNT_SHIFT) -#define TXSTAT_INFO_DEFER (1 << 25) /* Bit 25: Packet deffered */ -#define TXSTAT_INFO_EXCESSDEFER (1 << 26) /* Bit 26: Excessive packet defferals */ -#define TXSTAT_INFO_EXCESSCOL (1 << 27) /* Bit 27: Excessive packet collisions */ -#define TXSTAT_INFO_LATECOL (1 << 28) /* Bit 28: Out of window collision */ -#define TXSTAT_INFO_UNDERRUN (1 << 29) /* Bit 29: Tx underrun */ -#define TXSTAT_INFO_NODESC (1 << 30) /* Bit 29: No Tx descriptor available */ -#define TXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ - -/* Rx descriptor bit definitions */ - -#define RXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */ -#define RXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT) -#define RXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate RxDone interrupt */ - -/* Rx status bit definitions */ - -#define RXSTAT_SAHASHCRC_SHIFT (0) /* Bits 0-8: Hash CRC calculated from the source address */ -#define RXSTAT_SAHASHCRC_MASK (0x1ff << RXSTAT_SAHASHCRC_SHIFT) -#define RXSTAT_DAHASHCRC_SHIFT (16) /* Bits 16-24: Hash CRC calculated from the dest address */ -#define RXSTAT_DAHASHCRC_MASK (0x1ff << RXSTAT_DAHASHCRC_SHIFT) - -#define RXSTAT_INFO_RXSIZE_SHIFT (0) /* Bits 0-10: Size of actual data transferred */ -#define RXSTAT_INFO_RXSIZE_MASK (0x7ff << RXSTAT_INFO_RXSIZE_SHIFT) -#define RXSTAT_INFO_CONTROL (1 << 18) /* Bit 18: This is a control frame */ -#define RXSTAT_INFO_VLAN (1 << 19) /* Bit 19: This is a VLAN frame */ -#define RXSTAT_INFO_FAILFILTER (1 << 20) /* Bit 20: Frame failed Rx filter */ -#define RXSTAT_INFO_MULTICAST (1 << 21) /* Bit 21: This is a multicast frame */ -#define RXSTAT_INFO_BROADCAST (1 << 22) /* Bit 22: This is a broadcast frame */ -#define RXSTAT_INFO_CRCERROR (1 << 23) /* Bit 23: Received frame had a CRC error */ -#define RXSTAT_INFO_SYMBOLERROR (1 << 24) /* Bit 24: PHY reported bit error */ -#define RXSTAT_INFO_LENGTHERROR (1 << 25) /* Bit 25: Invalid frame length */ -#define RXSTAT_INFO_RANGEERROR (1 << 26) /* Bit 26: Exceeds maximum packet size */ -#define RXSTAT_INFO_ALIGNERROR (1 << 27) /* Bit 27: Alignment error */ -#define RXSTAT_INFO_OVERRUN (1 << 28) /* Bit 28: Receive overrun error */ -#define RXSTAT_INFO_NODESC (1 << 29) /* Bit 29: No Rx descriptor available */ -#define RXSTAT_INFO_LASTFLAG (1 << 30) /* Bit 30: Last fragment of a frame */ -#define RXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */ - /************************************************************************************ * Public Types ************************************************************************************/ @@ -590,8 +55,19 @@ * Public Data ************************************************************************************/ +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + /************************************************************************************ * Public Functions ************************************************************************************/ +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c index f567d52c0..4833fff3b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -51,8 +51,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" + +#include "chip/lpc17_syscon.h" #include "lpc17_gpdma.h" #ifdef CONFIG_LPC17_GPDMA diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h index c0e70efa5..41e60877d 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_gpdma.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,377 +41,190 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_gpdma.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ -#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ -#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ -#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ -#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ -#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ -#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ -#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ -#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ -#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ -#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ -#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ -#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ -#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ - -/* Channel Registers */ - -#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */ - -#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ -#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ -#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ -#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ -#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ - -#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) - -/* Register addresses ***************************************************************/ -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) -#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) -#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) -#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) -#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) -#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) -#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) -#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) -#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) -#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) -#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) -#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) -#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) -#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) - -/* Channel Registers */ - -#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) - -#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* DMA request connections */ - -#define DMA_REQ_SSP0TX (0) -#define DMA_REQ_SSP0RX (1) -#define DMA_REQ_SSP1TX (2) -#define DMA_REQ_SSP1RX (3) -#define DMA_REQ_ADC (4) -#define DMA_REQ_I2SCH0 (5) -#define DMA_REQ_I2SCH1 (6) -#define DMA_REQ_DAC (7) - -#define DMA_REQ_UART0TX (8) -#define DMA_REQ_UART0RX (9) -#define DMA_REQ_UART1TX (10) -#define DMA_REQ_UART1RX (11) -#define DMA_REQ_UART2TX (12) -#define DMA_REQ_UART2RX (13) -#define DMA_REQ_UART3TX (14) -#define DMA_REQ_UART3RX (15) - -#define DMA_REQ_MAT0p0 (8) -#define DMA_REQ_MAT0p1 (9) -#define DMA_REQ_MAT1p0 (10) -#define DMA_REQ_MAT1p1 (11) -#define DMA_REQ_MAT2p0 (12) -#define DMA_REQ_MAT2p1 (13) -#define DMA_REQ_MAT3p0 (14) -#define DMA_REQ_MAT3p1 (15) - -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ -/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, - * respectively. Bits 8-31 are reserved. - * - * DMA Interrupt Status Register - * DMA Interrupt Terminal Count Request Status Register - * DMA Interrupt Terminal Count Request Clear Register - * DMA Interrupt Error Status Register - * DMA Interrupt Error Clear Register - * DMA Raw Interrupt Terminal Count Status Register - * DMA Raw Error Interrupt Status Register - * DMA Enabled Channel Register - */ - -#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ - -/* For each of the following registers, bits 0-15 represent a set of encoded - * DMA sources. Bits 16-31 are reserved in each case. - * - * DMA Software Burst Request Register - * DMA Software Single Request Register - * DMA Software Last Burst Request Register - * DMA Software Last Single Request Register - * DMA Synchronization Register - */ - -#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) -#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) -#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) -#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) -#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) -#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) -#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) -#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) - -#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) -#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) -#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) -#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) -#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) -#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) -#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) -#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) - -#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) -#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) -#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) -#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) -#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) -#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) -#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) -#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) - -/* DMA Configuration Register */ - -#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ -#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ - /* Bits 2-31: Reserved */ -/* Channel Registers */ - -/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ -/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ -/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list - * item. Bits 0-1 must be zero. - */ - -/* DMA Channel Control Register */ - -#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ -#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) -#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ -#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) -#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ -#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) -#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ -#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) -#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ -#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) -#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ -#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ -#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ -#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ -#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ -#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ - -/* DMA Channel Configuration Register */ - - -#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ -#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ -#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) -#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */ -#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) -#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ -#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) -# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */ -# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */ -# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */ -# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */ -#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ -#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ -#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ -#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ -#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ - /* Bits 19-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ +#ifdef CONFIG_LPC17_GPDMA + +typedef FAR void *DMA_HANDLE; +typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct lpc17_dmaglobalregs_s +{ + /* Global Registers */ + + uint32_t intst; /* DMA Interrupt Status Register */ + uint32_t inttcst; /* DMA Interrupt Terminal Count Request Status Register */ + uint32_t interrst; /* DMA Interrupt Error Status Register */ + uint32_t rawinttcst; /* DMA Raw Interrupt Terminal Count Status Register */ + uint32_t rawinterrst; /* DMA Raw Error Interrupt Status Register */ + uint32_t enbldchns; /* DMA Enabled Channel Register */ + uint32_t softbreq; /* DMA Software Burst Request Register */ + uint32_t softsreq; /* DMA Software Single Request Register */ + uint32_t softlbreq; /* DMA Software Last Burst Request Register */ + uint32_t softlsreq; /* DMA Software Last Single Request Register */ + uint32_t config; /* DMA Configuration Register */ + uint32_t sync; /* DMA Synchronization Register */ +}; + +struct lpc17_dmachanregs_s +{ + /* Channel Registers */ + + uint32_t srcaddr; /* DMA Channel Source Address Register */ + uint32_t destaddr; /* DMA Channel Destination Address Register */ + uint32_t lli; /* DMA Channel Linked List Item Register */ + uint32_t control; /* DMA Channel Control Register */ + uint32_t config; /* DMA Channel Configuration Register */ +}; + +struct lpc17_dmaregs_s +{ + /* Global Registers */ + + struct lpc17_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct lpc17_dmachanregs_s ch; +}; + +#endif /* CONFIG_DEBUG_DMA */ + /************************************************************************************ * Public Data ************************************************************************************/ +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + /************************************************************************************ * Public Functions ************************************************************************************/ +/**************************************************************************** + * Name: lpc17_dmainitialize + * + * Description: + * Initialize the GPDMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void lpc17_dmainitilaize(void); + +/**************************************************************************** + * Name: lpc17_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +DMA_HANDLE lpc17_dmachannel(void); + +/**************************************************************************** + * Name: lpc17_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until lpc17_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void lpc17_dmafree(DMA_HANDLE handle); + +/**************************************************************************** + * Name: lpc17_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +int lpc17_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes); + +/**************************************************************************** + * Name: lpc17_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: lpc17_dmastop + * + * Description: + * Cancel the DMA. After lpc17_dmastop() is called, the DMA channel is + * reset and lpc17_dmasetup() must be called before lpc17_dmastart() can be + * called again + * + ****************************************************************************/ + +void lpc17_dmastop(DMA_HANDLE handle); + +/**************************************************************************** + * Name: lpc17_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +EXTERN void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); +#else +# define lpc17_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: lpc17_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +EXTERN void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, + const char *msg); +#else +# define lpc17_dmadump(handle,regs,msg) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC17_GPDMA */ #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c index 4cc73a3fc..9db9b136b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -49,8 +50,7 @@ #include "up_arch.h" #include "chip.h" #include "lpc17_gpio.h" -#include "lpc17_pinconn.h" -#include "lpc17_internal.h" + /**************************************************************************** * Pre-processor Definitions @@ -199,6 +199,7 @@ static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) putreg32(regval, regaddr); return OK; } + return -EINVAL; } @@ -265,6 +266,7 @@ static int lpc17_pullup(uint16_t cfgset, unsigned int port, unsigned int pin) putreg32(regval, regaddr); return OK; } + return -EINVAL; } @@ -518,6 +520,7 @@ static int lpc17_configalternate(uint16_t cfgset, unsigned int port, lpc17_setopendrain(port, pin); } + return OK; } @@ -582,6 +585,7 @@ int lpc17_configgpio(uint16_t cfgset) break; } } + return ret; } @@ -651,5 +655,6 @@ bool lpc17_gpioread(uint16_t pinset) pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; return ((getreg32(fiobase + LPC17_FIO_PIN_OFFSET) & (1 << pin)) != 0); } - return 0; + + return false; } diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h index 002ef3faf..dad14bc9e 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_gpio.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,144 +42,128 @@ #include -#include "chip.h" -#include "lpc17_memorymap.h" +#ifndef __ASSEMBLY__ +# include +#endif + +#include "chip/lpc17_gpio.h" +#include "chip/lpc17_pinconn.h" +#include "chip/lpc17_pinconfig.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* Bit-encoded input to lpc17_configgpio() ******************************************/ -/* Register offsets *****************************************************************/ -/* GPIO block register offsets ******************************************************/ - -#define LPC17_FIO0_OFFSET 0x0000 -#define LPC17_FIO1_OFFSET 0x0020 -#define LPC17_FIO2_OFFSET 0x0040 -#define LPC17_FIO3_OFFSET 0x0060 -#define LPC17_FIO4_OFFSET 0x0080 - -#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ -#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ -#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ -#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ -#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ - -/* GPIO interrupt block register offsets ********************************************/ - -#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) -#define LPC17_GPIOINT0_OFFSET 0x0080 -#define LPC17_GPIOINT2_OFFSET 0x00a0 - -#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ -#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ -#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ -#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ -#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ -#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ - -/* Register addresses ***************************************************************/ -/* GPIO block register addresses ****************************************************/ - -#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) -#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) -#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) -#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) -#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) - -#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) - -/* GPIO interrupt block register addresses ******************************************/ - -#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) -#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) - -#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) - -#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ - -#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P2.0-13 (P0.14-31 are reserved) */ - -#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Register bit definitions *********************************************************/ -/* GPIO block register bit definitions **********************************************/ - -/* Fast GPIO Port Direction control registers (FIODIR) */ -/* Fast Mask register for ports (FIOMASK) */ -/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ -/* Fast Port Output Set registers using FIOMASK (FIOSET) */ -/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ - -#define FIO(n) (1 << (n)) /* n=0,1,..31 */ - -/* GPIO interrupt block register bit definitions ************************************/ - -/* GPIO overall Interrupt Status (IOINTSTATUS) */ -#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ - /* Bit 1: Reserved */ -#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ - /* Bits 3-31: Reserved */ - -/* GPIO Interrupt Status for Rising edge (INTSTATR) - * GPIO Interrupt Status for Falling edge (INTSTATF) - * GPIO Interrupt Clear (INTCLR) - * GPIO Interrupt Enable for Rising edge (INTENR) - * GPIO Interrupt Enable for Falling edge (INTENF) +/* Encoding: FFFx MMOV PPPN NNNN + * + * Pin Function: FFF + * Pin Mode bits: MM + * Open drain: O (output pins) + * Initial value: V (output pins) + * Port number: PPP (0-4) + * Pin number: NNNNN (0-31) + */ + +/* Pin Function bits: FFF + * Only meaningful when the GPIO function is GPIO_PIN */ -#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ +#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */ +# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */ +# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */ +# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */ +# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */ +# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */ + +#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) + +#define GPIO_INOUT_MASK GPIO_OUTPUT +#define GPIO_FE_MASK GPIO_INTFE +#define GPIO_RE_MASK GPIO_INTRE + +#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT) +#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT) +#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) +#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) +#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) +#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) +#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) +#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) +#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) + +/* Pin Mode: MM */ + +#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */ +#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) +# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ +# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ +# define GPIO_FLOAT (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDN (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */ + +/* Open drain: O */ + +#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */ + +/* Initial value: V */ + +#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ +#define GPIO_VALUE_ONE GPIO_VALUE +#define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-4) */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) + +#define GPIO_NPORTS 5 + +/* Pin number: NNNNN (0-31) */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /************************************************************************************ * Public Types @@ -189,8 +173,40 @@ * Public Data ************************************************************************************/ -/************************************************************************************ +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* These tables have global scope only because they are shared between lpc17_gpio.c, + * lpc17_gpioint.c, and lpc17_gpiodbg.c + */ + +#ifdef CONFIG_GPIO_IRQ +EXTERN uint64_t g_intedge0; +EXTERN uint64_t g_intedge2; +#endif + +EXTERN const uint32_t g_fiobase[GPIO_NPORTS]; +EXTERN const uint32_t g_intbase[GPIO_NPORTS]; +EXTERN const uint32_t g_lopinsel[GPIO_NPORTS]; +EXTERN const uint32_t g_hipinsel[GPIO_NPORTS]; +EXTERN const uint32_t g_lopinmode[GPIO_NPORTS]; +EXTERN const uint32_t g_hipinmode[GPIO_NPORTS]; +EXTERN const uint32_t g_odmode[GPIO_NPORTS]; + +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c index dc4dac33a..9b16ce697 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpiodbg.c @@ -47,7 +47,7 @@ #include "up_arch.h" #include "chip.h" #include "lpc17_gpio.h" -#include "lpc17_internal.h" + /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c index 66988b0b9..7f18a33b4 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpioint.c @@ -50,8 +50,7 @@ #include "up_arch.h" #include "chip.h" #include "lpc17_gpio.h" -#include "lpc17_pinconn.h" -#include "lpc17_internal.h" + #ifdef CONFIG_GPIO_IRQ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c index 935dbfa0c..866a668ab 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -61,15 +62,13 @@ #include #include -#include "wdog.h" -#include "chip.h" #include "up_arch.h" #include "up_internal.h" #include "os_internal.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" +#include "chip.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_i2c.h" #if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h index 10e1fbeac..5d229f452 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_i2c.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,158 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_i2c.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ -#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ -#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ -#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ -#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ -#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ -#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ -#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ -#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ -#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ -#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ -#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ -#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ -#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ -#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ -#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* I2C Control Set Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ - /* Bits 7-31: Reserved */ -/* I2C Control Clear Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ -#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ - /* Bit 4: Reserved */ -#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ -#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ - /* Bits 7-31: Reserved */ -/* I2C Status Register - * - * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January - * 2010, NXP for definitions of status codes. - */ - -#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status - * Bits 0-1 always zero */ - /* Bits 8-31: Reserved */ -/* I2C Data Register */ - -#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ - /* Bits 8-31: Reserved */ -/* Monitor mode control register */ - -#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ -#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ -#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ - /* Bits 3-31: Reserved */ -/* Data buffer register */ - -#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ - /* Bits 8-31: Reserved */ -/* I2C Slave address registers: - * - * I2C Slave Address Register 0 - * I2C Slave Address Register 1 - * I2C Slave Address Register 2 - * I2C Slave Address Register 3 - */ - -#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ -#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ -#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Slave address mask registers: - * - * I2C Slave address mask register 0 - * I2C Slave address mask register 1 - * I2C Slave address mask register 2 - * I2C Slave address mask register 3 - */ - /* Bit 0: Reserved */ -#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ -#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* SCH Duty Cycle Register High Half Word */ - -#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ - /* Bits 16-31: Reserved */ -/* SCL Duty Cycle Register Low Half Word */ - -#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ - /* Bits 16-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h index 638d40178..9b5e390d0 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2s.h @@ -1,190 +1,190 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_i2s - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */ -#define LPC17_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */ -#define LPC17_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */ -#define LPC17_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */ -#define LPC17_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */ -#define LPC17_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */ -#define LPC17_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */ -#define LPC17_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */ -#define LPC17_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */ -#define LPC17_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */ -#define LPC17_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */ -#define LPC17_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */ -#define LPC17_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */ -#define LPC17_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */ - -/* Register addresses ***************************************************************/ - -#define LPC17_I2S_DAO (LPC17_I2S_BASE+LPC17_I2S_DAO_OFFSET) -#define LPC17_I2S_DAI (LPC17_I2S_BASE+LPC17_I2S_DAI_OFFSET) -#define LPC17_I2S_TXFIFO (LPC17_I2S_BASE+LPC17_I2S_TXFIFO_OFFSET) -#define LPC17_I2S_RXFIFO (LPC17_I2S_BASE+LPC17_I2S_RXFIFO_OFFSET) -#define LPC17_I2S_STATE (LPC17_I2S_BASE+LPC17_I2S_STATE_OFFSET) -#define LPC17_I2S_DMA1 (LPC17_I2S_BASE+LPC17_I2S_DMA1_OFFSET) -#define LPC17_I2S_DMA2 (LPC17_I2S_BASE+LPC17_I2S_DMA2_OFFSET) -#define LPC17_I2S_IRQ (LPC17_I2S_BASE+LPC17_I2S_IRQ_OFFSET) -#define LPC17_I2S_TXRATE (LPC17_I2S_BASE+LPC17_I2S_TXRATE_OFFSET) -#define LPC17_I2S_RXRATE (LPC17_I2S_BASE+LPC17_I2S_RXRATE_OFFSET) -#define LPC17_I2S_TXBITRATE (LPC17_I2S_BASE+LPC17_I2S_TXBITRATE_OFFSET) -#define LPC17_I2S_RXBITRATE (LPC17_I2S_BASE+LPC17_I2S_RXBITRATE_OFFSET) -#define LPC17_I2S_TXMODE (LPC17_I2S_BASE+LPC17_I2S_TXMODE_OFFSET) -#define LPC17_I2S_RXMODE (LPC17_I2S_BASE+LPC17_I2S_RXMODE_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Digital Audio Output Register */ - -#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ -#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) -# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) -#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ -#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ -#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ -#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */ -#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ -#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT) -#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */ - /* Bits 16-31: Reserved */ -/* Digital Audio Input Register */ - -#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ -#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) -# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) -#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ -#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ -#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ -#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */ -#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ -#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT) - /* Bits 15-31: Reserved */ -/* Transmit FIFO: 8 × 32-bit transmit FIFO */ -/* Receive FIFO: 8 × 32-bit receive FIFO */ - -/* Status Feedback Register */ - -#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */ -#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */ -#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */ - /* Bits 3-7: Reserved */ -#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */ -#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */ -#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT) - /* Bits 20-31: Reserved */ -/* DMA Configuration Register 1 and 2 */ - -#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ -#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ - /* Bits 2-7: Reserved */ -#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ -#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */ -#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT) - /* Bits 20-31: Reserved */ -/* Interrupt Request Control Register */ - -#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ -#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ - /* Bits 2-7: Reserved */ -#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ -#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) - /* Bits 12-15: Reserved */ -#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */ -#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT) - /* Bits 20-31: Reserved */ -/* Transmit and Receive MCLK divider */ - -#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */ -#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT) -#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */ -#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT) - /* Bits 16-31: Reserved */ - -/* Transmit and received bit rate divider */ - -#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */ -#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT) - /* Bits 6-31: Reserved */ -/* Transmit and Receive mode control */ - -#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */ -#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT) -# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */ -# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */ -# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */ -#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */ -#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_i2s + * + * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_I2S_DAO_OFFSET 0x0000 /* Digital Audio Output Register */ +#define LPC17_I2S_DAI_OFFSET 0x0004 /* Digital Audio Input Register */ +#define LPC17_I2S_TXFIFO_OFFSET 0x0008 /* Transmit FIFO */ +#define LPC17_I2S_RXFIFO_OFFSET 0x000c /* Receive FIFO */ +#define LPC17_I2S_STATE_OFFSET 0x0010 /* Status Feedback Register */ +#define LPC17_I2S_DMA1_OFFSET 0x0014 /* DMA Configuration Register 1 */ +#define LPC17_I2S_DMA2_OFFSET 0x0018 /* DMA Configuration Register 2 */ +#define LPC17_I2S_IRQ_OFFSET 0x001c /* Interrupt Request Control Register */ +#define LPC17_I2S_TXRATE_OFFSET 0x0020 /* Transmit MCLK divider */ +#define LPC17_I2S_RXRATE_OFFSET 0x0024 /* Receive MCLK divider */ +#define LPC17_I2S_TXBITRATE_OFFSET 0x0028 /* Transmit bit rate divider */ +#define LPC17_I2S_RXBITRATE_OFFSET 0x002c /* Receive bit rate divider */ +#define LPC17_I2S_TXMODE_OFFSET 0x0030 /* Transmit mode control */ +#define LPC17_I2S_RXMODE_OFFSET 0x0034 /* Receive mode control */ + +/* Register addresses ***************************************************************/ + +#define LPC17_I2S_DAO (LPC17_I2S_BASE+LPC17_I2S_DAO_OFFSET) +#define LPC17_I2S_DAI (LPC17_I2S_BASE+LPC17_I2S_DAI_OFFSET) +#define LPC17_I2S_TXFIFO (LPC17_I2S_BASE+LPC17_I2S_TXFIFO_OFFSET) +#define LPC17_I2S_RXFIFO (LPC17_I2S_BASE+LPC17_I2S_RXFIFO_OFFSET) +#define LPC17_I2S_STATE (LPC17_I2S_BASE+LPC17_I2S_STATE_OFFSET) +#define LPC17_I2S_DMA1 (LPC17_I2S_BASE+LPC17_I2S_DMA1_OFFSET) +#define LPC17_I2S_DMA2 (LPC17_I2S_BASE+LPC17_I2S_DMA2_OFFSET) +#define LPC17_I2S_IRQ (LPC17_I2S_BASE+LPC17_I2S_IRQ_OFFSET) +#define LPC17_I2S_TXRATE (LPC17_I2S_BASE+LPC17_I2S_TXRATE_OFFSET) +#define LPC17_I2S_RXRATE (LPC17_I2S_BASE+LPC17_I2S_RXRATE_OFFSET) +#define LPC17_I2S_TXBITRATE (LPC17_I2S_BASE+LPC17_I2S_TXBITRATE_OFFSET) +#define LPC17_I2S_RXBITRATE (LPC17_I2S_BASE+LPC17_I2S_RXBITRATE_OFFSET) +#define LPC17_I2S_TXMODE (LPC17_I2S_BASE+LPC17_I2S_TXMODE_OFFSET) +#define LPC17_I2S_RXMODE (LPC17_I2S_BASE+LPC17_I2S_RXMODE_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Digital Audio Output Register */ + +#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT) +# define I2S_DAO_WDWID_32BITS (3 << I2S_DAO_WDWID_SHIFT) +#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT) +#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */ + /* Bits 16-31: Reserved */ +/* Digital Audio Input Register */ + +#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */ +#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT) +# define I2S_DAI_WDWID_32BITS (3 << I2S_DAI_WDWID_SHIFT) +#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */ +#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */ +#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */ +#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */ +#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */ +#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT) + /* Bits 15-31: Reserved */ +/* Transmit FIFO: 8 × 32-bit transmit FIFO */ +/* Receive FIFO: 8 × 32-bit receive FIFO */ + +/* Status Feedback Register */ + +#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */ +#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */ +#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */ + /* Bits 3-7: Reserved */ +#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */ +#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */ +#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT) + /* Bits 20-31: Reserved */ +/* DMA Configuration Register 1 and 2 */ + +#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */ +#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */ + /* Bits 2-7: Reserved */ +#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */ +#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */ +#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Interrupt Request Control Register */ + +#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */ +#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */ + /* Bits 2-7: Reserved */ +#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */ +#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT) + /* Bits 12-15: Reserved */ +#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */ +#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT) + /* Bits 20-31: Reserved */ +/* Transmit and Receive MCLK divider */ + +#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */ +#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT) +#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */ +#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT) + /* Bits 16-31: Reserved */ + +/* Transmit and received bit rate divider */ + +#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */ +#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT) + /* Bits 6-31: Reserved */ +/* Transmit and Receive mode control */ + +#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */ +#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT) +# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */ +# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */ +# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */ +#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */ +#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2S_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h b/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h deleted file mode 100644 index 8b4358196..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_internal.h +++ /dev/null @@ -1,854 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_internal.h - * - * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include -#include -#include - -#if defined(CONFIG_LPC17_SPI) || defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) -# include -#endif - -#include "up_internal.h" -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Configuration ********************************************************************/ - -/* Bit-encoded input to lpc17_configgpio() ******************************************/ - -/* Encoding: FFFx MMOV PPPN NNNN - * - * Pin Function: FFF - * Pin Mode bits: MM - * Open drain: O (output pins) - * Initial value: V (output pins) - * Port number: PPP (0-4) - * Pin number: NNNNN (0-31) - */ - -/* Pin Function bits: FFF - * Only meaningful when the GPIO function is GPIO_PIN - */ - -#define GPIO_FUNC_SHIFT (13) /* Bits 13-15: GPIO mode */ -#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) -# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 000 GPIO input pin */ -# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 001 GPIO interrupt falling edge */ -# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 010 GPIO interrupt rising edge */ -# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 011 GPIO interrupt both edges */ -# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 100 GPIO outpout pin */ -# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 101 Alternate function 1 */ -# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 110 Alternate function 2 */ -# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 111 Alternate function 3 */ - -#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ -#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) - -#define GPIO_INOUT_MASK GPIO_OUTPUT -#define GPIO_FE_MASK GPIO_INTFE -#define GPIO_RE_MASK GPIO_INTRE - -#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT) -#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT) -#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) -#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) -#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) -#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) -#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) -#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) -#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) - -/* Pin Mode: MM */ - -#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */ -#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) -# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ -# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ -# define GPIO_FLOAT (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */ -# define GPIO_PULLDN (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */ - -/* Open drain: O */ - -#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */ - -/* Initial value: V */ - -#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ -#define GPIO_VALUE_ONE GPIO_VALUE -#define GPIO_VALUE_ZERO (0) - -/* Port number: PPP (0-4) */ - -#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ -#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) -# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) -# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) -# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) -# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) -# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) - -#define GPIO_NPORTS 5 - -/* Pin number: NNNNN (0-31) */ - -#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ -#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) -#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) -#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) -#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) -#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) -#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) -#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) -#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) -#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) -#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) -#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) -#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) -#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) -#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) -#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) -#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) -#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) -#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) - -/* GPIO pin definitions *************************************************************/ -/* NOTE that functions have a alternate pins that can be selected. These alternates - * are identified with a numerica suffix like _1, _2, or _3. Your board.h file - * should select the correct alternative for your board by including definitions - * such as: - * - * #define GPIO_UART1_RXD GPIO_UART1_RXD_1 - * - * (without the suffix) - */ - -#define GPIO_CAN1_RD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) -#define GPIO_UART3_TXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) -#define GPIO_I2C1_SDA_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) -#define GPIO_CAN1_TD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_UART3_RXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_I2C1_SCL_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_AD0p7 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) -#define GPIO_AD0p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) -#define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_CAN2_RD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_CAN2_TD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_I2S_RXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) -#define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) -#define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) -#define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) -#define GPIO_SSP0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) -#define GPIO_SPI_SCK (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) -#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) -#define GPIO_SSP0_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) -#define GPIO_SPI_SSEL (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) -#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) -#define GPIO_SSP0_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) -#define GPIO_SPI_MISO (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) -#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) -#define GPIO_SSP0_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) -#define GPIO_SPI_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) -#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) -#define GPIO_I2C1_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) -#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) -#define GPIO_I2C1_SCL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) -#define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) -#define GPIO_CAN1_RD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) -#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) -#define GPIO_CAN1_TD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) -#define GPIO_AD0p0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) -#define GPIO_I2S_RXCLK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) -#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) -#define GPIO_AD0p1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) -#define GPIO_I2S_RXWS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) -#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) -#define GPIO_AD0p2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) -#define GPIO_I2S_RXSDA_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) -#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) -#define GPIO_AD0p3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) -#define GPIO_AOUT (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) -#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) -#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) -#define GPIO_USB_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) -#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) -#define GPIO_USB_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) -#define GPIO_USB_DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN29) -#define GPIO_USB_DM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN30) -#define GPIO_ENET_TXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_ENET_TXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_ENET_TXEN (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN4) -#define GPIO_ENET_CRS (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN8) -#define GPIO_ENET_RXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN9) -#define GPIO_ENET_RXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN10) -#define GPIO_ENET_RXER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN14) -#define GPIO_ENET_REFCLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN15) -#define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN16) -#define GPIO_ENET_MDIO_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) -#define GPIO_USB_UPLED (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) -#define GPIO_PWM1p1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) -#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) -#define GPIO_MCPWM_MCOA0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_USB_PPWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_MCPWM_MCI0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_PWM1p2_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_SSP0_SCK_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_MCPWM_MCABORT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) -#define GPIO_PWM1p3_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) -#define GPIO_SSP0_SSEL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) -#define GPIO_MCPWM_MCOB0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_USB_PWRD (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_MCPWM_MCI1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_PWM1p4_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_SSP0_MISO_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_MCPWM_MCI2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_PWM1p5_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_SSP0_MOSI_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_MCPWM_MCOA1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) -#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) -#define GPIO_MCPWM_MCOB1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_PWM1p6_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) -#define GPIO_USB_OVRCR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) -#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) -#define GPIO_MCPWM_MCOA2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) -#define GPIO_PCAP1p0_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) -#define GPIO_MAT0p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) -#define GPIO_MCPWM_MCOB2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) -#define GPIO_PCAP1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) -#define GPIO_MAT0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) -#define GPIO_USB_VBUS (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN30) -#define GPIO_AD0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) -#define GPIO_SSP1_SCK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) -#define GPIO_AD0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) -#define GPIO_PWM1p1_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) -#define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) -#define GPIO_PWM1p2_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) -#define GPIO_UART1_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) -#define GPIO_PWM1p3_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) -#define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) -#define GPIO_PWM1p4_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) -#define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) -#define GPIO_PWM1p5_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) -#define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) -#define GPIO_PWM1p6_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) -#define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) -#define GPIO_PCAP1p0_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) -#define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) -#define GPIO_CAN2_RD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) -#define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) -#define GPIO_CAN2_TD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_ENET_MDC_2 (GPIO_ALT3 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_USB_CONNECT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) -#define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) -#define GPIO_ENET_MDIO_2 (GPIO_ALT3 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN9) -#define GPIO_EINT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) -#define GPIO_NMI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) -#define GPIO_EINT1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) -#define GPIO_I2S_TXCLK_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) -#define GPIO_PEINT2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) -#define GPIO_I2S_TXWS_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) -#define GPIO_EINT3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) -#define GPIO_I2S_TXSDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) -#define GPIO_MAT0p0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) -#define GPIO_PWM1p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) -#define GPIO_STCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) -#define GPIO_MAT0p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) -#define GPIO_PWM1p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) -#define GPIO_RXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_MAT2p0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_TXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_MAT2p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -typedef FAR void *DMA_HANDLE; -typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); - -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ - -#ifdef CONFIG_DEBUG_DMA -struct lpc17_dmaglobalregs_s -{ - /* Global Registers */ - - uint32_t intst; /* DMA Interrupt Status Register */ - uint32_t inttcst; /* DMA Interrupt Terminal Count Request Status Register */ - uint32_t interrst; /* DMA Interrupt Error Status Register */ - uint32_t rawinttcst; /* DMA Raw Interrupt Terminal Count Status Register */ - uint32_t rawinterrst; /* DMA Raw Error Interrupt Status Register */ - uint32_t enbldchns; /* DMA Enabled Channel Register */ - uint32_t softbreq; /* DMA Software Burst Request Register */ - uint32_t softsreq; /* DMA Software Single Request Register */ - uint32_t softlbreq; /* DMA Software Last Burst Request Register */ - uint32_t softlsreq; /* DMA Software Last Single Request Register */ - uint32_t config; /* DMA Configuration Register */ - uint32_t sync; /* DMA Synchronization Register */ -}; - -struct lpc17_dmachanregs_s -{ - /* Channel Registers */ - - uint32_t srcaddr; /* DMA Channel Source Address Register */ - uint32_t destaddr; /* DMA Channel Destination Address Register */ - uint32_t lli; /* DMA Channel Linked List Item Register */ - uint32_t control; /* DMA Channel Control Register */ - uint32_t config; /* DMA Channel Configuration Register */ -}; - -struct lpc17_dmaregs_s -{ - /* Global Registers */ - - struct lpc17_dmaglobalregs_s gbl; - - /* Channel Registers */ - - struct lpc17_dmachanregs_s ch; -}; -#endif - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/* These tables have global scope only because they are shared between lpc17_gpio.c, - * lpc17_gpioint.c, and lpc17_gpiodbg.c - */ - -#ifdef CONFIG_GPIO_IRQ -EXTERN uint64_t g_intedge0; -EXTERN uint64_t g_intedge2; -#endif - -EXTERN const uint32_t g_fiobase[GPIO_NPORTS]; -EXTERN const uint32_t g_intbase[GPIO_NPORTS]; -EXTERN const uint32_t g_lopinsel[GPIO_NPORTS]; -EXTERN const uint32_t g_hipinsel[GPIO_NPORTS]; -EXTERN const uint32_t g_lopinmode[GPIO_NPORTS]; -EXTERN const uint32_t g_hipinmode[GPIO_NPORTS]; -EXTERN const uint32_t g_odmode[GPIO_NPORTS]; - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc17_clockconfig - * - * Description: - * Called to initialize the LPC17XX. This does whatever setup is needed to put the - * MCU in a usable state. This includes the initialization of clocking using the - * settings in board.h. - * - ************************************************************************************/ - -EXTERN void lpc17_clockconfig(void); - -/************************************************************************************ - * Name: lpc17_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. - * - ************************************************************************************/ - -EXTERN void lpc17_lowsetup(void); - -/************************************************************************************ - * Name: lpc17_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -EXTERN void lpc17_gpioirqinitialize(void); -#else -# define lpc17_gpioirqinitialize() -#endif - -/************************************************************************************ - * Name: lpc17_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ************************************************************************************/ - -EXTERN int lpc17_configgpio(uint16_t cfgset); - -/************************************************************************************ - * Name: lpc17_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ************************************************************************************/ - -EXTERN void lpc17_gpiowrite(uint16_t pinset, bool value); - -/************************************************************************************ - * Name: lpc17_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ************************************************************************************/ - -EXTERN bool lpc17_gpioread(uint16_t pinset); - -/************************************************************************************ - * Name: lpc17_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -EXTERN void lpc17_gpioirqenable(int irq); -#else -# define lpc17_gpioirqenable(irq) -#endif - -/************************************************************************************ - * Name: lpc17_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -EXTERN void lpc17_gpioirqdisable(int irq); -#else -# define lpc17_gpioirqdisable(irq) -#endif - -/************************************************************************************ - * Function: lpc17_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO -EXTERN int lpc17_dumpgpio(uint16_t pinset, const char *msg); -#else -# define lpc17_dumpgpio(p,m) -#endif - -/************************************************************************************ - * Name: lpc17_clrpend - * - * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. Don't know why... but the LPC1766 Ethernet EMAC - * interrupt definitely needs it! - * - ************************************************************************************/ - -EXTERN void lpc17_clrpend(int irq); - -/************************************************************************************ - * Name: lpc17_spi/ssp0/ssp1select, lpc17_spi/ssp0/ssp1status, and - * lpc17_spi/ssp0/ssp1cmddata - * - * Description: - * These external functions must be provided by board-specific logic. They are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods - * including up_spiinitialize()) are provided by common LPC17xx logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select - * pins. - * 2. Provide lpc17_spi/ssp0/ssp1select() and lpc17_spi/ssp0/ssp1status() functions - * in your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * lpc17_spi/ssp0/ssp1cmddata() functions in your board-specific logic. These - * functions will perform cmd/data selection operations using GPIOs in the way - * your board is configured. - * 3. Add a call to up_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ************************************************************************************/ - -#ifdef CONFIG_LPC17_SPI -EXTERN void lpc17_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -EXTERN uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -EXTERN int lpc17_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -#ifdef CONFIG_LPC17_SSP0 -EXTERN void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -EXTERN uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -EXTERN int lpc17_ssp0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -#ifdef CONFIG_LPC17_SSP1 -EXTERN void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -EXTERN uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -EXTERN int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -/**************************************************************************** - * Name: spi_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from ssp0/1select after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_SPI -EXTERN void spi_flush(FAR struct spi_dev_s *dev); -#endif - -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) -EXTERN void ssp_flush(FAR struct spi_dev_s *dev); -#endif - -/**************************************************************************** - * Name: lpc17_spi/ssp0/1register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD drvier when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) must - * must be implemented. These functiosn implements the registercallback - * method of the SPI interface (see include/nuttx/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The funtion to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_LPC17_SPI -EXTERN int lpc17_spiregister(FAR struct spi_dev_s *dev, - spi_mediachange_t callback, void *arg); -#endif - -#ifdef CONFIG_LPC17_SSP0 -EXTERN int lpc17_ssp0register(FAR struct spi_dev_s *dev, - spi_mediachange_t callback, void *arg); -#endif - -#ifdef CONFIG_LPC17_SSP1 -EXTERN int lpc17_ssp1register(FAR struct spi_dev_s *dev, - spi_mediachange_t callback, void *arg); -#endif -#endif - -/**************************************************************************** - * Name: lpc17_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN void lpc17_dmainitilaize(void); -#endif - -/**************************************************************************** - * Name: lpc17_dmachannel - * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and - * gives the caller exclusive access to the DMA channel. - * - * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN DMA_HANDLE lpc17_dmachannel(void); -#endif - -/**************************************************************************** - * Name: lpc17_dmafree - * - * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until lpc17_dmachannel() is called again to re-gain - * a valid handle. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN void lpc17_dmafree(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: lpc17_dmasetup - * - * Description: - * Configure DMA for one transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN int lpc17_dmarxsetup(DMA_HANDLE handle, - uint32_t control, uint32_t config, - uint32_t srcaddr, uint32_t destaddr, - size_t nbytes); -#endif - -/**************************************************************************** - * Name: lpc17_dmastart - * - * Description: - * Start the DMA transfer - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -#endif - -/**************************************************************************** - * Name: lpc17_dmastop - * - * Description: - * Cancel the DMA. After lpc17_dmastop() is called, the DMA channel is - * reset and lpc17_dmasetup() must be called before lpc17_dmastart() can be - * called again - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -EXTERN void lpc17_dmastop(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: lpc17_dmasample - * - * Description: - * Sample DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -#ifdef CONFIG_DEBUG_DMA -EXTERN void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); -#else -# define lpc17_dmasample(handle,regs) -#endif -#endif - -/**************************************************************************** - * Name: lpc17_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_GPDMA -#ifdef CONFIG_DEBUG_DMA -EXTERN void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, - const char *msg); -#else -# define lpc17_dmadump(handle,regs,msg) -#endif -#endif - -/**************************************************************************** - * Name: lpc17_adcinitialize - * - * Description: - * Initialize the adc - * - * Returned Value: - * Valid can device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_ADC -FAR struct adc_dev_s *lpc17_adcinitialize(void); -#endif - -/**************************************************************************** - * Name: lpc17_dacinitialize - * - * Description: - * Initialize the DAC - * - * Returned Value: - * Valid dac device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_LPC17_DAC -EXTERN FAR struct dac_dev_s *lpc17_dacinitialize(void); -#endif - -/**************************************************************************** - * Name: lpc17_caninitialize - * - * Description: - * Initialize the selected can port - * - * Input Parameter: - * Port number (for hardware that has mutiple can interfaces) - * - * Returned Value: - * Valid can device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2)) -struct can_dev_s; -EXTERN FAR struct can_dev_s *lpc17_caninitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_INTERNAL_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index 8af2adafe..f3e93ffc2 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -51,7 +51,9 @@ #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" -#include "lpc17_internal.h" + +#include "lpc17_gpio.h" +#include "lpc17_clrpend.h" /**************************************************************************** * Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c index ba90c1ff6..5c34bda1b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.c @@ -47,9 +47,11 @@ #include "up_internal.h" #include "up_arch.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_uart.h" +#include "chip/lpc17_syscon.h" +#include "chip/lpc17_uart.h" + +#include "lpc17_gpio.h" +#include "lpc17_lowputc.h" #include "lpc17_serial.h" /************************************************************************** diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.h new file mode 100644 index 000000000..b1b226e03 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lowputc.h @@ -0,0 +1,84 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_lowputc.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART done early so that the serial + * console is available for debugging very early in the boot sequence. + * + ************************************************************************************/ + +void lpc17_lowsetup(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_LOWPUTC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h deleted file mode 100644 index 370aa42de..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h +++ /dev/null @@ -1,280 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_mcpwm.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ -#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ -#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ -#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ -#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ -#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ -#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ -#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ -#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ -#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ -#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ -#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ -#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ -#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ -#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ -#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ -#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ -#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ -#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ -#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ -#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ -#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ -#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ -#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ -#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ -#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ -#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ -#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ -#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ -#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ - -/* Register addresses ***************************************************************/ - -#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) -#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) -#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) -#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) -#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) -#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) -#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) -#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) -#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) -#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) -#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) -#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) -#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) -#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) -#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) -#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) -#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) -#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) -#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) -#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) -#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) -#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) -#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) -#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) -#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) -#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) -#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) -#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) -#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) -#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* There are no bit field definitions for the following registers because they support - * 32-bit values: - * - * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), - * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for - * channels 0, 1, 2 (no bit field definitions) - * - * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit - * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field - * definitions) - * - * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match - * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field - * definitions). - * - * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and - * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for - * channels 0, 1, 2 (no bit field definitions) - */ - -/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control - * clear address (CONCLR) common regiser bit definitions. - */ - -#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ -#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ -#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ -#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ -#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ - /* Bits 5-7: Reserved */ -#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ -#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ -#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ -#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ - /* Bits 13-15: Reserved */ -#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ -#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ -#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ -#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ - /* Bits 21-28: Reserved */ -#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ -#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ -#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ - -/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), - * and Event Control clear address (CAPCONCLR) common register bit defintions - */ - -#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ -#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ -#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ -#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ -#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ - /* Bits 24-31: Reserved -/* Dead time register */ - -#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ -#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) -#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ -#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) -#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ -#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) - /* Bits 30-31: reserved */ -/* Commutation Pattern register */ - -#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ -#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ - /* Bits 6-31: reserved */ - -/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), - * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), - * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) - * common bit field definitions - */ - -#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ -#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ -#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ - /* Bit 3: Reserved */ -#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ -#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ -#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ - /* Bit 7: Reserved */ -#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ -#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ -#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ - /* Bits 11-14: Reserved */ -#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ - /* Bits 16-31: Reserved */ - -/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and - * Count Control clear address (CNTCONCLR) common register bit definitions. - */ - -#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ - /* Bits 28-28: Reserved */ -#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ -#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ -#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ - -/* Capture clear address */ - -#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ -#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ -#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h deleted file mode 100644 index ae66b684c..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h +++ /dev/null @@ -1,136 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_memorymap.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ -#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ -#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ -#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ -# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ -# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ -#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ -#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ -# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ -# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ -# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ -#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ -#define LPC17_SCS_BASE 0xe000e000 -#define LPC17_DEBUGMCU_BASE 0xe0042000 - -/* AHB SRAM Bank sizes **************************************************************/ - -#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ -#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ - -/* APB0 Peripherals *****************************************************************/ - -#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ -#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ -#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ -#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ -#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ - /* -0x40017fff: Reserved */ -#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ -#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ -#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ -#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ -#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ -#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ -#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ -#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ -#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ -#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ -#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ -#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ -#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ - /* -0x4005bfff: Reserved */ -#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ - /* -0x4007ffff: Reserved */ - -/* APB1 Peripherals *****************************************************************/ - - /* -0x40087fff: Reserved */ -#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ -#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ -#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ -#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ -#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ -#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ -#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ - /* -0x400a7fff: Reserved */ -#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ - /* -0x400affff: Reserved */ -#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ - /* -0x400b7fff: Reserved */ -#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ -#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ - /* -0x400fbfff: Reserved */ -#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ - -/* AHB Peripherals ******************************************************************/ - -#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ -#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ -#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h index 1e0564a87..c508ddf6a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h @@ -42,7 +42,7 @@ #include #include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h deleted file mode 100644 index c0e0ec916..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h +++ /dev/null @@ -1,635 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_pinconn.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ -#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ -#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ -#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ -#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ -#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ -#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ -#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ -#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ -#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ -#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ -#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ -#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ -#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ -#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ -#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ -#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ -#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ -#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ -#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ -#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ -#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ -#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ -#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) -#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) -#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) -#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) -#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) -#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) -#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) -#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) -#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) -#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) -#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) -#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) -#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) -#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) -#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) -#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) -#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) -#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) -#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) -#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) -#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) -#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) -#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) -#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ - -#define PINCONN_PINSEL_GPIO (0) -#define PINCONN_PINSEL_ALT1 (1) -#define PINCONN_PINSEL_ALT2 (2) -#define PINCONN_PINSEL_ALT3 (3) -#define PINCONN_PINSEL_MASK (3) - -#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) -#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) - -#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ -#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) -#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ -#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) -#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ -#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) -#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ -#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) -#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ -#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) -#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ -#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) -#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ -#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) -#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ -#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) -#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ -#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) -#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ -#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) -#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ -#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) -#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ -#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ -#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) - -/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ - -#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ -#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) -#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ -#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) -#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ -#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) -#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ -#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) -#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ -#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) -#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ -#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) -#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ -#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) -#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ -#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) -#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ -#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) -#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ -#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) -#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ -#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) -#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ -#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) -#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ -#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) -#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) -#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) - /* Bits 30-31: Reserved */ -/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ - -#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) -#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) -#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) -#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) -#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) - -/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ - -#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) -#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) -#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ -#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) -#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ -#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) -#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ -#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) -#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ -#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) -#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ -#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) -#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ -#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) -#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ -#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) -#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ -#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) -#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ -#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) -#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ -#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) -#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ -#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) -#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ -#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) -#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ -#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) -#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ -#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) - -/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ - -#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) -#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) -#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) -#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) -#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) -#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) -#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ -#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) -#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) -#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ -#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) -#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ -#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) -#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ -#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) -#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ -#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) -#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ -#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) -#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ -#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ - -#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-17: Reserved */ -#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ -#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) -#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ -#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ -/* No description of bits -- Does this register exist? */ - -/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ - -#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-23: Reserved */ -#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ -#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) -#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ -#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ - /* Bits 0-2: Reserved */ -#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ - /* Bits 4-31: Reserved */ -/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ - -#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ -#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ -#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ -#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ -#define PINCONN_PINMODE_MASK (3) - -#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) -#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) - -#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ -#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) -#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ -#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) -#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ -#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) -#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ -#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) -#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ -#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) -#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ -#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) -#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ -#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) -#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ -#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) -#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ -#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) -#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ -#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) -#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ -#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) -#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ -#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ -#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) - -/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ - -#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ -#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) -#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ -#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) -#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ -#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) -#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ -#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) -#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ -#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) -#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ -#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) -#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ -#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) -#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ -#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) -#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ -#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) -#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ -#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) -#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ -#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ - -#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ -#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) -#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ -#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ -#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ -#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) -#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ -#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) -#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ -#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ -#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) -#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ -#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) - -/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ - -#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ -#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) -#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ -#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) -#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ -#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) -#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ -#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) -#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ -#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) -#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ -#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) -#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ -#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) -#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ -#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) -#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ -#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) -#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ -#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) -#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ -#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) -#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ -#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) -#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ -#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) -#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ -#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) -#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ -#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) -#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ -#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) - -/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ - -#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ -#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) -#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ -#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) -#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ -#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) -#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ -#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) -#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ -#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) -#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ -#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) -#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ -#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) -#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ -#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) -#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ -#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) -#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ -#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) -#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ -#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) -#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ -#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) -#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ -#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) -#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ -#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Mode select register 5 (PINMODE5: 0x4002c054) - * Pin Mode select register 6 (PINMODE6: 0x4002c058) - * No bit definitions -- do these registers exist? - */ - -#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ - -#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-17: Reserved */ -#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ -#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) -#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ -#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ -/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ - -#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-23: Reserved */ -#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ -#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) -#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ -#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ - -#define PINCONN_ODMODE0_P0(n) (1 << (n)) - -#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ -#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ -#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ -#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ -#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ -#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ -#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ -#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ -#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ -#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ -#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ -#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ - /* Bits 12-14: Reserved */ -#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ -#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ -#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ -#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ -#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ -#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ -#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ -#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ -#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ -#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ -#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ -#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ - /* Bits 27-28: Reserved */ -#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ -#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ - /* Bit 31: Reserved */ -/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ - -#define PINCONN_ODMODE1_P1(n) (1 << (n)) - -#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ -#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ - /* Bits 2-3: Reserved */ -#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ - /* Bits 5-7: Reserved */ -#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ -#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ -#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ - /* Bits 11-13: Reserved */ -#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ -#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ -#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ -#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ -#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ -#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ -#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ -#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ -#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ -#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ -#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ -#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ -#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ -#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ -#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ -#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ -#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ -#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ - -/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ - -#define PINCONN_ODMODE2_P2(n) (1 << (n)) - -#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ -#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ -#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ -#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ -#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ -#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ -#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ -#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ -#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ -#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ -#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ -#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ -#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ -#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ - /* Bits 14-31: Reserved */ -/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ - -#define PINCONN_ODMODE3_P3(n) (1 << (n)) - /* Bits 0-24: Reserved */ -#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ -#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ - /* Bits 17-31: Reserved */ -/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ - -#define PINCONN_ODMODE4_P4(n) (1 << (n)) - /* Bits 0-27: Reserved */ -#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ -#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ - /* Bits 30-31: Reserved */ -/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ - -#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch - * filtering/slew rate control */ -#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch - * filtering/slew rate control */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h index 6555ce616..d16c61210 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h @@ -43,7 +43,7 @@ #include #include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h index d1637f943..e2515b102 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_qei.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,140 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_qei.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ -#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ -#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ -#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ -#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ -#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ -#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ -#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ -#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ -#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ -#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ -#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ -#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ -#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ -#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ - -/* Interrupt registers */ - -#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ -#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ -#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ -#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ -#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ -#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ - -/* Register addresses ***************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) -#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) -#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) -#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) -#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) -#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) -#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) -#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) -#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) -#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) -#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) -#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) -#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) -#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) -#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) - -/* Interrupt registers */ - -#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) -#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) -#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) -#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) -#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) -#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) - -/* Register bit definitions *********************************************************/ -/* The following registers hold 32-bit integer values and have no bit fields defined - * in this section: - * - * Position register (POS) - * Maximum position register (MAXPOS) - * Position compare register 0 (CMPOS0) - * Position compare register 1 (CMPOS) - * Position compare register 2 (CMPOS2) - * Index count register (INXCNT) - * Index compare register (INXCMP) - * Velocity timer reload register (LOAD) - * Velocity timer register (TIME) - * Velocity counter register (VEL) - * Velocity capture register (CAP) - * Velocity compare register (VELCOMP) - * Digital filter register (FILTER) - */ - -/* Control registers */ -/* Control register */ - -#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ -#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ -#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ -#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ - /* Bits 4-31: reserved */ -/* Encoder status register */ - -#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ - /* Bits 1-31: reserved */ -/* Configuration register */ - -#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ -#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ -#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ -#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ - /* Bits 4-31: reserved */ -/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ - -/* Interrupt registers */ -/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), - * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt - * status clear register (CLR), and Interrupt status set register (SET) common - * bit definitions. - */ - -#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ -#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ -#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ -#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ -#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ -#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ -#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ -#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ -#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ -#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ -#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ -#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ -#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ - /* Bits 13-31: reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h index 2da0164bd..4c0949a46 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_rit.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,42 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_rit.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ -#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ -#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ -#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ - -/* Register addresses ***************************************************************/ - -#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) -#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) -#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) -#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Compare register (Bits 0-31: value compared to the counter) */ - -/* Mask register (Bits 0-31: 32-bit mask value) */ - -/* Control register */ - -#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ -#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ -#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ -#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ - /* Bits 4-31: Reserved */ -/* 32-bit counter (Bits 0-31: 32-bit up counter) */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h index 195e403c1..9011cd84a 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rtc.h @@ -1,270 +1,62 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_rtc.h - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* Miscellaneous registers */ - -#define LPC17_RTC_ILR_OFFSET 0x0000 /* Interrupt Location Register */ -#define LPC17_RTC_CCR_OFFSET 0x0008 /* Clock Control Register */ -#define LPC17_RTC_CIIR_OFFSET 0x000c /* Counter Increment Interrupt Register */ -#define LPC17_RTC_AMR_OFFSET 0x0010 /* Alarm Mask Register */ -#define LPC17_RTC_AUXEN_OFFSET 0x0058 /* RTC Auxiliary Enable register */ -#define LPC17_RTC_AUX_OFFSET 0x005c /* RTC Auxiliary control register */ - -/* Consolidated time registers */ - -#define LPC17_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */ -#define LPC17_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */ -#define LPC17_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */ - -/* Time counter registers */ - -#define LPC17_RTC_SEC_OFFSET 0x0020 /* Seconds Counter */ -#define LPC17_RTC_MIN_OFFSET 0x0024 /* Minutes Register */ -#define LPC17_RTC_HOUR_OFFSET 0x0028 /* Hours Register */ -#define LPC17_RTC_DOM_OFFSET 0x002c /* Day of Month Register */ -#define LPC17_RTC_DOW_OFFSET 0x0030 /* Day of Week Register */ -#define LPC17_RTC_DOY_OFFSET 0x0034 /* Day of Year Register */ -#define LPC17_RTC_MONTH_OFFSET 0x0038 /* Months Register */ -#define LPC17_RTC_YEAR_OFFSET 0x003c /* Years Register */ -#define LPC17_RTC_CALIB_OFFSET 0x0040 /* Calibration Value Register */ - -/* General purpose registers */ - -#define LPC17_RTC_GPREG0_OFFSET 0x0044 /* General Purpose Register 0 */ -#define LPC17_RTC_GPREG1_OFFSET 0x0048 /* General Purpose Register 1 */ -#define LPC17_RTC_GPREG2_OFFSET 0x004c /* General Purpose Register 2 */ -#define LPC17_RTC_GPREG3_OFFSET 0x0050 /* General Purpose Register 3 */ -#define LPC17_RTC_GPREG4_OFFSET 0x0054 /* General Purpose Register 4 */ - -/* Alarm register group */ - -#define LPC17_RTC_ALSEC_OFFSET 0x0060 /* Alarm value for Seconds */ -#define LPC17_RTC_ALMIN_OFFSET 0x0064 /* Alarm value for Minutes */ -#define LPC17_RTC_ALHOUR_OFFSET 0x0068 /* Alarm value for Hours */ -#define LPC17_RTC_ALDOM_OFFSET 0x006c /* Alarm value for Day of Month */ -#define LPC17_RTC_ALDOW_OFFSET 0x0070 /* Alarm value for Day of Week */ -#define LPC17_RTC_ALDOY_OFFSET 0x0074 /* Alarm value for Day of Year */ -#define LPC17_RTC_ALMON_OFFSET 0x0078 /* Alarm value for Months */ -#define LPC17_RTC_ALYEAR_OFFSET 0x007c /* Alarm value for Year */ - -/* Register addresses ***************************************************************/ -/* Miscellaneous registers */ - -#define LPC17_RTC_ILR (LPC17_RTC_BASE+LPC17_RTC_ILR_OFFSET) -#define LPC17_RTC_CCR (LPC17_RTC_BASE+LPC17_RTC_CCR_OFFSET) -#define LPC17_RTC_CIIR (LPC17_RTC_BASE+LPC17_RTC_CIIR_OFFSET) -#define LPC17_RTC_AMR (LPC17_RTC_BASE+LPC17_RTC_AMR_OFFSET) -#define LPC17_RTC_AUXEN (LPC17_RTC_BASE+LPC17_RTC_AUXEN_OFFSET) -#define LPC17_RTC_AUX (LPC17_RTC_BASE+LPC17_RTC_AUX_OFFSET) - -/* Consolidated time registers */ - -#define LPC17_RTC_CTIME0 (LPC17_RTC_BASE+LPC17_RTC_CTIME0_OFFSET) -#define LPC17_RTC_CTIME1 (LPC17_RTC_BASE+LPC17_RTC_CTIME1_OFFSET) -#define LPC17_RTC_CTIME2 (LPC17_RTC_BASE+LPC17_RTC_CTIME2_OFFSET) - -/* Time counter registers */ - -#define LPC17_RTC_SEC (LPC17_RTC_BASE+LPC17_RTC_SEC_OFFSET) -#define LPC17_RTC_MIN (LPC17_RTC_BASE+LPC17_RTC_MIN_OFFSET) -#define LPC17_RTC_HOUR (LPC17_RTC_BASE+LPC17_RTC_HOUR_OFFSET) -#define LPC17_RTC_DOM (LPC17_RTC_BASE+LPC17_RTC_DOM_OFFSET) -#define LPC17_RTC_DOW (LPC17_RTC_BASE+LPC17_RTC_DOW_OFFSET) -#define LPC17_RTC_DOY (LPC17_RTC_BASE+LPC17_RTC_DOY_OFFSET) -#define LPC17_RTC_MONTH (LPC17_RTC_BASE+LPC17_RTC_MONTH_OFFSET) -#define LPC17_RTC_YEAR (LPC17_RTC_BASE+LPC17_RTC_YEAR_OFFSET) -#define LPC17_RTC_CALIB (LPC17_RTC_BASE+LPC17_RTC_CALIB_OFFSET) - -/* General purpose registers */ - -#define LPC17_RTC_GPREG0 (LPC17_RTC_BASE+LPC17_RTC_GPREG0_OFFSET) -#define LPC17_RTC_GPREG1 (LPC17_RTC_BASE+LPC17_RTC_GPREG1_OFFSET) -#define LPC17_RTC_GPREG2 (LPC17_RTC_BASE+LPC17_RTC_GPREG2_OFFSET) -#define LPC17_RTC_GPREG3 (LPC17_RTC_BASE+LPC17_RTC_GPREG3_OFFSET) -#define LPC17_RTC_GPREG4 (LPC17_RTC_BASE+LPC17_RTC_GPREG4_OFFSET) - -/* Alarm register group */ - -#define LPC17_RTC_ALSEC (LPC17_RTC_BASE+LPC17_RTC_ALSEC_OFFSET) -#define LPC17_RTC_ALMIN (LPC17_RTC_BASE+LPC17_RTC_ALMIN_OFFSET) -#define LPC17_RTC_ALHOUR (LPC17_RTC_BASE+LPC17_RTC_ALHOUR_OFFSET) -#define LPC17_RTC_ALDOM (LPC17_RTC_BASE+LPC17_RTC_ALDOM_OFFSET) -#define LPC17_RTC_ALDOW (LPC17_RTC_BASE+LPC17_RTC_ALDOW_OFFSET) -#define LPC17_RTC_ALDOY (LPC17_RTC_BASE+LPC17_RTC_ALDOY_OFFSET) -#define LPC17_RTC_ALMON (LPC17_RTC_BASE+LPC17_RTC_ALMON_OFFSET) -#define LPC17_RTC_ALYEAR (LPC17_RTC_BASE+LPC17_RTC_ALYEAR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* The following registers hold 32-bit values and have no bit fields to be defined: - * - * General Purpose Register 0 - * General Purpose Register 1 - * General Purpose Register 2 - * General Purpose Register 3 - * General Purpose Register 4 - */ - -/* Miscellaneous registers */ -/* Interrupt Location Register */ - -#define RTC_ILR_RTCCIF (1 << 0) /* Bit 0: Counter Increment Interrupt */ -#define RTC_ILR_RTCALF (1 << 1) /* Bit 1: Alarm interrupt */ - /* Bits 2-31: Reserved */ -/* Clock Control Register */ - -#define RTC_CCR_CLKEN (1 << 0) /* Bit 0: Clock Enable */ -#define RTC_CCR_CTCRST (1 << 1) /* Bit 1: CTC Reset */ - /* Bits 2-3: Internal test mode controls */ -#define RTC_CCR_CCALEN (1 << 4) /* Bit 4: Calibration counter enable */ - /* Bits 5-31: Reserved */ -/* Counter Increment Interrupt Register */ - -#define RTC_CIIR_IMSEC (1 << 0) /* Bit 0: Second interrupt */ -#define RTC_CIIR_IMMIN (1 << 1) /* Bit 1: Minute interrupt */ -#define RTC_CIIR_IMHOUR (1 << 2) /* Bit 2: Hour interrupt */ -#define RTC_CIIR_IMDOM (1 << 3) /* Bit 3: Day of Month value interrupt */ -#define RTC_CIIR_IMDOW (1 << 4) /* Bit 4: Day of Week value interrupt */ -#define RTC_CIIR_IMDOY (1 << 5) /* Bit 5: Day of Year interrupt */ -#define RTC_CIIR_IMMON (1 << 6) /* Bit 6: Month interrupt */ -#define RTC_CIIR_IMYEAR (1 << 7) /* Bit 7: Yearinterrupt */ - /* Bits 8-31: Reserved */ -/* Alarm Mask Register */ - -#define RTC_AMR_SEC (1 << 0) /* Bit 0: Second not compared for alarm */ -#define RTC_AMR_MIN (1 << 1) /* Bit 1: Minutes not compared for alarm */ -#define RTC_AMR_HOUR (1 << 2) /* Bit 2: Hour not compared for alarm */ -#define RTC_AMR_DOM (1 << 3) /* Bit 3: Day of Monthnot compared for alarm */ -#define RTC_AMR_DOW (1 << 4) /* Bit 4: Day of Week not compared for alarm */ -#define RTC_AMR_DOY (1 << 5) /* Bit 5: Day of Year not compared for alarm */ -#define RTC_AMR_MON (1 << 6) /* Bit 6: Month not compared for alarm */ -#define RTC_AMR_YEAR (1 << 7) /* Bit 7: Year not compared for alarm */ - /* Bits 8-31: Reserved */ -/* RTC Auxiliary Enable register */ - /* Bits 0-3: Reserved */ -#define RTC_AUXEN_RTCOSCF (1 << 4) /* Bit 4: RTC Oscillator Fail detect flag */ - /* Bits 5-31: Reserved */ -/* RTC Auxiliary control register */ - /* Bits 0-3: Reserved */ -#define RTC_AUX_OSCFEN (1 << 4) /* Bit 4: Oscillator Fail Detect interrupt enable */ - /* Bits 5-31: Reserved */ -/* Consolidated time registers */ -/* Consolidated Time Register 0 */ - -#define RTC_CTIME0_SEC_SHIFT (0) /* Bits 0-5: Seconds */ -#define RTC_CTIME0_SEC_MASK (63 << RTC_CTIME0_SEC_SHIFT) - /* Bits 6-7: Reserved */ -#define RTC_CTIME0_MIN_SHIFT (8) /* Bits 8-13: Minutes */ -#define RTC_CTIME0_MIN_MASK (63 << RTC_CTIME0_MIN_SHIFT) - /* Bits 14-15: Reserved */ -#define RTC_CTIME0_HOURS_SHIFT (16) /* Bits 16-20: Hours */ -#define RTC_CTIME0_HOURS_MASK (31 << RTC_CTIME0_HOURS_SHIFT) - /* Bits 21-23: Reserved */ -#define RTC_CTIME0_DOW_SHIFT (24) /* Bits 24-26: Day of Week */ -#define RTC_CTIME0_DOW_MASK (7 << RTC_CTIME0_DOW_SHIFT) - /* Bits 27-31: Reserved */ -/* Consolidated Time Register 1 */ - -#define RTC_CTIME1_DOM_SHIFT (0) /* Bits 0-4: Day of Month */ -#define RTC_CTIME1_DOM_MASK (31 << RTC_CTIME1_DOM_SHIFT) - /* Bits 5-7: Reserved */ -#define RTC_CTIME1_MON_SHIFT (8) /* Bits 8-11: Month */ -#define RTC_CTIME1_MON_MASK (15 << RTC_CTIME1_MON_SHIFT) - /* Bits 12-15: Reserved */ -#define RTC_CTIME1_YEAR_SHIFT (16) /* Bits 16-27: Year */ -#define RTC_CTIME1_YEAR_MASK (0x0fff << RTC_CTIME1_YEAR_SHIFT) - /* Bits 28-31: Reserved */ -/* Consolidated Time Register 2 */ - -#define RTC_CTIME2_DOY_SHIFT (0) /* Bits 0-11: Day of Year */ -#define RTC_CTIME2_DOY_MASK (0x0fff << RTC_CTIME2_DOY_SHIFT) - /* Bits 12-31: Reserved */ -/* Time counter registers */ - -#define RTC_SEC_MASK (0x003f) -#define RTC_MIN_MASK (0x003f) -#define RTC_HOUR_MASK (0x001f) -#define RTC_DOM_MASK (0x001f) -#define RTC_DOW_MASK (0x0007) -#define RTC_DOY_MASK (0x01ff) -#define RTC_MONTH_MASK (0x000f) -#define RTC_YEAR_MASK (0x0fff) - -/* Calibration Value Register */ - -#define RTC_CALIB_CALVAL_SHIFT (0) /* Bits 0-16: calibration counter counts to this value */ -#define RTC_CALIB_CALVAL_MASK (0xffff << RTC_CALIB_CALVAL_SHIFT) -#define RTC_CALIB_CALDIR (1 << 17) /* Bit 17: Calibration direction */ - /* Bits 18-31: Reserved */ -/* Alarm register group */ - -#define RTC_ALSEC_MASK (0x003f) -#define RTC_ALMIN_MASK (0x003f) -#define RTC_ALHOUR_MASK (0x001f) -#define RTC_ALDOM_MASK (0x001f) -#define RTC_ALDOW_MASK (0x0007) -#define RTC_ALDOY_MASK (0x01ff) -#define RTC_ALMON_MASK (0x000f) -#define RTC_ALYEAR_MASK (0x0fff) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_rtc.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc17_rtc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RTC_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c index 5ea6348e0..c94f2ff60 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.c @@ -58,13 +58,13 @@ #include #include -#include "chip.h" #include "up_arch.h" #include "os_internal.h" #include "up_internal.h" -#include "lpc17_internal.h" -#include "lpc17_uart.h" +#include "chip.h" +#include "chip/lpc17_uart.h" +#include "lpc17_gpio.h" #include "lpc17_serial.h" /**************************************************************************** diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h index 27d7da9d1..95e8155de 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h @@ -43,8 +43,10 @@ #include #include -#include "lpc17_uart.h" -#include "lpc17_syscon.h" +#include "chip/lpc17_uart.h" +#include "chip/lpc17_syscon.h" + +#include "lpc17_gpio.h" /************************************************************************************ * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c index a7bb15931..05e791434 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c @@ -54,9 +54,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_spi.h" #ifdef CONFIG_LPC17_SPI diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h index 880966eb1..e6898aac7 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_spi.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,90 +42,14 @@ #include -#include "chip.h" -#include "lpc17_memorymap.h" +#include + +#include "chip/lpc17_spi.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ -#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ -#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ -#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ -#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ -#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ -#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) -#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) -#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) -#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) -#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) -#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) -#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Control Register */ - /* Bits 0-1: Reserved */ -#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ -#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ -#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ -#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ -#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ -#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ -#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ -#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) -# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ -# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ -# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ -# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ -# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ -# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ -# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ -# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ -# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ - /* Bits 12-31: Reserved */ -/* SPI Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Data Register */ - -#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ -#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ - /* Bits 8-31: Reserved */ -/* SPI Clock Counter Register */ - -#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ - /* Bits 8-31: Reserved */ -/* SPI Test Control Register */ - /* Bit 0: Reserved */ -#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ -#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) - /* Bits 8-31: Reserved */ -/* SPI Test Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Interrupt Register */ - -#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ - /* Bits 1-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ @@ -134,8 +58,97 @@ * Public Data ************************************************************************************/ +#ifdef CONFIG_LPC17_SPI + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + /************************************************************************************ * Public Functions ************************************************************************************/ +/************************************************************************************ + * Name: lpc17_spiselect, lpc17_status, and lpc17_spicmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods + * including up_spiinitialize()) are provided by common LPC17xx logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in lpc17_boardinitialize() to configure SPI chip select pins. + * 2. Provide lpc17_spiselect() and lpc17_spistatus() functions in your board- + * specific logic. These functions will perform chip selection and status + * operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * lpc17_spicmddata() functions in your board-specific logic. This function + * will perform cmd/data selection operations using GPIOs in the way your + * board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SPI driver to the SPI MMC/SD driver). + * + ************************************************************************************/ + +void lpc17_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc17_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc17_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif + +/**************************************************************************** + * Name: spi_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spiselect after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void spi_flush(FAR struct spi_dev_s *dev); + +/**************************************************************************** + * Name: lpc17_spiregister + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD drvier when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function must + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +nt lpc17_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC17_SPI */ #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index db6fbe1f8..96b66d7a1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -54,9 +54,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_ssp.h" #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h index 52b88da68..edc6846ba 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h @@ -1,174 +1,173 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_ssp.h - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* 8 frame FIFOs for both transmit and receive */ - -#define LPC17_SSP_FIFOSZ 8 - -/* Register offsets *****************************************************************/ - -#define LPC17_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ -#define LPC17_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ -#define LPC17_SSP_DR_OFFSET 0x0008 /* Data Register */ -#define LPC17_SSP_SR_OFFSET 0x000c /* Status Register */ -#define LPC17_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ -#define LPC17_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set and Clear Register */ -#define LPC17_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ -#define LPC17_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ -#define LPC17_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ -#define LPC17_SSP_DMACR_OFFSET 0x0024 /* DMA Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_SSP0_CR0 (LPC17_SSP0_BASE+LPC17_SSP_CR0_OFFSET) -#define LPC17_SSP0_CR1 (LPC17_SSP0_BASE+LPC17_SSP_CR1_OFFSET) -#define LPC17_SSP0_DR (LPC17_SSP0_BASE+LPC17_SSP_DR_OFFSET) -#define LPC17_SSP0_SR (LPC17_SSP0_BASE+LPC17_SSP_SR_OFFSET) -#define LPC17_SSP0_CPSR (LPC17_SSP0_BASE+LPC17_SSP_CPSR_OFFSET) -#define LPC17_SSP0_IMSC (LPC17_SSP0_BASE+LPC17_SSP_IMSC_OFFSET) -#define LPC17_SSP0_RIS (LPC17_SSP0_BASE+LPC17_SSP_RIS_OFFSET) -#define LPC17_SSP0_MIS (LPC17_SSP0_BASE+LPC17_SSP_MIS_OFFSET) -#define LPC17_SSP0_ICR (LPC17_SSP0_BASE+LPC17_SSP_ICR_OFFSET) -#define LPC17_SSP0_DMACR (LPC17_SSP0_BASE+LPC17_SSP_DMACR_OFFSET) - -#define LPC17_SSP1_CR0 (LPC17_SSP1_BASE+LPC17_SSP_CR0_OFFSET) -#define LPC17_SSP1_CR1 (LPC17_SSP1_BASE+LPC17_SSP_CR1_OFFSET) -#define LPC17_SSP1_DR (LPC17_SSP1_BASE+LPC17_SSP_DR_OFFSET) -#define LPC17_SSP1_SR (LPC17_SSP1_BASE+LPC17_SSP_SR_OFFSET) -#define LPC17_SSP1_CPSR (LPC17_SSP1_BASE+LPC17_SSP_CPSR_OFFSET) -#define LPC17_SSP1_IMSC (LPC17_SSP1_BASE+LPC17_SSP_IMSC_OFFSET) -#define LPC17_SSP1_RIS (LPC17_SSP1_BASE+LPC17_SSP_RIS_OFFSET) -#define LPC17_SSP1_MIS (LPC17_SSP1_BASE+LPC17_SSP_MIS_OFFSET) -#define LPC17_SSP1_ICR (LPC17_SSP1_BASE+LPC17_SSP_ICR_OFFSET) -#define LPC17_SSP1_DMACR (LPC17_SSP1_BASE+LPC17_SSP_DMACR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Control Register 0 */ - -#define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */ -#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT) -# define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT) -#define SSP_CR0_FRF_SHIFT (4) /* Bits 4-5: FRF Frame Format */ -#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) -# define SSP_CR0_FRF_UWIRE (2 << SSP_CR0_FRF_SHIFT) -#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock Out Polarity */ -#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock Out Phase */ -#define SSP_CR0_SCR_SHIFT (8) /* Bits 8-15: Serial Clock Rate */ -#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT) - /* Bits 8-31: Reserved */ -/* Control Register 1 */ - -#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ -#define SSP_CR1_SSE (1 << 1) /* Bit 1: SSP Enable */ -#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ -#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ - /* Bits 4-31: Reserved */ -/* Data Register */ - -#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ - /* Bits 16-31: Reserved */ -/* Status Register */ - -#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ -#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ -#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ -#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ -#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ - /* Bits 5-31: Reserved */ -/* Clock Prescale Register */ - -#define SSP_CPSR_DVSR_MASK (0xff) /* Bits 0-7: clock = SSP_PCLK/DVSR */ - /* Bits 8-31: Reserved */ -/* Common format for interrupt control registers: - * - * Interrupt Mask Set and Clear Register (IMSC) - * Raw Interrupt Status Register (RIS) - * Masked Interrupt Status Register (MIS) - * Interrupt Clear Register (ICR) - */ - -#define SSP_INT_ROR (1 << 0) /* Bit 0: RX FIFO overrun */ -#define SSP_INT_RT (1 << 1) /* Bit 1: RX FIFO timeout */ -#define SSP_INT_RX (1 << 2) /* Bit 2: RX FIFO at least half full (not ICR) */ -#define SSP_INT_TX (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */ - /* Bits 4-31: Reserved */ -/* DMA Control Register */ - -#define SSP_DMACR_RXDMAE (1 << 0) /* Bit 0: Receive DMA Enable */ -#define SSP_DMACR_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_ssp.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip/lpc17_ssp.h" + +#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_ssp0/ssp1select, lpc17_ssp0/ssp1status, and lpc17_ssp0/ssp1cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods + * including up_spiinitialize()) are provided by common LPC17xx logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in lpc17_boardinitialize() to configure SSP chip select pins. + * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * lpc17_ssp0/ssp1cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SSP driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SSP driver to the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_SSP0 +void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc17_ssp0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_LPC17_SSP1 +void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc17_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from ssp0/1select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) +void ssp_flush(FAR struct spi_dev_s *dev); +#endif + +/**************************************************************************** + * Name: lpc17_ssp0/1register + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD drvier when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) must + * must be implemented. These functiosn implements the registercallback + * method of the SPI interface (see include/nuttx/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +#ifdef CONFIG_LPC17_SSP0 +int lpc17_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif + +#ifdef CONFIG_LPC17_SSP1 +int lpc17_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SSP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_start.c b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c index abbe6e213..45e5b4551 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_start.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_start.c @@ -50,7 +50,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_clockconfig.h" +#include "lpc17_lowputc.h" /**************************************************************************** * Private Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h deleted file mode 100644 index 3b9c32526..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h +++ /dev/null @@ -1,494 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_syscon.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SYSCON_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SYSCON_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ -#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ -#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ -#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ - -#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ -#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ -#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ -#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ -#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ -#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ - -#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ -#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ -#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ - -/* Register addresses ***************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) -#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) -#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) -#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) - -#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) -#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) -#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) -#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) -#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) -#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) - -#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) -#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET) -#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET) - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Flash accelerator module */ - /* Bits 0-11: Reserved */ -#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ -#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) -# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock - * (Up to 120 Mhz for LPC1759/69 only */ -# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ - /* Bits 16-31: Reserved */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: - * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. - * 1:User mode. The on-chip Flash memory is mapped to address 0 */ - /* Bits 1-31: Reserved */ - -/* Clocking and power control -- Clock source selection */ - -#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ -#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) -# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ -# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ -# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ - /* Bits 2-31: Reserved */ - -/* Clocking and power control - Phase locked loops */ -/* PLL0/1 Control register */ - -#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ -#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ - /* Bits 2-31: Reserved */ -/* PLL0 Configuration register */ - -#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ -#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ -#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) - /* Bits 24-31: Reserved */ -/* PLL1 Configuration register */ - -#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ -#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) -#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ -#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) - /* Bits 7-31: Reserved */ -/* PLL0 Status register */ - -#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ -#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ -#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) -#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ -#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ -#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ - /* Bits 27-31: Reserved */ -/* PLL1 Status register */ - -#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ -#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) -#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ -#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) - /* Bit 7: Reserved */ -#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ -#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ -#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ - /* Bits 11-31: Reserved */ -/* PLL0/1 Feed register */ - -#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ -#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) - /* Bits 8-31: Reserved */ -/* Clocking and power control -- Clock dividers */ -/* CPU Clock Configuration register */ - -#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ -#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) -# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ - /* Bits 8-31: Reserved */ -/* USB Clock Configuration register */ - -#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ -#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) -# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ -# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ -# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ - /* Bits 8-31: Reserved */ -/* Peripheral Clock Selection registers 0 and 1 */ - -#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ -#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ -#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ -#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_MASK (3) - -#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ -#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) -#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ -#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) -#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ -#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) -#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ -#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) -#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ -#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) - /* Bits 10-11: Reserved */ -#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ -#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) -#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ -#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) -#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ -#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) - /* Bits 18-19: Reserved */ -#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ -#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) -#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ -#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) -#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ -#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) -#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ -#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) -#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ -#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) -#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ -#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) - -#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ -#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) -#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ -#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) -#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ -#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) -#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ -#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) - /* Bits 8-9: Reserved */ -#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ -#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) -#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ -#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) -#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ -#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) -#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ -#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) -#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ -#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) -#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ -#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) -#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ -#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) - /* Bits 24-25: Reserved */ -#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ -#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) -#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ -#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) -#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ -#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) - -/* Clocking and power control - Peripheral power control registers */ -/* Power Control Register */ - -#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ -#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ -#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ -#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ -#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ - /* Bits 5-7: Reserved */ -#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ -#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ -#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ -#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ - /* Bits 12-31: Reserved */ -/* Power Control for Peripherals Register */ - - /* Bit 0: Reserved */ -#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ -#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ -#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ -#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ - /* Bit 5: Reserved */ -#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ -#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ -#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ -#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ -#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ - /* Bit 11: Reserved */ -#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ -#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ -#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ -#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ -#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ -#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ -#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ -#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ - /* Bit 20: Reserved */ -#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ -#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ -#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ -#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ -#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ -#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ -#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ - /* Bit 28: Reserved */ -#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ -#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ -#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ - -/* More clocking and power control -- Utility */ - -#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ -#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) -# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ -# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ -# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ -# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ -# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ -#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ -#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) -# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ -#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ -#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ - /* Bits 10-31: Reserved */ -/* System control registers -- External Interrupts */ -/* External Interrupt Flag register */ - -#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ -#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ -#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ -#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ - /* Bits 4-31: Reserved */ -/* External Interrupt Mode register */ - -#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ -#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ -#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ -#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ - /* Bits 4-31: Reserved */ -/* External Interrupt Polarity register */ - -#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ - /* Bits 4-31: Reserved */ -/* System control registers -- Reset */ -/* Reset Source Identification Register */ - -#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ -#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ -#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ -#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ - /* Bits 4-31: Reserved */ -/* System control registers -- Syscon Miscellaneous Registers */ - - /* Bits 0-3: Reserved */ -#define SYSCON_SCS_OSCRANGE (1 << 4) /* Bit 4: Main oscillator range select */ -#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ -#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ - /* Bits 7-31: Reserved */ -/* Device Interrupt Registers */ -/* USB Interrupt Status register */ - -#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ -#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ -#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ -#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ -#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ -#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ -#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ - /* Bit 7: Reserved */ -#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ - /* Bits 9-30: Reserved */ -#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ - -/* DMA Request Select Register */ - -#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ -#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ -#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ -#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ -#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ -#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ -#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ -#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ - /* Bits 8-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SYSCON_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h index 207c6d5cc..d548fada5 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timer.h @@ -1,250 +1,62 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_timer.h - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ -#define LPC17_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ -#define LPC17_TMR_TC_OFFSET 0x0008 /* Timer Counter */ -#define LPC17_TMR_PR_OFFSET 0x000c /* Prescale Register */ -#define LPC17_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ -#define LPC17_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ -#define LPC17_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ -#define LPC17_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ -#define LPC17_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ -#define LPC17_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ -#define LPC17_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ -#define LPC17_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ -#define LPC17_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ -#define LPC17_TMR_EMR_OFFSET 0x003c /* External Match Register */ -#define LPC17_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_TMR0_IR (LPC17_TMR0_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR0_TCR (LPC17_TMR0_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR0_TC (LPC17_TMR0_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR0_PR (LPC17_TMR0_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR0_PC (LPC17_TMR0_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR0_MCR (LPC17_TMR0_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR0_MR0 (LPC17_TMR0_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR0_MR1 (LPC17_TMR0_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR0_MR2 (LPC17_TMR0_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR0_MR3 (LPC17_TMR0_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR0_CCR (LPC17_TMR0_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR0_CR0 (LPC17_TMR0_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR0_CR1 (LPC17_TMR0_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR0_EMR (LPC17_TMR0_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR0_CTCR (LPC17_TMR0_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR1_IR (LPC17_TMR1_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR1_TCR (LPC17_TMR1_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR1_TC (LPC17_TMR1_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR1_PR (LPC17_TMR1_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR1_PC (LPC17_TMR1_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR1_MCR (LPC17_TMR1_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR1_MR0 (LPC17_TMR1_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR1_MR1 (LPC17_TMR1_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR1_MR2 (LPC17_TMR1_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR1_MR3 (LPC17_TMR1_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR1_CCR (LPC17_TMR1_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR1_CR0 (LPC17_TMR1_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR1_CR1 (LPC17_TMR1_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR1_EMR (LPC17_TMR1_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR1_CTCR (LPC17_TMR1_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR2_IR (LPC17_TMR2_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR2_TCR (LPC17_TMR2_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR2_TC (LPC17_TMR2_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR2_PR (LPC17_TMR2_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR2_PC (LPC17_TMR2_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR2_MCR (LPC17_TMR2_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR2_MR0 (LPC17_TMR2_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR2_MR1 (LPC17_TMR2_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR2_MR2 (LPC17_TMR2_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR2_MR3 (LPC17_TMR2_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR2_CCR (LPC17_TMR2_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR2_CR0 (LPC17_TMR2_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR2_CR1 (LPC17_TMR2_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR2_EMR (LPC17_TMR2_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR2_CTCR (LPC17_TMR2_BASE+LPC17_TMR_CTCR_OFFSET) - -#define LPC17_TMR3_IR (LPC17_TMR3_BASE+LPC17_TMR_IR_OFFSET) -#define LPC17_TMR3_TCR (LPC17_TMR3_BASE+LPC17_TMR_TCR_OFFSET) -#define LPC17_TMR3_TC (LPC17_TMR3_BASE+LPC17_TMR_TC_OFFSET) -#define LPC17_TMR3_PR (LPC17_TMR3_BASE+LPC17_TMR_PR_OFFSET) -#define LPC17_TMR3_PC (LPC17_TMR3_BASE+LPC17_TMR_PC_OFFSET) -#define LPC17_TMR3_MCR (LPC17_TMR3_BASE+LPC17_TMR_MCR_OFFSET) -#define LPC17_TMR3_MR0 (LPC17_TMR3_BASE+LPC17_TMR_MR0_OFFSET) -#define LPC17_TMR3_MR1 (LPC17_TMR3_BASE+LPC17_TMR_MR1_OFFSET) -#define LPC17_TMR3_MR2 (LPC17_TMR3_BASE+LPC17_TMR_MR2_OFFSET) -#define LPC17_TMR3_MR3 (LPC17_TMR3_BASE+LPC17_TMR_MR3_OFFSET) -#define LPC17_TMR3_CCR (LPC17_TMR3_BASE+LPC17_TMR_CCR_OFFSET) -#define LPC17_TMR3_CR0 (LPC17_TMR3_BASE+LPC17_TMR_CR0_OFFSET) -#define LPC17_TMR3_CR1 (LPC17_TMR3_BASE+LPC17_TMR_CR1_OFFSET) -#define LPC17_TMR3_EMR (LPC17_TMR3_BASE+LPC17_TMR_EMR_OFFSET) -#define LPC17_TMR3_CTCR (LPC17_TMR3_BASE+LPC17_TMR_CTCR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Registers holding 32-bit numeric values (no bit field definitions): - * - * Timer Counter (TC) - * Prescale Register (PR) - * Prescale Counter (PC) - * Match Register 0 (MR0) - * Match Register 1 (MR1) - * Match Register 2 (MR2) - * Match Register 3 (MR3) - * Capture Register 0 (CR0) - * Capture Register 1 (CR1) - */ - -/* Interrupt Register */ - -#define TMR_IR_MR0 (1 << 0) /* Bit 0: Match channel 0 interrupt */ -#define TMR_IR_MR1 (1 << 1) /* Bit 1: Match channel 1 interrupt */ -#define TMR_IR_MR2 (1 << 2) /* Bit 2: Match channel 2 interrupt */ -#define TMR_IR_MR3 (1 << 3) /* Bit 3: Match channel 3 interrupt */ -#define TMR_IR_CR0 (1 << 4) /* Bit 4: Capture channel 0 interrupt */ -#define TMR_IR_CR1 (1 << 5) /* Bit 5: Capture channel 1 interrupt */ - /* Bits 6-31: Reserved */ -/* Timer Control Register */ - -#define TMR_TCR_EN (1 << 0) /* Bit 0: Counter Enable */ -#define TMR_TCR_RESET (1 << 1) /* Bit 1: Counter Reset */ - /* Bits 2-31: Reserved */ -/* Match Control Register */ - -#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ -#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ -#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ -#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ -#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ -#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ -#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ -#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ -#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ -#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ -#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ -#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ - /* Bits 12-31: Reserved */ -/* Capture Control Register */ - -#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ -#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ -#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ -#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ -#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ -#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ - /* Bits 6-31: Reserved */ -/* External Match Register */ - -#define TMR_EMR_NOTHING (0) /* Do Nothing */ -#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ -#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ -#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ - -#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ -#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ -#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ -#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ -#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ -#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) -# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) -# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) -#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ -#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) -# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) -#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ -#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) -# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) -#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ -#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) -# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) - /* Bits 12-31: Reserved */ -/* Count Control Register */ - -#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ -#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) -# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ -# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ -# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ -# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ -#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ -#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) -# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ -# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_timer.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc17_timer.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c index 918c153a4..ffe975e92 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -52,7 +52,7 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" + /**************************************************************************** * Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h b/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h deleted file mode 100644 index 3664a0cb8..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h +++ /dev/null @@ -1,339 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_uart.h - * - * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_UART_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ -#define LPC17_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ -#define LPC17_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ -#define LPC17_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ -#define LPC17_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ -#define LPC17_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ -#define LPC17_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ -#define LPC17_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ -#define LPC17_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ -#define LPC17_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ -#define LPC17_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ -#define LPC17_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ -#define LPC17_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ -#define LPC17_UART_ICR_OFFSET 0x0024 /* IrDA Control Register (UART0,2,3 only) */ -#define LPC17_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ -#define LPC17_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ -#define LPC17_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ -#define LPC17_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ -#define LPC17_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ -#define LPC17_UART_FIFOLVL_OFFSET 0x0058 /* FIFO Level register (all) */ - -/* Register addresses ***************************************************************/ - -#define LPC17_UART0_RBR (LPC17_UART0_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART0_THR (LPC17_UART0_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART0_DLL (LPC17_UART0_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART0_DLM (LPC17_UART0_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART0_IER (LPC17_UART0_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART0_IIR (LPC17_UART0_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART0_FCR (LPC17_UART0_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART0_LCR (LPC17_UART0_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART0_LSR (LPC17_UART0_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART0_SCR (LPC17_UART0_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART0_ACR (LPC17_UART0_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART0_ICR (LPC17_UART0_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART0_FDR (LPC17_UART0_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART0_TER (LPC17_UART0_BASE+LPC17_UART_TER_OFFSET) -#define LPC17_UART0_FIFOLVL (LPC17_UART0_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART1_RBR (LPC17_UART1_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART1_THR (LPC17_UART1_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART1_DLL (LPC17_UART1_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART1_DLM (LPC17_UART1_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART1_IER (LPC17_UART1_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART1_IIR (LPC17_UART1_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART1_FCR (LPC17_UART1_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART1_LCR (LPC17_UART1_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART1_MCR (LPC17_UART1_BASE+LPC17_UART_MCR_OFFSET) -#define LPC17_UART1_LSR (LPC17_UART1_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART1_MSR (LPC17_UART1_BASE+LPC17_UART_MSR_OFFSET) -#define LPC17_UART1_SCR (LPC17_UART1_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART1_ACR (LPC17_UART1_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART1_FDR (LPC17_UART1_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART1_TER (LPC17_UART1_BASE+LPC17_UART_TER_OFFSET) -#define LPC17_UART1_RS485CTRL (LPC17_UART1_BASE+LPC17_UART_RS485CTRL_OFFSET) -#define LPC17_UART1_ADRMATCH (LPC17_UART1_BASE+LPC17_UART_ADRMATCH_OFFSET) -#define LPC17_UART1_RS485DLY (LPC17_UART1_BASE+LPC17_UART_RS485DLY_OFFSET) -#define LPC17_UART1_FIFOLVL (LPC17_UART1_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART2_RBR (LPC17_UART2_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART2_THR (LPC17_UART2_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART2_DLL (LPC17_UART2_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART2_DLM (LPC17_UART2_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART2_IER (LPC17_UART2_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART2_IIR (LPC17_UART2_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART2_FCR (LPC17_UART2_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART2_LCR (LPC17_UART2_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART2_LSR (LPC17_UART2_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART2_SCR (LPC17_UART2_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART2_ACR (LPC17_UART2_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART2_ICR (LPC17_UART2_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART2_FDR (LPC17_UART2_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART2_TER (LPC17_UART2_BASE+LPC17_UART_TER_OFFSET) -#define LPC17_UART2_FIFOLVL (LPC17_UART2_BASE+LPC17_UART_FIFOLVL_OFFSET) - -#define LPC17_UART3_RBR (LPC17_UART3_BASE+LPC17_UART_RBR_OFFSET) -#define LPC17_UART3_THR (LPC17_UART3_BASE+LPC17_UART_THR_OFFSET) -#define LPC17_UART3_DLL (LPC17_UART3_BASE+LPC17_UART_DLL_OFFSET) -#define LPC17_UART3_DLM (LPC17_UART3_BASE+LPC17_UART_DLM_OFFSET) -#define LPC17_UART3_IER (LPC17_UART3_BASE+LPC17_UART_IER_OFFSET) -#define LPC17_UART3_IIR (LPC17_UART3_BASE+LPC17_UART_IIR_OFFSET) -#define LPC17_UART3_FCR (LPC17_UART3_BASE+LPC17_UART_FCR_OFFSET) -#define LPC17_UART3_LCR (LPC17_UART3_BASE+LPC17_UART_LCR_OFFSET) -#define LPC17_UART3_LSR (LPC17_UART3_BASE+LPC17_UART_LSR_OFFSET) -#define LPC17_UART3_SCR (LPC17_UART3_BASE+LPC17_UART_SCR_OFFSET) -#define LPC17_UART3_ACR (LPC17_UART3_BASE+LPC17_UART_ACR_OFFSET) -#define LPC17_UART3_ICR (LPC17_UART3_BASE+LPC17_UART_ICR_OFFSET) -#define LPC17_UART3_FDR (LPC17_UART3_BASE+LPC17_UART_FDR_OFFSET) -#define LPC17_UART3_TER (LPC17_UART3_BASE+LPC17_UART_TER_OFFSET) -#define LPC17_UART3_FIFOLVL (LPC17_UART3_BASE+LPC17_UART_FIFOLVL_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* RBR (DLAB =0) Receiver Buffer Register (all) */ - -#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ - /* Bits 8-31: Reserved */ - -/* THR (DLAB =0) Transmit Holding Register (all) */ - -#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ - /* Bits 8-31: Reserved */ - -/* DLL (DLAB =1) Divisor Latch LSB (all) */ - -#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ - /* Bits 8-31: Reserved */ - -/* DLM (DLAB =1) Divisor Latch MSB (all) */ - -#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ - /* Bits 8-31: Reserved */ - -/* IER (DLAB =0) Interrupt Enable Register (all) */ - -#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ -#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ -#define UART_IER_RLSIE (1 << 2) /* Bit 2: RX Line Status Interrupt Enable */ -#define UART_IER_MSIE (1 << 3) /* Bit 3: Modem Status Interrupt Enable (UART1 only) */ - /* Bits 4-6: Reserved */ -#define UART_IER_CTSIE (1 << 7) /* Bit 7: CTS transition interrupt (UART1 only) */ -#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ -#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -#define UART_IER_ALLIE (0x038f) - -/* IIR Interrupt ID Register (all) */ - -#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ -#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ -#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) -# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */ -# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ -# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ -# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ -# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ - /* Bits 4-5: Reserved */ -#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ -#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) -#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ -#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ - /* Bits 10-31: Reserved */ -/* FCR FIFO Control Register (all) */ - -#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ -#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ -#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ -#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */ - /* Bits 4-5: Reserved */ -#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ -#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) -# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ -# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ -# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ -# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ - /* Bits 8-31: Reserved */ -/* LCR Line Control Register (all) */ - -#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ -#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) -# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) -#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ -#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ -#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ -#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) -# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ -# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ -# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ -# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ -#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ -#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ - /* Bits 8-31: Reserved */ -/* MCR Modem Control Register (UART1 only) */ - -#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ -#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ - /* Bits 2-3: Reserved */ -#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ - /* Bit 5: Reserved */ -#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ -#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ - /* Bits 8-31: Reserved */ -/* LSR Line Status Register (all) */ - -#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ -#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ -#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ -#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ -#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ -#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ -#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ -#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ - /* Bits 8-31: Reserved */ -/* MSR Modem Status Register (UART1 only) */ - -#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ -#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ -#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ -#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ -#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ -#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ -#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ -#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ - /* Bits 8-31: Reserved */ -/* SCR Scratch Pad Register (all) */ - -#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ - /* Bits 8-31: Reserved */ -/* ACR Auto-baud Control Register (all) */ - -#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ -#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ -#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ - /* Bits 3-7: Reserved */ -#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ -#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ - /* Bits 10-31: Reserved */ -/* ICA IrDA Control Register (UART0,2,3 only) */ - -#define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */ -#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */ -#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */ -#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT) -# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */ -# define UART_ICR_PULSEDIV_4TPCLK (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */ -# define UART_ICR_PULSEDIV_8TPCLK (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */ -# define UART_ICR_PULSEDIV_16TPCLK (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */ -# define UART_ICR_PULSEDIV_32TPCLK (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */ -# define UART_ICR_PULSEDIV_64TPCLK (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */ -# define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */ -# define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 246 x TPCLK */ - /* Bits 6-31: Reserved */ -/* FDR Fractional Divider Register (all) */ - -#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ -#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) -#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) - /* Bits 8-31: Reserved */ -/* TER Transmit Enable Register (all) */ - /* Bits 0-6: Reserved */ -#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 Control (UART1 only) */ - -#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ -#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ -#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ -#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ -#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ -#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ - /* Bits 6-31: Reserved */ -/* RS-485/EIA-485 address match (UART1 only) */ - -#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ - /* Bits 8-31: Reserved */ -/* RS-485/EIA-485 direction control delay (UART1 only) */ - -#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ - /* Bits 8-31: Reserved */ -/* FIFOLVL FIFO Level register (all) */ - -#define UART_FIFOLVL_RX_SHIFT (0) /* Bits 0-3: Current level of the UART RX FIFO */ -#define UART_FIFOLVL_RX_MASK (15 << UART_FIFOLVL_RX_SHIFT) - /* Bits 4-7: Reserved */ -#define UART_FIFOLVL_TX_SHIFT (8) /* Bits 8-11: Current level of the UART TX FIFO */ -#define UART_FIFOLVL_TX_MASK (15 << UART_FIFOLVL_TX_SHIFT) - /* Bits 12-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_UART_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h b/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h deleted file mode 100644 index 8fd599584..000000000 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h +++ /dev/null @@ -1,778 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_usb.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ -#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ -#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ -#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ -#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ -#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ -#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ -#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ -#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ -#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ -#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ -#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ -#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ -#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ -#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ -#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ -#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ -#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ -#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ -#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ -#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ -#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ -#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ -#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ -#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ -#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ -#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ -#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ -#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ -#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ -#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ -#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ -#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ -#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ -#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ -#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ -#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ -#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ -#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ -#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ -#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ -#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ -#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ - -#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ -#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ - -/* Register addresses ***************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* Control and status registers (section 7.1) */ - -#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) -#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) -#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) -#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) -#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) -#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) - -/* Memory pointers (section 7.2) */ - -#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) -#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) -#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) -#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) -#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) -#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) -#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) - -/* Frame counters (section 7.3) */ - -#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) -#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) -#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) -#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) - -/* Root hub ports (section 7.4) */ - -#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) -#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) -#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) -#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) -#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) -#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) -#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) -#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) -#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) -#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) -#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) -#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) -#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) -#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) -#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) -#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) -#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) -#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) -#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) -#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) -#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) -#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) -#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) -#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) -#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) -#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) -#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) -#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) -#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) -#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) -#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) -#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) -#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) -#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) -#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) -#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) -#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) -#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) -#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) -#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) -#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) -#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) -#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) -#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) -#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) -#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) -#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) -#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) -#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) - -#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) -#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) - -/* Register bit definitions *********************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -/* Module ID/Revision ID */ - -#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ -#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) -#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ -#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) -#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ -#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) -# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers: - * - * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt - * Clear - */ - -#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ -#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ -#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ -#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ - /* Bits 4-31: Reserved */ -/* OTG Status and Control */ - -#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ -#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) -# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ -#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ -#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) -# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ -#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ -#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ -#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ - /* Bit 7: Reserved */ -#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ -#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ -#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ - /* Bits 11-15: Reserved */ -#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ -#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) - -/* OTG Timer */ - -#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ -#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) - /* Bits 16-31: Reserved */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ -/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt - * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority - */ - -#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ -#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ -#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ -#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ -#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ -#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ -#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ -#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ -#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ -#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ - /* Bits 10-31: Reserved */ -/* SIE Command registers: - * - * USB Command Code - */ - /* Bits 0-7: Reserved */ -#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ -#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) -#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ -#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) -#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ -#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) - /* Bits 24-31: Reserved */ -/* USB Command Data */ - -#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ -#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) - /* Bits 8-31: Reserved */ -/* USB transfer registers: - * - * USB Receive Data (Bits 0-31: Received data) - */ - -/* USB Receive Packet Length */ - -#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ -#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) -#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ -#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ - /* Bits 12-31: Reserved */ -/* USB Transmit Data (Bits 0-31: Transmit data) */ - -/* USB Transmit Packet Length */ - -#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ -#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) - /* Bits 10-31: Reserved */ -/* USB Control */ - -#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ -#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ -#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ -#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) - /* Bits 6-31: Reserved */ -/* Endpoint interrupt registers: - * - * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt - * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond - * to on RX or TX value for any of 15 logical endpoints). - */ - -#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) -#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) -#define USBDEV_LOGEPRX0 (1 << 0) -#define USBDEV_LOGEPTX0 (1 << 1) -#define USBDEV_LOGEPRX1 (1 << 2) -#define USBDEV_LOGEPTX1 (1 << 3) -#define USBDEV_LOGEPRX2 (1 << 4) -#define USBDEV_LOGEPTX2 (1 << 5) -#define USBDEV_LOGEPRX3 (1 << 6) -#define USBDEV_LOGEPTX3 (1 << 7) -#define USBDEV_LOGEPRX4 (1 << 8) -#define USBDEV_LOGEPTX4 (1 << 9) -#define USBDEV_LOGEPRX5 (1 << 10) -#define USBDEV_LOGEPTX5 (1 << 11) -#define USBDEV_LOGEPRX6 (1 << 12) -#define USBDEV_LOGEPTX6 (1 << 13) -#define USBDEV_LOGEPRX7 (1 << 14) -#define USBDEV_LOGEPTX7 (1 << 15) -#define USBDEV_LOGEPRX8 (1 << 16) -#define USBDEV_LOGEPTX8 (1 << 17) -#define USBDEV_LOGEPRX9 (1 << 18) -#define USBDEV_LOGEPTX9 (1 << 19) -#define USBDEV_LOGEPRX10 (1 << 20) -#define USBDEV_LOGEPTX10 (1 << 21) -#define USBDEV_LOGEPRX11 (1 << 22) -#define USBDEV_LOGEPTX11 (1 << 23) -#define USBDEV_LOGEPRX12 (1 << 24) -#define USBDEV_LOGEPTX12 (1 << 25) -#define USBDEV_LOGEPRX13 (1 << 26) -#define USBDEV_LOGEPTX13 (1 << 27) -#define USBDEV_LOGEPRX14 (1 << 28) -#define USBDEV_LOGEPTX14 (1 << 29) -#define USBDEV_LOGEPRX15 (1 << 30) -#define USBDEV_LOGEPTX15 (1 << 31) - -/* Endpoint realization registers: - * - * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) - */ - -#define USBDEV_PHYEP(n) (1 << (n)) -#define USBDEV_PHYEP0 (1 << 0) -#define USBDEV_PHYEP1 (1 << 1) -#define USBDEV_PHYEP2 (1 << 2) -#define USBDEV_PHYEP3 (1 << 3) -#define USBDEV_PHYEP4 (1 << 4) -#define USBDEV_PHYEP5 (1 << 5) -#define USBDEV_PHYEP6 (1 << 6) -#define USBDEV_PHYEP7 (1 << 7) -#define USBDEV_PHYEP8 (1 << 8) -#define USBDEV_PHYEP9 (1 << 9) -#define USBDEV_PHYEP10 (1 << 10) -#define USBDEV_PHYEP11 (1 << 11) -#define USBDEV_PHYEP12 (1 << 12) -#define USBDEV_PHYEP13 (1 << 13) -#define USBDEV_PHYEP14 (1 << 14) -#define USBDEV_PHYEP15 (1 << 15) -#define USBDEV_PHYEP16 (1 << 16) -#define USBDEV_PHYEP17 (1 << 17) -#define USBDEV_PHYEP18 (1 << 18) -#define USBDEV_PHYEP19 (1 << 19) -#define USBDEV_PHYEP20 (1 << 20) -#define USBDEV_PHYEP21 (1 << 21) -#define USBDEV_PHYEP22 (1 << 22) -#define USBDEV_PHYEP23 (1 << 23) -#define USBDEV_PHYEP24 (1 << 24) -#define USBDEV_PHYEP25 (1 << 25) -#define USBDEV_PHYEP26 (1 << 26) -#define USBDEV_PHYEP27 (1 << 27) -#define USBDEV_PHYEP28 (1 << 28) -#define USBDEV_PHYEP29 (1 << 29) -#define USBDEV_PHYEP30 (1 << 30) -#define USBDEV_PHYEP31 (1 << 31) - -/* USB Endpoint Index */ - -#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ -#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) - /* Bits 5-31: Reserved */ -/* USB MaxPacketSize */ - -#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ -#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) - /* Bits 10-31: Reserved */ -/* DMA registers: - * - * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers - * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions - * above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB UDCA Head */ - /* Bits 0-6: Reserved */ -#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ -#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) - -/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. - * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* - * definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ - -#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ -#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ -#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ - /* Bits 3-31: Reserved */ -/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB - * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB - * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System - * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use - * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* OTG I2C registers ****************************************************************/ - -/* I2C Receive */ - -#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ -#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Transmit */ - -#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ -#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) -#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ -#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ - /* Bits 3-31: Reserved */ -/* I2C Status */ - -#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ -#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ -#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ -#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ -#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ -#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ -#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ -#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ -#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ -#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ -#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ -#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ - /* Bits 12-31: Reserved */ -/* I2C Control */ - -#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ -#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ -#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ -#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ -#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ -#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ -#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ - /* Bits 9-31: Reserved */ -/* I2C Clock High */ - -#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Clock Low */ - -#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) - /* Bits 8-31: Reserved */ -/* Clock control registers ***********************************************************/ - -/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ - -#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ -#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ -#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ -#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ -#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ -#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ - /* Bits 5-31: Reserved */ -/* Alternate naming */ - -#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK -#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK -#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK -#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK -#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK -#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK - -/* Endpoints *************************************************************************/ - -#define LPC17_EP0_OUT 0 -#define LPC17_EP0_IN 1 -#define LPC17_CTRLEP_OUT LPC17_EP0_OUT -#define LPC17_CTRLEP_IN LPC17_EP0_IN -#define LPC17_EP1_OUT 2 -#define LPC17_EP1_IN 3 -#define LPC17_EP2_OUT 4 -#define LPC17_EP2_IN 5 -#define LPC17_EP3_OUT 6 -#define LPC17_EP3_IN 7 -#define LPC17_EP4_OUT 8 -#define LPC17_EP4_IN 9 -#define LPC17_EP5_OUT 10 -#define LPC17_EP5_IN 11 -#define LPC17_EP6_OUT 12 -#define LPC17_EP6_IN 13 -#define LPC17_EP7_OUT 14 -#define LPC17_EP7_IN 15 -#define LPC17_EP8_OUT 16 -#define LPC17_EP8_IN 17 -#define LPC17_EP9_OUT 18 -#define LPC17_EP9_IN 19 -#define LPC17_EP10_OUT 20 -#define LPC17_EP10_IN 21 -#define LPC17_EP11_OUT 22 -#define LPC17_EP11_IN 23 -#define LPC17_EP12_OUT 24 -#define LPC17_EP12_IN 25 -#define LPC17_EP13_OUT 26 -#define LPC17_EP13_IN 27 -#define LPC17_EP14_OUT 28 -#define LPC17_EP14_IN 29 -#define LPC17_EP15_OUT 30 -#define LPC17_EP15_IN 31 -#define LPC17_NUMEPS 32 - -/* Commands *************************************************************************/ - -/* USB Command Code Register */ - -#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ -#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) -#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ -#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) -#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT -#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK - -/* Device Commands */ - -#define CMD_USBDEV_SETADDRESS (0x00d0) -#define CMD_USBDEV_CONFIG (0x00d8) -#define CMD_USBDEV_SETMODE (0x00f3) -#define CMD_USBDEV_READFRAMENO (0x00f5) -#define CMD_USBDEV_READTESTREG (0x00fd) -#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ -#define CMD_USBDEV_GETSTATUS (0x00fe) -#define CMD_USBDEV_GETERRORCODE (0x00ff) -#define CMD_USBDEV_READERRORSTATUS (0x00fb) - -/* Endpoint Commands */ - -#define CMD_USBDEV_EPSELECT (0x0000) -#define CMD_USBDEV_EPSELECTCLEAR (0x0040) -#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ -#define CMD_USBDEV_EPCLRBUFFER (0x00f2) -#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) - -/* Command/response bit definitions ********************************************/ -/* SETADDRESS (0xd0) command definitions */ - -#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ -#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ - -/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ - -#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ -#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ -#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ -#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ -#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ - -/* EPSELECT (0x00) endpoint status response */ - -#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ -#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ -#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ -#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ -#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ -#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ -#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ - /* Bit 7: Reserved */ -/* EPSETSTATUS (0x40) command */ - -#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ - /* Bits 1-4: Reserved */ -#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ -#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ -#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ - -/* EPCLRBUFFER (0xf2) response */ - -#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) - -/* SETMODE(0xf3) command */ - -#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ -#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ -#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ -#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ -#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ -#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ -#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ - -/* READERRORSTATUS (0xFb) command */ - -#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ -#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ -#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ -#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ -#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ -#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ -#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ -#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ -#define CMD_READERRORSTATUS_ALLERRS (0xff) - -/* DMA ******************************************************************************/ -/* The DMA descriptor */ - -#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ -#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ -#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ -#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ -#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ - -/* Bit settings for CONFIG (offset 1 )*/ - -#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ -#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) -# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ -# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ -#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ - /* Bit 3: Reserved */ -#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ -#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ -#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) -#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ -#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT - -/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ - -#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ -#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) -#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ -#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ -#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ -#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ -#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) -#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ -#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) - -/* DMA packet size format */ - -#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ -#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) -#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ -#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ -#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c index a5cb443e4..b1ddb5928 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -55,13 +55,14 @@ #include #include -#include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" -#include "lpc17_usb.h" -#include "lpc17_syscon.h" +#include "chip.h" +#include "chip/lpc17_usb.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" +#include "lpc17_gpdma.h" /******************************************************************************* * Definitions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c index de880cac1..b0e9958e9 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -56,15 +56,15 @@ #include -#include "lpc17_internal.h" /* Includes default GPIO settings */ #include /* May redefine GPIO settings */ -#include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "lpc17_usb.h" -#include "lpc17_syscon.h" +#include "chip.h" +#include "chip/lpc17_usb.h" +#include "chip/lpc17_syscon.h" +#include "lpc17_gpio.h" #include "lpc17_ohciram.h" /******************************************************************************* diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h index bd7790a6e..b9ef49fc3 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc17xx/lpc17_wdt.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,58 +41,12 @@ ************************************************************************************/ #include - -#include "chip.h" -#include "lpc17_memorymap.h" +#include "chip/lpc17_wdt.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */ -#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */ -#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */ -#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */ -#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET) -#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET) -#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET) -#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET) -#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Watchdog mode register */ - -#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ -#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ -#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ -#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ - /* Bits 14-31: Reserved */ - -/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */ - -/* Watchdog feed sequence register */ - -#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */ - /* Bits 14-31: Reserved */ -/* Watchdog timer value register (Bits 0-31: Counter timer value) */ - -/* Watchdog clock source selection register */ - -#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ -#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT) -# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */ -# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ -# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ - /* Bits 2-30: Reserved */ -#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/configs/lincoln60/src/up_boot.c b/nuttx/configs/lincoln60/src/up_boot.c index 42b01a3ea..6e67f777b 100644 --- a/nuttx/configs/lincoln60/src/up_boot.c +++ b/nuttx/configs/lincoln60/src/up_boot.c @@ -47,7 +47,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" #include "lincoln60_internal.h" /************************************************************************************ diff --git a/nuttx/configs/lincoln60/src/up_buttons.c b/nuttx/configs/lincoln60/src/up_buttons.c index 55781846d..76cb1f2d9 100644 --- a/nuttx/configs/lincoln60/src/up_buttons.c +++ b/nuttx/configs/lincoln60/src/up_buttons.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/lincoln60/src/up_buttons.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,7 +47,7 @@ #include -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lincoln60_internal.h" #ifdef CONFIG_ARCH_BUTTONS diff --git a/nuttx/configs/lincoln60/src/up_leds.c b/nuttx/configs/lincoln60/src/up_leds.c index fe00895b1..3b8692d93 100644 --- a/nuttx/configs/lincoln60/src/up_leds.c +++ b/nuttx/configs/lincoln60/src/up_leds.c @@ -2,7 +2,7 @@ * configs/lincoln60/src/up_leds.c * arch/arm/src/board/up_leds.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lincoln60_internal.h" diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h b/nuttx/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h index 41ec1ce11..3e7dfa4e5 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h +++ b/nuttx/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h @@ -141,8 +141,8 @@ * SD Signal Pin Pin * --- ----------- ----- -------- * CS PIO1_11* 55 P2.2 (See LPCXPRESSO_SD_CS) - * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in lpc17_internal.h) - * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in lpc17_internal.h) + * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in chip/lpc17_ssp.h) + * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in chip/lpc17_ssp.h) * CLK PIO2_11-SCK 7 P0.9 SCK1 (See GPIO_SSP1_SCK in board.h) * CD PIO2_10 52 P2.11 (See LPCXPRESSO_SD_CD) */ diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_boot.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_boot.c index f672c4517..9766569a9 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/up_boot.c +++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_boot.c @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_ssp.h" #include "lpcxpresso_internal.h" /************************************************************************************ diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_leds.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_leds.c index cebf3a143..85539b378 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/up_leds.c +++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_leds.c @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/src/up_leds.c * arch/arm/src/board/up_leds.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -46,7 +46,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpcxpresso_internal.h" #ifdef CONFIG_ARCH_LEDS diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_oled.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_oled.c index f3ecde909..c22b09ceb 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/up_oled.c +++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_oled.c @@ -2,7 +2,7 @@ * config/lpcxpresso-lpc1768/src/up_oled.c * arch/arm/src/board/up_oled.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,7 +48,8 @@ #include #include -#include "lpc17_internal.h" +#include "lpc17_gpio.h" +#include "lpc17_ssp.h" #include "lpcxpresso_internal.h" /**************************************************************************** diff --git a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c index 7b5f02e31..3504d78c7 100644 --- a/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c +++ b/nuttx/configs/lpcxpresso-lpc1768/src/up_ssp.c @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/src/up_ssp.c * arch/arm/src/board/up_ssp.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" +#include "lpc17_ssp.h" #include "lpcxpresso_internal.h" #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) @@ -155,11 +156,11 @@ void weak_function lpc17_sspinitialize(void) void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_spi0select() Entry"); + ssp_dumpgpio("lpc17_ssp0select() Entry"); #warning "Assert CS here (false)" - ssp_dumpgpio("lpc17_spi0select() Exit"); + ssp_dumpgpio("lpc17_ssp0select() Exit"); } uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -173,7 +174,7 @@ uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_spi1select() Entry"); + ssp_dumpgpio("lpc17_ssp1select() Entry"); if (devid == SPIDEV_MMCSD) { @@ -189,7 +190,7 @@ void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel (void)lpc17_gpiowrite(LPCXPRESSO_OLED_CS, !selected); } #endif - ssp_dumpgpio("lpc17_spi1select() Exit"); + ssp_dumpgpio("lpc17_ssp1select() Exit"); } uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) diff --git a/nuttx/configs/mbed/src/up_boot.c b/nuttx/configs/mbed/src/up_boot.c index 42dd54bf5..489c0a58c 100644 --- a/nuttx/configs/mbed/src/up_boot.c +++ b/nuttx/configs/mbed/src/up_boot.c @@ -47,7 +47,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" #include "mbed_internal.h" /************************************************************************************ @@ -80,3 +79,4 @@ void lpc17_boardinitialize(void) up_ledinit(); #endif } + diff --git a/nuttx/configs/mbed/src/up_leds.c b/nuttx/configs/mbed/src/up_leds.c index bc8a87045..c8c78e3ad 100644 --- a/nuttx/configs/mbed/src/up_leds.c +++ b/nuttx/configs/mbed/src/up_leds.c @@ -2,7 +2,7 @@ * configs/mbed/src/up_leds.c * arch/arm/src/board/up_leds.c * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "mbed_internal.h" diff --git a/nuttx/configs/nucleus2g/src/up_boot.c b/nuttx/configs/nucleus2g/src/up_boot.c index d4c44a455..4718e9f82 100644 --- a/nuttx/configs/nucleus2g/src/up_boot.c +++ b/nuttx/configs/nucleus2g/src/up_boot.c @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_ssp.h" #include "nucleus2g_internal.h" /************************************************************************************ diff --git a/nuttx/configs/nucleus2g/src/up_leds.c b/nuttx/configs/nucleus2g/src/up_leds.c index 41f955af4..e1c39f515 100644 --- a/nuttx/configs/nucleus2g/src/up_leds.c +++ b/nuttx/configs/nucleus2g/src/up_leds.c @@ -2,7 +2,7 @@ * configs/nucleus2g/src/up_leds.c * arch/arm/src/board/up_leds.c * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "nucleus2g_internal.h" diff --git a/nuttx/configs/nucleus2g/src/up_outputs.c b/nuttx/configs/nucleus2g/src/up_outputs.c index 749f331eb..beb979ae0 100644 --- a/nuttx/configs/nucleus2g/src/up_outputs.c +++ b/nuttx/configs/nucleus2g/src/up_outputs.c @@ -7,7 +7,7 @@ * * This file is part of NuttX: * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,7 +54,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "nucleus2g_internal.h" diff --git a/nuttx/configs/nucleus2g/src/up_ssp.c b/nuttx/configs/nucleus2g/src/up_ssp.c index 13a768130..77c07f3eb 100644 --- a/nuttx/configs/nucleus2g/src/up_ssp.c +++ b/nuttx/configs/nucleus2g/src/up_ssp.c @@ -2,7 +2,7 @@ * configs/nucleus2g/src/up_ssp.c * arch/arm/src/board/up_ssp.c * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" +#include "lpc17_ssp.h" #include "nucleus2g_internal.h" #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) @@ -158,7 +159,7 @@ void weak_function lpc17_sspinitialize(void) void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_spiselect() Entry"); + ssp_dumpgpio("lpc17_ssp0select() Entry"); if (devid == SPIDEV_MMCSD) { @@ -166,7 +167,7 @@ void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel lpc17_gpiowrite(NUCLEUS2G_MMCSD_CS, !selected); } - ssp_dumpgpio("lpc17_spiselect() Exit"); + ssp_dumpgpio("lpc17_ssp0select() Exit"); } uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_boot.c b/nuttx/configs/olimex-lpc1766stk/src/up_boot.c index 9d4c3ad3b..9f4200004 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_boot.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_boot.c @@ -47,7 +47,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_ssp.h" #include "lpc1766stk_internal.h" /************************************************************************************ diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_buttons.c b/nuttx/configs/olimex-lpc1766stk/src/up_buttons.c index bcafc7337..6d47d2890 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_buttons.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_buttons.c @@ -47,7 +47,7 @@ #include -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpc1766stk_internal.h" #ifdef CONFIG_ARCH_BUTTONS diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_can.c b/nuttx/configs/olimex-lpc1766stk/src/up_can.c index f947c827e..51d8423e3 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_can.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_can.c @@ -49,7 +49,6 @@ #include "chip.h" #include "up_arch.h" -#include "lpc17_internal.h" #include "lpc17_can.h" #include "lpc1766stk_internal.h" diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_lcd.c b/nuttx/configs/olimex-lpc1766stk/src/up_lcd.c index 93923b91a..4e4c94856 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_lcd.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_lcd.c @@ -52,7 +52,7 @@ #include "up_arch.h" #include "lpc17_syscon.h" #include "lpc17_pwm.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpc1766stk_internal.h" #if defined(CONFIG_NX_LCDDRIVER) && defined(CONFIG_LCD_NOKIA6100) && defined(CONFIG_LPC17_SSP0) diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_leds.c b/nuttx/configs/olimex-lpc1766stk/src/up_leds.c index 75c6a8ce0..e590be39f 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_leds.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_leds.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpc1766stk_internal.h" diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_nsh.c b/nuttx/configs/olimex-lpc1766stk/src/up_nsh.c index 036350ded..99e9c4d9c 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_nsh.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_nsh.c @@ -2,7 +2,7 @@ * config/olimex-lpc1766stk/src/up_nsh.c * arch/arm/src/board/up_nsh.c * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,7 @@ #include #include -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpc1766stk_internal.h" /**************************************************************************** diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_ssp.c b/nuttx/configs/olimex-lpc1766stk/src/up_ssp.c index 272a17065..2c6c613c7 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_ssp.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_ssp.c @@ -53,7 +53,8 @@ #include "up_arch.h" #include "chip.h" -#include "lpc17_internal.h" +#include "lpc17_gpio.h" +#include "lpc17_ssp.h" #include "lpc1766stk_internal.h" #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) diff --git a/nuttx/configs/olimex-lpc1766stk/src/up_usbmsc.c b/nuttx/configs/olimex-lpc1766stk/src/up_usbmsc.c index 08c5fb887..ce7c75771 100644 --- a/nuttx/configs/olimex-lpc1766stk/src/up_usbmsc.c +++ b/nuttx/configs/olimex-lpc1766stk/src/up_usbmsc.c @@ -48,7 +48,7 @@ #include #include -#include "lpc17_internal.h" +#include "lpc17_gpio.h" #include "lpc1766stk_internal.h" /**************************************************************************** -- cgit v1.2.3 From a79a2bfbd6470061ec9a81340ff66c90ec54a376 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 20:25:32 +0000 Subject: More LPC1788 register definitions from Rommel Marcelo git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5535 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h | 494 +++++++++++++++++ .../arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h | 90 ++++ .../arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h | 589 +++++++++++++++++++- nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h | 598 +++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h | 115 +--- nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h | 441 +-------------- nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c | 16 +- nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h | 233 ++++++++ 8 files changed, 2036 insertions(+), 540 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h new file mode 100644 index 000000000..ddacc05b5 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h @@ -0,0 +1,494 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc176x_syscon.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ +#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ +#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ + +#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ +#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ +#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ +#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ +#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ + +#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ +#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ +#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ + +/* Register addresses ***************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) +#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) +#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) +#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) + +#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) +#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) +#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) +#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) +#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) +#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) + +#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) +#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) + +/* More clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET) +#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET) + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Flash accelerator module */ + /* Bits 0-11: Reserved */ +#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ +#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) +# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock + * (Up to 120 Mhz for LPC1759/69 only */ +# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ + /* Bits 16-31: Reserved */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: + * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. + * 1:User mode. The on-chip Flash memory is mapped to address 0 */ + /* Bits 1-31: Reserved */ + +/* Clocking and power control -- Clock source selection */ + +#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ +#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) +# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ +# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ +# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ + /* Bits 2-31: Reserved */ + +/* Clocking and power control - Phase locked loops */ +/* PLL0/1 Control register */ + +#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ +#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ + /* Bits 2-31: Reserved */ +/* PLL0 Configuration register */ + +#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ +#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ +#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) + /* Bits 24-31: Reserved */ +/* PLL1 Configuration register */ + +#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ +#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) +#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ +#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) + /* Bits 7-31: Reserved */ +/* PLL0 Status register */ + +#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ +#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) + /* Bit 15: Reserved */ +#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ +#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) +#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ +#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ +#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ + /* Bits 27-31: Reserved */ +/* PLL1 Status register */ + +#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ +#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) +#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ +#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) + /* Bit 7: Reserved */ +#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ +#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ +#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ + /* Bits 11-31: Reserved */ +/* PLL0/1 Feed register */ + +#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ +#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) + /* Bits 8-31: Reserved */ +/* Clocking and power control -- Clock dividers */ +/* CPU Clock Configuration register */ + +#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) +# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ + /* Bits 8-31: Reserved */ +/* USB Clock Configuration register */ + +#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ +#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) +# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ +# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ +# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ + /* Bits 8-31: Reserved */ +/* Peripheral Clock Selection registers 0 and 1 */ + +#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ +#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ +#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ +#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ +#define SYSCON_PCLKSEL_MASK (3) + +#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ +#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) +#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ +#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) +#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ +#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) +#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ +#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) +#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ +#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) + /* Bits 10-11: Reserved */ +#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ +#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) +#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ +#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) +#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ +#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) + /* Bits 18-19: Reserved */ +#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ +#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) +#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ +#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) +#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ +#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) +#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ +#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) +#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ +#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) +#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ +#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) + +#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ +#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) +#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ +#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) +#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ +#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) +#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ +#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) + /* Bits 8-9: Reserved */ +#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ +#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) +#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ +#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) +#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ +#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) +#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ +#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) +#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ +#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) +#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ +#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) +#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ +#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) + /* Bits 24-25: Reserved */ +#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ +#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) +#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ +#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) +#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ +#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) + +/* Clocking and power control - Peripheral power control registers */ +/* Power Control Register */ + +#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ +#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ +#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ +#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ +#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ + /* Bits 5-7: Reserved */ +#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ +#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ +#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ +#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ + /* Bits 12-31: Reserved */ +/* Power Control for Peripherals Register */ + + /* Bit 0: Reserved */ +#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ +#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ +#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ +#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ + /* Bit 5: Reserved */ +#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ +#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ +#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ +#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ +#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ + /* Bit 11: Reserved */ +#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ +#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ +#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ +#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ +#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ +#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ +#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ +#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ + /* Bit 20: Reserved */ +#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ +#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ +#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ +#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ +#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ +#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ +#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ + /* Bit 28: Reserved */ +#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ +#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ +#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ + +/* More clocking and power control -- Utility */ + +#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ +#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) +# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ +# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ +# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ +# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ +# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ +#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ +#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) +# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ +#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ +#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ + /* Bits 10-31: Reserved */ +/* System control registers -- External Interrupts */ +/* External Interrupt Flag register */ + +#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ +#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ +#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ +#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ + /* Bits 4-31: Reserved */ +/* External Interrupt Mode register */ + +#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ +#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ +#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ +#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ + /* Bits 4-31: Reserved */ +/* External Interrupt Polarity register */ + +#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ + /* Bits 4-31: Reserved */ +/* System control registers -- Reset */ +/* Reset Source Identification Register */ + +#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ +#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ +#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ +#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ + /* Bits 4-31: Reserved */ +/* System control registers -- Syscon Miscellaneous Registers */ + + /* Bits 0-3: Reserved */ +#define SYSCON_SCS_OSCRANGE (1 << 4) /* Bit 4: Main oscillator range select */ +#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ +#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ + /* Bits 7-31: Reserved */ +/* Device Interrupt Registers */ +/* USB Interrupt Status register */ + +#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ +#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ +#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ +#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ +#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ +#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ +#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ + /* Bit 7: Reserved */ +#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ + /* Bits 9-30: Reserved */ +#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ + +/* DMA Request Select Register */ + +#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ +#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ +#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ +#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ +#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ +#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ +#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ +#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ + /* Bits 8-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h index 21e8e6c33..295e1a0ee 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h @@ -48,6 +48,96 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* Memory Map ***********************************************************************/ + +#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip Peripheral SRAM (devices >32Kb) */ +# define LPC17_SRAM_BANK0 0x20000000 /* -0x20003fff: On-chip Peripheral SRAM Bank0 (devices >=32Kb) */ +# define LPC17_SRAM_BANK1 0x20004000 /* -0x20007fff: On-chip Peripheral SRAM Bank1 (devices 64Kb) */ +#define LPC17_AHB_BASE 0x20080000 /* -0x2008ffff: DMA Controller, Ethernet, and USB */ +#define LPC17_SPIFI_BASE 0x28000000 +#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ + +/* Off chip Memory via External Memory Interface */ + +#define LPC17_EXTRAM_BASE 0x80000000 /* */ +# define LPC17_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */ +# define LPC17_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */ +# define LPC17_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */ +# define LPC17_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */ + +# define LPC17_EXTDRAM_CS0 0x9c000000 /* Chip select 0 /up to 256MB/ */ +# define LPC17_EXTDRAM_CS1 0x9c000000 /* Chip select 1 /up to 256MB/ */ +# define LPC17_EXTDRAM_CS2 0x9c000000 /* Chip select 2 /up to 256MB/ */ +# define LPC17_EXTDRAM_CS3 0x9c000000 /* Chip select 3 /up to 256MB/ */ + +#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_SCS_BASE 0xe000e000 +#define LPC17_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ +#define LPC17_PWM0_BASE 0x40014000 /* -0x40017fff: PWM 0 */ +#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ + /* -0x40023fff: Reserved */ +#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ + /* -0x400a7fff: Reserved */ +#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ +#define LPC17_SSP2_BASE 0x400ac000 /* -0x400affff: SSP2 */ + /* -0x400b3fff: Reserved */ + /* -0x400b7fff: Reserved */ +#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ +#define LPC17_MCI_BASE 0x400c0000 /* -0x400fbfff: SD interface */ +#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_GPDMA_BASE 0x20080000 /* GPDMA controller */ +#define LPC17_ETH_BASE 0x20084000 /* Ethernet controller */ +#define LPC17_LCD_BASE 0x20088000 /* LCD controller */ +#define LPC17_USB_BASE 0x2008c000 /* USB controller */ +#define LPC17_CRC_BASE 0x20090000 /* CRC engine */ +#define LPC17_GPIO_BASE 0x20098000 /* GPIO */ +#define LPC17_EMC_BASE 0x2009c000 /* External Memory Controller */ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h index 53c2b26a9..37a16c1e0 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h @@ -48,7 +48,7 @@ ************************************************************************************/ /* GPIO pin definitions *************************************************************/ /* NOTE that functions have a alternate pins that can be selected. These alternates - * are identified with a numerica suffix like _1, _2, or _3. Your board.h file + * are identified with a numerical suffix like _1, _2, or _3. Your board.h file * should select the correct alternative for your board by including definitions * such as: * @@ -57,6 +57,593 @@ * (without the suffix) */ +#define GPIO_CAN1_RD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_UART3_TXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_I2C1_SDA_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_UART0_TXD_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0) + +#define GPIO_CAN1_TD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_UART3_RXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_I2C1_SCL_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_UART0_RXD_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) + +#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_UART3_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) + +#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_UART3_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) + +#define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAN2_RD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_LCD_VD0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) + +#define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAN2_TD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_LCD_VD1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) + +#define GPIO_I2S_RXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_UART1_RTS_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_LCD_VD8 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) + +#define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_RTC_EV0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_LCD_VD9 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) + +#define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_LCD_VD16 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) + +#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_RTC_EV2_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_LCD_VD17 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) + +#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) + +#define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) + +#define GPIO_USB_PPWR2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_AD0p6 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) + +#define GPIO_USB_LED2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_AD0p7 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) + +#define GPIO_USB_HSTEN2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_USB_CONNECT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) + +#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_SSP0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) +#define GPIO_SPIFI_IO2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) + +#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_SSP0_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) +#define GPIO_SPIFI_IO3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16) + +#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SSP0_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SPIFI_IO1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17) + +#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SSP0_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SPIFI_IO0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18) + +#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_SD_CLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_I2C1_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19) + +#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_SD_CMD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_I2C1_SCL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20) + +#define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_SD_PWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART4_OE (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_CAN1_RD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART4_SCLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) + +#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_SD_DAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_UART4_TXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_CAN1_TD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_SPIFI_SCLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) + +#define GPIO_AD0p0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_I2S_RXCLK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) + +#define GPIO_AD0p1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_I2S_RXWS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) + +#define GPIO_AD0p2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_I2S_RXSDA_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) + +#define GPIO_AD0p3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_AOUT (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) + +#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_USB_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) + +#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_USB_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) + +#define GPIO_USB1DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_EINT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN29) + +#define GPIO_USB1DM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_EINT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN30) + +#define GPIO_USB2_DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN31) + +#define GPIO_ENET_TXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_SSP2_SCK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) + +#define GPIO_ENET_TXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_SSP2_MOSI (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) + +#define GPIO_ENET_TXD2 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_SD_CLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_PWM0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) + +#define GPIO_ENET_TXD3 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_SD_CMD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_PWM0p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) + +#define GPIO_ENET_TXEN (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_SSP2_MISO (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) + +#define GPIO_ENET_TX_ER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_SD_PWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_PWM0p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) + +#define GPIO_ENET_TX_CLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SD_DAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_PWM0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) + +#define GPIO_ENET_COL (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SD_DAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_PWM0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) + +#define GPIO_ENET_CRSDV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SSP2_SSEL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) + +#define GPIO_ENET_RXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) + +#define GPIO_ENET_RXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) + +#define GPIO_ENET_RXD2 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_SD_DAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_PWM0p6 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) + +#define GPIO_ENET_RXD3 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_SD_DAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_PWM0CAPp0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) + +#define GPIO_ENET_RX_DV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN13) + +#define GPIO_ENET_RXER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN14) + +#define GPIO_ENET_REFCLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_I2C2_SDA (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN15) + +#define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_I2S_TXMCLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN16) + +#define GPIO_ENET_MDIO_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_I2S_RXMCLK (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN17) + +#define GPIO_USB_UPLED (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_PWM1p1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_SSP1_MISO (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) + +#define GPIO_USB1_TXE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_USB1_PPWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_MCPWM_MC0A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_SSP1_SCK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_UART2_OE (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) + +#define GPIO_USB1_TXDP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_PWM1p2_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_QEI_PHA (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_MCPWM_MCFB0 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_SSP0_SCK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_LCD_VD6 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_LCD_VD10 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) + +#define GPIO_USB1_TXDM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_PWM1p3_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_SSP0_SSEL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_MCPWM_ABORT (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_LCD_VD7 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_LCD_VD11 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) + +#define GPIO_USB1_RCV (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_USB1_PWRD (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_MCPWM_MCOB (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_SSP1_MOSI (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_LCD_VD8 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_LCD_VD12 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) + +#define GPIO_USB1_RXDP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_PWM1p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_QEI_PHB (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_MCPWM_MCFB1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPPIO_SSP0_MOSI (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_LCD_VD9 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_LCD_VD13 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) + +#define GPIO_USB1_RXDM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_PWM1p5_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_QEI_IDX (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_MCPWM_MCFB2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_SSP0_MOSI_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_LCD_VD10_VD14 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_LCD_VD10_VD14 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) + +#define GPIO_USB1_LS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_USB1_HSTEN (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_MCPWM_MC1A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_CLKOUT_ (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_LCD_VD11 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_LCD_VD15 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) + +#define GPIO_USB1_SSPND (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_PWM1p6_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_MCPWM_MC1B (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_SSP1_SSEL (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_LCD_VD12 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_LCD_VD20 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) + +#define GPIO_USB1_INT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_USB1_OVRCR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CLKOUT_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_LCD_VD13 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_LCD_VD21 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) + +#define GPIO_USB1_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_PCAP1p0_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_MAT0p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_MCPWM_MC2A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_SSP0_SSEL (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_LCD_VD14 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_LCD_VD22 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) + +#define GPIO_USB1_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_PCAP1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_MAT0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_MCPWM_MC2B (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_UART4_TXD (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_LCD_VD15 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_LCD_VD23 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) + +#define GPIO_USB2_PWRD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_USB_VBUS (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_AD0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_I2C0_SDA (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_UART3_OE (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) + +#define GPIO_USB2_OVRCR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_SSP1_SCK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_AD0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_I2C0_SCL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) + +#define GPIO_PWM1p1_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) +#define GPIO_LCD_PWR (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) + +#define GPIO_PWM1p2_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_UART1_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) +#define GPIO_LCD_LE (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1) + +#define GPIO_PWM1p3_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_TRACEDATA3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_LCD_DCLK (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) + +#define GPIO_PWM1p4_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_TRACEDATA2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_LCD_FP (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) + +#define GPIO_PWM1p5_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_MAT2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_TRACEDATA1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_LCD_ENABM (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) + +#define GPIO_PWM1p6_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_MAT2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_TRACEDATA0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_LCD_LP (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) + +#define GPIO_PCAP1p0_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_UART2_OE (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_TRACECLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_LCD_VD0_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_LCD_VD4 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) + +#define GPIO_CAN2_RD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_SPIFI_CS (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_LCD_VD1_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_LCD_VD5 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) + +#define GPIO_CAN2_TD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_UART1_CTS (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_ENET_MDC_2 (GPIO_ALT4 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LCD_VD2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LCD_VD6 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) + +#define GPIO_USB1_CONNECT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_UART4_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_ENET_MDIO_2 (GPIO_ALT4 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LCD_VD3 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LCD_VD7 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) + +#define GPIO_EINT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_NMI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) + +#define GPIO_EINT1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_SD_DAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_I2S_TXCLK_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_LCD_CLKIN (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) + +#define GPIO_EINT2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_SD_DAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_I2S_TXWS_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD4 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD8 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD18 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) + +#define GPIO_EINT3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_SD_DAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_I2S_TXSDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_VD5 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_VD9 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_VD19 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) + +#define GPIO_EMC_CS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_I2C1_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) + +#define GPIO_EMC_CS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_I2C1_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) + +#define GPIO_EMC_CAS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_EMC_RAS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_EMC_CLK0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN18) + +#define GPIO_EMC_CLK1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN19) +#define GPIO_EMC_DYCS0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN20) +#define GPIO_EMC_DYCS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN21) + +#define GPIO_EMC_DYCS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_SSP0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) + +#define GPIO_EMC_DYCS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_SSP0_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) + +#define GPIO_EMC_CKE0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN24) +#define GPIO_EMC_CKE1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN25) + +#define GPIO_EMC_CKE2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_SSP0_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) + +#define GPIO_EMC_CKE3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_SSP0_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) + +#define GPIO_EMC_DQM0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN28) +#define GPIO_EMC_DQM1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN29) + +#define GPIO_EMC_DQM2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) + +#define GPIO_EMC_DQM3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) + +#define GPIO_EMC_D0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_EMC_D1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_EMC_D2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_EMC_D3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_EMC_D4 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_EMC_D5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_EMC_D6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_EMC_D7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_EMC_D8 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_EMC_D9 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_EMC_D10 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_EMC_D11 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_EMC_12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_EMC_D13 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_EMC_D14 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_EMC_D15 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN15) + +#define GPIO_EMC_D16 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_PWM0p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_UART1_TXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) + +#define GPIO_EMC_D17 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_PWM0p2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_UART1_RXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) + +#define GPIO_EMC_D18 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_PWM0p3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_UART1_CTS (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) + +#define GPIO_EMC_D19 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_PWM0p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_UART1_DCD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) + +#define GPIO_EMC_D20 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_PWM0p5 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_UART1_DSR (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) + +#define GPIO_EMC_D21 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) +#define GPIO_PWM0p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) +#define GPIO_UART1_DTR (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) + +#define GPIO_EMC_D22 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) +#define GPIO_PWM0CAPp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) +#define GPIO_UART1_RI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) + +#define GPIO_EMC_D23 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) +#define GPIO_PWM1CAPp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) +#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) + +#define GPIO_EMC_D24 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) +#define GPIO_PWM1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) +#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) + +#define GPIO_EMC_D25 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_PWM1p2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_MAT0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) + +#define GPIO_EMC_D26 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_PWM1p3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_MAT0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_STCLK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) + +#define GPIO_EMC_D27 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_PWM1p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) + +#define GPIO_EMC_D28 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_PWM1p5 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) + +#define GPIO_EMC_D29 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_PWM1p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) + +#define GPIO_EMC_D30 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_UART1_RTS (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) + +#define GPIO_EMC_D31 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_MAT1p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN31) + +#define GPIO_EMC_A0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_EMC_A1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_EMC_A2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_EMC_A3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_EMC_A4 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_EMC_A5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_EMC_A6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_EMC_A7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_EMC_A8 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_EMC_A9 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_EMC_A10 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_EMC_A11 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN11) +#define GPIO_EMC_A12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN12) +#define GPIO_EMC_A13 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN13) +#define GPIO_EMC_A14 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN14) +#define GPIO_EMC_A15 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN15) +#define GPIO_EMC_A16 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN16) +#define GPIO_EMC_A17 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN17) +#define GPIO_EMC_A18 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN18) +#define GPIO_EMC_A19 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN19) + +#define GPIO_EMC_A20 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_SSP1_SCK (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) + +#define GPIO_EMC_A21 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_SSP1_SSEL (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) + +#define GPIO_EMC_A22 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_UART2_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_SSP1_MISO (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) + +#define GPIO_EMC_A23 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_UART2_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_SSP1_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) + +#define GPIO_EMC_OE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_EMC_WE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_EMC_BLS0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN26) +#define GPIO_EMC_BLS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN27) + +#define GPIO_EMC_BLS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_UART3_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_MAT2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD6 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD10 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) + +#define GPIO_EMC_BLS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_UART3_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_MAT2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_I2C2_SCL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD7 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD11 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) + +#define GPIO_EMC_CS0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_EMC_CS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN31) + +#define GPIO_EMC_A24 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) + +#define GPIO_EMC_A25 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) + +#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_I2C0_SDA (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) + +#define GPIO_UART4_RXD (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_I2C0_SCL0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) + +#define GPIO_UART4_OE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_UART4_TXD (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h new file mode 100644 index 000000000..5aafce7a6 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h @@ -0,0 +1,598 @@ +/**************************************************************************************************** + * arch/arm/src/lpc17xx/chip/lpc178x_syscon.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ +#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ +#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ +#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ + +#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ +#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ +#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ +#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ +#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_EMCCLKCFG_OFFSET 0x0100 /* EMC Clock Configuration Register */ +#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ +#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ +#define LPC17_SYSCON_CANSLEEPCLR_OFFSET 0x0110 /* CAN Channel Sleep State Register */ +#define LPC17_SYSCON_CANWAKEFLAGS_OFFSET 0x0114 /* CAN Channel Wake-Up State Register */ + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ +#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ +#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_MATRIXARB_OFFSET 0x0188 /* Matrix Arbitration Register */ +#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ +#define LPC17_SYSCON_PCLKSEL_OFFSET 0x01a8 /* Peripheral Clock Selection Register */ +#define LPC17_SYSCON_PBOOST_OFFSET 0x01b0 /* Power Boost Register */ +#define LPC17_SYSCON_SPIFICLKSEL_OFFSET 0x01b4 /* SPIFI Clock Selection Register */ +#define LPC17_SYSCON_LCDCFG_OFFSET 0x01b8 /* LCD Clock Configuration Register */ + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ + +/* Peripheral Reset Control */ + +#define LPC17_SYSCON_RSTCON0_OFFSET 0x01cc /* Individual Peripheral Reset Control Bits */ +#define LPC17_SYSCON_RSTCON1_OFFSET 0x01d0 /* Individual Peripheral Reset Control Bits */ + +/* EMC Clock Control and Calibration */ + +#define LPC17_SYSCON_EMCDLYCTL_OFFSET 0x01dc /* Programmable Delays for SDRAM Operation */ +#define LPC17_SYSCON_EMCCAL_OFFSET 0x01e0 /* Calibration Counter for EMCDLYCTL */ + + +/* Register addresses *******************************************************************************/ +/* Flash accelerator module */ + +#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) + +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) + +/* Clocking and power control - Phase locked loops */ + +#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) +#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) +#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) +#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) + +#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) +#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) +#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) +#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) + +/* Clocking and power control - Peripheral power control registers */ + +#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) +#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) + +/* Clocking and power control -- Clock dividers */ + +#define LPC17_SYSCON_EMCCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKCFG_OFFSET) +#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) +#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) + +/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ + +/* Clocking and power control -- Clock source selection */ + +#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) +#define LPC17_SYSCON_CANSLEEPCLR (LPC17_SYSCON_BASE+LPC17_SYSCON_CANSLEEPCLR_OFFSET) +#define LPC17_SYSCON_CANWAKEFLAGS (LPC17_SYSCON_BASE+LPC17_SYSCON_CANWAKEFLAGS_OFFSET) + +/* System control registers -- External Interrupts */ + +#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) + +#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) +#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) + +/* System control registers -- Reset */ + +#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) + +/* System control registers -- Syscon Miscellaneous Registers */ + +#define LPC17_SYSCON_MATRIXARB (LPC17_SYSCON_BASE+LPC17_SYSCON_MATRIXARB_OFFSET) +#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) +#define LPC17_SYSCON_PCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL_OFFSET) +#define LPC17_SYSCON_PBOOST (LPC17_SYSCON_BASE+LPC17_SYSCON_PBOOST_OFFSET) +#define LPC17_SYSCON_SPIFICLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_SPIFICLKSEL_OFFSET) +#define LPC17_SYSCON_LCDCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_LCDCFG_OFFSET) + +/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ + +#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) + +/* DMA Request Select Register */ + +#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) + +/* More clocking and power control -- Utility */ + +#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) + + +/* Peripheral Reset Control */ + +#define LPC17_SYSCON_RSTCON0 (LPC17_SYSCON_BASE+LPC17_SYSCON_RSTCON0_OFFSET) +#define LPC17_SYSCON_RSTCON1 (LPC17_SYSCON_BASE+LPC17_SYSCON_RSTCON1_OFFSET) + +/* EMC Clock Control and Calibration */ + +#define LPC17_SYSCON_EMCDLYCTL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCDLYCTL_OFFSET) +#define LPC17_SYSCON_EMCCAL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCAL_OFFSET) + +/* Register bit definitions *************************************************************************/ +/* Flash accelerator module */ + /* Bits 0-11: Reserved */ +#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ +#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) +# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ +# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock + * (Up to 120 Mhz for LPC1788x) */ +# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ + /* Bits 16-31: Reserved */ +/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ + +#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: + * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. + * 1:User mode. The on-chip Flash memory is mapped to address 0 */ + /* Bits 1-31: Reserved */ +/* Clocking and power control -- Clock source selection */ + +#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0: Clock selection */ +#define SYSCON_CLKSRCSEL_MASK (1 << SYSCON_CLKSRCSEL_SHIFT) +# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ +# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ + /* Bits 1-31: Reserved */ +/* Clocking and power control - Phase locked loops */ +/* PLL0/1 Control register */ + +#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL Enable */ + /* Bits 1-31: Reserved */ +/* PLL0/1 Configuration register */ + +#define SYSCON_PLLCFG_MSEL_SHIFT (0) /* Bit 0-4: PLL Multiplier value */ +#define SYSCON_PLLCFG_MSEL_MASK (0x1f << SYSCON_PLL0CFG_MSEL_SHIFT) +#define SYSCON_PLLCFG_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value */ +#define SYSCON_PLLCFG_PSEL_MASK (3 << SYSCON_PLL0CFG_PSEL_SHIFT) + +/* PLL0/1 Status register */ + +#define SYSCON_PLLSTAT_MSEL_SHIFT (0) /* Bit 0-4: PLLMultiplier value readback */ +#define SYSCON_PLLSTAT_MSEL_MASK (0x1f << SYSCON_PLLSTAT_MSEL_SHIFT) +#define SYSCON_PLLSTAT_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value readback */ +#define SYSCON_PLLSTAT_PSEL_MASK (3 << SYSCON_PLLSTAT_PSEL_SHIFT) + /* Bit 7: Reserved */ +#define SYSCON_PLLSTAT_PLLE (1 << 8) /* Bit 8: PLL enable readback */ +#define SYSCON_PLLSTAT_PLLC (1 << 9) /* Bit 9: PLL connect readback */ +#define SYSCON_PLLSTAT_PLOCK (1 << 10) /* Bit 10: PLL lock status */ + /* Bits 11-31: Reserved */ +/* PLL0/1 Feed register */ + +#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ +#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) + /* Bits 8-31: Reserved */ +/* Clocking and power control -- Clock dividers */ + +/* EMC Clock Selection Register */ + +#define SYSCON_EMCDIV (1 << 0) /* Bit 0: EMC Clock rate relative to CPU */ + /* 0: EMC uses same clock as CPU */ + /* 1: EMC uses half the rate of CPU */ + /* Bits 1-31: Reserved +/* CPU Clock Configuration register */ + +#define SYSCON_CCLKCFG_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */ +#define SYSCON_CCLKCFG_CCLKDIV_MASK (0x1f << SYSCON_CCLKCFG_CCLKDIV_SHIFT) +# define SYSCON_CCLKCFG_CCLKDIV(n) ((n-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT) /* n = 2 - 31 */ + /* Bits 5-7: Reserved */ +#define SYSCON_CCLKCFG_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */ + /* 0: Sysclk used as input to CCLKDIV */ + /* 1: Main PLL used as input to CCLKDIV */ + /* Bits 9-31: Reserved */ +/* USB Clock Configuration register */ + +#define SYSCON_USBCLKCFG_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */ +#define SYSCON_USBCLKCFG_USBDIV_MASK (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT) +# define SYSCON_USBCLKCFG_USBDIV_DIV1 (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */ +# define SYSCON_USBCLKCFG_USBDIV_DIV2 (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */ +# define SYSCON_USBCLKCFG_USBDIV_DIV3 (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */ + /* Bits 5-7: Reserved */ +#define SYSCON_USBCLKCFG_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */ +#define SYSCON_USBCLKCFG_USBSEL_MASK (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT) +#define SYSCON_USBCLKCFG_USBSEL_MAINPLL (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */ +#define SYSCON_USBCLKCFG_USBSEL_ALTPLL (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */ + /* 11: unused */ + /* Bits 10-31: Reserved */ +/* CAN0/1 Sleep Clear Register */ + /* Bit 0: Reserved */ +#define SYSCON_CANSLEEPCLR_SHIFT (1) /* Bits 1-2: CAN0/1 Sleep Status and Control */ +#define SYSCON_CANSLEEPCLR_MASK (3 << SYSCON_CANSLEEPCLR_SHIFT) /* */ +#define SYSCON_CANSLEEPCLR_CAN1 (1 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN1 Sleep Status */ +#define SYSCON_CANSLEEPCLR_CAN2 (2 << SYSCON_CANSLEEPCLR_SHIFT) /* CAN2 Sleep Status */ + /* Read 1: CAN channel in sleep mode */ + /* Write 1: CAN channel clocks restored */ + /* Bits 3-31: Reserved */ +/* CAN0/1 WakeUp Flags Register */ + /* Bit 0: Reserved */ +#define SYSCON_CANWAKEFLAGS_SHIFT (1) /* Bits 1-2: CAN0/1 WakeUp Status */ +#define SYSCON_CANWAKEFLAGS_MASK (3 << SYSCON_CANWAKEFLAGS_SHIFT) /* */ +#define SYSCON_CANWAKEFLAGS_CAN1 (1 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN1 WakeUp Status */ +#define SYSCON_CANWAKEFLAGS_CAN2 (2 << SYSCON_CANWAKEFLAGS_SHIFT) /* CAN2 WakeUp Status */ + /* Read 1: CAN channel falling edge occur on receive line */ + /* Write 1: CAN channel clears wakeup flag bit */ + /* Bits 3-31: Reserved */ +/* Peripheral Clock Selection register */ +/* PCLK is common to all peripheral */ + +#define SYSCON_PCLKSEL_PCLKDIV_SHIFT (0) /* Bits 0-4: Clock divide value for all APB peripherals */ +#define SYSCON_PCLKSEL_PCLKDIV_MASK (0x1f << SYSCON_PCLKSEL_PCLKDIV_SHIFT) +# define SYSCON_PCLKSEL_PCLKDIV(n) ((n-1) << SYSCON_PCLKSEL_PCLKDIV_SHIFT) /* n = 2 - 31 */ + /* Bits 5-31: Reserved */ +/* Power Boost Control Register */ + +#define SYSCON_PBOOST_BOOST_SHIFT (0) /* Bits 0-1: Boost control bits */ +#define SYSCON_PBOOST_BOOST_MASK (3 << SYSCON_PBOOST_BOOST_SHIFT) +#define SYSCON_PBOOST_BOOST_OFF (0) /* Boost OFF, operation must be below 100MHz */ +#define SYSCON_PBOOST_BOOST_ON (3) /* Boost ON, operation upto 120MHz allowed */ + /* Bits 2-31: Reserved */ +/* SPIFI Clock Selection Register */ + +#define SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT (0) /* Bits 0-4: divide value for SPIFI clock */ +#define SYSCON_SPIFICLKSEL_SPIFIDIV_MASK (0x1f << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) +# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */ + /* Bits 5-7: Reserved */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT (8) /* Bits 8-9: Selects input clock for SPIFI clock divider */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_MASK (3 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) +#define SYSCON_SPIFICLKSEL_SPIFISEL_SYSCLK (0) /* Sysclk used as input to SPIFIDIV */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL0 (1 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Main PLL used as input to SPIFIDIV */ +#define SYSCON_SPIFICLKSEL_SPIFISEL_PLL1 (2 << SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT) /* Alt PLL used as input to SPIFIDIV */ + /* Bits 10-31: Reserved */ +/* LCD Configuration Register */ + +#define SYSCON_LCDCFG_CLKDIV_SHIFT (0) /* Bits 0-4: LCD Panel clock prescaler */ +#define SYSCON_LCDCFG_CLKDIV_MASK (0x1f << SYSCON_LCDCFG_CLKDIV_SHIFT) +#define SYSCON_LCDCFG_CLKDIV(n) ((n+1) << SYSCON_LCDCFG_CLKDIV_SHIFT) /* n = 0 - 31 */ + /* Bits 5-31: Reserved */ +/* Clocking and power control - Peripheral power control registers */ +/* Power Control Register */ + +#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ +#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ +#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ +#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ +#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ + /* Bits 5-7: Reserved */ +#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ +#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ +#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ +#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ + /* Bits 12-31: Reserved */ +/* Power Control for Peripherals Register */ + +#define SYSCON_PCONP_PCLCD (1 << 0) /* Bit 0: LCD power/clock control */ +#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ +#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ +#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ +#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ +#define SYSCON_PCONP_PCPWM0 (1 << 5) /* Bit 5: PWM0 power/clock control */ +#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ +#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ +#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ +#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ +#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ +#define SYSCON_PCONP_PCEMC (1 << 11) /* Bit 11: External Memory */ +#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ +#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ +#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ +#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ +#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ +#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ +#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ +#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ +#define SYSCON_PCONP_PCSSP0 (1 << 20) /* Bit 20: SSP2 power/clock control */ +#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ +#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ +#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ +#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ +#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ +#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ +#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ +#define SYSCON_PCONP_PCSDC (1 << 28) /* Bit 28: SD Card power/clock control */ +#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ +#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ +#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ + +/* More clocking and power control -- Utility */ + +#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ +#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) +# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ +# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ +# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ +# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ +# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ +# define SYSCON_CLKOUTCFG_SEL_SPIFI (5 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=SPIFI osc */ +#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ +#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) +# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ +#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ +#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ + /* Bits 10-31: Reserved */ +/* System control registers -- External Interrupts */ +/* External Interrupt Flag register */ + +#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ +#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ +#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ +#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ + /* Bits 4-31: Reserved */ +/* External Interrupt Mode register */ + +#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ +#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ +#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ +#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ + /* Bits 4-31: Reserved */ +/* External Interrupt Polarity register */ + +#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ +#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ + /* Bits 4-31: Reserved */ +/* System control registers -- Reset */ +/* Reset Source Identification Register */ + +#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ +#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ +#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ +#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ +#define SYSCON_RSID_SYSRESET (1 << 4) /* Bit 4: System Reset */ +#define SYSCON_RSID_LOCKUP (1 << 5) /* Bit 5: Lockup Reset */ + /* Bits 6-31: Reserved */ +/* System control registers -- Matrix Arbitration Priorities */ +/*TODO*/ +#define SYSCON_MATRIXARB_PRI_ICODE (3 << 0) /* Bit 0-1: I-Code bus priority (should be lower than D-Code */ +#define SYSCON_MATRIXARB_PRI_DCODE (3 << 2) /* Bit 2-3: D-Code bus priority */ +#define SYSCON_MATRIXARB_PRI_SYS (3 << 4) /* Bit 4-5: System bus priority */ +#define SYSCON_MATRIXARB_PRI_GPDMA (3 << 6) /* Bit 6-7: General Purpose DMA priority */ +#define SYSCON_MATRIXARB_PRI_ETH (3 << 8) /* Bit 8-9: Ethernet DMA priority */ +#define SYSCON_MATRIXARB_PRI_LCD (3 << 10) /* Bit 10-11: LCD DMA priority */ +#define SYSCON_MATRIXARB_PRI_USB (3 << 12) /* Bit 12-13: USB DMA priority */ + /* Bits 14-15: Reserved */ +#define SYSCON_MATRIXARB_ROM_LAT (1 << 16) /* Bit 16: ROM Latency select (should always be zero) */ + /* Bits 17-31: Reserved */ +/* System control registers -- Syscon Miscellaneous Registers */ + +#define SYSCON_SCS_EMCSC (1 << 0) /* Bit 0: EMC shift control */ +#define SYSCON_SCS_EMCRD (1 << 1) /* Bit 1: EMC reset disable */ +#define SYSCON_SCS_EMCBC (1 << 2) /* Bit 2: EMC burst control */ +#define SYSCON_SCS_MCIPWRAL (1 << 3) /* Bit 3: MCI power active level */ +#define SYSCON_SCS_OSCRS (1 << 4) /* Bit 4: Main oscillator range select */ +#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ +#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ + /* Bits 7-31: Reserved */ +/* Device Interrupt Registers */ +/* USB Interrupt Status register */ + +#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ +#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ +#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ +#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ +#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ +#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ +#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ + /* Bit 7: Reserved */ +#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ + /* Bits 9-30: Reserved */ +#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ + +/* DMA Request Select Register */ + +#define SYSCON_DMAREQSEL_INP0 (1 << 0) /* Bit 0: Input 0 0=unused 1=Timer 0 match 0 */ +#define SYSCON_DMAREQSEL_INP1 (1 << 1) /* Bit 1: Input 1 0=SD 1=Timer 0 match 1 */ +#define SYSCON_DMAREQSEL_INP2 (1 << 2) /* Bit 2: Input 2 0=SSP0 TX 1=Timer 1 match 0 */ +#define SYSCON_DMAREQSEL_INP3 (1 << 3) /* Bit 3: Input 3 0=SSP0 RX 1=Timer 1 match 1 */ +#define SYSCON_DMAREQSEL_INP4 (1 << 4) /* Bit 4: Input 4 0=SSP1 TX 1=Timer 2 match 0 */ +#define SYSCON_DMAREQSEL_INP5 (1 << 5) /* Bit 5: Input 5 0=SSP1 RX 1=Timer 2 match 1 */ +#define SYSCON_DMAREQSEL_INP6 (1 << 6) /* Bit 6: Input 6 0=SSP2 TX 1=I2S0 */ +#define SYSCON_DMAREQSEL_INP7 (1 << 7) /* Bit 7: Input 7 0=SSP2 RX 1=I2S1 */ + /* Bits 8-9: Reserved */ +#define SYSCON_DMAREQSEL_INP10 (1 << 10) /* Bit 10: Input 10 0=UART0 TX 1=UART3 TX */ +#define SYSCON_DMAREQSEL_INP11 (1 << 11) /* Bit 11: Input 11 0=UART0 RX 1=UART3 RX */ +#define SYSCON_DMAREQSEL_INP12 (1 << 12) /* Bit 12: Input 12 0=UART1 TX 1=UART4 TX */ +#define SYSCON_DMAREQSEL_INP13 (1 << 13) /* Bit 13: Input 13 0=UART1 RX 1=UART4 RX */ +#define SYSCON_DMAREQSEL_INP14 (1 << 14) /* Bit 14: Input 14 0=UART2 TX 1=Timer 3 match 0 */ +#define SYSCON_DMAREQSEL_INP15 (1 << 15) /* Bit 15: Input 15 0=UART2 RX 1=Timer 3 match 1 */ + /* Bits 16-31: Reserved */ +/* Reset Control Register 0 */ + +#define SYSCON_RSTCON0_RSTLCD (1 << 0) /* LCD controller reset control bit */ +#define SYSCON_RSTCON0_RSTTIM0 (1 << 1) /* Timer/Counter 0 reset control bit */ +#define SYSCON_RSTCON0_RSTTIM1 (1 << 2) /* Timer/Counter 1 reset control bit */ +#define SYSCON_RSTCON0_RSTUART0 (1 << 3) /* UART0 reset control bit */ +#define SYSCON_RSTCON0_RSTUART1 (1 << 4) /* UART1 reset control bit */ +#define SYSCON_RSTCON0_RSTPWM0 (1 << 5) /* PWM0 reset control bit */ +#define SYSCON_RSTCON0_RSTPWM1 (1 << 6) /* PWM1 reset control bit */ +#define SYSCON_RSTCON0_RSTI2C0 (1 << 7) /* The I2C0 interface reset control bit */ +#define SYSCON_RSTCON0_RSTUART4 (1 << 8) /* UART4 reset control bit */ +#define SYSCON_RSTCON0_RSTRTC (1 << 9) /* RTC and Event Monitor/Recorder reset control bit. RTC reset is limited */ +#define SYSCON_RSTCON0_RSTSSP1 (1 << 10) /* The SSP 1 interface reset control bit */ +#define SYSCON_RSTCON0_RSTEMC (1 << 11) /* External Memory Controller reset control bit */ +#define SYSCON_RSTCON0_RSTADC (1 << 12) /* A/D converter (ADC) reset control bit */ +#define SYSCON_RSTCON0_RSTCAN1 (1 << 13) /* CAN Controller 1 reset control bit */ + /* Note: The CAN acceptance filter may be reset by 0 + * a separate bit in the RSTCON1 register. */ +#define SYSCON_RSTCON0_RSTCAN2 (1 << 14) /* CAN Controller 2 reset control bit */ + /* Note: The CAN acceptance filter may be reset by 0 + * a separate bit in the RSTCON1 register */ +#define SYSCON_RSTCON0_RSTGPIO (1 << 15) /* Reset control bit for GPIO, and GPIO interrupts */ + /* Note: IOCON may be reset by a 0 + * separate bit in the RSTCON1 register */ +#define SYSCON_RSTCON0_RSTSPIFI (1 << 16) /* SPI Flash Interface reset control bit (LPC1773 only) */ +#define SYSCON_RSTCON0_RSTMCPWM (1 << 17) /* Motor Control PWM reset control bit */ +#define SYSCON_RSTCON0_RSTQEI (1 << 18) /* Quadrature Encoder Interface reset control bit */ +#define SYSCON_RSTCON0_RSTI2C1 (1 << 19) /* The I2C1 interface reset control bit */ +#define SYSCON_RSTCON0_RSTSSP2 (1 << 20) /* The SSP2 interface reset control bit */ +#define SYSCON_RSTCON0_RSTSSP0 (1 << 21) /* The SSP0 interface reset control bit */ +#define SYSCON_RSTCON0_RSTTIM2 (1 << 22) /* Timer 2 reset control bit */ +#define SYSCON_RSTCON0_RSTTIM3 (1 << 23) /* Timer 3 reset control bit */ +#define SYSCON_RSTCON0_RSTUART2 (1 << 24) /* UART 2 reset control bit */ +#define SYSCON_RSTCON0_RSTUART3 (1 << 25) /* UART 3 reset control bit */ +#define SYSCON_RSTCON0_RSTI2C2 (1 << 26) /* I2C2 interface reset control bit.*/ +#define SYSCON_RSTCON0_RSTI2S (1 << 27) /* I2S interface reset control bit */ +#define SYSCON_RSTCON0_RSTSDC (1 << 28) /* SD Card interface reset control bit */ +#define SYSCON_RSTCON0_RSTGPDMA (1 << 29) /* GPDMA function reset control bit */ + +#define SYSCON_RSTCON0_RSTENET (1 << 30) /* Ethernet block reset control bit */ +#define SYSCON_RSTCON0_RSTUSB (1 << 31) /* USB interface reset control bit */ + +/* Reset Control Register 1 */ + +#define SYSCON_RSTCON1_RSTIOCON (1 << 0) /* Reset control bit for the IOCON registers */ +#define SYSCON_RSTCON1_RSTDAC (1 << 1) /* D/A converter (DAC) reset control bit */ +#define SYSCON_RSTCON1_RSTCANACC (1 << 2) /* CAN acceptance filter reset control bit */ + /* Bits 3-31: Reserved */ +/* Delay Control Register - EMC */ + /* Delay values multiplied by 250 picoseconds */ +#define SYSCON_EMCDLYCTL_CMDDLY_SHIFT (0) /* Bits 0-4: Delay value for EMC outputs in command delayed mode */ +#define SYSCON_EMCDLYCTL_CMDDLY_MASK (0x1f << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) +# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n+1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 2 - 31 */ + /* Bits 5-7: Reserved */ +#define SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT (8) /* Bits 8-12: Delay value for the feedback clock that controls input data sampling */ +#define SYSCON_EMCDLYCTL_FBCLKDLY_MASK (0x1f << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) +#define SYSCON_EMCDLYCTL_FBCLKDLY(n) ((n+1)<< SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT) /* n = 2 - 31 */ + /* Bits 13-15: Reserved */ +#define SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT (16) /* Bits 16-20: Delay value for the CLKOUT0 output */ +#define SYSCON_EMCDLYCTL_CLKOUT0DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) +# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n+1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 2 - 31 */ + /* Bits 21-23: Reserved */ +#define SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT (24) /* Bits 24-28: Delay value for the CLKOUT1 output */ +#define SYSCON_EMCDLYCTL_CLKOUT1DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) +# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n+1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 2 - 31 */ + /* Bits 29-31: Reserved */ +/* Calibration Register - EMC */ + +#define SYSCON_EMCCAL_CALVALUE_SHIFT (0) /* Bits 0-7: Ring oscillator count during 32 clocks of Internal RC */ +#define SYSCON_EMCCAL_CALVALUE_MASK (0xff << SYSCON_EMCCAL_CALVALUE_SHIFT) +//~ #define SYSCON_EMCCAL_CALVALUE + /* Bits 8-13: Reserved */ +#define SYSCON_EMCCAL_START_SHIFT (14) /* Bit 14: Start control bit for EMC calibration counter */ +#define SYSCON_EMCCAL_START_MASK (1 << SYSCON_EMCCAL_START_SHIFT) +# define SYSCON_EMCCAL_START (1) /* Automatically cleared when measurement is done */ +#define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completetion flag bit */ +#define SYSCON_EMCCAL_DONE_MASK (1 << SYSCON_EMCCAL_DONE_SHIFT) + /* Automatically cleared when START bit is set */ +//~ # define SYSCON_EMCCAL_DONE + /* Bits 16-31: Reserved */ +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h index 20b4ae380..aa5c0f57b 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_gpio.h @@ -57,6 +57,9 @@ #define LPC17_FIO2_OFFSET 0x0040 #define LPC17_FIO3_OFFSET 0x0060 #define LPC17_FIO4_OFFSET 0x0080 +#ifdef LPC178x +# define LPC17_FIO5_OFFSET 0x00a0 +#endif #define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ #define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ @@ -86,6 +89,9 @@ #define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) #define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) #define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) +#ifdef LPC178x +# define LPC17_FIO5_BASE (LPC17_GPIO_BASE+LPC17_FIO5_OFFSET) +#endif #define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) #define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) @@ -123,6 +129,14 @@ #define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) #define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) +#ifdef LPC178x +# define LPC17_FIO5_DIR (LPC17_FIO5_BASE+LPC17_FIO_DIR_OFFSET) +# define LPC17_FIO5_MASK (LPC17_FIO5_BASE+LPC17_FIO_MASK_OFFSET) +# define LPC17_FIO5_PIN (LPC17_FIO5_BASE+LPC17_FIO_PIN_OFFSET) +# define LPC17_FIO5_SET (LPC17_FIO5_BASE+LPC17_FIO_SET_OFFSET) +# define LPC17_FIO5_CLR (LPC17_FIO5_BASE+LPC17_FIO_CLR_OFFSET) +#endif + /* GPIO interrupt block register addresses ******************************************/ #define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) @@ -137,7 +151,7 @@ #define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) #define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) -/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ +/* Pins P0.0-31 */ #define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) #define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) @@ -145,7 +159,7 @@ #define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) #define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) -/* Pins P2.0-13 (P0.14-31 are reserved) */ +/* Pins P2.0-31 */ #define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) #define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) @@ -189,105 +203,8 @@ * Public Data ************************************************************************************/ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - /************************************************************************************ * Public Functions ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void lpc17_gpioirqinitialize(void); -#else -# define lpc17_gpioirqinitialize() -#endif - -/************************************************************************************ - * Name: lpc17_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * - ************************************************************************************/ - -int lpc17_configgpio(uint16_t cfgset); - -/************************************************************************************ - * Name: lpc17_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ************************************************************************************/ - -void lpc17_gpiowrite(uint16_t pinset, bool value); - -/************************************************************************************ - * Name: lpc17_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ************************************************************************************/ - -bool lpc17_gpioread(uint16_t pinset); - -/************************************************************************************ - * Name: lpc17_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void lpc17_gpioirqenable(int irq); -#else -# define lpc17_gpioirqenable(irq) -#endif - -/************************************************************************************ - * Name: lpc17_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void lpc17_gpioirqdisable(int irq); -#else -# define lpc17_gpioirqdisable(irq) -#endif - -/************************************************************************************ - * Function: lpc17_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO -int lpc17_dumpgpio(uint16_t pinset, const char *msg); -#else -# define lpc17_dumpgpio(p,m) -#endif - -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h index 15be1e672..ebe39cb72 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_syscon.h @@ -42,443 +42,20 @@ #include -#include "chip.h" -#include "chip/lpc17_memorymap.h" +#include + +#if defined(LPC176x) +# include "chip/lpc176x_syscon.h" +#elif defined(LPC178x) +# include "chip/lpc178x_syscon.h" +#else +# error "Unrecognized LPC17xx family" +#endif /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG_OFFSET 0x0000 /* Flash Accelerator Configuration Register */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */ - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON_OFFSET 0x0080 /* PLL0 Control Register */ -#define LPC17_SYSCON_PLL0CFG_OFFSET 0x0084 /* PLL0 Configuration Register */ -#define LPC17_SYSCON_PLL0STAT_OFFSET 0x0088 /* PLL0 Status Register */ -#define LPC17_SYSCON_PLL0FEED_OFFSET 0x008c /* PLL0 Feed Register */ - -#define LPC17_SYSCON_PLL1CON_OFFSET 0x00a0 /* PLL1 Control Register */ -#define LPC17_SYSCON_PLL1CFG_OFFSET 0x00a4 /* PLL1 Configuration Register */ -#define LPC17_SYSCON_PLL1STAT_OFFSET 0x00a8 /* PLL1 Status Register */ -#define LPC17_SYSCON_PLL1FEED_OFFSET 0x00ac /* PLL1 Feed Register */ - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON_OFFSET 0x00c0 /* Power Control Register */ -#define LPC17_SYSCON_PCONP_OFFSET 0x00c4 /* Power Control for Peripherals Register */ - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */ -#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */ - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL_OFFSET 0x010c /* Clock Source Select Register */ - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT_OFFSET 0x0140 /* External Interrupt Flag Register */ - -#define LPC17_SYSCON_EXTMODE_OFFSET 0x0148 /* External Interrupt Mode register */ -#define LPC17_SYSCON_EXTPOLAR_OFFSET 0x014c /* External Interrupt Polarity Register */ - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID_OFFSET 0x0180 /* Reset Source Identification Register */ - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS_OFFSET 0x01a0 /* System Control and Status */ - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0_OFFSET 0x01a8 /* Peripheral Clock Selection register 0 */ -#define LPC17_SYSCON_PCLKSEL1_OFFSET 0x01ac /* Peripheral Clock Selection register 1 */ - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST_OFFSET 0x01c0 /* USB Interrupt Status */ - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL_OFFSET 0x01c4 /* Selects between UART and timer DMA requests */ - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG_OFFSET 0x01c8 /* Clock Output Configuration Register */ - -/* Register addresses ***************************************************************/ -/* Flash accelerator module */ - -#define LPC17_SYSCON_FLASHCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_FLASHCFG_OFFSET) - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define LPC17_SYSCON_MEMMAP (LPC17_SYSCON_BASE+LPC17_SYSCON_MEMMAP_OFFSET) - -/* Clocking and power control - Phase locked loops */ - -#define LPC17_SYSCON_PLL0CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CON_OFFSET) -#define LPC17_SYSCON_PLL0CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0CFG_OFFSET) -#define LPC17_SYSCON_PLL0STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0STAT_OFFSET) -#define LPC17_SYSCON_PLL0FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL0FEED_OFFSET) - -#define LPC17_SYSCON_PLL1CON (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CON_OFFSET) -#define LPC17_SYSCON_PLL1CFG (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1CFG_OFFSET) -#define LPC17_SYSCON_PLL1STAT (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1STAT_OFFSET) -#define LPC17_SYSCON_PLL1FEED (LPC17_SYSCON_BASE+LPC17_SYSCON_PLL1FEED_OFFSET) - -/* Clocking and power control - Peripheral power control registers */ - -#define LPC17_SYSCON_PCON (LPC17_SYSCON_BASE+LPC17_SYSCON_PCON_OFFSET) -#define LPC17_SYSCON_PCONP (LPC17_SYSCON_BASE+LPC17_SYSCON_PCONP_OFFSET) - -/* Clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET) -#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET) - -/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */ - -/* Clocking and power control -- Clock source selection */ - -#define LPC17_SYSCON_CLKSRCSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKSRCSEL_OFFSET) - -/* System control registers -- External Interrupts */ - -#define LPC17_SYSCON_EXTINT (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTINT_OFFSET) - -#define LPC17_SYSCON_EXTMODE (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTMODE_OFFSET) -#define LPC17_SYSCON_EXTPOLAR (LPC17_SYSCON_BASE+LPC17_SYSCON_EXTPOLAR_OFFSET) - -/* System control registers -- Reset */ - -#define LPC17_SYSCON_RSID (LPC17_SYSCON_BASE+LPC17_SYSCON_RSID_OFFSET) - -/* System control registers -- Syscon Miscellaneous Registers */ - -#define LPC17_SYSCON_SCS (LPC17_SYSCON_BASE+LPC17_SYSCON_SCS_OFFSET) - -/* More clocking and power control -- Clock dividers */ - -#define LPC17_SYSCON_PCLKSEL0 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL0_OFFSET) -#define LPC17_SYSCON_PCLKSEL1 (LPC17_SYSCON_BASE+LPC17_SYSCON_PCLKSEL1_OFFSET) - -/* Device Interrupt Registers (Might be a error in the User Manual, might be at 0x5000c1c0) */ - -#define LPC17_SYSCON_USBINTST (LPC17_SYSCON_BASE+LPC17_SYSCON_USBINTST_OFFSET) - -/* DMA Request Select Register */ - -#define LPC17_SYSCON_DMAREQSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_DMAREQSEL_OFFSET) - -/* More clocking and power control -- Utility */ - -#define LPC17_SYSCON_CLKOUTCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CLKOUTCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Flash accelerator module */ - /* Bits 0-11: Reserved */ -#define SYSCON_FLASHCFG_TIM_SHIFT (12) /* Bits 12-15: FLASHTIM Flash access time */ -#define SYSCON_FLASHCFG_TIM_MASK (15 << SYSCON_FLASHCFG_TIM_SHIFT) -# define SYSCON_FLASHCFG_TIM_1 (0 << SYSCON_FLASHCFG_TIM_SHIFT) /* 1 CPU clock <= 20 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_2 (1 << SYSCON_FLASHCFG_TIM_SHIFT) /* 2 CPU clock <= 40 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_3 (2 << SYSCON_FLASHCFG_TIM_SHIFT) /* 3 CPU clock <= 60 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_4 (3 << SYSCON_FLASHCFG_TIM_SHIFT) /* 4 CPU clock <= 80 MHz CPU clock */ -# define SYSCON_FLASHCFG_TIM_5 (4 << SYSCON_FLASHCFG_TIM_SHIFT) /* 5 CPU clock <= 100 MHz CPU clock - * (Up to 120 Mhz for LPC1759/69 only */ -# define SYSCON_FLASHCFG_TIM_6 (5 << SYSCON_FLASHCFG_TIM_SHIFT) /* "safe" setting for any conditions */ - /* Bits 16-31: Reserved */ - -/* Memory Mapping Control register (MEMMAP - 0x400F C040) */ - -#define SYSCON_MEMMAP_MAP (1 << 0) /* Bit 0: - * 0:Boot mode. A portion of the Boot ROM is mapped to address 0. - * 1:User mode. The on-chip Flash memory is mapped to address 0 */ - /* Bits 1-31: Reserved */ - -/* Clocking and power control -- Clock source selection */ - -#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */ -#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT) -# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */ -# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */ -# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */ - /* Bits 2-31: Reserved */ - -/* Clocking and power control - Phase locked loops */ -/* PLL0/1 Control register */ - -#define SYSCON_PLLCON_PLLE (1 << 0) /* Bit 0: PLL0/1 Enable */ -#define SYSCON_PLLCON_PLLC (1 << 1) /* Bit 1: PLL0/1 Connect */ - /* Bits 2-31: Reserved */ -/* PLL0 Configuration register */ - -#define SYSCON_PLL0CFG_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value */ -#define SYSCON_PLL0CFG_MSEL_MASK (0x7fff << SYSCON_PLL0CFG_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0CFG_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value */ -#define SYSCON_PLL0CFG_NSEL_MASK (0xff << SYSCON_PLL0CFG_NSEL_SHIFT) - /* Bits 24-31: Reserved */ -/* PLL1 Configuration register */ - -#define SYSCON_PLL1CFG_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value */ -#define SYSCON_PLL1CFG_MSEL_MASK (0x1f < SYSCON_PLL1CFG_MSEL_SHIFT) -#define SYSCON_PLL1CFG_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value */ -#define SYSCON_PLL1CFG_NSEL_MASK (3 << SYSCON_PLL1CFG_NSEL_SHIFT) - /* Bits 7-31: Reserved */ -/* PLL0 Status register */ - -#define SYSCON_PLL0STAT_MSEL_SHIFT (0) /* Bit 0-14: PLL0 Multiplier value readback */ -#define SYSCON_PLL0STAT_MSEL_MASK (0x7fff << SYSCON_PLL0STAT_MSEL_SHIFT) - /* Bit 15: Reserved */ -#define SYSCON_PLL0STAT_NSEL_SHIFT (16) /* Bit 16-23: PLL0 Pre-Divider value readback */ -#define SYSCON_PLL0STAT_NSEL_MASK (0xff << SYSCON_PLL0STAT_NSEL_SHIFT) -#define SYSCON_PLL0STAT_PLLE (1 << 24) /* Bit 24: PLL0 enable readback */ -#define SYSCON_PLL0STAT_PLLC (1 << 25) /* Bit 25: PLL0 connect readback */ -#define SYSCON_PLL0STAT_PLOCK (1 << 26) /* Bit 26: PLL0 lock status */ - /* Bits 27-31: Reserved */ -/* PLL1 Status register */ - -#define SYSCON_PLL1STAT_MSEL_SHIFT (0) /* Bit 0-4: PLL1 Multiplier value readback */ -#define SYSCON_PLL1STAT_MSEL_MASK (0x1f << SYSCON_PLL1STAT_MSEL_SHIFT) -#define SYSCON_PLL1STAT_NSEL_SHIFT (5) /* Bit 5-6: PLL1 Pre-Divider value readback */ -#define SYSCON_PLL1STAT_NSEL_MASK (3 << SYSCON_PLL1STAT_NSEL_SHIFT) - /* Bit 7: Reserved */ -#define SYSCON_PLL1STAT_PLLE (1 << 8) /* Bit 8: PLL1 enable readback */ -#define SYSCON_PLL1STAT_PLLC (1 << 9) /* Bit 9: PLL1 connect readback */ -#define SYSCON_PLL1STAT_PLOCK (1 << 10) /* Bit 10: PLL1 lock status */ - /* Bits 11-31: Reserved */ -/* PLL0/1 Feed register */ - -#define SYSCON_PLLFEED_SHIFT (0) /* Bit 0-7: PLL0/1 feed sequence */ -#define SYSCON_PLLFEED_MASK (0xff << SYSCON_PLLFEED_SHIFT) - /* Bits 8-31: Reserved */ -/* Clocking and power control -- Clock dividers */ -/* CPU Clock Configuration register */ - -#define SYSCON_CCLKCFG_SHIFT (0) /* 0-7: Divide value for CPU clock (CCLK) */ -#define SYSCON_CCLKCFG_MASK (0xff << SYSCON_CCLKCFG_SHIFT) -# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ - /* Bits 8-31: Reserved */ -/* USB Clock Configuration register */ - -#define SYSCON_USBCLKCFG_SHIFT (0) /* Bits 0-3: PLL0 divide value USB clock */ -#define SYSCON_USBCLKCFG_MASK (15 << SYSCON_USBCLKCFG_SHIFT) -# define SYSCON_USBCLKCFG_DIV6 (5 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/6 for PLL0=288 MHz */ -# define SYSCON_USBCLKCFG_DIV8 (7 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/8 for PLL0=384 MHz */ -# define SYSCON_USBCLKCFG_DIV10 (9 << SYSCON_USBCLKCFG_SHIFT) /* PLL0/10 for PLL0=480 MHz */ - /* Bits 8-31: Reserved */ -/* Peripheral Clock Selection registers 0 and 1 */ - -#define SYSCON_PCLKSEL_CCLK4 (0) /* PCLK_peripheral = CCLK/4 */ -#define SYSCON_PCLKSEL_CCLK (1) /* PCLK_peripheral = CCLK */ -#define SYSCON_PCLKSEL_CCLK2 (2) /* PCLK_peripheral = CCLK/2 */ -#define SYSCON_PCLKSEL_CCLK8 (3) /* PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_CCLK6 (3) /* PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN) */ -#define SYSCON_PCLKSEL_MASK (3) - -#define SYSCON_PCLKSEL0_WDT_SHIFT (0) /* Bits 0-1: Peripheral clock WDT */ -#define SYSCON_PCLKSEL0_WDT_MASK (3 << SYSCON_PCLKSEL0_WDT_SHIFT) -#define SYSCON_PCLKSEL0_TMR0_SHIFT (2) /* Bits 2-3: Peripheral clock TIMER0 */ -#define SYSCON_PCLKSEL0_TMR0_MASK (3 << SYSCON_PCLKSEL0_TMR0_SHIFT) -#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */ -#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT) -#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */ -#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT) -#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */ -#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT) - /* Bits 10-11: Reserved */ -#define SYSCON_PCLKSEL0_PWM1_SHIFT (12) /* Bits 12-13: Peripheral clock PWM1 */ -#define SYSCON_PCLKSEL0_PWM1_MASK (3 << SYSCON_PCLKSEL0_PWM1_SHIFT) -#define SYSCON_PCLKSEL0_I2C0_SHIFT (14) /* Bits 14-15: Peripheral clock I2C0 */ -#define SYSCON_PCLKSEL0_I2C0_MASK (3 << SYSCON_PCLKSEL0_I2C0_SHIFT) -#define SYSCON_PCLKSEL0_SPI_SHIFT (16) /* Bits 16-17: Peripheral clock SPI */ -#define SYSCON_PCLKSEL0_SPI_MASK (3 << SYSCON_PCLKSEL0_SPI_SHIFT) - /* Bits 18-19: Reserved */ -#define SYSCON_PCLKSEL0_SSP1_SHIFT (20) /* Bits 20-21: Peripheral clock SSP1 */ -#define SYSCON_PCLKSEL0_SSP1_MASK (3 << SYSCON_PCLKSEL0_SSP1_SHIFT) -#define SYSCON_PCLKSEL0_DAC_SHIFT (22) /* Bits 22-23: Peripheral clock DAC */ -#define SYSCON_PCLKSEL0_DAC_MASK (3 << SYSCON_PCLKSEL0_DAC_SHIFT) -#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */ -#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT) -#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */ -#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT) -#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */ -#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT) -#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */ -#define SYSCON_PCLKSEL0_ACF_MASK (3 << SYSCON_PCLKSEL0_ACF_SHIFT) - -#define SYSCON_PCLKSEL1_QEI_SHIFT (0) /* Bits 0-1: Peripheral clock Quadrature Encoder */ -#define SYSCON_PCLKSEL1_QEI_MASK (3 << SYSCON_PCLKSEL1_QEI_SHIFT) -#define SYSCON_PCLKSEL1_GPIOINT_SHIFT (2) /* Bits 2-3: Peripheral clock GPIO interrupts */ -#define SYSCON_PCLKSEL1_GPIOINT_MASK (3 << SYSCON_PCLKSEL1_GPIOINT_SHIFT) -#define SYSCON_PCLKSEL1_PCB_SHIFT (4) /* Bits 4-5: Peripheral clock the Pin Connect block */ -#define SYSCON_PCLKSEL1_PCB_MASK (3 << SYSCON_PCLKSEL1_PCB_SHIFT) -#define SYSCON_PCLKSEL1_I2C1_SHIFT (6) /* Bits 6-7: Peripheral clock I2C1 */ -#define SYSCON_PCLKSEL1_I2C1_MASK (3 << SYSCON_PCLKSEL1_I2C1_SHIFT) - /* Bits 8-9: Reserved */ -#define SYSCON_PCLKSEL1_SSP0_SHIFT (10) /* Bits 10-11: Peripheral clock SSP0 */ -#define SYSCON_PCLKSEL1_SSP0_MASK (3 << SYSCON_PCLKSEL1_SSP0_SHIFT) -#define SYSCON_PCLKSEL1_TMR2_SHIFT (12) /* Bits 12-13: Peripheral clock TIMER2 */ -#define SYSCON_PCLKSEL1_TMR2_MASK (3 << SYSCON_PCLKSEL1_TMR2_SHIFT) -#define SYSCON_PCLKSEL1_TMR3_SHIFT (14) /* Bits 14-15: Peripheral clock TIMER3 */ -#define SYSCON_PCLKSEL1_TMR3_MASK (3 << SYSCON_PCLKSEL1_TMR3_SHIFT) -#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */ -#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT) -#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */ -#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT) -#define SYSCON_PCLKSEL1_I2C2_SHIFT (20) /* Bits 20-21: Peripheral clock I2C2 */ -#define SYSCON_PCLKSEL1_I2C2_MASK (3 << SYSCON_PCLKSEL1_I2C2_SHIFT) -#define SYSCON_PCLKSEL1_I2S_SHIFT (22) /* Bits 22-23: Peripheral clock I2S */ -#define SYSCON_PCLKSEL1_I2S_MASK (3 << SYSCON_PCLKSEL1_I2S_SHIFT) - /* Bits 24-25: Reserved */ -#define SYSCON_PCLKSEL1_RIT_SHIFT (26) /* Bits 26-27: Peripheral clock Repetitive Interrupt Timer */ -#define SYSCON_PCLKSEL1_RIT_MASK (3 << SYSCON_PCLKSEL1_RIT_SHIFT) -#define SYSCON_PCLKSEL1_SYSCON_SHIFT (28) /* Bits 28-29: Peripheral clock the System Control block */ -#define SYSCON_PCLKSEL1_SYSCON_MASK (3 << SYSCON_PCLKSEL1_SYSCON_SHIFT) -#define SYSCON_PCLKSEL1_MC_SHIFT (30) /* Bits 30-31: Peripheral clock the Motor Control PWM */ -#define SYSCON_PCLKSEL1_MC_MASK (3 << SYSCON_PCLKSEL1_MC_SHIFT) - -/* Clocking and power control - Peripheral power control registers */ -/* Power Control Register */ - -#define SYSCON_PCON_PM0 (1 << 0) /* Bit 0: Power mode control bit 0 */ -#define SYSCON_PCON_PM1 (1 << 1) /* Bit 1: Power mode control bit 1 */ -#define SYSCON_PCON_BODRPM (1 << 2) /* Bit 2: Brown-Out Reduced Power Mode */ -#define SYSCON_PCON_BOGD (1 << 3) /* Bit 3: Brown-Out Global Disable */ -#define SYSCON_PCON_BORD (1 << 4) /* Bit 4: Brown-Out Reset Disable */ - /* Bits 5-7: Reserved */ -#define SYSCON_PCON_SMFLAG (1 << 8) /* Bit 8: Sleep Mode entry flag */ -#define SYSCON_PCON_DSFLAG (1 << 9) /* Bit 9: Deep Sleep entry flag */ -#define SYSCON_PCON_PDFLAG (1 << 10) /* Bit 10: Power-down entry flag */ -#define SYSCON_PCON_DPDFLAG (1 << 11) /* Bit 11: Deep Power-down entry flag */ - /* Bits 12-31: Reserved */ -/* Power Control for Peripherals Register */ - - /* Bit 0: Reserved */ -#define SYSCON_PCONP_PCTIM0 (1 << 1) /* Bit 1: Timer/Counter 0 power/clock control */ -#define SYSCON_PCONP_PCTIM1 (1 << 2) /* Bit 2: Timer/Counter 1 power/clock control */ -#define SYSCON_PCONP_PCUART0 (1 << 3) /* Bit 3: UART0 power/clock control */ -#define SYSCON_PCONP_PCUART1 (1 << 4) /* Bit 4: UART1 power/clock control */ - /* Bit 5: Reserved */ -#define SYSCON_PCONP_PCPWM1 (1 << 6) /* Bit 6: PWM1 power/clock control */ -#define SYSCON_PCONP_PCI2C0 (1 << 7) /* Bit 7: I2C0 power/clock control */ -#define SYSCON_PCONP_PCSPI (1 << 8) /* Bit 8: SPI power/clock control */ -#define SYSCON_PCONP_PCRTC (1 << 9) /* Bit 9: RTC power/clock control */ -#define SYSCON_PCONP_PCSSP1 (1 << 10) /* Bit 10: SSP 1 power/clock control */ - /* Bit 11: Reserved */ -#define SYSCON_PCONP_PCADC (1 << 12) /* Bit 12: A/D converter (ADC) power/clock control */ -#define SYSCON_PCONP_PCCAN1 (1 << 13) /* Bit 13: CAN Controller 1 power/clock control */ -#define SYSCON_PCONP_PCCAN2 (1 << 14) /* Bit 14: CAN Controller 2 power/clock control */ -#define SYSCON_PCONP_PCGPIO (1 << 15) /* Bit 15: GPIOs power/clock enable */ -#define SYSCON_PCONP_PCRIT (1 << 16) /* Bit 16: Repetitive Interrupt Timer power/clock control */ -#define SYSCON_PCONP_PCMCPWM (1 << 17) /* Bit 17: Motor Control PWM */ -#define SYSCON_PCONP_PCQEI (1 << 18) /* Bit 18: Quadrature Encoder power/clock control */ -#define SYSCON_PCONP_PCI2C1 (1 << 19) /* Bit 19: I2C1 power/clock control */ - /* Bit 20: Reserved */ -#define SYSCON_PCONP_PCSSP0 (1 << 21) /* Bit 21: SSP0 power/clock control */ -#define SYSCON_PCONP_PCTIM2 (1 << 22) /* Bit 22: Timer 2 power/clock control */ -#define SYSCON_PCONP_PCTIM3 (1 << 23) /* Bit 23: Timer 3 power/clock control */ -#define SYSCON_PCONP_PCUART2 (1 << 24) /* Bit 24: UART 2 power/clock control */ -#define SYSCON_PCONP_PCUART3 (1 << 25) /* Bit 25: UART 3 power/clock control */ -#define SYSCON_PCONP_PCI2C2 (1 << 26) /* Bit 26: I2C 2 power/clock control */ -#define SYSCON_PCONP_PCI2S (1 << 27) /* Bit 27: I2S power/clock control */ - /* Bit 28: Reserved */ -#define SYSCON_PCONP_PCGPDMA (1 << 29) /* Bit 29: GPDMA function power/clock control */ -#define SYSCON_PCONP_PCENET (1 << 30) /* Bit 30: Ethernet block power/clock control */ -#define SYSCON_PCONP_PCUSB (1 << 31) /* Bit 31: USB power/clock control */ - -/* More clocking and power control -- Utility */ - -#define SYSCON_CLKOUTCFG_SEL_SHIFT (0) /* Bits 0-3: Selects clock source for CLKOUT */ -#define SYSCON_CLKOUTCFG_SEL_MASK (15 << SYSCON_CLKOUTCFG_SEL_SHIFT) -# define SYSCON_CLKOUTCFG_SEL_CPU (0 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=CPU clock */ -# define SYSCON_CLKOUTCFG_SEL_MAIN (1 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=main osc */ -# define SYSCON_CLKOUTCFG_SEL_INTRC (2 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=internal RC osc */ -# define SYSCON_CLKOUTCFG_SEL_USB (3 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=USB clock */ -# define SYSCON_CLKOUTCFG_SEL_RTC (4 << SYSCON_CLKOUTCFG_SEL_SHIFT) /* CLKOUT source=RTC osc */ -#define SYSCON_CLKOUTCFG_DIV_SHIFT (4) /* Bits 4-7: CLKOUT divisor */ -#define SYSCON_CLKOUTCFG_DIV_MASK (15 << SYSCON_CLKOUTCFG_DIV_SHIFT) -# define SYSCON_CLKOUTCFG_DIV(n) ((n-1) << SYSCON_CLKOUTCFG_DIV_SHIFT) /* n=1..16 */ -#define SYSCON_CLKOUTCFG_EN (1 << 8) /* Bit 8: CLKOUT enable control */ -#define SYSCON_CLKOUTCFG_ACT (1 << 9) /* Bit 9: CLKOUT activity indication */ - /* Bits 10-31: Reserved */ -/* System control registers -- External Interrupts */ -/* External Interrupt Flag register */ - -#define SYSCON_EXTINT_EINT0 (1 << 0) /* Bit 0: EINT0 */ -#define SYSCON_EXTINT_EINT1 (1 << 1) /* Bit 1: EINT1 */ -#define SYSCON_EXTINT_EINT2 (1 << 2) /* Bit 2: EINT2 */ -#define SYSCON_EXTINT_EINT3 (1 << 3) /* Bit 3: EINT3 */ - /* Bits 4-31: Reserved */ -/* External Interrupt Mode register */ - -#define SYSCON_EXTMODE_EINT0 (1 << 0) /* Bit 0: 1=EINT0 edge sensitive */ -#define SYSCON_EXTMODE_EINT1 (1 << 1) /* Bit 1: 1=EINT1 edge sensitive */ -#define SYSCON_EXTMODE_EINT2 (1 << 2) /* Bit 2: 1=EINT2 edge sensitive */ -#define SYSCON_EXTMODE_EINT3 (1 << 3) /* Bit 3: 1=EINT3 edge sensitive */ - /* Bits 4-31: Reserved */ -/* External Interrupt Polarity register */ - -#define SYSCON_EXTPOLAR_EINT0 (1 << 0) /* Bit 0: 1=EINT0 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT1 (1 << 1) /* Bit 1: 1=EINT1 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT2 (1 << 2) /* Bit 2: 1=EINT2 high active/rising edge */ -#define SYSCON_EXTPOLAR_EINT3 (1 << 3) /* Bit 3: 1=EINT3 high active/rising edge */ - /* Bits 4-31: Reserved */ -/* System control registers -- Reset */ -/* Reset Source Identification Register */ - -#define SYSCON_RSID_POR (1 << 0) /* Bit 0: Power on reset */ -#define SYSCON_RSID_EXTR (1 << 1) /* Bit 1: external RESET signal */ -#define SYSCON_RSID_WDTR (1 << 2) /* Bit 2: Watchdog Timer time out w/WDTRESET */ -#define SYSCON_RSID_BODR (1 << 3) /* Bit 3: Brown out detection */ - /* Bits 4-31: Reserved */ -/* System control registers -- Syscon Miscellaneous Registers */ - - /* Bits 0-3: Reserved */ -#define SYSCON_SCS_OSCRANGE (1 << 4) /* Bit 4: Main oscillator range select */ -#define SYSCON_SCS_OSCEN (1 << 5) /* Bit 5: Main oscillator enable */ -#define SYSCON_SCS_OSCSTAT (1 << 6) /* Bit 6: Main oscillator status */ - /* Bits 7-31: Reserved */ -/* Device Interrupt Registers */ -/* USB Interrupt Status register */ - -#define SYSCON_USBINTST_REQLP (1 << 0) /* Bit 0: Low priority interrupt line status */ -#define SYSCON_USBINTST_REQHP (1 << 1) /* Bit 1: High priority interrupt line status */ -#define SYSCON_USBINTST_REQDMA (1 << 2) /* Bit 2: DMA interrupt line status */ -#define SYSCON_USBINTST_HOSTINT (1 << 3) /* Bit 3: USB host interrupt line status */ -#define SYSCON_USBINTST_ATXINT (1 << 4) /* Bit 4: External ATX interrupt line status */ -#define SYSCON_USBINTST_OTGINT (1 << 5) /* Bit 5: OTG interrupt line status */ -#define SYSCON_USBINTST_I2CINT (1 << 6) /* Bit 6: I2C module interrupt line status */ - /* Bit 7: Reserved */ -#define SYSCON_USBINTST_NEEDCLK (1 << 8) /* Bit 8: USB need clock indicator */ - /* Bits 9-30: Reserved */ -#define SYSCON_USBINTST_ENINTS (1 << 31) /* Bit 31: Enable all USB interrupts */ - -/* DMA Request Select Register */ - -#define SYSCON_DMAREQSEL_INP8 (1 << 0) /* Bit 0: Input 8 0=UART0 TX 1=Timer 0 match 0 */ -#define SYSCON_DMAREQSEL_INP9 (1 << 1) /* Bit 1: Input 8 0=UART0 RX 1=Timer 0 match 1 */ -#define SYSCON_DMAREQSEL_INP10 (1 << 2) /* Bit 2: Input 8 0=UART1 TX 1=Timer 1 match 0 */ -#define SYSCON_DMAREQSEL_INP11 (1 << 3) /* Bit 3: Input 8 0=UART1 RX 1=Timer 1 match 1 */ -#define SYSCON_DMAREQSEL_INP12 (1 << 4) /* Bit 4: Input 8 0=UART2 TX 1=Timer 2 match 0 */ -#define SYSCON_DMAREQSEL_INP13 (1 << 5) /* Bit 5: Input 8 0=UART2 RX 1=Timer 2 match 1 */ -#define SYSCON_DMAREQSEL_INP14 (1 << 6) /* Bit 6: Input 8 0=UART3 TX 1=Timer 3 match 0 */ -#define SYSCON_DMAREQSEL_INP15 (1 << 7) /* Bit 7: Input 8 0=UART3 RX 1=Timer 3 match 1 */ - /* Bits 8-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c index 9db9b136b..73939a389 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c @@ -212,7 +212,7 @@ static int lpc17_pinsel(unsigned int port, unsigned int pin, unsigned int value) * ****************************************************************************/ -static int lpc17_pullup(uint16_t cfgset, unsigned int port, unsigned int pin) +static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin) { const uint32_t *table; uint32_t regaddr; @@ -355,7 +355,7 @@ static void lpc17_clropendrain(unsigned int port, unsigned int pin) * ****************************************************************************/ -static inline int lpc17_configinput(uint16_t cfgset, unsigned int port, unsigned int pin) +static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t regval; uint32_t fiobase; @@ -419,7 +419,7 @@ static inline int lpc17_configinput(uint16_t cfgset, unsigned int port, unsigned * ****************************************************************************/ -static inline int lpc17_configinterrupt(uint16_t cfgset, unsigned int port, +static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin) { /* First, configure the port as a generic input so that we have a known @@ -445,7 +445,7 @@ static inline int lpc17_configinterrupt(uint16_t cfgset, unsigned int port, * ****************************************************************************/ -static inline int lpc17_configoutput(uint16_t cfgset, unsigned int port, +static inline int lpc17_configoutput(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin) { uint32_t fiobase; @@ -494,7 +494,7 @@ static inline int lpc17_configoutput(uint16_t cfgset, unsigned int port, * ****************************************************************************/ -static int lpc17_configalternate(uint16_t cfgset, unsigned int port, +static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port, unsigned int pin, uint32_t alt) { /* First, configure the port as an input so that we have a known @@ -536,7 +536,7 @@ static int lpc17_configalternate(uint16_t cfgset, unsigned int port, * ****************************************************************************/ -int lpc17_configgpio(uint16_t cfgset) +int lpc17_configgpio(lpc17_pinset_t cfgset) { unsigned int port; unsigned int pin; @@ -597,7 +597,7 @@ int lpc17_configgpio(uint16_t cfgset) * ****************************************************************************/ -void lpc17_gpiowrite(uint16_t pinset, bool value) +void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value) { uint32_t fiobase; uint32_t offset; @@ -637,7 +637,7 @@ void lpc17_gpiowrite(uint16_t pinset, bool value) * ****************************************************************************/ -bool lpc17_gpioread(uint16_t pinset) +bool lpc17_gpioread(lpc17_pinset_t pinset) { uint32_t fiobase; unsigned int port; diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h index dad14bc9e..f3a003255 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -46,6 +46,8 @@ # include #endif +#include + #include "chip/lpc17_gpio.h" #include "chip/lpc17_pinconn.h" #include "chip/lpc17_pinconfig.h" @@ -55,6 +57,8 @@ ************************************************************************************/ /* Bit-encoded input to lpc17_configgpio() ******************************************/ +#if defined(LPC176x) + /* Encoding: FFFx MMOV PPPN NNNN * * Pin Function: FFF @@ -165,10 +169,153 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) +#elif defined(LPC178x) + +/* Encoding: TT FFFF MMOV PPPN NNNN + Encoding: TTTT TTTT FFFF MMOV PPPN NNNN + */ +/* Encoding: FFFF MMOV PPPN NNNN + * + * Pin Function: FFFF + * Pin Mode bits: MM + * Open drain: O (output pins) + * Initial value: V (output pins) + * Port number: PPP (0-4) + * Pin number: NNNNN (0-31) + */ + +/* Pin Function bits: FFFF + * Only meaningful when the GPIO function is GPIO_PIN + */ + +#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */ +#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */ +# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */ +# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */ +# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */ +# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */ +# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */ + +# define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */ +# define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */ +# define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */ +# define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */ + +/* Options for each IOCON Types */ +//~ #define GPIO_TYPE_SHIFT (16) +//~ #define GPIO_TYPE_MASK (3 << GPIO_TYPE_SHIFT) +//~ # define GPIO_HYSTERIS (<< 0 << ) +//~ # define GPIO_INVERTED (<< 1 << ) +//~ # define GPIO_SLEW (<< 2 << ) +//~ # define GPIO_ADMODE (<< 3 << ) +//~ # define GPIO_FILTER (<< 4 << ) +//~ # define GPIO_DACEN (<< 5 << ) +//~ # define GPIO_I2CHS (<< 6 << ) +//~ # define GPIO_HIDRIVE (<< 7 << ) + +#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) + +#define GPIO_INOUT_MASK GPIO_OUTPUT +#define GPIO_FE_MASK GPIO_INTFE +#define GPIO_RE_MASK GPIO_INTRE + +#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT) +#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT) +#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) +#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) +#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) +#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) +#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) +#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) +#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) + +/* Pin Mode: MM */ + +#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */ +#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) +# define GPIO_PULLUP (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ +# define GPIO_REPEATER (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ +# define GPIO_FLOAT (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDN (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */ + +/* Open drain: O */ + +#define GPIO_OPEN_DRAIN (1 << 9) /* Bit 9: Open drain mode */ + +/* Initial value: V */ + +#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ +#define GPIO_VALUE_ONE GPIO_VALUE +#define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-5) */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) + +#define GPIO_NPORTS 6 + +/* Pin number: NNNNN (0-31) */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +#else +# error "Unrecognized LPC17xx family" +#endif + /************************************************************************************ * Public Types ************************************************************************************/ +#ifdef LPC176x +typedef uint16_t lpc17_pinset_t; +#else +typedef uint32_t lpc17_pinset_t; +#endif + /************************************************************************************ * Public Data ************************************************************************************/ @@ -204,6 +351,92 @@ EXTERN const uint32_t g_odmode[GPIO_NPORTS]; * Public Functions ****************************************************************************/ +/************************************************************************************ + * Name: lpc17_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqinitialize(void); +#else +# define lpc17_gpioirqinitialize() +#endif + +/************************************************************************************ + * Name: lpc17_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int lpc17_configgpio(lpc17_pinset_t cfgset); + +/************************************************************************************ + * Name: lpc17_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void lpc17_gpiowrite(lpc17_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: lpc17_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool lpc17_gpioread(lpc17_pinset_t pinset); + +/************************************************************************************ + * Name: lpc17_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqenable(int irq); +#else +# define lpc17_gpioirqenable(irq) +#endif + +/************************************************************************************ + * Name: lpc17_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc17_gpioirqdisable(int irq); +#else +# define lpc17_gpioirqdisable(irq) +#endif + +/************************************************************************************ + * Function: lpc17_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg); +#else +# define lpc17_dumpgpio(p,m) +#endif + #ifdef __cplusplus } #endif -- cgit v1.2.3 From eb1e5b46af1a5161017553941970163995e00505 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 21:05:17 +0000 Subject: Add vectors for the LPC1788 - from Rommel Marcelo git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5536 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h | 2 +- nuttx/arch/arm/src/lpc17xx/chip/lpc176x_vectors.h | 110 ++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc178x_vectors.h | 117 ++++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S | 101 ++++++------------- 4 files changed, 258 insertions(+), 72 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc176x_vectors.h create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc178x_vectors.h diff --git a/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h index 9f7cbf9a7..65738e1c7 100644 --- a/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h +++ b/nuttx/arch/arm/include/lpc17xx/lpc178x_irq.h @@ -95,7 +95,7 @@ #define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */ #define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */ #define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */ -/* (LPC17_IRQ_EXTINT+13) Unused */ +#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */ #define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0 * Rx FIFO half full of SSP0 * Rx Timeout of SSP0 diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_vectors.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_vectors.h new file mode 100644 index 000000000..d6320bd12 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_vectors.h @@ -0,0 +1,110 @@ +/******************************************************************************** + * arch/arm/src/lpc17xx/chip/lpc176x_vectors.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************/ + +/******************************************************************************** + * Included Files + ********************************************************************************/ + +/******************************************************************************** + * Preprocessor Definitions + ********************************************************************************/ +/* This file is included by lpc17_vectors.S. It provides the macro VECTOR that + * supplies each LPC17xx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/lpc17/lpc17xx_irq.h. + * lpc17_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 35 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 35 + +#else + +VECTOR(lpc17_wdt, LPC17_IRQ_WDT) /* Vector 16+0: Watchdog timer */ +VECTOR(lpc17_tmr0, LPC17_IRQ_TMR0) /* Vector 16+1: Timer 0 */ +VECTOR(lpc17_tmr1, LPC17_IRQ_TMR1) /* Vector 16+2: Timer 1 */ +VECTOR(lpc17_tmr2, LPC17_IRQ_TMR2) /* Vector 16+3: Timer 2 */ +VECTOR(lpc17_tmr3, LPC17_IRQ_TMR3) /* Vector 16+4: Timer 3 */ +VECTOR(lpc17_uart0, LPC17_IRQ_UART0) /* Vector 16+5: UART 0 */ +VECTOR(lpc17_uart1, LPC17_IRQ_UART1) /* Vector 16+6: UART 1 */ +VECTOR(lpc17_uart2, LPC17_IRQ_UART2) /* Vector 16+7: UART 2 */ +VECTOR(lpc17_uart3, LPC17_IRQ_UART3) /* Vector 16+8: UART 3 */ +VECTOR(lpc17_pwm1, LPC17_IRQ_PWM1) /* Vector 16+9: PWM 1 */ +VECTOR(lpc17_i2c0, LPC17_IRQ_I2C0) /* Vector 16+10: I2C 0 */ +VECTOR(lpc17_i2c1, LPC17_IRQ_I2C1) /* Vector 16+11: I2C 1 */ +VECTOR(lpc17_i2c2, LPC17_IRQ_I2C2) /* Vector 16+12: I2C 2 */ +VECTOR(lpc17_spif, LPC17_IRQ_SPIF) /* Vector 16+13: SPI */ +VECTOR(lpc17_ssp0, LPC17_IRQ_SSP0) /* Vector 16+14: SSP 0 */ +VECTOR(lpc17_ssp1, LPC17_IRQ_SSP1) /* Vector 16+15: SSP 1 */ +VECTOR(lpc17_pll0, LPC17_IRQ_PLL0) /* Vector 16+16: PLL 0 */ +VECTOR(lpc17_rtc, LPC17_IRQ_RTC) /* Vector 16+17: Real time clock */ +VECTOR(lpc17_eint0, LPC17_IRQ_EINT0) /* Vector 16+18: External interrupt 0 */ +VECTOR(lpc17_eint1, LPC17_IRQ_EINT1) /* Vector 16+19: External interrupt 1 */ +VECTOR(lpc17_eint2, LPC17_IRQ_EINT2) /* Vector 16+20: External interrupt 2 */ +VECTOR(lpc17_eint3, LPC17_IRQ_EINT3) /* Vector 16+21: External interrupt 3 */ +VECTOR(lpc17_adc, LPC17_IRQ_ADC) /* Vector 16+22: A/D Converter */ +VECTOR(lpc17_bod, LPC17_IRQ_BOD) /* Vector 16+23: Brown Out detect */ +VECTOR(lpc17_usb, LPC17_IRQ_USB) /* Vector 16+24: USB */ +VECTOR(lpc17_can, LPC17_IRQ_CAN) /* Vector 16+25: CAN */ +VECTOR(lpc17_gpdma, LPC17_IRQ_GPDMA) /* Vector 16+26: GPDMA */ +VECTOR(lpc17_i2s, LPC17_IRQ_I2S) /* Vector 16+27: I2S */ +VECTOR(lpc17_eth, LPC17_IRQ_ETH) /* Vector 16+28: Ethernet */ +VECTOR(lpc17_ritint, LPC17_IRQ_RITINT) /* Vector 16+29: Repetitive Interrupt Timer */ +VECTOR(lpc17_mcpwm, LPC17_IRQ_MCPWM) /* Vector 16+30: Motor Control PWM */ +VECTOR(lpc17_qei, LPC17_IRQ_QEI) /* Vector 16+31: Quadrature Encoder */ +VECTOR(lpc17_pll1, LPC17_IRQ_PLL1) /* Vector 16+32: PLL 1 */ +VECTOR(lpc17_usbact, LPC17_IRQ_USBACT) /* Vector 16+33: USB Activity Interrupt */ +VECTOR(lpc17_canact, LPC17_IRQ_CANACT) /* Vector 16+34: CAN Activity Interrupt */ + +#endif + +/******************************************************************************** + * Public Types + ********************************************************************************/ + +/******************************************************************************** + * Public Data + ********************************************************************************/ + +/******************************************************************************** + * Public Function Prototypes + ********************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_vectors.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_vectors.h new file mode 100644 index 000000000..001cc7690 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_vectors.h @@ -0,0 +1,117 @@ +/************************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc178x_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************/ + +/******************************************************************************** + * Included Files + ********************************************************************************/ + +/********************************************************************************* + * Preprocessor Definitions + ********************************************************************************/ +/* This file is included by lpc17_vectors.S. It provides the macro VECTOR that + * supplies each LPC17xx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/lpc17/lpc17xx_irq.h. + * lpc17_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 41 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 41 + +#else + +VECTOR(lpc17_wdt, LPC17_IRQ_WDT) /* Vector 16+0: Watchdog timer */ +VECTOR(lpc17_tmr0, LPC17_IRQ_TMR0) /* Vector 16+1: Timer 0 */ +VECTOR(lpc17_tmr1, LPC17_IRQ_TMR1) /* Vector 16+2: Timer 1 */ +VECTOR(lpc17_tmr2, LPC17_IRQ_TMR2) /* Vector 16+3: Timer 2 */ +VECTOR(lpc17_tmr3, LPC17_IRQ_TMR3) /* Vector 16+4: Timer 3 */ +VECTOR(lpc17_uart0, LPC17_IRQ_UART0) /* Vector 16+5: UART 0 */ +VECTOR(lpc17_uart1, LPC17_IRQ_UART1) /* Vector 16+6: UART 1 */ +VECTOR(lpc17_uart2, LPC17_IRQ_UART2) /* Vector 16+7: UART 2 */ +VECTOR(lpc17_uart3, LPC17_IRQ_UART3) /* Vector 16+8: UART 3 */ +VECTOR(lpc17_pwm1, LPC17_IRQ_PWM1) /* Vector 16+9: PWM 1 */ +VECTOR(lpc17_i2c0, LPC17_IRQ_I2C0) /* Vector 16+10: I2C 0 */ +VECTOR(lpc17_i2c1, LPC17_IRQ_I2C1) /* Vector 16+11: I2C 1 */ +VECTOR(lpc17_i2c2, LPC17_IRQ_I2C2) /* Vector 16+12: I2C 2 */ +UNUSED(LPC17_IRQ_RESERVED29) /* Vector 16+13: Reserved */ +VECTOR(lpc17_ssp0, LPC17_IRQ_SSP0) /* Vector 16+14: SSP 0 */ +VECTOR(lpc17_ssp1, LPC17_IRQ_SSP1) /* Vector 16+15: SSP 1 */ +VECTOR(lpc17_pll0, LPC17_IRQ_PLL0) /* Vector 16+16: PLL 0 */ +VECTOR(lpc17_rtc, LPC17_IRQ_RTC) /* Vector 16+17: Real time clock */ +VECTOR(lpc17_eint0, LPC17_IRQ_EINT0) /* Vector 16+18: External interrupt 0 */ +VECTOR(lpc17_eint1, LPC17_IRQ_EINT1) /* Vector 16+19: External interrupt 1 */ +VECTOR(lpc17_eint2, LPC17_IRQ_EINT2) /* Vector 16+20: External interrupt 2 */ +VECTOR(lpc17_eint3, LPC17_IRQ_EINT3) /* Vector 16+21: External interrupt 3 */ +VECTOR(lpc17_adc, LPC17_IRQ_ADC) /* Vector 16+22: A/D Converter */ +VECTOR(lpc17_bod, LPC17_IRQ_BOD) /* Vector 16+23: Brown Out detect */ +VECTOR(lpc17_usb, LPC17_IRQ_USB) /* Vector 16+24: USB */ +VECTOR(lpc17_can, LPC17_IRQ_CAN) /* Vector 16+25: CAN */ +VECTOR(lpc17_gpdma, LPC17_IRQ_GPDMA) /* Vector 16+26: GPDMA */ +VECTOR(lpc17_i2s, LPC17_IRQ_I2S) /* Vector 16+27: I2S */ +VECTOR(lpc17_eth, LPC17_IRQ_ETH) /* Vector 16+28: Ethernet */ +VECTOR(lpc17_mci, LPC17_IRQ_MCI) /* Vector 16+29: MMC/SD */ +VECTOR(lpc17_mcpwm, LPC17_IRQ_MCPWM) /* Vector 16+30: Motor Control PWM */ +VECTOR(lpc17_qei, LPC17_IRQ_QEI) /* Vector 16+31: Quadrature Encoder */ +VECTOR(lpc17_pll1, LPC17_IRQ_PLL1) /* Vector 16+32: PLL 1 */ +VECTOR(lpc17_usbact, LPC17_IRQ_USBACT) /* Vector 16+33: USB Activity Interrupt */ +VECTOR(lpc17_canact, LPC17_IRQ_CANACT) /* Vector 16+34: CAN Activity Interrupt */ +VECTOR(lpc17_uart4, LPC17_IRQ_UART4) /* Vector 16+35: UART 4 */ +VECTOR(lpc17_ssp2, LPC17_IRQ_SSP2) /* Vector 16+36: SSP 2 */ +VECTOR(lpc17_lcd, LPC17_IRQ_LCD) /* Vector 16+37: LCD */ +VECTOR(lpc17_gpio, LPC17_IRQ_GPIO) /* Vector 16+38: GPIO */ +VECTOR(lpc17_pwm0, LPC17_IRQ_PWM0) /* Vector 16+39: PWM0 */ +VECTOR(lpc17_eeprom, LPC17_IRQ_EEPROM) /* Vector 16+40: EEPROM */ + +#endif + +/******************************************************************************** + * Public Types + ********************************************************************************/ + +/******************************************************************************** + * Public Data + ********************************************************************************/ + +/******************************************************************************** + * Public Function Prototypes + ********************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S index cdb4bef66..74e53b411 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_vectors.S * arch/arm/src/chip/lpc17_vectors.S * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -128,41 +128,20 @@ lpc17_vectors: /* External Interrupts */ - .word lpc17_wdt /* Vector 16+0: Watchdog timer */ - .word lpc17_tmr0 /* Vector 16+1: Timer 0 */ - .word lpc17_tmr1 /* Vector 16+2: Timer 1 */ - .word lpc17_tmr2 /* Vector 16+3: Timer 2 */ - .word lpc17_tmr3 /* Vector 16+4: Timer 3 */ - .word lpc17_uart0 /* Vector 16+5: UART 0 */ - .word lpc17_uart1 /* Vector 16+6: UART 1 */ - .word lpc17_uart2 /* Vector 16+7: UART 2 */ - .word lpc17_uart3 /* Vector 16+8: UART 3 */ - .word lpc17_pwm1 /* Vector 16+9: PWM */ - .word lpc17_i2c0 /* Vector 16+10: I2C 0 */ - .word lpc17_i2c1 /* Vector 16+11: I2C 1 */ - .word lpc17_i2c2 /* Vector 16+12: I2C 2 */ - .word lpc17_spif /* Vector 16+13: SPI */ - .word lpc17_ssp0 /* Vector 16+14: SSP 0 */ - .word lpc17_ssp1 /* Vector 16+15: SSP 1 */ - .word lpc17_pll0 /* Vector 16+16: PLL 0 */ - .word lpc17_rtc /* Vector 16+17: Real time clock */ - .word lpc17_eint0 /* Vector 16+18: External interrupt 0 */ - .word lpc17_eint1 /* Vector 16+19: External interrupt 1 */ - .word lpc17_eint2 /* Vector 16+20: External interrupt 2 */ - .word lpc17_eint3 /* Vector 16+21: External interrupt 3 */ - .word lpc17_adc /* Vector 16+22: A/D Converter */ - .word lpc17_bod /* Vector 16+23: Brown Out detect */ - .word lpc17_usb /* Vector 16+24: USB */ - .word lpc17_can /* Vector 16+25: CAN */ - .word lpc17_gpdma /* Vector 16+26: GPDMA */ - .word lpc17_i2s /* Vector 16+27: I2S */ - .word lpc17_eth /* Vector 16+28: Ethernet */ - .word lpc17_ritint /* Vector 16+29: Repetitive Interrupt Timer */ - .word lpc17_mcpwm /* Vector 16+30: Motor Control PWM */ - .word lpc17_qei /* Vector 16+31: Quadrature Encoder */ - .word lpc17_pll1 /* Vector 16+32: PLL 1 */ - .word lpc17_usbact /* Vector 16+33: USB Activity Interrupt */ - .word lpc17_canact /* Vector 16+34: CAN Activity Interrupt */ +#undef VECTOR +#define VECTOR(l,i) .word l + +#undef UNUSED +#define UNUSED(i) .word lpc17_reserved + +#if defined(LPC176x) +# include "chip/lpc176x_vectors.h" +#elif defined(LPC178x) +# include "chip/lpc178x_vectors.h" +#else +# error "Unrecognized LPC17xx family" +#endif + .size lpc17_vectors, .-lpc17_vectors /************************************************************************************************ @@ -184,41 +163,21 @@ handlers: HANDLER lpc17_pendsv, LPC17_IRQ_PENDSV /* Vector 14: Penable system service request */ HANDLER lpc17_systick, LPC17_IRQ_SYSTICK /* Vector 15: System tick */ - HANDLER lpc17_wdt, LPC17_IRQ_WDT /* Vector 16+0: Watchdog timer */ - HANDLER lpc17_tmr0, LPC17_IRQ_TMR0 /* Vector 16+1: Timer 0 */ - HANDLER lpc17_tmr1, LPC17_IRQ_TMR1 /* Vector 16+2: Timer 1 */ - HANDLER lpc17_tmr2, LPC17_IRQ_TMR2 /* Vector 16+3: Timer 2 */ - HANDLER lpc17_tmr3, LPC17_IRQ_TMR3 /* Vector 16+4: Timer 3 */ - HANDLER lpc17_uart0, LPC17_IRQ_UART0 /* Vector 16+5: UART 0 */ - HANDLER lpc17_uart1, LPC17_IRQ_UART1 /* Vector 16+6: UART 1 */ - HANDLER lpc17_uart2, LPC17_IRQ_UART2 /* Vector 16+7: UART 2 */ - HANDLER lpc17_uart3, LPC17_IRQ_UART3 /* Vector 16+8: UART 3 */ - HANDLER lpc17_pwm1, LPC17_IRQ_PWM1 /* Vector 16+9: PWM 1 */ - HANDLER lpc17_i2c0, LPC17_IRQ_I2C0 /* Vector 16+10: I2C 0 */ - HANDLER lpc17_i2c1, LPC17_IRQ_I2C1 /* Vector 16+11: I2C 1 */ - HANDLER lpc17_i2c2, LPC17_IRQ_I2C2 /* Vector 16+12: I2C 2 */ - HANDLER lpc17_spif, LPC17_IRQ_SPIF /* Vector 16+13: SPI */ - HANDLER lpc17_ssp0, LPC17_IRQ_SSP0 /* Vector 16+14: SSP 0 */ - HANDLER lpc17_ssp1, LPC17_IRQ_SSP1 /* Vector 16+15: SSP 1 */ - HANDLER lpc17_pll0, LPC17_IRQ_PLL0 /* Vector 16+16: PLL 0 */ - HANDLER lpc17_rtc, LPC17_IRQ_RTC /* Vector 16+17: Real time clock */ - HANDLER lpc17_eint0, LPC17_IRQ_EINT0 /* Vector 16+18: External interrupt 0 */ - HANDLER lpc17_eint1, LPC17_IRQ_EINT1 /* Vector 16+19: External interrupt 1 */ - HANDLER lpc17_eint2, LPC17_IRQ_EINT2 /* Vector 16+20: External interrupt 2 */ - HANDLER lpc17_eint3, LPC17_IRQ_EINT3 /* Vector 16+21: External interrupt 3 */ - HANDLER lpc17_adc, LPC17_IRQ_ADC /* Vector 16+22: A/D Converter */ - HANDLER lpc17_bod, LPC17_IRQ_BOD /* Vector 16+23: Brown Out detect */ - HANDLER lpc17_usb, LPC17_IRQ_USB /* Vector 16+24: USB */ - HANDLER lpc17_can, LPC17_IRQ_CAN /* Vector 16+25: CAN */ - HANDLER lpc17_gpdma, LPC17_IRQ_GPDMA /* Vector 16+26: GPDMA */ - HANDLER lpc17_i2s, LPC17_IRQ_I2S /* Vector 16+27: I2S */ - HANDLER lpc17_eth, LPC17_IRQ_ETH /* Vector 16+28: Ethernet */ - HANDLER lpc17_ritint, LPC17_IRQ_RITINT /* Vector 16+29: Repetitive Interrupt Timer */ - HANDLER lpc17_mcpwm, LPC17_IRQ_MCPWM /* Vector 16+30: Motor Control PWM */ - HANDLER lpc17_qei, LPC17_IRQ_QEI /* Vector 16+31: Quadrature Encoder */ - HANDLER lpc17_pll1, LPC17_IRQ_PLL1 /* Vector 16+32: PLL 1 */ - HANDLER lpc17_usbact, LPC17_IRQ_USBACT /* Vector 16+33: USB Activity Interrupt */ - HANDLER lpc17_canact, LPC17_IRQ_CANACT /* Vector 16+34: CAN Activity Interrupt */ +/* External Interrupts */ + +#undef VECTOR +#define VECTOR(l,i) HANDLER l, i + +#undef UNUSED +#define UNUSED(i) + +#if defined(LPC176x) +# include "chip/lpc176x_vectors.h" +#elif defined(LPC178x) +# include "chip/lpc178x_vectors.h" +#else +# error "Unrecognized LPC17xx family" +#endif /* Common IRQ handling logic. On entry here, the return stack is on either * the PSP or the MSP and looks like the following: -- cgit v1.2.3 From 53e8b454bf671e2b7e2cfe1898468543ab231984 Mon Sep 17 00:00:00 2001 From: patacongo Date: Fri, 18 Jan 2013 22:42:37 +0000 Subject: Add configuration for Wave Share Open1788 (fragmentary) git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5537 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 5 + nuttx/arch/Kconfig | 125 +++++ nuttx/arch/arm/src/lpc17xx/Kconfig | 8 + nuttx/arch/arm/src/lpc31xx/Kconfig | 85 +--- nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c | 32 +- nuttx/arch/arm/src/lpc31xx/lpc31_boot.c | 6 +- nuttx/arch/arm/src/lpc31xx/lpc31_memorymap.h | 8 +- nuttx/configs/Kconfig | 12 + nuttx/configs/ea3131/README.txt | 22 +- nuttx/configs/ea3131/nsh/defconfig | 22 +- nuttx/configs/ea3131/ostest/defconfig | 22 +- nuttx/configs/ea3131/pgnsh/defconfig | 22 +- nuttx/configs/ea3131/src/Makefile | 2 +- nuttx/configs/ea3131/src/ea3131_internal.h | 2 +- nuttx/configs/ea3131/src/up_boot.c | 2 +- nuttx/configs/ea3131/src/up_mem.c | 4 +- nuttx/configs/ea3131/usbserial/defconfig | 22 +- nuttx/configs/ea3131/usbstorage/defconfig | 22 +- nuttx/configs/ea3152/README.txt | 22 +- nuttx/configs/ea3152/ostest/defconfig | 22 +- nuttx/configs/ea3152/src/Makefile | 2 +- nuttx/configs/ea3152/src/ea3152_internal.h | 2 +- nuttx/configs/ea3152/src/up_boot.c | 2 +- nuttx/configs/ea3152/src/up_mem.c | 4 +- nuttx/configs/open1788/Kconfig | 7 + nuttx/configs/open1788/README.txt | 38 ++ nuttx/configs/open1788/ostest/Make.defs | 109 +++++ nuttx/configs/open1788/ostest/defconfig | 604 ++++++++++++++++++++++++ nuttx/configs/open1788/ostest/setenv.sh | 73 +++ nuttx/configs/open1788/scripts/ld.script | 135 ++++++ 30 files changed, 1254 insertions(+), 189 deletions(-) create mode 100644 nuttx/configs/open1788/Kconfig create mode 100644 nuttx/configs/open1788/README.txt create mode 100644 nuttx/configs/open1788/ostest/Make.defs create mode 100644 nuttx/configs/open1788/ostest/defconfig create mode 100755 nuttx/configs/open1788/ostest/setenv.sh create mode 100755 nuttx/configs/open1788/scripts/ld.script diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c61479cad..a5bcaf1bc 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3982,3 +3982,8 @@ * configs/olimex-lpc1766stk/nsh: Convert configuration to use the kconfig-frontends tools. * sched/task_reparent.c: Simplify reparenting interface. + * arch/arm/src/[many]: More LPC1788 definitions from Rommel + Marcelo incorporated. + * configs/open1788: Board configuration for the Wave Share + Open1788 board. Still fragmentary (contribnuted by Rommel + Marcelo, adapted to use kconfig-frontends. diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig index d43137adb..c0f235c5d 100644 --- a/nuttx/arch/Kconfig +++ b/nuttx/arch/Kconfig @@ -103,6 +103,131 @@ source arch/x86/Kconfig source arch/z16/Kconfig source arch/z80/Kconfig +comment "External Memory Configuration" + +config ARCH_HAVE_EXTNAND + bool + +config ARCH_HAVE_EXTNOR + bool + +config ARCH_HAVE_EXTDRAM + bool + +config ARCH_HAVE_EXTSRAM0 + bool + +config ARCH_HAVE_EXTSRAM1 + bool + +config ARCH_EXTNAND + bool "Configure external NAND" + default n + depends on ARCH_HAVE_EXTNAND + ---help--- + Configure external NAND memory and, if applicable, map then external + NAND into the memory map. + +if ARCH_EXTNAND + +config ARCH_EXTNANDSIZE + int "External NAND size" + default 0 + ---help--- + Size of the external NAND in bytes. + +endif + +config ARCH_EXTNOR + bool "Configure external NOR memory" + default n + depends on ARCH_HAVE_EXTNOR + ---help--- + Configure external NOR memory and, if applicable, map then external + NOR into the memory map. + +if ARCH_EXTNOR + +config ARCH_EXTNORSIZE + int "External NOR size" + default 0 + ---help--- + Size of the external NOR in bytes. + +endif + +config ARCH_EXTDRAM + bool "Configure external DRAM" + default n + depends on ARCH_HAVE_EXTDRAM + ---help--- + Configure external DRAM memory and, if applicable, map then external + DRAM into the memory map. + +if ARCH_EXTDRAM + +config ARCH_EXTDRAMSIZE + int "External SDRAM size" + default 0 + ---help--- + Size of the external SDRAM in bytes. + +config ARCH_EXTDRAMHEAP + bool "Add external SDRAM to the heap" + default y + ---help--- + Add the external SDRAM into the heap. + +endif + +config ARCH_EXTSRAM0 + bool "Configure external SRAM (Bank 0)" + default n + depends on ARCH_HAVE_EXTSRAM0 + ---help--- + Configure external SRAM Bank 0 memory and, if applicable, map then + external SRAM Bank 0 into the memory map. + +if ARCH_EXTSRAM0 + +config ARCH_EXTSRAM0SIZE + int "External SRAM size" + default 0 + ---help--- + Size of the external SRAM Bank 0 in bytes. + +config ARCH_EXTSRAM0HEAP + bool "Add external SRAM (Bank 0) to the heap" + default y + ---help--- + Add external SRAM Bank 0 into the heap. + +endif + +config ARCH_EXTSRAM1 + bool "Configure external SRAM (Bank 1)" + default n + depends on ARCH_HAVE_EXTSRAM1 + ---help--- + Configure external SRAM Bank 1 memory and, if applicable, map then + external SRAM Bank 1 into the memory map. + +if ARCH_EXTSRAM1 + +config ARCH_EXTSRAM1SIZE + int "External SRAM1 size" + default 0 + ---help--- + Size of the external SRAM Bank 1 in bytes. + +config ARCH_EXTSRAM1HEAP + bool "Add external SRAM (Bank 1) to the heap" + default y + ---help--- + Add external SRAM Bank 1 into the heap. + +endif + comment "Architecture Options" config ARCH_NOINTC diff --git a/nuttx/arch/arm/src/lpc17xx/Kconfig b/nuttx/arch/arm/src/lpc17xx/Kconfig index b7dd7ac34..22ba6fa04 100644 --- a/nuttx/arch/arm/src/lpc17xx/Kconfig +++ b/nuttx/arch/arm/src/lpc17xx/Kconfig @@ -104,9 +104,17 @@ config ARCH_FAMILY_LPC176X config ARCH_FAMILY_LPC177X bool + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTDRAM + select ARCH_HAVE_EXTNOR config ARCH_FAMILY_LPC178X bool + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTDRAM + select ARCH_HAVE_EXTNOR menu "LPC17xx Peripheral Support" diff --git a/nuttx/arch/arm/src/lpc31xx/Kconfig b/nuttx/arch/arm/src/lpc31xx/Kconfig index ad7bf3d4e..531cea0af 100644 --- a/nuttx/arch/arm/src/lpc31xx/Kconfig +++ b/nuttx/arch/arm/src/lpc31xx/Kconfig @@ -12,15 +12,31 @@ choice config ARCH_CHIP_LPC3130 bool "LPC3130" + select ARCH_HAVE_EXTNAN + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + select ARCH_HAVE_EXTDRAM config ARCH_CHIP_LPC3131 bool "LPC3131" + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + select ARCH_HAVE_EXTDRAM config ARCH_CHIP_LPC3152 bool "LPC3152" + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + select ARCH_HAVE_EXTDRAM config ARCH_CHIP_LPC3154 bool "LPC3154" + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + select ARCH_HAVE_EXTDRAM endchoice @@ -48,79 +64,12 @@ config LPC31_BUILDROOT endchoice -menu "LPC31xx Memory Mapping" - -config LPC31_EXTNAND - bool "Map external NAND" - default n - ---help--- - Map external NAND into the memory map. - -config LPC31_EXTSDRAM - bool "Map external SDRAM" - default n - ---help--- - Map external SDRAM into the memory map. - -config LPC31_EXTSDRAMHEAP - bool "Add external SDRAM to the heap" - default y - depends on LPC31_EXTSDRAM - ---help--- - Add external SDRAM into the heap. - -config LPC31_EXTSDRAMSIZE - int "External SDRAM size" - depends on LPC31_EXTSDRAM - ---help--- - Size of the external SDRAM. - config LPC31_SDRAMHCLK int "External SDRAM HCLK" - depends on LPC31_EXTSDRAM + depends on ARCH_EXTSDRAM ---help--- The SDRAM HCLK may be specified here (if not, it will be calculated). -config LPC31_EXTSRAM0 - bool "Map external SRAM0" - default n - ---help--- - Map external SRAM0 into the memory map. - -config LPC31_EXTSRAM0HEAP - bool "Add external SRAM0 to the heap" - default y - depends on LPC31_EXTSRAM0 - ---help--- - Add external SRAM0 into the heap. - -config LPC31_EXTSRAM0SIZE - int "External SRAM size" - depends on LPC31_EXTSRAM0 - ---help--- - Size of the external SRAM. - -config LPC31_EXTSRAM1 - bool "Map external SRAM0" - default n - ---help--- - Map external SRAM1 into the memory map. - -config LPC31_EXTSRAM1HEAP - bool "Add external SRAM1 to the heap" - default y - depends on LPC31_EXTSRAM1 - ---help--- - Add external SRAM1 into the heap. - -config LPC31_EXTSRAM1SIZE - int "External SRAM1 size" - depends on LPC31_EXTSRAM1 - ---help--- - Size of the external SRAM1. - -endmenu - menu "LPC31xx Peripheral Support" config LPC31_UART diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c index df3c897e1..58772a630 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -67,31 +67,31 @@ * memory regions that we have been asked to add to the heap. */ -#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP) -# if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP) -# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) +#if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP) +# if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP) +# if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) # /* SRAM+EXTSRAM0+EXTSRAM1+EXTSDRAM */ # define LPC31_NEXT_REGIONS 4 # else # /* SRAM+EXTSRAM0+EXTSRAM1 */ # define LPC31_NEXT_REGIONS 3 # endif -# elif defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) +# elif defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) # /* SRAM+EXTSRAM0+EXTSDRAM */ # define LPC31_NEXT_REGIONS 3 # else # /* SRAM+EXTSRAM0 */ # define LPC31_NEXT_REGIONS 2 # endif -#elif defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP) -# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) +#elif defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP) +# if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) # /* SRAM+EXTSRAM1+EXTSDRAM */ # define LPC31_NEXT_REGIONS 3 # else # /* SRAM+EXTSRAM1 */ # define LPC31_NEXT_REGIONS 2 # endif -#elif defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) +#elif defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) # /* SRAM+EXTSDRAM */ # define LPC31_NEXT_REGIONS 2 #else @@ -105,13 +105,13 @@ # else # error "CONFIG_MM_REGIONS is too large for the selected memory regions" # endif -# if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP) +# if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP) # error "External SRAM0 is selected for heap" # endif -# if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP) +# if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP) # error "External SRAM1 is selected for heap" # endif -# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) +# if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) # error "External SRAM1 is selected for heap" # endif #endif @@ -191,16 +191,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP) - mm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_LPC31_EXTSRAM0SIZE); +#if defined(CONFIG_ARCH_EXTSRAM0) && defined(CONFIG_ARCH_EXTSRAM0HEAP) + mm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_ARCH_EXTSRAM0SIZE); #endif -#if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP) - mm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_LPC31_EXTSRAM1SIZE); +#if defined(CONFIG_ARCH_EXTSRAM1) && defined(CONFIG_ARCH_EXTSRAM1HEAP) + mm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_ARCH_EXTSRAM1SIZE); #endif -#if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP) - mm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_LPC31_EXTSDRAMSIZE); +#if defined(CONFIG_ARCH_EXTDRAM) && defined(CONFIG_ARCH_EXTDRAMHEAP) + mm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_ARCH_EXTDRAMSIZE); #endif } #endif diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c b/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c index 7abe15d4d..a7c1acdc8 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_boot.c @@ -112,17 +112,17 @@ static const struct section_mapping_s section_mapping[] = LPC31_MCI_MMUFLAGS, LPC31_MCI_NSECTIONS}, { LPC31_USBOTG_PSECTION, LPC31_USBOTG_VSECTION, LPC31_USBOTG_MMUFLAGS, LPC31_USBOTG_NSECTIONS}, -#if defined(CONFIG_LPC31_EXTSRAM0) && CONFIG_LPC31_EXTSRAM0SIZE > 0 +#if defined(CONFIG_ARCH_EXTSRAM0) && CONFIG_ARCH_EXTSRAM0SIZE > 0 { LPC31_EXTSRAM_PSECTION, LPC31_EXTSRAM_VSECTION, LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSRAM_NSECTIONS}, #endif -#if defined(CONFIG_LPC31_EXTSDRAM) && CONFIG_LPC31_EXTSDRAMSIZE > 0 +#if defined(CONFIG_ARCH_EXTDRAM) && CONFIG_ARCH_EXTDRAMSIZE > 0 { LPC31_EXTSDRAM0_PSECTION, LPC31_EXTSDRAM0_VSECTION, LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSDRAM0_NSECTIONS}, #endif { LPC31_INTC_PSECTION, LPC31_INTC_VSECTION, LPC31_INTC_MMUFLAGS, LPC31_INTC_NSECTIONS}, -#ifdef CONFIG_LPC31_EXTNAND +#ifdef CONFIG_ARCH_EXTNAND { LPC31_NAND_PSECTION, LPC31_NAND_VSECTION LPC31_NAND_MMUFLAGS, LPC31_NAND_NSECTIONS}, #endif diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_memorymap.h b/nuttx/arch/arm/src/lpc31xx/lpc31_memorymap.h index b5155df89..8d13019ac 100644 --- a/nuttx/arch/arm/src/lpc31xx/lpc31_memorymap.h +++ b/nuttx/arch/arm/src/lpc31xx/lpc31_memorymap.h @@ -81,7 +81,7 @@ /* 0x60001000-0x6fffffff: Reserved */ #define LPC31_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */ /* 0x70000800-0xffffffff: Reserved */ -#ifdef CONFIG_LPC31_EXTNAND /* End of the physical address space */ +#ifdef CONFIG_ARCH_EXTNAND /* End of the physical address space */ # define LPC31_LAST_PSECTION (LPC31_NAND_PSECTION + (1 << 20)) #else # define LPC31_LAST_PSECTION (LPC31_INTC_PSECTION + (1 << 20)) @@ -176,8 +176,8 @@ * the size of the SDRAM installed. */ -#if defined(CONFIG_LPC31_EXTSDRAM) && CONFIG_LPC31_EXTSDRAMSIZE > 0 -# define LPC31_EXTSDRAM0_NSECTIONS _NSECTIONS(CONFIG_LPC31_EXTSDRAMSIZE) +#if defined(CONFIG_ARCH_EXTDRAM) && CONFIG_ARCH_EXTDRAMSIZE > 0 +# define LPC31_EXTSDRAM0_NSECTIONS _NSECTIONS(CONFIG_ARCH_EXTDRAMSIZE) #endif /* Section MMU Flags */ @@ -233,7 +233,7 @@ # define LPC31_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */ # define LPC31_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */ # -# ifdef CONFIG_LPC31_EXTNAND /* End of the virtual address space */ +# ifdef CONFIG_ARCH_EXTNAND /* End of the virtual address space */ # define LPC31_LAST_VSECTION (LPC31_NAND_VSECTION + (1 << 20)) # else # define LPC31_LAST_VSECTION (LPC31_INTC_VSECTION + (1 << 20)) diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index d851eeccb..d72d01058 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -346,6 +346,14 @@ config ARCH_BOARD_OLIMEX_STM32P107 Linux or Cygwin. See the http://www.olimex.com for further information. This board features the STMicro STM32F107VC MCU +config ARCH_BOARD_OPEN1788 + bool "Wave Share Open1788" + depends on ARCH_CHIP_LPC1788 + ---help--- + This port uses the Wave Share Open1788 board. See the + http://wvshare.com/product/Open1788-Standard.htm for further + information. This board features the NXP LPC1788 MCU + config ARCH_BOARD_P112 bool "P112 Z180-based platform" depends on ARCH_CHIP_Z8018216FSG @@ -682,6 +690,7 @@ config ARCH_BOARD default "olimex-lpc2378" if ARCH_BOARD_OLIMEXLPC2378 default "olimex-stm32-p107" if ARCH_BOARD_OLIMEX_STM32P107 default "olimex-strp711" if ARCH_BOARD_OLIMEX_STRP711 + default "open1788" if ARCH_BOARD_OPEN1788 default "p112" if ARCH_BOARD_P112 default "pcblogic-pic32mx" if ARCH_BOARD_PCBLOGICPIC32MX default "pic32-starterkit" if ARCH_BOARD_PIC32_STARTERKIT @@ -869,6 +878,9 @@ endif if ARCH_BOARD_OLIMEX_STRP711 source "configs/olimex-strp711/Kconfig" endif +if ARCH_BOARD_OPEN1788 +source "configs/open1788/Kconfig" +endif if ARCH_BOARD_PCBLOGICPIC32MX source "configs/pcblogic-pic32mx/Kconfig" endif diff --git a/nuttx/configs/ea3131/README.txt b/nuttx/configs/ea3131/README.txt index 986b7778c..f11caab4f 100644 --- a/nuttx/configs/ea3131/README.txt +++ b/nuttx/configs/ea3131/README.txt @@ -570,23 +570,23 @@ ARM/EA3131-specific Configuration Options External memory available on the board (see also CONFIG_MM_REGIONS) - CONFIG_LPC31_EXTSRAM0 - Select if external SRAM0 is present - CONFIG_LPC31_EXTSRAM0HEAP - Select if external SRAM0 should be + CONFIG_ARCH_EXTSRAM0 - Select if external SRAM0 is present + CONFIG_ARCH_EXTSRAM0HEAP - Select if external SRAM0 should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSRAM0SIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTSRAM0SIZE - Size (in bytes) of the installed external SRAM0 memory - CONFIG_LPC31_EXTSRAM1 - Select if external SRAM1 is present - CONFIG_LPC31_EXTSRAM1HEAP - Select if external SRAM1 should be + CONFIG_ARCH_EXTSRAM1 - Select if external SRAM1 is present + CONFIG_ARCH_EXTSRAM1HEAP - Select if external SRAM1 should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSRAM1SIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTSRAM1SIZE - Size (in bytes) of the installed external SRAM1 memory - CONFIG_LPC31_EXTSDRAM - Select if external SDRAM is present - CONFIG_LPC31_EXTSDRAMHEAP - Select if external SDRAM should be + CONFIG_ARCH_EXTDRAM - Select if external SDRAM is present + CONFIG_ARCH_EXTDRAMHEAP - Select if external SDRAM should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSDRAMSIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTDRAMSIZE - Size (in bytes) of the installed external SDRAM memory - CONFIG_LPC31_EXTNAND - Select if external NAND is present - CONFIG_LPC31_EXTSDRAMSIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTNAND - Select if external NAND is present + CONFIG_ARCH_EXTNANDSIZE - Size (in bytes) of the installed external NAND memory LPC313X specific device driver settings diff --git a/nuttx/configs/ea3131/nsh/defconfig b/nuttx/configs/ea3131/nsh/defconfig index 43510fa59..04398d1a2 100644 --- a/nuttx/configs/ea3131/nsh/defconfig +++ b/nuttx/configs/ea3131/nsh/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3131/ostest/defconfig b/nuttx/configs/ea3131/ostest/defconfig index 6da813d9e..d137835af 100644 --- a/nuttx/configs/ea3131/ostest/defconfig +++ b/nuttx/configs/ea3131/ostest/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3131/pgnsh/defconfig b/nuttx/configs/ea3131/pgnsh/defconfig index 2a9eeff93..d734bc21c 100644 --- a/nuttx/configs/ea3131/pgnsh/defconfig +++ b/nuttx/configs/ea3131/pgnsh/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3131/src/Makefile b/nuttx/configs/ea3131/src/Makefile index 778a2b138..1b91577e9 100644 --- a/nuttx/configs/ea3131/src/Makefile +++ b/nuttx/configs/ea3131/src/Makefile @@ -44,7 +44,7 @@ CSRCS = up_boot.c up_clkinit.c ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += up_buttons.c endif -ifeq ($(CONFIG_LPC31_EXTSDRAM),y) +ifeq ($(CONFIG_ARCH_EXTDRAM),y) CSRCS += up_mem.c endif ifeq ($(CONFIG_ARCH_LEDS),y) diff --git a/nuttx/configs/ea3131/src/ea3131_internal.h b/nuttx/configs/ea3131/src/ea3131_internal.h index 4a8ae3fa4..4ba97d83d 100644 --- a/nuttx/configs/ea3131/src/ea3131_internal.h +++ b/nuttx/configs/ea3131/src/ea3131_internal.h @@ -86,7 +86,7 @@ * ************************************************************************************/ -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM extern void lpc31_meminitialize(void); #endif diff --git a/nuttx/configs/ea3131/src/up_boot.c b/nuttx/configs/ea3131/src/up_boot.c index 1fd9069f8..c8ae70461 100644 --- a/nuttx/configs/ea3131/src/up_boot.c +++ b/nuttx/configs/ea3131/src/up_boot.c @@ -75,7 +75,7 @@ void lpc31_boardinitialize(void) { /* Initialize configured, external memory resources */ -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM lpc31_meminitialize(); #endif diff --git a/nuttx/configs/ea3131/src/up_mem.c b/nuttx/configs/ea3131/src/up_mem.c index 060f58eec..668233d3b 100644 --- a/nuttx/configs/ea3131/src/up_mem.c +++ b/nuttx/configs/ea3131/src/up_mem.c @@ -59,7 +59,7 @@ #include "lpc31_mpmc.h" #include "ea3131_internal.h" -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM /**************************************************************************** * Pre-processor Definitions @@ -356,4 +356,4 @@ void lpc31_meminitialize(void) lpc31_sdraminitialize(); } -#endif /* CONFIG_LPC31_EXTSDRAM */ +#endif /* CONFIG_ARCH_EXTDRAM */ diff --git a/nuttx/configs/ea3131/usbserial/defconfig b/nuttx/configs/ea3131/usbserial/defconfig index 40c0897f7..398d9b3bc 100644 --- a/nuttx/configs/ea3131/usbserial/defconfig +++ b/nuttx/configs/ea3131/usbserial/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3131/usbstorage/defconfig b/nuttx/configs/ea3131/usbstorage/defconfig index 0659383a6..c69379ba9 100644 --- a/nuttx/configs/ea3131/usbstorage/defconfig +++ b/nuttx/configs/ea3131/usbstorage/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3152/README.txt b/nuttx/configs/ea3152/README.txt index 4f507e7b0..8ede86b4f 100644 --- a/nuttx/configs/ea3152/README.txt +++ b/nuttx/configs/ea3152/README.txt @@ -376,23 +376,23 @@ ARM/EA3152-specific Configuration Options External memory available on the board (see also CONFIG_MM_REGIONS) - CONFIG_LPC31_EXTSRAM0 - Select if external SRAM0 is present - CONFIG_LPC31_EXTSRAM0HEAP - Select if external SRAM0 should be + CONFIG_ARCH_EXTSRAM0 - Select if external SRAM0 is present + CONFIG_ARCH_EXTSRAM0HEAP - Select if external SRAM0 should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSRAM0SIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTSRAM0SIZE - Size (in bytes) of the installed external SRAM0 memory - CONFIG_LPC31_EXTSRAM1 - Select if external SRAM1 is present - CONFIG_LPC31_EXTSRAM1HEAP - Select if external SRAM1 should be + CONFIG_ARCH_EXTSRAM1 - Select if external SRAM1 is present + CONFIG_ARCH_EXTSRAM1HEAP - Select if external SRAM1 should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSRAM1SIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTSRAM1SIZE - Size (in bytes) of the installed external SRAM1 memory - CONFIG_LPC31_EXTSDRAM - Select if external SDRAM is present - CONFIG_LPC31_EXTSDRAMHEAP - Select if external SDRAM should be + CONFIG_ARCH_EXTDRAM - Select if external SDRAM is present + CONFIG_ARCH_EXTDRAMHEAP - Select if external SDRAM should be configured as part of the NuttX heap. - CONFIG_LPC31_EXTSDRAMSIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTDRAMSIZE - Size (in bytes) of the installed external SDRAM memory - CONFIG_LPC31_EXTNAND - Select if external NAND is present - CONFIG_LPC31_EXTSDRAMSIZE - Size (in bytes) of the installed + CONFIG_ARCH_EXTNAND - Select if external NAND is present + CONFIG_ARCH_EXTNANDSIZE - Size (in bytes) of the installed external NAND memory LPC315X specific device driver settings diff --git a/nuttx/configs/ea3152/ostest/defconfig b/nuttx/configs/ea3152/ostest/defconfig index d4d978649..07a1491ed 100644 --- a/nuttx/configs/ea3152/ostest/defconfig +++ b/nuttx/configs/ea3152/ostest/defconfig @@ -79,17 +79,17 @@ CONFIG_LPC31_UART=y # # Exernal memory available on the board (see also CONFIG_MM_REGIONS) # -CONFIG_LPC31_EXTSRAM0=n -CONFIG_LPC31_EXTSRAM0HEAP=n -CONFIG_LPC31_EXTSRAM0SIZE=131072 -CONFIG_LPC31_EXTSRAM1=n -CONFIG_LPC31_EXTSRAM1HEAP=n -CONFIG_LPC31_EXTSRAM1SIZE=131072 -CONFIG_LPC31_EXTSDRAM=n -CONFIG_LPC31_EXTSDRAMHEAP=n -CONFIG_LPC31_EXTSDRAMSIZE=67108864 -CONFIG_LPC31_EXTNAND=n -CONFIG_LPC31_EXTNANDSIZE=67108864 +CONFIG_ARCH_EXTSRAM0=n +CONFIG_ARCH_EXTSRAM0HEAP=n +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM1=n +CONFIG_ARCH_EXTSRAM1HEAP=n +CONFIG_ARCH_EXTSRAM1SIZE=131072 +CONFIG_ARCH_EXTDRAM=n +CONFIG_ARCH_EXTDRAMHEAP=n +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTNAND=n +CONFIG_ARCH_EXTNANDSIZE=67108864 # # LPC31XX specific device driver settings diff --git a/nuttx/configs/ea3152/src/Makefile b/nuttx/configs/ea3152/src/Makefile index cb945f5aa..c184838d5 100644 --- a/nuttx/configs/ea3152/src/Makefile +++ b/nuttx/configs/ea3152/src/Makefile @@ -44,7 +44,7 @@ CSRCS = up_boot.c up_clkinit.c ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += up_buttons.c endif -ifeq ($(CONFIG_LPC31_EXTSDRAM),y) +ifeq ($(CONFIG_ARCH_EXTDRAM),y) CSRCS += up_mem.c endif ifeq ($(CONFIG_ARCH_LEDS),y) diff --git a/nuttx/configs/ea3152/src/ea3152_internal.h b/nuttx/configs/ea3152/src/ea3152_internal.h index ee93c36a1..84fab1338 100644 --- a/nuttx/configs/ea3152/src/ea3152_internal.h +++ b/nuttx/configs/ea3152/src/ea3152_internal.h @@ -86,7 +86,7 @@ * ************************************************************************************/ -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM extern void lpc31_meminitialize(void); #endif diff --git a/nuttx/configs/ea3152/src/up_boot.c b/nuttx/configs/ea3152/src/up_boot.c index c8870cfdf..066808b2f 100644 --- a/nuttx/configs/ea3152/src/up_boot.c +++ b/nuttx/configs/ea3152/src/up_boot.c @@ -75,7 +75,7 @@ void lpc31_boardinitialize(void) { /* Initialize configured, external memory resources */ -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM lpc31_meminitialize(); #endif diff --git a/nuttx/configs/ea3152/src/up_mem.c b/nuttx/configs/ea3152/src/up_mem.c index 4f6c71e87..4ac716f06 100644 --- a/nuttx/configs/ea3152/src/up_mem.c +++ b/nuttx/configs/ea3152/src/up_mem.c @@ -59,7 +59,7 @@ #include "lpc31_mpmc.h" #include "ea3152_internal.h" -#ifdef CONFIG_LPC31_EXTSDRAM +#ifdef CONFIG_ARCH_EXTDRAM /**************************************************************************** * Pre-processor Definitions @@ -356,4 +356,4 @@ void lpc31_meminitialize(void) lpc31_sdraminitialize(); } -#endif /* CONFIG_LPC31_EXTSDRAM */ +#endif /* CONFIG_ARCH_EXTDRAM */ diff --git a/nuttx/configs/open1788/Kconfig b/nuttx/configs/open1788/Kconfig new file mode 100644 index 000000000..08df7b38d --- /dev/null +++ b/nuttx/configs/open1788/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_OPEN1788 +endif diff --git a/nuttx/configs/open1788/README.txt b/nuttx/configs/open1788/README.txt new file mode 100644 index 000000000..144be5242 --- /dev/null +++ b/nuttx/configs/open1788/README.txt @@ -0,0 +1,38 @@ +README.txt +========== + +This README file discusses the port of NuttX to the WaveShare Open1788 board: +See http://wvshare.com/product/Open1788-Standard.htm. This board features the +NXP LPC1788 MCU + +CONTENTS +======== + + o Configuration + +CONFIGURURATION +=============== + + ostest + ------ + This configuration directory, performs a simple OS test using + apps/examples/ostest. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + diff --git a/nuttx/configs/open1788/ostest/Make.defs b/nuttx/configs/open1788/ostest/Make.defs new file mode 100644 index 000000000..d6e1f1a9c --- /dev/null +++ b/nuttx/configs/open1788/ostest/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/open1788k/ostest/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + MAXOPTIMIZATION = -O2 +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps.sh + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + diff --git a/nuttx/configs/open1788/ostest/defconfig b/nuttx/configs/open1788/ostest/defconfig new file mode 100644 index 000000000..69c480344 --- /dev/null +++ b/nuttx/configs/open1788/ostest/defconfig @@ -0,0 +1,604 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# +CONFIG_NUTTX_NEWCONFIG=y + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_SYMBOLS is not set + +# +# System Type +# +# CONFIG_ARCH_8051 is not set +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_LM is not set +CONFIG_ARCH_CHIP_LPC17XX=y +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +CONFIG_ARCH_CORTEXM3=y +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="lpc17xx" +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARMV7M_MPU is not set +CONFIG_BOARD_LOOPSPERMSEC=8079 +# CONFIG_ARCH_CALIBRATION is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y + +# +# LPC17xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC1751 is not set +# CONFIG_ARCH_CHIP_LPC1752 is not set +# CONFIG_ARCH_CHIP_LPC1754 is not set +# CONFIG_ARCH_CHIP_LPC1756 is not set +# CONFIG_ARCH_CHIP_LPC1758 is not set +# CONFIG_ARCH_CHIP_LPC1759 is not set +# CONFIG_ARCH_CHIP_LPC1764 is not set +# CONFIG_ARCH_CHIP_LPC1765 is not set +# CONFIG_ARCH_CHIP_LPC1766 is not set +# CONFIG_ARCH_CHIP_LPC1767 is not set +# CONFIG_ARCH_CHIP_LPC1768 is not set +# CONFIG_ARCH_CHIP_LPC1769 is not set +# CONFIG_ARCH_CHIP_LPC1773 is not set +# CONFIG_ARCH_CHIP_LPC1774 is not set +# CONFIG_ARCH_CHIP_LPC1776 is not set +# CONFIG_ARCH_CHIP_LPC1777 is not set +# CONFIG_ARCH_CHIP_LPC1778 is not set +# CONFIG_ARCH_CHIP_LPC1785 is not set +# CONFIG_ARCH_CHIP_LPC1786 is not set +# CONFIG_ARCH_CHIP_LPC1787 is not set +CONFIG_ARCH_CHIP_LPC1788=y +CONFIG_ARCH_FAMILY_LPC178X=y + +# +# LPC17xx Peripheral Support +# +CONFIG_LPC17_MAINOSC=y +CONFIG_LPC17_PLL0=y +CONFIG_LPC17_PLL1=y +# CONFIG_LPC17_ETHERNET is not set +# CONFIG_LPC17_USBHOST is not set +# CONFIG_LPC17_USBDEV is not set +CONFIG_LPC17_UART0=y +# CONFIG_LPC17_UART1 is not set +# CONFIG_LPC17_UART2 is not set +# CONFIG_LPC17_UART3 is not set +# CONFIG_LPC17_CAN1 is not set +# CONFIG_LPC17_CAN2 is not set +# CONFIG_LPC17_SPI is not set +# CONFIG_LPC17_SSP0 is not set +# CONFIG_LPC17_SSP1 is not set +# CONFIG_LPC17_I2C0 is not set +# CONFIG_LPC17_I2C1 is not set +# CONFIG_LPC17_I2C2 is not set +# CONFIG_LPC17_I2S is not set +# CONFIG_LPC17_TMR0 is not set +# CONFIG_LPC17_TMR1 is not set +# CONFIG_LPC17_TMR2 is not set +# CONFIG_LPC17_TMR3 is not set +# CONFIG_LPC17_RIT is not set +# CONFIG_LPC17_PWM is not set +# CONFIG_LPC17_MCPWM is not set +# CONFIG_LPC17_QEI is not set +# CONFIG_LPC17_RTC is not set +# CONFIG_LPC17_WDT is not set +# CONFIG_LPC17_ADC is not set +# CONFIG_LPC17_DAC is not set +# CONFIG_LPC17_GPDMA is not set +# CONFIG_LPC17_FLASH is not set + +# +# Serial driver options +# +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_UART0_FLOWCONTROL is not set + +# +# ADC driver options +# + +# +# CAN driver options +# +# CONFIG_GPIO_IRQ is not set + +# +# I2C driver options +# + +# +# Ethernet driver options +# + +# +# USB device driver options +# + +# +# USB host driver options +# + +# +# External Memory Configuration +# +CONFIG_ARCH_HAVE_EXTNAND=y +CONFIG_ARCH_HAVE_EXTNOR=y +CONFIG_ARCH_HAVE_EXTDRAM=y +CONFIG_ARCH_HAVE_EXTSRAM0=y +CONFIG_ARCH_EXTNAND=y +CONFIG_ARCH_EXTNANDSIZE=134217728 +CONFIG_ARCH_EXTNOR=y +CONFIG_ARCH_EXTNORSIZE=4194304 +CONFIG_ARCH_EXTDRAM=y +CONFIG_ARCH_EXTDRAMSIZE=67108864 +CONFIG_ARCH_EXTDRAMHEAP=y +CONFIG_ARCH_EXTSRAM0=y +CONFIG_ARCH_EXTSRAM0SIZE=131072 +CONFIG_ARCH_EXTSRAM0HEAP=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_IRQPRIO=y +# CONFIG_CUSTOM_STACK is not set +# CONFIG_ADDRENV is not set +CONFIG_ARCH_HAVE_VFORK=y +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set + +# +# Board Settings +# +CONFIG_DRAM_START=0x10000000 +CONFIG_DRAM_SIZE=65536 +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_OPEN1788=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="open1788" + +# +# Common Board Options +# + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_MSEC_PER_TICK=10 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_INSTRUMENTATION is not set +CONFIG_TASK_NAME_SIZE=0 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=15 +CONFIG_DEV_CONSOLE=y +# CONFIG_MUTEX_TYPES is not set +# CONFIG_PRIORITY_INHERITANCE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_WAITPID is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +CONFIG_USER_ENTRYPOINT="ostest_main" +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_CLOCK is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_POLL=y + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Sizes of configurable things (0 disables) +# +CONFIG_MAX_TASKS=16 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 + +# +# Device Drivers +# +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_PWM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_ARCH_HAVE_UART0=y +CONFIG_MCU_SERIAL=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set + +# +# Networking Support +# +# CONFIG_NET is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_FS_RAMMAP is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_GRAN is not set + +# +# Binary Formats +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Helper Functions +# +# CONFIG_LIB_KBDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CDCACM is not set +# CONFIG_EXAMPLES_COMPOSITE is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_LCDRW is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXCONSOLE is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +# CONFIG_EXAMPLES_OSTEST_BUILTIN is not set +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PASHELLO is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UIP is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBMSC is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Interpreters +# + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_DHCPC is not set +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_RESOLV is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_UIPLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# ModBus +# + +# +# FreeModbus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# System NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# I2C tool +# + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# readline() +# +# CONFIG_SYSTEM_READLINE is not set + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set diff --git a/nuttx/configs/open1788/ostest/setenv.sh b/nuttx/configs/open1788/ostest/setenv.sh new file mode 100755 index 000000000..ecbc9ef1c --- /dev/null +++ b/nuttx/configs/open1788/ostest/setenv.sh @@ -0,0 +1,73 @@ +#!/bin/bash +# configs/open1788/ostest/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# The Olimex-lpc1766stk/tools directory +export LPCTOOL_DIR="${WD}/configs/olimex-lpc1766stk/tools" + +# Add the path to the toolchain and tools directory to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/open1788/scripts/ld.script b/nuttx/configs/open1788/scripts/ld.script new file mode 100755 index 000000000..a4ca9cf80 --- /dev/null +++ b/nuttx/configs/open1788/scripts/ld.script @@ -0,0 +1,135 @@ +/**************************************************************************** + * configs/open1788/scripts/ld.script + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20020000 at bank0 second. And 16Kb + * at 0x20040000 on bank1. + * Here we assume that .data and .bss will all fit + * into the 64Kb CPU SRAM address range. + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + PSRAM0 (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Peripheral SRAM Bank 0 */ + PSRAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 16K /* Peripheral SRAM Bank 1 */ +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > FLASH + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > FLASH + + .ARM.extab : { + *(.ARM.extab*) + } > FLASH + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > FLASH + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > FLASH + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + .psram0 (NOLOAD) : + { + *(.psram0) + . = ALIGN(4) + } > PSRAM0 + + + .psram1 (NOLOAD) : + { + *(.psram0) + . = ALIGN(4) + } > PSRAM1 + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} -- cgit v1.2.3 From 070651221f4f60c2074e7641affa10e2b8714f07 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 19 Jan 2013 16:40:43 +0000 Subject: Add split package logic to improve TCP send performance with delayed ACKs git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5538 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 + apps/examples/ftpd/Makefile | 2 +- nuttx/ChangeLog | 2 + nuttx/configs/olimex-lpc1766stk/nsh/defconfig | 14 ++++ nuttx/net/Kconfig | 35 +++++++++- nuttx/net/send.c | 99 ++++++++++++++++++++++++++- 6 files changed, 150 insertions(+), 4 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index ba8dec613..a445c2024 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -488,3 +488,5 @@ * apps/nshlib/nsh_fileapp.c: Add the ability to execute a file from a file system using posix_spawn(). * apps/builtin/: Extensions from Mike Smith. + * apps/examples/ftpd/Makefile: Name ftpd_start is not the name of + the entrypoint. Should be ftpd_main (from Yan T.) diff --git a/apps/examples/ftpd/Makefile b/apps/examples/ftpd/Makefile index dd18d5043..61752931c 100644 --- a/apps/examples/ftpd/Makefile +++ b/apps/examples/ftpd/Makefile @@ -80,7 +80,7 @@ $(COBJS): %$(OBJEXT): %.c ifeq ($(CONFIG_NSH_BUILTIN_APPS),y) $(BUILTIN_REGISTRY)$(DELIM)ftpd_start.bdat: $(DEPCONFIG) Makefile - $(call REGISTER,ftpd_start,SCHED_PRIORITY_DEFAULT,2048,ftpd_start) + $(call REGISTER,ftpd_start,SCHED_PRIORITY_DEFAULT,2048,ftpd_main) $(BUILTIN_REGISTRY)$(DELIM)ftpd_stop.bdat: $(DEPCONFIG) Makefile $(call REGISTER,ftpd_stop,SCHED_PRIORITY_DEFAULT,2048,ftpd_stop) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index a5bcaf1bc..122187410 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3987,3 +3987,5 @@ * configs/open1788: Board configuration for the Wave Share Open1788 board. Still fragmentary (contribnuted by Rommel Marcelo, adapted to use kconfig-frontends. + * net/send(): Add logic to work around delayed ACKs by splitting + packets (contributed by Yan T.). diff --git a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig index 0f16933b8..c77f3f0c2 100755 --- a/nuttx/configs/olimex-lpc1766stk/nsh/defconfig +++ b/nuttx/configs/olimex-lpc1766stk/nsh/defconfig @@ -193,6 +193,10 @@ CONFIG_NET_PRIORITY=0 # USB host driver options # +# +# External Memory Configuration +# + # # Architecture Options # @@ -396,6 +400,10 @@ CONFIG_NET_NACTIVESOCKETS=16 CONFIG_NET_SOCKOPTS=y CONFIG_NET_BUFSIZE=562 # CONFIG_NET_TCPURGDATA is not set + +# +# TCP/IP Networking +# CONFIG_NET_TCP=y CONFIG_NET_TCP_CONNS=8 CONFIG_NET_MAX_LISTENPORTS=8 @@ -403,6 +411,12 @@ CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 CONFIG_NET_NTCP_READAHEAD_BUFFERS=16 CONFIG_NET_TCP_RECVDELAY=0 # CONFIG_NET_TCPBACKLOG is not set +CONFIG_NET_TCP_SPLIT=y +CONFIG_NET_TCP_SPLIT_SIZE=40 + +# +# UDP Networking +# CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y CONFIG_NET_UDP_CONNS=8 diff --git a/nuttx/net/Kconfig b/nuttx/net/Kconfig index d4ea8befb..6a084914f 100644 --- a/nuttx/net/Kconfig +++ b/nuttx/net/Kconfig @@ -97,14 +97,14 @@ config NET_TCPURGDATA compiled in. Urgent data (out-of-band data) is a rarely used TCP feature that is very seldom would be required. +menu "TCP/IP Networking" + config NET_TCP bool "TCP/IP Networking" default n ---help--- TCP support on or off -endif - if NET_TCP config NET_TCP_CONNS int "Number of TCP/IP connections" @@ -164,7 +164,36 @@ config NET_TCPBACKLOG Incoming connections pend in a backlog until accept() is called. The size of the backlog is selected when listen() is called. +config NET_TCP_SPLIT + bool "Enable packet splitting" + default n + ---help--- + send() will not return until the the transfer has been ACKed by the + recipient. But under RFC 1122, the host need not ACK each packet + immediately; the host may wait for 500 MS before ACKing. This + combination can cause very slow performance with small transfers are + made to an RFC 1122 client. However, the RFC 1122 must ACK at least + every second (odd) packet. + + This option enables logic to trick the RFC 1122 host be exploiting + this last RFC 1122 requirement: If an odd number of packets were to + be sent, then send() will split the last even packet to guarantee + that an even number of packets will be sent and the RFC 1122 host + will ACK the final packet immediately. + +if NET_TCP_SPLIT + +config NET_TCP_SPLIT_SIZE + int "Split size threshold" + default 40 + ---help--- + Packets of this size or smaller than this will not be split. + endif +endif +endmenu + +menu "UDP Networking" config NET_UDP bool "UDP Networking" @@ -193,6 +222,7 @@ config NET_BROADCAST Incoming UDP broadcast support endif +endmenu config NET_ICMP bool "ICMP networking support" @@ -321,3 +351,4 @@ config SLIP_DEFPRIO The priority of the SLIP RX and TX tasks. Default: 128 endif +endif diff --git a/nuttx/net/send.c b/nuttx/net/send.c index 8a5154191..b75a864e3 100644 --- a/nuttx/net/send.c +++ b/nuttx/net/send.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/send.c * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,7 +42,9 @@ #include #include + #include +#include #include #include #include @@ -62,6 +64,10 @@ * Definitions ****************************************************************************/ +#if defined(CONFIG_NET_TCP_SPLIT) && !defined(CONFIG_NET_TCP_SPLIT_SIZE) +# define CONFIG_NET_TCP_SPLIT_SIZE 40 +#endif + #define TCPBUF ((struct uip_tcpip_hdr *)&dev->d_buf[UIP_LLH_LEN]) /**************************************************************************** @@ -85,6 +91,9 @@ struct send_s #if defined(CONFIG_NET_SOCKOPTS) && !defined(CONFIG_DISABLE_CLOCK) uint32_t snd_time; /* last send time for determining timeout */ #endif +#if defined(CONFIG_NET_TCP_SPLIT) + bool snd_odd; /* True: Odd packet in pair transaction */ +#endif }; /**************************************************************************** @@ -200,6 +209,14 @@ static uint16_t send_interrupt(struct uip_driver_s *dev, void *pvconn, pstate->snd_sent = pstate->snd_acked; +#if defined(CONFIG_NET_TCP_SPLIT) + /* Reset the the even/odd indicator to even since we need to + * retransmit. + */ + + pstate->snd_odd = false; +#endif + /* Fall through to re-send data from the last that was ACKed */ } @@ -242,6 +259,86 @@ static uint16_t send_interrupt(struct uip_driver_s *dev, void *pvconn, /* Get the amount of data that we can send in the next packet */ uint32_t sndlen = pstate->snd_buflen - pstate->snd_sent; + + +#if defined(CONFIG_NET_TCP_SPLIT) + + /* RFC 1122 states that a host may delay ACKing for up to 500ms but + * must respond to every second segment). This logic here will trick + * the RFC 1122 recipient into responding sooner. This logic will be + * activated if: + * + * 1. An even number of packets has been send (where zero is an even + * number), + * 2. There is more data be sent (more than or equal to + * CONFIG_NET_TCP_SPLIT_SIZE), but + * 3. Not enough data for two packets. + * + * Then we will split the remaining, single packet into two partial + * packets. This will stimulate the RFC 1122 not into ACKing sooner. + * + * Check if there is more data to be sent (more than or equal to + * CONFIG_NET_TCP_SPLIT_SIZE): + */ + + if (sndlen >= CONFIG_NET_TCP_SPLIT_SIZE) + { + /* sndlen is the number of bytes remaining to be sent. + * uip_mss(conn) will return the number of bytes that can sent + * in one packet. The difference, then, is the number of bytes + * that would be sent in the next packet after this one. + */ + + int32_t next_sndlen = sndlen - uip_mss(conn); + + /* Is this the even packet in the packet pair transaction? */ + + if (!pstate->snd_odd) + { + /* next_sndlen <= 0 means that the entire remaining data + * could fit into this single packet. This is condition + * in which we must do the split. + */ + + if (next_sndlen <= 0) + { + /* Split so that there will be an odd packet. Here + * we know that 0 < sndlen <= MSS + */ + + sndlen = (sndlen / 2) + 1; + } + } + + /* No... this is the odd packet in the packet pair transaction */ + + else + { + /* Will there be another (even) packet afer this one? + * (next_sndlen > 0) Will the split conidition occur on that + * next, even packet? ((next_sndlen - uip_mss(conn)) < 0) If + * so, then perform the split now to avoid the case where the + * byte count is less than CONFIG_NET_TCP_SPLIT_SIZE on the + * next pair. + */ + + if (next_sndlen > 0 && (next_sndlen - uip_mss(conn)) < 0) + { + /* Here, we know that sndlen must be MSS <= sndlen <= 2*MSS + * and so (sndlen / 2) is <= MSS. + */ + + sndlen /= 2; + } + } + } + + /* Toggle the even/odd indicator */ + + pstate->snd_odd ^= true; + +#endif /* CONFIG_NET_TCP_SPLIT */ + if (sndlen > uip_mss(conn)) { sndlen = uip_mss(conn); -- cgit v1.2.3 From 1094575ce544860bc66b7c88d6b5eaf419d5ed7d Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 19 Jan 2013 19:18:44 +0000 Subject: Fix a bug where recv[from]() would hang when remote host gracefully closed connection git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5539 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 4 ++++ nuttx/net/recvfrom.c | 24 +++++++++++++++++++++++- nuttx/net/send.c | 2 +- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 122187410..80944db66 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3989,3 +3989,7 @@ Marcelo, adapted to use kconfig-frontends. * net/send(): Add logic to work around delayed ACKs by splitting packets (contributed by Yan T.). + * net/recvfrom(): Fix a bug. When the host closes a connection + (gracefully). recv[from]() returned success and the closure + was never detected. Hmmm.. I don't know why the network monitor + did not catch this event. This is an important bug fix. diff --git a/nuttx/net/recvfrom.c b/nuttx/net/recvfrom.c index 6bfbd31ad..679b5e8ce 100644 --- a/nuttx/net/recvfrom.c +++ b/nuttx/net/recvfrom.c @@ -83,7 +83,7 @@ struct recvfrom_s FAR struct sockaddr_in *rf_from; /* Address of sender */ #endif size_t rf_recvlen; /* The received length */ - int rf_result; /* OK:success, failure:negated errno */ + int rf_result; /* Success:OK, failure:negated errno */ }; #endif /* CONFIG_NET_UDP || CONFIG_NET_TCP */ @@ -553,6 +553,8 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, else if ((flags & (UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT)) != 0) { + FAR struct socket *psock = 0; + nllvdbg("error\n"); /* Stop further callbacks */ @@ -563,9 +565,29 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, /* If the peer gracefully closed the connection, then return zero * (end-of-file). Otherwise, report a not-connected error + * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was + * gracefully disconnected + * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was + * rudely disconnected */ + psock = pstate->rf_sock; if ((flags & UIP_CLOSE) != 0) + { + psock->s_flags &= ~_SF_CONNECTED; + psock->s_flags |= _SF_CLOSED; + } + else + { + psock->s_flags &= ~(_SF_CONNECTED |_SF_CLOSED); + } + + /* If no data has been received, then return ENOTCONN. + * Otherwise, let this return success. The failure will + * be reported the next time that recv[from]() is called. + */ + + if (pstate->rf_recvlen > 0) { pstate->rf_result = 0; } diff --git a/nuttx/net/send.c b/nuttx/net/send.c index b75a864e3..8c07b391c 100644 --- a/nuttx/net/send.c +++ b/nuttx/net/send.c @@ -324,7 +324,7 @@ static uint16_t send_interrupt(struct uip_driver_s *dev, void *pvconn, if (next_sndlen > 0 && (next_sndlen - uip_mss(conn)) < 0) { - /* Here, we know that sndlen must be MSS <= sndlen <= 2*MSS + /* Here, we know that sndlen must be MSS < sndlen <= 2*MSS * and so (sndlen / 2) is <= MSS. */ -- cgit v1.2.3 From 598b4b28793536198ffd145b895e2821334332da Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 19 Jan 2013 19:45:08 +0000 Subject: Minor tweak to last bugfix git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5540 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/net/recvfrom.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/nuttx/net/recvfrom.c b/nuttx/net/recvfrom.c index 679b5e8ce..ac8065f81 100644 --- a/nuttx/net/recvfrom.c +++ b/nuttx/net/recvfrom.c @@ -563,12 +563,18 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, pstate->rf_cb->priv = NULL; pstate->rf_cb->event = NULL; - /* If the peer gracefully closed the connection, then return zero - * (end-of-file). Otherwise, report a not-connected error - * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was - * gracefully disconnected - * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was - * rudely disconnected + /* Check if the peer gracefully closed the connection. We need + * these flags in case we return zero (below) to remember the + * state of the connection. + * + * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was + * gracefully disconnected + * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was + * rudely disconnected + * + * These flag settings are probably not necessary if + * CONFIG_NET_TCP_RECVDELAY == 0; in that case we know that + * pstate->rf_recvlen == 0 and we will always return -ENOTCONN. */ psock = pstate->rf_sock; @@ -587,6 +593,7 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, * be reported the next time that recv[from]() is called. */ +#if CONFIG_NET_TCP_RECVDELAY > 0 if (pstate->rf_recvlen > 0) { pstate->rf_result = 0; @@ -595,6 +602,9 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, { pstate->rf_result = -ENOTCONN; } +#else + pstate->rf_result = -ENOTCONN; +#endif /* Wake up the waiting thread */ -- cgit v1.2.3 From 28a0cf4aa03e0a43d63492844ef3f3eee9da84a5 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 20 Jan 2013 00:41:33 +0000 Subject: Yet another repair for the previouis botched recvfrom() fix; Fix telnet driver: It needs to break out of the read loop if 0 (meaning not conneced) of a value < 0 (an error) is encountered. git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5541 42af7a65-404d-4744-a932-0658087f49c3 --- apps/ChangeLog.txt | 2 ++ apps/netutils/telnetd/telnetd_driver.c | 18 ++++++++++++-- nuttx/ChangeLog | 3 +++ nuttx/net/recvfrom.c | 43 ++++++++++++++++++++-------------- 4 files changed, 46 insertions(+), 20 deletions(-) diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index a445c2024..bcc0ac172 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -490,3 +490,5 @@ * apps/builtin/: Extensions from Mike Smith. * apps/examples/ftpd/Makefile: Name ftpd_start is not the name of the entrypoint. Should be ftpd_main (from Yan T.) + * apps/netutils/telnetd/telnetd_driver: Was stuck in a loop if + recv[from]() ever returned a value <= 0. diff --git a/apps/netutils/telnetd/telnetd_driver.c b/apps/netutils/telnetd/telnetd_driver.c index 1183a2f70..274fde370 100644 --- a/apps/netutils/telnetd/telnetd_driver.c +++ b/apps/netutils/telnetd/telnetd_driver.c @@ -558,6 +558,8 @@ static ssize_t telnetd_read(FAR struct file *filep, FAR char *buffer, size_t len { if (priv->td_pending > 0) { + /* Process the buffered telnet data */ + FAR const char *src = &priv->td_rxbuffer[priv->td_offset]; ret = telnetd_receive(priv, src, priv->td_pending, buffer, len); } @@ -568,13 +570,25 @@ static ssize_t telnetd_read(FAR struct file *filep, FAR char *buffer, size_t len { ret = psock_recv(&priv->td_psock, priv->td_rxbuffer, CONFIG_TELNETD_RXBUFFER_SIZE, 0); + + /* Did we receive anything? */ + if (ret > 0) { - /* Process the received telnet data */ + /* Yes.. Process the newly received telnet data */ telnetd_dumpbuffer("Received buffer", priv->td_rxbuffer, ret); ret = telnetd_receive(priv, priv->td_rxbuffer, ret, buffer, len); } + + /* Otherwise the peer closed the connection (ret == 0) or an error + * occurred (ret < 0). + */ + + else + { + break; + } } } while (ret == 0); @@ -746,7 +760,7 @@ FAR char *telnetd_driver(int sd, FAR struct telnetd_s *daemon) * instance resided in the daemon's socket array). */ - psock = sockfd_socket(sd); + psock = sockfd_socket(sd); if (!psock) { nlldbg("Failed to convert sd=%d to a socket structure\n", sd); diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 80944db66..77441dd21 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3993,3 +3993,6 @@ (gracefully). recv[from]() returned success and the closure was never detected. Hmmm.. I don't know why the network monitor did not catch this event. This is an important bug fix. + * net/recvfrom(): Fix a introduced with the last bugfix. If + the peer does an orderly closure of the socket, report 0 not + -ENOTCONN diff --git a/nuttx/net/recvfrom.c b/nuttx/net/recvfrom.c index ac8065f81..a1a6742c5 100644 --- a/nuttx/net/recvfrom.c +++ b/nuttx/net/recvfrom.c @@ -571,40 +571,47 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, * gracefully disconnected * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was * rudely disconnected - * - * These flag settings are probably not necessary if - * CONFIG_NET_TCP_RECVDELAY == 0; in that case we know that - * pstate->rf_recvlen == 0 and we will always return -ENOTCONN. */ psock = pstate->rf_sock; if ((flags & UIP_CLOSE) != 0) { + /* Report that the connection was gracefully closed */ + psock->s_flags &= ~_SF_CONNECTED; psock->s_flags |= _SF_CLOSED; + + /* This case should always return success (zero)! The value of + * rf_recvlen, if zero, will indicate that the connection was + * gracefully closed. + */ + + pstate->rf_result = 0; } else { + /* Report that the connection was rudely lost */ + psock->s_flags &= ~(_SF_CONNECTED |_SF_CLOSED); - } - /* If no data has been received, then return ENOTCONN. - * Otherwise, let this return success. The failure will - * be reported the next time that recv[from]() is called. - */ + /* If no data has been received, then return ENOTCONN. + * Otherwise, let this return success. The failure will + * be reported the next time that recv[from]() is called. + */ #if CONFIG_NET_TCP_RECVDELAY > 0 - if (pstate->rf_recvlen > 0) - { - pstate->rf_result = 0; - } - else - { - pstate->rf_result = -ENOTCONN; - } + if (pstate->rf_recvlen > 0) + { + pstate->rf_result = 0; + } + else + { + pstate->rf_result = -ENOTCONN; + } #else - pstate->rf_result = -ENOTCONN; + pstate->rf_result = -ENOTCONN; #endif + } /* Wake up the waiting thread */ -- cgit v1.2.3 From 70cab4d7975291861185e38a12a75f6c232fae56 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sun, 20 Jan 2013 17:21:42 +0000 Subject: Centralize TCP loss-of-connection bit twiddling git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5542 42af7a65-404d-4744-a932-0658087f49c3 --- apps/netutils/telnetd/telnetd_driver.c | 9 +++- nuttx/net/net_internal.h | 62 ++++++++++++----------- nuttx/net/net_monitor.c | 93 ++++++++++++++++++++++------------ nuttx/net/recvfrom.c | 37 ++++---------- nuttx/net/send.c | 11 ++-- 5 files changed, 120 insertions(+), 92 deletions(-) diff --git a/apps/netutils/telnetd/telnetd_driver.c b/apps/netutils/telnetd/telnetd_driver.c index 274fde370..1b04bfbe5 100644 --- a/apps/netutils/telnetd/telnetd_driver.c +++ b/apps/netutils/telnetd/telnetd_driver.c @@ -1,7 +1,7 @@ /**************************************************************************** * apps/netutils/telnetd_driver.c * - * Copyright (C) 2007, 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * This is a leverage of similar logic from uIP which has a compatible BSD @@ -593,6 +593,13 @@ static ssize_t telnetd_read(FAR struct file *filep, FAR char *buffer, size_t len } while (ret == 0); + /* Return: + * + * ret > 0: The number of characters copied into the user buffer by + * telnetd_receive(). + * ret <= 0: Loss of connection or error events reported by recv(). + */ + return ret; } diff --git a/nuttx/net/net_internal.h b/nuttx/net/net_internal.h index ed2f12aa7..0726c7a80 100644 --- a/nuttx/net/net_internal.h +++ b/nuttx/net/net_internal.h @@ -1,7 +1,7 @@ /**************************************************************************** * net/net_internal.h * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -139,94 +139,96 @@ * Public Variables ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /* List of registered ethernet device drivers */ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -extern struct uip_driver_s *g_netdevices; +EXTERN struct uip_driver_s *g_netdevices; #endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - /* net_sockets.c *************************************************************/ -EXTERN int sockfd_allocate(int minsd); -EXTERN void sock_release(FAR struct socket *psock); -EXTERN void sockfd_release(int sockfd); -EXTERN FAR struct socket *sockfd_socket(int sockfd); +int sockfd_allocate(int minsd); +void sock_release(FAR struct socket *psock); +void sockfd_release(int sockfd); +FAR struct socket *sockfd_socket(int sockfd); /* net_connect.c *************************************************************/ #ifdef CONFIG_NET_TCP -EXTERN int net_startmonitor(FAR struct socket *psock); -EXTERN void net_stopmonitor(FAR struct uip_conn *conn); +int net_startmonitor(FAR struct socket *psock); +void net_stopmonitor(FAR struct uip_conn *conn); +void net_lostconnection(FAR struct socket *psock, uint16_t flags); #endif /* net_close.c ***************************************************************/ -EXTERN int psock_close(FAR struct socket *psock); +int psock_close(FAR struct socket *psock); /* sockopt support ***********************************************************/ #if defined(CONFIG_NET_SOCKOPTS) && !defined(CONFIG_DISABLE_CLOCK) -EXTERN int net_timeo(uint32_t start_time, socktimeo_t timeo); -EXTERN socktimeo_t net_timeval2dsec(struct timeval *tv); -EXTERN void net_dsec2timeval(uint16_t dsec, struct timeval *tv); +int net_timeo(uint32_t start_time, socktimeo_t timeo); +socktimeo_t net_timeval2dsec(FAR struct timeval *tv); +void net_dsec2timeval(uint16_t dsec, FAR struct timeval *tv); #endif /* net_register.c ************************************************************/ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN void netdev_seminit(void); -EXTERN void netdev_semtake(void); -EXTERN void netdev_semgive(void); +void netdev_seminit(void); +void netdev_semtake(void); +void netdev_semgive(void); #endif /* net_findbyname.c **********************************************************/ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN FAR struct uip_driver_s *netdev_findbyname(const char *ifname); +FAR struct uip_driver_s *netdev_findbyname(FAR const char *ifname); #endif /* net_findbyaddr.c **********************************************************/ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN FAR struct uip_driver_s *netdev_findbyaddr(const uip_ipaddr_t *raddr); +FAR struct uip_driver_s *netdev_findbyaddr(FAR const uip_ipaddr_t *raddr); #endif /* net_txnotify.c ************************************************************/ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN void netdev_txnotify(const uip_ipaddr_t *raddr); +void netdev_txnotify(const uip_ipaddr_t *raddr); #endif /* net_count.c ***************************************************************/ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN int netdev_count(void); +int netdev_count(void); #endif /* net_arptimer.c ************************************************************/ #ifdef CONFIG_NET_ARP -EXTERN void arptimer_init(void); +void arptimer_init(void); #else # define arptimer_init() #endif /* send.c ********************************************************************/ -EXTERN ssize_t psock_send(FAR struct socket *psock, const void *buf, - size_t len, int flags); +ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, + int flags); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/net/net_monitor.c b/nuttx/net/net_monitor.c index 4bdae4ccf..1eeb4bd27 100644 --- a/nuttx/net/net_monitor.c +++ b/nuttx/net/net_monitor.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/net_monitor.c * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -67,7 +67,6 @@ static void connection_event(struct uip_conn *conn, uint16_t flags); * Some connection related event has occurred * * Parameters: - * dev The sructure of the network driver that caused the interrupt * conn The connection structure associated with the socket * flags Set of events describing why the callback was invoked * @@ -79,7 +78,7 @@ static void connection_event(struct uip_conn *conn, uint16_t flags); * ****************************************************************************/ -static void connection_event(struct uip_conn *conn, uint16_t flags) +static void connection_event(FAR struct uip_conn *conn, uint16_t flags) { FAR struct socket *psock = (FAR struct socket *)conn->connection_private; @@ -87,37 +86,11 @@ static void connection_event(struct uip_conn *conn, uint16_t flags) { nllvdbg("flags: %04x s_flags: %02x\n", flags, psock->s_flags); - /* These loss-of-connection events may be reported: - * - * UIP_CLOSE: The remote host has closed the connection - * UIP_ABORT: The remote host has aborted the connection - * UIP_TIMEDOUT: Connection aborted due to too many retransmissions. - * - * And we need to set these two socket status bits appropriately: - * - * _SF_CONNECTED==1 && _SF_CLOSED==0 - the socket is connected - * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was gracefully disconnected - * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was rudely disconnected - */ + /* UIP_CLOSE, UIP_ABORT, or UIP_TIMEDOUT: Loss-of-connection events */ - if ((flags & UIP_CLOSE) != 0) - { - /* The peer gracefully closed the connection. Marking the - * connection as disconnected will suppress some subsequent - * ENOTCONN errors from receive. A graceful disconnection is - * not handle as an error but as an "end-of-file" - */ - - psock->s_flags &= ~_SF_CONNECTED; - psock->s_flags |= _SF_CLOSED; - } - else if ((flags & (UIP_ABORT|UIP_TIMEDOUT)) != 0) + if ((flags & (UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT)) != 0) { - /* The loss of connection was less than graceful. This will (eventually) - * be reported as an ENOTCONN error. - */ - - psock->s_flags &= ~(_SF_CONNECTED |_SF_CLOSED); + net_lostconnection(psock, flags); } /* UIP_CONNECTED: The socket is successfully connected */ @@ -184,4 +157,60 @@ void net_stopmonitor(FAR struct uip_conn *conn) conn->connection_event = NULL; } +/**************************************************************************** + * Name: net_lostconnection + * + * Description: + * Called when a loss-of-connection event has occurred. + * + * Parameters: + * psock The TCP socket structure associated. + * flags Set of connection events events + * + * Returned Value: + * None + * + * Assumptions: + * Running at the interrupt level + * + ****************************************************************************/ + +void net_lostconnection(FAR struct socket *psock, uint16_t flags) +{ + DEBUGASSERT(psock) + + /* These loss-of-connection events may be reported: + * + * UIP_CLOSE: The remote host has closed the connection + * UIP_ABORT: The remote host has aborted the connection + * UIP_TIMEDOUT: Connection aborted due to too many retransmissions. + * + * And we need to set these two socket status bits appropriately: + * + * _SF_CONNECTED==1 && _SF_CLOSED==0 - the socket is connected + * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was gracefully disconnected + * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was rudely disconnected + */ + + if ((flags & UIP_CLOSE) != 0) + { + /* The peer gracefully closed the connection. Marking the + * connection as disconnected will suppress some subsequent + * ENOTCONN errors from receive. A graceful disconnection is + * not handle as an error but as an "end-of-file" + */ + + psock->s_flags &= ~_SF_CONNECTED; + psock->s_flags |= _SF_CLOSED; + } + else if ((flags & (UIP_ABORT|UIP_TIMEDOUT)) != 0) + { + /* The loss of connection was less than graceful. This will (eventually) + * be reported as an ENOTCONN error. + */ + + psock->s_flags &= ~(_SF_CONNECTED |_SF_CLOSED); + } +} + #endif /* CONFIG_NET && CONFIG_NET_TCP */ diff --git a/nuttx/net/recvfrom.c b/nuttx/net/recvfrom.c index a1a6742c5..6864dace3 100644 --- a/nuttx/net/recvfrom.c +++ b/nuttx/net/recvfrom.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/recvfrom.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -464,10 +464,11 @@ static inline void recvfrom_tcpsender(struct uip_driver_s *dev, struct recvfrom_ ****************************************************************************/ #ifdef CONFIG_NET_TCP -static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, - void *pvpriv, uint16_t flags) +static uint16_t recvfrom_tcpinterrupt(FAR struct uip_driver_s *dev, + FAR void *conn, FAR void *pvpriv, + uint16_t flags) { - struct recvfrom_s *pstate = (struct recvfrom_s *)pvpriv; + FAR struct recvfrom_s *pstate = (struct recvfrom_s *)pvpriv; nllvdbg("flags: %04x\n", flags); @@ -553,9 +554,7 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, else if ((flags & (UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT)) != 0) { - FAR struct socket *psock = 0; - - nllvdbg("error\n"); + nllvdbg("Lost connection\n"); /* Stop further callbacks */ @@ -563,24 +562,14 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, pstate->rf_cb->priv = NULL; pstate->rf_cb->event = NULL; - /* Check if the peer gracefully closed the connection. We need - * these flags in case we return zero (below) to remember the - * state of the connection. - * - * _SF_CONNECTED==0 && _SF_CLOSED==1 - the socket was - * gracefully disconnected - * _SF_CONNECTED==0 && _SF_CLOSED==0 - the socket was - * rudely disconnected - */ + /* Handle loss-of-connection event */ - psock = pstate->rf_sock; - if ((flags & UIP_CLOSE) != 0) - { - /* Report that the connection was gracefully closed */ + net_lostconnection(pstate->rf_sock, flags); - psock->s_flags &= ~_SF_CONNECTED; - psock->s_flags |= _SF_CLOSED; + /* Check if the peer gracefully closed the connection. */ + if ((flags & UIP_CLOSE) != 0) + { /* This case should always return success (zero)! The value of * rf_recvlen, if zero, will indicate that the connection was * gracefully closed. @@ -590,10 +579,6 @@ static uint16_t recvfrom_tcpinterrupt(struct uip_driver_s *dev, void *conn, } else { - /* Report that the connection was rudely lost */ - - psock->s_flags &= ~(_SF_CONNECTED |_SF_CLOSED); - /* If no data has been received, then return ENOTCONN. * Otherwise, let this return success. The failure will * be reported the next time that recv[from]() is called. diff --git a/nuttx/net/send.c b/nuttx/net/send.c index 8c07b391c..79dfef4ec 100644 --- a/nuttx/net/send.c +++ b/nuttx/net/send.c @@ -227,6 +227,8 @@ static uint16_t send_interrupt(struct uip_driver_s *dev, void *pvconn, /* Report not connected */ nllvdbg("Lost connection\n"); + + net_lostconnection(pstate->snd_sock, flags); pstate->snd_sent = -ENOTCONN; goto end_wait; } @@ -275,10 +277,13 @@ static uint16_t send_interrupt(struct uip_driver_s *dev, void *pvconn, * 3. Not enough data for two packets. * * Then we will split the remaining, single packet into two partial - * packets. This will stimulate the RFC 1122 not into ACKing sooner. + * packets. This will stimulate the RFC 1122 peer to ACK sooner. * - * Check if there is more data to be sent (more than or equal to - * CONFIG_NET_TCP_SPLIT_SIZE): + * Don't try to split very small packets (less than CONFIG_NET_TCP_SPLIT_SIZE). + * Only the first even packet and the last odd packets could have + * sndlen less than CONFIG_NET_TCP_SPLIT_SIZE. The value of sndlen on + * the last even packet is guaranteed to be at least MSS/2 by the + * logic below. */ if (sndlen >= CONFIG_NET_TCP_SPLIT_SIZE) -- cgit v1.2.3 From 724252768c6978d7f776895811a3e30cb3e77368 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Sat, 19 Jan 2013 12:58:02 +1100 Subject: stdio: added vdprintf() for printf to a file descriptor --- nuttx/libc/lib_internal.h | 1 + nuttx/libc/stdio/Make.defs | 2 +- nuttx/libc/stdio/lib_rawprintf.c | 15 ++++++++ nuttx/libc/stdio/lib_vdprintf.c | 81 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 nuttx/libc/stdio/lib_vdprintf.c diff --git a/nuttx/libc/lib_internal.h b/nuttx/libc/lib_internal.h index c09c751d4..efe895465 100644 --- a/nuttx/libc/lib_internal.h +++ b/nuttx/libc/lib_internal.h @@ -140,6 +140,7 @@ int lib_vsprintf(FAR struct lib_outstream_s *obj, /* Defined lib_rawprintf.c */ int lib_rawvprintf(const char *src, va_list ap); +int lib_rawvdprintf(int fd, const char *fmt, va_list ap); /* Defined lib_lowprintf.c */ diff --git a/nuttx/libc/stdio/Make.defs b/nuttx/libc/stdio/Make.defs index e18ab0220..0670724da 100644 --- a/nuttx/libc/stdio/Make.defs +++ b/nuttx/libc/stdio/Make.defs @@ -59,7 +59,7 @@ CSRCS += lib_fopen.c lib_fclose.c lib_fread.c lib_libfread.c lib_fseek.c \ lib_gets.c lib_fwrite.c lib_libfwrite.c lib_fflush.c \ lib_libflushall.c lib_libfflush.c lib_rdflush.c lib_wrflush.c \ lib_fputc.c lib_puts.c lib_fputs.c lib_ungetc.c lib_vprintf.c \ - lib_fprintf.c lib_vfprintf.c lib_stdinstream.c lib_stdoutstream.c \ + lib_fprintf.c lib_vfprintf.c lib_vdprintf.c lib_stdinstream.c lib_stdoutstream.c \ lib_perror.c lib_feof.c lib_ferror.c lib_clearerr.c endif diff --git a/nuttx/libc/stdio/lib_rawprintf.c b/nuttx/libc/stdio/lib_rawprintf.c index 98bbbea05..ddbb84f94 100644 --- a/nuttx/libc/stdio/lib_rawprintf.c +++ b/nuttx/libc/stdio/lib_rawprintf.c @@ -149,3 +149,18 @@ int lib_rawprintf(const char *fmt, ...) return ret; } + + +/**************************************************************************** + * Name: lib_rawvdprintf + ****************************************************************************/ + +int lib_rawvdprintf(int fd, const char *fmt, va_list ap) +{ + /* Wrap the fd in a stream object and let lib_vsprintf + * do the work. + */ + struct lib_rawoutstream_s rawoutstream; + lib_rawoutstream(&rawoutstream, fd); + return lib_vsprintf(&rawoutstream.public, fmt, ap); +} diff --git a/nuttx/libc/stdio/lib_vdprintf.c b/nuttx/libc/stdio/lib_vdprintf.c new file mode 100644 index 000000000..932342e1c --- /dev/null +++ b/nuttx/libc/stdio/lib_vdprintf.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * libc/stdio/lib_vdprintf.c + * + * Copyright (C) 2007-2009, 2011 Andrew Tridgell. All rights reserved. + * Author: Andrew Tridgell + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "lib_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Type Declarations + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Constant Data + ****************************************************************************/ + +/**************************************************************************** + * Global Variables + ****************************************************************************/ + +/**************************************************************************** + * Private Constant Data + ****************************************************************************/ + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int vdprintf(int fd, FAR const char *fmt, va_list ap) +{ + return lib_rawvdprintf(fd, fmt, ap); +} -- cgit v1.2.3 From 96fa586589da450c9cc9669ed94fdcb0ee5add2d Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Mon, 14 Jan 2013 16:20:20 +1100 Subject: px4: enable APPS_BINDIR support useful for APM startup script --- nuttx/configs/px4fmu/nsh/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nuttx/configs/px4fmu/nsh/defconfig b/nuttx/configs/px4fmu/nsh/defconfig index 0b27b552e..b6de5864b 100755 --- a/nuttx/configs/px4fmu/nsh/defconfig +++ b/nuttx/configs/px4fmu/nsh/defconfig @@ -1045,3 +1045,6 @@ CONFIG_PTHREAD_STACK_MIN=512 CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_HEAP_BASE= CONFIG_HEAP_SIZE= + +# enable bindir +CONFIG_APPS_BINDIR=y -- cgit v1.2.3 From 09ddf7f1b3e79bd37227520610847fbcf94187ce Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Mon, 21 Jan 2013 08:16:03 +1100 Subject: ROMFS: add support for EXTERNAL_SCRIPTS this adds support for an EXTERNAL_SCRIPTS directory, to complement the EXTERNAL_APPS option. It allows external apps to install scripts in ROMFS --- ROMFS/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ROMFS/Makefile b/ROMFS/Makefile index ec4221b93..3b024de06 100644 --- a/ROMFS/Makefile +++ b/ROMFS/Makefile @@ -35,6 +35,10 @@ ROMFS_FSSPEC := $(SRCROOT)/scripts/rcS~init.d/rcS \ $(SRCROOT)/mixers/FMU_octo_+.mix~mixers/FMU_octo_+.mix \ $(SRCROOT)/logging/logconv.m~logging/logconv.m +# the EXTERNAL_SCRIPTS variable is used to add out of tree scripts +# to ROMFS. +ROMFS_FSSPEC += $(EXTERNAL_SCRIPTS) + # # Add the PX4IO firmware to the spec if someone has dropped it into the # source directory, or otherwise specified its location. -- cgit v1.2.3 From ff35e5a58347f4d03d097f5939f19751ed82ae06 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Mon, 21 Jan 2013 08:15:13 +1100 Subject: if rc.APM is installed, run it --- ROMFS/scripts/rcS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/ROMFS/scripts/rcS b/ROMFS/scripts/rcS index 69d791da5..660bf61e9 100755 --- a/ROMFS/scripts/rcS +++ b/ROMFS/scripts/rcS @@ -69,6 +69,16 @@ else fi fi +# if this is an APM build then there will be a rc.APM script +# from an EXTERNAL_SCRIPTS build option +if [ -f /etc/init.d/rc.APM ] +then + echo Running rc.APM + # if APM startup is successful then nsh will exit + sh /etc/init.d/rc.APM +fi + + # # If we are still in flight mode, work out what airframe # configuration we have and start up accordingly. -- cgit v1.2.3 From aa88fc315e563345c4a9ab2667563c02edb967aa Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 21 Jan 2013 14:17:11 +0000 Subject: poll was not checking if the socket was still connected git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5543 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/net/net_poll.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/nuttx/net/net_poll.c b/nuttx/net/net_poll.c index 815c6a71d..2e73bd73c 100644 --- a/nuttx/net/net_poll.c +++ b/nuttx/net/net_poll.c @@ -125,16 +125,22 @@ static uint16_t poll_interrupt(struct uip_driver_s *dev, FAR void *conn, if ((flags & UIP_POLL) != 0) { - eventset |= POLLOUT & fds->events; + eventset |= (POLLOUT & fds->events); } - /* Check for a loss of connection events */ + /* Check for a loss of connection events. + * + * REVISIT: Need to call net_lostconnection() here, but don't have + * the psock instance. What should we do? + */ if ((flags & (UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT)) != 0) { - eventset |= (POLLERR|POLLHUP); + eventset |= (POLLERR | POLLHUP); } + /* Awaken the caller of poll() is requested event occurred. */ + if (eventset) { fds->revents |= eventset; @@ -192,9 +198,9 @@ static inline int net_pollsetup(FAR struct socket *psock, struct pollfd *fds) goto errout_with_irq; } - /* Initialize the callbcack structure */ + /* Initialize the callback structure */ - cb->flags = UIP_NEWDATA|UIP_BACKLOG|UIP_POLL|UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT; + cb->flags = (UIP_NEWDATA|UIP_BACKLOG|UIP_POLL|UIP_CLOSE|UIP_ABORT|UIP_TIMEDOUT); cb->priv = (FAR void *)fds; cb->event = poll_interrupt; @@ -212,13 +218,23 @@ static inline int net_pollsetup(FAR struct socket *psock, struct pollfd *fds) if (!sq_empty(&conn->readahead)) #endif { - fds->revents = fds->events & POLLIN; - if (fds->revents != 0) - { - /* If data is available now, the signal the poll logic */ + fds->revents |= (POLLOUT & fds->events); + } - sem_post(fds->sem); - } + /* Check for a loss of connection events */ + + if (!_SS_ISCONNECTED(psock->s_flags)) + { + fds->revents |= (POLLERR | POLLHUP); + } + + /* Check if any requested events are already in effect */ + + if (fds->revents != 0) + { + /* Yes.. then signal the poll logic */ + + sem_post(fds->sem); } uip_unlock(flags); -- cgit v1.2.3 From 41b7f883e55c3ad085e4e538b5703369ae6e59d2 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 21 Jan 2013 16:56:29 +0000 Subject: LM3S OpenOCD configuration from Jose Pablo Carballo git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5544 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/configs/lm3s6965-ek/README.txt | 80 +++++++++++++++ nuttx/configs/lm3s6965-ek/tools/lm3s6965-ek.cfg | 131 ++++++++++++++++++++++++ nuttx/configs/lm3s6965-ek/tools/oocd.sh | 52 ++++++++++ nuttx/drivers/lcd/README.txt | 72 ++++++++----- nuttx/include/nuttx/lcd/ug-2864ambag01.h | 1 + nuttx/include/nuttx/lcd/ug-2864hsweg01.h | 1 + nuttx/include/nuttx/lcd/ug-9664hswag01.h | 1 + 7 files changed, 311 insertions(+), 27 deletions(-) create mode 100644 nuttx/configs/lm3s6965-ek/tools/lm3s6965-ek.cfg create mode 100755 nuttx/configs/lm3s6965-ek/tools/oocd.sh diff --git a/nuttx/configs/lm3s6965-ek/README.txt b/nuttx/configs/lm3s6965-ek/README.txt index 77f034bf5..94cf4d902 100644 --- a/nuttx/configs/lm3s6965-ek/README.txt +++ b/nuttx/configs/lm3s6965-ek/README.txt @@ -15,6 +15,7 @@ Contents NXFLAT Toolchain USB Device Controller Functions OLED + Using OpenOCD and GDB with an FT2232 JTAG emulator Stellaris LM3S6965 Evaluation Kit Configuration Options Configurations @@ -103,6 +104,85 @@ OLED display. Some tweaks to drivers/lcd/p14201.c would be required to support that LCD. +Using OpenOCD and GDB with an FT2232 JTAG emulator +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Building OpenOCD under Cygwin: + + Refer to configs/olimex-lpc1766stk/README.txt + + Installing OpenOCD in Linux: + + sudo apt-get install openocd + + Helper Scripts. + + I have been using the on-board FT2232 JTAG/SWD/SWO interface. OpenOCD + requires a configuration file. I keep the one I used last here: + + configs/lm3s6965-ek/tools/lm3s6965-ek.cfg + + However, the "correct" configuration script to use with OpenOCD may + change as the features of OpenOCD evolve. So you should at least + compare that lm3s6965-ek.cfg file with configuration files in + /usr/share/openocd/scripts. As of this writing, the configuration + files of interest were: + + /usr/share/openocd/scripts/interface/luminary.cfg + /usr/share/openocd/scripts/board/ek-lm3s6965.cfg + /usr/share/openocd/scripts/target/stellaris.cfg + + There is also a script on the tools/ directory that I use to start + the OpenOCD daemon on my system called oocd.sh. That script will + probably require some modifications to work in another environment: + + - Possibly the value of OPENOCD_PATH and TARGET_PATH + - It assumes that the correct script to use is the one at + configs/lm3s6965-ek/tools/lm3s6965-ek.cfg + + Starting OpenOCD + + Then you should be able to start the OpenOCD daemon like: + + configs/lm3s6965-ek/tools/oocd.sh $PWD + + Connecting GDB + + Once the OpenOCD daemon has been started, you can connect to it via + GDB using the following GDB command: + + arm-nuttx-elf-gdb + (gdb) target remote localhost:3333 + + NOTE: The name of your GDB program may differ. For example, with the + CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb. + + After starting GDB, you can load the NuttX ELF file: + + (gdb) symbol-file nuttx + (gdb) monitor reset + (gdb) monitor halt + (gdb) load nuttx + + NOTES: + 1. Loading the symbol-file is only useful if you have built NuttX to + include debug symbols (by setting CONFIG_DEBUG_SYMBOLS=y in the + .config file). + 2. The MCU must be halted prior to loading code using 'mon reset' + as described below. + + OpenOCD will support several special 'monitor' commands. These + GDB commands will send comments to the OpenOCD monitor. Here + are a couple that you will need to use: + + (gdb) monitor reset + (gdb) monitor halt + + NOTES: + 1. The MCU must be halted using 'mon halt' prior to loading code. + 2. Reset will restart the processor after loading code. + 3. The 'monitor' command can be abbreviated as just 'mon'. + Development Environment ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/configs/lm3s6965-ek/tools/lm3s6965-ek.cfg b/nuttx/configs/lm3s6965-ek/tools/lm3s6965-ek.cfg new file mode 100644 index 000000000..a82aa4cb9 --- /dev/null +++ b/nuttx/configs/lm3s6965-ek/tools/lm3s6965-ek.cfg @@ -0,0 +1,131 @@ +# +# TI/Luminary Stellaris LM3S6965 Evaluation Kits +# +# http://www.luminarymicro.com/products/lm3s6965_ethernet_evaluation_kit.html + +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using it in JTAG mode, as done here. + +# Interface configuration + +interface ft2232 +ft2232_device_desc "Stellaris Evaluation Board" +ft2232_layout luminary_icdi +ft2232_vid_pid 0x0403 0xbcd9 + +# Board configuration + +# 20k working area +set WORKAREASIZE 0x5000 +set CHIPNAME lm3s6965 + +# Target configuration + +# Some devices have errata in returning their device class. +# DEVICECLASS is provided as a manual override +# Manual setting of a device class of 0xff is not allowed + +global _DEVICECLASS + +if { [info exists DEVICECLASS ] } { + set _DEVICECLASS $DEVICECLASS +} else { + set _DEVICECLASS 0xff +} + +# Luminary chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# For now we ignore the SPI and UART options, which +# are usable only for ISP style initial flash programming. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s +} + +# CPU TAP ID 0x1ba00477 for early Sandstorm parts +# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2 +# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil) +# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest) +# ... we'll ignore the JTAG version field, rather than list every +# chip revision that turns up. +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3ba00477 +} + +# SWD DAP, and JTAG TAP, take same params for now; +# ... even though SWD ignores all except TAPID, and +# JTAG shouldn't need anything more then irlen. (and TAPID). +swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ + -expected-id $_CPUTAPID -ignore-version + +if { [info exists WORKAREASIZE ] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # default to 8K working area + set _WORKAREASIZE 0x2000 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu + +# 8K working area at base of ram, not backed up +# +# NOTE: you may need or want to reconfigure the work area; +# some parts have just 6K, and you may want to use other +# addresses (at end of mem not beginning) or back it up. +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE + +# JTAG speed ... slow enough to work with a 12 MHz RC oscillator; +# LM3S parts don't support RTCK +# +# NOTE: this may be increased by a reset-init handler, after it +# configures and enables the PLL. Or you might need to decrease +# this, if you're using a slower clock. +adapter_khz 500 + +source [find mem_helper.tcl] + +$_TARGETNAME configure -event reset-start { + adapter_khz 500 + + # + # When nRST is asserted on most Stellaris devices, it clears some of + # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + # and OpenOCD depends on those TRMs. So we won't use SRST on those + # chips. (Only power-on reset should affect debug state, beyond a + # few specified bits; not the chip's nRST input, wired to SRST.) + # + # REVISIT current errata specs don't seem to cover this issue. + # Do we have more details than this email? + # https://lists.berlios.de/pipermail + # /openocd-development/2008-August/003065.html + # + + global _DEVICECLASS + + if {$_DEVICECLASS != 0xff} { + set device_class $_DEVICECLASS + } else { + set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)] + } + + if {$device_class == 0 || $device_class == 1 || $device_class == 3} { + # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ + cortex_m3 reset_config sysresetreq + } else { + # Tempest and newer default to using NVIC VECTRESET + # this does mean a reset-init event handler is required to reset + # any peripherals + cortex_m3 reset_config vectreset + } +} + +# flash configuration ... autodetects sizes, autoprobed +flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME + diff --git a/nuttx/configs/lm3s6965-ek/tools/oocd.sh b/nuttx/configs/lm3s6965-ek/tools/oocd.sh new file mode 100755 index 000000000..28bcc48a7 --- /dev/null +++ b/nuttx/configs/lm3s6965-ek/tools/oocd.sh @@ -0,0 +1,52 @@ +#!/bin/sh +# +# See configs/lm3s6965-ek/README.txt for information about +# this file. + +TOPDIR=$1 +USAGE="$0 [-d]" +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment +# the following to run directly from the build directory +#OPENOCD_PATH="/home/OpenOCD/openocd/src" +#TARGET_PATH="/home/OpenOCD/openocd/tcl" +OPENOCD_PATH="/usr/bin" +TARGET_PATH="/usr/share/openocd/scripts" + +# Assume a Unix development environment. Uncomment to use a Windows +# like environment +#OPENOCD_EXE=openocd.exe +OPENOCD_EXE=openocd +OPENOCD_CFG="${TOPDIR}/configs/lm3s6965-ek/tools/ek-lm3s6965.cfg" +OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}" + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +if [ ! -d ${OPENOCD_PATH} ]; then + echo "OpenOCD path does not exist: ${OPENOCD_PATH}" + exit 1 +fi +if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then + echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f ${OPENOCD_CFG} ]; then + echo "OpenOCD config file does not exist: ${OPENOCD_CFG}" + exit 1 +fi + +echo "Starting OpenOCD" +cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; } +${OPENOCD_EXE} ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" + diff --git a/nuttx/drivers/lcd/README.txt b/nuttx/drivers/lcd/README.txt index 77ae536b2..198be18a1 100644 --- a/nuttx/drivers/lcd/README.txt +++ b/nuttx/drivers/lcd/README.txt @@ -119,47 +119,65 @@ that support additional LCDs. LCD drivers in the configuration directory if they support some differ LCD interface (such as a parallel interface) that makes then less re-usable: - configs/compal_e99/src/ssd1783.c + SSD1783 Drivers: - SSD1783 + configs/compal_e99/src/ssd1783.c - configs/hymini-stm32v/src/ssd1289.c. See also drivers/lcd/ssd1298.c - above. + SSD1289 Drivers: + + configs/hymini-stm32v/src/ssd1289.c. See also drivers/lcd/ssd1298.c + above. + configs/stm32f4discovery/src/up_ssd1289.c. This examples is the + bottom half for the SSD1289 driver at drivers/lcd/ssd1289.c + configs/hymini-stm32v/src/ssd1289.c. See also drivers/lcd/ssd1298.c + above. + configs/shenzhou/src/up_ssd1289.c + + kwikstik-k40: - SSD1289 + configs/kwikstik-k40/src/up_lcd.c. Don't waste your time. This is + just a stub. - configs/kwikstik-k40/src/up_lcd.c. Don't waste your time. This is - just a stub. + Nokia LCD Drivers: - configs/olimex-lpc1766stk/src/up_lcd.c. This examples is the - bottom half for the SSD1289 driver at drivers/lcd/nokia6100.c. - This was never completedly debugged ... there are probably issues - with that nasty 9-bit SPI interfaces. + configs/olimex-lpc1766stk/src/up_lcd.c. This examples is the + bottom half for the driver at drivers/lcd/nokia6100.c. + This was never completedly debugged ... there are probably issues + with that nasty 9-bit SPI interfaces. - configs/sam3u-ek/src/up_lcd.c - - The SAM3U-EK developement board features a TFT/Transmissive color - LCD module with touch-screen, FTM280C12D, with integrated driver IC - HX8346. + HX8346: + + configs/sam3u-ek/src/up_lcd.c. The SAM3U-EK developement board features + a TFT/Transmissive color LCD module with touch-screen, FTM280C12D, + with integrated driver IC HX8346. - configs/skp16c26/src/up_lcd.c. Untested alphanumeric LCD driver. + ILI93xx and Similar: - configs/stm3210e-eval/src/up_lcd.c + configs/stm3210e-eval/src/up_lcd.c. This driver supports the following + LCDs: - This driver supports the following LCDs: + 1. Ampire AM-240320LTNQW00H + 2. Orise Tech SPFD5408B + 3. RenesasSP R61580 - 1. Ampire AM-240320LTNQW00H - 2. Orise Tech SPFD5408B - 3. RenesasSP R61580 + configs/stm3220g-eval/src/up_lcd.c and configs/stm3240g-eval/src/up_lcd.c. + AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) and + AM-240320D5TOQW01H (LCD_ILI9325) + configs/shenzhou/src/up_ili93xx.c. Another ILI93xx driver. - configs/stm3220g-eval/src/up_lcd.c and configs/stm3240g-eval/src/up_lcd.c. - AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) and - AM-240320D5TOQW01H (LCD_ILI9325) + OLEDs: - configs/stm32f4discovery/src/up_ssd1289.c. This examples is the - bottom half for the SSD1289 driver at drivers/lcd/ssd1289.c + configs/stm32f4discovery/src/up_ug2864ambag01.c + configs/stm32f4discovery/src/up_ug2864hsweg01.c + configs/zp214xpa/src/up_ug2864ambag01.c + + Alphnumeric Displays: + + configs/skp16c26/src/up_lcd.c. Untested alphanumeric LCD driver. + configs/stm32f4discovery/src/up_lcd1602.c graphics/ ========= See also the usage of the LCD driver in the graphics/ directory. + diff --git a/nuttx/include/nuttx/lcd/ug-2864ambag01.h b/nuttx/include/nuttx/lcd/ug-2864ambag01.h index deb568981..86362d773 100644 --- a/nuttx/include/nuttx/lcd/ug-2864ambag01.h +++ b/nuttx/include/nuttx/lcd/ug-2864ambag01.h @@ -1,5 +1,6 @@ /************************************************************************************** * include/nuttx/lcd/ug-2864ambag01.h + * * Driver for Univision UG-2864AMBAG01 OLED display (wih SH1101A controller) in SPI * mode * diff --git a/nuttx/include/nuttx/lcd/ug-2864hsweg01.h b/nuttx/include/nuttx/lcd/ug-2864hsweg01.h index bbefd39be..e38741967 100644 --- a/nuttx/include/nuttx/lcd/ug-2864hsweg01.h +++ b/nuttx/include/nuttx/lcd/ug-2864hsweg01.h @@ -1,5 +1,6 @@ /************************************************************************************** * include/nuttx/lcd/ug-2864hsweg01.h + * * Driver for Univision UG-2864HSWEG01 OLED display (wih SSD1306 controller) in SPI * mode * diff --git a/nuttx/include/nuttx/lcd/ug-9664hswag01.h b/nuttx/include/nuttx/lcd/ug-9664hswag01.h index b470e0895..a60b5ed67 100644 --- a/nuttx/include/nuttx/lcd/ug-9664hswag01.h +++ b/nuttx/include/nuttx/lcd/ug-9664hswag01.h @@ -1,5 +1,6 @@ /**************************************************************************** * include/nuttx/lcd/ug-9664hswag01.h + * * Driver for the Univision UG-9664HSWAG01 Display with the Solomon Systech * SSD1305 LCD controller. * -- cgit v1.2.3 From e504d643fc23cefe61340e4d3a75d6e80f4b76fb Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 21 Jan 2013 22:46:37 +0000 Subject: Beginning of support for LCD1602 git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5545 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 5 + nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h | 3 +- nuttx/configs/pcblogic-pic32mx/src/up_lcd1602.c | 374 ++++++++++++++++++++++++ nuttx/configs/pic32mx7mmb/src/up_mio283qt2.c | 2 +- nuttx/drivers/lcd/README.txt | 10 +- nuttx/include/nuttx/lcd/hd4478ou.h | 118 ++++++++ 6 files changed, 508 insertions(+), 4 deletions(-) create mode 100644 nuttx/configs/pcblogic-pic32mx/src/up_lcd1602.c create mode 100644 nuttx/include/nuttx/lcd/hd4478ou.h diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 77441dd21..41f38bd91 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3996,3 +3996,8 @@ * net/recvfrom(): Fix a introduced with the last bugfix. If the peer does an orderly closure of the socket, report 0 not -ENOTCONN + * configs/lm3s6965-ek/README.txt and tools/: Add an OpenOCD + configuration for the LM3S (from Jose Pablo Carballo). + * nuttx/lcd/hd4478ou.h and configs/pcblogic-pic32mx/src/up_lcd1602: + Start of support of LCD1602 alphanumeric LCD. I need a few + more parts before I can finish integrating this one. diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h index 745c56a3d..abfc3358b 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h @@ -157,7 +157,8 @@ # define PMP_MODE_MODE_SLAVE (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */ # define PMP_MODE_MODE_MODE2 (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */ # define PMP_MODE_MODE_MODE1 (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */ -#define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 8/16-bit mode */ +#define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 1=16-bit mode */ +#define PMP_MODE_MODE8 (0) /* 0=8-bit mode */ #define PMP_MODE_INCM_SHIFT (11) /* Bits 11-12: Increment Mode */ #define PMP_MODE_INCM_MASK (3 << PMP_MODE_INCM_SHIFT) # define PMP_MODE_INCM_NONE (0 << PMP_MODE_INCM_SHIFT) /* No incr or decr of addr */ diff --git a/nuttx/configs/pcblogic-pic32mx/src/up_lcd1602.c b/nuttx/configs/pcblogic-pic32mx/src/up_lcd1602.c new file mode 100644 index 000000000..3f99baee1 --- /dev/null +++ b/nuttx/configs/pcblogic-pic32mx/src/up_lcd1602.c @@ -0,0 +1,374 @@ +/**************************************************************************** + * configs/pcblocic-pic32mx/src/up_lcd1602.c + * + * This logic supports the connection of an LCD1602 LCD to the + * STM32F4Discovery board. The LCD1602 is based on the Hitachi HD44780U LCD + * controller + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + /* LCD pin mapping (see configs/pcblogic-pic32mx/README.txt) + * + * ----------------------------------- ---------- ---------------------------------- + * PIC32 LCD1602 UBW32 PIN + * PIN SIGNAL NAME PIN NAME(s) + * ----------------------------------- ---------- ---------------------------------- + * 1. Vss GND + * 2. Vdd Vcc (5V) + * 3. Vee To ground via 10K potentiometer + * 4 AN15/OCFB/PMALL/PMA0/CN12/RB15 4. RS PMA0, Selects registers + * 82 PMRD/CN14/RD5 5. RW PMRD/PMWR, Selects read or write + * 81 OC5/PMWR/CN13/RD4 6. E PMENB, Starts data read/write + * 93 PMD0/RE0 7. D0 PMD0 + * 94 PMD1/RE1 8. D1 PMD1 + * 98 PMD2/RE2 9. D2 PMD2 + * 99 PMD3/RE3 10. D3 PMD3 + * 100 PMD4/RE4 11. D4 PMD4 + * 3 PMD5/RE5 12. D5 PMD5 + * 4 PMD6/RE6 13. D6 PMD6 + * 5 PMD7/RE7 14. D7 PMD7 + * 15. A To Vcc (5V) via 10K potentiometer + * 16. K GND + * ----------------------------------- ---------- ---------------------------------- + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "pic32mx-pmp.h" +#include "pic32mx-int.h" +#include "pic32mx-internal.h" +#include "pcblogic-internal.h" + +#ifdef CONFIG_LCD_LCD1602 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_PIC32MX_PMP +# error "CONFIG_PIC32MX_PMP is required to use the LCD" +#endif + +/* Define CONFIG_DEBUG_LCD to enable detailed LCD debug output. Verbose debug must + * also be enabled. + */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_VERBOSE +# undef CONFIG_DEBUG_GRAPHICS +# undef CONFIG_DEBUG_LCD +#endif + +#ifndef CONFIG_DEBUG_VERBOSE +# undef CONFIG_DEBUG_LCD +#endif + +/* Pin configuratin *********************************************************/ +/* RB15, RS -- High values selects data */ + +#define GPIO_LCD_RS (GPIO_OUTPUT|GPIO_VALUE_ZERO|GPIO_PORTB|GPIO_PIN15) + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_LCD +# define lcddbg dbg +# define lcdvdbg vdbg +#else +# define lcddbg(x...) +# define lcdvdbg(x...) +#endif + +/**************************************************************************** + * Private Type Definition + ****************************************************************************/ + +struct lpc1620_s +{ + bool initialized; /* True: Completed initialization sequence */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static ssize_t lcd_read(FAR struct file *, FAR char *, size_t); +static ssize_t lcd_write(FAR struct file *, FAR const char *, size_t); +#ifndef CONFIG_DISABLE_POLL +static int lcd_poll(FAR struct file *filp, FAR struct pollfd *fds, + bool setup); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the driver state structure (there is no retained state information) */ + +static const struct file_operations g_lcd1602 = +{ + 0, /* open */ + 0, /* close */ + lcd_read, /* read */ + lcd_write, /* write */ + 0, /* seek */ + 0 /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , lcd_poll /* poll */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lcd_wrcommand + * + * Description: + * Configure to write an LCD command + * + ****************************************************************************/ + +static void lcd_wrcommand(uint8_t cmd) +{ + /* Address bit A0 is RS. Set the address latch to A0=0 */ + + putreg32(1, PIC32MX_PMP_ADDRCLR); + + /* And write the command to the data out register */ + + putreg32((uint32_t)cmd, PIC32MX_PMP_DOUT); +} + +/**************************************************************************** + * Name: lcd_wrdata + * + * Description: + * Configure to read or write LCD data + * + ****************************************************************************/ + +static void lcd_wrdata(uint8_t data) +{ + /* Address bit A0 is RS. Set the address latch to A0=1 */ + + putreg32(1, PIC32MX_PMP_ADDRSET); + + /* And write the data to the data out register */ + + putreg32((uint32_t)data, PIC32MX_PMP_DOUT); +} + +/**************************************************************************** + * Name: lcd_rddata + * + * Description: + * Configure to read or write LCD data + * + ****************************************************************************/ + +static uint8_t lcd_rddata(void) +{ + /* Address bit A0 is RS. Set the address latch to A0=1 */ + + putreg32(1, PIC32MX_PMP_ADDRSET); + + /* And read the data to the data in register */ + + return (uint8_t)getreg32(PIC32MX_PMP_DIN); +} + +/**************************************************************************** + * Name: lcd_read + ****************************************************************************/ + +static ssize_t lcd_read(FAR struct file *filp, FAR char *buffer, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + { + *buffer++ = lcd_rddata(); + } + + return len; +} + +/**************************************************************************** + * Name: lcd_write + ****************************************************************************/ + +static ssize_t lcd_write(FAR struct file *filp, FAR const char *buffer, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + { + uint8_t data = *buffer++; + lcd_wrdata(data); + } + + return len; +} + +/**************************************************************************** + * Name: lcd_poll + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int lcd_poll(FAR struct file *filp, FAR struct pollfd *fds, + bool setup) +{ + if (setup) + { + /* Data is always avaialble to be read */ + + fds->revents |= (fds->events & (POLLIN|POLLOUT)); + if (fds->revents != 0) + { + sem_post(fds->sem); + } + } + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lcd1602_initialize + * + * Description: + * Initialize the LCD1602 hardware and register the character driver. + * + ****************************************************************************/ + +int up_lcd1602_initialize(void) +{ + uint32_t regval; + int ret = OK; + + /* Only initialize the driver once. */ + + if (!g_lcd1602.initialized) + { + lcdvdbg("Initializing\n"); + + /* PMP Master mode configuration */ + /* Make sure that interrupts are disabled */ + + putreg32(INT_PMP, PIC32MX_INT_IEC1CLR); + + /* Stop and reset the PMP module and clear the mode and control registers. */ + + putreg32(0, PIC32MX_PMP_MODE); + putreg32(0, PIC32MX_PMP_AEN); + putreg32(0, PIC32MX_PMP_CON); + putreg32(0, PIC32MX_PMP_ADDR); + + /* Set LCD timing values, PMP master mode 3, 8-bit mode, no address + * increment, and no interrupts. + */ + + regval = (PMP_MODE_WAITE_RD(0) | PMP_MODE_WAITM(3) | PMP_MODE_WAITB_1TPB | + PMP_MODE_MODE_MODE1 | PMP_MODE_MODE8 | PMP_MODE_INCM_NONE | + PMP_MODE_IRQM_NONE); + putreg32(regval, PIC32MX_PMP_MODE); + + /* Enable the PMP for reading and writing + * PMRD/PMWR is active high (1=RD; 0=WR) + * PMENB is active high. + * No chip selects + * Address latch is active high + * Enable PMRD/PMWR, PMENB, and the PMP. + */ + + + regval = (PMP_CON_RDSP | PMP_CON_WRSP | PMP_CON_ALP | + PMP_CON_CSF_ADDR1415 | PMP_CON_PTRDEN | PMP_CON_PTWREN | + PMP_CON_ADRMUX_NONE | PMP_CON_ON); + putreg32(regval, PIC32MX_PMP_CON); + + /* Configure and enable the LCD */ + /* Wait > 15 milliseconds afer Vdd > 4.5V */ + + up_mdelay(100); + + /* Select the 8-bit interface. BF cannot be checked before this command. + * This needs to be done a few times with some magic delays. + */ + + lcd_wrcommand(HD4478OU_FUNC | HD4478OU_FUNC_DL8D | HD4478OU_FUNC_N1); + up_mdelay(50); + lcd_wrcommand(HD4478OU_FUNC | HD4478OU_FUNC_DL8D | HD4478OU_FUNC_N1); + up_udelay(50); + lcd_wrcommand(HD4478OU_FUNC | HD4478OU_FUNC_DL8D | HD4478OU_FUNC_N1); + lcd_wrcommand(HD4478OU_FUNC | HD4478OU_FUNC_DL8D | HD4478OU_FUNC_N1); + + /* Configure the display */ + + lcd_wrcommand(HD4478OU_DISPLAY); /* Display, cursor, and blink off */ + lcd_wrcommand(HD4478OU_CLEAR); /* Clear the display */ + lcd_wrcommand(HD4478OU_INPUT | HD4478OU_INPUT_INCR); /* Increment mode */ + lcd_wrcommand(HD4478OU_DISPLAY | HD4478OU_DISPLAY_ON); /* Display on, cursor and blink off */ + lcd_wrcommand(HD4478OU_DDRAM_AD(0)); /* Select DDRAM RAM AD=0 */ + + /* Register the LCD device driver */ + + ret = register_driver("/dev/lcd1602", &g_lcd1602, 0644, &g_lcd1602); + g_lcd1602.initialized = true; + } + + return ret; +} + +#endif /* CONFIG_LCD_LCD1602 */ diff --git a/nuttx/configs/pic32mx7mmb/src/up_mio283qt2.c b/nuttx/configs/pic32mx7mmb/src/up_mio283qt2.c index 22d6252a9..7ab4353c6 100644 --- a/nuttx/configs/pic32mx7mmb/src/up_mio283qt2.c +++ b/nuttx/configs/pic32mx7mmb/src/up_mio283qt2.c @@ -138,7 +138,7 @@ #define GPIO_LCD_RS (GPIO_OUTPUT|GPIO_VALUE_ZERO|GPIO_PORTB|GPIO_PIN15) - /* Debug ******************************************************************************/ +/* Debug ******************************************************************************/ #ifdef CONFIG_DEBUG_LCD # define lcddbg dbg diff --git a/nuttx/drivers/lcd/README.txt b/nuttx/drivers/lcd/README.txt index 198be18a1..0472043e6 100644 --- a/nuttx/drivers/lcd/README.txt +++ b/nuttx/drivers/lcd/README.txt @@ -151,6 +151,12 @@ that makes then less re-usable: a TFT/Transmissive color LCD module with touch-screen, FTM280C12D, with integrated driver IC HX8346. + HX8347: + + configs/pic32mx7mmb/src/up_mio283qt2.c. This driver is for the MI0283QT-2 + LCD from Multi-Inno Technology Co., Ltd. This LCD is based on the Himax + HX8347-D LCD controller. + ILI93xx and Similar: configs/stm3210e-eval/src/up_lcd.c. This driver supports the following @@ -171,10 +177,10 @@ that makes then less re-usable: configs/stm32f4discovery/src/up_ug2864hsweg01.c configs/zp214xpa/src/up_ug2864ambag01.c - Alphnumeric Displays: + Alphnumeric LCD Displays: configs/skp16c26/src/up_lcd.c. Untested alphanumeric LCD driver. - configs/stm32f4discovery/src/up_lcd1602.c + configs/pcblogic-pic32/src/up_lcd1602.c graphics/ ========= diff --git a/nuttx/include/nuttx/lcd/hd4478ou.h b/nuttx/include/nuttx/lcd/hd4478ou.h new file mode 100644 index 000000000..4bb93fca9 --- /dev/null +++ b/nuttx/include/nuttx/lcd/hd4478ou.h @@ -0,0 +1,118 @@ +/******************************************************************************************** + * include/nuttx/lcd/hd4478ou.h + * + * Definitions for the Hitachi HD44780U LCD controller (as used in the + * LCD1602). + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __INCLUDE_NUTTX_HD4478OU_H +#define __INCLUDE_NUTTX_HD4478OU_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ +/* Command set: + * + * RS=0 R/W=0 : Command + * RS=0 R/W=1 : Busy/AD, Read CT (see below) + * RS=1 R/W=0 : Write data to CGRAM or DDRAM + * RS=1 R/W=0 : Read data from CGRAM or DDRAM + */ + +#define HD4478OU_CLEAR (0x01) /* Screen Clear, Set AC to 0 */ +#define HD4478OU_RETURN (0x02) /* DDRAM AD=0, return */ +#define HD4478OU_INPUT (0x04) /* Set moving direction of cursor */ +# define HD4478OU_INPUT_SHIFT (1 << 0) /* Shift */ +# define HD4478OU_INPUT_INCR (1 << 1) /* Increment mode */ +# define HD4478OU_INPUT_DECR (0x00) /* Decrement mode */ +#define HD4478OU_DISPLAY (0x08) /* Set display, cursor, blink on/off */ +# define HD4478OU_DISPLAY_BLINK (1 << 0) /* Blink on/off */ +# define HD4478OU_DISPLAY_CURSOR (1 << 1) /* Cursor on/off */ +# define HD4478OU_DISPLAY_ON (1 << 2) /* Display on/off */ +#define HD4478OU_SHIFT (0x10) /* Remove cursor and whole diplay */ +# define HD4478OU_SHIFT_RIGHT (1 << 2) /* Shift right */ +# define HD4478OU_SHIFT_LEFT (0x00) /* Shift right */ +# define HD4478OU_SHIFT_DISPLAY (1 << 3) /* Display shift */ +# define HD4478OU_SHIFT_CURSOR (0x00) /* Cursor shift */ +#define HD4478OU_FUNC (0x20) /* Set DL, display line, font */ +# define HD4478OU_FUNC_F5x10 (1 << 2) /* 5x10 Style */ +# define HD4478OU_FUNC_F5x7 (0x00) /* 5x7 Style */ +# define HD4478OU_FUNC_N1 (1 << 3) /* N=2R */ +# define HD4478OU_FUNC_N0 (0x00) /* N=1R */ +# define HD4478OU_FUNC_DL8D (1 << 4) /* DL=8D, 8-bit interface */ +# define HD4478OU_FUNC_DL4D (0x00) /* DL=4D, 4-bit interface */ +#define HD4478OU_CGRAM_AD(a) (0x40|(a)) /* Set CGRAM AD, send receive data */ +#define HD4478OU_DDRAM_AD(a) (0x80|(a)) /* Set DDRAM AD, send receive data */ + +/* RS=0 R/W=1 : Execute internal function, read AD of CT */ + +#define HD4478OU_BUSY(bf,ac) ((bf) << 7 | (ac)) + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +/******************************************************************************************** + * Name: up_lcd1602_initialize + * + * Description: + * the LCD1602 is an HD4478OU-based LCD from Wave share. This function initializes the + * LCD1602 hardware and registers the character driver as /dev/lcd1602. + * + ********************************************************************************************/ + +int up_lcd1602_initialize(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_HD4478OU_H */ -- cgit v1.2.3 From 4742f55507b6e1392f459a2c228efb75b567b62e Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 22 Jan 2013 01:25:40 +0000 Subject: Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/Kconfig | 19 +- nuttx/arch/arm/include/armv7-m/irq.h | 141 +++-- nuttx/arch/arm/include/kinetis/chip.h | 850 ++++++++++++++++++++++++++++++ nuttx/arch/arm/include/lm/chip.h | 14 + nuttx/arch/arm/include/lm/irq.h | 24 +- nuttx/arch/arm/include/lm/lm3s_irq.h | 16 - nuttx/arch/arm/include/lpc17xx/chip.h | 14 + nuttx/arch/arm/include/lpc43xx/chip.h | 31 +- nuttx/arch/arm/include/sam3u/chip.h | 95 ++++ nuttx/arch/arm/include/stm32/chip.h | 10 + nuttx/arch/arm/src/armv7-m/up_hardfault.c | 8 +- nuttx/arch/arm/src/kinetis/chip.h | 797 +--------------------------- nuttx/arch/arm/src/kinetis/kinetis_irq.c | 43 +- nuttx/arch/arm/src/lm/chip.h | 16 +- nuttx/arch/arm/src/lm/lm_irq.c | 43 +- nuttx/arch/arm/src/lpc17xx/chip.h | 16 +- nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 43 +- nuttx/arch/arm/src/lpc43xx/chip.h | 19 +- nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 42 +- nuttx/arch/arm/src/sam3u/chip.h | 43 +- nuttx/arch/arm/src/sam3u/sam3u_irq.c | 43 +- nuttx/arch/arm/src/stm32/chip.h | 2 +- nuttx/arch/arm/src/stm32/stm32.h | 6 - nuttx/arch/arm/src/stm32/stm32_irq.c | 43 +- 24 files changed, 1399 insertions(+), 979 deletions(-) create mode 100644 nuttx/arch/arm/include/kinetis/chip.h create mode 100644 nuttx/arch/arm/include/sam3u/chip.h diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 36343e319..5709f890f 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -46,7 +46,6 @@ config ARCH_CHIP_KINETIS bool "Freescale Kinetis" select ARCH_CORTEXM4 select ARCH_HAVE_MPU - select ARCH_IRQPRIO select ARCH_HAVE_RAMFUNCS select ARCH_RAMFUNCS ---help--- @@ -55,7 +54,6 @@ config ARCH_CHIP_KINETIS config ARCH_CHIP_LM bool "TI Stellaris" select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- TI Stellaris LMS3 architecutres (ARM Cortex-M3) @@ -63,7 +61,6 @@ config ARCH_CHIP_LPC17XX bool "NXP LPC17xx" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NXP LPC17xx architectures (ARM Cortex-M3) @@ -95,7 +92,6 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_CMNVECTOR select ARMV7M_CMNVECTOR select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -103,7 +99,6 @@ config ARCH_CHIP_SAM3U bool "Atmel AT91SAM3U" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- Atmel AT91SAM3U architectures (ARM Cortex-M3) @@ -112,7 +107,6 @@ config ARCH_CHIP_STM32 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET - select ARCH_IRQPRIO ---help--- STMicro STM32 architectures (ARM Cortex-M3/4). @@ -136,9 +130,11 @@ config ARCH_ARM920T config ARCH_CORTEXM3 bool + select ARCH_IRQPRIO config ARCH_CORTEXM4 bool + select ARCH_IRQPRIO config ARCH_FAMILY string @@ -162,6 +158,17 @@ config ARCH_CHIP default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X +config ARMV7M_USEBASEPRI + bool "Use BASEPRI Register" + default n + depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 + ---help--- + Use the BASEPRI register to enable and disable able interrupts. By + default, the PRIMASK register is used for this purpose. This + usually results in hardfaults that are properly handling by the + RTOS. Using the BASEPRI register will avoid these hardfault. + That is needed primarily for integration with some toolchains. + config ARCH_HAVE_CMNVECTOR bool diff --git a/nuttx/arch/arm/include/armv7-m/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h index 606b3988f..9491e57c0 100644 --- a/nuttx/arch/arm/include/armv7-m/irq.h +++ b/nuttx/arch/arm/include/armv7-m/irq.h @@ -60,6 +60,10 @@ # include #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI +# include +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -130,64 +134,6 @@ struct xcptcontext #ifndef __ASSEMBLY__ -/* Disable IRQs */ - -static inline void irqdisable(void) inline_function; -static inline void irqdisable(void) -{ - __asm__ __volatile__ ("\tcpsid i\n"); -} - -/* Save the current primask state & disable IRQs */ - -static inline irqstate_t irqsave(void) inline_function; -static inline irqstate_t irqsave(void) -{ - unsigned short primask; - - /* Return the current value of primask register and set - * bit 0 of the primask register to disable interrupts - */ - - __asm__ __volatile__ - ( - "\tmrs %0, primask\n" - "\tcpsid i\n" - : "=r" (primask) - : - : "memory"); - - return primask; -} - -/* Enable IRQs */ - -static inline void irqenable(void) inline_function; -static inline void irqenable(void) -{ - __asm__ __volatile__ ("\tcpsie i\n"); -} - -/* Restore saved primask state */ - -static inline void irqrestore(irqstate_t primask) inline_function; -static inline void irqrestore(irqstate_t primask) -{ - /* If bit 0 of the primask is 0, then we need to restore - * interupts. - */ - - __asm__ __volatile__ - ( - "\ttst %0, #1\n" - "\tbne 1f\n" - "\tcpsie i\n" - "1:\n" - : - : "r" (primask) - : "memory"); -} - /* Get/set the primask register */ static inline uint8_t getprimask(void) inline_function; @@ -243,6 +189,85 @@ static inline void setbasepri(uint32_t basepri) : "memory"); } +/* Disable IRQs */ + +static inline void irqdisable(void) inline_function; +static inline void irqdisable(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); +#else + __asm__ __volatile__ ("\tcpsid i\n"); +#endif +} + +/* Save the current primask state & disable IRQs */ + +static inline irqstate_t irqsave(void) inline_function; +static inline irqstate_t irqsave(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + + uint8_t basepri = getbasepri(); + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); + return basepri; + +#else + + unsigned short primask; + + /* Return the current value of primask register and set + * bit 0 of the primask register to disable interrupts + */ + + __asm__ __volatile__ + ( + "\tmrs %0, primask\n" + "\tcpsid i\n" + : "=r" (primask) + : + : "memory"); + + return primask; +#endif +} + +/* Enable IRQs */ + +static inline void irqenable(void) inline_function; +static inline void irqenable(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(NVIC_SYSH_PRIORITY_MIN); +#else + __asm__ __volatile__ ("\tcpsie i\n"); +#endif +} + +/* Restore saved primask state */ + +static inline void irqrestore(irqstate_t flags) inline_function; +static inline void irqrestore(irqstate_t flags) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(flags); +#else + /* If bit 0 of the primask is 0, then we need to restore + * interupts. + */ + + __asm__ __volatile__ + ( + "\ttst %0, #1\n" + "\tbne 1f\n" + "\tcpsie i\n" + "1:\n" + : + : "r" (flags) + : "memory"); +#endif +} + /* Get/set IPSR */ static inline uint32_t getipsr(void) inline_function; diff --git a/nuttx/arch/arm/include/kinetis/chip.h b/nuttx/arch/arm/include/kinetis/chip.h new file mode 100644 index 000000000..cb686c5d6 --- /dev/null +++ b/nuttx/arch/arm/include/kinetis/chip.h @@ -0,0 +1,850 @@ +/************************************************************************************ + * arch/arm/include/kinetis/chip.h + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_CHIP_H +#define __ARCH_ARM_INCLUDE_KINETIS_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# else +# undef KINETIS_NCAN /* No CAN in 64-pin chips */ +# endif +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# undef KINETIS_NRNG /* No random number generator */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ +# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#else +# error "Unsupported Kinetis chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_CHIP_H */ diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h index 8293c7938..6b49fe2ce 100644 --- a/nuttx/arch/arm/include/lm/chip.h +++ b/nuttx/arch/arm/include/lm/chip.h @@ -108,6 +108,20 @@ # error "Capabilities not specified for this Stellaris chip" #endif +/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism + * will only look at the upper N bits of the 8-bit priority level (where N is 3 for + * the Stellaris family), so any prioritization must be performed in those bits. + * The default priority level is set to the middle value + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [5:7] set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h index 3b984a826..4f72e9824 100644 --- a/nuttx/arch/arm/include/lm/irq.h +++ b/nuttx/arch/arm/include/lm/irq.h @@ -43,6 +43,26 @@ #include #include +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Processor Exceptions (vectors 0-15) */ + +#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ + #if defined(CONFIG_ARCH_CHIP_LM3S) # include #elif defined(CONFIG_ARCH_CHIP_LM4F) @@ -51,10 +71,6 @@ # error "Unsupported Stellaris IRQ file" #endif -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - /* GPIO IRQs -- Note that support for individual GPIO ports can * be disabled in order to reduce the size of the implemenation. */ diff --git a/nuttx/arch/arm/include/lm/lm3s_irq.h b/nuttx/arch/arm/include/lm/lm3s_irq.h index a9d0640d9..e9cfe8bdc 100644 --- a/nuttx/arch/arm/include/lm/lm3s_irq.h +++ b/nuttx/arch/arm/include/lm/lm3s_irq.h @@ -51,22 +51,6 @@ * to handle mapping tables. */ -/* Processor Exceptions (vectors 0-15) */ - -#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ - /* External interrupts (vectors >= 16) */ #define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h index d2c436d35..c22c6aa60 100644 --- a/nuttx/arch/arm/include/lpc17xx/chip.h +++ b/nuttx/arch/arm/include/lpc17xx/chip.h @@ -362,6 +362,20 @@ # error "Unsupported LPC17xx chip" #endif +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/lpc43xx/chip.h b/nuttx/arch/arm/include/lpc43xx/chip.h index 220ce38d0..7ff787e48 100644 --- a/nuttx/arch/arm/include/lpc43xx/chip.h +++ b/nuttx/arch/arm/include/lpc43xx/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/lpc43xx/chip.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -542,6 +542,35 @@ # error "Unsupported LPC43xx chip" #endif +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. + * + * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt + * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4 + * programmable interrupt priorities. + */ + +#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ +#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define LPC43M4_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */ + +#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define LPC43M0_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ + +/* Only the Cortex-M4 is supported by Nuttx */ + +#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN +#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT +#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX +#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/sam3u/chip.h b/nuttx/arch/arm/include/sam3u/chip.h new file mode 100644 index 000000000..da8c28345 --- /dev/null +++ b/nuttx/arch/arm/include/sam3u/chip.h @@ -0,0 +1,95 @@ +/************************************************************************************ + * arch/arm/include/sam3u/chip.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_SAM3U_CHIP_H +#define __ARCH_ARM_INCLUDE_SAM3U_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E +/* Internal memory */ + +# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */ +# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */ +# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */ + +/* DMA */ + +# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */ + +/* Memory card interface */ + +# define CONFIG_SAM3U_MCI2 1 +#else +# error "Unknown SAM3U chip type" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_SAM3U_CHIP_H */ diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index b7ec7dbba..14d92ea3d 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -692,5 +692,15 @@ # error "Unsupported STM32 chip" #endif +/* NVIC priority levels *************************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + #endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/nuttx/arch/arm/src/armv7-m/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c index c30015ad2..b043db3df 100644 --- a/nuttx/arch/arm/src/armv7-m/up_hardfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c @@ -93,17 +93,16 @@ int up_hardfault(int irq, FAR void *context) { uint32_t *regs = (uint32_t*)context; - uint16_t *pc; - uint16_t insn; /* Get the value of the program counter where the fault occurred */ - pc = (uint16_t*)regs[REG_PC] - 1; +#ifndef CONFIG_ARMV7M_USEBASEPRI + uint16_t *pc = (uint16_t*)regs[REG_PC] - 1; if ((void*)pc >= (void*)&_stext && (void*)pc < (void*)&_etext) { /* Fetch the instruction that caused the Hard fault */ - insn = *pc; + uint16_t insn = *pc; hfdbg(" PC: %p INSN: %04x\n", pc, insn); /* If this was the instruction 'svc 0', then forward processing @@ -116,6 +115,7 @@ int up_hardfault(int irq, FAR void *context) return up_svcall(irq, context); } } +#endif /* Dump some hard fault info */ diff --git a/nuttx/arch/arm/src/kinetis/chip.h b/nuttx/arch/arm/src/kinetis/chip.h index 6ad781c20..0ed152bac 100644 --- a/nuttx/arch/arm/src/kinetis/chip.h +++ b/nuttx/arch/arm/src/kinetis/chip.h @@ -42,801 +42,16 @@ #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ - defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# else -# undef KINETIS_NCAN /* No CAN in 64-pin chips */ -# endif -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# undef KINETIS_NRNG /* No random number generator */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ -# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#else -# error "Unsupported Kinetis chip" -#endif - -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include #include "kinetis_memorymap.h" -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-15. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 6fb58c6bf..31310b03c 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17/kinetis_irq.c * arch/arm/src/chip/kinetis_irq.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -208,6 +208,35 @@ static int kinetis_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: kinetis_irqinfo * @@ -358,6 +387,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(KINETIS_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -486,7 +518,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < KINETIS_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h index b5974b5dc..e476ce435 100644 --- a/nuttx/arch/arm/src/lm/chip.h +++ b/nuttx/arch/arm/src/lm/chip.h @@ -43,10 +43,6 @@ #include #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - /* Then get all of the register definitions */ #include "chip/lm_memorymap.h" /* Memory map */ @@ -58,15 +54,9 @@ #include "chip/lm_ethernet.h" /* Ethernet MAC and PHY */ #include "chip/lm_flash.h" /* FLASH */ -/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism - * will only look at the upper N bits of the 8-bit priority level (where N is 3 for - * the Stellaris family), so any prioritization must be performed in those bits. - * The default priority level is set to the middle value - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index fa8e271bc..dc9997afa 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lm/lm_irq.c * arch/arm/src/chip/lm_irq.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -190,6 +190,35 @@ static int lm_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: lm_irqinfo * @@ -316,6 +345,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LM_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -433,7 +465,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LM_IRQ_INTERRUPTS) { diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index d9b3998fe..7bc1ab345 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,28 +41,18 @@ ************************************************************************************/ #include -#include -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include #include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index f3e93ffc2..2d66dd0b1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17/lpc17_irq.c * arch/arm/src/chip/lpc17_irq.c * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -189,6 +189,35 @@ static int lpc17_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: lpc17_irqinfo * @@ -304,6 +333,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LPC17_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -448,7 +480,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LPC17_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/lpc43xx/chip.h b/nuttx/arch/arm/src/lpc43xx/chip.h index 35150d08c..151571e74 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip.h +++ b/nuttx/arch/arm/src/lpc43xx/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc43xx/chip.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -141,23 +141,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. - * - * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt - * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4 - * programmable interrupt priorities. - */ - -#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ -#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - -#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 9cbb8238c..2fddd79ad 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc43/lpc43_irq.c * arch/arm/src/chip/lpc43_irq.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -191,6 +191,35 @@ static int lpc43_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: lpc43_irqinfo * @@ -333,6 +362,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LPC43_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -477,8 +509,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; +#ifdef CONFIG_ARMV7M_USEBASEPRI DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS && - (unsigned)priority <= LPC43M4_SYSH_PRIORITY_MIN); + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LPC43_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/sam3u/chip.h b/nuttx/arch/arm/src/sam3u/chip.h index 865cad5ea..1ce104ab2 100644 --- a/nuttx/arch/arm/src/sam3u/chip.h +++ b/nuttx/arch/arm/src/sam3u/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sam3u/chip.h * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,45 +42,16 @@ #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E -/* Internal memory */ - -# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */ -# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */ -# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */ - -/* DMA */ - -# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */ - -/* Memory card interface */ - -# define CONFIG_SAM3U_MCI2 1 -#else -# error "Unknown SAM3U chip type" -#endif - -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include #include "sam3u_memorymap.h" -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-15. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index db79314c0..d9fd4dac8 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_irq.c * arch/arm/src/chip/sam3u_irq.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -184,6 +184,35 @@ static int sam3u_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: sam3u_irqinfo * @@ -295,6 +324,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(SAM3U_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -436,7 +468,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < SAM3U_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 3fac597ef..41a87feae 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/chip.h * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/stm32.h b/nuttx/arch/arm/src/stm32/stm32.h index 44a23aece..95fd19779 100644 --- a/nuttx/arch/arm/src/stm32/stm32.h +++ b/nuttx/arch/arm/src/stm32/stm32.h @@ -68,12 +68,6 @@ # undef CONFIG_DEBUG_QENCODER #endif -/* NVIC priority levels *************************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /* Peripherals **********************************************************************/ #include "chip.h" diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 36a5cf5fa..8f2b070fb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_irq.c * arch/arm/src/chip/stm32_irq.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -194,6 +194,35 @@ static int stm32_reserved(int irq, FAR void *context) } #endif +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + /**************************************************************************** * Name: stm32_irqinfo * @@ -334,6 +363,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(STM32_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -451,7 +483,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < STM32_IRQ_INTERRUPTS) { -- cgit v1.2.3 From 9375b285f28c3636edab8bc60540f156aa11eaf7 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 22 Jan 2013 14:37:17 +0000 Subject: More logic to use BASEPRI to control interrupts -- still doesn't work git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 10 ++++++++++ nuttx/TODO | 23 +---------------------- nuttx/arch/arm/include/armv7-m/irq.h | 21 +++++++++++++-------- nuttx/arch/arm/include/armv7-m/irq_cmnvector.h | 6 +++++- nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h | 6 +++++- nuttx/arch/arm/include/types.h | 6 ++++++ nuttx/arch/arm/src/armv7-m/up_assert.c | 7 ++++++- nuttx/arch/arm/src/armv7-m/up_exception.S | 11 ++++++++++- nuttx/arch/arm/src/armv7-m/up_hardfault.c | 16 +++++++++++++--- nuttx/arch/arm/src/armv7-m/up_initialstate.c | 12 ++++++++---- nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c | 18 +++++++++++++++++- nuttx/arch/arm/src/armv7-m/up_sigdeliver.c | 10 +++++++++- nuttx/arch/arm/src/kinetis/kinetis_irq.c | 3 +-- nuttx/arch/arm/src/kinetis/kinetis_vectors.S | 9 +++++++++ nuttx/arch/arm/src/lm/lm_irq.c | 3 +-- nuttx/arch/arm/src/lm/lm_vectors.S | 9 +++++++++ nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 3 +-- nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S | 9 +++++++++ nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 3 +-- nuttx/arch/arm/src/sam3u/sam3u_irq.c | 3 +-- nuttx/arch/arm/src/sam3u/sam3u_vectors.S | 11 ++++++++++- nuttx/arch/arm/src/stm32/stm32_irq.c | 3 +-- nuttx/arch/arm/src/stm32/stm32_vectors.S | 17 +++++++++++++---- 23 files changed, 159 insertions(+), 60 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 41f38bd91..75bfd457f 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4001,3 +4001,13 @@ * nuttx/lcd/hd4478ou.h and configs/pcblogic-pic32mx/src/up_lcd1602: Start of support of LCD1602 alphanumeric LCD. I need a few more parts before I can finish integrating this one. + * arch/arm/src/*/chip.h and arch/arm/include/*/chip.h: Move all + priority ragnes from the src to the include chip.h header file. + * arch/arm/include/armv7-m/irq.h: Add inline functions to enable + and disable interrupts via the BASEPRI register. + * arch/arm/Kconfig: Add new option CONFIG_ARM7VM_USEBASEI + * arch/arm/src/*/*_irq.c: Set the priority of the SVCALL exception + to the highest possible value. + * arch/armv7-m/up_hardfault.c: Fail if a hardfault occurs + while CONFIG_ARM7VM_USEBASEI=y. + diff --git a/nuttx/TODO b/nuttx/TODO index 91b4aebaa..94c3dba0d 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -21,7 +21,7 @@ nuttx/ (1) Documentation (Documentation/) (7) Build system / Toolchains (5) Linux/Cywgin simulation (arch/sim) - (6) ARM (arch/arm/) + (5) ARM (arch/arm/) (1) ARM/C5471 (arch/arm/src/c5471/) (3) ARM/DM320 (arch/arm/src/dm320/) (2) ARM/i.MX (arch/arm/src/imx/) @@ -1176,27 +1176,6 @@ o ARM (arch/arm/) Status: Open Priority: Low - Title: SVCALLS AND HARDFAULTS - Description: The Cortex-M3 user context switch logic uses SVCall instructions. - This user context switching time could be improved by eliminating - the SVCalls and developing assembly language implementations - of the context save and restore logic. - Also, because interrupts are always disabled when the SVCall is - executed, the SVC goes to the hard fault handler where it must - be handled as a special case. I recall seeing some controls - somewhere that will allow to suppress one hard fault. I don't - recall the control, but something like this should be used before - executing the SVCall so that it vectors directly to the SVC - handler. - Another, more standard option would be to use interrupt priority - levels to control interrupts. In that case, (1) The SVC would - be the highest priority interrupt (0), (2) irqsave() would set - the interrupt mask level to just above that, and (2) irqrestore - would restore the interrupt level. This would not be diffult, - but does affect a lot of files! - Status: Open - Priority: Low - Title: ARM INTERRUPTS AND USER MODE Description: The ARM interrupt handling (arch/arm/src/arm/up_vectors.S) returns using 'ldmia sp, {r0-r15}^' My understanding is that this works diff --git a/nuttx/arch/arm/include/armv7-m/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h index 9491e57c0..8acec4c07 100644 --- a/nuttx/arch/arm/include/armv7-m/irq.h +++ b/nuttx/arch/arm/include/armv7-m/irq.h @@ -118,7 +118,11 @@ struct xcptcontext */ uint32_t saved_pc; +#ifdef CONFIG_ARMV7M_USEBASEPRI + uint32_t saved_basepri; +#else uint32_t saved_primask; +#endif uint32_t saved_xpsr; #endif @@ -134,7 +138,7 @@ struct xcptcontext #ifndef __ASSEMBLY__ -/* Get/set the primask register */ +/* Get/set the PRIMASK register */ static inline uint8_t getprimask(void) inline_function; static inline uint8_t getprimask(void) @@ -161,7 +165,11 @@ static inline void setprimask(uint32_t primask) : "memory"); } -/* Get/set the basepri register */ +/* Get/set the BASEPRI register. The BASEPRI register defines the minimum + * priority for exception processing. When BASEPRI is set to a nonzero + * value, it prevents the activation of all exceptions with the same or + * lower priority level as the BASEPRI value. + */ static inline uint8_t getbasepri(void) inline_function; static inline uint8_t getbasepri(void) @@ -210,7 +218,7 @@ static inline irqstate_t irqsave(void) uint8_t basepri = getbasepri(); setbasepri(NVIC_SYSH_DISABLE_PRIORITY); - return basepri; + return (irqstate_t)basepri; #else @@ -237,11 +245,8 @@ static inline irqstate_t irqsave(void) static inline void irqenable(void) inline_function; static inline void irqenable(void) { -#ifdef CONFIG_ARMV7M_USEBASEPRI - setbasepri(NVIC_SYSH_PRIORITY_MIN); -#else + setbasepri(0); __asm__ __volatile__ ("\tcpsie i\n"); -#endif } /* Restore saved primask state */ @@ -250,7 +255,7 @@ static inline void irqrestore(irqstate_t flags) inline_function; static inline void irqrestore(irqstate_t flags) { #ifdef CONFIG_ARMV7M_USEBASEPRI - setbasepri(flags); + setbasepri((uint32_t)flags); #else /* If bit 0 of the primask is 0, then we need to restore * interupts. diff --git a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h index e646731eb..bc67004ed 100644 --- a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h +++ b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h @@ -51,7 +51,11 @@ */ #define REG_R13 (0) /* R13 = SP at time of interrupt */ -#define REG_PRIMASK (1) /* PRIMASK */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif #define REG_R4 (2) /* R4 */ #define REG_R5 (3) /* R5 */ #define REG_R6 (4) /* R6 */ diff --git a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h index 2c3600b7f..f2380cbb6 100644 --- a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h +++ b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h @@ -51,7 +51,11 @@ */ #define REG_R13 (0) /* R13 = SP at time of interrupt */ -#define REG_PRIMASK (1) /* PRIMASK */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif #define REG_R4 (2) /* R4 */ #define REG_R5 (3) /* R5 */ #define REG_R6 (4) /* R6 */ diff --git a/nuttx/arch/arm/include/types.h b/nuttx/arch/arm/include/types.h index c06b28950..1d2ea4cfe 100644 --- a/nuttx/arch/arm/include/types.h +++ b/nuttx/arch/arm/include/types.h @@ -44,6 +44,8 @@ * Included Files ****************************************************************************/ +#include + /**************************************************************************** * Definitions ****************************************************************************/ @@ -87,7 +89,11 @@ typedef unsigned int _uintptr_t; */ #ifdef __thumb2__ +#ifdef CONFIG_ARMV7M_USEBASEPRI +typedef unsigned char irqstate_t; +#else typedef unsigned short irqstate_t; +#endif #else /* __thumb2__ */ typedef unsigned int irqstate_t; #endif /* __thumb2__ */ diff --git a/nuttx/arch/arm/src/armv7-m/up_assert.c b/nuttx/arch/arm/src/armv7-m/up_assert.c index 282ff6a57..ab30b09f3 100644 --- a/nuttx/arch/arm/src/armv7-m/up_assert.c +++ b/nuttx/arch/arm/src/armv7-m/up_assert.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_assert.c * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -147,8 +147,13 @@ static inline void up_registerdump(void) current_regs[REG_R10], current_regs[REG_R11], current_regs[REG_R12], current_regs[REG_R13], current_regs[REG_R14], current_regs[REG_R15]); +#ifdef CONFIG_ARMV7M_USEBASEPRI + lldbg("xPSR: %08x BASEPRI: %08x\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); +#else lldbg("xPSR: %08x PRIMASK: %08x\n", current_regs[REG_XPSR], current_regs[REG_PRIMASK]); +#endif } } #else diff --git a/nuttx/arch/arm/src/armv7-m/up_exception.S b/nuttx/arch/arm/src/armv7-m/up_exception.S index c9f216027..17344db41 100644 --- a/nuttx/arch/arm/src/armv7-m/up_exception.S +++ b/nuttx/arch/arm/src/armv7-m/up_exception.S @@ -2,7 +2,7 @@ * arch/arm/src/stm32/up_exception.S * arch/arm/src/chip/up_exception.S * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Michael Smith. All rights reserved. * Author: Gregory Nutt * @@ -100,7 +100,11 @@ exception_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ /* (ignoring the xPSR[9] alignment bit) */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_ARCH_FPU @@ -205,7 +209,12 @@ exception_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) select the correct stack. diff --git a/nuttx/arch/arm/src/armv7-m/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c index b043db3df..fa750b525 100644 --- a/nuttx/arch/arm/src/armv7-m/up_hardfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_hardfault.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -55,7 +55,9 @@ * Pre-processor Definitions ****************************************************************************/ -/* Debug output from this file may interfere with context switching! */ +/* If CONFIG_ARMV7M_USEBASEPRI=n, then debug output from this file may + * interfere with context switching! + */ #ifdef CONFIG_DEBUG_HARDFAULT # define hfdbg(format, arg...) lldbg(format, ##arg) @@ -92,7 +94,9 @@ int up_hardfault(int irq, FAR void *context) { +#if defined(CONFIG_DEBUG_HARDFAULT) || !defined(CONFIG_ARMV7M_USEBASEPRI) uint32_t *regs = (uint32_t*)context; +#endif /* Get the value of the program counter where the fault occurred */ @@ -133,7 +137,13 @@ int up_hardfault(int irq, FAR void *context) hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - hfdbg(" PSR=%08x\n", regs[REG_XPSR]); +#ifdef CONFIG_ARMV7M_USEBASEPRI + hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); +#else + hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n", + current_regs[REG_XPSR], current_regs[REG_PRIMASK]); +#endif (void)irqsave(); lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); diff --git a/nuttx/arch/arm/src/armv7-m/up_initialstate.c b/nuttx/arch/arm/src/armv7-m/up_initialstate.c index 81a4dc9ea..635a700fd 100644 --- a/nuttx/arch/arm/src/armv7-m/up_initialstate.c +++ b/nuttx/arch/arm/src/armv7-m/up_initialstate.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_initialstate.c * - * Copyright (C) 2009, 2011-2 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -148,7 +148,7 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_FPSCR] = 0; // XXX initial FPSCR should be configurable xcp->regs[REG_FPReserved] = 0; -#endif +#endif /* CONFIG_ARCH_FPU */ #ifdef CONFIG_NUTTX_KERNEL if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) @@ -157,7 +157,7 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PROCESS_STACK; } -#endif +#endif /* CONFIG_NUTTX_KERNEL */ #else /* CONFIG_ARMV7M_CMNVECTOR */ @@ -181,12 +181,16 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; } -#endif +#endif /* CONFIG_NUTTX_KERNEL */ #endif /* CONFIG_ARMV7M_CMNVECTOR */ /* Enable or disable interrupts, based on user configuration */ #ifdef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_ARMV7M_USEBASEPRI + xcp->regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else xcp->regs[REG_PRIMASK] = 1; #endif +#endif /* CONFIG_SUPPRESS_INTERRUPTS */ } diff --git a/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c index 9e6dbd14b..9221a69a2 100644 --- a/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_schedulesigaction.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -155,7 +155,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = current_regs[REG_PC]; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.saved_basepri = current_regs[REG_BASEPRI]; +#else tcb->xcp.saved_primask = current_regs[REG_PRIMASK]; +#endif tcb->xcp.saved_xpsr = current_regs[REG_XPSR]; /* Then set up to vector to the trampoline with interrupts @@ -163,7 +167,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) */ current_regs[REG_PC] = (uint32_t)up_sigdeliver; +#ifdef CONFIG_ARMV7M_USEBASEPRI + current_regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else current_regs[REG_PRIMASK] = 1; +#endif current_regs[REG_XPSR] = ARMV7M_XPSR_T; /* And make sure that the saved context in the TCB @@ -189,7 +197,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI]; +#else tcb->xcp.saved_primask = tcb->xcp.regs[REG_PRIMASK]; +#endif tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR]; /* Then set up to vector to the trampoline with interrupts @@ -197,7 +209,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) */ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else tcb->xcp.regs[REG_PRIMASK] = 1; +#endif tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T; } diff --git a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c index 38673c41d..654214b39 100644 --- a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_sigdeliver.c * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -102,7 +102,11 @@ void up_sigdeliver(void) up_copystate(regs, rtcb->xcp.regs); regs[REG_PC] = rtcb->xcp.saved_pc; +#ifdef CONFIG_ARMV7M_USEBASEPRI + regs[REG_BASEPRI] = rtcb->xcp.saved_basepri; +#else regs[REG_PRIMASK] = rtcb->xcp.saved_primask; +#endif regs[REG_XPSR] = rtcb->xcp.saved_xpsr; /* Get a local copy of the sigdeliver function pointer. We do this so that @@ -115,7 +119,11 @@ void up_sigdeliver(void) /* Then restore the task interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + irqrestore((uint8_t)regs[REG_BASEPRI]); +#else irqrestore((uint16_t)regs[REG_PRIMASK]); +#endif /* Deliver the signals */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 31310b03c..37a6a4a63 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -428,8 +428,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S index faa1ce7a7..7fa223615 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S +++ b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S @@ -605,7 +605,11 @@ kinetis_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_NUTTX_KERNEL stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ #else @@ -691,7 +695,12 @@ kinetis_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index dc9997afa..7d8d2135a 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -379,8 +379,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S index d3798fbb7..1d3553b4e 100644 --- a/nuttx/arch/arm/src/lm/lm_vectors.S +++ b/nuttx/arch/arm/src/lm/lm_vectors.S @@ -203,7 +203,11 @@ lm_irqcommon: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_NUTTX_KERNEL stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ #else @@ -289,7 +293,12 @@ lm_irqcommon: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index 2d66dd0b1..c9b289d4e 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -374,8 +374,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S index 74e53b411..e2cf91b1c 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S @@ -217,7 +217,11 @@ lpc17_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_NUTTX_KERNEL stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ #else @@ -303,7 +307,12 @@ lpc17_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 2fddd79ad..1867aa150 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -403,8 +403,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS - setbasepri(LPC43M4_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index d9fd4dac8..690a075ef 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -366,8 +366,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S index 3ed17f767..53e2f636c 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S +++ b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_vectors.S * arch/arm/src/chip/sam3u_vectors.S * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -249,7 +249,11 @@ sam3u_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_NUTTX_KERNEL stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ #else @@ -335,7 +339,12 @@ sam3u_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 8f2b070fb..bff3eb2b7 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -397,8 +397,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index ab4dadb77..c9b62d762 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_vectors.S * arch/arm/src/chip/stm32_vectors.S * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -235,7 +235,11 @@ stm32_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_ARCH_FPU /* Skip over the block of memory reserved for floating pointer register save. @@ -248,8 +252,8 @@ stm32_common: #endif /* Save the the remaining registers on the stack after the registers pushed - * by the exception handling logic. r2=SP and r3=primask, r4-r11,r14=register - * values. + * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11, + * r14=register values. */ #ifdef CONFIG_NUTTX_KERNEL @@ -349,7 +353,7 @@ stm32_common: * Here: * r1 = Address on the target thread's stack position at the start of * the registers saved by hardware - * r3 = primask + * r3 = primask or basepri * r4-r11 = restored register values */ 2: @@ -375,7 +379,12 @@ stm32_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP -- cgit v1.2.3 From 7dad51762decebe5d104fe7dad9eb23680cabd23 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 22 Jan 2013 16:09:10 +0000 Subject: Use of BASEPRI to control ARM interrupts is now functional git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5548 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/kinetis/kinetis_irq.c | 32 ++++++++++++++--------------- nuttx/arch/arm/src/lm/lm_irq.c | 32 ++++++++++++++--------------- nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c | 21 +++++++++++++++++-- nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 32 ++++++++++++++--------------- nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 32 ++++++++++++++--------------- nuttx/arch/arm/src/sam3u/sam3u_irq.c | 32 ++++++++++++++--------------- nuttx/arch/arm/src/stm32/stm32_irq.c | 32 ++++++++++++++--------------- 7 files changed, 115 insertions(+), 98 deletions(-) diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 37a6a4a63..b0aea55d1 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -209,7 +209,7 @@ static int kinetis_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: kinetis_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -217,23 +217,17 @@ static int kinetis_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void kinetis_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -389,7 +383,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(KINETIS_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + kinetis_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -528,11 +522,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < KINETIS_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= KINETIS_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index 7d8d2135a..d8c0852ed 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -191,7 +191,7 @@ static int lm_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lm_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -199,23 +199,17 @@ static int lm_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lm_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -347,7 +341,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LM_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lm_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -475,11 +469,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LM_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LM_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c index bf6d18287..0241d4bf7 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -104,11 +104,28 @@ #endif /* If the user did not specify a priority for Ethernet interrupts, set the - * interrupt priority to the maximum. + * interrupt priority to the maximum (unless CONFIG_ARMV7M_USEBASEPRI is + * defined, then set it to the maximum allowable priority). */ #ifndef CONFIG_NET_PRIORITY -# define CONFIG_NET_PRIORITY NVIC_SYSH_PRIORITY_MAX +# ifdef CONFIG_ARMV7M_USEBASEPRI +# define CONFIG_NET_PRIORITY NVIC_SYSH_DISABLE_PRIORITY +# else +# define CONFIG_NET_PRIORITY NVIC_SYSH_PRIORITY_MAX +# endif +#endif + +/* If the priority is set at the max (0) and CONFIG_ARMV7M_USEBASEPRI is + * defined, then silently drop the priority to NVIC_SYSH_DISABLE_PRIORITY. + * In this configuratin, nothing is permitted to run at priority zero + * except for the SVCALL handler. NVIC_SYSH_DISABLE_PRIORITY is the + * maximum allowable priority in that case. + */ + +#if CONFIG_NET_PRIORITY == 0 && defined(CONFIG_ARMV7M_USEBASEPRI) +# undef CONFIG_NET_PRIORITY +# define CONFIG_NET_PRIORITY NVIC_SYSH_DISABLE_PRIORITY #endif /* Debug Configuration *****************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index c9b289d4e..6d96ff386 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -190,7 +190,7 @@ static int lpc17_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lpc17_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -198,23 +198,17 @@ static int lpc17_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lpc17_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -335,7 +329,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LPC17_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -490,11 +484,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LPC17_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LPC17_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 1867aa150..aa0e4cf09 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -192,7 +192,7 @@ static int lpc43_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lpc43_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -200,23 +200,17 @@ static int lpc43_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lpc43_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -364,7 +358,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LPC43_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lpc43_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -519,11 +513,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LPC43_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LPC43_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index 690a075ef..ed424f91d 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -185,7 +185,7 @@ static int sam3u_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: sam3u_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -193,23 +193,17 @@ static int sam3u_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void sam3u_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -326,7 +320,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(SAM3U_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + sam3u_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -478,11 +472,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < SAM3U_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= SAM3U_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index bff3eb2b7..a952c2486 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -195,7 +195,7 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -203,23 +203,17 @@ static int stm32_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void stm32_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -365,7 +359,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(STM32_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -493,11 +487,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < STM32_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } -- cgit v1.2.3 From 336f91b4e6b029e4fd76783931e3d6bd6b879d5f Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 22 Jan 2013 23:42:51 +0000 Subject: lpc1788 update from Rommel Marcelo; Beginning of logic to retain child exit status git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5549 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h | 635 +++++++++++++++++++++ .../arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h | 2 +- .../arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h | 358 ++++++------ nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h | 582 +------------------ nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h | 52 +- nuttx/include/nuttx/sched.h | 70 ++- nuttx/include/sched.h | 65 ++- nuttx/sched/Makefile | 5 +- nuttx/sched/os_internal.h | 12 +- nuttx/sched/os_start.c | 11 + nuttx/sched/sched_waitid.c | 2 +- nuttx/sched/task_childstatus.c | 365 ++++++++++++ 12 files changed, 1331 insertions(+), 828 deletions(-) create mode 100644 nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h create mode 100644 nuttx/sched/task_childstatus.c diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h new file mode 100644 index 000000000..6d5b05ba9 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h @@ -0,0 +1,635 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ +#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ +#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ +#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ +#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ +#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ +#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ +#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ +#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ +#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ +#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ +#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ +#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ +#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ +#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ +#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ +#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ +#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ +#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ +#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ +#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ +#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ +#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ +#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) +#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) +#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) +#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) +#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) +#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) +#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) +#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) +#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) +#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) +#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) +#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) +#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) +#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) +#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) +#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) +#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) +#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) +#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) +#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) +#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) +#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) +#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) +#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ + +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + +#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) +#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) + +#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ +#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) +#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ +#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) +#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ +#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) +#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ +#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) +#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ +#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) +#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ +#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) +#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ +#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) +#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ +#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) +#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ +#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) +#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ +#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) +#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ +#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) +#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ +#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ +#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) + +/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ + +#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ +#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) +#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ +#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) +#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ +#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) +#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ +#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) +#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ +#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) +#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ +#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) +#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ +#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) +#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ +#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) +#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ +#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) +#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ +#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) +#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ +#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) +#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ +#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) +#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ +#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) +#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) +#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) + /* Bits 30-31: Reserved */ +/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ + +#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) +#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) +#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) +#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) +#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) + +/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ + +#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) +#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) +#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ +#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) +#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ +#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) +#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ +#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) +#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ +#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) +#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ +#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) +#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ +#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) +#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ +#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) +#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ +#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) +#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ +#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) +#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ +#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) +#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ +#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) +#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ +#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) +#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ +#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) +#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ +#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) + +/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ + +#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) +#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) +#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) +#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) +#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) +#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) +#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ +#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) +#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) +#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ +#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) +#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ +#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) +#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ +#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) +#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ +#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) +#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ +#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) +#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ +#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ + +#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-17: Reserved */ +#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ +#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) +#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ +#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ +/* No description of bits -- Does this register exist? */ + +/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ + +#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-23: Reserved */ +#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ +#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) +#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ +#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ + /* Bits 0-2: Reserved */ +#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ + /* Bits 4-31: Reserved */ +/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ + +#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ +#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ +#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ +#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ +#define PINCONN_PINMODE_MASK (3) + +#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) +#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) + +#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ +#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) +#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ +#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) +#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ +#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) +#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ +#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) +#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ +#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) +#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ +#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) +#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ +#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) +#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ +#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) +#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ +#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) +#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ +#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) +#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ +#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) +#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ +#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ +#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) + +/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ + +#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ +#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) +#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ +#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) +#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ +#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) +#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ +#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) +#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ +#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) +#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ +#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) +#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ +#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) +#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ +#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) +#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ +#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) +#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ +#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) +#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ +#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ + +#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ +#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) +#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ +#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ +#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ +#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) +#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ +#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) +#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ +#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ +#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) +#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ +#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) + +/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ + +#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ +#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) +#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ +#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) +#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ +#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) +#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ +#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) +#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ +#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) +#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ +#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) +#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ +#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) +#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ +#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) +#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ +#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) +#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ +#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) +#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ +#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) +#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ +#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) +#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ +#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) +#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ +#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) +#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ +#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) +#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ +#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) + +/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ + +#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ +#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) +#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ +#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) +#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ +#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) +#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ +#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) +#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ +#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) +#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ +#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Mode select register 5 (PINMODE5: 0x4002c054) + * Pin Mode select register 6 (PINMODE6: 0x4002c058) + * No bit definitions -- do these registers exist? + */ + +#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ + +#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-17: Reserved */ +#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ +#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) +#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ +#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ +/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ + +#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-23: Reserved */ +#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ +#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) +#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ +#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ + +#define PINCONN_ODMODE0_P0(n) (1 << (n)) + +#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ +#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ +#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ +#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ +#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ +#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ +#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ +#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ +#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ +#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ +#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ +#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ + /* Bits 12-14: Reserved */ +#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ +#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ +#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ +#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ +#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ +#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ +#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ +#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ +#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ +#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ +#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ +#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ + /* Bits 27-28: Reserved */ +#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ +#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ + /* Bit 31: Reserved */ +/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ + +#define PINCONN_ODMODE1_P1(n) (1 << (n)) + +#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ +#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ + /* Bits 2-3: Reserved */ +#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ + /* Bits 5-7: Reserved */ +#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ +#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ +#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ + /* Bits 11-13: Reserved */ +#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ +#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ +#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ +#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ +#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ +#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ +#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ +#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ +#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ +#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ +#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ +#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ +#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ +#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ +#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ +#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ +#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ +#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ + +/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ + +#define PINCONN_ODMODE2_P2(n) (1 << (n)) + +#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ +#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ +#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ +#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ +#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ +#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ +#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ +#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ +#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ +#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ +#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ +#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ +#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ +#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ + /* Bits 14-31: Reserved */ +/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ + +#define PINCONN_ODMODE3_P3(n) (1 << (n)) + /* Bits 0-24: Reserved */ +#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ +#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ + /* Bits 17-31: Reserved */ +/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ + +#define PINCONN_ODMODE4_P4(n) (1 << (n)) + /* Bits 0-27: Reserved */ +#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ +#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ + /* Bits 30-31: Reserved */ +/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ + +#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch + * filtering/slew rate control */ +#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch + * filtering/slew rate control */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h index 295e1a0ee..dfee7d375 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h @@ -97,7 +97,7 @@ /* -0x40023fff: Reserved */ #define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ #define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ -#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_IOCON_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ #define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ #define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ #define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h index 37a16c1e0..58bd413ea 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h @@ -67,64 +67,64 @@ #define GPIO_I2C1_SCL_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) #define GPIO_UART0_RXD_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) -#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_UART3_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_UART0_TXD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_UART3_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) -#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) -#define GPIO_UART3_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_UART0_RXD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_UART3_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3) #define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_CAN2_RD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) -#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAN2_RD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAP2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) #define GPIO_LCD_VD0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) #define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_CAN2_TD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) -#define GPIO_LCD_VD1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAN2_TD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAP2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_LCD_VD1_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) #define GPIO_I2S_RXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_SSP1_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_UART1_RTS_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) -#define GPIO_LCD_VD8 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_LCD_VD8_1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) #define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_RTC_EV0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) -#define GPIO_LCD_VD9 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_LCD_VD9_1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) #define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) -#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SSP1_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_MAT2p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_LCD_VD16 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) #define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) -#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_SSP1_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_MAT2p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_RTC_EV2_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_LCD_VD17 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) #define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) -#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_I2C2_SDA_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_MAT3p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) #define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) -#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_I2C2_SCL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_MAT3p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) #define GPIO_USB_PPWR2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) -#define GPIO_SSP1_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_SSP1_MISO_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) #define GPIO_AD0p6 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN12) #define GPIO_USB_LED2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) -#define GPIO_SSP1_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) +#define GPIO_SSP1_MOSI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) #define GPIO_AD0p7 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) #define GPIO_USB_HSTEN2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) -#define GPIO_SSP1_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) +#define GPIO_SSP1_SSEL_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) #define GPIO_USB_CONNECT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN14) #define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15) @@ -153,36 +153,36 @@ #define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_SD_PWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) -#define GPIO_UART4_OE (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UART4_OE_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_CAN1_RD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) #define GPIO_UART4_SCLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21) -#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_UART1_RTS_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) #define GPIO_SD_DAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) -#define GPIO_UART4_TXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_UART4_TXD_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) #define GPIO_CAN1_TD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) #define GPIO_SPIFI_SCLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22) #define GPIO_AD0p0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) #define GPIO_I2S_RXCLK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) -#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) +#define GPIO_CAP3p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN23) #define GPIO_AD0p1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) #define GPIO_I2S_RXWS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) -#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_CAP3p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN24) #define GPIO_AD0p2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) #define GPIO_I2S_RXSDA_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) -#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25) #define GPIO_AD0p3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) #define GPIO_AOUT (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) -#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26) -#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_I2C0_SDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) #define GPIO_USB_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN27) -#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_I2C0_SCL_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) #define GPIO_USB_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN28) #define GPIO_USB1DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN29) @@ -194,62 +194,62 @@ #define GPIO_USB2_DP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN31) #define GPIO_ENET_TXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) -#define GPIO_SSP2_SCK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_CAP3p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_SSP2_SCK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) #define GPIO_ENET_TXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) -#define GPIO_SSP2_MOSI (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_MAT3p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_SSP2_MOSI (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) #define GPIO_ENET_TXD2 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN2) -#define GPIO_SD_CLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) -#define GPIO_PWM0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_SD_CLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_PWM0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) #define GPIO_ENET_TXD3 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_SD_CMD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) -#define GPIO_PWM0p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_SD_CMD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_PWM0p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) #define GPIO_ENET_TXEN (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN4) -#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) -#define GPIO_SSP2_MISO (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_MAT3p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_SSP2_MISO (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) #define GPIO_ENET_TX_ER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN5) -#define GPIO_SD_PWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) -#define GPIO_PWM0p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_SD_PWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_PWM0p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) #define GPIO_ENET_TX_CLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN6) -#define GPIO_SD_DAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) -#define GPIO_PWM0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SD_DAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_PWM0p4_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) #define GPIO_ENET_COL (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN7) -#define GPIO_SD_DAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) -#define GPIO_PWM0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SD_DAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_PWM0p5_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) #define GPIO_ENET_CRSDV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN8) -#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) -#define GPIO_SSP2_SSEL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_MAT3p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SSP2_SSEL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) #define GPIO_ENET_RXD0 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN9) -#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_MAT3p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) #define GPIO_ENET_RXD1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN10) -#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CAP3p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) #define GPIO_ENET_RXD2 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN11) #define GPIO_SD_DAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) -#define GPIO_PWM0p6 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_PWM0p6_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) #define GPIO_ENET_RXD3 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN12) #define GPIO_SD_DAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) -#define GPIO_PWM0CAPp0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_PWM0CAPp0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN12) #define GPIO_ENET_RX_DV (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN13) #define GPIO_ENET_RXER (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN14) -#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_CAP2p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN14) #define GPIO_ENET_REFCLK (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN15) -#define GPIO_I2C2_SDA (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_I2C2_SDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN15) #define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN16) #define GPIO_I2S_TXMCLK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN16) @@ -259,83 +259,83 @@ #define GPIO_USB_UPLED (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) #define GPIO_PWM1p1_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) -#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) -#define GPIO_SSP1_MISO (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_CAP1p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_SSP1_MISO_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN18) #define GPIO_USB1_TXE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) #define GPIO_USB1_PPWR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_CAP1p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) #define GPIO_MCPWM_MC0A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_SSP1_SCK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) -#define GPIO_UART2_OE (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_SSP1_SCK_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_UART2_OE_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN19) #define GPIO_USB1_TXDP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) #define GPIO_PWM1p2_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) #define GPIO_QEI_PHA (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) #define GPIO_MCPWM_MCFB0 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_SSP0_SCK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_LCD_VD6 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) -#define GPIO_LCD_VD10 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_SSP0_SCK_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_LCD_VD6_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_LCD_VD10_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN20) #define GPIO_USB1_TXDM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) #define GPIO_PWM1p3_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) #define GPIO_SSP0_SSEL_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) #define GPIO_MCPWM_ABORT (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) -#define GPIO_LCD_VD7 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) -#define GPIO_LCD_VD11 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_LCD_VD7_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_LCD_VD11_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN21) #define GPIO_USB1_RCV (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) #define GPIO_USB1_PWRD (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_MAT1p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) #define GPIO_MCPWM_MCOB (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_SSP1_MOSI (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_LCD_VD8 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) -#define GPIO_LCD_VD12 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_SSP1_MOSI_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_LCD_VD8_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_LCD_VD12_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN22) #define GPIO_USB1_RXDP (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_PWM1p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_PWM1p4_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) #define GPIO_QEI_PHB (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) #define GPIO_MCPWM_MCFB1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPPIO_SSP0_MOSI (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_LCD_VD9 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) -#define GPIO_LCD_VD13 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_SSP0_MOSI_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_LCD_VD9_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_LCD_VD13_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN23) #define GPIO_USB1_RXDM (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) #define GPIO_PWM1p5_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) #define GPIO_QEI_IDX (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) #define GPIO_MCPWM_MCFB2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_SSP0_MOSI_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_LCD_VD10_VD14 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) -#define GPIO_LCD_VD10_VD14 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_SSP0_MOSI_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_LCD_VD10_14_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_LCD_VD10_14_2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN24) #define GPIO_USB1_LS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) #define GPIO_USB1_HSTEN (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) -#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_MAT1p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) #define GPIO_MCPWM_MC1A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) #define GPIO_CLKOUT_ (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) -#define GPIO_LCD_VD11 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) -#define GPIO_LCD_VD15 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_LCD_VD11_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_LCD_VD15_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN25) #define GPIO_USB1_SSPND (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) #define GPIO_PWM1p6_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_CAP0p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) #define GPIO_MCPWM_MC1B (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_SSP1_SSEL (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) -#define GPIO_LCD_VD12 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_SSP1_SSEL_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_LCD_VD12_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) #define GPIO_LCD_VD20 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN26) #define GPIO_USB1_INT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) #define GPIO_USB1_OVRCR (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) -#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CAP0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) #define GPIO_CLKOUT_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) -#define GPIO_LCD_VD13 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_LCD_VD13_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) #define GPIO_LCD_VD21 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN27) #define GPIO_USB1_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) #define GPIO_PCAP1p0_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) #define GPIO_MAT0p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) #define GPIO_MCPWM_MC2A (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) -#define GPIO_SSP0_SSEL (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_SSP0_SSEL_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) #define GPIO_LCD_VD14 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) #define GPIO_LCD_VD22 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN28) @@ -343,20 +343,20 @@ #define GPIO_PCAP1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) #define GPIO_MAT0p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) #define GPIO_MCPWM_MC2B (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) -#define GPIO_UART4_TXD (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) -#define GPIO_LCD_VD15 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_UART4_TXD_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_LCD_VD15_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) #define GPIO_LCD_VD23 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN29) #define GPIO_USB2_PWRD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) #define GPIO_USB_VBUS (GPIO_ALT2 | GPIO_FLOAT | GPIO_PORT1 | GPIO_PIN30) #define GPIO_AD0p4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) -#define GPIO_I2C0_SDA (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_I2C0_SDA_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) #define GPIO_UART3_OE (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN30) #define GPIO_USB2_OVRCR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) -#define GPIO_SSP1_SCK_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_SSP1_SCK_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) #define GPIO_AD0p5 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) -#define GPIO_I2C0_SCL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_I2C0_SCL_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN31) #define GPIO_PWM1p1_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) #define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) @@ -368,54 +368,54 @@ #define GPIO_PWM1p3_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) #define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) -#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_MAT2p3_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) #define GPIO_TRACEDATA3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) #define GPIO_LCD_DCLK (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2) #define GPIO_PWM1p4_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) #define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) -#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_MAT2p2_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) #define GPIO_TRACEDATA2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) #define GPIO_LCD_FP (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3) #define GPIO_PWM1p5_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) #define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) -#define GPIO_MAT2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_MAT2p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) #define GPIO_TRACEDATA1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) #define GPIO_LCD_ENABM (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4) #define GPIO_PWM1p6_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) #define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) -#define GPIO_MAT2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_MAT2p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) #define GPIO_TRACEDATA0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) #define GPIO_LCD_LP (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5) #define GPIO_PCAP1p0_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) #define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) -#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) -#define GPIO_UART2_OE (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CAP2p0_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_UART2_OE_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) #define GPIO_TRACECLK (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) #define GPIO_LCD_VD0_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) -#define GPIO_LCD_VD4 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_LCD_VD4_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6) #define GPIO_CAN2_RD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) #define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) #define GPIO_SPIFI_CS (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) #define GPIO_LCD_VD1_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) -#define GPIO_LCD_VD5 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_LCD_VD5_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7) #define GPIO_CAN2_TD_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) #define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_UART1_CTS (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_UART1_CTS_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) #define GPIO_ENET_MDC_2 (GPIO_ALT4 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_LCD_VD2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) -#define GPIO_LCD_VD6 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LCD_VD2_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_LCD_VD6_2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8) #define GPIO_USB1_CONNECT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) #define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) -#define GPIO_UART4_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_UART4_RXD_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) #define GPIO_ENET_MDIO_2 (GPIO_ALT4 | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN9) -#define GPIO_LCD_VD3 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_LCD_VD3_1 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) #define GPIO_LCD_VD7 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9) #define GPIO_EINT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN10) @@ -429,25 +429,25 @@ #define GPIO_EINT2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #define GPIO_SD_DAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #define GPIO_I2S_TXWS_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) -#define GPIO_LCD_VD4 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) -#define GPIO_LCD_VD3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD4_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_VD3_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #define GPIO_LCD_VD8 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #define GPIO_LCD_VD18 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN12) #define GPIO_EINT3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) #define GPIO_SD_DAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) #define GPIO_I2S_TXSDA_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) -#define GPIO_LCD_VD5 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) -#define GPIO_LCD_VD9 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_VD5_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_VD9_3 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) #define GPIO_LCD_VD19 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN13) #define GPIO_EMC_CS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) -#define GPIO_I2C1_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) -#define GPIO_CAP2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_I2C1_SDA_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CAP2p0_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN14) #define GPIO_EMC_CS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) #define GPIO_I2C1_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) -#define GPIO_CAP2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_CAP2p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN15) #define GPIO_EMC_CAS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN16) #define GPIO_EMC_RAS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN17) @@ -458,34 +458,34 @@ #define GPIO_EMC_DYCS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN21) #define GPIO_EMC_DYCS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) -#define GPIO_SSP0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) -#define GPIO_CAP3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_SSP0_SCK_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_CAP3p0_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN22) #define GPIO_EMC_DYCS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) -#define GPIO_SSP0_SSEL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) -#define GPIO_CAP3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_SSP0_SSEL_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_CAP3p1_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN23) #define GPIO_EMC_CKE0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN24) #define GPIO_EMC_CKE1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN25) #define GPIO_EMC_CKE2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) -#define GPIO_SSP0_MISO (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) -#define GPIO_MAT3p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_SSP0_MISO_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_MAT3p0_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN26) #define GPIO_EMC_CKE3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) -#define GPIO_SSP0_MOSI (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) -#define GPIO_MAT3p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_SSP0_MOSI_4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_MAT3p1_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN27) #define GPIO_EMC_DQM0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN28) #define GPIO_EMC_DQM1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN29) #define GPIO_EMC_DQM2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) -#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) -#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_I2C2_SDA_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_MAT3p2_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) #define GPIO_EMC_DQM3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) -#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) -#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_I2C2_SCL_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_MAT3p3_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN30) #define GPIO_EMC_D0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN0) #define GPIO_EMC_D1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN1) @@ -505,65 +505,65 @@ #define GPIO_EMC_D15 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN15) #define GPIO_EMC_D16 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) -#define GPIO_PWM0p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) -#define GPIO_UART1_TXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_PWM0p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_UART1_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN16) #define GPIO_EMC_D17 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) -#define GPIO_PWM0p2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) -#define GPIO_UART1_RXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_PWM0p2_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_UART1_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN17) #define GPIO_EMC_D18 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) -#define GPIO_PWM0p3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) -#define GPIO_UART1_CTS (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_PWM0p3_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_UART1_CTS_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN18) #define GPIO_EMC_D19 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) -#define GPIO_PWM0p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) -#define GPIO_UART1_DCD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_PWM0p4_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_UART1_DCD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN19) #define GPIO_EMC_D20 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) -#define GPIO_PWM0p5 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) -#define GPIO_UART1_DSR (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_PWM0p5_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_UART1_DSR_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN20) #define GPIO_EMC_D21 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) -#define GPIO_PWM0p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) -#define GPIO_UART1_DTR (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) +#define GPIO_PWM0p6_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) +#define GPIO_UART1_DTR_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN21) #define GPIO_EMC_D22 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) -#define GPIO_PWM0CAPp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) -#define GPIO_UART1_RI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) +#define GPIO_PWM0CAPp0_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) +#define GPIO_UART1_RI_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN22) #define GPIO_EMC_D23 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) #define GPIO_PWM1CAPp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) -#define GPIO_CAP0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) +#define GPIO_CAP0p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN23) #define GPIO_EMC_D24 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) -#define GPIO_PWM1p1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) -#define GPIO_CAP0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) +#define GPIO_PWM1p1_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) +#define GPIO_CAP0p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN24) #define GPIO_EMC_D25 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) -#define GPIO_PWM1p2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) -#define GPIO_MAT0p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_PWM1p2_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_MAT0p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN25) #define GPIO_EMC_D26 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) -#define GPIO_PWM1p3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) -#define GPIO_MAT0p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_PWM1p3_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_MAT0p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) #define GPIO_STCLK (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN26) #define GPIO_EMC_D27 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) -#define GPIO_PWM1p4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) -#define GPIO_CAP1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_PWM1p4_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_CAP1p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN27) #define GPIO_EMC_D28 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) -#define GPIO_PWM1p5 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) -#define GPIO_CAP1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_PWM1p5_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_CAP1p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN28) #define GPIO_EMC_D29 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) -#define GPIO_PWM1p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) -#define GPIO_MAT1p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_PWM1p6_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_MAT1p0_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN29) #define GPIO_EMC_D30 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) -#define GPIO_UART1_RTS (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) -#define GPIO_MAT1p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_UART1_RTS_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_MAT1p1_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN30) #define GPIO_EMC_D31 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN31) #define GPIO_MAT1p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN31) @@ -590,20 +590,20 @@ #define GPIO_EMC_A19 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN19) #define GPIO_EMC_A20 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) -#define GPIO_I2C2_SDA (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) -#define GPIO_SSP1_SCK (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_I2C2_SDA_4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_SSP1_SCK_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN20) #define GPIO_EMC_A21 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) -#define GPIO_I2C2_SCL (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) -#define GPIO_SSP1_SSEL (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_I2C2_SCL_4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_SSP1_SSEL_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN21) #define GPIO_EMC_A22 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) -#define GPIO_UART2_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) -#define GPIO_SSP1_MISO (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_UART2_TXD_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_SSP1_MISO_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN22) #define GPIO_EMC_A23 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) -#define GPIO_UART2_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) -#define GPIO_SSP1_MOSI (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_UART2_RXD_3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_SSP1_MOSI_4 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN23) #define GPIO_EMC_OE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN24) #define GPIO_EMC_WE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN25) @@ -611,38 +611,38 @@ #define GPIO_EMC_BLS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN27) #define GPIO_EMC_BLS2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_UART3_TXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_MAT2p0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_LCD_VD6 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_LCD_VD10 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) -#define GPIO_LCD_VD2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_UART3_TXD_4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_MAT2p0_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD6_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD10_2 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_LCD_VD2_2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28) #define GPIO_EMC_BLS3 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_UART3_RXD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_MAT2p1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_I2C2_SCL (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_LCD_VD7 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_LCD_VD11 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) -#define GPIO_LCD_VD2 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_UART3_RXD_4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_MAT2p1_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_I2C2_SCL_3 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD7_2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD11_3 (GPIO_ALT6 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_LCD_VD2_3 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29) #define GPIO_EMC_CS0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN30) #define GPIO_EMC_CS1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN31) #define GPIO_EMC_A24 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) -#define GPIO_MAT2p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_MAT2p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN0) #define GPIO_EMC_A25 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) -#define GPIO_MAT2p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_MAT2p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN1) -#define GPIO_MAT3p2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) -#define GPIO_I2C0_SDA (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_MAT3p2_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_I2C0_SDA_3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN2) -#define GPIO_UART4_RXD (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_UART4_RXD_2 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) #define GPIO_I2C0_SCL0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN3) -#define GPIO_UART4_OE (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) -#define GPIO_MAT3p3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) -#define GPIO_UART4_TXD (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_UART4_OE_2 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_MAT3p3_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_UART4_TXD_3 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT5 | GPIO_PIN4) /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h index d8b8e0d37..c432c6f25 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h @@ -42,584 +42,20 @@ #include -#include "chip.h" -#include "chip/lpc17_memorymap.h" +#include + +#if defined(LPC176x) +# include "chip/lpc176x_pinconn.h" +#elif defined(LPC178x) +# include "chip/lpc178x_pinconn.h" +#else +# error "Unrecognized LPC17xx family" +#endif /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ -#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ -#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ -#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ -#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ -#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ -#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ -#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ -#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ -#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ -#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ -#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ -#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ -#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ -#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ -#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ -#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ -#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ -#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ -#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ -#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ -#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ -#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ -#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) -#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) -#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) -#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) -#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) -#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) -#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) -#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) -#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) -#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) -#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) -#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) -#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) -#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) -#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) -#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) -#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) -#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) -#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) -#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) -#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) -#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) -#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) -#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ - -#define PINCONN_PINSEL_GPIO (0) -#define PINCONN_PINSEL_ALT1 (1) -#define PINCONN_PINSEL_ALT2 (2) -#define PINCONN_PINSEL_ALT3 (3) -#define PINCONN_PINSEL_MASK (3) - -#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) -#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) - -#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ -#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) -#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ -#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) -#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ -#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) -#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ -#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) -#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ -#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) -#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ -#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) -#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ -#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) -#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ -#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) -#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ -#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) -#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ -#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) -#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ -#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) -#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ -#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ -#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) - -/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ - -#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ -#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) -#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ -#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) -#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ -#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) -#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ -#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) -#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ -#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) -#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ -#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) -#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ -#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) -#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ -#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) -#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ -#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) -#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ -#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) -#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ -#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) -#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ -#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) -#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ -#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) -#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) -#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) - /* Bits 30-31: Reserved */ -/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ - -#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) -#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) -#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) -#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) -#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) - -/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ - -#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) -#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) -#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ -#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) -#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ -#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) -#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ -#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) -#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ -#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) -#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ -#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) -#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ -#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) -#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ -#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) -#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ -#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) -#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ -#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) -#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ -#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) -#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ -#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) -#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ -#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) -#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ -#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) -#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ -#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) - -/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ - -#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) -#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) -#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) -#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) -#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) -#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) -#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ -#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) -#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) -#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ -#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) -#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ -#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) -#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ -#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) -#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ -#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) -#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ -#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) -#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ -#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ - -#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-17: Reserved */ -#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ -#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) -#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ -#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ -/* No description of bits -- Does this register exist? */ - -/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ - -#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-23: Reserved */ -#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ -#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) -#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ -#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ - /* Bits 0-2: Reserved */ -#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ - /* Bits 4-31: Reserved */ -/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ - -#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ -#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ -#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ -#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ -#define PINCONN_PINMODE_MASK (3) - -#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) -#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) - -#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ -#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) -#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ -#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) -#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ -#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) -#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ -#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) -#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ -#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) -#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ -#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) -#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ -#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) -#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ -#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) -#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ -#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) -#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ -#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) -#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ -#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) -#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ -#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ -#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) - -/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ - -#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ -#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) -#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ -#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) -#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ -#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) -#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ -#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) -#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ -#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) -#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ -#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) -#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ -#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) -#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ -#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) -#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ -#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) -#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ -#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) -#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ -#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ - -#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ -#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) -#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ -#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ -#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ -#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) -#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ -#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) -#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ -#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ -#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) -#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ -#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) - -/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ - -#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ -#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) -#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ -#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) -#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ -#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) -#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ -#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) -#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ -#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) -#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ -#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) -#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ -#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) -#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ -#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) -#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ -#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) -#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ -#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) -#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ -#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) -#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ -#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) -#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ -#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) -#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ -#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) -#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ -#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) -#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ -#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) - -/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ - -#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ -#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) -#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ -#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) -#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ -#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) -#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ -#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) -#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ -#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) -#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ -#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) -#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ -#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) -#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ -#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) -#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ -#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) -#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ -#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) -#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ -#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) -#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ -#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) -#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ -#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) -#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ -#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Mode select register 5 (PINMODE5: 0x4002c054) - * Pin Mode select register 6 (PINMODE6: 0x4002c058) - * No bit definitions -- do these registers exist? - */ - -#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ - -#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-17: Reserved */ -#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ -#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) -#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ -#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ -/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ - -#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-23: Reserved */ -#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ -#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) -#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ -#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ - -#define PINCONN_ODMODE0_P0(n) (1 << (n)) - -#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ -#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ -#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ -#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ -#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ -#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ -#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ -#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ -#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ -#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ -#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ -#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ - /* Bits 12-14: Reserved */ -#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ -#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ -#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ -#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ -#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ -#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ -#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ -#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ -#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ -#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ -#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ -#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ - /* Bits 27-28: Reserved */ -#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ -#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ - /* Bit 31: Reserved */ -/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ - -#define PINCONN_ODMODE1_P1(n) (1 << (n)) - -#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ -#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ - /* Bits 2-3: Reserved */ -#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ - /* Bits 5-7: Reserved */ -#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ -#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ -#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ - /* Bits 11-13: Reserved */ -#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ -#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ -#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ -#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ -#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ -#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ -#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ -#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ -#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ -#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ -#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ -#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ -#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ -#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ -#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ -#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ -#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ -#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ - -/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ - -#define PINCONN_ODMODE2_P2(n) (1 << (n)) - -#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ -#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ -#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ -#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ -#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ -#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ -#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ -#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ -#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ -#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ -#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ -#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ -#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ -#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ - /* Bits 14-31: Reserved */ -/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ - -#define PINCONN_ODMODE3_P3(n) (1 << (n)) - /* Bits 0-24: Reserved */ -#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ -#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ - /* Bits 17-31: Reserved */ -/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ - -#define PINCONN_ODMODE4_P4(n) (1 << (n)) - /* Bits 0-27: Reserved */ -#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ -#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ - /* Bits 30-31: Reserved */ -/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ - -#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch - * filtering/slew rate control */ -#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch - * filtering/slew rate control */ - /* Bits 4-31: Reserved */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h index f3a003255..993369aa2 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -171,19 +171,36 @@ #elif defined(LPC178x) -/* Encoding: TT FFFF MMOV PPPN NNNN - Encoding: TTTT TTTT FFFF MMOV PPPN NNNN - */ -/* Encoding: FFFF MMOV PPPN NNNN - * - * Pin Function: FFFF - * Pin Mode bits: MM - * Open drain: O (output pins) - * Initial value: V (output pins) - * Port number: PPP (0-4) - * Pin number: NNNNN (0-31) +/* Encoding: TTTT TTTT FFFF MMOV PPPN NNNN + * + * Special Pin Functions: TTTT TTTT + * Pin Function: FFFF + * Pin Mode bits: MM + * Open drain: O (output pins) + * Initial value: V (output pins) + * Port number: PPP (0-4) + * Pin number: NNNNN (0-31) */ +/* Special Pin Functions + * For pins that has ADC/DAC, USB, I2C + */ + +#define GPIO_IOCON_TYPE_D_MASK (0x0000067f) /* All port except where ADC/DAC, USB, I2C is present */ +#define GPIO_IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12 to 13, P0:23 to 26, P1:30 to 31 */ +#define GPIO_IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */ +#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27 to 28, P5:2 to 3 */ +#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7 to 9 */ + +# define GPIO_HYS (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */ +# define GPIO_INV (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */ +# define GPIO_SLEW (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */ +# define GPIO_ADMODE (1 << 19) /* Bit 19: A/D Modes: 0-Analog, 1-Digital */ +# define GPIO_FILTER (1 << 20) /* Bit 20: Filter: 0-Off, 1-ON */ +# define GPIO_DACEN (1 << 21) /* Bit 21: DAC: 0-Disabled, 1-Enabled, P0:26 only */ +# define GPIO_I2CHS (1 << 22) /* Bit 22: Filter and Rate Control: 0-Enabled, 1-Disabled */ +# define GPIO_HIDRIVE (1 << 23) /* Bit 23: Current Sink: 0-4mA, 1-20mA P5:2 and P5:3 only,*/ + /* Pin Function bits: FFFF * Only meaningful when the GPIO function is GPIO_PIN */ @@ -198,24 +215,11 @@ # define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */ # define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */ # define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */ - # define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */ # define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */ # define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */ # define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */ -/* Options for each IOCON Types */ -//~ #define GPIO_TYPE_SHIFT (16) -//~ #define GPIO_TYPE_MASK (3 << GPIO_TYPE_SHIFT) -//~ # define GPIO_HYSTERIS (<< 0 << ) -//~ # define GPIO_INVERTED (<< 1 << ) -//~ # define GPIO_SLEW (<< 2 << ) -//~ # define GPIO_ADMODE (<< 3 << ) -//~ # define GPIO_FILTER (<< 4 << ) -//~ # define GPIO_DACEN (<< 5 << ) -//~ # define GPIO_I2CHS (<< 6 << ) -//~ # define GPIO_HIDRIVE (<< 7 << ) - #define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ #define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h index b2ec1cee4..9ab96b7d2 100644 --- a/nuttx/include/nuttx/sched.h +++ b/nuttx/include/nuttx/sched.h @@ -62,21 +62,30 @@ /* This is the maximum number of times that a lock can be set */ -#define MAX_LOCK_COUNT 127 +#define MAX_LOCK_COUNT 127 /* Values for the _TCB flags flag bits */ -#define TCB_FLAG_TTYPE_SHIFT (0) /* Bits 0-1: thread type */ -#define TCB_FLAG_TTYPE_MASK (3 << TCB_FLAG_TTYPE_SHIFT) -# define TCB_FLAG_TTYPE_TASK (0 << TCB_FLAG_TTYPE_SHIFT) /* Normal user task */ -# define TCB_FLAG_TTYPE_PTHREAD (1 << TCB_FLAG_TTYPE_SHIFT) /* User pthread */ -# define TCB_FLAG_TTYPE_KERNEL (2 << TCB_FLAG_TTYPE_SHIFT) /* Kernel thread */ -#define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ -#define TCB_FLAG_CANCEL_PENDING (1 << 3) /* Bit 3: Pthread cancel is pending */ -#define TCB_FLAG_ROUND_ROBIN (1 << 4) /* Bit 4: Round robin sched enabled */ +#define TCB_FLAG_TTYPE_SHIFT (0) /* Bits 0-1: thread type */ +#define TCB_FLAG_TTYPE_MASK (3 << TCB_FLAG_TTYPE_SHIFT) +# define TCB_FLAG_TTYPE_TASK (0 << TCB_FLAG_TTYPE_SHIFT) /* Normal user task */ +# define TCB_FLAG_TTYPE_PTHREAD (1 << TCB_FLAG_TTYPE_SHIFT) /* User pthread */ +# define TCB_FLAG_TTYPE_KERNEL (2 << TCB_FLAG_TTYPE_SHIFT) /* Kernel thread */ +#define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ +#define TCB_FLAG_CANCEL_PENDING (1 << 3) /* Bit 3: Pthread cancel is pending */ +#define TCB_FLAG_ROUND_ROBIN (1 << 4) /* Bit 4: Round robin sched enabled */ + +/* Values for struct child_status_s ch_flags */ + +#define CHILD_FLAG_TTYPE_SHIFT (0) /* Bits 0-1: child thread type */ +#define CHILD_FLAG_TTYPE_MASK (3 << CHILD_FLAG_TTYPE_SHIFT) +# define CHILD_FLAG_TTYPE_TASK (0 << CHILD_FLAG_TTYPE_SHIFT) /* Normal user task */ +# define CHILD_FLAG_TTYPE_PTHREAD (1 << CHILD_FLAG_TTYPE_SHIFT) /* User pthread */ +# define CHILD_FLAG_TTYPE_KERNEL (2 << CHILD_FLAG_TTYPE_SHIFT) /* Kernel thread */ +#define CHILD_FLAG_EXITED (1 << 0) /* Bit 2: The child thread has exit'ed */ /******************************************************************************** - * Global Type Definitions + * Public Type Definitions ********************************************************************************/ #ifndef __ASSEMBLY__ @@ -163,6 +172,22 @@ typedef struct environ_s environ_t; # define SIZEOF_ENVIRON_T(alloc) (sizeof(environ_t) + alloc - 1) #endif +/* This structure is used to maintin information about child tasks. + * pthreads work differently, they have join information. This is + * only for child tasks. + */ + +#ifdef CONFIG_SCHED_CHILD_STATUS +struct child_status_s +{ + FAR struct child_status_s *flink; + + uint8_t ch_flags; /* Child status: See CHILD_FLAG_* definitions */ + pid_y ch_pid; /* Child task ID */ + int ch_status; /* Child exit status */ +}; +#endif + /* This structure describes a reference counted D-Space region. This must be a * separately allocated "break-away" structure that can be owned by a task and * any pthreads created by the task. @@ -202,9 +227,13 @@ struct _TCB /* Task Management Fields *****************************************************/ pid_t pid; /* This is the ID of the thread */ -#ifdef CONFIG_SCHED_HAVE_PARENT +#ifdef CONFIG_SCHED_HAVE_PARENT /* Support parent-child relationship */ pid_t parent; /* This is the ID of the parent thread */ +#ifdef CONFIG_SCHED_CHILD_STATUS /* Retain child thread status */ + FAR struct child_status_s *children; /* Head of a list of child status */ +#else uint16_t nchildren; /* This is the number active children */ +#endif #endif start_t start; /* Thread start function */ entry_t entry; /* Entry Point into the thread */ @@ -357,33 +386,38 @@ typedef void (*sched_foreach_t)(FAR _TCB *tcb, FAR void *arg); #endif /* __ASSEMBLY__ */ /******************************************************************************** - * Global Function Prototypes + * Public Data ********************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif +/******************************************************************************** + * Public Function Prototypes + ********************************************************************************/ + /* TCB helpers */ -EXTERN FAR _TCB *sched_self(void); +FAR _TCB *sched_self(void); /* File system helpers */ #if CONFIG_NFILE_DESCRIPTORS > 0 -EXTERN FAR struct filelist *sched_getfiles(void); +FAR struct filelist *sched_getfiles(void); #if CONFIG_NFILE_STREAMS > 0 -EXTERN FAR struct streamlist *sched_getstreams(void); +FAR struct streamlist *sched_getstreams(void); #endif /* CONFIG_NFILE_STREAMS */ #endif /* CONFIG_NFILE_DESCRIPTORS */ #if CONFIG_NSOCKET_DESCRIPTORS > 0 -EXTERN FAR struct socketlist *sched_getsockets(void); +FAR struct socketlist *sched_getsockets(void); #endif /* CONFIG_NSOCKET_DESCRIPTORS */ /* Internal vfork support.The overall sequence is: @@ -417,7 +451,7 @@ void task_vforkabort(FAR _TCB *child, int errcode); * will be disabled throughout this enumeration! */ -EXTERN void sched_foreach(sched_foreach_t handler, FAR void *arg); +void sched_foreach(sched_foreach_t handler, FAR void *arg); #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/include/sched.h b/nuttx/include/sched.h index 4494d8ef5..9ccbf57b2 100644 --- a/nuttx/include/sched.h +++ b/nuttx/include/sched.h @@ -79,7 +79,7 @@ #endif /******************************************************************************** - * Global Type Definitions + * Public Type Definitions ********************************************************************************/ /* This is the POSIX-like scheduling parameter structure */ @@ -90,56 +90,61 @@ struct sched_param }; /******************************************************************************** - * Global Function Prototypes + * Public Data ********************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif +/******************************************************************************** + * Public Function Prototypes + ********************************************************************************/ + /* Task Control Interfaces (non-standard) */ #ifndef CONFIG_CUSTOM_STACK -EXTERN int task_init(FAR _TCB *tcb, const char *name, int priority, - FAR uint32_t *stack, uint32_t stack_size, - main_t entry, const char *argv[]); +int task_init(FAR _TCB *tcb, const char *name, int priority, + FAR uint32_t *stack, uint32_t stack_size, main_t entry, + FAR const char *argv[]); #else -EXTERN int task_init(FAR _TCB *tcb, const char *name, int priority, - main_t entry, const char *argv[]); +int task_init(FAR _TCB *tcb, const char *name, int priority, main_t entry, + FAR const char *argv[]); #endif -EXTERN int task_activate(FAR _TCB *tcb); +int task_activate(FAR _TCB *tcb); #ifndef CONFIG_CUSTOM_STACK -EXTERN int task_create(const char *name, int priority, int stack_size, - main_t entry, const char *argv[]); +int task_create(FAR const char *name, int priority, int stack_size, main_t entry, + FAR const char *argv[]); #else -EXTERN int task_create(const char *name, int priority, - main_t entry, const char *argv[]); +int task_create(FAR const char *name, int priority, main_t entry, + FAR const char *argv[]); #endif -EXTERN int task_delete(pid_t pid); -EXTERN int task_restart(pid_t pid); +int task_delete(pid_t pid); +int task_restart(pid_t pid); /* Task Scheduling Interfaces (based on POSIX APIs) */ -EXTERN int sched_setparam(pid_t pid, const struct sched_param *param); -EXTERN int sched_getparam(pid_t pid, struct sched_param *param); -EXTERN int sched_setscheduler(pid_t pid, int policy, - const struct sched_param *param); -EXTERN int sched_getscheduler(pid_t pid); -EXTERN int sched_yield(void); -EXTERN int sched_get_priority_max(int policy); -EXTERN int sched_get_priority_min(int policy); -EXTERN int sched_rr_get_interval(pid_t pid, struct timespec *interval); +int sched_setparam(pid_t pid, const struct sched_param *param); +int sched_getparam(pid_t pid, struct sched_param *param); +int sched_setscheduler(pid_t pid, int policy, + FAR const struct sched_param *param); +int sched_getscheduler(pid_t pid); +int sched_yield(void); +int sched_get_priority_max(int policy); +int sched_get_priority_min(int policy); +int sched_rr_get_interval(pid_t pid, FAR struct timespec *interval); /* Task Switching Interfaces (non-standard) */ -EXTERN int sched_lock(void); -EXTERN int sched_unlock(void); -EXTERN int sched_lockcount(void); +int sched_lock(void); +int sched_unlock(void); +int sched_lockcount(void); /* If instrumentation of the scheduler is enabled, then some outboard logic * must provide the following interfaces. @@ -147,9 +152,9 @@ EXTERN int sched_lockcount(void); #ifdef CONFIG_SCHED_INSTRUMENTATION -EXTERN void sched_note_start(FAR _TCB *tcb); -EXTERN void sched_note_stop(FAR _TCB *tcb); -EXTERN void sched_note_switch(FAR _TCB *pFromTcb, FAR _TCB *pToTcb); +void sched_note_start(FAR _TCB *tcb); +void sched_note_stop(FAR _TCB *tcb); +void sched_note_switch(FAR _TCB *pFromTcb, FAR _TCB *pToTcb); #else # define sched_note_start(t) diff --git a/nuttx/sched/Makefile b/nuttx/sched/Makefile index 38d3e047f..1ad244450 100644 --- a/nuttx/sched/Makefile +++ b/nuttx/sched/Makefile @@ -74,7 +74,10 @@ SCHED_SRCS += sched_reprioritize.c endif ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) -SCHED_SRCS += task_reparent.c +SCHED_SRCS += task_reparent.c +ifeq ($(CONFIG_SCHED_CHILD_STATUS),y) +SCHED_SRCS += task_childstatus.c +endif endif ifeq ($(CONFIG_SCHED_WAITPID),y) diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h index 95b42c7ae..b048f00a8 100644 --- a/nuttx/sched/os_internal.h +++ b/nuttx/sched/os_internal.h @@ -1,7 +1,7 @@ /**************************************************************************** * sched/os_internal.h * - * Copyright (C) 2007-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -269,6 +269,16 @@ int task_argsetup(FAR _TCB *tcb, FAR const char *name, FAR const char *argv[]); void task_exithook(FAR _TCB *tcb, int status); int task_deletecurrent(void); #ifdef CONFIG_SCHED_HAVE_PARENT +#ifdef CONFIG_SCHED_CHILD_STATUS +void weak_functiontask_initialize(void); +FAR struct child_status_s *task_allocchild(void); +void task_freechild(FAR struct child_status_s *status); +FAR struct child_status_s *task_addchild(FAR _TCB *tcb, pid_t pid, int status, + uint8_t flags); +FAR struct child_status_s *task_findchild(FAR _TCB *tcb, pid_t pid); +FAR struct child_status_s *task_removechild(FAR _TCB *tcb, pid_t pid); +void task_removechildren(FAR _TCB *tcb); +#endif int task_reparent(pid_t ppid, pid_t chpid); #endif #ifndef CONFIG_CUSTOM_STACK diff --git a/nuttx/sched/os_start.c b/nuttx/sched/os_start.c index a53ac2aa8..cb6a2c869 100644 --- a/nuttx/sched/os_start.c +++ b/nuttx/sched/os_start.c @@ -314,6 +314,17 @@ void os_start(void) kmm_initialize((void*)CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE); #endif + /* Initialize tasking data structures */ + +#if defined(CONFIG_SCHED_HAVE_PARENT) && defined(CONFIG_SCHED_CHILD_STATUS) +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (task_initialize != NULL) +#endif + { + task_initialize(); + } +#endif + /* Initialize the interrupt handling subsystem (if included) */ #ifdef CONFIG_HAVE_WEAKFUNCTIONS diff --git a/nuttx/sched/sched_waitid.c b/nuttx/sched/sched_waitid.c index eabc69afe..a3f7221df 100644 --- a/nuttx/sched/sched_waitid.c +++ b/nuttx/sched/sched_waitid.c @@ -155,7 +155,7 @@ int waitid(idtype_t idtype, id_t id, siginfo_t *info, int options) sched_lock(); - /* Verify that this task actually has children and that the the requeste + /* Verify that this task actually has children and that the the requested * TCB is actually a child of this task. */ diff --git a/nuttx/sched/task_childstatus.c b/nuttx/sched/task_childstatus.c new file mode 100644 index 000000000..ab5ace43a --- /dev/null +++ b/nuttx/sched/task_childstatus.c @@ -0,0 +1,365 @@ +/***************************************************************************** + * sched/task_childstatus.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include + +#include "os_internal.h" + +#if defined(CONFIG_SCHED_HAVE_PARENT) && defined(CONFIG_SCHED_CHILD_STATUS) + +/***************************************************************************** + * Private Types + *****************************************************************************/ +/* Globals are maintained in a structure to minimize name collisions. Note + * that there cannot be more that CONFIG_MAX_TASKS tasks in total. So using + * CONFIG_MAX_TASKS should be sufficient (at least one task, the IDLE thread, + * will have no parent). + */ + +struct child_pool_s +{ + struct child_status_s alloc[CONFIG_MAX_TASKS]; + FAR struct child_status_s *freelist; +}; + +/***************************************************************************** + * Private Data + *****************************************************************************/ + +static struct child_pool_s g_child_pool; + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: task_initialize + * + * Description: + * Initialize task related status. At present, this includes only the + * initialize of the child status pool. + * + * Parameters: + * None. + * + * Return Value: + * None. + * + * Assumptions: + * Called early in initializatin. No special precautions are required. + * + *****************************************************************************/ + +void task_initialize(void) +{ + FAR struct child_status_s *curr; + FAR struct child_status_s *prev; + int i; + + /* Save all of the child status structures in a free list */ + + prev = &g_child_pool.alloc[0]; + g_child_pool.freelist = prev; + for (i = 0; i < CONFIG_MAX_TASKS; i++) + { + curr = &g_child_pool.alloc[i] + prev->flink = curr; + prev = curr; + } +} + +/***************************************************************************** + * Name: task_allocchild + * + * Description: + * Allocate a child status structure by removing the next entry from a + * free list. + * + * Parameters: + * None. + * + * Return Value: + * On success, a non-NULL pointer to a child status structure. NULL is + * returned if there are no remaining, pre-allocated child status structures. + * + * Assumptions: + * Called during task creation in a safe context. No special precautions + * are required here. + * + *****************************************************************************/ + +FAR struct child_status_s *task_allocchild(void) +{ + FAR struct child_status_s *ret; + + /* Return the status block at the head of the free list */ + + ret = g_child_pool.freelist; + if (ret) + { + g_child_pool.freelist = ret->flink; + ret->flink = NULL; + } + + return ret; +} + +/***************************************************************************** + * Name: task_freechild + * + * Description: + * Release a child status structure by returning it to a free list. + * + * Parameters: + * status - The child status structure to be freed. + * + * Return Value: + * None. + * + * Assumptions: + * Called during task creation in a safe context. No special precautions + * are required here. + * + *****************************************************************************/ + +void task_freechild(FAR struct child_status_s *child) +{ + /* Return the child status structure to the free list */ + + if (child) + { + child->flink = g_child_pool.freelist; + g_child_pool.freelist = child; + } +} + +/***************************************************************************** + * Name: task_addchild + * + * Description: + * Find a child status structure in the given TCB. + * + * Parameters: + * tcb - The TCB of the parent task to containing the child status. + * pid - The ID of the child to create + * status - Child exit status (should be zero) + * flags - Child flags (see CHILD_FLAGS_* defininitions) + * + * Return Value: + * On success, a non-NULL pointer to a child status structure. NULL is + * returned if (1) there are no free status structures, or (2) an entry + * with this PID already exists. + * + * Assumptions: + * Called during task creation processing in a safe context. No special + * precautions are required here. + * + *****************************************************************************/ + +FAR struct child_status_s *task_addchild(FAR _TCB *tcb, pid_t pid, int status, + uint8_t flags) +{ + FAR struct child_status_s *child; + + /* Make sure that there is not already a structure for this PID */ + + child = task_findchild(tcb, pid); + if (child) + { + return NULL; + } + + /* Allocate a new status structure */ + + child = task_allocchild(void); + if (child) + { + /* Initialize the structure */ + + child->ch_flags = flags; + child->ch_pid = pid; + child->ch_status = status; + + /* Add the entry into the TCB list of children */ + + status->flink = tcb->children; + tcb->childen = status; + } + + return child; +} + +/***************************************************************************** + * Name: task_findchild + * + * Description: + * Find a child status structure in the given TCB. A reference to the + * child structure is returned, but the child remains the the TCB's list + * of children. + * + * Parameters: + * tcb - The TCB of the parent task to containing the child status. + * pid - The ID of the child to find. + * + * Return Value: + * On success, a non-NULL pointer to a child status structure. NULL is + * returned if there is child status structure for that pid in the TCB. + * + * Assumptions: + * Called during SIGCHLD processing in a safe context. No special precautions + * are required here. + * + *****************************************************************************/ + +FAR struct child_status_s *task_findchild(FAR _TCB *tcb, pid_t pid) +{ + FAR struct child_status_s *child; + + /* Find the status structure with the matching PID */ + + for (child = tcb->children; child; child = child->flink) + { + if (child->ch_pid == pid) + { + return child; + } + } + + return NULL; +} + +/***************************************************************************** + * Name: task_removechild + * + * Description: + * Remove one child structure from the TCB. The child is removed, but is + * not yet freed. task_freechild must be called in order to free the child + * status structure. + * + * Parameters: + * tcb - The TCB of the parent task to containing the child status. + * pid - The ID of the child to find. + * + * Return Value: + * On success, a non-NULL pointer to a child status structure. NULL is + * returned if there is child status structure for that pid in the TCB. + * + * Assumptions: + * Called during SIGCHLD processing in a safe context. No special precautions + * are required here. + * + *****************************************************************************/ + +FAR struct child_status_s *task_removechild(FAR _TCB *tcb, pid_t pid) +{ + FAR struct child_status_s *curr; + FAR struct child_status_s *prev; + + /* Find the status structure with the matching PID */ + + for (prev = NULL, curr = tcb->children; + curr; + prev = curr, curr = curr->flink) + { + if (curr->ch_pid == pid) + { + break; + } + } + + /* Did we find it? If so, remove it from the TCB. */ + + if (curr) + { + /* Do we remove it from mid-list? Or from the head of the list? */ + + if (prev) + { + prev->flink = curr->flink; + } + else + { + tcb->children = curr->flink; + } + + curr->flink = NULL; + } + + return curr; +} + +/***************************************************************************** + * Name: task_removechildren + * + * Description: + * Remove and free all child structure from the TCB. + * + * Parameters: + * tcb - The TCB of the parent task to containing the child status. + * + * Return Value: + * None. + * + * Assumptions: + * Called during task exit processing in a safe context. No special + * precautions are required here. + * + *****************************************************************************/ + +void task_removechildren(FAR _TCB *tcb) +{ + FAR struct child_status_s *curr; + FAR struct child_status_s *next; + + /* Remove all child structures for the TCB and return them to the freelist */ + + for (curr = tcb->children; curr; curr = next) + { + next = curr->flink; + task_freechild(curr); + } +} + +#endif /* CONFIG_SCHED_HAVE_PARENT && CONFIG_SCHED_CHILD_STATUS */ -- cgit v1.2.3 From 3cb33101a916278c43fd3995880a2a9440794e4c Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 22 Jan 2013 23:54:31 +0000 Subject: Add lpc178x_iocon.h from Rommel Marcelo git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5550 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h | 152 ++++++++++++++++++++++++ nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h | 2 +- 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100755 nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h new file mode 100755 index 000000000..0f820f7a6 --- /dev/null +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h @@ -0,0 +1,152 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/chip/lpc178x_iocon.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_IOCON_P0_OFFSET (LPC17_IOCON_BASE+0x0000) +#define LPC17_IOCON_P1_OFFSET (LPC17_IOCON_BASE+0x0080) +#define LPC17_IOCON_P2_OFFSET (LPC17_IOCON_BASE+0x0100) +#define LPC17_IOCON_P3_OFFSET (LPC17_IOCON_BASE+0x0180) +#define LPC17_IOCON_P4_OFFSET (LPC17_IOCON_BASE+0x0200) +#define LPC17_IOCON_P5_OFFSET (LPC17_IOCON_BASE+0x0280) + +#define LPC17_IOCON_PP0_OFFSET (0x0000) /* IOCON Port(n) register 0 */ +#define LPC17_IOCON_PP1_OFFSET (0x0004) /* IOCON Port(n) register 1 */ +#define LPC17_IOCON_PP2_OFFSET (0x0008) /* IOCON Port(n) register 2 */ +#define LPC17_IOCON_PP3_OFFSET (0x000c) /* IOCON Port(n) register 3 */ +#define LPC17_IOCON_PP4_OFFSET (0x0010) /* IOCON Port(n) register 4 */ +#define LPC17_IOCON_PP5_OFFSET (0x0014) /* IOCON Port(n) register 5 */ +#define LPC17_IOCON_PP6_OFFSET (0x0018) /* IOCON Port(n) register 6 */ +#define LPC17_IOCON_PP7_OFFSET (0x001c) /* IOCON Port(n) register 7 */ +#define LPC17_IOCON_PP8_OFFSET (0x0020) /* IOCON Port(n) register 8 */ +#define LPC17_IOCON_PP9_OFFSET (0x0024) /* IOCON Port(n) register 9 */ +#define LPC17_IOCON_PP10_OFFSET (0x0028) /* IOCON Port(n) register 10 */ +#define LPC17_IOCON_PP11_OFFSET (0x002c) /* IOCON Port(n) register 11 */ +#define LPC17_IOCON_PP12_OFFSET (0x0030) /* IOCON Port(n) register 12 */ +#define LPC17_IOCON_PP13_OFFSET (0x0034) /* IOCON Port(n) register 13 */ +#define LPC17_IOCON_PP14_OFFSET (0x0038) /* IOCON Port(n) register 14 */ +#define LPC17_IOCON_PP15_OFFSET (0x003c) /* IOCON Port(n) register 15 */ +#define LPC17_IOCON_PP16_OFFSET (0x0040) /* IOCON Port(n) register 16 */ +#define LPC17_IOCON_PP17_OFFSET (0x0044) /* IOCON Port(n) register 17 */ +#define LPC17_IOCON_PP18_OFFSET (0x0048) /* IOCON Port(n) register 18 */ +#define LPC17_IOCON_PP19_OFFSET (0x004c) /* IOCON Port(n) register 19 */ +#define LPC17_IOCON_PP20_OFFSET (0x0050) /* IOCON Port(n) register 20 */ +#define LPC17_IOCON_PP21_OFFSET (0x0054) /* IOCON Port(n) register 21 */ +#define LPC17_IOCON_PP22_OFFSET (0x0058) /* IOCON Port(n) register 22 */ +#define LPC17_IOCON_PP23_OFFSET (0x005c) /* IOCON Port(n) register 23 */ +#define LPC17_IOCON_PP24_OFFSET (0x0060) /* IOCON Port(n) register 24 */ +#define LPC17_IOCON_PP25_OFFSET (0x0064) /* IOCON Port(n) register 25 */ +#define LPC17_IOCON_PP26_OFFSET (0x0068) /* IOCON Port(n) register 26 */ +#define LPC17_IOCON_PP27_OFFSET (0x006c) /* IOCON Port(n) register 27 */ +#define LPC17_IOCON_PP28_OFFSET (0x0070) /* IOCON Port(n) register 28 */ +#define LPC17_IOCON_PP29_OFFSET (0x0074) /* IOCON Port(n) register 29 */ +#define LPC17_IOCON_PP30_OFFSET (0x0078) /* IOCON Port(n) register 30 */ +#define LPC17_IOCON_PP31_OFFSET (0x007c) /* IOCON Port(n) register 31 */ + +/* Register addresses ***************************************************************/ + +//~ #define LPC17_IOCON_PP1(portoffset) (portoffset+LPC17_IOCON_P0_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ +/* IOCON pin function select */ + +#define IOCON_FUNC_GPIO (0) +#define IOCON_FUNC_ALT1 (1) +#define IOCON_FUNC_ALT2 (2) +#define IOCON_FUNC_ALT3 (3) +#define IOCON_FUNC_ALT4 (4) +#define IOCON_FUNC_ALT5 (5) +#define IOCON_FUNC_ALT6 (6) +#define IOCON_FUNC_ALT7 (7) + +#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ +#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) +#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ +#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) +#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ +#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) +#define IOCON_INV_SHIFT (6) /* Bit 6: Typ D,A,I,W */ +#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT) +#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */ +#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT) +#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */ +#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT) +#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W*/ +#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT) +#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */ +#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT) +#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */ +#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) +#define IOCON_DACEN_SHIFT (16) /* Bit 16: Type A */ +#define IOCON_DACEN_MASK (1 << IOCON_DACEN_SHIFT) + +/* Pin modes */ + +#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ +#define IOCON_MODE_PD (1) /* 00: pin has a pull-down resistor enabled */ +#define IOCON_MODE_PU (2) /* 00: pin has a pull-up resistor enabled */ +#define IOCON_MODE_RM (3) /* 00: pin has repeater mode enabled */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h index c432c6f25..1ca4d163f 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h @@ -47,7 +47,7 @@ #if defined(LPC176x) # include "chip/lpc176x_pinconn.h" #elif defined(LPC178x) -# include "chip/lpc178x_pinconn.h" +# include "chip/lpc178x_iocon.h" #else # error "Unrecognized LPC17xx family" #endif -- cgit v1.2.3 From b10238efee96527ec14de35bc5bc63a8a02dc42c Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 23 Jan 2013 00:19:46 +0000 Subject: Missed changed from last lpc1788 check-in git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5551 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h index 0f820f7a6..b8c9ee480 100755 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H -#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H +#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H +#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H /************************************************************************************ * Included Files @@ -149,4 +149,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_IOCON_H */ +#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H */ -- cgit v1.2.3 From deb5fe51871666073a4e4dbb6de391612df38e4b Mon Sep 17 00:00:00 2001 From: Marco Bauer Date: Wed, 23 Jan 2013 15:29:24 +0100 Subject: timing changed and amber for manual added --- Makefile | 3 ++- apps/drivers/blinkm/blinkm.cpp | 42 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index f91e75d0b..84086347f 100644 --- a/Makefile +++ b/Makefile @@ -116,7 +116,8 @@ ifeq ($(SYSTYPE),Linux) SERIAL_PORTS ?= "/dev/ttyACM5,/dev/ttyACM4,/dev/ttyACM3,/dev/ttyACM2,/dev/ttyACM1,/dev/ttyACM0" endif ifeq ($(SERIAL_PORTS),) -SERIAL_PORTS = "\\\\.\\COM32,\\\\.\\COM31,\\\\.\\COM30,\\\\.\\COM29,\\\\.\\COM28,\\\\.\\COM27,\\\\.\\COM26,\\\\.\\COM25,\\\\.\\COM24,\\\\.\\COM23,\\\\.\\COM22,\\\\.\\COM21,\\\\.\\COM20,\\\\.\\COM19,\\\\.\\COM18,\\\\.\\COM17,\\\\.\\COM16,\\\\.\\COM15,\\\\.\\COM14,\\\\.\\COM13,\\\\.\\COM12,\\\\.\\COM11,\\\\.\\COM10,\\\\.\\COM9,\\\\.\\COM8,\\\\.\\COM7,\\\\.\\COM6,\\\\.\\COM5,\\\\.\\COM4,\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" +#SERIAL_PORTS = "\\\\.\\COM32,\\\\.\\COM31,\\\\.\\COM30,\\\\.\\COM29,\\\\.\\COM28,\\\\.\\COM27,\\\\.\\COM26,\\\\.\\COM25,\\\\.\\COM24,\\\\.\\COM23,\\\\.\\COM22,\\\\.\\COM21,\\\\.\\COM20,\\\\.\\COM19,\\\\.\\COM18,\\\\.\\COM17,\\\\.\\COM16,\\\\.\\COM15,\\\\.\\COM14,\\\\.\\COM13,\\\\.\\COM12,\\\\.\\COM11,\\\\.\\COM10,\\\\.\\COM9,\\\\.\\COM8,\\\\.\\COM7,\\\\.\\COM6,\\\\.\\COM5,\\\\.\\COM4,\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" +SERIAL_PORTS = "\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" endif upload: $(FIRMWARE_BUNDLE) $(UPLOADER) diff --git a/apps/drivers/blinkm/blinkm.cpp b/apps/drivers/blinkm/blinkm.cpp index aeee80905..2ff59d5f3 100644 --- a/apps/drivers/blinkm/blinkm.cpp +++ b/apps/drivers/blinkm/blinkm.cpp @@ -118,8 +118,8 @@ #include static const float MAX_CELL_VOLTAGE = 4.3f; -static const int LED_ONTIME = 100; -static const int LED_OFFTIME = 100; +static const int LED_ONTIME = 120; +static const int LED_OFFTIME = 120; static const int LED_BLINK = 1; static const int LED_NOBLINK = 0; @@ -167,7 +167,8 @@ private: LED_PURPLE, LED_GREEN, LED_BLUE, - LED_WHITE + LED_WHITE, + LED_AMBER }; work_s _work; @@ -178,6 +179,8 @@ private: int led_color_4; int led_color_5; int led_color_6; + int led_color_7; + int led_color_8; int led_blink; bool systemstate_run; @@ -250,6 +253,8 @@ BlinkM::BlinkM(int bus) : led_color_4(LED_OFF), led_color_5(LED_OFF), led_color_6(LED_OFF), + led_color_7(LED_OFF), + led_color_8(LED_OFF), led_blink(LED_NOBLINK), systemstate_run(false) { @@ -374,7 +379,7 @@ BlinkM::led() static int num_of_cells = 0; static int detected_cells_runcount = 0; - static int t_led_color[6] = { 0, 0, 0, 0, 0, 0}; + static int t_led_color[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; static int t_led_blink = 0; static int led_thread_runcount=0; static int led_interval = 1000; @@ -416,6 +421,8 @@ BlinkM::led() t_led_color[4] = LED_PURPLE; } t_led_color[5] = LED_OFF; + t_led_color[6] = LED_OFF; + t_led_color[7] = LED_OFF; t_led_blink = LED_BLINK; } else { t_led_color[0] = led_color_1; @@ -424,6 +431,8 @@ BlinkM::led() t_led_color[3] = led_color_4; t_led_color[4] = led_color_5; t_led_color[5] = led_color_6; + t_led_color[6] = led_color_7; + t_led_color[7] = led_color_8; t_led_blink = led_blink; } led_thread_ready = false; @@ -434,16 +443,19 @@ BlinkM::led() setLEDColor(LED_OFF); led_interval = LED_OFFTIME; } else { - setLEDColor(t_led_color[(led_thread_runcount / 2) % 6]); + setLEDColor(t_led_color[(led_thread_runcount / 2) % 8]); //led_interval = (led_thread_runcount & 1) : LED_ONTIME; led_interval = LED_ONTIME; } - if (led_thread_runcount == 11) { + if (led_thread_runcount == 15) { /* obtained data for the first file descriptor */ struct vehicle_status_s vehicle_status_raw; struct vehicle_gps_position_s vehicle_gps_position_raw; + memset(&vehicle_status_raw, 0, sizeof(vehicle_status_raw)); + memset(&vehicle_gps_position_raw, 0, sizeof(vehicle_gps_position_raw)); + bool new_data_vehicle_status; bool new_data_vehicle_gps_position; @@ -473,7 +485,8 @@ BlinkM::led() /* get number of used satellites in navigation */ num_of_used_sats = 0; - for(int satloop=0; satloop<20; satloop++) { + //for(int satloop=0; satloop<20; satloop++) { + for(int satloop=0; satloop Date: Wed, 23 Jan 2013 15:29:46 +0100 Subject: timing changed and amber for manual added --- Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 84086347f..f91e75d0b 100644 --- a/Makefile +++ b/Makefile @@ -116,8 +116,7 @@ ifeq ($(SYSTYPE),Linux) SERIAL_PORTS ?= "/dev/ttyACM5,/dev/ttyACM4,/dev/ttyACM3,/dev/ttyACM2,/dev/ttyACM1,/dev/ttyACM0" endif ifeq ($(SERIAL_PORTS),) -#SERIAL_PORTS = "\\\\.\\COM32,\\\\.\\COM31,\\\\.\\COM30,\\\\.\\COM29,\\\\.\\COM28,\\\\.\\COM27,\\\\.\\COM26,\\\\.\\COM25,\\\\.\\COM24,\\\\.\\COM23,\\\\.\\COM22,\\\\.\\COM21,\\\\.\\COM20,\\\\.\\COM19,\\\\.\\COM18,\\\\.\\COM17,\\\\.\\COM16,\\\\.\\COM15,\\\\.\\COM14,\\\\.\\COM13,\\\\.\\COM12,\\\\.\\COM11,\\\\.\\COM10,\\\\.\\COM9,\\\\.\\COM8,\\\\.\\COM7,\\\\.\\COM6,\\\\.\\COM5,\\\\.\\COM4,\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" -SERIAL_PORTS = "\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" +SERIAL_PORTS = "\\\\.\\COM32,\\\\.\\COM31,\\\\.\\COM30,\\\\.\\COM29,\\\\.\\COM28,\\\\.\\COM27,\\\\.\\COM26,\\\\.\\COM25,\\\\.\\COM24,\\\\.\\COM23,\\\\.\\COM22,\\\\.\\COM21,\\\\.\\COM20,\\\\.\\COM19,\\\\.\\COM18,\\\\.\\COM17,\\\\.\\COM16,\\\\.\\COM15,\\\\.\\COM14,\\\\.\\COM13,\\\\.\\COM12,\\\\.\\COM11,\\\\.\\COM10,\\\\.\\COM9,\\\\.\\COM8,\\\\.\\COM7,\\\\.\\COM6,\\\\.\\COM5,\\\\.\\COM4,\\\\.\\COM3,\\\\.\\COM2,\\\\.\\COM1,\\\\.\\COM0" endif upload: $(FIRMWARE_BUNDLE) $(UPLOADER) -- cgit v1.2.3 From f86f863834bf7eae566e4ccce00ecfef3f914b05 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 23 Jan 2013 14:38:13 +0000 Subject: Add single-wire UART support to STM32 serial driver git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5552 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 4 +++- nuttx/arch/arm/src/stm32/Kconfig | 19 ++++++++++++++++++- nuttx/arch/arm/src/stm32/stm32_serial.c | 27 ++++++++++++++++++++++++++- nuttx/include/nuttx/serial/tioctl.h | 23 +++++++++++++++-------- 4 files changed, 62 insertions(+), 11 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 75bfd457f..6c176c601 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4009,5 +4009,7 @@ * arch/arm/src/*/*_irq.c: Set the priority of the SVCALL exception to the highest possible value. * arch/armv7-m/up_hardfault.c: Fail if a hardfault occurs - while CONFIG_ARM7VM_USEBASEI=y. + while CONFIG_ARM7VM_USEBASEPRI=y. + * arch/arm/src/stm32/stm32_serial.c: Add support for USART + single wire more (Contributed by the PX4 team). diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 99dde3209..85cdebd35 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -457,32 +457,38 @@ config STM32_USART1 bool "USART1" default n select ARCH_HAVE_USART1 + select STM32_USART config STM32_USART2 bool "USART2" default n select ARCH_HAVE_USART2 + select STM32_USART config STM32_USART3 bool "USART3" default n select ARCH_HAVE_USART3 + select STM32_USART config STM32_UART4 bool "UART4" default n select ARCH_HAVE_UART4 + select STM32_USART config STM32_UART5 bool "UART5" default n select ARCH_HAVE_UART5 + select STM32_USART config STM32_USART6 bool "USART6" default n depends on STM32_STM32F20XX || STM32_STM32F40XX select ARCH_HAVE_USART6 + select STM32_USART config STM32_USB bool "USB Device" @@ -1804,8 +1810,11 @@ config STM32_TIM14_DAC2 endchoice +bool STM32_USART + bool + menu "U[S]ART Configuration" - depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_USART4 || STM32_USART5 || STM32_USART6 + depends on STM32_USART config USART1_RS485 bool "RS-485 on USART1" @@ -1968,6 +1977,14 @@ config SERIAL_TERMIOS endmenu +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + default n + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + menu "SPI Configuration" depends on STM32_SPI diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index e86fbcf6f..0151bd247 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_serial.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -1401,6 +1401,31 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) } break; +#ifdef CONFIG_STM32_USART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ + + uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + + if (arg == SER_SINGLEWIRE_ENABLED) + { + stm32_configgpio(priv->tx_gpio | GPIO_OPENDRAIN); + cr |= USART_CR3_HDSEL; + } + else + { + stm32_configgpio(priv->tx_gpio | GPIO_PUSHPULL); + cr &= ~USART_CR3_HDSEL; + } + + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); + } + break; +#endif + #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { diff --git a/nuttx/include/nuttx/serial/tioctl.h b/nuttx/include/nuttx/serial/tioctl.h index b309ff37c..a98b487a6 100644 --- a/nuttx/include/nuttx/serial/tioctl.h +++ b/nuttx/include/nuttx/serial/tioctl.h @@ -1,7 +1,7 @@ /******************************************************************************************** * include/nuttx/serial/tioctl.h * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -165,16 +165,23 @@ #define TIOCSRS485 _TIOC(0x002a) /* Set RS485 mode, arg: pointer to struct serial_rs485 */ #define TIOCGRS485 _TIOC(0x002b) /* Get RS485 mode, arg: pointer to struct serial_rs485 */ -/* Debugging */ +/* Definitions for flags used in struct serial_rs485 (Linux compatible) */ + +# define SER_RS485_ENABLED (1 << 0) /* Enable/disble RS-485 support */ +# define SER_RS485_RTS_ON_SEND (1 << 1) /* Logic level for RTS pin when sending */ +# define SER_RS485_RTS_AFTER_SEND (1 << 2) /* Logic level for RTS pin after sent */ +# define SER_RS485_RX_DURING_TX (1 << 4) + +/* Single-wire UART support */ -#define TIOCSERGSTRUCT _TIOC(0x002c) /* Get device TTY structure */ +#define TIOCSSINGLEWIRE _TIOC(0x002c) /* Set single-wire mode */ +#define TIOCGSINGLEWIRE _TIOC(0x002d) /* Get single-wire mode */ -/* Definitions used in struct serial_rs485 (Linux compatible) */ +# define SER_SINGLEWIRE_ENABLED (1 << 0) /* Enable/disable single-wire support */ + +/* Debugging */ -#define SER_RS485_ENABLED (1 << 0) /* Enable/disble RS-485 support */ -#define SER_RS485_RTS_ON_SEND (1 << 1) /* Logic level for RTS pin when sending */ -#define SER_RS485_RTS_AFTER_SEND (1 << 2) /* Logic level for RTS pin after sent */ -#define SER_RS485_RX_DURING_TX (1 << 4) +#define TIOCSERGSTRUCT _TIOC(0x002e) /* Get device TTY structure */ /******************************************************************************************** * Public Type Definitions -- cgit v1.2.3 From efd4250e84980453276f167e6d0ed5f594a37c76 Mon Sep 17 00:00:00 2001 From: Marco Bauer Date: Wed, 23 Jan 2013 15:38:38 +0100 Subject: timing changed and amber for manual added --- apps/drivers/blinkm/blinkm.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/apps/drivers/blinkm/blinkm.cpp b/apps/drivers/blinkm/blinkm.cpp index 2ff59d5f3..bc5c74de1 100644 --- a/apps/drivers/blinkm/blinkm.cpp +++ b/apps/drivers/blinkm/blinkm.cpp @@ -57,7 +57,7 @@ * System armed: * One message is made of 4 Blinks and a pause in the same length as the 4 blinks. * - * X-X-X-X-_-_-_-_- + * X-X-X-X-_-_-_-_-_-_- * ------------------------- * G G G M * P P P O @@ -67,26 +67,26 @@ * (X = on, _=off) * * The first 3 blinks indicates the status of the GPS-Signal (red): - * 0-4 satellites = X-X-X-X-_-_-_-_- - * 5 satellites = X-X-_-X-_-_-_-_- - * 6 satellites = X-_-_-X-_-_-_-_- - * >=7 satellites = _-_-_-X-_-_-_-_- + * 0-4 satellites = X-X-X-X-_-_-_-_-_-_- + * 5 satellites = X-X-_-X-_-_-_-_-_-_- + * 6 satellites = X-_-_-X-_-_-_-_-_-_- + * >=7 satellites = _-_-_-X-_-_-_-_-_-_- * If no GPS is found the first 3 blinks are white * * The fourth Blink indicates the Flightmode: - * MANUAL : off + * MANUAL : amber * STABILIZED : yellow * HOLD : blue * AUTO : green * * Battery Warning (low Battery Level): - * Continuously blinking in yellow X-X-X-X-X-X-X-X + * Continuously blinking in yellow X-X-X-X-X-X-X-X-X-X * * Battery Alert (critical Battery Level) - * Continuously blinking in red X-X-X-X-X-X-X-X + * Continuously blinking in red X-X-X-X-X-X-X-X-X-X * * General Error (no uOrb Data) - * Continuously blinking in white X-X-X-X-X-X-X-X + * Continuously blinking in white X-X-X-X-X-X-X-X-X-X * */ -- cgit v1.2.3 From 340a72b7cdfb3c1c79044f53decc055ee6c06f19 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 23 Jan 2013 22:23:46 +0000 Subject: Add logic to retain child task exit status if so configured git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5553 42af7a65-404d-4744-a932-0658087f49c3 --- nuttx/ChangeLog | 6 +- nuttx/Documentation/NuttxPortingGuide.html | 66 +++++++++++- nuttx/Documentation/NuttxUserGuide.html | 128 ++++++++++++++++++++--- nuttx/arch/arm/src/stm32/Kconfig | 2 +- nuttx/configs/README.txt | 71 ++++++++++++- nuttx/configs/sim/ostest/defconfig | 11 +- nuttx/include/nuttx/sched.h | 3 +- nuttx/include/signal.h | 12 ++- nuttx/include/sys/types.h | 4 +- nuttx/sched/Kconfig | 79 ++++++++++++++- nuttx/sched/os_internal.h | 7 +- nuttx/sched/os_start.c | 2 +- nuttx/sched/pthread_create.c | 11 +- nuttx/sched/sched_waitid.c | 75 ++++++++++++++ nuttx/sched/sched_waitpid.c | 62 +++++++++++- nuttx/sched/sig_action.c | 157 ++++++++++++++++++----------- nuttx/sched/task_childstatus.c | 125 ++++++++++++++--------- nuttx/sched/task_create.c | 16 +-- nuttx/sched/task_exithook.c | 109 +++++++++++++------- nuttx/sched/task_init.c | 3 +- nuttx/sched/task_reparent.c | 23 ++++- nuttx/sched/task_setup.c | 68 +++++++++++-- nuttx/sched/task_vfork.c | 9 +- 23 files changed, 836 insertions(+), 213 deletions(-) diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 6c176c601..38b1b6b1f 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4002,7 +4002,7 @@ Start of support of LCD1602 alphanumeric LCD. I need a few more parts before I can finish integrating this one. * arch/arm/src/*/chip.h and arch/arm/include/*/chip.h: Move all - priority ragnes from the src to the include chip.h header file. + priority ranges from the src to the include chip.h header file. * arch/arm/include/armv7-m/irq.h: Add inline functions to enable and disable interrupts via the BASEPRI register. * arch/arm/Kconfig: Add new option CONFIG_ARM7VM_USEBASEI @@ -4012,4 +4012,8 @@ while CONFIG_ARM7VM_USEBASEPRI=y. * arch/arm/src/stm32/stm32_serial.c: Add support for USART single wire more (Contributed by the PX4 team). + * sched/: Implement support for retaining child task status after + the child task exists. This is behavior required by POSIX. + But in NuttX is only enabled with CONFIG_SCHED_HAVE_PARENT and + CONFIG_SCHED_CHILD_STATUS diff --git a/nuttx/Documentation/NuttxPortingGuide.html b/nuttx/Documentation/NuttxPortingGuide.html index fec7106b0..fd358f423 100644 --- a/nuttx/Documentation/NuttxPortingGuide.html +++ b/nuttx/Documentation/NuttxPortingGuide.html @@ -12,7 +12,7 @@

NuttX RTOS Porting Guide

-

Last Updated: January 13, 2013

+

Last Updated: January 23, 2013

@@ -4481,11 +4481,73 @@ build instrumentation is selected. Set to zero to disable.
  • - CONFIG_SCHED_HAVE_PARENT: Remember the ID of the parent thread when a new child thread is created. + CONFIG_SCHED_HAVE_PARENT: Remember the ID of the parent thread when a new child task is created. This support enables some additional features (such as SIGCHLD) and modifies the behavior of other interfaces. For example, it makes waitpid() more standards complete by restricting the waited-for tasks to the children of the caller. Default: disabled.
    • +
  • + CONFIG_SCHED_CHILD_STATUS: If this option is selected, then the exit status of the child task will be retained after the child task exits. + This option should be selected if you require knowledge of a child process' exit status. + Without this setting, wait(), waitpid() or waitid() may fail. + For example, if you do: +

      +
    1. + Start child task +
      2. +
    2. + Wait for exit status (using wait(), waitpid() or waitid()). +
      3. +

    +

    + This can fail because the child task may run to completion before the wait begins. + There is a non-standard work-around in this case: + The above sequence will work if you disable pre-emption using sched_lock() prior to starting the child task, then re-enable pre-emption with sched_unlock() after the wait completes. + This works because the child task is not permitted to run until the wait is in place. +

    +

    + The standard solution would be to enable CONFIG_SCHED_CHILD_STATUS. + In this case the exit status of the child task is retained after the child exits and the wait will successful obtain the child task's exit status whether it is called before the child task exits or not. +

    +

    + Warning: + If you enable this feature, then your application must either (1) take responsibility for reaping the child status with wait(), waitpid() or waitid(), or (2) suppress retention of child status. + If you do not reap the child status, then you have a memory leak and your system will eventually fail. +

    + Retention of child status can be suppressed on the parent using logic like: +

    + 
      +struct sigaction sa;
+
+sa.sa_handler = SIG_IGN;
+sa.sa_flags = SA_NOCLDWAIT;
+int ret = sigaction(SIGCHLD, &sa, NULL);
+
    +
    • +
  • + CONFIG_PREALLOC_CHILDSTATUS: To prevent runaway child status allocations and to improve + allocation performance, child task exit status structures are pre-allocated when the system boots. + This setting determines the number of child status structures that will be pre-allocated. + If this setting is not defined or if it is defined to be zero then a value of 2*MAX_TASKS is used. +

    + Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. + However, the number of child status structures may need to be significantly larger because this number includes the maximum number of tasks that are running PLUS the number of tasks that have exit'ed without having their exit status reaped (via wait(), waitpid() or waitid()). +

    +

    + Obviously, if tasks spawn children indefinitely and never have the exit status reaped, then you may have a memory leak! + If you enable the SCHED_CHILD_STATUS feature, then your application must take responsibility for either (1) reaping the child status with wait(), waitpid() or waitid() or it must (2) suppress retention of child status. Otherwise, your system will eventually fail. +

    +

    + Retention of child status can be suppressed on the parent using logic like: +

    + 
      +struct sigaction sa;
+
+sa.sa_handler = SIG_IGN;
+sa.sa_flags = SA_NOCLDWAIT;
+int ret = sigaction(SIGCHLD, &sa, NULL);
+
    +
  • CONFIG_SYSTEM_TIME16: The range of system time is, by default, 32-bits. diff --git a/nuttx/Documentation/NuttxUserGuide.html b/nuttx/Documentation/NuttxUserGuide.html index 3cfb63f11..10e5eb7ba 100644 --- a/nuttx/Documentation/NuttxUserGuide.html +++ b/nuttx/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

    NuttX Operating System

    User's Manual

    by

    Gregory Nutt

    -

    Last Updated: January 13, 2013

    +

    Last Updated: January 23, 2013

    @@ -1767,20 +1767,114 @@ priority of the calling task is returned. -

    Scheduler locking interfaces

    +

    + Task Control Interfaces. +

    -

    Task synchronization interfaces

    + +

    + Parent and Child Tasks. + The task synchronization interfaces historically depend upon parent and child relationships between tasks. + But default, NuttX does not use any parent/child knowledge. + However, there are three important configuration options that can change that. +

      -
    • 2.3.4 waitpid
      • -
    • 2.3.5 waitid
      • -
    • 2.3.6 wait
      • -
    • 2.3.7 atexit
      • -
    • 2.3.8 on_exit
      • +
    • +

      + CONFIG_SCHED_HAVE_PARENT. + If this setting is defined, then it instructs NuttX to remember the task ID of the parent task when each new child task is created. + This support enables some additional features (such as SIGCHLD) and modifies the behavior of other interfaces. + For example, it makes waitpid() more standards complete by restricting the waited-for tasks to the children of the caller. +

      +
      • +
    • +

      + CONFIG_SCHED_CHILD_STATUS + If this option is selected, then the exit status of the child task will be retained after the child task exits. + This option should be selected if you require knowledge of a child process' exit status. + Without this setting, wait(), waitpid() or waitid() may fail. + For example, if you do: +

      +
        +
      1. + Start child task +
        2. +
      2. + Wait for exit status (using wait(), waitpid() or waitid()). +
        3. +
      +

      + This may fail because the child task may run to completion before the wait begins. + There is a non-standard work-around in this case: + The above sequence will work if you disable pre-emption using sched_lock() prior to starting the child task, then re-enable pre-emption with sched_unlock() after the wait completes. + This works because the child task is not permitted to run until the wait is in place. +

      +

      + The standard solution would be to enable CONFIG_SCHED_CHILD_STATUS. + In this case the exit status of the child task is retained after the child exits and the wait will successful obtain the child task's exit status whether it is called before the child task exits or not. +

      +
      • +
    • +

      + CONFIG_PREALLOC_CHILDSTATUS. + To prevent runaway child status allocations and to improve allocation performance, child task exit status structures are pre-allocated when the system boots. + This setting determines the number of child status structures that will be pre-allocated. + If this setting is not defined or if it is defined to be zero then a value of 2*MAX_TASKS is used. +

      +

      + Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. + However, the number of child status structures may need to be significantly larger because this number includes the maximum number of tasks that are running PLUS the number of tasks that have exit'ed without having their exit status reaped (via wait(), waitpid() or waitid()). +

      +

      + Obviously, if tasks spawn children indefinitely and never have the exit status reaped, then you may have a memory leak! + (See Warning below) +

      +
    +

    + Warning: + If you enable the CONFIG_SCHED_CHILD_STATUS feature, then your application must either (1) take responsibility for reaping the child status with wait(), waitpid() or waitid(), or (2) suppress retention of child status. + If you do not reap the child status, then you have a memory leak and your system will eventually fail. +

    + Retention of child status can be suppressed on the parent using logic like: +

    +
      +struct sigaction sa;
+
+sa.sa_handler = SIG_IGN;
+sa.sa_flags = SA_NOCLDWAIT;
+int ret = sigaction(SIGCHLD, &sa, NULL);
+

    2.3.1 sched_lock

    @@ -4589,10 +4683,14 @@ sigaction(). interface of the same name. Differences from the POSIX implementation include:
      -
    • Special values of sa_handler in the struct sigaction act input -not handled (SIG_DFL, SIG_IGN). -
    • All sa_flags in struct sigaction of act input are ignored -(all treated like SA_SIGINFO). +
    • + There are no default actions so the special value SIG_DFL is treated like SIG_IGN. +
      • +
    • + All sa_flags in struct sigaction of act input are ignored (all treated like SA_SIGINFO). + The one exception is if CONFIG_SCHED_CHILDSTATUS is defined; + then SA_NOCLDWAIT is supported but only for SIGCHLD. +

    2.8.7 sigprocmask

    diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 85cdebd35..41724be2d 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -1810,7 +1810,7 @@ config STM32_TIM14_DAC2 endchoice -bool STM32_USART +config STM32_USART bool menu "U[S]ART Configuration" diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index babdf7330..1b78567a3 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -334,12 +334,79 @@ defconfig -- This is a configuration file similar to the Linux CONFIG_TASK_NAME_SIZE - Specifies that maximum size of a task name to save in the TCB. Useful if scheduler instrumentation is selected. Set to zero to disable. - CONFIG_SCHED_HAVE_PARENT - Remember the ID of the parent thread - when a new child thread is created. This support enables some + CONFIG_SCHED_HAVE_PARENT - Remember the ID of the parent task + when a new child task is created. This support enables some additional features (such as SIGCHLD) and modifies the behavior of other interfaces. For example, it makes waitpid() more standards complete by restricting the waited-for tasks to the children of the caller. Default: disabled. + CONFIG_SCHED_CHILD_STATUS + If this option is selected, then the exit status of the child task + will be retained after the child task exits. This option should be + selected if you require knowledge of a child process' exit status. + Without this setting, wait(), waitpid() or waitid() may fail. For + example, if you do: + + 1) Start child task + 2) Wait for exit status (using wait(), waitpid(), or waitid()). + + This can fail because the child task may run to completion before + the wait begins. There is a non-standard work-around in this case: + The above sequence will work if you disable pre-emption using + sched_lock() prior to starting the child task, then re-enable pre- + emption with sched_unlock() after the wait completes. This works + because the child task is not permitted to run until the wait is in + place. + + The standard solution would be to enable CONFIG_SCHED_CHILD_STATUS. In + this case the exit status of the child task is retained after the + child exits and the wait will successful obtain the child task's + exit status whether it is called before the child task exits or not. + + Warning: If you enable this feature, then your application must + either (1) take responsibility for reaping the child status with wait(), + waitpid(), or waitid(), or (2) suppress retention of child status. + If you do not reap the child status, then you have a memory leak and + your system will eventually fail. + + Retention of child status can be suppressed on the parent using logic like: + + struct sigaction sa; + + sa.sa_handler = SIG_IGN; + sa.sa_flags = SA_NOCLDWAIT; + int ret = sigaction(SIGCHLD, &sa, NULL); + + CONFIG_PREALLOC_CHILDSTATUS + To prevent runaway child status allocations and to improve + allocation performance, child task exit status structures are pre- + allocated when the system boots. This setting determines the number + of child status structures that will be pre-allocated. If this + setting is not defined or if it is defined to be zero then a value + of 2*MAX_TASKS is used. + + Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. + However, the number of child status structures may need to be + significantly larger because this number includes the maximum number + of tasks that are running PLUS the number of tasks that have exit'ed + without having their exit status reaped (via wait(), waitid(), or + waitpid()). + + Obviously, if tasks spawn children indefinitely and never have the + exit status reaped, then you may have a memory leak! If you enable + the SCHED_CHILD_STATUS feature, then your application must take + responsibility for either (1) reaping the child status with wait(), + waitpid(), or waitid() or it must (2) suppress retention of child + status. Otherwise, your system will eventually fail. + + Retention of child status can be suppressed on the parent using logic like: + + struct sigaction sa; + + sa.sa_handler = SIG_IGN; + sa.sa_flags = SA_NOCLDWAIT; + int ret = sigaction(SIGCHLD, &sa, NULL); + CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - Used to initialize the internal time logic. CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions. diff --git a/nuttx/configs/sim/ostest/defconfig b/nuttx/configs/sim/ostest/defconfig index c8d5c501d..65f5330fc 100644 --- a/nuttx/configs/sim/ostest/defconfig +++ b/nuttx/configs/sim/ostest/defconfig @@ -82,10 +82,15 @@ CONFIG_BOARD_LOOPSPERMSEC=100 # CONFIG_SIM_M32 is not set # CONFIG_SIM_WALLTIME is not set +# +# External Memory Configuration +# + # # Architecture Options # # CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set # CONFIG_ARCH_DMA is not set # CONFIG_ARCH_IRQPRIO is not set # CONFIG_CUSTOM_STACK is not set @@ -93,6 +98,7 @@ CONFIG_BOARD_LOOPSPERMSEC=100 # CONFIG_ARCH_HAVE_VFORK is not set # CONFIG_ARCH_STACKDUMP is not set # CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set # # Board Settings @@ -132,6 +138,7 @@ CONFIG_RR_INTERVAL=0 # CONFIG_SCHED_INSTRUMENTATION is not set CONFIG_TASK_NAME_SIZE=32 CONFIG_SCHED_HAVE_PARENT=y +# CONFIG_SCHED_CHILD_STATUS is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -242,8 +249,8 @@ CONFIG_SERIAL=y # # File system configuration # -# CONFIG_FS_FAT is not set # CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set @@ -271,6 +278,7 @@ CONFIG_MM_REGIONS=1 # CONFIG_BINFMT_EXEPATH is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set +# CONFIG_BUILTIN is not set # CONFIG_PIC is not set # CONFIG_SYMTAB_ORDEREDBYNAME is not set @@ -318,7 +326,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Built-In Applications # -# CONFIG_BUILTIN is not set # # Examples diff --git a/nuttx/include/nuttx/sched.h b/nuttx/include/nuttx/sched.h index 9ab96b7d2..1e75b5020 100644 --- a/nuttx/include/nuttx/sched.h +++ b/nuttx/include/nuttx/sched.h @@ -74,6 +74,7 @@ #define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ #define TCB_FLAG_CANCEL_PENDING (1 << 3) /* Bit 3: Pthread cancel is pending */ #define TCB_FLAG_ROUND_ROBIN (1 << 4) /* Bit 4: Round robin sched enabled */ +#define TCB_FLAG_NOCLDWAIT (1 << 5) /* Bit 5: Do not retain child exit status */ /* Values for struct child_status_s ch_flags */ @@ -183,7 +184,7 @@ struct child_status_s FAR struct child_status_s *flink; uint8_t ch_flags; /* Child status: See CHILD_FLAG_* definitions */ - pid_y ch_pid; /* Child task ID */ + pid_t ch_pid; /* Child task ID */ int ch_status; /* Child exit status */ }; #endif diff --git a/nuttx/include/signal.h b/nuttx/include/signal.h index 7c6b4cd55..a02170242 100644 --- a/nuttx/include/signal.h +++ b/nuttx/include/signal.h @@ -129,11 +129,13 @@ /* struct sigaction flag values */ -#define SA_NOCLDSTOP 1 /* Do not generate SIGCHILD when - * children stop (ignored) */ -#define SA_SIGINFO 2 /* Invoke the signal-catching function - * with 3 args instead of 1 - * (always assumed) */ +#define SA_NOCLDSTOP (1 << 0) /* Do not generate SIGCHILD when + * children stop (ignored) */ +#define SA_SIGINFO (1 << 1) /* Invoke the signal-catching function + * with 3 args instead of 1 + * (always assumed) */ +#define SA_NOCLDWAIT (1 << 2) /* If signo=SIGCHLD, exit status of child + * processes will be discarded */ /* These are the possible values of the signfo si_code field */ diff --git a/nuttx/include/sys/types.h b/nuttx/include/sys/types.h index 95feee72e..38f091e8a 100644 --- a/nuttx/include/sys/types.h +++ b/nuttx/include/sys/types.h @@ -158,13 +158,13 @@ typedef uint16_t ino_t; * negative PID values are used to represent invalid PIDs. */ -typedef int pid_t; +typedef int16_t pid_t; /* id_t is a general identifier that can be used to contain at least a pid_t, * uid_t, or gid_t. */ -typedef unsigned int id_t; +typedef int16_t id_t; /* Signed integral type of the result of subtracting two pointers */ diff --git a/nuttx/sched/Kconfig b/nuttx/sched/Kconfig index 11d74b583..fe9a88085 100644 --- a/nuttx/sched/Kconfig +++ b/nuttx/sched/Kconfig @@ -42,13 +42,88 @@ config SCHED_HAVE_PARENT bool "Support parent/child task relationships" default n ---help--- - Remember the ID of the parent thread when a new child thread is + Remember the ID of the parent task when a new child task is created. This support enables some additional features (such as SIGCHLD) and modifies the behavior of other interfaces. For example, it makes waitpid() more standards complete by restricting the waited-for tasks to the children of the caller. Default: disabled. +config SCHED_CHILD_STATUS + bool "Retain child exit status" + default n + depends on SCHED_HAVE_PARENT + ---help--- + If this option is selected, then the exit status of the child task + will be retained after the child task exits. This option should be + selected if you require knowledge of a child process' exit status. + Without this setting, wait(), waitpid() or waitid() may fail. For + example, if you do: + + 1) Start child task + 2) Wait for exit status (using wait(), waitpid(), or waitid()). + + This can fail because the child task may run to completion before + the wait begins. There is a non-standard work-around in this case: + The above sequence will work if you disable pre-emption using + sched_lock() prior to starting the child task, then re-enable pre- + emption with sched_unlock() after the wait completes. This works + because the child task is not permitted to run until the wait is in + place. + + The standard solution would be to enable SCHED_CHILD_STATUS. In + this case the exit status of the child task is retained after the + child exits and the wait will successful obtain the child task's + exit status whether it is called before the child task exits or not. + + Warning: If you enable this feature, then your application must + either (1) take responsibility for reaping the child status with wait(), + waitpid(), or waitid(), or (2) suppress retention of child status. + If you do not reap the child status, then you have a memory leak and + your system will eventually fail. + + Retention of child status can be suppressed on the parent using logic like: + + struct sigaction sa; + + sa.sa_handler = SIG_IGN; + sa.sa_flags = SA_NOCLDWAIT; + int ret = sigaction(SIGCHLD, &sa, NULL); + +config PREALLOC_CHILDSTATUS + int "Number of pre-allocated child status" + default 0 + depends on SCHED_CHILD_STATUS + ---help--- + To prevent runaway child status allocations and to improve + allocation performance, child task exit status structures are pre- + allocated when the system boots. This setting determines the number + of child status structures that will be pre-allocated. If this + setting is not defined or if it is defined to be zero then a value + of 2*MAX_TASKS is used. + + Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. + However, the number of child status structures may need to be + significantly larger because this number includes the maximum number + of tasks that are running PLUS the number of tasks that have exit'ed + without having their exit status reaped (via wait(), waitid(), or + waitpid()). + + Obviously, if tasks spawn children indefinitely and never have the + exit status reaped, then you may have a memory leak! If you enable + the SCHED_CHILD_STATUS feature, then your application must take + responsibility for either (1) reaping the child status with wait(), + waitpid(), or waitid() or it must (2) suppress retention of child + status. Otherwise, your system will eventually fail. + + Retention of child status can be suppressed on the parent using logic like: + + struct sigaction sa; + + sa.sa_handler = SIG_IGN; + sa.sa_flags = SA_NOCLDWAIT; + int ret = sigaction(SIGCHLD, &sa, NULL); + config JULIAN_TIME bool "Enables Julian time conversions" default n @@ -88,7 +163,7 @@ config PRIORITY_INHERITANCE Set to enable support for priority inheritance on mutexes and semaphores. config SEM_PREALLOCHOLDERS - int "Pre-allocated holders" + int "Number of pre-allocated holders" default 16 depends on PRIORITY_INHERITANCE ---help--- diff --git a/nuttx/sched/os_internal.h b/nuttx/sched/os_internal.h index b048f00a8..7d5095bad 100644 --- a/nuttx/sched/os_internal.h +++ b/nuttx/sched/os_internal.h @@ -264,17 +264,16 @@ extern const tasklist_t g_tasklisttable[NUM_TASK_STATES]; int os_bringup(void); void task_start(void); int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, - main_t main); + main_t main, uint8_t ttype); int task_argsetup(FAR _TCB *tcb, FAR const char *name, FAR const char *argv[]); void task_exithook(FAR _TCB *tcb, int status); int task_deletecurrent(void); #ifdef CONFIG_SCHED_HAVE_PARENT #ifdef CONFIG_SCHED_CHILD_STATUS -void weak_functiontask_initialize(void); +void weak_function task_initialize(void); FAR struct child_status_s *task_allocchild(void); void task_freechild(FAR struct child_status_s *status); -FAR struct child_status_s *task_addchild(FAR _TCB *tcb, pid_t pid, int status, - uint8_t flags); +void task_addchild(FAR _TCB *tcb, FAR struct child_status_s *child); FAR struct child_status_s *task_findchild(FAR _TCB *tcb, pid_t pid); FAR struct child_status_s *task_removechild(FAR _TCB *tcb, pid_t pid); void task_removechildren(FAR _TCB *tcb); diff --git a/nuttx/sched/os_start.c b/nuttx/sched/os_start.c index cb6a2c869..a6d4e83b9 100644 --- a/nuttx/sched/os_start.c +++ b/nuttx/sched/os_start.c @@ -286,7 +286,7 @@ void os_start(void) /* Initialize the processor-specific portion of the TCB */ - g_idletcb.flags = TCB_FLAG_TTYPE_KERNEL; + g_idletcb.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_NOCLDWAIT); up_initial_state(&g_idletcb); /* Initialize the semaphore facility(if in link). This has to be done diff --git a/nuttx/sched/pthread_create.c b/nuttx/sched/pthread_create.c index dc2db2916..f4d0d8fdf 100644 --- a/nuttx/sched/pthread_create.c +++ b/nuttx/sched/pthread_create.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread_create.c * - * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -354,15 +354,10 @@ int pthread_create(FAR pthread_t *thread, FAR pthread_attr_t *attr, #endif } - /* Mark this task as a pthread (this setting will be needed in - * task_schedsetup() when up_initial_state() is called. - */ - - ptcb->flags |= TCB_FLAG_TTYPE_PTHREAD; - /* Initialize the task control block */ - ret = task_schedsetup(ptcb, priority, pthread_start, (main_t)start_routine); + ret = task_schedsetup(ptcb, priority, pthread_start, (main_t)start_routine, + TCB_FLAG_TTYPE_PTHREAD); if (ret != OK) { sched_releasetcb(ptcb); diff --git a/nuttx/sched/sched_waitid.c b/nuttx/sched/sched_waitid.c index a3f7221df..37ee26ce0 100644 --- a/nuttx/sched/sched_waitid.c +++ b/nuttx/sched/sched_waitid.c @@ -159,8 +159,29 @@ int waitid(idtype_t idtype, id_t id, siginfo_t *info, int options) * TCB is actually a child of this task. */ +#ifdef CONFIG_SCHED_CHILD_STATUS + if (rtcb->children == NULL) + { + /* There are no children */ + + err = ECHILD; + goto errout_with_errno; + } + else if (idtype == P_PID) + { + if (task_findchild(rtcb, (pid_t)id) == NULL) + { + /* This specific pid is not a child */ + + err = ECHILD; + goto errout_with_errno; + } + } +#else if (rtcb->nchildren == 0) { + /* There are no children */ + err = ECHILD; goto errout_with_errno; } @@ -175,11 +196,64 @@ int waitid(idtype_t idtype, id_t id, siginfo_t *info, int options) goto errout_with_errno; } } +#endif /* Loop until the child that we are waiting for dies */ for (;;) { +#ifdef CONFIG_SCHED_CHILD_STATUS + /* Check if the task has already died. Signals are not queued in + * NuttX. So a possibility is that the child has died and we + * missed the death of child signal (we got some other signal + * instead). + */ + + DEBUGASSERT(rtcb->children); + if (rtcb->children == NULL) + { + /* This should not happen. I am just wasting your FLASH. */ + + err = ECHILD; + goto errout_with_errno; + } + else if (idtype == P_PID) + { + FAR struct child_status_s *child; + + /* We are waiting for a specific PID. Get the current status + * of the child task. + */ + + child = task_findchild(rtcb, (pid_t)id); + DEBUGASSERT(child); + if (!child) + { + /* Yikes! The child status entry just disappeared! */ + + err = ECHILD; + goto errout_with_errno; + } + + /* Did the child exit? */ + + if ((child->ch_flags & CHILD_FLAG_EXITED) != 0) + { + /* The child has exited. Return the saved exit status */ + + info->si_signo = SIGCHLD; + info->si_code = CLD_EXITED; + info->si_value.sival_ptr = NULL; + info->si_pid = (pid_t)id; + info->si_status = child->ch_status; + + /* Discard the child entry and break out of the loop */ + + (void)task_removechild(rtcb, (pid_t)id); + task_freechild(child); + } + } +#else /* Check if the task has already died. Signals are not queued in * NuttX. So a possibility is that the child has died and we * missed the death of child signal (we got some other signal @@ -197,6 +271,7 @@ int waitid(idtype_t idtype, id_t id, siginfo_t *info, int options) err = EINTR; goto errout_with_errno; } +#endif /* Wait for any death-of-child signal */ diff --git a/nuttx/sched/sched_waitpid.c b/nuttx/sched/sched_waitpid.c index dc715b2e9..fe3f7167d 100644 --- a/nuttx/sched/sched_waitpid.c +++ b/nuttx/sched/sched_waitpid.c @@ -274,6 +274,9 @@ errout: pid_t waitpid(pid_t pid, int *stat_loc, int options) { FAR _TCB *rtcb = (FAR _TCB *)g_readytorun.head; +#ifdef CONFIG_SCHED_CHILD_STATUS + FAR struct child_status_s *child; +#endif FAR struct siginfo info; sigset_t sigset; int err; @@ -300,12 +303,33 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) sched_lock(); - /* Verify that this task actually has children and that the the requeste + /* Verify that this task actually has children and that the the request * TCB is actually a child of this task. */ +#ifdef CONFIG_SCHED_CHILD_STATUS + if (rtcb->children == NULL) + { + /* There are no children */ + + err = ECHILD; + goto errout_with_errno; + } + else if (pid != (pid_t)-1) + { + /* This specific pid is not a child */ + + if (task_findchild(rtcb, pid) == NULL) + { + err = ECHILD; + goto errout_with_errno; + } + } +#else if (rtcb->nchildren == 0) { + /* There are no children */ + err = ECHILD; goto errout_with_errno; } @@ -320,6 +344,7 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) goto errout_with_errno; } } +#endif /* Loop until the child that we are waiting for dies */ @@ -337,7 +362,12 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) * chilren. */ +#ifdef CONFIG_SCHED_CHILD_STATUS + DEBUGASSERT(rtcb->children); + if (rtcb->children == NULL) +#else if (rtcb->nchildren == 0) +#endif { /* There were one or more children when we started so they * must have exit'ed. There are just no bread crumbs left @@ -351,6 +381,35 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) } else { +#ifdef CONFIG_SCHED_CHILD_STATUS + /* We are waiting for a specific PID. Get the current status + * of the child task. + */ + + child = task_findchild(rtcb, pid); + DEBUGASSERT(child); + if (!child) + { + /* Yikes! The child status entry just disappeared! */ + + err = ECHILD; + goto errout_with_errno; + } + + /* Did the child exit? */ + + if ((child->ch_flags & CHILD_FLAG_EXITED) != 0) + { + /* The child has exited. Return the saved exit status */ + + *stat_loc = child->ch_status; + + /* Discard the child entry and break out of the loop */ + + (void)task_removechild(rtcb, pid); + task_freechild(child); + } +#else /* We are waiting for a specific PID. We can use kill() with * signal number 0 to determine if that task is still alive. */ @@ -368,6 +427,7 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) err = ECHILD; goto errout_with_errno; } +#endif } /* Wait for any death-of-child signal */ diff --git a/nuttx/sched/sig_action.c b/nuttx/sched/sig_action.c index fef5f1558..708667993 100644 --- a/nuttx/sched/sig_action.c +++ b/nuttx/sched/sig_action.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/sig_action.c * - * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,6 +43,7 @@ #include #include #include +#include #include "os_internal.h" #include "sig_internal.h" @@ -156,10 +157,11 @@ static FAR sigactq_t *sig_allocateaction(void) * Assumptions: * * POSIX Compatibility: - * - Special values of sa_handler in the struct sigaction - * act input not handled (SIG_DFL, SIG_IGN). - * - All sa_flags in struct sigaction of act input are - * ignored (all treated like SA_SIGINFO). + * - There are no default actions so the special value SIG_DFL is treated + * like SIG_IGN. + * - All sa_flags in struct sigaction of act input are ignored (all + * treated like SA_SIGINFO). The one exception is if CONFIG_SCHED_CHILDSTATUS + * is defined; then SA_NOCLDWAIT is supported but only for SIGCHLD * ****************************************************************************/ @@ -167,90 +169,129 @@ int sigaction(int signo, FAR const struct sigaction *act, FAR struct sigaction * { FAR _TCB *rtcb = (FAR _TCB*)g_readytorun.head; FAR sigactq_t *sigact; - int ret = ERROR; /* Assume failure */ + int ret; /* Since sigactions can only be installed from the running thread of * execution, no special precautions should be necessary. */ - /* Verify the signal */ + /* Verify the signal number */ - if (GOOD_SIGNO(signo)) + if (!GOOD_SIGNO(signo)) { - ret = OK; /* Assume success */ + set_errno(EINVAL); + return ERROR; + } - /* Find the signal in the sigactionq */ + /* Find the signal in the sigactionq */ - sigact = sig_findaction(rtcb, signo); + sigact = sig_findaction(rtcb, signo); - /* Return the old sigaction value if so requested */ + /* Return the old sigaction value if so requested */ - if (oact) + if (oact) + { + if (sigact) { - if (sigact) - { - COPY_SIGACTION(oact, &sigact->act); - } - else - { - /* There isn't an old value */ - - oact->sa_u._sa_handler = NULL; - oact->sa_mask = NULL_SIGNAL_SET; - oact->sa_flags = 0; - } + COPY_SIGACTION(oact, &sigact->act); + } + else + { + /* There isn't an old value */ + + oact->sa_u._sa_handler = NULL; + oact->sa_mask = NULL_SIGNAL_SET; + oact->sa_flags = 0; } + } + + /* If the argument act is a null pointer, signal handling is unchanged; + * thus, the call can be used to enquire about the current handling of + * a given signal. + */ - /* If no sigaction was found, but one is needed, then - * allocate one. + if (!act) + { + return OK; + } + +#if defined(CONFIG_SCHED_HAVE_PARENT) && defined(CONFIG_SCHED_CHILD_STATUS) + + /* Handle a special case. Retention of child status can be suppressed + * if signo == SIGCHLD and sa_flags == SA_NOCLDWAIT. + * + * POSIX.1 leaves it unspecified whether a SIGCHLD signal is generated + * when a child process terminates. In NuttX, a SIGCHLD signal is + * generated in this case; but in some other implementations, it may not + * be. + */ + + if (signo == SIGCHLD && (act->sa_flags & SA_NOCLDWAIT) != 0) + { + irqstate_t flags; + + /* We do require a critical section to muck with the TCB values that + * can be modified by the child thread. */ - if (!sigact && act && act->sa_u._sa_handler) - { - sigact = sig_allocateaction(); + flags = irqsave(); - /* An error has occurred if we could not allocate the sigaction */ + /* Mark that status should be not be retained */ - if (!sigact) - { - ret = ERROR; - } - else - { - /* Put the signal number in the queue entry */ + rtcb->flags |= TCB_FLAG_NOCLDWAIT; - sigact->signo = (uint8_t)signo; + /* Free all pending exit status */ - /* Add the new sigaction to sigactionq */ + task_removechildren(rtcb); + irqrestore(flags); + } +#endif - sq_addlast((FAR sq_entry_t*)sigact, &rtcb->sigactionq); - } - } + /* Handle the case where no sigaction is supplied (SIG_IGN) */ + + if (act->sa_u._sa_handler == SIG_IGN) + { + /* If there is a old sigaction, remove it from sigactionq */ + + sq_rem((FAR sq_entry_t*)sigact, &rtcb->sigactionq); + + /* And deallocate it */ + + sig_releaseaction(sigact); + } - /* Set the new sigaction if so requested */ + /* A sigaction has been supplied */ - if ((sigact) && (act)) + else + { + /* Check if a sigaction was found */ + + if (!sigact) { - /* Check if it is a request to install a new handler */ + /* No sigaction was found, but one is needed. Allocate one. */ - if (act->sa_u._sa_handler) - { - COPY_SIGACTION(&sigact->act, act); - } + sigact = sig_allocateaction(); - /* No.. It is a request to remove the old handler */ + /* An error has occurred if we could not allocate the sigaction */ - else - { - /* Remove the old sigaction from sigactionq */ + if (!sigact) + { + set_errno(ENOMEM); + return ERROR; + } + + /* Put the signal number in the queue entry */ - sq_rem((FAR sq_entry_t*)sigact, &rtcb->sigactionq); + sigact->signo = (uint8_t)signo; - /* And deallocate it */ + /* Add the new sigaction to sigactionq */ - sig_releaseaction(sigact); - } + sq_addlast((FAR sq_entry_t*)sigact, &rtcb->sigactionq); } + + /* Set the new sigaction */ + + COPY_SIGACTION(&sigact->act, act); } return ret; diff --git a/nuttx/sched/task_childstatus.c b/nuttx/sched/task_childstatus.c index ab5ace43a..0f6d36c29 100644 --- a/nuttx/sched/task_childstatus.c +++ b/nuttx/sched/task_childstatus.c @@ -39,24 +39,44 @@ #include +#include #include +#include #include "os_internal.h" #if defined(CONFIG_SCHED_HAVE_PARENT) && defined(CONFIG_SCHED_CHILD_STATUS) /***************************************************************************** - * Private Types + * Pre-processor Definitions *****************************************************************************/ -/* Globals are maintained in a structure to minimize name collisions. Note - * that there cannot be more that CONFIG_MAX_TASKS tasks in total. So using - * CONFIG_MAX_TASKS should be sufficient (at least one task, the IDLE thread, - * will have no parent). +/* Note that there cannot be more that CONFIG_MAX_TASKS tasks in total. + * However, the number of child status structures may need to be significantly + * larger because this number includes the maximum number of tasks that are + * running PLUS the number of tasks that have exit'ed without having their + * exit status reaped (via wait(), waitid(), or waitpid()). + * + * Obviously, if tasks spawn children indefinitely and never have the exit + * status reaped, then you have a memory leak! */ +#if !defined(CONFIG_PREALLOC_CHILDSTATUS) || CONFIG_PREALLOC_CHILDSTATUS == 0 +# undef CONFIG_PREALLOC_CHILDSTATUS +# define CONFIG_PREALLOC_CHILDSTATUS (2*CONFIG_MAX_TASKS) +#endif + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_CHILDSTATUS +#endif + +/***************************************************************************** + * Private Types + *****************************************************************************/ +/* Globals are maintained in a structure to minimize name collisions. */ + struct child_pool_s { - struct child_status_s alloc[CONFIG_MAX_TASKS]; + struct child_status_s alloc[CONFIG_PREALLOC_CHILDSTATUS]; FAR struct child_status_s *freelist; }; @@ -70,6 +90,40 @@ static struct child_pool_s g_child_pool; * Private Functions *****************************************************************************/ +/***************************************************************************** + * Name: task_dumpchildren + * + * Description: + * Dump all of the children when the part TCB list is modified. + * + * Parameters: + * tcb - The parent TCB. + * + * Return Value: + * None. + * + * Assumptions: + * Called early in initialization. No special precautions are required. + * + *****************************************************************************/ + +#ifdef CONFIG_DEBUG_CHILDSTATUS +static void task_dumpchildren(FAR _TCB *tcb, FAR const char *msg) +{ + FAR struct child_status_s *child; + int i; + + dbg("Parent TCB=%p: %s\n", tcb, msg); + for (i = 0, child = tcb->children; child; i++, child = child->flink) + { + dbg(" %d. ch_flags=%02x ch_pid=%d ch_status=%d\n", + i, child->ch_flags, child->ch_pid, child->ch_status); + } +} +#else +# task_dumpchildren(t,m) +#endif + /***************************************************************************** * Public Functions *****************************************************************************/ @@ -88,7 +142,7 @@ static struct child_pool_s g_child_pool; * None. * * Assumptions: - * Called early in initializatin. No special precautions are required. + * Called early in initialization. No special precautions are required. * *****************************************************************************/ @@ -102,11 +156,11 @@ void task_initialize(void) prev = &g_child_pool.alloc[0]; g_child_pool.freelist = prev; - for (i = 0; i < CONFIG_MAX_TASKS; i++) + for (i = 0; i < CONFIG_PREALLOC_CHILDSTATUS; i++) { - curr = &g_child_pool.alloc[i] + curr = &g_child_pool.alloc[i]; prev->flink = curr; - prev = curr; + prev = curr; } } @@ -140,7 +194,7 @@ FAR struct child_status_s *task_allocchild(void) if (ret) { g_child_pool.freelist = ret->flink; - ret->flink = NULL; + ret->flink = NULL; } return ret; @@ -170,7 +224,7 @@ void task_freechild(FAR struct child_status_s *child) if (child) { - child->flink = g_child_pool.freelist; + child->flink = g_child_pool.freelist; g_child_pool.freelist = child; } } @@ -179,18 +233,14 @@ void task_freechild(FAR struct child_status_s *child) * Name: task_addchild * * Description: - * Find a child status structure in the given TCB. + * Add a child status structure in the given TCB. * * Parameters: * tcb - The TCB of the parent task to containing the child status. - * pid - The ID of the child to create - * status - Child exit status (should be zero) - * flags - Child flags (see CHILD_FLAGS_* defininitions) + * child - The structure to be added * * Return Value: - * On success, a non-NULL pointer to a child status structure. NULL is - * returned if (1) there are no free status structures, or (2) an entry - * with this PID already exists. + * N * * Assumptions: * Called during task creation processing in a safe context. No special @@ -198,37 +248,14 @@ void task_freechild(FAR struct child_status_s *child) * *****************************************************************************/ -FAR struct child_status_s *task_addchild(FAR _TCB *tcb, pid_t pid, int status, - uint8_t flags) +void task_addchild(FAR _TCB *tcb, FAR struct child_status_s *child) { - FAR struct child_status_s *child; + /* Add the entry into the TCB list of children */ - /* Make sure that there is not already a structure for this PID */ + child->flink = tcb->children; + tcb->children = child; - child = task_findchild(tcb, pid); - if (child) - { - return NULL; - } - - /* Allocate a new status structure */ - - child = task_allocchild(void); - if (child) - { - /* Initialize the structure */ - - child->ch_flags = flags; - child->ch_pid = pid; - child->ch_status = status; - - /* Add the entry into the TCB list of children */ - - status->flink = tcb->children; - tcb->childen = status; - } - - return child; + task_dumpchildren(tcb, "task_addchild"); } /***************************************************************************** @@ -325,6 +352,7 @@ FAR struct child_status_s *task_removechild(FAR _TCB *tcb, pid_t pid) } curr->flink = NULL; + task_dumpchildren(tcb, "task_removechild"); } return curr; @@ -360,6 +388,9 @@ void task_removechildren(FAR _TCB *tcb) next = curr->flink; task_freechild(curr); } + + tcb->children = NULL; + task_dumpchildren(tcb, "task_removechildren"); } #endif /* CONFIG_SCHED_HAVE_PARENT && CONFIG_SCHED_CHILD_STATUS */ diff --git a/nuttx/sched/task_create.c b/nuttx/sched/task_create.c index 801706cbf..2ed929ab0 100644 --- a/nuttx/sched/task_create.c +++ b/nuttx/sched/task_create.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/task_create.c * - * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -81,7 +81,7 @@ * * Input Parameters: * name - Name of the new task - * type - Type of the new task + * ttype - Type of the new task * priority - Priority of the new task * stack_size - size (in bytes) of the stack needed * entry - Entry point of a new task @@ -99,10 +99,10 @@ ****************************************************************************/ #ifndef CONFIG_CUSTOM_STACK -static int thread_create(const char *name, uint8_t type, int priority, +static int thread_create(const char *name, uint8_t ttype, int priority, int stack_size, main_t entry, const char **argv) #else -static int thread_create(const char *name, uint8_t type, int priority, +static int thread_create(const char *name, uint8_t ttype, int priority, main_t entry, const char **argv) #endif { @@ -142,15 +142,9 @@ static int thread_create(const char *name, uint8_t type, int priority, } #endif - /* Mark the type of this thread (this setting will be needed in - * task_schedsetup() when up_initial_state() is called. - */ - - tcb->flags |= type; - /* Initialize the task control block */ - ret = task_schedsetup(tcb, priority, task_start, entry); + ret = task_schedsetup(tcb, priority, task_start, entry, ttype); if (ret != OK) { goto errout_with_tcb; diff --git a/nuttx/sched/task_exithook.c b/nuttx/sched/task_exithook.c index 1106f2885..1813c12ed 100644 --- a/nuttx/sched/task_exithook.c +++ b/nuttx/sched/task_exithook.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/task_exithook.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -202,51 +202,86 @@ static inline void task_sigchild(FAR _TCB *tcb, int status) FAR _TCB *ptcb; siginfo_t info; - /* Keep things stationary through the following */ + /* Only exiting tasks should generate SIGCHLD. pthreads use other + * mechansims. + */ - sched_lock(); + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_TASK) + { + /* Keep things stationary through the following */ - /* Get the TCB of the receiving task */ + sched_lock(); - ptcb = sched_gettcb(tcb->parent); - if (!ptcb) - { - /* The parent no longer exists... bail */ + /* Get the TCB of the receiving task */ - sched_unlock(); - return; - } + ptcb = sched_gettcb(tcb->parent); + if (!ptcb) + { + /* The parent no longer exists... bail */ - /* Decrement the number of children from this parent */ + sched_unlock(); + return; + } - DEBUGASSERT(ptcb->nchildren > 0); - ptcb->nchildren--; +#ifdef CONFIG_SCHED_CHILD_STATUS + /* Check if the parent task has suppressed retention of child exit + * status information. Only 'tasks' report exit status, not pthreads. + * pthreads have a different mechanism. + */ - /* Set the parent to an impossible PID. We do this because under certain - * conditions, task_exithook() can be called multiple times. If this - * function is called again, sched_gettcb() will fail on the invalid - * parent PID above, nchildren will be decremented once and all will be - * well. - */ + if ((ptcb->flags & TCB_FLAG_NOCLDWAIT) == 0) + { + FAR struct child_status_s *child; - tcb->parent = INVALID_PROCESS_ID; + /* No.. Find the exit status entry for this task in the parent TCB */ - /* Create the siginfo structure. We don't actually know the cause. That - * is a bug. Let's just say that the child task just exit-ted for now. - */ + child = task_findchild(ptcb, getpid()); + DEBUGASSERT(child); + if (child) + { + /* Mark that the child has exit'ed */ - info.si_signo = SIGCHLD; - info.si_code = CLD_EXITED; - info.si_value.sival_ptr = NULL; - info.si_pid = tcb->pid; - info.si_status = status; + child->ch_flags |= CHILD_FLAG_EXITED; - /* Send the signal. We need to use this internal interface so that we can - * provide the correct si_code value with the signal. - */ + /* Save the exit status */ + + child->ch_status = status; + } + } +#else + /* Decrement the number of children from this parent */ - (void)sig_received(ptcb, &info); - sched_unlock(); + DEBUGASSERT(ptcb->nchildren > 0); + ptcb->nchildren--; +#endif + + /* Set the parent to an impossible PID. We do this because under + * certain conditions, task_exithook() can be called multiple times. + * If this function is called again, sched_gettcb() will fail on the + * invalid parent PID above, nchildren will be decremented once and + * all will be well. + */ + + tcb->parent = INVALID_PROCESS_ID; + + /* Create the siginfo structure. We don't actually know the cause. + * That is a bug. Let's just say that the child task just exit-ted + * for now. + */ + + info.si_signo = SIGCHLD; + info.si_code = CLD_EXITED; + info.si_value.sival_ptr = NULL; + info.si_pid = tcb->pid; + info.si_status = status; + + /* Send the signal. We need to use this internal interface so that we + * can provide the correct si_code value with the signal. + */ + + (void)sig_received(ptcb, &info); + sched_unlock(); + } } #else # define task_sigchild(tcb,status) @@ -344,6 +379,12 @@ void task_exithook(FAR _TCB *tcb, int status) (void)lib_flushall(tcb->streams); #endif + /* Discard any un-reaped child status (no zombies here!) */ + +#if defined(CONFIG_SCHED_HAVE_PARENT) && defined(CONFIG_SCHED_CHILD_STATUS) + task_removechildren(tcb); +#endif + /* Free all file-related resources now. This gets called again * just be be certain when the TCB is delallocated. However, we * really need to close files as soon as possible while we still diff --git a/nuttx/sched/task_init.c b/nuttx/sched/task_init.c index 31fc5ef70..0f0fdc68e 100644 --- a/nuttx/sched/task_init.c +++ b/nuttx/sched/task_init.c @@ -141,7 +141,8 @@ int task_init(FAR _TCB *tcb, const char *name, int priority, /* Initialize the task control block */ - ret = task_schedsetup(tcb, priority, task_start, entry); + ret = task_schedsetup(tcb, priority, task_start, entry, + TCB_FLAG_TTYPE_TASK); if (ret == OK) { /* Setup to pass parameters to the new task */ diff --git a/nuttx/sched/task_reparent.c b/nuttx/sched/task_reparent.c index 244825f80..28d371bf1 100644 --- a/nuttx/sched/task_reparent.c +++ b/nuttx/sched/task_reparent.c @@ -71,6 +71,9 @@ int task_reparent(pid_t ppid, pid_t chpid) { +#ifdef CONFIG_SCHED_CHILD_STATUS + FAR struct child_status_s *child; +#endif _TCB *ptcb; _TCB *chtcb; _TCB *otcb; @@ -127,12 +130,30 @@ int task_reparent(pid_t ppid, pid_t chpid) /* Then reparent the child */ + chtcb->parent = ppid; /* The task specified by ppid is the new parent */ + +#ifdef CONFIG_SCHED_CHILD_STATUS + /* Remove the child status entry from old parent TCB */ + + child = task_removechild(otcb, chpid); + if (child) + { + /* Add the child status entry to the new parent TCB */ + + task_addchild(ptcb, child); + ret = OK; + } + else + { + ret = -ENOENT; + } +#else DEBUGASSERT(otcb->nchildren > 0); - chtcb->parent = ppid; /* The task specified by ppid is the new parent */ otcb->nchildren--; /* The orignal parent now has one few children */ ptcb->nchildren++; /* The new parent has one additional child */ ret = OK; +#endif errout_with_ints: irqrestore(flags); diff --git a/nuttx/sched/task_setup.c b/nuttx/sched/task_setup.c index 92897f0ae..80aefded3 100644 --- a/nuttx/sched/task_setup.c +++ b/nuttx/sched/task_setup.c @@ -153,7 +153,8 @@ static int task_assignpid(FAR _TCB *tcb) * Save the task ID of the parent task in the child task's TCB. * * Parameters: - * tcb - The TCB of the new, child task. + * tcb - The TCB of the new, child task. + * ttype - Type of the new thread: task, pthread, or kernel thread * * Returned Value: * None @@ -165,13 +166,57 @@ static int task_assignpid(FAR _TCB *tcb) ****************************************************************************/ #ifdef CONFIG_SCHED_HAVE_PARENT -static inline void task_saveparent(FAR _TCB *tcb) +static inline void task_saveparent(FAR _TCB *tcb, uint8_t ttype) { FAR _TCB *rtcb = (FAR _TCB*)g_readytorun.head; - DEBUGASSERT(rtcb->nchildren < UINT16_MAX); + /* Save the parent task's ID in the child task's TCB. I am not sure if + * this makes sense for the case of pthreads or not, but I don't think it + * is harmful in any event. + */ + tcb->parent = rtcb->pid; - rtcb->nchildren++; + + /* Exit status only needs to be retained for the case of tasks, however */ + + if (ttype == TCB_FLAG_TTYPE_TASK) + { +#ifdef CONFIG_SCHED_CHILD_STATUS + FAR struct child_status_s *child; + + /* Make sure that there is not already a structure for this PID in the + * parent TCB. There should not be. + */ + + child = task_findchild(rtcb, tcb->pid); + DEBUGASSERT(!child); + if (!child) + { + /* Allocate a new status structure */ + + child = task_allocchild(); + } + + /* Did we successfully find/allocate the child status structure? */ + + DEBUGASSERT(child); + if (child) + { + /* Yes.. Initialize the structure */ + + child->ch_flags = ttype; + child->ch_pid = tcb->pid; + child->ch_status = 0; + + /* Add the entry into the TCB list of children */ + + task_addchild(rtcb, child); + } +#else + DEBUGASSERT(rtcb->nchildren < UINT16_MAX); + rtcb->nchildren++; +#endif + } } #else # define task_saveparent(tcb) @@ -235,7 +280,7 @@ static inline void task_dupdspace(FAR _TCB *tcb) * priority - Priority of the new task * entry - Entry point of a new task * main - Application start point of the new task - * type - Type of the new thread: task, pthread, or kernel thread + * ttype - Type of the new thread: task, pthread, or kernel thread * * Return Value: * OK on success; ERROR on failure. @@ -245,7 +290,8 @@ static inline void task_dupdspace(FAR _TCB *tcb) * ****************************************************************************/ -int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main) +int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main, + uint8_t ttype) { int ret; @@ -264,9 +310,17 @@ int task_schedsetup(FAR _TCB *tcb, int priority, start_t start, main_t main) tcb->start = start; tcb->entry.main = main; + /* Save the thrad type. This setting will be needed in + * up_initial_state() is called. + */ + + ttype &= TCB_FLAG_TTYPE_MASK; + tcb->flags &= ~TCB_FLAG_TTYPE_MASK; + tcb->flags |= ttype; + /* Save the task ID of the parent task in the TCB */ - task_saveparent(tcb); + task_saveparent(tcb, ttype); /* exec(), pthread_create(), task_create(), and vfork() all * inherit the signal mask of the parent thread. diff --git a/nuttx/sched/task_vfork.c b/nuttx/sched/task_vfork.c index 46b2d8e9f..fece4c596 100644 --- a/nuttx/sched/task_vfork.c +++ b/nuttx/sched/task_vfork.c @@ -136,12 +136,6 @@ FAR _TCB *task_vforksetup(start_t retaddr) (void)env_dup(child); - /* Mark the type of this thread (this setting will be needed in - * task_schedsetup() when up_initial_state() is called. - */ - - child->flags |= TCB_FLAG_TTYPE_TASK; - /* Get the priority of the parent task */ #ifdef CONFIG_PRIORITY_INHERITANCE @@ -153,7 +147,8 @@ FAR _TCB *task_vforksetup(start_t retaddr) /* Initialize the task control block. This calls up_initial_state() */ svdbg("Child priority=%d start=%p\n", priority, retaddr); - ret = task_schedsetup(child, priority, retaddr, parent->entry.main); + ret = task_schedsetup(child, priority, retaddr, parent->entry.main, + TCB_FLAG_TTYPE_TASK); if (ret != OK) { goto errout_with_tcb; -- cgit v1.2.3 From 63f8c0a954ef61ee416e78ea55899bc322aa313b Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 23 Jan 2013 23:11:13 +0000 Subject: Add option to used keyboard CODEC in apps/examples/keypadtest git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5554 42af7a65-404d-4744-a932-0658087f49c3 --- apps/examples/keypadtest/Kconfig | 8 ++ apps/examples/keypadtest/keypadtest_main.c | 115 ++++++++++++++++++++++++++- nuttx/ChangeLog | 2 + nuttx/TODO | 121 +++++++++++++++++++---------- nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 7 +- 5 files changed, 207 insertions(+), 46 deletions(-) diff --git a/apps/examples/keypadtest/Kconfig b/apps/examples/keypadtest/Kconfig index 9dee80633..98c6d348e 100644 --- a/apps/examples/keypadtest/Kconfig +++ b/apps/examples/keypadtest/Kconfig @@ -18,4 +18,12 @@ if EXAMPLES_KEYPADTEST The name of the keypad device that will be opened in order to perform the keypad test. Default: "/dev/keypad" +config EXAMPLES_KEYPADTEST_ENCODED + bool "Use Keyboard CODEC" + default n + ---help--- + Use the keyboard encoded/decoder to pass control information from + the keypad driver to the keypad test. This is the keyboard CODEC + defined in nuttx/input/kbd_codec.h. + endif diff --git a/apps/examples/keypadtest/keypadtest_main.c b/apps/examples/keypadtest/keypadtest_main.c index afdc3e08a..dd7369c3e 100644 --- a/apps/examples/keypadtest/keypadtest_main.c +++ b/apps/examples/keypadtest/keypadtest_main.c @@ -50,6 +50,11 @@ #include +#ifdef CONFIG_EXAMPLES_KEYPADTEST_ENCODED +# include +# include +#endif + /**************************************************************************** * Definitions ****************************************************************************/ @@ -67,6 +72,15 @@ * Private Types ****************************************************************************/ +#ifdef CONFIG_EXAMPLES_KEYPADTEST_ENCODED +struct keypad_instream_s +{ + struct lib_instream_s stream; + FAR char *buffer; + ssize_t nbytes; +}; +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -75,6 +89,102 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: keypad_getstream + * + * Description: + * Get one character from the keyboard. + * + ****************************************************************************/ + +#ifdef CONFIG_EXAMPLES_KEYPADTEST_ENCODED +static int keypad_getstream(FAR struct lib_instream_s *this) +{ + FAR struct keypad_instream_s *kbdstream = (FAR struct keypad_instream_s *)this; + + DEBUGASSERT(kbdstream && kbdstream->buffer); + if (kbdstream->nbytes > 0) + { + kbdstream->nbytes--; + kbdstream->stream.nget++; + return (int)*kbdstream->buffer++; + } + + return EOF; +} +#endif + +/**************************************************************************** + * Name: keypad_decode + * + * Description: + * Decode encoded keyboard input + * + ****************************************************************************/ + +#ifdef CONFIG_EXAMPLES_KEYPADTEST_ENCODED +static void keypad_decode(FAR char *buffer, ssize_t nbytes) +{ + struct keypad_instream_s kbdstream; + struct kbd_getstate_s state; + uint8_t ch; + int ret; + + /* Initialize */ + + memset(&state, 0, sizeof(struct kbd_getstate_s)); + kbdstream.stream.get = keypad_getstream; + kbdstream.stream.nget = 0; + kbdstream.buffer = buffer; + kbdstream.nbytes = nbytes; + + /* Loop until all of the bytes have been consumed. We implicitly assume + * that the the escaped sequences do not cross buffer boundaries. That + * might be true if the read buffer were small or the data rates high. + */ + + for (;;) + { + /* Decode the next thing from the buffer */ + + ret = kbd_decode((FAR struct lib_instream_s *)&kbdstream, &state, &ch); + if (ret == KBD_ERROR) + { + break; + } + + /* Normal data? Or special key? */ + + switch (ret) + { + case KBD_PRESS: /* Key press event */ + printf("Normal Press: %c [%02x]\n", isprint(ch) ? ch : '.', ch); + break; + + case KBD_RELEASE: /* Key release event */ + printf("Normal Release: %c [%02x]\n", isprint(ch) ? ch : '.', ch); + break; + + case KBD_SPECPRESS: /* Special key press event */ + printf("Special Press: %d\n", ch); + break; + + case KBD_SPECREL: /* Special key release event */ + printf("Special Release: %d\n", ch); + break; + + case KBD_ERROR: /* Error or end-of-file */ + printf("EOF: %d\n", ret); + break; + + default: + printf("Unexpected: %d\n", ret); + break; + } + } +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -125,8 +235,11 @@ int keypadtest_main(int argc, char *argv[]) if (nbytes > 0) { /* On success, echo the buffer to stdout */ - +#ifdef CONFIG_EXAMPLES_KEYPADTEST_ENCODED + keypad_decode(buffer, nbytes); +#else (void)write(1, buffer, nbytes); +#endif } } while (nbytes >= 0); diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 38b1b6b1f..99f6d4a52 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4016,4 +4016,6 @@ the child task exists. This is behavior required by POSIX. But in NuttX is only enabled with CONFIG_SCHED_HAVE_PARENT and CONFIG_SCHED_CHILD_STATUS + * Add support for keyboard encode to the keypad test (from + Denis Carikli). diff --git a/nuttx/TODO b/nuttx/TODO index 94c3dba0d..c302760ab 100644 --- a/nuttx/TODO +++ b/nuttx/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated January 14, 2013) +NuttX TODO List (Last updated January 23, 2013) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -38,14 +38,14 @@ nuttx/ (3) MIPS/PIC32 (arch/mips) (1) Hitachi/Renesas SH-1 (arch/sh/src/sh1) (4) Renesas M16C/26 (arch/sh/src/m16c) - (10) z80/z8/ez80 (arch/z80/) + (11) z80/z8/ez80/z180 (arch/z80/) (9) z16 (arch/z16/) (1) mc68hc1x (arch/hc) apps/ (5) Network Utilities (apps/netutils/) - (4) NuttShell (NSH) (apps/nshlib) + (5) NuttShell (NSH) (apps/nshlib) (1) System libraries apps/system (apps/system) (5) Other Applications & Tests (apps/examples/) @@ -161,37 +161,6 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium Low for now - Title: RETAINING TASK EXIT STATUS - Description: When a task exists, its exit status should be retained in - so data structure until it is reaped (via waitpid(), or - similar interface) or until the parent thread exists. - - You would think that this should be a clone of the existing - pthread join logic. Howver there is no need for zombies - in NuttX so no need to keep the status if the parent has - already exit'ed. Other simplifications: - - 1. Keep the array/list of return status in the parent - tasks TCB. - 2. Use a fixed size array of return status (perhaps the - the enire array is allocated so that that is con - penalty for tasks that have no childre. - - At present, exit status is not retained. If waitpid() - is called after the child task has exit'ed it simpley - returns with the ECHLD error. That is not too bad, but - does not tell you what the exit status was. - - A work-around is to: - 1) Call sched_lock() to disable pre-emption. - 2) Start the task (it cannot run because pre-emption is - disbled. - 3) Call waitpid(); - 4) Call sched_unlock() to re-enable pre-emption. - - Status: Open - Priority: Low - Title: IMPROVED TASK CONTROL BLOCK STRUCTURE Description: All task resources that are shared amongst threads have their own "break-away", reference-counted structure. The @@ -226,6 +195,23 @@ o Task/Scheduler (sched/) important interfaces. For the average user, these functions are just fine the way they are. + Title: execv() AND vfork() + Description: There is a problem when vfork() calls execv() (or execl()) to + start a new appliction: When the parent thread calls vfork() + it receives and gets the pid of the vforked task, and *not* + the pid of the desired execv'ed application. + + The same tasking arrangement is used by the standard function + posix_spawn(). However, posix_spawn uses the non-standard, internal + NuttX interface task_reparent() to replace the childs parent task + with the caller of posix_spawn(). That cannot be done with vfork() + because we don't know what vfor() is going to do. + + Any solution to this is either very difficult or impossible with + an MMU. + Status: Open + Priority: Low (it might as well be low since it isn't going to be fixed). + o Memory Managment (mm/) ^^^^^^^^^^^^^^^^^^^^^^ @@ -531,7 +517,7 @@ o Network (net/, drivers/net) Status: Open. No changes are planned. Priority: Low - Tile: MULTIPLE NETWORK INTERFACE SUPPORT + Title: MULTIPLE NETWORK INTERFACE SUPPORT Description: uIP polling issues / Multiple network interface support: (1) Current logic will not support multiple ethernet drivers. @@ -681,6 +667,21 @@ o Network (net/, drivers/net) Status: Open Priority: Low... fix defconfig files as necessary. + Title: net_poll() DOES NOT HANDLE LOSS-OF-CONNECTION CORRECTLY + Description: When a loss of connection is detected by any logic waiting on the + networking events, the function net_lostconnection() must be called. + That function just sets some bits in the socket structure so that + it remembers that the connection is lost. + + That is currently done in recvfrom(), send(), and net_monitor.c. But + it is not done in the net_poll() logic; that logic correctly sets + the POLLHUP status, but it does not call net_lostconnection(). As a + result, if recv() is called after the poll() or select(), the system + will hang because the recv() does not know that the connection has + been lost. + Status: Open + Priority: High + o USB (drivers/usbdev, drivers/usbhost) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1074,13 +1075,13 @@ o Build system Priority: Low -- the kernel build configuration is not fully fielded yet. - Title: mconf NOT AVAILABLE IN NATIVE WINDOWS BUILD - Description: NuttX is migrating to the use of the kconfig-frontends mconf + Title: kconfig-mconf NOT AVAILABLE IN NATIVE WINDOWS BUILD + Description: NuttX is migrating to the use of the kconfig-frontends kconfig-mconf tool for all configurations. In NuttX 6.24, support for native - Windows builds was added. However, the mconf tool does not + Windows builds was added. However, thekconfig- mconf tool does not build to run natively under Windows. - Some effort was spent trying to get a clean mconf build under + Some effort was spent trying to get a clean kconfig-mconf build under Windows. This is documented in the message thread beginning here: http://tech.groups.yahoo.com/group/nuttx/message/2900. The build was successfully completed using: MinGW-GCC, MSYS, @@ -1092,8 +1093,8 @@ o Build system was considered a show stopper and the changs were not checked in. - Options: (1) Use conf (not mconf). confis the text-only - configuration tool, (2) fix mconf, (3) write another variant + Options: (1) Use kconfigs-conf (not kconfig-mconf). confis the text-only + configuration tool, (2) fix kconfig-mconf, (3) write another variant of the configuration tool for windows, or (4) do all configuration under Cygwin or MSYS. I am doing (4) now, but this is very awkward because I have to set the apps path to ../apps (vs @@ -1763,8 +1764,8 @@ o Renesas M16C/26 (arch/sh/src/m16c) Status: Open Priority: Medium -o z80/z8/ez80 (arch/z80) - ^^^^^^^^^^^^^^^^^^^^^^^ +o z80/z8/ez80/z180 (arch/z80) + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Title: SDCC INTEGER OVERFLOWS Description: The SDCC version the same problems with integer overflow during @@ -1854,6 +1855,14 @@ o z80/z8/ez80 (arch/z80) Status: Open Priority: Med + Title: UNFINISHED Z180 LOGIC NEEDED BY THE P112 BOARD + Description: 1) Need to revist the start-up logic. Looking at the P112 Bios + (Bios.mcd), I see that quite of bit of register setup is done + there. + 2) Finish ESCC driver logic. + Status: Open + Priority: Low (at least until I get P112 hardware) + o z16 (arch/z16) ^^^^^^^^^^^^^^^^ @@ -2045,6 +2054,32 @@ o NuttShell (NSH) (apps/nshlib) Status: Open Priority: Low (enhancement) + Title: RE-DIRECTION OF BUILTIN APPLICATONS + Description: There is a problem with the re-direction of output form built-in + applications in NSH. When output is re-directed, exec_builtin() + spawns a tiny trampoline task that re-directs the output as + requested, starts the built-in task and then exit. + + The problem is that when exec_builtin() starts the trampoline task, + it receives and returns the pid of the trampoline task, and *not* + the pid of the desired builtin application. This bad pid is returned + to NSH and when NSH tries to use that pid in the waitpid() call, it + fails because the trampoline task no longer exists. + + The same tasking arrangement is used by the standard function + posix_spawn(). However, posix_spawn uses the non-standard, internal + NuttX interface task_reparent() to replace the childs parent task + with the caller of posix_spawn(). + + exec_builtin() should not use this internal interface, however, + since it resides in the application space. The suggested solution + is (1) move the exec_builtin() logic into nuttx/sched, (2) make it + a semi-standard interface renamed to task_spawn() and prototyped + in nuttx/include/sched.h, and then (2) use task_reparent to solve + the parental problem in the same way that posix_spawn does. + Status: Open + Priority: Medium + o System libraries apps/system (apps/system) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index aa0e4cf09..6f49b3e38 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -386,9 +386,12 @@ void up_irqinitialize(void) lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS); - /* If a debugger is connected, try to prevent it from catching hardfaults */ + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ -#ifdef CONFIG_DEBUG +#if defined(CONFIG_DEBUG) && !defined(CONFIG_ARMV7M_USEBASEPRI) regval = getreg32(NVIC_DEMCR); regval &= ~NVIC_DEMCR_VCHARDERR; putreg32(regval, NVIC_DEMCR); -- cgit v1.2.3 From 379ed0a0922362a1bb92d03a661684a87824454d Mon Sep 17 00:00:00 2001 From: px4dev Date: Thu, 24 Jan 2013 00:22:01 -0800 Subject: Trivial compile fix. --- nuttx/sched/task_setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nuttx/sched/task_setup.c b/nuttx/sched/task_setup.c index 80aefded3..43ed24b32 100644 --- a/nuttx/sched/task_setup.c +++ b/nuttx/sched/task_setup.c @@ -219,7 +219,7 @@ static inline void task_saveparent(FAR _TCB *tcb, uint8_t ttype) } } #else -# define task_saveparent(tcb) +# define task_saveparent(tcb, type) #endif /**************************************************************************** -- cgit v1.2.3